Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 2 0 2 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 8 0 8 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 121393 1 T2 100 T3 139 T25 376
all_pins[1] 121393 1 T2 100 T3 139 T25 376



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 231381 1 T2 173 T3 278 T25 752
values[0x1] 11405 1 T2 27 T5 21 T26 34
transitions[0x0=>0x1] 10509 1 T2 22 T5 17 T26 33
transitions[0x1=>0x0] 10519 1 T2 22 T5 17 T26 33



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 111984 1 T2 82 T3 139 T25 376
all_pins[0] values[0x1] 9409 1 T2 18 T5 12 T26 29
all_pins[0] transitions[0x0=>0x1] 8910 1 T2 16 T5 10 T26 29
all_pins[0] transitions[0x1=>0x0] 1497 1 T2 7 T5 7 T26 5
all_pins[1] values[0x0] 119397 1 T2 91 T3 139 T25 376
all_pins[1] values[0x1] 1996 1 T2 9 T5 9 T26 5
all_pins[1] transitions[0x0=>0x1] 1599 1 T2 6 T5 7 T26 4
all_pins[1] transitions[0x1=>0x0] 9022 1 T2 15 T5 10 T26 28

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