Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

8626

1

T2

35

T5

29

T26

15

all_values[1]

8626

1

T2

35

T5

29

T26

15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9005

1

T2

40

T5

24

T26

13

auto[1]

8247

1

T2

30

T5

34

T26

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6701

1

T2

18

T5

26

T26

8

auto[1]

10551

1

T2

52

T5

32

T26

22

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10157

1

T2

39

T5

36

T26

16

auto[1]

7095

1

T2

31

T5

22

T26

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	0	12	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

1742

1

T2

1

T5

8

T26

2

all_values[0]

auto[0]

auto[0]

auto[1]

899

1

T2

6

T5

3

T26

1

all_values[0]

auto[0]

auto[1]

auto[0]

1629

1

T2

8

T5

6

T26

3

all_values[0]

auto[0]

auto[1]

auto[1]

829

1

T2

4

T5

1

T26

2

all_values[0]

auto[1]

auto[0]

auto[1]

1931

1

T2

9

T5

5

T26

4

all_values[0]

auto[1]

auto[1]

auto[1]

1596

1

T2

7

T5

6

T26

3

all_values[1]

auto[0]

auto[0]

auto[0]

1697

1

T2

8

T5

4

T41

17

all_values[1]

auto[0]

auto[0]

auto[1]

874

1

T2

6

T5

1

T26

3

all_values[1]

auto[0]

auto[1]

auto[0]

1633

1

T2

1

T5

8

T26

3

all_values[1]

auto[0]

auto[1]

auto[1]

854

1

T2

5

T5

5

T26

2

all_values[1]

auto[1]

auto[0]

auto[1]

1862

1

T2

10

T5

3

T26

3

all_values[1]

auto[1]

auto[1]

auto[1]

1706

1

T2

5

T5

8

T26

4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal