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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.56 98.25 93.91 97.07 91.28 96.37 99.77 92.28


Total test records in report: 1129
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T1021 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3942185250 Jul 24 05:53:35 PM PDT 24 Jul 24 05:53:36 PM PDT 24 13884997 ps
T1022 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1144015888 Jul 24 05:53:47 PM PDT 24 Jul 24 05:53:48 PM PDT 24 58311499 ps
T255 /workspace/coverage/cover_reg_top/10.edn_csr_rw.649082531 Jul 24 05:53:34 PM PDT 24 Jul 24 05:53:35 PM PDT 24 16283290 ps
T277 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2776010452 Jul 24 05:53:33 PM PDT 24 Jul 24 05:53:35 PM PDT 24 155582856 ps
T1023 /workspace/coverage/cover_reg_top/16.edn_csr_rw.4267579068 Jul 24 05:53:44 PM PDT 24 Jul 24 05:53:45 PM PDT 24 69794620 ps
T1024 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.714702050 Jul 24 05:53:18 PM PDT 24 Jul 24 05:53:22 PM PDT 24 541310580 ps
T1025 /workspace/coverage/cover_reg_top/32.edn_intr_test.2313612309 Jul 24 05:53:52 PM PDT 24 Jul 24 05:53:53 PM PDT 24 50708481 ps
T1026 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2088319415 Jul 24 05:53:45 PM PDT 24 Jul 24 05:53:49 PM PDT 24 107335682 ps
T284 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.342827072 Jul 24 05:53:31 PM PDT 24 Jul 24 05:53:36 PM PDT 24 232145230 ps
T1027 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1024731921 Jul 24 05:53:33 PM PDT 24 Jul 24 05:53:34 PM PDT 24 152656870 ps
T267 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3191801609 Jul 24 05:53:45 PM PDT 24 Jul 24 05:53:47 PM PDT 24 37140172 ps
T1028 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1671893344 Jul 24 05:53:43 PM PDT 24 Jul 24 05:53:46 PM PDT 24 76536866 ps
T256 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2991148053 Jul 24 05:53:48 PM PDT 24 Jul 24 05:53:49 PM PDT 24 33936253 ps
T1029 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3222435606 Jul 24 05:53:49 PM PDT 24 Jul 24 05:53:52 PM PDT 24 74132121 ps
T268 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3714658586 Jul 24 05:53:38 PM PDT 24 Jul 24 05:53:39 PM PDT 24 32835268 ps
T269 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1985060994 Jul 24 05:53:15 PM PDT 24 Jul 24 05:53:17 PM PDT 24 20689678 ps
T1030 /workspace/coverage/cover_reg_top/43.edn_intr_test.3232641631 Jul 24 05:53:55 PM PDT 24 Jul 24 05:53:56 PM PDT 24 14843338 ps
T1031 /workspace/coverage/cover_reg_top/26.edn_intr_test.2405212599 Jul 24 05:53:50 PM PDT 24 Jul 24 05:53:51 PM PDT 24 16685614 ps
T1032 /workspace/coverage/cover_reg_top/28.edn_intr_test.2838426431 Jul 24 05:53:48 PM PDT 24 Jul 24 05:53:50 PM PDT 24 43599781 ps
T285 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.704891481 Jul 24 05:53:35 PM PDT 24 Jul 24 05:53:38 PM PDT 24 554307435 ps
T1033 /workspace/coverage/cover_reg_top/41.edn_intr_test.4293070466 Jul 24 05:53:50 PM PDT 24 Jul 24 05:53:51 PM PDT 24 58281388 ps
T1034 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2872707199 Jul 24 05:53:19 PM PDT 24 Jul 24 05:53:20 PM PDT 24 24337162 ps
T1035 /workspace/coverage/cover_reg_top/45.edn_intr_test.3907837297 Jul 24 05:53:52 PM PDT 24 Jul 24 05:53:53 PM PDT 24 18105676 ps
T1036 /workspace/coverage/cover_reg_top/16.edn_tl_errors.4125171347 Jul 24 05:53:42 PM PDT 24 Jul 24 05:53:45 PM PDT 24 35734406 ps
T270 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2014568617 Jul 24 05:53:29 PM PDT 24 Jul 24 05:53:30 PM PDT 24 97988054 ps
T1037 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2407960467 Jul 24 05:53:35 PM PDT 24 Jul 24 05:53:36 PM PDT 24 87774649 ps
T1038 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2091128603 Jul 24 05:53:23 PM PDT 24 Jul 24 05:53:25 PM PDT 24 109549857 ps
T271 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1514229721 Jul 24 05:53:45 PM PDT 24 Jul 24 05:53:47 PM PDT 24 20507520 ps
T1039 /workspace/coverage/cover_reg_top/48.edn_intr_test.4055289949 Jul 24 05:53:48 PM PDT 24 Jul 24 05:53:49 PM PDT 24 119568868 ps
T272 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.492716053 Jul 24 05:53:34 PM PDT 24 Jul 24 05:53:35 PM PDT 24 56672306 ps
T1040 /workspace/coverage/cover_reg_top/40.edn_intr_test.1136893994 Jul 24 05:53:48 PM PDT 24 Jul 24 05:53:49 PM PDT 24 15801239 ps
T1041 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3270977474 Jul 24 05:53:42 PM PDT 24 Jul 24 05:53:44 PM PDT 24 68725978 ps
T1042 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3270327289 Jul 24 05:53:21 PM PDT 24 Jul 24 05:53:23 PM PDT 24 630776993 ps
T1043 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3640290368 Jul 24 05:53:46 PM PDT 24 Jul 24 05:53:48 PM PDT 24 105038607 ps
T1044 /workspace/coverage/cover_reg_top/25.edn_intr_test.2028934288 Jul 24 05:53:45 PM PDT 24 Jul 24 05:53:47 PM PDT 24 14570345 ps
T1045 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3140284416 Jul 24 05:53:28 PM PDT 24 Jul 24 05:53:30 PM PDT 24 28946492 ps
T257 /workspace/coverage/cover_reg_top/2.edn_csr_rw.371218742 Jul 24 05:53:22 PM PDT 24 Jul 24 05:53:23 PM PDT 24 15663229 ps
T1046 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2300132050 Jul 24 05:53:21 PM PDT 24 Jul 24 05:53:23 PM PDT 24 45309581 ps
T1047 /workspace/coverage/cover_reg_top/7.edn_intr_test.17410268 Jul 24 05:53:35 PM PDT 24 Jul 24 05:53:36 PM PDT 24 19028117 ps
T258 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3535115363 Jul 24 05:53:32 PM PDT 24 Jul 24 05:53:33 PM PDT 24 23562084 ps
T1048 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.653545425 Jul 24 05:53:33 PM PDT 24 Jul 24 05:53:35 PM PDT 24 34024794 ps
T1049 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1468322423 Jul 24 05:53:41 PM PDT 24 Jul 24 05:53:42 PM PDT 24 30570704 ps
T259 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2780106599 Jul 24 05:53:33 PM PDT 24 Jul 24 05:53:34 PM PDT 24 146636097 ps
T1050 /workspace/coverage/cover_reg_top/4.edn_intr_test.2076305074 Jul 24 05:53:27 PM PDT 24 Jul 24 05:53:28 PM PDT 24 16570326 ps
T1051 /workspace/coverage/cover_reg_top/17.edn_intr_test.4018030349 Jul 24 05:53:40 PM PDT 24 Jul 24 05:53:41 PM PDT 24 11701744 ps
T1052 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2218404456 Jul 24 05:53:20 PM PDT 24 Jul 24 05:53:22 PM PDT 24 50894234 ps
T1053 /workspace/coverage/cover_reg_top/15.edn_intr_test.2976010901 Jul 24 05:53:48 PM PDT 24 Jul 24 05:53:49 PM PDT 24 14916886 ps
T1054 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3233081582 Jul 24 05:53:34 PM PDT 24 Jul 24 05:53:35 PM PDT 24 34967401 ps
T1055 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3465122812 Jul 24 05:53:22 PM PDT 24 Jul 24 05:53:25 PM PDT 24 31664729 ps
T1056 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1224884920 Jul 24 05:53:39 PM PDT 24 Jul 24 05:53:41 PM PDT 24 73487083 ps
T1057 /workspace/coverage/cover_reg_top/9.edn_tl_errors.887963576 Jul 24 05:53:29 PM PDT 24 Jul 24 05:53:31 PM PDT 24 26005287 ps
T1058 /workspace/coverage/cover_reg_top/34.edn_intr_test.1485896249 Jul 24 05:53:48 PM PDT 24 Jul 24 05:53:50 PM PDT 24 14480456 ps
T1059 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1977373139 Jul 24 05:53:26 PM PDT 24 Jul 24 05:53:27 PM PDT 24 88309575 ps
T1060 /workspace/coverage/cover_reg_top/36.edn_intr_test.3873910055 Jul 24 05:53:50 PM PDT 24 Jul 24 05:53:51 PM PDT 24 15117952 ps
T1061 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1891113522 Jul 24 05:53:32 PM PDT 24 Jul 24 05:53:34 PM PDT 24 100357298 ps
T1062 /workspace/coverage/cover_reg_top/11.edn_intr_test.902745865 Jul 24 05:53:34 PM PDT 24 Jul 24 05:53:36 PM PDT 24 14520464 ps
T1063 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.426744455 Jul 24 05:53:43 PM PDT 24 Jul 24 05:53:46 PM PDT 24 349143812 ps
T1064 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.844494676 Jul 24 05:53:31 PM PDT 24 Jul 24 05:53:32 PM PDT 24 35021812 ps
T1065 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3885133627 Jul 24 05:53:18 PM PDT 24 Jul 24 05:53:20 PM PDT 24 56196562 ps
T1066 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1602553020 Jul 24 05:53:45 PM PDT 24 Jul 24 05:53:47 PM PDT 24 34556573 ps
T1067 /workspace/coverage/cover_reg_top/9.edn_intr_test.2206869712 Jul 24 05:53:34 PM PDT 24 Jul 24 05:53:35 PM PDT 24 18567737 ps
T1068 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3749046714 Jul 24 05:53:31 PM PDT 24 Jul 24 05:53:33 PM PDT 24 21785346 ps
T1069 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.750208959 Jul 24 05:53:22 PM PDT 24 Jul 24 05:53:24 PM PDT 24 365121308 ps
T1070 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2564291655 Jul 24 05:53:44 PM PDT 24 Jul 24 05:53:45 PM PDT 24 31682766 ps
T1071 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1834868973 Jul 24 05:53:17 PM PDT 24 Jul 24 05:53:18 PM PDT 24 159008089 ps
T1072 /workspace/coverage/cover_reg_top/33.edn_intr_test.4075317418 Jul 24 05:53:50 PM PDT 24 Jul 24 05:53:51 PM PDT 24 10693001 ps
T1073 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2185484722 Jul 24 05:53:28 PM PDT 24 Jul 24 05:53:29 PM PDT 24 15148093 ps
T1074 /workspace/coverage/cover_reg_top/31.edn_intr_test.1868962312 Jul 24 05:53:51 PM PDT 24 Jul 24 05:53:52 PM PDT 24 19329265 ps
T1075 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3568332036 Jul 24 05:53:33 PM PDT 24 Jul 24 05:53:35 PM PDT 24 103950396 ps
T1076 /workspace/coverage/cover_reg_top/29.edn_intr_test.2076942749 Jul 24 05:53:50 PM PDT 24 Jul 24 05:53:51 PM PDT 24 14231375 ps
T1077 /workspace/coverage/cover_reg_top/14.edn_intr_test.2814195549 Jul 24 05:53:45 PM PDT 24 Jul 24 05:53:46 PM PDT 24 34446085 ps
T1078 /workspace/coverage/cover_reg_top/14.edn_tl_errors.4177082389 Jul 24 05:53:38 PM PDT 24 Jul 24 05:53:40 PM PDT 24 224284362 ps
T1079 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2336605999 Jul 24 05:53:37 PM PDT 24 Jul 24 05:53:38 PM PDT 24 131680348 ps
T1080 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.667813515 Jul 24 05:53:48 PM PDT 24 Jul 24 05:53:50 PM PDT 24 32382902 ps
T1081 /workspace/coverage/cover_reg_top/21.edn_intr_test.2461906272 Jul 24 05:53:45 PM PDT 24 Jul 24 05:53:47 PM PDT 24 70052271 ps
T1082 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2086642056 Jul 24 05:53:36 PM PDT 24 Jul 24 05:53:37 PM PDT 24 18529955 ps
T1083 /workspace/coverage/cover_reg_top/20.edn_intr_test.3471443595 Jul 24 05:53:47 PM PDT 24 Jul 24 05:53:48 PM PDT 24 14143931 ps
T1084 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4211102816 Jul 24 05:53:47 PM PDT 24 Jul 24 05:53:49 PM PDT 24 166920502 ps
T1085 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1222494257 Jul 24 05:53:34 PM PDT 24 Jul 24 05:53:40 PM PDT 24 302594429 ps
T1086 /workspace/coverage/cover_reg_top/37.edn_intr_test.227540152 Jul 24 05:53:48 PM PDT 24 Jul 24 05:53:49 PM PDT 24 31746473 ps
T286 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2455522307 Jul 24 05:53:42 PM PDT 24 Jul 24 05:53:46 PM PDT 24 130451962 ps
T1087 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2196882091 Jul 24 05:53:47 PM PDT 24 Jul 24 05:53:48 PM PDT 24 17825916 ps
T1088 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1936934186 Jul 24 05:53:48 PM PDT 24 Jul 24 05:53:50 PM PDT 24 177673190 ps
T1089 /workspace/coverage/cover_reg_top/18.edn_intr_test.389686554 Jul 24 05:53:48 PM PDT 24 Jul 24 05:53:49 PM PDT 24 19269587 ps
T1090 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1904542170 Jul 24 05:53:48 PM PDT 24 Jul 24 05:53:50 PM PDT 24 46728972 ps
T1091 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2399088395 Jul 24 05:53:46 PM PDT 24 Jul 24 05:53:47 PM PDT 24 24784053 ps
T1092 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4232618976 Jul 24 05:53:45 PM PDT 24 Jul 24 05:53:46 PM PDT 24 20162030 ps
T1093 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3817149039 Jul 24 05:53:29 PM PDT 24 Jul 24 05:53:32 PM PDT 24 281674095 ps
T260 /workspace/coverage/cover_reg_top/17.edn_csr_rw.248889311 Jul 24 05:53:47 PM PDT 24 Jul 24 05:53:48 PM PDT 24 31312133 ps
T263 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1868932794 Jul 24 05:53:22 PM PDT 24 Jul 24 05:53:24 PM PDT 24 90271054 ps
T262 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1301176728 Jul 24 05:53:32 PM PDT 24 Jul 24 05:53:33 PM PDT 24 31839984 ps
T1094 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.924427057 Jul 24 05:53:33 PM PDT 24 Jul 24 05:53:34 PM PDT 24 22472934 ps
T1095 /workspace/coverage/cover_reg_top/6.edn_intr_test.1258016246 Jul 24 05:53:29 PM PDT 24 Jul 24 05:53:30 PM PDT 24 42352417 ps
T1096 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2800718372 Jul 24 05:53:42 PM PDT 24 Jul 24 05:53:43 PM PDT 24 95302442 ps
T1097 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1516602949 Jul 24 05:53:35 PM PDT 24 Jul 24 05:53:38 PM PDT 24 131571005 ps
T1098 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.4147791493 Jul 24 05:53:16 PM PDT 24 Jul 24 05:53:23 PM PDT 24 23336854 ps
T1099 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1022538936 Jul 24 05:53:32 PM PDT 24 Jul 24 05:53:33 PM PDT 24 29693600 ps
T1100 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1098818197 Jul 24 05:53:48 PM PDT 24 Jul 24 05:53:50 PM PDT 24 23991890 ps
T287 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1660676002 Jul 24 05:53:35 PM PDT 24 Jul 24 05:53:37 PM PDT 24 85050244 ps
T1101 /workspace/coverage/cover_reg_top/2.edn_intr_test.2080063170 Jul 24 05:53:26 PM PDT 24 Jul 24 05:53:27 PM PDT 24 11930145 ps
T1102 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1979421892 Jul 24 05:53:27 PM PDT 24 Jul 24 05:53:29 PM PDT 24 251056114 ps
T1103 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3174910008 Jul 24 05:53:27 PM PDT 24 Jul 24 05:53:29 PM PDT 24 52871483 ps
T1104 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.430478240 Jul 24 05:53:35 PM PDT 24 Jul 24 05:53:36 PM PDT 24 83474831 ps
T1105 /workspace/coverage/cover_reg_top/13.edn_intr_test.3048545383 Jul 24 05:53:40 PM PDT 24 Jul 24 05:53:41 PM PDT 24 13959204 ps
T1106 /workspace/coverage/cover_reg_top/24.edn_intr_test.2050370486 Jul 24 05:53:46 PM PDT 24 Jul 24 05:53:47 PM PDT 24 101366485 ps
T1107 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1083242435 Jul 24 05:53:44 PM PDT 24 Jul 24 05:53:46 PM PDT 24 38727250 ps
T1108 /workspace/coverage/cover_reg_top/42.edn_intr_test.3879677852 Jul 24 05:53:54 PM PDT 24 Jul 24 05:53:55 PM PDT 24 51062054 ps
T1109 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3819606588 Jul 24 05:53:49 PM PDT 24 Jul 24 05:53:51 PM PDT 24 173469134 ps
T1110 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1260374856 Jul 24 05:53:31 PM PDT 24 Jul 24 05:53:33 PM PDT 24 48451804 ps
T1111 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3352802528 Jul 24 05:53:49 PM PDT 24 Jul 24 05:53:51 PM PDT 24 59839047 ps
T1112 /workspace/coverage/cover_reg_top/44.edn_intr_test.1479475667 Jul 24 05:53:50 PM PDT 24 Jul 24 05:53:51 PM PDT 24 46970358 ps
T1113 /workspace/coverage/cover_reg_top/1.edn_intr_test.986569872 Jul 24 05:53:21 PM PDT 24 Jul 24 05:53:22 PM PDT 24 50694363 ps
T1114 /workspace/coverage/cover_reg_top/8.edn_intr_test.3151957210 Jul 24 05:53:28 PM PDT 24 Jul 24 05:53:29 PM PDT 24 16026632 ps
T1115 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2439933630 Jul 24 05:53:36 PM PDT 24 Jul 24 05:53:37 PM PDT 24 27618568 ps
T1116 /workspace/coverage/cover_reg_top/27.edn_intr_test.2683902853 Jul 24 05:53:49 PM PDT 24 Jul 24 05:53:50 PM PDT 24 45386303 ps
T1117 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1002222150 Jul 24 05:53:26 PM PDT 24 Jul 24 05:53:32 PM PDT 24 672843910 ps
T1118 /workspace/coverage/cover_reg_top/49.edn_intr_test.1912507934 Jul 24 05:53:48 PM PDT 24 Jul 24 05:53:49 PM PDT 24 15444675 ps
T1119 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1686605889 Jul 24 05:53:29 PM PDT 24 Jul 24 05:53:30 PM PDT 24 86828523 ps
T1120 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3558669770 Jul 24 05:53:31 PM PDT 24 Jul 24 05:53:32 PM PDT 24 17063438 ps
T1121 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2300143679 Jul 24 05:53:34 PM PDT 24 Jul 24 05:53:35 PM PDT 24 38684846 ps
T1122 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2735895730 Jul 24 05:53:21 PM PDT 24 Jul 24 05:53:22 PM PDT 24 34921553 ps
T1123 /workspace/coverage/cover_reg_top/6.edn_csr_rw.447286387 Jul 24 05:53:29 PM PDT 24 Jul 24 05:53:30 PM PDT 24 16214730 ps
T1124 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3476862130 Jul 24 05:53:34 PM PDT 24 Jul 24 05:53:35 PM PDT 24 112993090 ps
T1125 /workspace/coverage/cover_reg_top/0.edn_intr_test.1457844446 Jul 24 05:53:20 PM PDT 24 Jul 24 05:53:21 PM PDT 24 36102117 ps
T1126 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.965205855 Jul 24 05:53:22 PM PDT 24 Jul 24 05:53:23 PM PDT 24 127341797 ps
T1127 /workspace/coverage/cover_reg_top/23.edn_intr_test.63692016 Jul 24 05:53:44 PM PDT 24 Jul 24 05:53:45 PM PDT 24 14688621 ps
T1128 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3423922799 Jul 24 05:53:22 PM PDT 24 Jul 24 05:53:23 PM PDT 24 17799926 ps
T288 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.335327707 Jul 24 05:53:34 PM PDT 24 Jul 24 05:53:37 PM PDT 24 89930827 ps
T1129 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3391267388 Jul 24 05:53:21 PM PDT 24 Jul 24 05:53:22 PM PDT 24 44123827 ps

Test location /workspace/coverage/default/127.edn_genbits.2764662615
Short name T9
Test name
Test status
Simulation time 66035486 ps
CPU time 1.68 seconds
Started Jul 24 06:01:23 PM PDT 24
Finished Jul 24 06:01:24 PM PDT 24
Peak memory 218996 kb
Host smart-1f01e5a2-a6c1-48af-85b4-853b0d80924b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764662615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2764662615
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_stress_all.1407040064
Short name T5
Test name
Test status
Simulation time 1083693818 ps
CPU time 5.57 seconds
Started Jul 24 06:00:24 PM PDT 24
Finished Jul 24 06:00:30 PM PDT 24
Peak memory 217600 kb
Host smart-4f4d820f-461c-41e8-9953-c935ef8f6237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407040064 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1407040064
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3044564445
Short name T17
Test name
Test status
Simulation time 598586275 ps
CPU time 9.11 seconds
Started Jul 24 05:59:54 PM PDT 24
Finished Jul 24 06:00:03 PM PDT 24
Peak memory 236172 kb
Host smart-a07c16bc-2cf9-499e-b389-02aafafaeb9c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044564445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3044564445
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/105.edn_alert.2562210801
Short name T10
Test name
Test status
Simulation time 26944624 ps
CPU time 1.39 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 219556 kb
Host smart-e6e56d44-c7fc-4559-843a-d4d753b123b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562210801 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.2562210801
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.363776885
Short name T86
Test name
Test status
Simulation time 29683287607 ps
CPU time 673.92 seconds
Started Jul 24 06:00:42 PM PDT 24
Finished Jul 24 06:11:57 PM PDT 24
Peak memory 218540 kb
Host smart-ead00e5b-c074-4496-8bf4-c6da85145f0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363776885 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.363776885
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2207554447
Short name T18
Test name
Test status
Simulation time 2194098348 ps
CPU time 9.16 seconds
Started Jul 24 05:59:50 PM PDT 24
Finished Jul 24 05:59:59 PM PDT 24
Peak memory 238184 kb
Host smart-996d724c-0aed-4bd5-a4fb-ae84f0527fc7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207554447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2207554447
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/24.edn_disable.1417120372
Short name T166
Test name
Test status
Simulation time 19673524 ps
CPU time 0.85 seconds
Started Jul 24 06:00:29 PM PDT 24
Finished Jul 24 06:00:30 PM PDT 24
Peak memory 216484 kb
Host smart-367e79a5-0a5b-4bc5-9b57-20bc19edcae4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417120372 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1417120372
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/17.edn_alert.1737252961
Short name T16
Test name
Test status
Simulation time 259455342 ps
CPU time 1.33 seconds
Started Jul 24 06:00:10 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 219908 kb
Host smart-5b369b9c-5349-40d1-88d3-15077e8564b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737252961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1737252961
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2907441638
Short name T20
Test name
Test status
Simulation time 89229307 ps
CPU time 1.19 seconds
Started Jul 24 06:01:04 PM PDT 24
Finished Jul 24 06:01:05 PM PDT 24
Peak memory 217156 kb
Host smart-645560f7-357a-43fa-83d1-f1af007d43ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907441638 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2907441638
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/132.edn_alert.3194654907
Short name T100
Test name
Test status
Simulation time 30001514 ps
CPU time 1.39 seconds
Started Jul 24 06:01:19 PM PDT 24
Finished Jul 24 06:01:21 PM PDT 24
Peak memory 219828 kb
Host smart-c0762334-6dd9-418a-a939-fdd017f600c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194654907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3194654907
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/56.edn_genbits.2419780478
Short name T45
Test name
Test status
Simulation time 105784989 ps
CPU time 1.36 seconds
Started Jul 24 06:00:57 PM PDT 24
Finished Jul 24 06:00:59 PM PDT 24
Peak memory 219328 kb
Host smart-6b865f06-d79b-4d3c-828b-3156526061db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419780478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2419780478
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.743275874
Short name T129
Test name
Test status
Simulation time 92409700 ps
CPU time 1.24 seconds
Started Jul 24 06:01:33 PM PDT 24
Finished Jul 24 06:01:34 PM PDT 24
Peak memory 220032 kb
Host smart-41f5da4f-6a90-4aae-9713-8ef4eb75c946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743275874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.743275874
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/2.edn_regwen.478530386
Short name T29
Test name
Test status
Simulation time 165640379 ps
CPU time 0.99 seconds
Started Jul 24 05:59:48 PM PDT 24
Finished Jul 24 05:59:49 PM PDT 24
Peak memory 207224 kb
Host smart-eccd34fa-32a5-41b2-96be-429fd3995231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478530386 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.478530386
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/116.edn_genbits.4223760874
Short name T19
Test name
Test status
Simulation time 42568865 ps
CPU time 1.49 seconds
Started Jul 24 06:01:23 PM PDT 24
Finished Jul 24 06:01:24 PM PDT 24
Peak memory 220164 kb
Host smart-8b1bb940-63d9-4d27-aa2a-fbeab56dd93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223760874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4223760874
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.4021658109
Short name T205
Test name
Test status
Simulation time 56318826 ps
CPU time 1.6 seconds
Started Jul 24 05:59:48 PM PDT 24
Finished Jul 24 05:59:50 PM PDT 24
Peak memory 217324 kb
Host smart-56b3c0a9-b721-4ba0-bb8d-05d5599d6845
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021658109 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.4021658109
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2859018146
Short name T252
Test name
Test status
Simulation time 20993751 ps
CPU time 0.86 seconds
Started Jul 24 05:53:34 PM PDT 24
Finished Jul 24 05:53:35 PM PDT 24
Peak memory 206476 kb
Host smart-c29c4543-e51b-4114-95f8-0dc7edd0a64b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859018146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2859018146
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/default/9.edn_disable.1355124558
Short name T174
Test name
Test status
Simulation time 140172864 ps
CPU time 0.84 seconds
Started Jul 24 06:00:04 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 216688 kb
Host smart-a9a29f60-228d-4813-8c90-62238117045d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355124558 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1355124558
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2372810030
Short name T276
Test name
Test status
Simulation time 318841341 ps
CPU time 2.37 seconds
Started Jul 24 05:53:19 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 206548 kb
Host smart-b5c34aa1-1ed6-42b1-a3f2-fd58b2df1bef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372810030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2372810030
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/177.edn_alert.3918243285
Short name T181
Test name
Test status
Simulation time 48585448 ps
CPU time 1.17 seconds
Started Jul 24 06:01:43 PM PDT 24
Finished Jul 24 06:01:45 PM PDT 24
Peak memory 219700 kb
Host smart-a18256ed-6ad0-445b-bdb9-ee8f93525af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918243285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.3918243285
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.431481897
Short name T150
Test name
Test status
Simulation time 13149822 ps
CPU time 0.99 seconds
Started Jul 24 06:00:06 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 216864 kb
Host smart-3baaa877-4745-49e8-be05-813a2fabb50b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431481897 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.431481897
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable.273456410
Short name T186
Test name
Test status
Simulation time 42918162 ps
CPU time 0.91 seconds
Started Jul 24 05:59:55 PM PDT 24
Finished Jul 24 05:59:57 PM PDT 24
Peak memory 215776 kb
Host smart-72f1b7b9-8862-4331-b8b3-63c71ded7ca8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273456410 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.273456410
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable.1303377959
Short name T903
Test name
Test status
Simulation time 103695681 ps
CPU time 0.88 seconds
Started Jul 24 05:59:49 PM PDT 24
Finished Jul 24 05:59:50 PM PDT 24
Peak memory 216504 kb
Host smart-4ef18c3c-a1e9-421d-91bf-deb2bc84efa4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303377959 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1303377959
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/29.edn_alert.1966934595
Short name T89
Test name
Test status
Simulation time 173151799 ps
CPU time 1.38 seconds
Started Jul 24 06:00:33 PM PDT 24
Finished Jul 24 06:00:35 PM PDT 24
Peak memory 220032 kb
Host smart-32e8d526-c08e-4b17-81db-073a223a6f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966934595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1966934595
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/148.edn_alert.1468419559
Short name T141
Test name
Test status
Simulation time 76758485 ps
CPU time 1.16 seconds
Started Jul 24 06:01:47 PM PDT 24
Finished Jul 24 06:01:48 PM PDT 24
Peak memory 218976 kb
Host smart-bec960bb-1891-47a1-8169-712c0d4b38bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468419559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1468419559
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/123.edn_alert.4207293293
Short name T168
Test name
Test status
Simulation time 43544559 ps
CPU time 1.16 seconds
Started Jul 24 06:01:25 PM PDT 24
Finished Jul 24 06:01:26 PM PDT 24
Peak memory 218944 kb
Host smart-2b6e7357-c1d8-4c68-94e1-57a31243672e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207293293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.4207293293
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/92.edn_alert.2363151203
Short name T27
Test name
Test status
Simulation time 55166444 ps
CPU time 1.11 seconds
Started Jul 24 06:01:18 PM PDT 24
Finished Jul 24 06:01:19 PM PDT 24
Peak memory 219196 kb
Host smart-f375da55-0520-4dd4-89aa-c173ab4ed573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363151203 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2363151203
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2922054666
Short name T222
Test name
Test status
Simulation time 775988918977 ps
CPU time 1023.97 seconds
Started Jul 24 05:59:56 PM PDT 24
Finished Jul 24 06:17:01 PM PDT 24
Peak memory 224032 kb
Host smart-f98fe460-d9d3-47b4-8197-9a50b2b6a085
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922054666 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2922054666
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.edn_alert.1162249978
Short name T769
Test name
Test status
Simulation time 247062082 ps
CPU time 1.22 seconds
Started Jul 24 06:01:17 PM PDT 24
Finished Jul 24 06:01:19 PM PDT 24
Peak memory 218952 kb
Host smart-a8411f59-087a-4771-ad15-fe0fb94f5263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162249978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1162249978
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/108.edn_alert.2630549531
Short name T246
Test name
Test status
Simulation time 88792917 ps
CPU time 1.21 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:29 PM PDT 24
Peak memory 219884 kb
Host smart-9563ae60-15ae-4435-9eff-cc9474bd8d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630549531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2630549531
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/114.edn_alert.3543825353
Short name T105
Test name
Test status
Simulation time 109256860 ps
CPU time 1.2 seconds
Started Jul 24 06:01:25 PM PDT 24
Finished Jul 24 06:01:36 PM PDT 24
Peak memory 220324 kb
Host smart-5d449188-95fa-4916-bcf6-5d23f6a1fa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543825353 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3543825353
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/144.edn_alert.425147634
Short name T162
Test name
Test status
Simulation time 36426352 ps
CPU time 1.19 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:29 PM PDT 24
Peak memory 219140 kb
Host smart-3b79931f-0283-46f4-9f3b-568cb746c4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425147634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.425147634
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert.2504543197
Short name T63
Test name
Test status
Simulation time 58375759 ps
CPU time 1.06 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:02 PM PDT 24
Peak memory 219976 kb
Host smart-c09ea5f9-d693-4f66-9b4c-d42305bef767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504543197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2504543197
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/23.edn_err.1939497596
Short name T53
Test name
Test status
Simulation time 71925222 ps
CPU time 0.94 seconds
Started Jul 24 06:00:19 PM PDT 24
Finished Jul 24 06:00:20 PM PDT 24
Peak memory 224064 kb
Host smart-0a84249b-b9e0-4633-b366-c0e8d0bbe6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939497596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1939497596
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.4175155579
Short name T21
Test name
Test status
Simulation time 25964344 ps
CPU time 1.17 seconds
Started Jul 24 06:01:11 PM PDT 24
Finished Jul 24 06:01:12 PM PDT 24
Peak memory 220288 kb
Host smart-1e8ec7c4-bf9b-4a2a-b392-4d0a42247728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175155579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4175155579
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.332009219
Short name T38
Test name
Test status
Simulation time 26392418 ps
CPU time 1 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:01 PM PDT 24
Peak memory 216200 kb
Host smart-78b59e14-67fd-4517-bb95-358a28018eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332009219 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.332009219
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/14.edn_intr.3564175451
Short name T81
Test name
Test status
Simulation time 19752240 ps
CPU time 1.16 seconds
Started Jul 24 06:00:09 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 216208 kb
Host smart-c25541bc-3b63-42ee-aa8a-f178550fe030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564175451 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3564175451
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/33.edn_alert.3626701656
Short name T937
Test name
Test status
Simulation time 21646841 ps
CPU time 1.18 seconds
Started Jul 24 06:00:41 PM PDT 24
Finished Jul 24 06:00:43 PM PDT 24
Peak memory 220316 kb
Host smart-aa6fa29a-c4f4-4b58-bafb-98e83c2f323b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626701656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3626701656
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/7.edn_disable.2090767342
Short name T206
Test name
Test status
Simulation time 11490242 ps
CPU time 0.9 seconds
Started Jul 24 05:59:59 PM PDT 24
Finished Jul 24 06:00:00 PM PDT 24
Peak memory 216820 kb
Host smart-94d51d7c-7cef-4829-a45c-97f202874b92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090767342 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2090767342
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3876185112
Short name T188
Test name
Test status
Simulation time 308032814 ps
CPU time 1.2 seconds
Started Jul 24 05:59:49 PM PDT 24
Finished Jul 24 05:59:51 PM PDT 24
Peak memory 220220 kb
Host smart-77b2dc6e-f1d8-4e1b-ac9c-7ecd4a5a41b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876185112 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3876185112
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1820977015
Short name T640
Test name
Test status
Simulation time 125426364 ps
CPU time 1.17 seconds
Started Jul 24 06:00:07 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 217292 kb
Host smart-b6ffdcc7-b648-46fa-99a2-2db71e37cdef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820977015 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1820977015
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_disable.2880861468
Short name T799
Test name
Test status
Simulation time 77893059 ps
CPU time 0.86 seconds
Started Jul 24 06:00:09 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 216584 kb
Host smart-2fa1aa70-7198-4a88-a6b2-e690fa9fe8e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880861468 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2880861468
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.258367848
Short name T132
Test name
Test status
Simulation time 70131953 ps
CPU time 1.09 seconds
Started Jul 24 06:00:05 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 217388 kb
Host smart-353a1b03-8a2e-433c-b933-c391207eaf66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258367848 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.258367848
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3430910722
Short name T84
Test name
Test status
Simulation time 24722923 ps
CPU time 1.06 seconds
Started Jul 24 06:00:04 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 220248 kb
Host smart-91e57962-bc29-4e36-aa96-d7b5195c87bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430910722 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3430910722
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.195405627
Short name T111
Test name
Test status
Simulation time 358564102 ps
CPU time 1.13 seconds
Started Jul 24 06:00:07 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 217352 kb
Host smart-37cdfa49-0b5c-4093-9d5d-bb5b0f7ac25c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195405627 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.195405627
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/147.edn_alert.2031713179
Short name T135
Test name
Test status
Simulation time 92128861 ps
CPU time 1.26 seconds
Started Jul 24 06:01:36 PM PDT 24
Finished Jul 24 06:01:37 PM PDT 24
Peak memory 216020 kb
Host smart-6d2ac089-ded8-426a-980b-a7e023aaebbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031713179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.2031713179
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/21.edn_err.899197082
Short name T842
Test name
Test status
Simulation time 19597188 ps
CPU time 1.09 seconds
Started Jul 24 06:00:20 PM PDT 24
Finished Jul 24 06:00:21 PM PDT 24
Peak memory 219748 kb
Host smart-c190cf52-b3b5-451e-b2b2-10b74f9913ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899197082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.899197082
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/9.edn_err.1650019810
Short name T179
Test name
Test status
Simulation time 20294791 ps
CPU time 1.12 seconds
Started Jul 24 05:59:58 PM PDT 24
Finished Jul 24 06:00:00 PM PDT 24
Peak memory 218804 kb
Host smart-ddd7e9d5-8d54-4392-8b0d-cafbac0c5252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650019810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1650019810
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/164.edn_genbits.3332501290
Short name T321
Test name
Test status
Simulation time 54582021 ps
CPU time 1.32 seconds
Started Jul 24 06:01:41 PM PDT 24
Finished Jul 24 06:01:43 PM PDT 24
Peak memory 219248 kb
Host smart-1b28bc0b-a4d6-4f41-8dd1-a0fd013fe9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332501290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3332501290
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert_test.2193092312
Short name T94
Test name
Test status
Simulation time 32236892 ps
CPU time 0.79 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 206664 kb
Host smart-5fecba00-2bb3-43c5-bce4-798c1eb05279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193092312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2193092312
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_genbits.1160078382
Short name T329
Test name
Test status
Simulation time 22490093 ps
CPU time 1.25 seconds
Started Jul 24 06:00:23 PM PDT 24
Finished Jul 24 06:00:24 PM PDT 24
Peak memory 217952 kb
Host smart-0957055e-b4ba-453d-b1f4-2101826d9ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160078382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1160078382
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_genbits.117017873
Short name T316
Test name
Test status
Simulation time 82250145 ps
CPU time 1.21 seconds
Started Jul 24 05:59:48 PM PDT 24
Finished Jul 24 05:59:49 PM PDT 24
Peak memory 219360 kb
Host smart-664976ce-c1c3-49dc-97bd-c515d27f6b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117017873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.117017873
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2008318307
Short name T545
Test name
Test status
Simulation time 21059712167 ps
CPU time 513.29 seconds
Started Jul 24 06:00:11 PM PDT 24
Finished Jul 24 06:08:45 PM PDT 24
Peak memory 218596 kb
Host smart-e35ac7fe-7798-4034-af5e-85f8aeef247b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008318307 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2008318307
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.edn_genbits.439010995
Short name T533
Test name
Test status
Simulation time 96605438 ps
CPU time 1.5 seconds
Started Jul 24 06:01:34 PM PDT 24
Finished Jul 24 06:01:36 PM PDT 24
Peak memory 219364 kb
Host smart-6886730d-fbbf-4fc7-971a-0ffb812c84f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439010995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.439010995
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2541845954
Short name T37
Test name
Test status
Simulation time 21789224 ps
CPU time 0.95 seconds
Started Jul 24 06:00:26 PM PDT 24
Finished Jul 24 06:00:27 PM PDT 24
Peak memory 216124 kb
Host smart-e54f720b-203b-4667-b4b1-44fab42083e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541845954 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2541845954
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.335327707
Short name T288
Test name
Test status
Simulation time 89930827 ps
CPU time 2.56 seconds
Started Jul 24 05:53:34 PM PDT 24
Finished Jul 24 05:53:37 PM PDT 24
Peak memory 206636 kb
Host smart-a1cd0cb6-6fee-4047-8711-857e17d7a753
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335327707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.335327707
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2455522307
Short name T286
Test name
Test status
Simulation time 130451962 ps
CPU time 2.86 seconds
Started Jul 24 05:53:42 PM PDT 24
Finished Jul 24 05:53:46 PM PDT 24
Peak memory 214736 kb
Host smart-556ee2df-ef1c-46da-ac30-aed272fba7e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455522307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2455522307
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2563450279
Short name T231
Test name
Test status
Simulation time 52821970040 ps
CPU time 1167.06 seconds
Started Jul 24 05:59:53 PM PDT 24
Finished Jul 24 06:19:20 PM PDT 24
Peak memory 221144 kb
Host smart-a4d9ab68-c6b4-4b09-b870-21b0a043b49c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563450279 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2563450279
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.edn_genbits.1652757992
Short name T323
Test name
Test status
Simulation time 40864611 ps
CPU time 1.47 seconds
Started Jul 24 06:01:19 PM PDT 24
Finished Jul 24 06:01:21 PM PDT 24
Peak memory 217576 kb
Host smart-2d20875a-7d25-4c4f-9e68-f270023c51ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652757992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1652757992
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.953475254
Short name T59
Test name
Test status
Simulation time 42506995 ps
CPU time 1.41 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:29 PM PDT 24
Peak memory 218820 kb
Host smart-1cf2cef3-c523-406c-acc4-b5529c43ee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953475254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.953475254
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3981209440
Short name T835
Test name
Test status
Simulation time 103041856 ps
CPU time 1.7 seconds
Started Jul 24 06:01:22 PM PDT 24
Finished Jul 24 06:01:24 PM PDT 24
Peak memory 219388 kb
Host smart-5302eb2d-a9a2-402d-abaf-8ea5ef47468a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981209440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3981209440
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3861631034
Short name T915
Test name
Test status
Simulation time 103058956 ps
CPU time 1.29 seconds
Started Jul 24 06:01:25 PM PDT 24
Finished Jul 24 06:01:27 PM PDT 24
Peak memory 217652 kb
Host smart-01084aa8-d1aa-425d-9cdf-dbc1420a9ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861631034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3861631034
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.2787267377
Short name T311
Test name
Test status
Simulation time 43551994 ps
CPU time 1.53 seconds
Started Jul 24 06:01:33 PM PDT 24
Finished Jul 24 06:01:35 PM PDT 24
Peak memory 219064 kb
Host smart-f0d08ce5-215a-4f78-96c0-5ee927f1e0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787267377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2787267377
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_genbits.2264889556
Short name T328
Test name
Test status
Simulation time 88681368 ps
CPU time 1.56 seconds
Started Jul 24 06:00:10 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 219176 kb
Host smart-e44812a3-3df1-4837-9290-37537bf2f675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264889556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2264889556
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_stress_all.1894301545
Short name T821
Test name
Test status
Simulation time 384070191 ps
CPU time 4.02 seconds
Started Jul 24 06:00:15 PM PDT 24
Finished Jul 24 06:00:20 PM PDT 24
Peak memory 218880 kb
Host smart-dee21977-6dd3-4743-9d59-fff7f7ce4bea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894301545 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1894301545
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/172.edn_genbits.3260391689
Short name T324
Test name
Test status
Simulation time 36156918 ps
CPU time 1.39 seconds
Started Jul 24 06:01:57 PM PDT 24
Finished Jul 24 06:01:58 PM PDT 24
Peak memory 217816 kb
Host smart-f9c0ffad-50a1-4caa-814d-8af86ea6b2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260391689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3260391689
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3901883560
Short name T327
Test name
Test status
Simulation time 136369988 ps
CPU time 3.45 seconds
Started Jul 24 06:02:01 PM PDT 24
Finished Jul 24 06:02:04 PM PDT 24
Peak memory 218928 kb
Host smart-29d73097-e674-44f1-8af2-4befdfbaae1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901883560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3901883560
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/240.edn_genbits.2687946349
Short name T319
Test name
Test status
Simulation time 33193727 ps
CPU time 1.19 seconds
Started Jul 24 06:02:02 PM PDT 24
Finished Jul 24 06:02:04 PM PDT 24
Peak memory 218776 kb
Host smart-1152a297-62ac-4b24-9275-2aa1279e8182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687946349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2687946349
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_genbits.2721450920
Short name T318
Test name
Test status
Simulation time 66899303 ps
CPU time 1.27 seconds
Started Jul 24 06:01:06 PM PDT 24
Finished Jul 24 06:01:07 PM PDT 24
Peak memory 220292 kb
Host smart-c2b69c42-83b7-426d-99e9-e6667eeec333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721450920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2721450920
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1232425656
Short name T283
Test name
Test status
Simulation time 79468852 ps
CPU time 1.05 seconds
Started Jul 24 05:59:59 PM PDT 24
Finished Jul 24 06:00:01 PM PDT 24
Peak memory 217144 kb
Host smart-50d8ac39-b4ed-4069-8a38-3dd01ffc40b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232425656 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1232425656
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_intr.3192393105
Short name T837
Test name
Test status
Simulation time 40867653 ps
CPU time 0.92 seconds
Started Jul 24 06:00:05 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215884 kb
Host smart-718c0998-687d-4219-93d2-5c18c94749d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192393105 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3192393105
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/27.edn_err.2350054510
Short name T96
Test name
Test status
Simulation time 47965068 ps
CPU time 1.08 seconds
Started Jul 24 06:00:24 PM PDT 24
Finished Jul 24 06:00:30 PM PDT 24
Peak memory 220248 kb
Host smart-eff8031f-0f0b-4ff3-b9e7-c9b99655b9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350054510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2350054510
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3009912280
Short name T78
Test name
Test status
Simulation time 56441115 ps
CPU time 1.86 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:00:55 PM PDT 24
Peak memory 220604 kb
Host smart-fd80fa88-3bdf-474f-b70e-f68e87cb223d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009912280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3009912280
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2872707199
Short name T1034
Test name
Test status
Simulation time 24337162 ps
CPU time 1.13 seconds
Started Jul 24 05:53:19 PM PDT 24
Finished Jul 24 05:53:20 PM PDT 24
Peak memory 206516 kb
Host smart-ca386f53-6e0f-45af-a994-32fbff14b473
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872707199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2872707199
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.714702050
Short name T1024
Test name
Test status
Simulation time 541310580 ps
CPU time 3.76 seconds
Started Jul 24 05:53:18 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 206448 kb
Host smart-028a00e7-9acc-425c-995a-67574b6be08c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714702050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.714702050
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1398513724
Short name T253
Test name
Test status
Simulation time 39831487 ps
CPU time 1.23 seconds
Started Jul 24 05:53:16 PM PDT 24
Finished Jul 24 05:53:18 PM PDT 24
Peak memory 206420 kb
Host smart-5ff728c1-6b16-4700-9690-137fd38158f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398513724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1398513724
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.4147791493
Short name T1098
Test name
Test status
Simulation time 23336854 ps
CPU time 1.11 seconds
Started Jul 24 05:53:16 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 214884 kb
Host smart-9af1756c-042a-4ecb-9368-f837dc031595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147791493 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.4147791493
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2357171065
Short name T265
Test name
Test status
Simulation time 40053751 ps
CPU time 0.81 seconds
Started Jul 24 05:53:17 PM PDT 24
Finished Jul 24 05:53:18 PM PDT 24
Peak memory 206296 kb
Host smart-9f306308-cfdb-48fb-ace1-a4e13821465e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357171065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2357171065
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1457844446
Short name T1125
Test name
Test status
Simulation time 36102117 ps
CPU time 0.86 seconds
Started Jul 24 05:53:20 PM PDT 24
Finished Jul 24 05:53:21 PM PDT 24
Peak memory 206464 kb
Host smart-be8e26ce-c46a-451c-b9d7-0f5a4c0b6f09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457844446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1457844446
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1985060994
Short name T269
Test name
Test status
Simulation time 20689678 ps
CPU time 1.1 seconds
Started Jul 24 05:53:15 PM PDT 24
Finished Jul 24 05:53:17 PM PDT 24
Peak memory 206512 kb
Host smart-5572fdb7-191c-4148-a636-99bc2381a8ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985060994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1985060994
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2300132050
Short name T1046
Test name
Test status
Simulation time 45309581 ps
CPU time 1.95 seconds
Started Jul 24 05:53:21 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 223028 kb
Host smart-5c3729aa-1d88-4056-8157-cab5533f97ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300132050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2300132050
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1834868973
Short name T1071
Test name
Test status
Simulation time 159008089 ps
CPU time 1.56 seconds
Started Jul 24 05:53:17 PM PDT 24
Finished Jul 24 05:53:18 PM PDT 24
Peak memory 206516 kb
Host smart-7503d49a-41c9-40e1-a6bf-e8de9c068f17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834868973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1834868973
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2218404456
Short name T1052
Test name
Test status
Simulation time 50894234 ps
CPU time 1.45 seconds
Started Jul 24 05:53:20 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 206424 kb
Host smart-71143934-4012-401d-a512-63fe296982f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218404456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2218404456
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1428837135
Short name T1015
Test name
Test status
Simulation time 182638995 ps
CPU time 2.92 seconds
Started Jul 24 05:53:18 PM PDT 24
Finished Jul 24 05:53:21 PM PDT 24
Peak memory 206440 kb
Host smart-cc7cd9d2-4c62-41c5-80f3-91365a22f208
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428837135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1428837135
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3885133627
Short name T1065
Test name
Test status
Simulation time 56196562 ps
CPU time 0.94 seconds
Started Jul 24 05:53:18 PM PDT 24
Finished Jul 24 05:53:20 PM PDT 24
Peak memory 206480 kb
Host smart-0b7f1ed4-4c48-4754-a9af-bb8eece26468
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885133627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3885133627
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3423922799
Short name T1128
Test name
Test status
Simulation time 17799926 ps
CPU time 1.04 seconds
Started Jul 24 05:53:22 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 206596 kb
Host smart-e7e93919-5976-476d-9d53-b1b405e0e5a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423922799 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3423922799
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2735895730
Short name T1122
Test name
Test status
Simulation time 34921553 ps
CPU time 0.92 seconds
Started Jul 24 05:53:21 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 206292 kb
Host smart-6002ddfe-e619-4838-9c96-7eb1f6ea6da5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735895730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2735895730
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.986569872
Short name T1113
Test name
Test status
Simulation time 50694363 ps
CPU time 0.84 seconds
Started Jul 24 05:53:21 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 206480 kb
Host smart-cb8ce141-9450-4922-9440-3000c8d4429e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986569872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.986569872
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.965205855
Short name T1126
Test name
Test status
Simulation time 127341797 ps
CPU time 1.33 seconds
Started Jul 24 05:53:22 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 206500 kb
Host smart-b78224ca-829b-4890-b09b-a5836173fe6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965205855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.965205855
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.314410473
Short name T1019
Test name
Test status
Simulation time 248823438 ps
CPU time 4.41 seconds
Started Jul 24 05:53:19 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 214764 kb
Host smart-524d679a-8cfb-4578-a0f9-62fa7f92602b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314410473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.314410473
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1144015888
Short name T1022
Test name
Test status
Simulation time 58311499 ps
CPU time 1 seconds
Started Jul 24 05:53:47 PM PDT 24
Finished Jul 24 05:53:48 PM PDT 24
Peak memory 206520 kb
Host smart-0781106e-7f9d-4ce7-94fc-fdbf5b097dba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144015888 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1144015888
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.649082531
Short name T255
Test name
Test status
Simulation time 16283290 ps
CPU time 0.96 seconds
Started Jul 24 05:53:34 PM PDT 24
Finished Jul 24 05:53:35 PM PDT 24
Peak memory 206492 kb
Host smart-4bf179e1-2a10-4f12-b70d-45f724fc7c73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649082531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.649082531
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3358707616
Short name T1004
Test name
Test status
Simulation time 15708171 ps
CPU time 0.88 seconds
Started Jul 24 05:53:47 PM PDT 24
Finished Jul 24 05:53:48 PM PDT 24
Peak memory 206456 kb
Host smart-fd296a95-a7e0-4b28-82ae-712e559f327b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358707616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3358707616
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3233081582
Short name T1054
Test name
Test status
Simulation time 34967401 ps
CPU time 0.91 seconds
Started Jul 24 05:53:34 PM PDT 24
Finished Jul 24 05:53:35 PM PDT 24
Peak memory 206576 kb
Host smart-9046582d-4924-4944-b5f0-244521fc3e1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233081582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3233081582
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3009299592
Short name T1010
Test name
Test status
Simulation time 103687512 ps
CPU time 3.88 seconds
Started Jul 24 05:53:34 PM PDT 24
Finished Jul 24 05:53:38 PM PDT 24
Peak memory 214908 kb
Host smart-c439035b-8914-40ca-877f-c76406be89a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009299592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3009299592
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2439933630
Short name T1115
Test name
Test status
Simulation time 27618568 ps
CPU time 1.37 seconds
Started Jul 24 05:53:36 PM PDT 24
Finished Jul 24 05:53:37 PM PDT 24
Peak memory 217240 kb
Host smart-a822f65c-2705-4ac1-b778-de1a6868809b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439933630 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2439933630
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2407960467
Short name T1037
Test name
Test status
Simulation time 87774649 ps
CPU time 0.93 seconds
Started Jul 24 05:53:35 PM PDT 24
Finished Jul 24 05:53:36 PM PDT 24
Peak memory 206508 kb
Host smart-07c3f83d-c96f-4a34-967a-15886986855c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407960467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2407960467
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.902745865
Short name T1062
Test name
Test status
Simulation time 14520464 ps
CPU time 0.88 seconds
Started Jul 24 05:53:34 PM PDT 24
Finished Jul 24 05:53:36 PM PDT 24
Peak memory 206480 kb
Host smart-28443a18-283e-4bf2-b13b-47066a0811f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902745865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.902745865
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1468322423
Short name T1049
Test name
Test status
Simulation time 30570704 ps
CPU time 1.02 seconds
Started Jul 24 05:53:41 PM PDT 24
Finished Jul 24 05:53:42 PM PDT 24
Peak memory 206644 kb
Host smart-5a143d55-a51f-434f-a12b-ae20152d9189
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468322423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1468322423
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1728970212
Short name T1017
Test name
Test status
Simulation time 135853707 ps
CPU time 1.62 seconds
Started Jul 24 05:53:36 PM PDT 24
Finished Jul 24 05:53:38 PM PDT 24
Peak memory 214832 kb
Host smart-f3a56ef8-b505-470f-b276-a63746d823f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728970212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1728970212
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2776010452
Short name T277
Test name
Test status
Simulation time 155582856 ps
CPU time 2.28 seconds
Started Jul 24 05:53:33 PM PDT 24
Finished Jul 24 05:53:35 PM PDT 24
Peak memory 206568 kb
Host smart-5a7fc8d4-9c42-4242-8bd9-8bd2a83f01f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776010452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2776010452
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2399088395
Short name T1091
Test name
Test status
Simulation time 24784053 ps
CPU time 1.24 seconds
Started Jul 24 05:53:46 PM PDT 24
Finished Jul 24 05:53:47 PM PDT 24
Peak memory 214772 kb
Host smart-2c040c65-7a77-431e-9783-4a15a56011cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399088395 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2399088395
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3066349298
Short name T1002
Test name
Test status
Simulation time 36634688 ps
CPU time 1.12 seconds
Started Jul 24 05:53:36 PM PDT 24
Finished Jul 24 05:53:37 PM PDT 24
Peak memory 206580 kb
Host smart-16e24595-b07a-46b4-9bfa-0458e65f60b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066349298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3066349298
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1598559313
Short name T1013
Test name
Test status
Simulation time 23605560 ps
CPU time 0.87 seconds
Started Jul 24 05:53:34 PM PDT 24
Finished Jul 24 05:53:35 PM PDT 24
Peak memory 206404 kb
Host smart-301bce40-b0ad-40b4-87db-59d6d23db672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598559313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1598559313
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1533169193
Short name T264
Test name
Test status
Simulation time 30079241 ps
CPU time 1.29 seconds
Started Jul 24 05:53:41 PM PDT 24
Finished Jul 24 05:53:42 PM PDT 24
Peak memory 206472 kb
Host smart-d2fdf9aa-6e1d-427c-8d0c-e01afa893332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533169193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1533169193
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3568332036
Short name T1075
Test name
Test status
Simulation time 103950396 ps
CPU time 1.32 seconds
Started Jul 24 05:53:33 PM PDT 24
Finished Jul 24 05:53:35 PM PDT 24
Peak memory 214800 kb
Host smart-e8a0e2c5-7f85-4ea3-8e61-ca9e0dedfca0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568332036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3568332036
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1516602949
Short name T1097
Test name
Test status
Simulation time 131571005 ps
CPU time 3.09 seconds
Started Jul 24 05:53:35 PM PDT 24
Finished Jul 24 05:53:38 PM PDT 24
Peak memory 206876 kb
Host smart-31daca57-b194-4a97-8a42-a1fa6c82c853
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516602949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1516602949
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.653545425
Short name T1048
Test name
Test status
Simulation time 34024794 ps
CPU time 1.59 seconds
Started Jul 24 05:53:33 PM PDT 24
Finished Jul 24 05:53:35 PM PDT 24
Peak memory 214780 kb
Host smart-9a4a4015-cd82-4cb0-8040-224a16d28174
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653545425 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.653545425
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1301176728
Short name T262
Test name
Test status
Simulation time 31839984 ps
CPU time 0.8 seconds
Started Jul 24 05:53:32 PM PDT 24
Finished Jul 24 05:53:33 PM PDT 24
Peak memory 206308 kb
Host smart-f05ac07f-3f9f-455a-ace7-e481fd65a02d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301176728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1301176728
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3048545383
Short name T1105
Test name
Test status
Simulation time 13959204 ps
CPU time 0.86 seconds
Started Jul 24 05:53:40 PM PDT 24
Finished Jul 24 05:53:41 PM PDT 24
Peak memory 206432 kb
Host smart-50d50fab-2d2a-42fe-9209-386f74460f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048545383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3048545383
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3352802528
Short name T1111
Test name
Test status
Simulation time 59839047 ps
CPU time 1.15 seconds
Started Jul 24 05:53:49 PM PDT 24
Finished Jul 24 05:53:51 PM PDT 24
Peak memory 206544 kb
Host smart-8b3b5a24-8374-4cd3-9610-ef1b79b7b461
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352802528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3352802528
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3640290368
Short name T1043
Test name
Test status
Simulation time 105038607 ps
CPU time 2.13 seconds
Started Jul 24 05:53:46 PM PDT 24
Finished Jul 24 05:53:48 PM PDT 24
Peak memory 214776 kb
Host smart-d992c83c-a1d6-4e37-8a89-33e961aa4292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640290368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3640290368
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1222494257
Short name T1085
Test name
Test status
Simulation time 302594429 ps
CPU time 5.24 seconds
Started Jul 24 05:53:34 PM PDT 24
Finished Jul 24 05:53:40 PM PDT 24
Peak memory 206532 kb
Host smart-2639213c-a409-4895-adac-155199685ddf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222494257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1222494257
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1671893344
Short name T1028
Test name
Test status
Simulation time 76536866 ps
CPU time 2.01 seconds
Started Jul 24 05:53:43 PM PDT 24
Finished Jul 24 05:53:46 PM PDT 24
Peak memory 214856 kb
Host smart-b7dbdd66-6478-4d82-8c58-a2c918acd18c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671893344 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1671893344
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2814195549
Short name T1077
Test name
Test status
Simulation time 34446085 ps
CPU time 0.85 seconds
Started Jul 24 05:53:45 PM PDT 24
Finished Jul 24 05:53:46 PM PDT 24
Peak memory 206276 kb
Host smart-55e1d900-42ab-4db7-add9-0ffdf88cd4cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814195549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2814195549
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.924427057
Short name T1094
Test name
Test status
Simulation time 22472934 ps
CPU time 1.09 seconds
Started Jul 24 05:53:33 PM PDT 24
Finished Jul 24 05:53:34 PM PDT 24
Peak memory 206572 kb
Host smart-051762f1-11a1-4e42-bcd1-54b0a33fa213
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924427057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.924427057
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.4177082389
Short name T1078
Test name
Test status
Simulation time 224284362 ps
CPU time 1.88 seconds
Started Jul 24 05:53:38 PM PDT 24
Finished Jul 24 05:53:40 PM PDT 24
Peak memory 214884 kb
Host smart-6cea32e0-9c1a-4d37-bb4f-0d98dd74be91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177082389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.4177082389
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1224884920
Short name T1056
Test name
Test status
Simulation time 73487083 ps
CPU time 1.45 seconds
Started Jul 24 05:53:39 PM PDT 24
Finished Jul 24 05:53:41 PM PDT 24
Peak memory 206640 kb
Host smart-f079225c-c111-4830-8959-ab96cea6113b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224884920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1224884920
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3270977474
Short name T1041
Test name
Test status
Simulation time 68725978 ps
CPU time 1.53 seconds
Started Jul 24 05:53:42 PM PDT 24
Finished Jul 24 05:53:44 PM PDT 24
Peak memory 214848 kb
Host smart-f9ed663b-36e8-4bfd-86cb-d9a4d1cd8416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270977474 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3270977474
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2991148053
Short name T256
Test name
Test status
Simulation time 33936253 ps
CPU time 0.96 seconds
Started Jul 24 05:53:48 PM PDT 24
Finished Jul 24 05:53:49 PM PDT 24
Peak memory 206424 kb
Host smart-4f4d3f4c-befc-4b97-80af-79c606a71453
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991148053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2991148053
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2976010901
Short name T1053
Test name
Test status
Simulation time 14916886 ps
CPU time 0.91 seconds
Started Jul 24 05:53:48 PM PDT 24
Finished Jul 24 05:53:49 PM PDT 24
Peak memory 206432 kb
Host smart-b88a15fb-7347-4b54-b429-4c17e54478f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976010901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2976010901
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4232618976
Short name T1092
Test name
Test status
Simulation time 20162030 ps
CPU time 1.04 seconds
Started Jul 24 05:53:45 PM PDT 24
Finished Jul 24 05:53:46 PM PDT 24
Peak memory 206616 kb
Host smart-f64661cf-15c6-4026-9414-6ef20c822d38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232618976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.4232618976
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1083242435
Short name T1107
Test name
Test status
Simulation time 38727250 ps
CPU time 1.6 seconds
Started Jul 24 05:53:44 PM PDT 24
Finished Jul 24 05:53:46 PM PDT 24
Peak memory 214828 kb
Host smart-16801b29-fb2f-4231-9f66-c8cc18e1b669
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083242435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1083242435
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4211102816
Short name T1084
Test name
Test status
Simulation time 166920502 ps
CPU time 1.65 seconds
Started Jul 24 05:53:47 PM PDT 24
Finished Jul 24 05:53:49 PM PDT 24
Peak memory 206620 kb
Host smart-76f5e01e-351d-47e4-829b-94f80c7cc49a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211102816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.4211102816
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2800718372
Short name T1096
Test name
Test status
Simulation time 95302442 ps
CPU time 1.48 seconds
Started Jul 24 05:53:42 PM PDT 24
Finished Jul 24 05:53:43 PM PDT 24
Peak memory 214892 kb
Host smart-36e63e1e-f01b-48ee-ada8-f3569bca68d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800718372 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2800718372
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.4267579068
Short name T1023
Test name
Test status
Simulation time 69794620 ps
CPU time 0.9 seconds
Started Jul 24 05:53:44 PM PDT 24
Finished Jul 24 05:53:45 PM PDT 24
Peak memory 206448 kb
Host smart-c345ef9d-0a7e-460c-bd34-8e6e3b02ca4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267579068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.4267579068
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3577785768
Short name T1007
Test name
Test status
Simulation time 15421923 ps
CPU time 0.92 seconds
Started Jul 24 05:53:47 PM PDT 24
Finished Jul 24 05:53:48 PM PDT 24
Peak memory 206464 kb
Host smart-0d140d5b-09ee-47e9-88d6-feba8a0d5066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577785768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3577785768
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.667813515
Short name T1080
Test name
Test status
Simulation time 32382902 ps
CPU time 1.38 seconds
Started Jul 24 05:53:48 PM PDT 24
Finished Jul 24 05:53:50 PM PDT 24
Peak memory 206132 kb
Host smart-5a0888ff-1c04-4546-97ac-782b6f24dbfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667813515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_ou
tstanding.667813515
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.4125171347
Short name T1036
Test name
Test status
Simulation time 35734406 ps
CPU time 2.36 seconds
Started Jul 24 05:53:42 PM PDT 24
Finished Jul 24 05:53:45 PM PDT 24
Peak memory 214784 kb
Host smart-b74dae1c-de62-4c96-b628-25fe106b890d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125171347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.4125171347
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1541772435
Short name T997
Test name
Test status
Simulation time 93539358 ps
CPU time 1.62 seconds
Started Jul 24 05:53:49 PM PDT 24
Finished Jul 24 05:53:51 PM PDT 24
Peak memory 214756 kb
Host smart-dc02893b-7ee4-4ba5-b791-9cb1c629d5e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541772435 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1541772435
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.248889311
Short name T260
Test name
Test status
Simulation time 31312133 ps
CPU time 0.78 seconds
Started Jul 24 05:53:47 PM PDT 24
Finished Jul 24 05:53:48 PM PDT 24
Peak memory 206308 kb
Host smart-f95c5dd4-b8f2-4eb1-960d-f38f0f0bb2c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248889311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.248889311
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.4018030349
Short name T1051
Test name
Test status
Simulation time 11701744 ps
CPU time 0.85 seconds
Started Jul 24 05:53:40 PM PDT 24
Finished Jul 24 05:53:41 PM PDT 24
Peak memory 206496 kb
Host smart-8357a1ca-7d23-4fca-bddb-ae86108aa957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018030349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.4018030349
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3191801609
Short name T267
Test name
Test status
Simulation time 37140172 ps
CPU time 1.13 seconds
Started Jul 24 05:53:45 PM PDT 24
Finished Jul 24 05:53:47 PM PDT 24
Peak memory 206552 kb
Host smart-ebb56676-c4a3-4493-9547-d85028ee5aca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191801609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3191801609
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1098818197
Short name T1100
Test name
Test status
Simulation time 23991890 ps
CPU time 1.72 seconds
Started Jul 24 05:53:48 PM PDT 24
Finished Jul 24 05:53:50 PM PDT 24
Peak memory 222992 kb
Host smart-bd38d09b-115d-46e2-be53-4d31594cbb4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098818197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1098818197
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1904542170
Short name T1090
Test name
Test status
Simulation time 46728972 ps
CPU time 1.64 seconds
Started Jul 24 05:53:48 PM PDT 24
Finished Jul 24 05:53:50 PM PDT 24
Peak memory 214432 kb
Host smart-081d540b-c7a2-4236-a24f-e58a7eece6ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904542170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1904542170
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1602553020
Short name T1066
Test name
Test status
Simulation time 34556573 ps
CPU time 1.6 seconds
Started Jul 24 05:53:45 PM PDT 24
Finished Jul 24 05:53:47 PM PDT 24
Peak memory 214836 kb
Host smart-234722ba-a9f8-413d-b25a-a866df48714f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602553020 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1602553020
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.288741715
Short name T254
Test name
Test status
Simulation time 26739469 ps
CPU time 0.93 seconds
Started Jul 24 05:53:46 PM PDT 24
Finished Jul 24 05:53:47 PM PDT 24
Peak memory 206476 kb
Host smart-f9712282-750f-4019-84de-1ac2a01c1fda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288741715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.288741715
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.389686554
Short name T1089
Test name
Test status
Simulation time 19269587 ps
CPU time 0.82 seconds
Started Jul 24 05:53:48 PM PDT 24
Finished Jul 24 05:53:49 PM PDT 24
Peak memory 206304 kb
Host smart-89fabc08-d957-41f6-aef3-29d1b0717f7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389686554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.389686554
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1514229721
Short name T271
Test name
Test status
Simulation time 20507520 ps
CPU time 1.11 seconds
Started Jul 24 05:53:45 PM PDT 24
Finished Jul 24 05:53:47 PM PDT 24
Peak memory 206484 kb
Host smart-b2db31b7-0609-47fb-9909-3e45da62a50a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514229721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1514229721
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2088319415
Short name T1026
Test name
Test status
Simulation time 107335682 ps
CPU time 3.5 seconds
Started Jul 24 05:53:45 PM PDT 24
Finished Jul 24 05:53:49 PM PDT 24
Peak memory 214748 kb
Host smart-67f51955-0848-4e13-9020-a296b481fd87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088319415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2088319415
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1936934186
Short name T1088
Test name
Test status
Simulation time 177673190 ps
CPU time 1.64 seconds
Started Jul 24 05:53:48 PM PDT 24
Finished Jul 24 05:53:50 PM PDT 24
Peak memory 214756 kb
Host smart-858b20ec-79c1-4d8f-9d8d-030a559d2292
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936934186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1936934186
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2196882091
Short name T1087
Test name
Test status
Simulation time 17825916 ps
CPU time 1.04 seconds
Started Jul 24 05:53:47 PM PDT 24
Finished Jul 24 05:53:48 PM PDT 24
Peak memory 206588 kb
Host smart-d3babaed-04dc-49dd-ba08-73d043873dce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196882091 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2196882091
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2564291655
Short name T1070
Test name
Test status
Simulation time 31682766 ps
CPU time 0.8 seconds
Started Jul 24 05:53:44 PM PDT 24
Finished Jul 24 05:53:45 PM PDT 24
Peak memory 206208 kb
Host smart-6f2ee59e-34d2-4adf-b276-d266f6d6519f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564291655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2564291655
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1877124202
Short name T1014
Test name
Test status
Simulation time 12866480 ps
CPU time 0.87 seconds
Started Jul 24 05:53:49 PM PDT 24
Finished Jul 24 05:53:50 PM PDT 24
Peak memory 206468 kb
Host smart-282d73b4-a8dc-412c-9d1f-078dd49f9744
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877124202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1877124202
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3819606588
Short name T1109
Test name
Test status
Simulation time 173469134 ps
CPU time 1.29 seconds
Started Jul 24 05:53:49 PM PDT 24
Finished Jul 24 05:53:51 PM PDT 24
Peak memory 206764 kb
Host smart-26ca72d8-a20b-4691-be15-a19fa4e856c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819606588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3819606588
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3222435606
Short name T1029
Test name
Test status
Simulation time 74132121 ps
CPU time 2.86 seconds
Started Jul 24 05:53:49 PM PDT 24
Finished Jul 24 05:53:52 PM PDT 24
Peak memory 214776 kb
Host smart-db61bca0-ccfb-4bee-8672-91669b37e9a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222435606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3222435606
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.426744455
Short name T1063
Test name
Test status
Simulation time 349143812 ps
CPU time 2.06 seconds
Started Jul 24 05:53:43 PM PDT 24
Finished Jul 24 05:53:46 PM PDT 24
Peak memory 206544 kb
Host smart-5fcb472b-9dae-428a-a99b-966b2375cc7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426744455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.426744455
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3391267388
Short name T1129
Test name
Test status
Simulation time 44123827 ps
CPU time 1 seconds
Started Jul 24 05:53:21 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 206552 kb
Host smart-adbc31eb-64f0-4f64-85f9-31a9377aa7f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391267388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3391267388
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1002222150
Short name T1117
Test name
Test status
Simulation time 672843910 ps
CPU time 5.64 seconds
Started Jul 24 05:53:26 PM PDT 24
Finished Jul 24 05:53:32 PM PDT 24
Peak memory 206464 kb
Host smart-b245bc64-f2b3-4355-b966-9b80985f840a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002222150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1002222150
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.840485329
Short name T1008
Test name
Test status
Simulation time 87287862 ps
CPU time 0.83 seconds
Started Jul 24 05:53:34 PM PDT 24
Finished Jul 24 05:53:35 PM PDT 24
Peak memory 206360 kb
Host smart-0ced026f-fa00-4d5d-9ef6-0c12f7f08cfd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840485329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.840485329
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.537134652
Short name T1001
Test name
Test status
Simulation time 20456032 ps
CPU time 1.25 seconds
Started Jul 24 05:53:24 PM PDT 24
Finished Jul 24 05:53:26 PM PDT 24
Peak memory 214912 kb
Host smart-e3050d4a-f349-49bd-b9bf-6a2c8e024665
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537134652 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.537134652
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.371218742
Short name T257
Test name
Test status
Simulation time 15663229 ps
CPU time 0.9 seconds
Started Jul 24 05:53:22 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 206496 kb
Host smart-882c139d-da19-4cad-9f41-f18b8b236dbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371218742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.371218742
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2080063170
Short name T1101
Test name
Test status
Simulation time 11930145 ps
CPU time 0.86 seconds
Started Jul 24 05:53:26 PM PDT 24
Finished Jul 24 05:53:27 PM PDT 24
Peak memory 206532 kb
Host smart-dbd201c2-c8c5-4feb-bab0-04cc174d7cfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080063170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2080063170
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.750208959
Short name T1069
Test name
Test status
Simulation time 365121308 ps
CPU time 1.53 seconds
Started Jul 24 05:53:22 PM PDT 24
Finished Jul 24 05:53:24 PM PDT 24
Peak memory 206664 kb
Host smart-6e146a76-73a2-41d6-a580-01649169a38f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750208959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.750208959
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2565813955
Short name T999
Test name
Test status
Simulation time 49991613 ps
CPU time 3.22 seconds
Started Jul 24 05:53:29 PM PDT 24
Finished Jul 24 05:53:32 PM PDT 24
Peak memory 214820 kb
Host smart-9c4a62b4-a2c5-4bf4-9801-660fe92d3336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565813955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2565813955
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3270327289
Short name T1042
Test name
Test status
Simulation time 630776993 ps
CPU time 1.69 seconds
Started Jul 24 05:53:21 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 206588 kb
Host smart-6551ea81-8d6c-4bb4-8b59-a3d3dbf63e3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270327289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3270327289
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3471443595
Short name T1083
Test name
Test status
Simulation time 14143931 ps
CPU time 0.92 seconds
Started Jul 24 05:53:47 PM PDT 24
Finished Jul 24 05:53:48 PM PDT 24
Peak memory 206460 kb
Host smart-73f0392f-f052-4a8b-a049-491fe2f4bd02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471443595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3471443595
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2461906272
Short name T1081
Test name
Test status
Simulation time 70052271 ps
CPU time 0.83 seconds
Started Jul 24 05:53:45 PM PDT 24
Finished Jul 24 05:53:47 PM PDT 24
Peak memory 206320 kb
Host smart-a2d197cd-2806-4c14-a431-92bc36a0e719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461906272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2461906272
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2937318334
Short name T1009
Test name
Test status
Simulation time 19696053 ps
CPU time 0.79 seconds
Started Jul 24 05:53:43 PM PDT 24
Finished Jul 24 05:53:44 PM PDT 24
Peak memory 206504 kb
Host smart-7f48e554-d30e-45c4-9701-ecc092132448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937318334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2937318334
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.63692016
Short name T1127
Test name
Test status
Simulation time 14688621 ps
CPU time 0.87 seconds
Started Jul 24 05:53:44 PM PDT 24
Finished Jul 24 05:53:45 PM PDT 24
Peak memory 206496 kb
Host smart-3e26578b-1665-4be6-b20d-47a647890963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63692016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.63692016
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2050370486
Short name T1106
Test name
Test status
Simulation time 101366485 ps
CPU time 0.89 seconds
Started Jul 24 05:53:46 PM PDT 24
Finished Jul 24 05:53:47 PM PDT 24
Peak memory 206484 kb
Host smart-7981c16a-ca5b-497a-897e-ecb0acd84eb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050370486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2050370486
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2028934288
Short name T1044
Test name
Test status
Simulation time 14570345 ps
CPU time 0.89 seconds
Started Jul 24 05:53:45 PM PDT 24
Finished Jul 24 05:53:47 PM PDT 24
Peak memory 206444 kb
Host smart-a582e5ba-067e-47de-9b1f-cad44e661cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028934288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2028934288
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2405212599
Short name T1031
Test name
Test status
Simulation time 16685614 ps
CPU time 0.98 seconds
Started Jul 24 05:53:50 PM PDT 24
Finished Jul 24 05:53:51 PM PDT 24
Peak memory 206488 kb
Host smart-0d4f0b20-a064-4836-98c1-383915baa149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405212599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2405212599
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2683902853
Short name T1116
Test name
Test status
Simulation time 45386303 ps
CPU time 0.87 seconds
Started Jul 24 05:53:49 PM PDT 24
Finished Jul 24 05:53:50 PM PDT 24
Peak memory 206488 kb
Host smart-41c3461e-a378-47c0-9ac8-6718e41ed239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683902853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2683902853
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2838426431
Short name T1032
Test name
Test status
Simulation time 43599781 ps
CPU time 0.93 seconds
Started Jul 24 05:53:48 PM PDT 24
Finished Jul 24 05:53:50 PM PDT 24
Peak memory 206504 kb
Host smart-2db14311-8f3a-4d74-88b7-c19eabc26ddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838426431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2838426431
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2076942749
Short name T1076
Test name
Test status
Simulation time 14231375 ps
CPU time 0.89 seconds
Started Jul 24 05:53:50 PM PDT 24
Finished Jul 24 05:53:51 PM PDT 24
Peak memory 206468 kb
Host smart-36d05b6d-e2c6-4e88-8f7e-dcb41109493f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076942749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2076942749
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1868932794
Short name T263
Test name
Test status
Simulation time 90271054 ps
CPU time 1.21 seconds
Started Jul 24 05:53:22 PM PDT 24
Finished Jul 24 05:53:24 PM PDT 24
Peak memory 206568 kb
Host smart-5543c3db-f3ce-4d3d-87a7-73c27774aeec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868932794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1868932794
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2337494385
Short name T1016
Test name
Test status
Simulation time 140007667 ps
CPU time 3.49 seconds
Started Jul 24 05:53:20 PM PDT 24
Finished Jul 24 05:53:24 PM PDT 24
Peak memory 206452 kb
Host smart-b0df702e-df0f-4baf-8cca-aaf3fe4886d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337494385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2337494385
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.806928992
Short name T1018
Test name
Test status
Simulation time 26084360 ps
CPU time 0.93 seconds
Started Jul 24 05:53:27 PM PDT 24
Finished Jul 24 05:53:28 PM PDT 24
Peak memory 206476 kb
Host smart-d9828b0e-5e70-46f6-9c13-4d4d07ea7d48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806928992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.806928992
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1686605889
Short name T1119
Test name
Test status
Simulation time 86828523 ps
CPU time 1.57 seconds
Started Jul 24 05:53:29 PM PDT 24
Finished Jul 24 05:53:30 PM PDT 24
Peak memory 214756 kb
Host smart-ecca2635-ce56-45b4-9e0f-d9ba207ed201
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686605889 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1686605889
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.26340750
Short name T1011
Test name
Test status
Simulation time 14287818 ps
CPU time 0.92 seconds
Started Jul 24 05:53:22 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 206504 kb
Host smart-48f9e3ba-2af7-4ab1-a1b8-42e550ab33e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26340750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.26340750
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.4265209752
Short name T1006
Test name
Test status
Simulation time 137554967 ps
CPU time 0.95 seconds
Started Jul 24 05:53:22 PM PDT 24
Finished Jul 24 05:53:24 PM PDT 24
Peak memory 206468 kb
Host smart-fbcf2fd3-50c1-4a4d-ba82-ad6ace1f34b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265209752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.4265209752
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1022538936
Short name T1099
Test name
Test status
Simulation time 29693600 ps
CPU time 0.96 seconds
Started Jul 24 05:53:32 PM PDT 24
Finished Jul 24 05:53:33 PM PDT 24
Peak memory 206540 kb
Host smart-b95ace13-df91-4547-8b58-52da7b980bd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022538936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1022538936
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3817149039
Short name T1093
Test name
Test status
Simulation time 281674095 ps
CPU time 2.75 seconds
Started Jul 24 05:53:29 PM PDT 24
Finished Jul 24 05:53:32 PM PDT 24
Peak memory 214816 kb
Host smart-659a5d56-20af-4c99-a583-ff1217989903
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817149039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3817149039
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1977373139
Short name T1059
Test name
Test status
Simulation time 88309575 ps
CPU time 1.6 seconds
Started Jul 24 05:53:26 PM PDT 24
Finished Jul 24 05:53:27 PM PDT 24
Peak memory 206584 kb
Host smart-5355decf-b8f9-4382-a545-0b91a31a4a73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977373139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1977373139
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1299872042
Short name T995
Test name
Test status
Simulation time 28270825 ps
CPU time 0.93 seconds
Started Jul 24 05:53:56 PM PDT 24
Finished Jul 24 05:53:57 PM PDT 24
Peak memory 206500 kb
Host smart-b5b68919-bd4b-4646-9a4a-179c842c984b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299872042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1299872042
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1868962312
Short name T1074
Test name
Test status
Simulation time 19329265 ps
CPU time 0.84 seconds
Started Jul 24 05:53:51 PM PDT 24
Finished Jul 24 05:53:52 PM PDT 24
Peak memory 206276 kb
Host smart-fa257527-6220-41dc-8b2d-7553b1fca2a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868962312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1868962312
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2313612309
Short name T1025
Test name
Test status
Simulation time 50708481 ps
CPU time 0.87 seconds
Started Jul 24 05:53:52 PM PDT 24
Finished Jul 24 05:53:53 PM PDT 24
Peak memory 206460 kb
Host smart-255f3890-9c56-48bb-b2b8-130a28aa9c65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313612309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2313612309
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.4075317418
Short name T1072
Test name
Test status
Simulation time 10693001 ps
CPU time 0.87 seconds
Started Jul 24 05:53:50 PM PDT 24
Finished Jul 24 05:53:51 PM PDT 24
Peak memory 206488 kb
Host smart-230d5bd3-c8a3-4951-ad50-41a7654f95a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075317418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.4075317418
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1485896249
Short name T1058
Test name
Test status
Simulation time 14480456 ps
CPU time 0.88 seconds
Started Jul 24 05:53:48 PM PDT 24
Finished Jul 24 05:53:50 PM PDT 24
Peak memory 206620 kb
Host smart-92e534dc-de03-458b-aa84-63284866e1ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485896249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1485896249
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2565926809
Short name T1003
Test name
Test status
Simulation time 12411402 ps
CPU time 0.84 seconds
Started Jul 24 05:53:50 PM PDT 24
Finished Jul 24 05:53:51 PM PDT 24
Peak memory 206468 kb
Host smart-5f3adf58-7a13-4d1e-a3e4-db00cdbb5d3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565926809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2565926809
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3873910055
Short name T1060
Test name
Test status
Simulation time 15117952 ps
CPU time 0.92 seconds
Started Jul 24 05:53:50 PM PDT 24
Finished Jul 24 05:53:51 PM PDT 24
Peak memory 206532 kb
Host smart-c3ff4425-bc31-4e51-bfa0-5c36c026470e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873910055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3873910055
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.227540152
Short name T1086
Test name
Test status
Simulation time 31746473 ps
CPU time 0.77 seconds
Started Jul 24 05:53:48 PM PDT 24
Finished Jul 24 05:53:49 PM PDT 24
Peak memory 206280 kb
Host smart-052f23d2-bbd8-4999-9271-ca1f9ba6790f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227540152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.227540152
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.661004590
Short name T1000
Test name
Test status
Simulation time 99053827 ps
CPU time 0.86 seconds
Started Jul 24 05:53:48 PM PDT 24
Finished Jul 24 05:53:49 PM PDT 24
Peak memory 206468 kb
Host smart-99f697c9-2226-4d8c-b1da-d60959d98bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661004590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.661004590
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.199778760
Short name T1012
Test name
Test status
Simulation time 11756683 ps
CPU time 0.85 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:53:58 PM PDT 24
Peak memory 206492 kb
Host smart-ef2456f5-2673-448c-91db-b6979ec1e27f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199778760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.199778760
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2780106599
Short name T259
Test name
Test status
Simulation time 146636097 ps
CPU time 0.98 seconds
Started Jul 24 05:53:33 PM PDT 24
Finished Jul 24 05:53:34 PM PDT 24
Peak memory 206460 kb
Host smart-1ca33a05-f994-4a3d-88f1-9b8482f32f6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780106599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2780106599
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2866289119
Short name T261
Test name
Test status
Simulation time 61424821 ps
CPU time 3.28 seconds
Started Jul 24 05:53:35 PM PDT 24
Finished Jul 24 05:53:39 PM PDT 24
Peak memory 206476 kb
Host smart-d23d8f6a-28bf-43a7-91c6-8a8bec8034b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866289119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2866289119
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1007508822
Short name T251
Test name
Test status
Simulation time 72335525 ps
CPU time 0.97 seconds
Started Jul 24 05:53:32 PM PDT 24
Finished Jul 24 05:53:33 PM PDT 24
Peak memory 206440 kb
Host smart-177ddc03-7a71-4cea-8ca3-a9dc9027529f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007508822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1007508822
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.844494676
Short name T1064
Test name
Test status
Simulation time 35021812 ps
CPU time 1.19 seconds
Started Jul 24 05:53:31 PM PDT 24
Finished Jul 24 05:53:32 PM PDT 24
Peak memory 214820 kb
Host smart-6aeda95b-a7e9-4c00-a71d-6348acdd7791
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844494676 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.844494676
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3476862130
Short name T1124
Test name
Test status
Simulation time 112993090 ps
CPU time 0.94 seconds
Started Jul 24 05:53:34 PM PDT 24
Finished Jul 24 05:53:35 PM PDT 24
Peak memory 206436 kb
Host smart-330a30b2-29e9-40b3-b144-b1d1d7820268
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476862130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3476862130
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2076305074
Short name T1050
Test name
Test status
Simulation time 16570326 ps
CPU time 0.88 seconds
Started Jul 24 05:53:27 PM PDT 24
Finished Jul 24 05:53:28 PM PDT 24
Peak memory 206528 kb
Host smart-c90f9048-5d69-4d7e-a4b1-6016a66becb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076305074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2076305074
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2300143679
Short name T1121
Test name
Test status
Simulation time 38684846 ps
CPU time 1.5 seconds
Started Jul 24 05:53:34 PM PDT 24
Finished Jul 24 05:53:35 PM PDT 24
Peak memory 206592 kb
Host smart-b7695f50-4c58-4dbb-8f92-bc875ed0e728
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300143679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2300143679
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3465122812
Short name T1055
Test name
Test status
Simulation time 31664729 ps
CPU time 2.24 seconds
Started Jul 24 05:53:22 PM PDT 24
Finished Jul 24 05:53:25 PM PDT 24
Peak memory 214876 kb
Host smart-a98974ab-ff54-4a7c-a34f-ab266bf3710a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465122812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3465122812
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2091128603
Short name T1038
Test name
Test status
Simulation time 109549857 ps
CPU time 2.51 seconds
Started Jul 24 05:53:23 PM PDT 24
Finished Jul 24 05:53:25 PM PDT 24
Peak memory 206612 kb
Host smart-f955d7b5-088e-4b8f-b92b-fd7ba5243c30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091128603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2091128603
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1136893994
Short name T1040
Test name
Test status
Simulation time 15801239 ps
CPU time 0.92 seconds
Started Jul 24 05:53:48 PM PDT 24
Finished Jul 24 05:53:49 PM PDT 24
Peak memory 206556 kb
Host smart-35a94e97-2abe-4f28-ac7d-ac270c7eeef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136893994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1136893994
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.4293070466
Short name T1033
Test name
Test status
Simulation time 58281388 ps
CPU time 0.91 seconds
Started Jul 24 05:53:50 PM PDT 24
Finished Jul 24 05:53:51 PM PDT 24
Peak memory 206484 kb
Host smart-ecf9e543-0c93-4865-9d8b-e9bb8e2de196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293070466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.4293070466
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3879677852
Short name T1108
Test name
Test status
Simulation time 51062054 ps
CPU time 0.75 seconds
Started Jul 24 05:53:54 PM PDT 24
Finished Jul 24 05:53:55 PM PDT 24
Peak memory 206308 kb
Host smart-8034c3da-ce86-4c14-9e82-135fc6873061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879677852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3879677852
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3232641631
Short name T1030
Test name
Test status
Simulation time 14843338 ps
CPU time 1.01 seconds
Started Jul 24 05:53:55 PM PDT 24
Finished Jul 24 05:53:56 PM PDT 24
Peak memory 206484 kb
Host smart-190e03b8-c1f8-40b5-9b05-b45f43f7fc8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232641631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3232641631
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1479475667
Short name T1112
Test name
Test status
Simulation time 46970358 ps
CPU time 0.81 seconds
Started Jul 24 05:53:50 PM PDT 24
Finished Jul 24 05:53:51 PM PDT 24
Peak memory 206304 kb
Host smart-7aea6e23-9169-43c2-8365-75068ef82c25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479475667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1479475667
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3907837297
Short name T1035
Test name
Test status
Simulation time 18105676 ps
CPU time 0.88 seconds
Started Jul 24 05:53:52 PM PDT 24
Finished Jul 24 05:53:53 PM PDT 24
Peak memory 206460 kb
Host smart-cd17daa3-f6cd-4e02-aab9-7d95a4e617c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907837297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3907837297
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1504223494
Short name T1020
Test name
Test status
Simulation time 15395189 ps
CPU time 0.92 seconds
Started Jul 24 05:53:57 PM PDT 24
Finished Jul 24 05:53:58 PM PDT 24
Peak memory 206500 kb
Host smart-a9447e32-ad4f-48c0-8124-88a228c9b8d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504223494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1504223494
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2034196342
Short name T998
Test name
Test status
Simulation time 25003277 ps
CPU time 0.85 seconds
Started Jul 24 05:53:55 PM PDT 24
Finished Jul 24 05:53:56 PM PDT 24
Peak memory 206496 kb
Host smart-eceafbaa-771e-420e-9815-d2fb9a1c5397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034196342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2034196342
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.4055289949
Short name T1039
Test name
Test status
Simulation time 119568868 ps
CPU time 0.82 seconds
Started Jul 24 05:53:48 PM PDT 24
Finished Jul 24 05:53:49 PM PDT 24
Peak memory 206260 kb
Host smart-86e3457b-9f12-48a9-9981-9c2e09ab8025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055289949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.4055289949
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1912507934
Short name T1118
Test name
Test status
Simulation time 15444675 ps
CPU time 0.88 seconds
Started Jul 24 05:53:48 PM PDT 24
Finished Jul 24 05:53:49 PM PDT 24
Peak memory 206496 kb
Host smart-c62e242e-1521-4201-9da0-1ac196a4c0e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912507934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1912507934
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1260374856
Short name T1110
Test name
Test status
Simulation time 48451804 ps
CPU time 1.57 seconds
Started Jul 24 05:53:31 PM PDT 24
Finished Jul 24 05:53:33 PM PDT 24
Peak memory 214880 kb
Host smart-587989e2-20d8-49cd-beab-15e5f58b2dae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260374856 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1260374856
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2185484722
Short name T1073
Test name
Test status
Simulation time 15148093 ps
CPU time 0.89 seconds
Started Jul 24 05:53:28 PM PDT 24
Finished Jul 24 05:53:29 PM PDT 24
Peak memory 206492 kb
Host smart-3db968bc-c61d-4d29-8d3e-72da9152d19c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185484722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2185484722
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2584968668
Short name T1005
Test name
Test status
Simulation time 11099531 ps
CPU time 0.84 seconds
Started Jul 24 05:53:29 PM PDT 24
Finished Jul 24 05:53:30 PM PDT 24
Peak memory 206460 kb
Host smart-dc87b2e4-e850-43c5-87cb-45a5959b96db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584968668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2584968668
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3558669770
Short name T1120
Test name
Test status
Simulation time 17063438 ps
CPU time 0.98 seconds
Started Jul 24 05:53:31 PM PDT 24
Finished Jul 24 05:53:32 PM PDT 24
Peak memory 206624 kb
Host smart-e4ef74c8-4900-4810-96a1-7996707ff8c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558669770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3558669770
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1979421892
Short name T1102
Test name
Test status
Simulation time 251056114 ps
CPU time 2.36 seconds
Started Jul 24 05:53:27 PM PDT 24
Finished Jul 24 05:53:29 PM PDT 24
Peak memory 214872 kb
Host smart-4d47f2c3-f82d-4ce0-9902-8084dc530ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979421892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1979421892
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.342827072
Short name T284
Test name
Test status
Simulation time 232145230 ps
CPU time 4.56 seconds
Started Jul 24 05:53:31 PM PDT 24
Finished Jul 24 05:53:36 PM PDT 24
Peak memory 206500 kb
Host smart-865cc095-1bc3-4957-9a68-8e0fa25ff2f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342827072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.342827072
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1024731921
Short name T1027
Test name
Test status
Simulation time 152656870 ps
CPU time 1.33 seconds
Started Jul 24 05:53:33 PM PDT 24
Finished Jul 24 05:53:34 PM PDT 24
Peak memory 214792 kb
Host smart-c9611033-0d0b-4023-ab60-57d271ef27f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024731921 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1024731921
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.447286387
Short name T1123
Test name
Test status
Simulation time 16214730 ps
CPU time 1.01 seconds
Started Jul 24 05:53:29 PM PDT 24
Finished Jul 24 05:53:30 PM PDT 24
Peak memory 206504 kb
Host smart-36234317-6c6d-470f-a260-a85bd850b3a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447286387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.447286387
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1258016246
Short name T1095
Test name
Test status
Simulation time 42352417 ps
CPU time 0.83 seconds
Started Jul 24 05:53:29 PM PDT 24
Finished Jul 24 05:53:30 PM PDT 24
Peak memory 206316 kb
Host smart-5957a517-1b6a-47cb-83ac-5c84dd085bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258016246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1258016246
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.687154488
Short name T266
Test name
Test status
Simulation time 25196793 ps
CPU time 1.18 seconds
Started Jul 24 05:53:30 PM PDT 24
Finished Jul 24 05:53:32 PM PDT 24
Peak memory 206596 kb
Host smart-ce267360-aaf4-44f9-8e16-86bd07e3c7db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687154488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.687154488
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3174910008
Short name T1103
Test name
Test status
Simulation time 52871483 ps
CPU time 1.99 seconds
Started Jul 24 05:53:27 PM PDT 24
Finished Jul 24 05:53:29 PM PDT 24
Peak memory 214908 kb
Host smart-91aeed19-1eab-4275-823a-2846133a35ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174910008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3174910008
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1891113522
Short name T1061
Test name
Test status
Simulation time 100357298 ps
CPU time 2.5 seconds
Started Jul 24 05:53:32 PM PDT 24
Finished Jul 24 05:53:34 PM PDT 24
Peak memory 206668 kb
Host smart-a5bc7d55-2c20-4b36-9203-3a8449e8489a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891113522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1891113522
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3942185250
Short name T1021
Test name
Test status
Simulation time 13884997 ps
CPU time 0.99 seconds
Started Jul 24 05:53:35 PM PDT 24
Finished Jul 24 05:53:36 PM PDT 24
Peak memory 206608 kb
Host smart-8a3ed82c-d620-4a06-96f8-995acc9d61c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942185250 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3942185250
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3535115363
Short name T258
Test name
Test status
Simulation time 23562084 ps
CPU time 1.02 seconds
Started Jul 24 05:53:32 PM PDT 24
Finished Jul 24 05:53:33 PM PDT 24
Peak memory 206416 kb
Host smart-beaaef72-8c0a-46ff-a6fb-8f7666235aef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535115363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3535115363
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.17410268
Short name T1047
Test name
Test status
Simulation time 19028117 ps
CPU time 0.83 seconds
Started Jul 24 05:53:35 PM PDT 24
Finished Jul 24 05:53:36 PM PDT 24
Peak memory 206304 kb
Host smart-a3d8aefe-5e56-4488-9347-02ae9d7d2d2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17410268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.17410268
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.492716053
Short name T272
Test name
Test status
Simulation time 56672306 ps
CPU time 1.44 seconds
Started Jul 24 05:53:34 PM PDT 24
Finished Jul 24 05:53:35 PM PDT 24
Peak memory 206484 kb
Host smart-de8eae26-7edf-4b3c-a265-5e9775e87473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492716053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.492716053
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3140284416
Short name T1045
Test name
Test status
Simulation time 28946492 ps
CPU time 2.23 seconds
Started Jul 24 05:53:28 PM PDT 24
Finished Jul 24 05:53:30 PM PDT 24
Peak memory 214764 kb
Host smart-f1368768-9cdf-4ef9-a099-b5374b3711ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140284416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3140284416
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1298924914
Short name T275
Test name
Test status
Simulation time 313744350 ps
CPU time 2.03 seconds
Started Jul 24 05:53:35 PM PDT 24
Finished Jul 24 05:53:37 PM PDT 24
Peak memory 206628 kb
Host smart-9f907003-20da-41d9-9552-c98e1ffdb395
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298924914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1298924914
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2336605999
Short name T1079
Test name
Test status
Simulation time 131680348 ps
CPU time 1.03 seconds
Started Jul 24 05:53:37 PM PDT 24
Finished Jul 24 05:53:38 PM PDT 24
Peak memory 206588 kb
Host smart-205b2481-64ee-47de-8d1b-4e50ef7beda1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336605999 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2336605999
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2086642056
Short name T1082
Test name
Test status
Simulation time 18529955 ps
CPU time 0.92 seconds
Started Jul 24 05:53:36 PM PDT 24
Finished Jul 24 05:53:37 PM PDT 24
Peak memory 206476 kb
Host smart-bef418cf-9699-4ad3-bdf1-39d9d43f8505
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086642056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2086642056
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3151957210
Short name T1114
Test name
Test status
Simulation time 16026632 ps
CPU time 0.89 seconds
Started Jul 24 05:53:28 PM PDT 24
Finished Jul 24 05:53:29 PM PDT 24
Peak memory 206472 kb
Host smart-6c3298f9-20d6-49e0-8bac-4655977bf44b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151957210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3151957210
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2014568617
Short name T270
Test name
Test status
Simulation time 97988054 ps
CPU time 1.01 seconds
Started Jul 24 05:53:29 PM PDT 24
Finished Jul 24 05:53:30 PM PDT 24
Peak memory 206564 kb
Host smart-039d085d-4811-4019-b1f9-8ea07f6f6d29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014568617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2014568617
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3749046714
Short name T1068
Test name
Test status
Simulation time 21785346 ps
CPU time 1.61 seconds
Started Jul 24 05:53:31 PM PDT 24
Finished Jul 24 05:53:33 PM PDT 24
Peak memory 214868 kb
Host smart-61265ecb-87fc-40c3-8d29-b466a51d18e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749046714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3749046714
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1660676002
Short name T287
Test name
Test status
Simulation time 85050244 ps
CPU time 1.67 seconds
Started Jul 24 05:53:35 PM PDT 24
Finished Jul 24 05:53:37 PM PDT 24
Peak memory 206588 kb
Host smart-a3070ce7-66e1-4c1e-a581-d274a75c6920
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660676002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1660676002
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.480096073
Short name T996
Test name
Test status
Simulation time 23429974 ps
CPU time 1.24 seconds
Started Jul 24 05:53:33 PM PDT 24
Finished Jul 24 05:53:34 PM PDT 24
Peak memory 223048 kb
Host smart-79c2af87-6924-4c66-8acc-4a1df0e8a4ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480096073 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.480096073
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3714658586
Short name T268
Test name
Test status
Simulation time 32835268 ps
CPU time 0.88 seconds
Started Jul 24 05:53:38 PM PDT 24
Finished Jul 24 05:53:39 PM PDT 24
Peak memory 206256 kb
Host smart-f93468e2-93ae-4702-949b-95d597fb0bc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714658586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3714658586
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2206869712
Short name T1067
Test name
Test status
Simulation time 18567737 ps
CPU time 0.81 seconds
Started Jul 24 05:53:34 PM PDT 24
Finished Jul 24 05:53:35 PM PDT 24
Peak memory 206296 kb
Host smart-c26028ae-f6a5-421b-a0db-872a6dc71c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206869712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2206869712
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.430478240
Short name T1104
Test name
Test status
Simulation time 83474831 ps
CPU time 1.05 seconds
Started Jul 24 05:53:35 PM PDT 24
Finished Jul 24 05:53:36 PM PDT 24
Peak memory 206612 kb
Host smart-2a3de993-43d0-4ae8-9b75-4b9957596dfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430478240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.430478240
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.887963576
Short name T1057
Test name
Test status
Simulation time 26005287 ps
CPU time 1.7 seconds
Started Jul 24 05:53:29 PM PDT 24
Finished Jul 24 05:53:31 PM PDT 24
Peak memory 214840 kb
Host smart-2698f479-dd38-4096-a460-630a1c720952
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887963576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.887963576
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.704891481
Short name T285
Test name
Test status
Simulation time 554307435 ps
CPU time 2.62 seconds
Started Jul 24 05:53:35 PM PDT 24
Finished Jul 24 05:53:38 PM PDT 24
Peak memory 206904 kb
Host smart-03d42bca-fa18-42ca-9f92-a42eb5feda9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704891481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.704891481
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1753626814
Short name T278
Test name
Test status
Simulation time 183832427 ps
CPU time 1.18 seconds
Started Jul 24 05:59:51 PM PDT 24
Finished Jul 24 05:59:52 PM PDT 24
Peak memory 220456 kb
Host smart-02db1ac1-2cdb-4d17-8e1c-71221ec836fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753626814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1753626814
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.803064721
Short name T705
Test name
Test status
Simulation time 29362083 ps
CPU time 0.91 seconds
Started Jul 24 05:59:49 PM PDT 24
Finished Jul 24 05:59:50 PM PDT 24
Peak memory 206984 kb
Host smart-fd4973cf-07e8-4c76-9074-ed8ec4f241ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803064721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.803064721
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3982083181
Short name T212
Test name
Test status
Simulation time 84003935 ps
CPU time 0.89 seconds
Started Jul 24 05:59:57 PM PDT 24
Finished Jul 24 05:59:58 PM PDT 24
Peak memory 215788 kb
Host smart-9c136133-3c4f-487d-b93a-29443418cdcc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982083181 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3982083181
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.3275223648
Short name T400
Test name
Test status
Simulation time 34933786 ps
CPU time 1.13 seconds
Started Jul 24 05:59:55 PM PDT 24
Finished Jul 24 05:59:56 PM PDT 24
Peak memory 220292 kb
Host smart-5c31c562-c0f1-4bef-a9d6-765868202cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275223648 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3275223648
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.2690259468
Short name T441
Test name
Test status
Simulation time 80297717 ps
CPU time 0.97 seconds
Started Jul 24 05:59:49 PM PDT 24
Finished Jul 24 05:59:50 PM PDT 24
Peak memory 224156 kb
Host smart-208351c5-1ba0-466b-b38b-220f4a77521b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690259468 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2690259468
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3478543079
Short name T740
Test name
Test status
Simulation time 46765658 ps
CPU time 0.89 seconds
Started Jul 24 05:59:50 PM PDT 24
Finished Jul 24 05:59:51 PM PDT 24
Peak memory 207412 kb
Host smart-e0507fbf-c745-400c-8079-280bd82eefa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478543079 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3478543079
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.701449367
Short name T68
Test name
Test status
Simulation time 59621061 ps
CPU time 1.03 seconds
Started Jul 24 05:59:50 PM PDT 24
Finished Jul 24 05:59:51 PM PDT 24
Peak memory 215644 kb
Host smart-2aefb1c9-46cc-470c-bf25-5b7f45440b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701449367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.701449367
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1712965388
Short name T459
Test name
Test status
Simulation time 229934027 ps
CPU time 4.63 seconds
Started Jul 24 05:59:48 PM PDT 24
Finished Jul 24 05:59:53 PM PDT 24
Peak memory 217540 kb
Host smart-ed95cef1-d9b6-4f95-a995-b01b0cf2ec52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712965388 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1712965388
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.3118546024
Short name T298
Test name
Test status
Simulation time 104284488 ps
CPU time 1.27 seconds
Started Jul 24 05:59:48 PM PDT 24
Finished Jul 24 05:59:50 PM PDT 24
Peak memory 218872 kb
Host smart-7cbf9d95-03ac-4d37-9ff6-5fb72cd34cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118546024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3118546024
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.4194198145
Short name T612
Test name
Test status
Simulation time 15839723 ps
CPU time 0.92 seconds
Started Jul 24 05:59:51 PM PDT 24
Finished Jul 24 05:59:52 PM PDT 24
Peak memory 207016 kb
Host smart-1b040244-8b02-4e96-b95e-6053d7b6ce20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194198145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.4194198145
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_err.3572104883
Short name T778
Test name
Test status
Simulation time 28964031 ps
CPU time 0.86 seconds
Started Jul 24 05:59:52 PM PDT 24
Finished Jul 24 05:59:53 PM PDT 24
Peak memory 218304 kb
Host smart-c14375c2-f12b-4707-b633-56c1ea9573a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572104883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3572104883
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3612310791
Short name T424
Test name
Test status
Simulation time 49640286 ps
CPU time 1.39 seconds
Started Jul 24 05:59:48 PM PDT 24
Finished Jul 24 05:59:50 PM PDT 24
Peak memory 219132 kb
Host smart-523eecd8-7cd8-4023-a0f6-ca0850f80f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612310791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3612310791
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2333762398
Short name T50
Test name
Test status
Simulation time 29359437 ps
CPU time 1.04 seconds
Started Jul 24 05:59:51 PM PDT 24
Finished Jul 24 05:59:53 PM PDT 24
Peak memory 224324 kb
Host smart-30f56a1c-60fa-4a44-8bbf-005ce48bab5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333762398 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2333762398
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.2179846780
Short name T527
Test name
Test status
Simulation time 19515562 ps
CPU time 1 seconds
Started Jul 24 05:59:49 PM PDT 24
Finished Jul 24 05:59:50 PM PDT 24
Peak memory 207440 kb
Host smart-d3c30f12-c4e9-4782-934e-44549df40338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179846780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2179846780
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.772879601
Short name T60
Test name
Test status
Simulation time 882113175 ps
CPU time 4.13 seconds
Started Jul 24 05:59:57 PM PDT 24
Finished Jul 24 06:00:02 PM PDT 24
Peak memory 235548 kb
Host smart-427df2c1-24c6-4140-8cb0-9dd4555dcff2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772879601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.772879601
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1494570529
Short name T365
Test name
Test status
Simulation time 47446654 ps
CPU time 0.99 seconds
Started Jul 24 05:59:47 PM PDT 24
Finished Jul 24 05:59:49 PM PDT 24
Peak memory 215608 kb
Host smart-3a381703-d3c9-4756-882d-dabbc970f282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494570529 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1494570529
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1817595457
Short name T811
Test name
Test status
Simulation time 1285169636 ps
CPU time 3.96 seconds
Started Jul 24 05:59:52 PM PDT 24
Finished Jul 24 05:59:56 PM PDT 24
Peak memory 217552 kb
Host smart-662124c3-7d46-49f6-870e-5bffcd3661c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817595457 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1817595457
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2228390493
Short name T221
Test name
Test status
Simulation time 81208351945 ps
CPU time 1621.15 seconds
Started Jul 24 05:59:50 PM PDT 24
Finished Jul 24 06:26:52 PM PDT 24
Peak memory 227160 kb
Host smart-50d467a3-b4f7-4c0f-8ed8-51f1aa9b8aff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228390493 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2228390493
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.785967194
Short name T914
Test name
Test status
Simulation time 27704314 ps
CPU time 1.18 seconds
Started Jul 24 06:00:05 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 219980 kb
Host smart-aa9b8867-e4f8-48c4-8513-83d04fc2b222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785967194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.785967194
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2207693973
Short name T756
Test name
Test status
Simulation time 15510082 ps
CPU time 0.93 seconds
Started Jul 24 06:00:06 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 206972 kb
Host smart-62602f82-f0b6-4f68-b663-4ff68ae8b4ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207693973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2207693973
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.4006578483
Short name T189
Test name
Test status
Simulation time 33338319 ps
CPU time 0.81 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 216540 kb
Host smart-db9f42b1-512d-46ad-860e-1fc8566ff0e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006578483 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.4006578483
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.1107018017
Short name T960
Test name
Test status
Simulation time 28513895 ps
CPU time 0.87 seconds
Started Jul 24 06:00:06 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 218328 kb
Host smart-995b6a70-28ed-4266-9cd3-e456b554954f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107018017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1107018017
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3689686309
Short name T313
Test name
Test status
Simulation time 220309654 ps
CPU time 1.23 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:02 PM PDT 24
Peak memory 219184 kb
Host smart-156416e4-3bd8-4bd9-a7cc-1c4e091812da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689686309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3689686309
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.821932692
Short name T591
Test name
Test status
Simulation time 51932356 ps
CPU time 0.97 seconds
Started Jul 24 06:00:04 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 224144 kb
Host smart-55f91205-4a2f-496c-8293-9d88909a8398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821932692 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.821932692
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1922538612
Short name T707
Test name
Test status
Simulation time 67311494 ps
CPU time 0.93 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:02 PM PDT 24
Peak memory 215588 kb
Host smart-c7d5d665-5cf0-4898-8b85-68133b025025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922538612 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1922538612
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3806252842
Short name T672
Test name
Test status
Simulation time 316401457 ps
CPU time 5.63 seconds
Started Jul 24 05:59:59 PM PDT 24
Finished Jul 24 06:00:05 PM PDT 24
Peak memory 215672 kb
Host smart-1d3c3b86-7da4-488f-90ed-332d2a2979a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806252842 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3806252842
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2090412012
Short name T364
Test name
Test status
Simulation time 143919284799 ps
CPU time 873.17 seconds
Started Jul 24 06:00:03 PM PDT 24
Finished Jul 24 06:14:43 PM PDT 24
Peak memory 222132 kb
Host smart-8390deac-908b-4ee0-a335-679502343efa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090412012 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2090412012
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.2116081958
Short name T661
Test name
Test status
Simulation time 81287098 ps
CPU time 1.28 seconds
Started Jul 24 06:01:16 PM PDT 24
Finished Jul 24 06:01:18 PM PDT 24
Peak memory 220260 kb
Host smart-5fdc4325-d13a-4579-b2b5-e6588a51a487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116081958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2116081958
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.3491840048
Short name T803
Test name
Test status
Simulation time 49347106 ps
CPU time 1.8 seconds
Started Jul 24 06:01:18 PM PDT 24
Finished Jul 24 06:01:20 PM PDT 24
Peak memory 218848 kb
Host smart-ebbd7388-af75-4630-a391-9ccc7ab44967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491840048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3491840048
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.2552807341
Short name T501
Test name
Test status
Simulation time 36927591 ps
CPU time 1.14 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 218680 kb
Host smart-7ae7ed1c-80a1-4d97-81d8-1e39c8419085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552807341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2552807341
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.1936088698
Short name T753
Test name
Test status
Simulation time 41824268 ps
CPU time 1.69 seconds
Started Jul 24 06:01:19 PM PDT 24
Finished Jul 24 06:01:21 PM PDT 24
Peak memory 218768 kb
Host smart-04013aa8-d4af-476c-b2a5-29b156a4741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936088698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1936088698
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.739483506
Short name T508
Test name
Test status
Simulation time 60804433 ps
CPU time 1.27 seconds
Started Jul 24 06:01:15 PM PDT 24
Finished Jul 24 06:01:17 PM PDT 24
Peak memory 217612 kb
Host smart-69841ae2-4be1-4902-9856-ff3f384c6417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739483506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.739483506
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.477010909
Short name T841
Test name
Test status
Simulation time 66891884 ps
CPU time 1.1 seconds
Started Jul 24 06:01:17 PM PDT 24
Finished Jul 24 06:01:18 PM PDT 24
Peak memory 218988 kb
Host smart-aebc6d9c-44b0-4f3d-91b2-82f14113aa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477010909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.477010909
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.122671628
Short name T504
Test name
Test status
Simulation time 127843457 ps
CPU time 3.26 seconds
Started Jul 24 06:01:14 PM PDT 24
Finished Jul 24 06:01:18 PM PDT 24
Peak memory 219436 kb
Host smart-4b3c682d-e195-4a84-9014-49ed3ff98293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122671628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.122671628
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.1965782783
Short name T360
Test name
Test status
Simulation time 40188058 ps
CPU time 1.19 seconds
Started Jul 24 06:01:15 PM PDT 24
Finished Jul 24 06:01:17 PM PDT 24
Peak memory 219148 kb
Host smart-633758e8-a79a-42b4-8765-b6e441a6f6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965782783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1965782783
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.3469944587
Short name T483
Test name
Test status
Simulation time 62686704 ps
CPU time 1.45 seconds
Started Jul 24 06:01:18 PM PDT 24
Finished Jul 24 06:01:19 PM PDT 24
Peak memory 219060 kb
Host smart-03d64624-1e68-4a93-a68e-dd8e128ded32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469944587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3469944587
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.3168856536
Short name T620
Test name
Test status
Simulation time 165993707 ps
CPU time 3.4 seconds
Started Jul 24 06:01:14 PM PDT 24
Finished Jul 24 06:01:18 PM PDT 24
Peak memory 220540 kb
Host smart-4b060e7b-bcfa-4016-9cae-b1250d367dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168856536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3168856536
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.3506965728
Short name T472
Test name
Test status
Simulation time 41050395 ps
CPU time 1.27 seconds
Started Jul 24 06:01:31 PM PDT 24
Finished Jul 24 06:01:32 PM PDT 24
Peak memory 219676 kb
Host smart-abb9c58a-a1d1-44b9-bdaf-353cc4317587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506965728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3506965728
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.1331322367
Short name T686
Test name
Test status
Simulation time 39795338 ps
CPU time 1.51 seconds
Started Jul 24 06:01:13 PM PDT 24
Finished Jul 24 06:01:15 PM PDT 24
Peak memory 218576 kb
Host smart-4f8d9c47-40c5-46e6-bbd3-f8506d212a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331322367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1331322367
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.3651160313
Short name T216
Test name
Test status
Simulation time 39651761 ps
CPU time 1.49 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:29 PM PDT 24
Peak memory 222356 kb
Host smart-ed58c945-f2ed-466e-856b-e8792b907f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651160313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3651160313
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.2708206246
Short name T415
Test name
Test status
Simulation time 44660470 ps
CPU time 1.48 seconds
Started Jul 24 06:01:14 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 220208 kb
Host smart-e7516e9d-ea19-4276-8dab-bd356379b6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708206246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2708206246
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3235070845
Short name T74
Test name
Test status
Simulation time 66353918 ps
CPU time 1.09 seconds
Started Jul 24 06:01:23 PM PDT 24
Finished Jul 24 06:01:25 PM PDT 24
Peak memory 216072 kb
Host smart-c9006500-edd1-4d22-9e50-7af2b3f2ca73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235070845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3235070845
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.1871904202
Short name T863
Test name
Test status
Simulation time 60618927 ps
CPU time 1.18 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:29 PM PDT 24
Peak memory 219256 kb
Host smart-dd4158c9-5344-485e-aba7-e552347c8add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871904202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1871904202
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.4019902638
Short name T182
Test name
Test status
Simulation time 44278141 ps
CPU time 1.16 seconds
Started Jul 24 06:00:07 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 220180 kb
Host smart-a10d4c4f-9ee5-4d9c-89ac-6f9401a76642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019902638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.4019902638
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3260258407
Short name T728
Test name
Test status
Simulation time 41916013 ps
CPU time 0.85 seconds
Started Jul 24 06:00:13 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 206796 kb
Host smart-28d0247c-764d-41d1-bd12-b5813895e8d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260258407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3260258407
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_err.3351360309
Short name T8
Test name
Test status
Simulation time 24688429 ps
CPU time 1.29 seconds
Started Jul 24 06:00:10 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 224324 kb
Host smart-c160cb5a-66e8-4dd6-b1b9-39bffb75699f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351360309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3351360309
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1530865965
Short name T54
Test name
Test status
Simulation time 50375858 ps
CPU time 1.8 seconds
Started Jul 24 06:00:05 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 218868 kb
Host smart-4adce407-fb1e-4c8b-a3ce-e27df1a9cb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530865965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1530865965
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1945869657
Short name T787
Test name
Test status
Simulation time 36777469 ps
CPU time 0.91 seconds
Started Jul 24 06:00:05 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215760 kb
Host smart-4308eb45-2260-49e8-bd78-496b8284bbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945869657 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1945869657
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2197672923
Short name T986
Test name
Test status
Simulation time 16258277 ps
CPU time 1 seconds
Started Jul 24 06:00:08 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215624 kb
Host smart-cb95a5d6-6683-46cb-9fe9-389e082a1cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197672923 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2197672923
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3900771496
Short name T430
Test name
Test status
Simulation time 532041365 ps
CPU time 2.92 seconds
Started Jul 24 06:00:04 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 217612 kb
Host smart-3d7bd730-be01-43b7-85e4-d224d7d54ef2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900771496 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3900771496
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1255975569
Short name T975
Test name
Test status
Simulation time 374979042556 ps
CPU time 1343.19 seconds
Started Jul 24 06:00:04 PM PDT 24
Finished Jul 24 06:22:33 PM PDT 24
Peak memory 225644 kb
Host smart-ce382ab5-3346-4a68-afba-4b45600d8b7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255975569 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1255975569
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.4108642516
Short name T862
Test name
Test status
Simulation time 46743769 ps
CPU time 1.19 seconds
Started Jul 24 06:01:25 PM PDT 24
Finished Jul 24 06:01:27 PM PDT 24
Peak memory 218884 kb
Host smart-43820303-b43f-406a-949c-5e66351763bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108642516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.4108642516
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.2248280238
Short name T660
Test name
Test status
Simulation time 57232823 ps
CPU time 1.09 seconds
Started Jul 24 06:01:20 PM PDT 24
Finished Jul 24 06:01:21 PM PDT 24
Peak memory 219132 kb
Host smart-db74c417-7290-4bcc-a972-21ba09f7a17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248280238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2248280238
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.163535543
Short name T838
Test name
Test status
Simulation time 93816697 ps
CPU time 1.26 seconds
Started Jul 24 06:01:17 PM PDT 24
Finished Jul 24 06:01:19 PM PDT 24
Peak memory 219220 kb
Host smart-61aeb5bc-ed96-43c8-b796-dd40a0b5e0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163535543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.163535543
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.3764665151
Short name T896
Test name
Test status
Simulation time 99046118 ps
CPU time 1.25 seconds
Started Jul 24 06:01:31 PM PDT 24
Finished Jul 24 06:01:32 PM PDT 24
Peak memory 217800 kb
Host smart-d203445e-b684-43f4-b9c4-f6037e9f2423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764665151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3764665151
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3459866074
Short name T115
Test name
Test status
Simulation time 43744549 ps
CPU time 1.21 seconds
Started Jul 24 06:01:23 PM PDT 24
Finished Jul 24 06:01:25 PM PDT 24
Peak memory 220076 kb
Host smart-872fa2a6-9fee-4da6-a21a-4f9f860630c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459866074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3459866074
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3026567628
Short name T339
Test name
Test status
Simulation time 61413199 ps
CPU time 1.55 seconds
Started Jul 24 06:01:23 PM PDT 24
Finished Jul 24 06:01:25 PM PDT 24
Peak memory 218944 kb
Host smart-55156a4c-1001-461f-bedb-bf1dfcca0c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026567628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3026567628
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.4247419159
Short name T291
Test name
Test status
Simulation time 240661219 ps
CPU time 1.34 seconds
Started Jul 24 06:01:19 PM PDT 24
Finished Jul 24 06:01:21 PM PDT 24
Peak memory 219836 kb
Host smart-25678ca2-8f17-4814-8902-21b76f63ed44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247419159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.4247419159
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.3987972600
Short name T470
Test name
Test status
Simulation time 61652268 ps
CPU time 1.24 seconds
Started Jul 24 06:01:31 PM PDT 24
Finished Jul 24 06:01:32 PM PDT 24
Peak memory 217580 kb
Host smart-230b4130-7cb0-4c47-96a9-0c37b63d25e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987972600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3987972600
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.1692531354
Short name T359
Test name
Test status
Simulation time 118920460 ps
CPU time 1.53 seconds
Started Jul 24 06:01:14 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 217736 kb
Host smart-c26f1d6c-0cb9-4ba4-a169-9a1edc704c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692531354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1692531354
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.1995563878
Short name T142
Test name
Test status
Simulation time 92637311 ps
CPU time 1.33 seconds
Started Jul 24 06:01:16 PM PDT 24
Finished Jul 24 06:01:18 PM PDT 24
Peak memory 220256 kb
Host smart-d4438b54-5f6a-4960-a8ab-04f8e74d6180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995563878 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.1995563878
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.1107210710
Short name T23
Test name
Test status
Simulation time 145769054 ps
CPU time 3.29 seconds
Started Jul 24 06:01:28 PM PDT 24
Finished Jul 24 06:01:32 PM PDT 24
Peak memory 217792 kb
Host smart-d5eb7cf9-dbb9-4ac4-ae5c-3c8155f07a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107210710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1107210710
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.4256001331
Short name T645
Test name
Test status
Simulation time 79634592 ps
CPU time 1.22 seconds
Started Jul 24 06:01:19 PM PDT 24
Finished Jul 24 06:01:20 PM PDT 24
Peak memory 219412 kb
Host smart-35b2fc11-3b8f-4b33-a813-f1c224041338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256001331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.4256001331
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/117.edn_alert.1788050184
Short name T953
Test name
Test status
Simulation time 50284465 ps
CPU time 1.31 seconds
Started Jul 24 06:01:24 PM PDT 24
Finished Jul 24 06:01:25 PM PDT 24
Peak memory 216036 kb
Host smart-22da219b-9526-433c-8e81-5bbfdef4b84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788050184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1788050184
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/118.edn_alert.1326539344
Short name T895
Test name
Test status
Simulation time 24839146 ps
CPU time 1.18 seconds
Started Jul 24 06:01:22 PM PDT 24
Finished Jul 24 06:01:23 PM PDT 24
Peak memory 219016 kb
Host smart-e20fd535-ce68-4188-856f-577f5c8a7328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326539344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1326539344
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.3578361207
Short name T65
Test name
Test status
Simulation time 55981325 ps
CPU time 1.53 seconds
Started Jul 24 06:01:29 PM PDT 24
Finished Jul 24 06:01:30 PM PDT 24
Peak memory 218880 kb
Host smart-8a090b57-39f3-4fcf-9fc8-b63a5a63e8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578361207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3578361207
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1044401452
Short name T584
Test name
Test status
Simulation time 25794614 ps
CPU time 1.21 seconds
Started Jul 24 06:01:13 PM PDT 24
Finished Jul 24 06:01:14 PM PDT 24
Peak memory 218944 kb
Host smart-241ba137-9ada-4d54-85f2-e81667f88a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044401452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1044401452
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.2399841432
Short name T957
Test name
Test status
Simulation time 55045901 ps
CPU time 1.31 seconds
Started Jul 24 06:01:33 PM PDT 24
Finished Jul 24 06:01:34 PM PDT 24
Peak memory 220376 kb
Host smart-aceee159-0284-49e7-a91c-cce8f5696357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399841432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2399841432
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.887403373
Short name T442
Test name
Test status
Simulation time 42186330 ps
CPU time 1.08 seconds
Started Jul 24 06:00:11 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 219972 kb
Host smart-e5382fdf-847f-448c-bf2f-c0f925185960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887403373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.887403373
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.712289372
Short name T613
Test name
Test status
Simulation time 50346181 ps
CPU time 1.01 seconds
Started Jul 24 06:00:11 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 215196 kb
Host smart-6088a697-57a9-4be8-9155-68cbd826bf8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712289372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.712289372
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2003452675
Short name T90
Test name
Test status
Simulation time 11484295 ps
CPU time 0.96 seconds
Started Jul 24 06:00:07 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215940 kb
Host smart-f3d2d9a3-692f-464b-8d4e-47e396e00f7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003452675 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2003452675
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.2832019736
Short name T585
Test name
Test status
Simulation time 138991095 ps
CPU time 1.33 seconds
Started Jul 24 06:00:05 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 225860 kb
Host smart-2136b801-2c57-476b-abee-2e0592403b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832019736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2832019736
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3374840202
Short name T496
Test name
Test status
Simulation time 61534692 ps
CPU time 1.48 seconds
Started Jul 24 06:00:06 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 220304 kb
Host smart-7ab2f188-3971-4d2c-919b-6152d37b86d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374840202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3374840202
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1797876407
Short name T664
Test name
Test status
Simulation time 22212716 ps
CPU time 1.11 seconds
Started Jul 24 06:00:09 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215780 kb
Host smart-2f6bd972-ddd4-4b12-a14e-dcc9ab4a6971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797876407 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1797876407
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1915689137
Short name T865
Test name
Test status
Simulation time 54344328 ps
CPU time 0.95 seconds
Started Jul 24 06:00:05 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215616 kb
Host smart-0630fc30-17be-491b-b735-6bb3803b67f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915689137 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1915689137
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.4289710631
Short name T698
Test name
Test status
Simulation time 2314359511 ps
CPU time 3.82 seconds
Started Jul 24 06:00:05 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 215792 kb
Host smart-810e5716-3854-49c2-b9b0-4d8c85f80cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289710631 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.4289710631
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.747497713
Short name T228
Test name
Test status
Simulation time 32582745639 ps
CPU time 350.66 seconds
Started Jul 24 06:00:08 PM PDT 24
Finished Jul 24 06:06:01 PM PDT 24
Peak memory 218808 kb
Host smart-e6bc39e9-ef9f-4411-913c-931369c7f11a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747497713 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.747497713
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.3255143046
Short name T972
Test name
Test status
Simulation time 85152901 ps
CPU time 1.12 seconds
Started Jul 24 06:01:16 PM PDT 24
Finished Jul 24 06:01:18 PM PDT 24
Peak memory 219004 kb
Host smart-62d9e66d-4d98-44a1-8c80-387a3836d745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255143046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.3255143046
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.2648272724
Short name T626
Test name
Test status
Simulation time 82145935 ps
CPU time 1.42 seconds
Started Jul 24 06:01:32 PM PDT 24
Finished Jul 24 06:01:34 PM PDT 24
Peak memory 219184 kb
Host smart-f1f8564c-bb95-4c4e-acfe-2f5d73838ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648272724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2648272724
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.3566987713
Short name T214
Test name
Test status
Simulation time 121177535 ps
CPU time 1.18 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 219820 kb
Host smart-797f86c8-d588-4585-a75f-4203a383e1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566987713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3566987713
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.1874610078
Short name T304
Test name
Test status
Simulation time 58376855 ps
CPU time 1.15 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 217664 kb
Host smart-b805966f-3681-40cd-b5ff-8fca6909537a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874610078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1874610078
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.903229815
Short name T679
Test name
Test status
Simulation time 50214046 ps
CPU time 1.2 seconds
Started Jul 24 06:01:15 PM PDT 24
Finished Jul 24 06:01:17 PM PDT 24
Peak memory 220116 kb
Host smart-406df2a5-cd19-4d2d-b1cc-0b589ecdb803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903229815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.903229815
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/124.edn_alert.1732050437
Short name T816
Test name
Test status
Simulation time 37966123 ps
CPU time 1.25 seconds
Started Jul 24 06:01:21 PM PDT 24
Finished Jul 24 06:01:23 PM PDT 24
Peak memory 216036 kb
Host smart-4f8946d6-767c-496f-af15-6a048faf5103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732050437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.1732050437
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.475935484
Short name T767
Test name
Test status
Simulation time 54482113 ps
CPU time 1.28 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:29 PM PDT 24
Peak memory 218932 kb
Host smart-ac9e4eca-1679-4c6a-925d-8ee14c25551f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475935484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.475935484
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.3919754725
Short name T507
Test name
Test status
Simulation time 73040512 ps
CPU time 1.14 seconds
Started Jul 24 06:01:18 PM PDT 24
Finished Jul 24 06:01:20 PM PDT 24
Peak memory 219640 kb
Host smart-7c23e992-c4ae-4f65-863e-fa688ddaf433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919754725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3919754725
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.59692944
Short name T22
Test name
Test status
Simulation time 52964606 ps
CPU time 1.75 seconds
Started Jul 24 06:01:30 PM PDT 24
Finished Jul 24 06:01:32 PM PDT 24
Peak memory 220396 kb
Host smart-aa402654-acc5-4d3e-8634-71cbc798bec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59692944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.59692944
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.3180727618
Short name T250
Test name
Test status
Simulation time 73513579 ps
CPU time 1.19 seconds
Started Jul 24 06:01:21 PM PDT 24
Finished Jul 24 06:01:23 PM PDT 24
Peak memory 218960 kb
Host smart-0777eb8f-756f-413b-ace8-7d8ab561b302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180727618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3180727618
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.912038632
Short name T606
Test name
Test status
Simulation time 433259954 ps
CPU time 2.75 seconds
Started Jul 24 06:01:22 PM PDT 24
Finished Jul 24 06:01:25 PM PDT 24
Peak memory 217888 kb
Host smart-a8ebe212-53bf-4430-a51f-97ed46b839f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912038632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.912038632
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.3093298799
Short name T211
Test name
Test status
Simulation time 43737314 ps
CPU time 1.23 seconds
Started Jul 24 06:01:30 PM PDT 24
Finished Jul 24 06:01:31 PM PDT 24
Peak memory 220472 kb
Host smart-3f436b15-51f2-4fac-bb60-fb974ec086ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093298799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.3093298799
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/128.edn_alert.3470837027
Short name T967
Test name
Test status
Simulation time 39828697 ps
CPU time 1.2 seconds
Started Jul 24 06:01:17 PM PDT 24
Finished Jul 24 06:01:18 PM PDT 24
Peak memory 216056 kb
Host smart-e80f108a-94f3-4a37-a3ab-81eef1e7582c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470837027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3470837027
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.297614867
Short name T416
Test name
Test status
Simulation time 36824854 ps
CPU time 1.42 seconds
Started Jul 24 06:01:22 PM PDT 24
Finished Jul 24 06:01:23 PM PDT 24
Peak memory 217812 kb
Host smart-377ddfe7-394f-42fd-a5c9-87e53b51c250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297614867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.297614867
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.3003763891
Short name T169
Test name
Test status
Simulation time 64867974 ps
CPU time 1.16 seconds
Started Jul 24 06:01:24 PM PDT 24
Finished Jul 24 06:01:25 PM PDT 24
Peak memory 221884 kb
Host smart-194c847c-8e9b-4aff-ac6a-53f5252d91af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003763891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3003763891
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.586279109
Short name T538
Test name
Test status
Simulation time 50877787 ps
CPU time 1.21 seconds
Started Jul 24 06:01:21 PM PDT 24
Finished Jul 24 06:01:22 PM PDT 24
Peak memory 217580 kb
Host smart-f294474a-365d-4e31-97d6-1bf0bdc77fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586279109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.586279109
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.4064266367
Short name T279
Test name
Test status
Simulation time 54454750 ps
CPU time 1.35 seconds
Started Jul 24 06:00:04 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215984 kb
Host smart-b61f82a5-7ac6-409c-b09b-fcfd1cb76faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064266367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.4064266367
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.170657453
Short name T465
Test name
Test status
Simulation time 26599080 ps
CPU time 1.14 seconds
Started Jul 24 06:00:03 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215408 kb
Host smart-73642ac0-ad98-4302-83c8-acdc27179dfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170657453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.170657453
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3913162
Short name T389
Test name
Test status
Simulation time 262675770 ps
CPU time 1.23 seconds
Started Jul 24 06:00:09 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 217248 kb
Host smart-f9b43ca1-3a4d-47c5-ac67-a82ee362e982
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913162 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disab
le_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disa
ble_auto_req_mode.3913162
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1382151994
Short name T650
Test name
Test status
Simulation time 22189048 ps
CPU time 1.11 seconds
Started Jul 24 06:00:04 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 224256 kb
Host smart-6ba7eab8-a438-4426-86e0-2bdb1bf16f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382151994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1382151994
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3241719947
Short name T979
Test name
Test status
Simulation time 67060152 ps
CPU time 1.31 seconds
Started Jul 24 06:00:10 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 218712 kb
Host smart-0ea17a35-4b18-4241-845e-91e6241e46f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241719947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3241719947
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.3650287044
Short name T784
Test name
Test status
Simulation time 108622659 ps
CPU time 0.89 seconds
Started Jul 24 06:00:09 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215812 kb
Host smart-4d53316a-27c5-402d-bffa-d0a7e407c009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650287044 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3650287044
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.4253430718
Short name T368
Test name
Test status
Simulation time 458104138 ps
CPU time 3.24 seconds
Started Jul 24 06:00:06 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 217516 kb
Host smart-aa1c91c9-fc3c-4c20-915c-d33d38c3d3fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253430718 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.4253430718
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.753189137
Short name T581
Test name
Test status
Simulation time 257873377889 ps
CPU time 1553.92 seconds
Started Jul 24 06:00:13 PM PDT 24
Finished Jul 24 06:26:07 PM PDT 24
Peak memory 224740 kb
Host smart-85af6d28-0096-4ad8-b837-0780416ecad9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753189137 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.753189137
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.3653703049
Short name T866
Test name
Test status
Simulation time 50227893 ps
CPU time 1.34 seconds
Started Jul 24 06:01:18 PM PDT 24
Finished Jul 24 06:01:19 PM PDT 24
Peak memory 216068 kb
Host smart-2b1bfc91-0958-4b23-8fdd-344d4990565b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653703049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3653703049
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1084864450
Short name T662
Test name
Test status
Simulation time 81155105 ps
CPU time 1.81 seconds
Started Jul 24 06:01:34 PM PDT 24
Finished Jul 24 06:01:36 PM PDT 24
Peak memory 218904 kb
Host smart-fa5b858d-7cc6-4264-bd1e-4c97ddde54e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084864450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1084864450
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.851482074
Short name T297
Test name
Test status
Simulation time 385770086 ps
CPU time 1.24 seconds
Started Jul 24 06:01:24 PM PDT 24
Finished Jul 24 06:01:25 PM PDT 24
Peak memory 220880 kb
Host smart-d641972f-5266-455d-946a-a243b60da129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851482074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.851482074
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.2462648944
Short name T676
Test name
Test status
Simulation time 47938991 ps
CPU time 1.08 seconds
Started Jul 24 06:01:29 PM PDT 24
Finished Jul 24 06:01:31 PM PDT 24
Peak memory 218820 kb
Host smart-e0d15f1c-277e-4efd-acec-220ae87a1a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462648944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2462648944
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1248414744
Short name T87
Test name
Test status
Simulation time 85045268 ps
CPU time 2.98 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:31 PM PDT 24
Peak memory 219448 kb
Host smart-28d8a7ad-db92-41aa-89c0-ea7175a434a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248414744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1248414744
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.601197541
Short name T119
Test name
Test status
Simulation time 28430077 ps
CPU time 1.15 seconds
Started Jul 24 06:01:22 PM PDT 24
Finished Jul 24 06:01:24 PM PDT 24
Peak memory 218980 kb
Host smart-af331043-b112-49a7-9dc8-0e6ac42ad4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601197541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.601197541
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/134.edn_alert.3216706968
Short name T779
Test name
Test status
Simulation time 60924533 ps
CPU time 1.24 seconds
Started Jul 24 06:01:21 PM PDT 24
Finished Jul 24 06:01:22 PM PDT 24
Peak memory 219092 kb
Host smart-f8bcfe0c-58b1-4ccd-9f3e-fe62c4e5bca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216706968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.3216706968
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.1468370687
Short name T588
Test name
Test status
Simulation time 96021676 ps
CPU time 1.43 seconds
Started Jul 24 06:01:21 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 218972 kb
Host smart-0410a74d-cc4a-4b75-8de3-e7a11a532274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468370687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1468370687
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.2061192242
Short name T130
Test name
Test status
Simulation time 76975491 ps
CPU time 1.13 seconds
Started Jul 24 06:01:25 PM PDT 24
Finished Jul 24 06:01:26 PM PDT 24
Peak memory 218880 kb
Host smart-1f6a50a3-8555-47de-ad02-b62914072eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061192242 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2061192242
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.1492877448
Short name T563
Test name
Test status
Simulation time 163876939 ps
CPU time 1.28 seconds
Started Jul 24 06:01:30 PM PDT 24
Finished Jul 24 06:01:31 PM PDT 24
Peak memory 219124 kb
Host smart-5fbd0c78-0924-448d-bc1c-9c88c37a05ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492877448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1492877448
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.2057220444
Short name T379
Test name
Test status
Simulation time 33982399 ps
CPU time 1.37 seconds
Started Jul 24 06:01:25 PM PDT 24
Finished Jul 24 06:01:27 PM PDT 24
Peak memory 216084 kb
Host smart-caf13a33-c972-4175-b742-a60aff9b2d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057220444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.2057220444
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2152430149
Short name T861
Test name
Test status
Simulation time 70921367 ps
CPU time 1.12 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 217508 kb
Host smart-26199d9b-0dbb-4e35-9311-eaaf02d874f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152430149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2152430149
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.1489820225
Short name T524
Test name
Test status
Simulation time 82357625 ps
CPU time 1.19 seconds
Started Jul 24 06:01:22 PM PDT 24
Finished Jul 24 06:01:24 PM PDT 24
Peak memory 219956 kb
Host smart-06a47a17-5f1d-4aeb-8585-22626c4e0aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489820225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1489820225
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/138.edn_alert.1047785957
Short name T919
Test name
Test status
Simulation time 27700671 ps
CPU time 1.26 seconds
Started Jul 24 06:01:29 PM PDT 24
Finished Jul 24 06:01:31 PM PDT 24
Peak memory 220328 kb
Host smart-4c3b3aff-a0a0-4bb0-896e-13ffa4500adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047785957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.1047785957
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.341400321
Short name T900
Test name
Test status
Simulation time 67395617 ps
CPU time 1.21 seconds
Started Jul 24 06:01:33 PM PDT 24
Finished Jul 24 06:01:34 PM PDT 24
Peak memory 219172 kb
Host smart-e33f2b6b-50aa-4186-bf58-d5f02b3a762a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341400321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.341400321
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2059258839
Short name T161
Test name
Test status
Simulation time 200379400 ps
CPU time 1.24 seconds
Started Jul 24 06:01:35 PM PDT 24
Finished Jul 24 06:01:36 PM PDT 24
Peak memory 220844 kb
Host smart-448343ef-c4d2-47a3-9d88-1c2e2a1f66d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059258839 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2059258839
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.2832592077
Short name T595
Test name
Test status
Simulation time 40785675 ps
CPU time 1.06 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:27 PM PDT 24
Peak memory 217548 kb
Host smart-4a85dd32-88f9-420e-ad39-50fc5a7bbb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832592077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2832592077
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3268161335
Short name T648
Test name
Test status
Simulation time 27097725 ps
CPU time 1.27 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 218924 kb
Host smart-b830192e-3eb7-4a42-a7d9-3714a343e657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268161335 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3268161335
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1814001991
Short name T868
Test name
Test status
Simulation time 156086260 ps
CPU time 0.84 seconds
Started Jul 24 06:00:10 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 215012 kb
Host smart-b28e8d1b-0e5d-4bca-8524-2ace07d30e36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814001991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1814001991
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.4248334721
Short name T754
Test name
Test status
Simulation time 30656451 ps
CPU time 0.87 seconds
Started Jul 24 06:00:11 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 216552 kb
Host smart-b7d386bc-6681-4c16-8805-7f760675a3b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248334721 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.4248334721
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.2810543506
Short name T207
Test name
Test status
Simulation time 19349864 ps
CPU time 1.07 seconds
Started Jul 24 06:00:09 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 218832 kb
Host smart-6ed6be98-887d-4fea-8826-491a2a91bf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810543506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2810543506
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2841002296
Short name T810
Test name
Test status
Simulation time 40196273 ps
CPU time 1.36 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 217604 kb
Host smart-35e8f029-7eff-4a37-9e17-77d0ca31909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841002296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2841002296
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.2622973530
Short name T242
Test name
Test status
Simulation time 46025072 ps
CPU time 0.94 seconds
Started Jul 24 06:00:06 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215624 kb
Host smart-e576a5ca-5d11-4e99-9879-ec4a1f198ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622973530 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2622973530
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3800218549
Short name T306
Test name
Test status
Simulation time 266301788 ps
CPU time 3.02 seconds
Started Jul 24 06:00:05 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 217612 kb
Host smart-778be862-7cc2-44f6-81b5-9b5cc83c147e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800218549 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3800218549
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1958733525
Short name T855
Test name
Test status
Simulation time 286448949146 ps
CPU time 2578.66 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:43:11 PM PDT 24
Peak memory 232900 kb
Host smart-4b9eef2d-b9f0-48b4-84cf-4f87c7083c44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958733525 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1958733525
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.4111858988
Short name T383
Test name
Test status
Simulation time 50554143 ps
CPU time 1.18 seconds
Started Jul 24 06:01:37 PM PDT 24
Finished Jul 24 06:01:38 PM PDT 24
Peak memory 218920 kb
Host smart-5f913b81-e12a-4689-8309-f62e5c2f4a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111858988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.4111858988
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.2346166675
Short name T557
Test name
Test status
Simulation time 58437016 ps
CPU time 1.09 seconds
Started Jul 24 06:01:23 PM PDT 24
Finished Jul 24 06:01:24 PM PDT 24
Peak memory 217668 kb
Host smart-00cdc7c1-7a5d-4711-86af-91c378301eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346166675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2346166675
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2298043485
Short name T791
Test name
Test status
Simulation time 64392556 ps
CPU time 1.24 seconds
Started Jul 24 06:01:23 PM PDT 24
Finished Jul 24 06:01:24 PM PDT 24
Peak memory 221184 kb
Host smart-855ef7ec-a2d7-4e84-9a0e-86c0bce28285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298043485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2298043485
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.481583320
Short name T432
Test name
Test status
Simulation time 95569977 ps
CPU time 1.17 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:29 PM PDT 24
Peak memory 217832 kb
Host smart-db22bf9e-fdd7-4308-883f-fd52e09a2ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481583320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.481583320
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.2143516341
Short name T890
Test name
Test status
Simulation time 25909602 ps
CPU time 1.17 seconds
Started Jul 24 06:01:33 PM PDT 24
Finished Jul 24 06:01:34 PM PDT 24
Peak memory 219164 kb
Host smart-a0a29e7d-ce18-4314-9ff4-6a241d71207b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143516341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2143516341
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.3187263919
Short name T651
Test name
Test status
Simulation time 93882729 ps
CPU time 2.23 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:29 PM PDT 24
Peak memory 220324 kb
Host smart-618d95c8-5b72-422d-a4b0-a2223eeff2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187263919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3187263919
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.608998947
Short name T847
Test name
Test status
Simulation time 132290220 ps
CPU time 1.32 seconds
Started Jul 24 06:01:29 PM PDT 24
Finished Jul 24 06:01:31 PM PDT 24
Peak memory 220180 kb
Host smart-0848803b-ad5d-41cb-b36d-2ed9bce9e9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608998947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.608998947
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.1774414757
Short name T906
Test name
Test status
Simulation time 61932722 ps
CPU time 1.1 seconds
Started Jul 24 06:01:34 PM PDT 24
Finished Jul 24 06:01:35 PM PDT 24
Peak memory 217576 kb
Host smart-b9a7502e-d7a4-461f-91ed-29a679f09dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774414757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1774414757
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.918361393
Short name T310
Test name
Test status
Simulation time 85592682 ps
CPU time 1.31 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 219044 kb
Host smart-901d0300-bf3d-4a0d-9f02-5f9d1d4dfd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918361393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.918361393
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.3121199882
Short name T180
Test name
Test status
Simulation time 29685369 ps
CPU time 1.28 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:27 PM PDT 24
Peak memory 221212 kb
Host smart-fbc1500c-c0ee-44da-a561-a4d3b5933b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121199882 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3121199882
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.817366973
Short name T819
Test name
Test status
Simulation time 40858514 ps
CPU time 1.44 seconds
Started Jul 24 06:01:24 PM PDT 24
Finished Jul 24 06:01:26 PM PDT 24
Peak memory 218732 kb
Host smart-c610768d-14c9-4f81-9e4f-f5d673783629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817366973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.817366973
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.540098374
Short name T879
Test name
Test status
Simulation time 49820734 ps
CPU time 1.22 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 220176 kb
Host smart-b0e91ace-3aff-422b-b453-725580ed3e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540098374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.540098374
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.3231186018
Short name T817
Test name
Test status
Simulation time 91877081 ps
CPU time 1.51 seconds
Started Jul 24 06:01:33 PM PDT 24
Finished Jul 24 06:01:34 PM PDT 24
Peak memory 219140 kb
Host smart-177443ff-99a2-4cd6-ab38-c402c72162d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231186018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3231186018
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.662498479
Short name T418
Test name
Test status
Simulation time 50664321 ps
CPU time 1.6 seconds
Started Jul 24 06:01:38 PM PDT 24
Finished Jul 24 06:01:40 PM PDT 24
Peak memory 218628 kb
Host smart-761d3216-a4fb-4c7e-8c10-0c6e6a4cd107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662498479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.662498479
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.310033193
Short name T968
Test name
Test status
Simulation time 132592498 ps
CPU time 1.24 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 220008 kb
Host smart-edd9a16b-e46b-4cdc-86b7-ff832f838099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310033193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.310033193
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3838384671
Short name T47
Test name
Test status
Simulation time 108185179 ps
CPU time 1.17 seconds
Started Jul 24 06:01:29 PM PDT 24
Finished Jul 24 06:01:30 PM PDT 24
Peak memory 220552 kb
Host smart-e04244a7-b053-403c-9a28-b8d321f7b00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838384671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3838384671
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.4061955941
Short name T438
Test name
Test status
Simulation time 41361940 ps
CPU time 1.61 seconds
Started Jul 24 06:01:38 PM PDT 24
Finished Jul 24 06:01:40 PM PDT 24
Peak memory 218784 kb
Host smart-ea69e800-9573-47e2-af11-4a1ca95467a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061955941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.4061955941
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2187133688
Short name T455
Test name
Test status
Simulation time 48088867 ps
CPU time 1.23 seconds
Started Jul 24 06:00:08 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 219084 kb
Host smart-a9151677-ace8-4e37-b3e3-2f6d3d5aa2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187133688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2187133688
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2818097544
Short name T443
Test name
Test status
Simulation time 24230158 ps
CPU time 0.9 seconds
Started Jul 24 06:00:10 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 215472 kb
Host smart-ed881e7e-496e-48fb-917a-e9c56436fe50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818097544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2818097544
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1234788455
Short name T652
Test name
Test status
Simulation time 13263958 ps
CPU time 0.91 seconds
Started Jul 24 06:00:10 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 216800 kb
Host smart-ecc079e1-1098-4269-87f3-a7ff1fda314b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234788455 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1234788455
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1569538457
Short name T531
Test name
Test status
Simulation time 34161547 ps
CPU time 1.19 seconds
Started Jul 24 06:00:09 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 218912 kb
Host smart-01133b6f-c368-4c47-babf-2e6294875b41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569538457 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1569538457
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.331617575
Short name T934
Test name
Test status
Simulation time 25126823 ps
CPU time 1.2 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 220980 kb
Host smart-dafc8864-5f7e-41cb-9677-9a6fdcffb142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331617575 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.331617575
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_intr.2214759213
Short name T85
Test name
Test status
Simulation time 20751054 ps
CPU time 1.03 seconds
Started Jul 24 06:00:09 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 216252 kb
Host smart-36d8ff9e-e1a8-4967-8d90-b8f84fd33135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214759213 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2214759213
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.676854319
Short name T456
Test name
Test status
Simulation time 51323358 ps
CPU time 0.98 seconds
Started Jul 24 06:00:13 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 215636 kb
Host smart-a8e8609d-701a-40e5-8af3-e8e35a6a83a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676854319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.676854319
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1440720148
Short name T702
Test name
Test status
Simulation time 261641384 ps
CPU time 2.97 seconds
Started Jul 24 06:00:05 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 215660 kb
Host smart-ef02724e-cf86-49a0-8aaf-fac5ac7f8e34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440720148 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1440720148
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.773309377
Short name T223
Test name
Test status
Simulation time 82843583190 ps
CPU time 791.54 seconds
Started Jul 24 06:00:13 PM PDT 24
Finished Jul 24 06:13:25 PM PDT 24
Peak memory 222456 kb
Host smart-c4da866a-6000-4395-959a-8c9521f9569b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773309377 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.773309377
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.3347557989
Short name T990
Test name
Test status
Simulation time 23897381 ps
CPU time 1.19 seconds
Started Jul 24 06:01:54 PM PDT 24
Finished Jul 24 06:01:56 PM PDT 24
Peak memory 219144 kb
Host smart-d29bcf88-4858-4955-a772-83374eddfbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347557989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.3347557989
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.754254464
Short name T56
Test name
Test status
Simulation time 79080838 ps
CPU time 1.15 seconds
Started Jul 24 06:01:34 PM PDT 24
Finished Jul 24 06:01:36 PM PDT 24
Peak memory 217600 kb
Host smart-5547d3d5-6eb4-4f32-ac0e-e0d2b98519ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754254464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.754254464
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.108475981
Short name T491
Test name
Test status
Simulation time 63524021 ps
CPU time 1.11 seconds
Started Jul 24 06:01:35 PM PDT 24
Finished Jul 24 06:01:36 PM PDT 24
Peak memory 219864 kb
Host smart-3405ac95-15e1-4ebb-8b07-b96ad1ea8bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108475981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.108475981
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3605562478
Short name T458
Test name
Test status
Simulation time 26925944 ps
CPU time 1.38 seconds
Started Jul 24 06:01:40 PM PDT 24
Finished Jul 24 06:01:42 PM PDT 24
Peak memory 218652 kb
Host smart-5290b39c-04ad-4cc3-a424-3f3a43d7850e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605562478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3605562478
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3509442339
Short name T628
Test name
Test status
Simulation time 244279810 ps
CPU time 1.22 seconds
Started Jul 24 06:01:35 PM PDT 24
Finished Jul 24 06:01:37 PM PDT 24
Peak memory 220776 kb
Host smart-50db554e-2554-45df-b1ca-5733ae67ee4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509442339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3509442339
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.2630121049
Short name T397
Test name
Test status
Simulation time 83682309 ps
CPU time 1.43 seconds
Started Jul 24 06:01:29 PM PDT 24
Finished Jul 24 06:01:31 PM PDT 24
Peak memory 219192 kb
Host smart-3959d5b6-152b-415e-8bb2-a312dafffdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630121049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2630121049
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2564196307
Short name T759
Test name
Test status
Simulation time 70281426 ps
CPU time 1.07 seconds
Started Jul 24 06:01:39 PM PDT 24
Finished Jul 24 06:01:40 PM PDT 24
Peak memory 220036 kb
Host smart-6bb69157-c2b1-46b6-ba2f-b6c19f8093a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564196307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2564196307
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3252837691
Short name T24
Test name
Test status
Simulation time 74273842 ps
CPU time 1.64 seconds
Started Jul 24 06:01:39 PM PDT 24
Finished Jul 24 06:01:41 PM PDT 24
Peak memory 219636 kb
Host smart-bad9ae35-48be-414e-950c-1c8aba5c84a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252837691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3252837691
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.258056003
Short name T243
Test name
Test status
Simulation time 32535735 ps
CPU time 1.32 seconds
Started Jul 24 06:01:39 PM PDT 24
Finished Jul 24 06:01:41 PM PDT 24
Peak memory 218892 kb
Host smart-ec65076c-99f7-4a40-87e9-4f39acca8130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258056003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.258056003
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.3421835340
Short name T537
Test name
Test status
Simulation time 49937924 ps
CPU time 1.35 seconds
Started Jul 24 06:01:29 PM PDT 24
Finished Jul 24 06:01:30 PM PDT 24
Peak memory 217760 kb
Host smart-b7d8cc97-dd20-4720-8817-6c3a4f448709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421835340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3421835340
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3016594434
Short name T611
Test name
Test status
Simulation time 23099712 ps
CPU time 1.21 seconds
Started Jul 24 06:01:52 PM PDT 24
Finished Jul 24 06:01:54 PM PDT 24
Peak memory 221020 kb
Host smart-f9eb90d8-6248-479a-a35b-9902387b3809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016594434 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3016594434
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.4248579242
Short name T422
Test name
Test status
Simulation time 92305626 ps
CPU time 1.33 seconds
Started Jul 24 06:01:52 PM PDT 24
Finished Jul 24 06:01:54 PM PDT 24
Peak memory 220604 kb
Host smart-f6a1dfc7-02ef-4ea2-812f-8ef1d5cb0f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248579242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.4248579242
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.3262559128
Short name T294
Test name
Test status
Simulation time 26724608 ps
CPU time 1.28 seconds
Started Jul 24 06:01:29 PM PDT 24
Finished Jul 24 06:01:31 PM PDT 24
Peak memory 219092 kb
Host smart-194671f7-cc6d-446a-bc29-ecad5ec90e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262559128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3262559128
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2560825725
Short name T500
Test name
Test status
Simulation time 58264681 ps
CPU time 1.3 seconds
Started Jul 24 06:01:43 PM PDT 24
Finished Jul 24 06:01:45 PM PDT 24
Peak memory 218900 kb
Host smart-fbd8b75f-ca8b-43cd-83d4-cd50804779cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560825725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2560825725
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.1705144967
Short name T301
Test name
Test status
Simulation time 107809013 ps
CPU time 1.27 seconds
Started Jul 24 06:01:29 PM PDT 24
Finished Jul 24 06:01:30 PM PDT 24
Peak memory 220176 kb
Host smart-c6c81336-3007-4b59-9e4a-5d0363aeb5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705144967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1705144967
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.3528692433
Short name T734
Test name
Test status
Simulation time 101612620 ps
CPU time 1.22 seconds
Started Jul 24 06:01:37 PM PDT 24
Finished Jul 24 06:01:38 PM PDT 24
Peak memory 218844 kb
Host smart-5cd5c80b-cf8b-44c3-9db8-f258486b42df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528692433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3528692433
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.94842777
Short name T623
Test name
Test status
Simulation time 24581784 ps
CPU time 1.17 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 218876 kb
Host smart-8dd871dc-fc12-4e43-b935-efe50935f308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94842777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.94842777
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.3558656032
Short name T409
Test name
Test status
Simulation time 160246078 ps
CPU time 2.08 seconds
Started Jul 24 06:01:45 PM PDT 24
Finished Jul 24 06:01:53 PM PDT 24
Peak memory 220636 kb
Host smart-d6b3fdc2-d99c-4a16-b5ac-45c84c11647c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558656032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3558656032
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.1599621831
Short name T58
Test name
Test status
Simulation time 30028750 ps
CPU time 1.26 seconds
Started Jul 24 06:01:47 PM PDT 24
Finished Jul 24 06:01:48 PM PDT 24
Peak memory 219800 kb
Host smart-671e7f6f-3d83-4e3c-a03c-ecb88f074d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599621831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.1599621831
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1142174475
Short name T657
Test name
Test status
Simulation time 79324026 ps
CPU time 1.12 seconds
Started Jul 24 06:01:39 PM PDT 24
Finished Jul 24 06:01:41 PM PDT 24
Peak memory 217628 kb
Host smart-ec40445c-55d7-4463-a2da-c291d0124606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142174475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1142174475
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1346119791
Short name T101
Test name
Test status
Simulation time 27157203 ps
CPU time 1.31 seconds
Started Jul 24 06:00:14 PM PDT 24
Finished Jul 24 06:00:16 PM PDT 24
Peak memory 218992 kb
Host smart-7f9e360a-80e5-489f-9416-96b76314a3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346119791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1346119791
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable.3075194198
Short name T201
Test name
Test status
Simulation time 33936909 ps
CPU time 0.88 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 216720 kb
Host smart-8a5feee3-7a12-4c28-b314-145084305e09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075194198 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3075194198
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2056992399
Short name T448
Test name
Test status
Simulation time 57249681 ps
CPU time 1.11 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 217288 kb
Host smart-d1f6ec69-8ecb-4496-8f8c-a7e716c68b28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056992399 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2056992399
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2140639063
Short name T700
Test name
Test status
Simulation time 68171881 ps
CPU time 1.11 seconds
Started Jul 24 06:00:11 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 230008 kb
Host smart-1b4fb3c9-7ffa-4212-b6a2-ef208421598a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140639063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2140639063
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1399664747
Short name T961
Test name
Test status
Simulation time 191109242 ps
CPU time 1.47 seconds
Started Jul 24 06:00:07 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 219860 kb
Host smart-a3f54187-440b-4f51-bb7d-91d36fa2403d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399664747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1399664747
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1784464610
Short name T578
Test name
Test status
Simulation time 22182710 ps
CPU time 1.08 seconds
Started Jul 24 06:00:14 PM PDT 24
Finished Jul 24 06:00:16 PM PDT 24
Peak memory 215960 kb
Host smart-20b4160d-67e5-4b0a-814e-6285fb5e2a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784464610 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1784464610
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.622847260
Short name T384
Test name
Test status
Simulation time 73023557 ps
CPU time 0.9 seconds
Started Jul 24 06:00:09 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215612 kb
Host smart-fbc24c79-1824-41c4-a6e6-a1c4bd911321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622847260 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.622847260
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1798645516
Short name T963
Test name
Test status
Simulation time 113425530 ps
CPU time 2.28 seconds
Started Jul 24 06:00:06 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 215576 kb
Host smart-9c9206a1-f9a1-4f96-a41b-dced1b727432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798645516 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1798645516
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_alert.3277545062
Short name T299
Test name
Test status
Simulation time 27152137 ps
CPU time 1.22 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 220080 kb
Host smart-7bd36940-67aa-4b4b-b163-6227ff172104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277545062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3277545062
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.3789233853
Short name T366
Test name
Test status
Simulation time 26179792 ps
CPU time 1.41 seconds
Started Jul 24 06:01:57 PM PDT 24
Finished Jul 24 06:01:58 PM PDT 24
Peak memory 217764 kb
Host smart-6f2e2ae2-a1ef-460f-891b-01eca8fd48e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789233853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3789233853
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.4012010920
Short name T522
Test name
Test status
Simulation time 35962487 ps
CPU time 1.35 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:29 PM PDT 24
Peak memory 217580 kb
Host smart-b3a6aa70-b007-416d-a43a-e683adb70a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012010920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.4012010920
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.1962534088
Short name T48
Test name
Test status
Simulation time 41553262 ps
CPU time 1.08 seconds
Started Jul 24 06:01:28 PM PDT 24
Finished Jul 24 06:01:30 PM PDT 24
Peak memory 219964 kb
Host smart-35f5f679-61f6-4ad5-9437-8658e48b3dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962534088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1962534088
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.4021119939
Short name T832
Test name
Test status
Simulation time 38935876 ps
CPU time 1.61 seconds
Started Jul 24 06:01:34 PM PDT 24
Finished Jul 24 06:01:36 PM PDT 24
Peak memory 217556 kb
Host smart-6fe87a08-eee1-437f-a0cd-49b5344d18d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021119939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.4021119939
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.3101256743
Short name T725
Test name
Test status
Simulation time 46133829 ps
CPU time 1.24 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:29 PM PDT 24
Peak memory 218924 kb
Host smart-56dc666a-45fa-465f-83a5-19378f5c1709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101256743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.3101256743
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1141002615
Short name T57
Test name
Test status
Simulation time 63243030 ps
CPU time 1.42 seconds
Started Jul 24 06:01:39 PM PDT 24
Finished Jul 24 06:01:40 PM PDT 24
Peak memory 218972 kb
Host smart-fdeae0a0-06f1-4cb8-9a94-633286f7bc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141002615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1141002615
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2927919445
Short name T118
Test name
Test status
Simulation time 38783919 ps
CPU time 1.13 seconds
Started Jul 24 06:01:46 PM PDT 24
Finished Jul 24 06:01:47 PM PDT 24
Peak memory 218972 kb
Host smart-a4c9bfab-93f4-40cf-b36d-afcff012b50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927919445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2927919445
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/165.edn_alert.2758188190
Short name T493
Test name
Test status
Simulation time 40519177 ps
CPU time 1.32 seconds
Started Jul 24 06:01:28 PM PDT 24
Finished Jul 24 06:01:30 PM PDT 24
Peak memory 220828 kb
Host smart-a71e6a3f-5308-42cf-b7d1-5fb662da8bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758188190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2758188190
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3256463856
Short name T796
Test name
Test status
Simulation time 75564390 ps
CPU time 1.73 seconds
Started Jul 24 06:01:45 PM PDT 24
Finished Jul 24 06:01:47 PM PDT 24
Peak memory 218924 kb
Host smart-44e33f8b-f50b-4219-9fc9-602e400592b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256463856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3256463856
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.225341404
Short name T215
Test name
Test status
Simulation time 136852741 ps
CPU time 1.35 seconds
Started Jul 24 06:01:46 PM PDT 24
Finished Jul 24 06:01:47 PM PDT 24
Peak memory 220068 kb
Host smart-caae86d0-9f09-4681-a56e-967afd598409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225341404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.225341404
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.707353614
Short name T859
Test name
Test status
Simulation time 135570417 ps
CPU time 2 seconds
Started Jul 24 06:01:58 PM PDT 24
Finished Jul 24 06:02:01 PM PDT 24
Peak memory 220444 kb
Host smart-1530cb4a-69d3-4280-b429-365cf9f7d98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707353614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.707353614
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2689009377
Short name T295
Test name
Test status
Simulation time 32845738 ps
CPU time 1.27 seconds
Started Jul 24 06:01:54 PM PDT 24
Finished Jul 24 06:01:55 PM PDT 24
Peak memory 220148 kb
Host smart-0f026c25-d0e6-4615-b519-bbaff3d53d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689009377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2689009377
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1992608466
Short name T426
Test name
Test status
Simulation time 37964588 ps
CPU time 1.47 seconds
Started Jul 24 06:01:43 PM PDT 24
Finished Jul 24 06:01:45 PM PDT 24
Peak memory 220348 kb
Host smart-3cfc61ea-fde9-4162-8b07-697425a2f84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992608466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1992608466
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.3080812030
Short name T943
Test name
Test status
Simulation time 89436450 ps
CPU time 1.13 seconds
Started Jul 24 06:01:53 PM PDT 24
Finished Jul 24 06:01:54 PM PDT 24
Peak memory 218972 kb
Host smart-692396b3-464e-48bc-b89a-d6a816a54b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080812030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3080812030
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1288980217
Short name T502
Test name
Test status
Simulation time 21685638 ps
CPU time 1.15 seconds
Started Jul 24 06:01:40 PM PDT 24
Finished Jul 24 06:01:42 PM PDT 24
Peak memory 217900 kb
Host smart-3eadb193-e20a-4186-a940-ca66db895a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288980217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1288980217
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.461771053
Short name T755
Test name
Test status
Simulation time 26232606 ps
CPU time 1.24 seconds
Started Jul 24 06:01:36 PM PDT 24
Finished Jul 24 06:01:38 PM PDT 24
Peak memory 219840 kb
Host smart-dba9a69d-195e-4963-b114-c7e3a933729d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461771053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.461771053
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.621443604
Short name T758
Test name
Test status
Simulation time 74716503 ps
CPU time 1.41 seconds
Started Jul 24 06:01:35 PM PDT 24
Finished Jul 24 06:01:37 PM PDT 24
Peak memory 217812 kb
Host smart-c559ed0d-9745-4dc7-84b4-d6813a9d6e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621443604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.621443604
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.3178836233
Short name T638
Test name
Test status
Simulation time 16673721 ps
CPU time 0.93 seconds
Started Jul 24 06:00:09 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 206952 kb
Host smart-eb751cc0-d367-44c0-a214-ae48f83c2601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178836233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3178836233
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.702476605
Short name T187
Test name
Test status
Simulation time 12858901 ps
CPU time 0.93 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 215940 kb
Host smart-efdc9e3e-d358-4c09-bd4f-84cebb48bca5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702476605 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.702476605
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.4204165082
Short name T901
Test name
Test status
Simulation time 41867819 ps
CPU time 1.1 seconds
Started Jul 24 06:00:13 PM PDT 24
Finished Jul 24 06:00:20 PM PDT 24
Peak memory 217288 kb
Host smart-b88ef17a-08db-4ead-9752-6371c5c996cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204165082 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.4204165082
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.3691139816
Short name T4
Test name
Test status
Simulation time 30717776 ps
CPU time 0.87 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 218488 kb
Host smart-d175fe1a-da33-4389-863a-6eb9555fb23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691139816 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3691139816
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3004149791
Short name T658
Test name
Test status
Simulation time 41978365 ps
CPU time 1.19 seconds
Started Jul 24 06:00:10 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 219648 kb
Host smart-a057be73-3a1b-4603-95bb-af31428fa0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004149791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3004149791
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3092897592
Short name T39
Test name
Test status
Simulation time 27365547 ps
CPU time 0.94 seconds
Started Jul 24 06:00:15 PM PDT 24
Finished Jul 24 06:00:16 PM PDT 24
Peak memory 216176 kb
Host smart-9c5f9a2c-be24-4ff3-8530-403c280f76bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092897592 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3092897592
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3363692239
Short name T597
Test name
Test status
Simulation time 28572879 ps
CPU time 0.98 seconds
Started Jul 24 06:00:16 PM PDT 24
Finished Jul 24 06:00:17 PM PDT 24
Peak memory 215632 kb
Host smart-63ff3ce8-a899-42ee-8db9-438decab1509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363692239 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3363692239
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2447498832
Short name T227
Test name
Test status
Simulation time 41205193968 ps
CPU time 879.02 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:14:52 PM PDT 24
Peak memory 218252 kb
Host smart-db123ffd-9365-4abe-b7ba-53f2d3b6e044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447498832 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2447498832
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.3199091121
Short name T776
Test name
Test status
Simulation time 29835317 ps
CPU time 1.26 seconds
Started Jul 24 06:01:48 PM PDT 24
Finished Jul 24 06:01:49 PM PDT 24
Peak memory 220136 kb
Host smart-6fa8c9bd-621d-48b5-bd66-6f0a5bc9c794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199091121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.3199091121
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.2460211699
Short name T830
Test name
Test status
Simulation time 45528295 ps
CPU time 1.83 seconds
Started Jul 24 06:01:42 PM PDT 24
Finished Jul 24 06:01:44 PM PDT 24
Peak memory 218944 kb
Host smart-4f24cf70-2cba-483e-b883-1cbc666961e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460211699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2460211699
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.202195445
Short name T889
Test name
Test status
Simulation time 26136649 ps
CPU time 1.18 seconds
Started Jul 24 06:01:43 PM PDT 24
Finished Jul 24 06:01:45 PM PDT 24
Peak memory 221164 kb
Host smart-3d9038ab-61b4-4638-ae74-a8710a21a8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202195445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.202195445
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.518334857
Short name T589
Test name
Test status
Simulation time 136752861 ps
CPU time 1.35 seconds
Started Jul 24 06:01:44 PM PDT 24
Finished Jul 24 06:01:46 PM PDT 24
Peak memory 219192 kb
Host smart-37213fe3-2df5-4a94-b123-00d383babfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518334857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.518334857
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.3719765470
Short name T125
Test name
Test status
Simulation time 82414810 ps
CPU time 1.19 seconds
Started Jul 24 06:01:33 PM PDT 24
Finished Jul 24 06:01:34 PM PDT 24
Peak memory 220876 kb
Host smart-521e8bb5-e775-40ff-ad9a-09fdedd49ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719765470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.3719765470
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/173.edn_alert.4162330967
Short name T605
Test name
Test status
Simulation time 28571178 ps
CPU time 1.26 seconds
Started Jul 24 06:01:35 PM PDT 24
Finished Jul 24 06:01:37 PM PDT 24
Peak memory 218908 kb
Host smart-306d427f-0c66-41d0-87de-1189d4c524ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162330967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.4162330967
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.157972693
Short name T307
Test name
Test status
Simulation time 45238430 ps
CPU time 1.6 seconds
Started Jul 24 06:01:38 PM PDT 24
Finished Jul 24 06:01:40 PM PDT 24
Peak memory 219032 kb
Host smart-bd4fa66e-d010-4945-9511-884438c24d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157972693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.157972693
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.4101448196
Short name T114
Test name
Test status
Simulation time 50388210 ps
CPU time 1.27 seconds
Started Jul 24 06:01:33 PM PDT 24
Finished Jul 24 06:01:35 PM PDT 24
Peak memory 218920 kb
Host smart-9ecbb0c9-30d0-43b5-b846-2ef21cd3ecbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101448196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.4101448196
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3954732067
Short name T429
Test name
Test status
Simulation time 50658963 ps
CPU time 1.36 seconds
Started Jul 24 06:02:04 PM PDT 24
Finished Jul 24 06:02:06 PM PDT 24
Peak memory 220316 kb
Host smart-bc3a7dad-9c8e-4690-bc0f-59b3705bd378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954732067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3954732067
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.1536475062
Short name T864
Test name
Test status
Simulation time 49547341 ps
CPU time 1.27 seconds
Started Jul 24 06:01:41 PM PDT 24
Finished Jul 24 06:01:42 PM PDT 24
Peak memory 219988 kb
Host smart-3718282c-c9ce-4c58-ae52-b993ef9b3edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536475062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1536475062
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.1706354298
Short name T904
Test name
Test status
Simulation time 63186770 ps
CPU time 1.18 seconds
Started Jul 24 06:01:39 PM PDT 24
Finished Jul 24 06:01:40 PM PDT 24
Peak memory 217644 kb
Host smart-41e3e7d8-497d-488e-b0e0-a1ac2eaf9a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706354298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1706354298
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.3761423199
Short name T106
Test name
Test status
Simulation time 25704568 ps
CPU time 1.23 seconds
Started Jul 24 06:02:04 PM PDT 24
Finished Jul 24 06:02:05 PM PDT 24
Peak memory 218964 kb
Host smart-445f6a67-e5bb-46a3-82d9-562442e83aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761423199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.3761423199
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.3875939178
Short name T884
Test name
Test status
Simulation time 67410487 ps
CPU time 1.41 seconds
Started Jul 24 06:01:40 PM PDT 24
Finished Jul 24 06:01:41 PM PDT 24
Peak memory 219044 kb
Host smart-2363416a-1b45-49ea-a26a-45b411702185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875939178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3875939178
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.3275588031
Short name T512
Test name
Test status
Simulation time 30658581 ps
CPU time 1.34 seconds
Started Jul 24 06:01:59 PM PDT 24
Finished Jul 24 06:02:01 PM PDT 24
Peak memory 220300 kb
Host smart-5d6e7616-f593-48ab-9fdb-002437785019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275588031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3275588031
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2599259243
Short name T236
Test name
Test status
Simulation time 30084102 ps
CPU time 1.28 seconds
Started Jul 24 06:01:42 PM PDT 24
Finished Jul 24 06:01:44 PM PDT 24
Peak memory 219000 kb
Host smart-372803d1-2739-4cff-98ca-fd495163be5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599259243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2599259243
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3702219329
Short name T80
Test name
Test status
Simulation time 60933613 ps
CPU time 1.52 seconds
Started Jul 24 06:01:39 PM PDT 24
Finished Jul 24 06:01:41 PM PDT 24
Peak memory 219036 kb
Host smart-9bbd25c3-fa14-4cb7-91d4-0265b4d9365f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702219329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3702219329
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.1278994122
Short name T833
Test name
Test status
Simulation time 26817211 ps
CPU time 1.23 seconds
Started Jul 24 06:01:53 PM PDT 24
Finished Jul 24 06:01:54 PM PDT 24
Peak memory 221208 kb
Host smart-de373a8a-c3f1-4065-9a70-fd520280e162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278994122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.1278994122
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2195236611
Short name T586
Test name
Test status
Simulation time 66588939 ps
CPU time 0.99 seconds
Started Jul 24 06:01:59 PM PDT 24
Finished Jul 24 06:02:00 PM PDT 24
Peak memory 217572 kb
Host smart-32012866-f893-403a-a6de-a3a6bbe69d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195236611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2195236611
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2818429588
Short name T97
Test name
Test status
Simulation time 142973542 ps
CPU time 1.3 seconds
Started Jul 24 06:00:10 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 220016 kb
Host smart-58476474-f64b-41e1-b194-52ccfebb89bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818429588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2818429588
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2570411015
Short name T673
Test name
Test status
Simulation time 18634159 ps
CPU time 0.92 seconds
Started Jul 24 06:00:10 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 206980 kb
Host smart-ba7261ef-1001-4021-8407-42dee39c28c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570411015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2570411015
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.4017406544
Short name T157
Test name
Test status
Simulation time 28795205 ps
CPU time 0.85 seconds
Started Jul 24 06:00:11 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 216612 kb
Host smart-3c1cd3b2-171d-4587-9418-2de35a9362ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017406544 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.4017406544
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3703379520
Short name T103
Test name
Test status
Simulation time 207754242 ps
CPU time 1.12 seconds
Started Jul 24 06:00:13 PM PDT 24
Finished Jul 24 06:00:15 PM PDT 24
Peak memory 217376 kb
Host smart-a96afaca-f1b7-474e-a17c-fade047eacbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703379520 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3703379520
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.480580066
Short name T144
Test name
Test status
Simulation time 20578971 ps
CPU time 1.13 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 218916 kb
Host smart-b4c2a0dc-845f-46e0-8330-75b5066bc547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480580066 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.480580066
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2073658104
Short name T28
Test name
Test status
Simulation time 40036844 ps
CPU time 1.53 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 218988 kb
Host smart-bbb3cafd-5f0e-4efb-9264-167b14474378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073658104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2073658104
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.143376292
Short name T408
Test name
Test status
Simulation time 22501994 ps
CPU time 1.14 seconds
Started Jul 24 06:00:10 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 215748 kb
Host smart-6457086a-f6e3-4463-86e4-223bf34b58ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143376292 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.143376292
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2053863585
Short name T917
Test name
Test status
Simulation time 15726373 ps
CPU time 0.97 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 215640 kb
Host smart-1f28c344-f894-49db-8592-467d5507ea91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053863585 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2053863585
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2414568433
Short name T928
Test name
Test status
Simulation time 311935877 ps
CPU time 6.31 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:19 PM PDT 24
Peak memory 217548 kb
Host smart-2fdf098e-fc2f-44af-bd31-3b207458de79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414568433 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2414568433
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1191205769
Short name T460
Test name
Test status
Simulation time 47659828917 ps
CPU time 631.88 seconds
Started Jul 24 06:00:13 PM PDT 24
Finished Jul 24 06:10:45 PM PDT 24
Peak memory 219708 kb
Host smart-73382fa0-bd50-42b6-8f8a-26a1a29b7783
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191205769 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1191205769
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.2318670366
Short name T824
Test name
Test status
Simulation time 51318147 ps
CPU time 1.14 seconds
Started Jul 24 06:01:39 PM PDT 24
Finished Jul 24 06:01:40 PM PDT 24
Peak memory 221176 kb
Host smart-86241c79-bc2c-4d69-84a4-d39e4356127c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318670366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2318670366
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3697540418
Short name T930
Test name
Test status
Simulation time 80911175 ps
CPU time 1.03 seconds
Started Jul 24 06:01:42 PM PDT 24
Finished Jul 24 06:01:43 PM PDT 24
Peak memory 217572 kb
Host smart-71b9ed1a-9493-4bcf-8c72-1974e98e097e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697540418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3697540418
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1576484532
Short name T858
Test name
Test status
Simulation time 46433248 ps
CPU time 1.2 seconds
Started Jul 24 06:01:40 PM PDT 24
Finished Jul 24 06:01:42 PM PDT 24
Peak memory 219276 kb
Host smart-27f59c5e-65f4-4a79-91db-f4fe070a6cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576484532 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1576484532
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.2654516137
Short name T234
Test name
Test status
Simulation time 270686341 ps
CPU time 3.79 seconds
Started Jul 24 06:01:38 PM PDT 24
Finished Jul 24 06:01:42 PM PDT 24
Peak memory 217836 kb
Host smart-7fbad31f-b106-4f1d-bd43-aad2e6ef877a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654516137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2654516137
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3142493973
Short name T249
Test name
Test status
Simulation time 228925122 ps
CPU time 1.13 seconds
Started Jul 24 06:01:43 PM PDT 24
Finished Jul 24 06:01:44 PM PDT 24
Peak memory 218840 kb
Host smart-02328f3a-cd14-4e5f-8327-42d755dc0050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142493973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3142493973
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.367472846
Short name T12
Test name
Test status
Simulation time 67589163 ps
CPU time 1.14 seconds
Started Jul 24 06:01:49 PM PDT 24
Finished Jul 24 06:01:50 PM PDT 24
Peak memory 219668 kb
Host smart-d40534f1-90f5-4771-99c2-9332ae07fde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367472846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.367472846
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.471494724
Short name T170
Test name
Test status
Simulation time 49064162 ps
CPU time 1.12 seconds
Started Jul 24 06:02:05 PM PDT 24
Finished Jul 24 06:02:06 PM PDT 24
Peak memory 219272 kb
Host smart-1390b972-1315-415f-8b9f-45b6d28529fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471494724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.471494724
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.3817596105
Short name T646
Test name
Test status
Simulation time 35486457 ps
CPU time 1.41 seconds
Started Jul 24 06:01:36 PM PDT 24
Finished Jul 24 06:01:38 PM PDT 24
Peak memory 218872 kb
Host smart-80576170-a148-4ad8-9ee4-309ee2320506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817596105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3817596105
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.2983855350
Short name T948
Test name
Test status
Simulation time 451715688 ps
CPU time 1.29 seconds
Started Jul 24 06:01:33 PM PDT 24
Finished Jul 24 06:01:34 PM PDT 24
Peak memory 216064 kb
Host smart-b3bb3cc0-5671-49a8-b7b1-f58c395a1c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983855350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2983855350
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.3807791024
Short name T354
Test name
Test status
Simulation time 44915136 ps
CPU time 1.19 seconds
Started Jul 24 06:01:43 PM PDT 24
Finished Jul 24 06:01:45 PM PDT 24
Peak memory 218760 kb
Host smart-93555fb8-08a1-448c-bae8-0ccd273ea849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807791024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3807791024
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.124519147
Short name T436
Test name
Test status
Simulation time 48105461 ps
CPU time 1.11 seconds
Started Jul 24 06:01:49 PM PDT 24
Finished Jul 24 06:01:51 PM PDT 24
Peak memory 218628 kb
Host smart-e429ba91-522a-4d1f-a3ee-f906ce259911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124519147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.124519147
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2983388782
Short name T484
Test name
Test status
Simulation time 35711605 ps
CPU time 1.41 seconds
Started Jul 24 06:02:05 PM PDT 24
Finished Jul 24 06:02:07 PM PDT 24
Peak memory 215624 kb
Host smart-29c5383b-1538-4e7f-8e6a-998d85822e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983388782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2983388782
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2764351611
Short name T872
Test name
Test status
Simulation time 76067510 ps
CPU time 1.17 seconds
Started Jul 24 06:01:38 PM PDT 24
Finished Jul 24 06:01:40 PM PDT 24
Peak memory 220492 kb
Host smart-e71cf6a7-3679-4cda-b49a-6f41c2ee4c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764351611 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2764351611
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.18005968
Short name T390
Test name
Test status
Simulation time 98309318 ps
CPU time 0.94 seconds
Started Jul 24 06:01:46 PM PDT 24
Finished Jul 24 06:01:48 PM PDT 24
Peak memory 217516 kb
Host smart-8c91940c-445a-45c1-93e5-0d50b85ab58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18005968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.18005968
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.3861435522
Short name T711
Test name
Test status
Simulation time 94624356 ps
CPU time 1.24 seconds
Started Jul 24 06:01:45 PM PDT 24
Finished Jul 24 06:01:46 PM PDT 24
Peak memory 220048 kb
Host smart-6da55b13-2867-4908-a62a-3a81247208cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861435522 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3861435522
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.2392057391
Short name T714
Test name
Test status
Simulation time 125706346 ps
CPU time 0.94 seconds
Started Jul 24 06:01:44 PM PDT 24
Finished Jul 24 06:01:45 PM PDT 24
Peak memory 217476 kb
Host smart-b1a009f3-2c13-4d31-acb7-11e88158c640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392057391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2392057391
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2977872712
Short name T722
Test name
Test status
Simulation time 78845741 ps
CPU time 1.16 seconds
Started Jul 24 06:01:42 PM PDT 24
Finished Jul 24 06:01:43 PM PDT 24
Peak memory 218928 kb
Host smart-f55578ba-41b0-4c60-a30c-efbe6ebf7282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977872712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2977872712
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.1526319355
Short name T604
Test name
Test status
Simulation time 79573781 ps
CPU time 1.63 seconds
Started Jul 24 06:02:04 PM PDT 24
Finished Jul 24 06:02:06 PM PDT 24
Peak memory 217756 kb
Host smart-6c270b1b-e2b4-4819-bc10-051a73e7ab9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526319355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1526319355
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3821721656
Short name T905
Test name
Test status
Simulation time 47179170 ps
CPU time 1.17 seconds
Started Jul 24 06:01:51 PM PDT 24
Finished Jul 24 06:01:53 PM PDT 24
Peak memory 219108 kb
Host smart-4fc32800-717a-4fba-8010-4d38668ef7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821721656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3821721656
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.3540106069
Short name T689
Test name
Test status
Simulation time 52384473 ps
CPU time 1.14 seconds
Started Jul 24 06:01:57 PM PDT 24
Finished Jul 24 06:01:58 PM PDT 24
Peak memory 215476 kb
Host smart-f3060928-d1b1-40ce-a74d-1e85da6830b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540106069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3540106069
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2694896435
Short name T751
Test name
Test status
Simulation time 28976691 ps
CPU time 1.26 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 220040 kb
Host smart-f7fb4add-304f-4927-8d66-25043edbb1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694896435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2694896435
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2462741356
Short name T568
Test name
Test status
Simulation time 18999839 ps
CPU time 1 seconds
Started Jul 24 06:00:13 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 215348 kb
Host smart-d2c537a1-4cd3-4290-9287-da7812175420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462741356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2462741356
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2869948034
Short name T843
Test name
Test status
Simulation time 38244342 ps
CPU time 0.83 seconds
Started Jul 24 06:00:13 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 216704 kb
Host smart-8318e8c7-9f3f-4ec5-93cb-a1d5a87c0df0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869948034 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2869948034
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.23676142
Short name T468
Test name
Test status
Simulation time 41403043 ps
CPU time 1.05 seconds
Started Jul 24 06:00:13 PM PDT 24
Finished Jul 24 06:00:15 PM PDT 24
Peak memory 217180 kb
Host smart-836096b5-f5bb-4aa2-995e-55c88ffd4189
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23676142 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_dis
able_auto_req_mode.23676142
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1023593328
Short name T152
Test name
Test status
Simulation time 19559148 ps
CPU time 1.13 seconds
Started Jul 24 06:00:12 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 224296 kb
Host smart-a6a1ed91-8374-4fea-a43e-adb011019d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023593328 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1023593328
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2733973959
Short name T428
Test name
Test status
Simulation time 75553143 ps
CPU time 1.26 seconds
Started Jul 24 06:00:11 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 220504 kb
Host smart-8e188d88-a506-4743-a932-6083c90cd16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733973959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2733973959
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.4050085387
Short name T952
Test name
Test status
Simulation time 27103530 ps
CPU time 0.97 seconds
Started Jul 24 06:00:10 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 215960 kb
Host smart-e271b4b3-cfc2-486e-ba09-d5925816c0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050085387 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.4050085387
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1253685707
Short name T710
Test name
Test status
Simulation time 18105821 ps
CPU time 1.03 seconds
Started Jul 24 06:00:14 PM PDT 24
Finished Jul 24 06:00:16 PM PDT 24
Peak memory 215640 kb
Host smart-cc73e0d0-d877-4c48-98c3-d67c031e8be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253685707 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1253685707
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.422669843
Short name T805
Test name
Test status
Simulation time 67176742 ps
CPU time 1.97 seconds
Started Jul 24 06:00:10 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 217508 kb
Host smart-9e706877-f9f8-40d3-a5ea-dd1ba275f309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422669843 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.422669843
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3824369953
Short name T43
Test name
Test status
Simulation time 151009009394 ps
CPU time 648.45 seconds
Started Jul 24 06:00:15 PM PDT 24
Finished Jul 24 06:11:04 PM PDT 24
Peak memory 221268 kb
Host smart-4cabae41-2f1a-46fd-b33c-61c1bc5d2091
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824369953 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3824369953
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.2830697176
Short name T871
Test name
Test status
Simulation time 102017320 ps
CPU time 1.16 seconds
Started Jul 24 06:01:36 PM PDT 24
Finished Jul 24 06:01:37 PM PDT 24
Peak memory 220044 kb
Host smart-f215222a-f6a7-4207-9f90-4ebe12879763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830697176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2830697176
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.1196619469
Short name T712
Test name
Test status
Simulation time 134738257 ps
CPU time 0.98 seconds
Started Jul 24 06:01:51 PM PDT 24
Finished Jul 24 06:01:52 PM PDT 24
Peak memory 217600 kb
Host smart-9a63eeea-afb4-4e0a-b23e-51bc29c902ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196619469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1196619469
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3900518903
Short name T938
Test name
Test status
Simulation time 38808858 ps
CPU time 1.37 seconds
Started Jul 24 06:01:41 PM PDT 24
Finished Jul 24 06:01:42 PM PDT 24
Peak memory 216044 kb
Host smart-fd9ecf4b-b6f5-4e1b-8174-f972edcd6b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900518903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3900518903
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.2689753037
Short name T985
Test name
Test status
Simulation time 28903603 ps
CPU time 1.21 seconds
Started Jul 24 06:01:45 PM PDT 24
Finished Jul 24 06:01:47 PM PDT 24
Peak memory 217700 kb
Host smart-3c019f98-9980-4e03-96f7-e277e76af44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689753037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2689753037
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.1314479739
Short name T812
Test name
Test status
Simulation time 25311911 ps
CPU time 1.21 seconds
Started Jul 24 06:01:42 PM PDT 24
Finished Jul 24 06:01:43 PM PDT 24
Peak memory 220336 kb
Host smart-f66ff949-a8d1-4112-b4f3-79eac5861876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314479739 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.1314479739
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.1163460255
Short name T308
Test name
Test status
Simulation time 45499623 ps
CPU time 1.48 seconds
Started Jul 24 06:01:55 PM PDT 24
Finished Jul 24 06:01:57 PM PDT 24
Peak memory 217552 kb
Host smart-9db79b5d-8179-42a0-9676-5bc6cd22933b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163460255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1163460255
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.588790756
Short name T959
Test name
Test status
Simulation time 224694423 ps
CPU time 1.37 seconds
Started Jul 24 06:01:44 PM PDT 24
Finished Jul 24 06:01:46 PM PDT 24
Peak memory 220036 kb
Host smart-f117cd58-96b5-493a-9d6d-044e7220a6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588790756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.588790756
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.3113923586
Short name T530
Test name
Test status
Simulation time 49705397 ps
CPU time 1.23 seconds
Started Jul 24 06:01:41 PM PDT 24
Finished Jul 24 06:01:42 PM PDT 24
Peak memory 218908 kb
Host smart-46f79555-6158-4bde-8e60-1949c804cb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113923586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3113923586
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.646565991
Short name T820
Test name
Test status
Simulation time 27285724 ps
CPU time 1.22 seconds
Started Jul 24 06:01:41 PM PDT 24
Finished Jul 24 06:01:43 PM PDT 24
Peak memory 220160 kb
Host smart-e83fd3e4-bd99-4d55-9dcc-9fa2b057c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646565991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.646565991
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.1427485536
Short name T908
Test name
Test status
Simulation time 95670536 ps
CPU time 1.22 seconds
Started Jul 24 06:01:53 PM PDT 24
Finished Jul 24 06:01:55 PM PDT 24
Peak memory 217732 kb
Host smart-9ab53bb6-5ae9-4d13-8742-f35994c3799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427485536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1427485536
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.3108063640
Short name T93
Test name
Test status
Simulation time 120316363 ps
CPU time 1.09 seconds
Started Jul 24 06:02:01 PM PDT 24
Finished Jul 24 06:02:02 PM PDT 24
Peak memory 218980 kb
Host smart-1d2f03f5-d1a6-4072-adc1-24567dc384a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108063640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3108063640
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3423466457
Short name T925
Test name
Test status
Simulation time 47318714 ps
CPU time 1.43 seconds
Started Jul 24 06:02:01 PM PDT 24
Finished Jul 24 06:02:02 PM PDT 24
Peak memory 218932 kb
Host smart-25ab4ed3-f486-4aae-b609-932c1ac61c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423466457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3423466457
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.2121091305
Short name T296
Test name
Test status
Simulation time 26039144 ps
CPU time 1.19 seconds
Started Jul 24 06:01:40 PM PDT 24
Finished Jul 24 06:01:42 PM PDT 24
Peak memory 219888 kb
Host smart-132a7f35-9fef-45e4-ac3a-dd7918c60af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121091305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.2121091305
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.2103021028
Short name T681
Test name
Test status
Simulation time 68151837 ps
CPU time 1.1 seconds
Started Jul 24 06:01:49 PM PDT 24
Finished Jul 24 06:01:51 PM PDT 24
Peak memory 215620 kb
Host smart-d9021f0f-fba1-4f29-82ce-b8ba2c07f2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103021028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2103021028
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3646372390
Short name T541
Test name
Test status
Simulation time 93993019 ps
CPU time 1.3 seconds
Started Jul 24 06:01:38 PM PDT 24
Finished Jul 24 06:01:40 PM PDT 24
Peak memory 220084 kb
Host smart-f330e3de-8bb0-42ad-b494-2dd72ffb2a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646372390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3646372390
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.4219427590
Short name T876
Test name
Test status
Simulation time 51173953 ps
CPU time 1.79 seconds
Started Jul 24 06:01:46 PM PDT 24
Finished Jul 24 06:01:48 PM PDT 24
Peak memory 219036 kb
Host smart-9fa6747b-90bc-4070-ae1e-28feebd20b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219427590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.4219427590
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.2963984596
Short name T683
Test name
Test status
Simulation time 22990306 ps
CPU time 1.18 seconds
Started Jul 24 06:01:40 PM PDT 24
Finished Jul 24 06:01:41 PM PDT 24
Peak memory 219052 kb
Host smart-397fe819-9c9f-4c8a-908d-526b9e5509a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963984596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2963984596
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3564605814
Short name T870
Test name
Test status
Simulation time 106756995 ps
CPU time 1.62 seconds
Started Jul 24 06:01:43 PM PDT 24
Finished Jul 24 06:01:45 PM PDT 24
Peak memory 219232 kb
Host smart-6dada6c2-64fa-4fdc-bbf7-952c6d23a4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564605814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3564605814
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.708406395
Short name T974
Test name
Test status
Simulation time 111506467 ps
CPU time 1.16 seconds
Started Jul 24 06:01:40 PM PDT 24
Finished Jul 24 06:01:41 PM PDT 24
Peak memory 219444 kb
Host smart-67b613cc-a609-4a89-be4f-d930c72257e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708406395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.708406395
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.3961213355
Short name T376
Test name
Test status
Simulation time 141492090 ps
CPU time 1.34 seconds
Started Jul 24 06:01:44 PM PDT 24
Finished Jul 24 06:01:46 PM PDT 24
Peak memory 220064 kb
Host smart-89a9f232-6a99-4043-af29-4d92229c740e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961213355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3961213355
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert_test.3887589044
Short name T929
Test name
Test status
Simulation time 16296643 ps
CPU time 0.98 seconds
Started Jul 24 05:59:54 PM PDT 24
Finished Jul 24 05:59:55 PM PDT 24
Peak memory 215168 kb
Host smart-2e9222cb-3d0c-4d01-bf11-95d315c48f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887589044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3887589044
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.315213588
Short name T892
Test name
Test status
Simulation time 37863695 ps
CPU time 0.88 seconds
Started Jul 24 05:59:55 PM PDT 24
Finished Jul 24 05:59:56 PM PDT 24
Peak memory 216192 kb
Host smart-ab3b322d-a1a1-4bf5-8ab4-43a0f3bc0cf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315213588 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.315213588
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1543585831
Short name T104
Test name
Test status
Simulation time 40378743 ps
CPU time 1.02 seconds
Started Jul 24 05:59:55 PM PDT 24
Finished Jul 24 05:59:57 PM PDT 24
Peak memory 217232 kb
Host smart-242f6e27-5d7f-46da-9833-616d3909f004
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543585831 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1543585831
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.4022508742
Short name T198
Test name
Test status
Simulation time 19681672 ps
CPU time 1.22 seconds
Started Jul 24 05:59:54 PM PDT 24
Finished Jul 24 05:59:55 PM PDT 24
Peak memory 224316 kb
Host smart-c8193f96-2d7e-4c63-abad-a74153e00d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022508742 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.4022508742
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1764942517
Short name T511
Test name
Test status
Simulation time 61418178 ps
CPU time 1.65 seconds
Started Jul 24 05:59:51 PM PDT 24
Finished Jul 24 05:59:53 PM PDT 24
Peak memory 220612 kb
Host smart-06c329b5-6863-415c-bbf4-38e4f7cece37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764942517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1764942517
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_sec_cm.487961718
Short name T61
Test name
Test status
Simulation time 460747580 ps
CPU time 6.95 seconds
Started Jul 24 05:59:59 PM PDT 24
Finished Jul 24 06:00:06 PM PDT 24
Peak memory 236464 kb
Host smart-7be12bc6-a97c-45a5-ba4f-b92b7ab14339
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487961718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.487961718
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1241996501
Short name T226
Test name
Test status
Simulation time 26852165 ps
CPU time 0.93 seconds
Started Jul 24 05:59:54 PM PDT 24
Finished Jul 24 05:59:56 PM PDT 24
Peak memory 215616 kb
Host smart-b9deef7b-7de3-4865-bcae-df3363b9d099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241996501 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1241996501
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.488810171
Short name T330
Test name
Test status
Simulation time 35456967 ps
CPU time 1.34 seconds
Started Jul 24 05:59:57 PM PDT 24
Finished Jul 24 05:59:59 PM PDT 24
Peak memory 215576 kb
Host smart-4a9599bf-ec41-4481-aade-625bfd727d25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488810171 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.488810171
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_alert.327594610
Short name T669
Test name
Test status
Simulation time 61735636 ps
CPU time 1.06 seconds
Started Jul 24 06:00:16 PM PDT 24
Finished Jul 24 06:00:18 PM PDT 24
Peak memory 220140 kb
Host smart-efab6303-54e7-48ae-b80c-ca6611084050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327594610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.327594610
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3675650187
Short name T525
Test name
Test status
Simulation time 86272965 ps
CPU time 0.87 seconds
Started Jul 24 06:00:15 PM PDT 24
Finished Jul 24 06:00:16 PM PDT 24
Peak memory 207152 kb
Host smart-69429e38-03b1-4421-a863-c2578b95c443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675650187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3675650187
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3009113550
Short name T691
Test name
Test status
Simulation time 41484513 ps
CPU time 0.88 seconds
Started Jul 24 06:00:17 PM PDT 24
Finished Jul 24 06:00:18 PM PDT 24
Peak memory 216612 kb
Host smart-6ac8aaaa-5d19-4717-b6b2-32fc65ec45d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009113550 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3009113550
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.186298430
Short name T372
Test name
Test status
Simulation time 91957543 ps
CPU time 1.15 seconds
Started Jul 24 06:00:27 PM PDT 24
Finished Jul 24 06:00:28 PM PDT 24
Peak memory 217264 kb
Host smart-720cedda-bc5d-4f54-bd06-d3de98e9c083
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186298430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.186298430
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1048348247
Short name T988
Test name
Test status
Simulation time 21160120 ps
CPU time 1.11 seconds
Started Jul 24 06:00:20 PM PDT 24
Finished Jul 24 06:00:21 PM PDT 24
Peak memory 220060 kb
Host smart-ffda9e0e-2078-4262-b762-fa98f51f4079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048348247 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1048348247
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2072387317
Short name T333
Test name
Test status
Simulation time 49310997 ps
CPU time 1.79 seconds
Started Jul 24 06:00:22 PM PDT 24
Finished Jul 24 06:00:24 PM PDT 24
Peak memory 220528 kb
Host smart-52daa6cf-c5f5-4ff8-a33c-57f6f9a2914b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072387317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2072387317
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.669249200
Short name T867
Test name
Test status
Simulation time 53287401 ps
CPU time 1.01 seconds
Started Jul 24 06:00:14 PM PDT 24
Finished Jul 24 06:00:15 PM PDT 24
Peak memory 224124 kb
Host smart-318e0cfa-6023-406b-b9b8-b7c8705e3e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669249200 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.669249200
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3520437579
Short name T348
Test name
Test status
Simulation time 21415734 ps
CPU time 1 seconds
Started Jul 24 06:00:18 PM PDT 24
Finished Jul 24 06:00:19 PM PDT 24
Peak memory 215564 kb
Host smart-dab94aeb-4397-4ca8-941d-7c889b4462d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520437579 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3520437579
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2564192857
Short name T659
Test name
Test status
Simulation time 520536250 ps
CPU time 3.2 seconds
Started Jul 24 06:00:24 PM PDT 24
Finished Jul 24 06:00:28 PM PDT 24
Peak memory 220220 kb
Host smart-21c0d760-c9eb-4290-ad3b-c67d516a2ac6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564192857 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2564192857
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3090333255
Short name T942
Test name
Test status
Simulation time 71269126636 ps
CPU time 452.12 seconds
Started Jul 24 06:00:18 PM PDT 24
Finished Jul 24 06:07:50 PM PDT 24
Peak memory 218472 kb
Host smart-ddf8cedf-e1f1-45f4-af4d-1f1dd8ac9a5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090333255 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3090333255
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.136337123
Short name T434
Test name
Test status
Simulation time 137734090 ps
CPU time 2.24 seconds
Started Jul 24 06:01:54 PM PDT 24
Finished Jul 24 06:01:57 PM PDT 24
Peak memory 219152 kb
Host smart-3da2421d-6052-441c-b954-987f1f2e41a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136337123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.136337123
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2668600058
Short name T969
Test name
Test status
Simulation time 89272693 ps
CPU time 1.14 seconds
Started Jul 24 06:01:48 PM PDT 24
Finished Jul 24 06:01:49 PM PDT 24
Peak memory 217676 kb
Host smart-caaa8ea1-ef1b-4428-8ae7-6d13b6aa2eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668600058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2668600058
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3339712796
Short name T378
Test name
Test status
Simulation time 61199526 ps
CPU time 1.52 seconds
Started Jul 24 06:01:44 PM PDT 24
Finished Jul 24 06:01:46 PM PDT 24
Peak memory 219084 kb
Host smart-32c95e90-740a-4edb-92ca-d679e7f0f701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339712796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3339712796
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3263564
Short name T678
Test name
Test status
Simulation time 86981350 ps
CPU time 1.33 seconds
Started Jul 24 06:01:45 PM PDT 24
Finished Jul 24 06:01:47 PM PDT 24
Peak memory 219276 kb
Host smart-228dd59d-115e-4423-9a0e-779e80664919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3263564
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2559820080
Short name T750
Test name
Test status
Simulation time 72443239 ps
CPU time 1.94 seconds
Started Jul 24 06:01:55 PM PDT 24
Finished Jul 24 06:01:57 PM PDT 24
Peak memory 219052 kb
Host smart-ebd35ae5-6a7f-4027-8ffa-519c6f4d8f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559820080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2559820080
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.822510917
Short name T446
Test name
Test status
Simulation time 36743390 ps
CPU time 1.18 seconds
Started Jul 24 06:01:35 PM PDT 24
Finished Jul 24 06:01:37 PM PDT 24
Peak memory 215696 kb
Host smart-c650b973-f170-43a6-9859-afaf5fd2e52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822510917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.822510917
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2843657820
Short name T757
Test name
Test status
Simulation time 166625851 ps
CPU time 1.32 seconds
Started Jul 24 06:01:56 PM PDT 24
Finished Jul 24 06:01:57 PM PDT 24
Peak memory 219144 kb
Host smart-fb84a353-b270-439e-b85b-9e2da3080128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843657820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2843657820
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1795246964
Short name T642
Test name
Test status
Simulation time 80436382 ps
CPU time 1.15 seconds
Started Jul 24 06:01:47 PM PDT 24
Finished Jul 24 06:01:49 PM PDT 24
Peak memory 217520 kb
Host smart-715b56ab-f69d-47ae-b124-e152a9e9f5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795246964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1795246964
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2088332830
Short name T3
Test name
Test status
Simulation time 65461575 ps
CPU time 2.46 seconds
Started Jul 24 06:01:40 PM PDT 24
Finished Jul 24 06:01:43 PM PDT 24
Peak memory 217864 kb
Host smart-51f61f4f-de3d-4923-99f3-e0267ed7f265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088332830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2088332830
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1223339635
Short name T556
Test name
Test status
Simulation time 243304644 ps
CPU time 1.66 seconds
Started Jul 24 06:01:42 PM PDT 24
Finished Jul 24 06:01:44 PM PDT 24
Peak memory 219092 kb
Host smart-cd258344-2610-4542-b43a-4c522beb0976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223339635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1223339635
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1230545941
Short name T732
Test name
Test status
Simulation time 57887077 ps
CPU time 1.29 seconds
Started Jul 24 06:00:20 PM PDT 24
Finished Jul 24 06:00:22 PM PDT 24
Peak memory 216116 kb
Host smart-28c6b6ee-3ebf-4a3f-b020-795cb1c3125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230545941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1230545941
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3886814568
Short name T492
Test name
Test status
Simulation time 121432451 ps
CPU time 0.93 seconds
Started Jul 24 06:00:27 PM PDT 24
Finished Jul 24 06:00:29 PM PDT 24
Peak memory 215400 kb
Host smart-0a56f526-e39c-4804-8639-36ce11c26c59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886814568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3886814568
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.4229026985
Short name T932
Test name
Test status
Simulation time 10952348 ps
CPU time 0.87 seconds
Started Jul 24 06:00:23 PM PDT 24
Finished Jul 24 06:00:24 PM PDT 24
Peak memory 216548 kb
Host smart-9c6dc87e-8618-4955-93d6-b5d54da16e91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229026985 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4229026985
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2989916870
Short name T131
Test name
Test status
Simulation time 155873973 ps
CPU time 1.05 seconds
Started Jul 24 06:00:17 PM PDT 24
Finished Jul 24 06:00:18 PM PDT 24
Peak memory 217388 kb
Host smart-4a1f93ee-509b-4f87-a025-a01f7ff87108
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989916870 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2989916870
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_genbits.910905605
Short name T941
Test name
Test status
Simulation time 160821067 ps
CPU time 3.51 seconds
Started Jul 24 06:00:17 PM PDT 24
Finished Jul 24 06:00:21 PM PDT 24
Peak memory 220472 kb
Host smart-77bc9ecc-76ff-45f4-80ed-9bda25e274a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910905605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.910905605
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3350701188
Short name T992
Test name
Test status
Simulation time 30370001 ps
CPU time 1.19 seconds
Started Jul 24 06:00:24 PM PDT 24
Finished Jul 24 06:00:25 PM PDT 24
Peak memory 215728 kb
Host smart-ce31191c-56b8-4b5c-b6da-37119c59609c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350701188 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3350701188
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3125775045
Short name T399
Test name
Test status
Simulation time 19173549 ps
CPU time 1.05 seconds
Started Jul 24 06:00:16 PM PDT 24
Finished Jul 24 06:00:17 PM PDT 24
Peak memory 215608 kb
Host smart-bad540bf-1abb-4889-a9c6-9b08dbf6281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125775045 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3125775045
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2396337989
Short name T989
Test name
Test status
Simulation time 206748152 ps
CPU time 2.65 seconds
Started Jul 24 06:00:24 PM PDT 24
Finished Jul 24 06:00:27 PM PDT 24
Peak memory 217784 kb
Host smart-2458e26e-9947-4919-97cb-b3928c0d3088
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396337989 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2396337989
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2849522224
Short name T380
Test name
Test status
Simulation time 213691950682 ps
CPU time 1336.53 seconds
Started Jul 24 06:00:22 PM PDT 24
Finished Jul 24 06:22:38 PM PDT 24
Peak memory 226124 kb
Host smart-20577676-debd-49b2-aa0c-d8bf84b2742e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849522224 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2849522224
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3591198611
Short name T598
Test name
Test status
Simulation time 47961894 ps
CPU time 1.15 seconds
Started Jul 24 06:01:41 PM PDT 24
Finished Jul 24 06:01:42 PM PDT 24
Peak memory 217816 kb
Host smart-51b4919c-ebc1-4357-8124-10e2511c7f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591198611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3591198611
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3898020864
Short name T543
Test name
Test status
Simulation time 49855882 ps
CPU time 1.44 seconds
Started Jul 24 06:01:43 PM PDT 24
Finished Jul 24 06:01:44 PM PDT 24
Peak memory 218744 kb
Host smart-e7c394cf-e6e8-420f-ac09-9c82410b519a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898020864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3898020864
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3682017412
Short name T499
Test name
Test status
Simulation time 34876840 ps
CPU time 1.08 seconds
Started Jul 24 06:01:41 PM PDT 24
Finished Jul 24 06:01:42 PM PDT 24
Peak memory 218864 kb
Host smart-fcdf4c8e-4fac-4cd9-b5dd-7dba7388beaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682017412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3682017412
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1550099419
Short name T518
Test name
Test status
Simulation time 62911824 ps
CPU time 1.32 seconds
Started Jul 24 06:01:41 PM PDT 24
Finished Jul 24 06:01:43 PM PDT 24
Peak memory 219096 kb
Host smart-4012f6f4-1224-412e-9e69-93a2effe703f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550099419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1550099419
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2128492884
Short name T920
Test name
Test status
Simulation time 137156241 ps
CPU time 1.11 seconds
Started Jul 24 06:01:48 PM PDT 24
Finished Jul 24 06:01:50 PM PDT 24
Peak memory 217456 kb
Host smart-b806ae2d-827d-481d-ad6e-044ba3a01309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128492884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2128492884
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2139207984
Short name T854
Test name
Test status
Simulation time 35311096 ps
CPU time 1.51 seconds
Started Jul 24 06:01:59 PM PDT 24
Finished Jul 24 06:02:01 PM PDT 24
Peak memory 218860 kb
Host smart-0e7fe18e-ce99-4910-a0e3-8e32bcfe01d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139207984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2139207984
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.135389105
Short name T571
Test name
Test status
Simulation time 40129521 ps
CPU time 1.47 seconds
Started Jul 24 06:01:36 PM PDT 24
Finished Jul 24 06:01:37 PM PDT 24
Peak memory 218768 kb
Host smart-3c317a2c-8d34-46e3-9177-5a75f778d7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135389105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.135389105
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3748656236
Short name T544
Test name
Test status
Simulation time 43295799 ps
CPU time 1.47 seconds
Started Jul 24 06:01:49 PM PDT 24
Finished Jul 24 06:01:50 PM PDT 24
Peak memory 219772 kb
Host smart-f9b17115-8a98-47b0-8480-5198a9592d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748656236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3748656236
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3539107180
Short name T309
Test name
Test status
Simulation time 79250643 ps
CPU time 1.81 seconds
Started Jul 24 06:01:42 PM PDT 24
Finished Jul 24 06:01:44 PM PDT 24
Peak memory 219016 kb
Host smart-95dee3a5-f231-4194-b784-ecf6990fbe00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539107180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3539107180
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2979861402
Short name T564
Test name
Test status
Simulation time 69175503 ps
CPU time 1.48 seconds
Started Jul 24 06:02:01 PM PDT 24
Finished Jul 24 06:02:03 PM PDT 24
Peak memory 219264 kb
Host smart-58664d50-5d3b-4cb4-b6f0-74e020a6d34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979861402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2979861402
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.130420509
Short name T576
Test name
Test status
Simulation time 24051061 ps
CPU time 1.15 seconds
Started Jul 24 06:00:17 PM PDT 24
Finished Jul 24 06:00:18 PM PDT 24
Peak memory 220276 kb
Host smart-6d515c00-42f1-4200-b07a-ccfed0908eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130420509 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.130420509
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.218427662
Short name T944
Test name
Test status
Simulation time 30069582 ps
CPU time 1.13 seconds
Started Jul 24 06:00:20 PM PDT 24
Finished Jul 24 06:00:21 PM PDT 24
Peak memory 207232 kb
Host smart-499c0c7c-0731-4f87-8e15-bcadb299221f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218427662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.218427662
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2214725231
Short name T151
Test name
Test status
Simulation time 22364811 ps
CPU time 0.91 seconds
Started Jul 24 06:00:26 PM PDT 24
Finished Jul 24 06:00:27 PM PDT 24
Peak memory 216572 kb
Host smart-4cbc75f1-b7ed-4a95-a227-2b7b952a263a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214725231 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2214725231
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1293404430
Short name T77
Test name
Test status
Simulation time 35150678 ps
CPU time 1.25 seconds
Started Jul 24 06:00:18 PM PDT 24
Finished Jul 24 06:00:19 PM PDT 24
Peak memory 219740 kb
Host smart-4ad4ab7a-fc9d-4121-a43f-ac3fd2e91989
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293404430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1293404430
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1562532685
Short name T143
Test name
Test status
Simulation time 24264101 ps
CPU time 0.88 seconds
Started Jul 24 06:00:18 PM PDT 24
Finished Jul 24 06:00:19 PM PDT 24
Peak memory 218552 kb
Host smart-95e93959-441a-4c2b-86b5-0cec6c6c7150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562532685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1562532685
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.498481477
Short name T794
Test name
Test status
Simulation time 107753012 ps
CPU time 1.32 seconds
Started Jul 24 06:00:16 PM PDT 24
Finished Jul 24 06:00:17 PM PDT 24
Peak memory 217656 kb
Host smart-82da08f9-e283-4221-9dcb-88f05b1d71c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498481477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.498481477
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2361100050
Short name T473
Test name
Test status
Simulation time 38504983 ps
CPU time 0.91 seconds
Started Jul 24 06:00:21 PM PDT 24
Finished Jul 24 06:00:22 PM PDT 24
Peak memory 215720 kb
Host smart-c7c7e082-3ae9-4a68-89a3-3998c922252c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361100050 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2361100050
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1112046183
Short name T353
Test name
Test status
Simulation time 26472284 ps
CPU time 0.96 seconds
Started Jul 24 06:00:23 PM PDT 24
Finished Jul 24 06:00:25 PM PDT 24
Peak memory 215624 kb
Host smart-2ca7d416-529b-4204-bc14-b95794f46b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112046183 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1112046183
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1879603830
Short name T191
Test name
Test status
Simulation time 162089316 ps
CPU time 2.09 seconds
Started Jul 24 06:00:20 PM PDT 24
Finished Jul 24 06:00:22 PM PDT 24
Peak memory 220488 kb
Host smart-8899b20e-3d26-4b86-80c4-88bff57f5989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879603830 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1879603830
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3215441522
Short name T825
Test name
Test status
Simulation time 120100065858 ps
CPU time 816.3 seconds
Started Jul 24 06:00:16 PM PDT 24
Finished Jul 24 06:13:53 PM PDT 24
Peak memory 223024 kb
Host smart-89d9b29f-5788-4f38-b90f-4d57529f3efa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215441522 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3215441522
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.963714470
Short name T582
Test name
Test status
Simulation time 53284925 ps
CPU time 1.04 seconds
Started Jul 24 06:01:45 PM PDT 24
Finished Jul 24 06:01:46 PM PDT 24
Peak memory 217768 kb
Host smart-984dab30-9c32-47af-9f2f-088154d6444a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963714470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.963714470
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1851828020
Short name T736
Test name
Test status
Simulation time 45918696 ps
CPU time 1.28 seconds
Started Jul 24 06:01:44 PM PDT 24
Finished Jul 24 06:01:46 PM PDT 24
Peak memory 218752 kb
Host smart-b2741ffd-7e2f-4e91-be9f-4eee30bdd8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851828020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1851828020
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2129353802
Short name T875
Test name
Test status
Simulation time 59528815 ps
CPU time 1.35 seconds
Started Jul 24 06:02:04 PM PDT 24
Finished Jul 24 06:02:06 PM PDT 24
Peak memory 218856 kb
Host smart-48530b56-2003-4742-aa80-7fd0aae1bdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129353802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2129353802
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.601669762
Short name T546
Test name
Test status
Simulation time 53949196 ps
CPU time 1.42 seconds
Started Jul 24 06:01:45 PM PDT 24
Finished Jul 24 06:01:47 PM PDT 24
Peak memory 218864 kb
Host smart-be435dc0-d6a5-411f-84c9-3ef6caaa9bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601669762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.601669762
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.253910322
Short name T671
Test name
Test status
Simulation time 156073541 ps
CPU time 1.08 seconds
Started Jul 24 06:01:56 PM PDT 24
Finished Jul 24 06:01:58 PM PDT 24
Peak memory 217604 kb
Host smart-81688bd1-edfe-440a-a725-770e8e9a1807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253910322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.253910322
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3823810291
Short name T741
Test name
Test status
Simulation time 55508378 ps
CPU time 1.27 seconds
Started Jul 24 06:01:52 PM PDT 24
Finished Jul 24 06:01:53 PM PDT 24
Peak memory 220304 kb
Host smart-e2868bac-aff4-48cb-aa20-a2c99a060686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823810291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3823810291
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.229795785
Short name T583
Test name
Test status
Simulation time 55922028 ps
CPU time 1.1 seconds
Started Jul 24 06:02:07 PM PDT 24
Finished Jul 24 06:02:09 PM PDT 24
Peak memory 218844 kb
Host smart-ad0e233e-98ef-40fd-a17e-9bda65578658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229795785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.229795785
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2257106201
Short name T602
Test name
Test status
Simulation time 59523147 ps
CPU time 1.17 seconds
Started Jul 24 06:02:01 PM PDT 24
Finished Jul 24 06:02:02 PM PDT 24
Peak memory 219208 kb
Host smart-bb8e91c4-920e-48b8-8717-50444dafe39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257106201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2257106201
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1636842431
Short name T516
Test name
Test status
Simulation time 79651300 ps
CPU time 1.04 seconds
Started Jul 24 06:01:51 PM PDT 24
Finished Jul 24 06:01:53 PM PDT 24
Peak memory 220072 kb
Host smart-f25eb883-674b-44da-81ce-6db4c5107a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636842431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1636842431
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3216135232
Short name T565
Test name
Test status
Simulation time 100379096 ps
CPU time 1.14 seconds
Started Jul 24 06:00:23 PM PDT 24
Finished Jul 24 06:00:24 PM PDT 24
Peak memory 221004 kb
Host smart-0933e8cc-40ab-4cd5-9337-a2f30992d040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216135232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3216135232
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1717925441
Short name T981
Test name
Test status
Simulation time 22594406 ps
CPU time 0.85 seconds
Started Jul 24 06:00:17 PM PDT 24
Finished Jul 24 06:00:18 PM PDT 24
Peak memory 214996 kb
Host smart-22d5d44a-0e70-4a3c-8717-ae973e8cda21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717925441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1717925441
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3930596776
Short name T621
Test name
Test status
Simulation time 17661679 ps
CPU time 0.86 seconds
Started Jul 24 06:00:17 PM PDT 24
Finished Jul 24 06:00:18 PM PDT 24
Peak memory 216248 kb
Host smart-a4ec3eed-14a8-42ef-8811-bd64729c242a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930596776 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3930596776
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3524258839
Short name T853
Test name
Test status
Simulation time 48291680 ps
CPU time 1.09 seconds
Started Jul 24 06:00:22 PM PDT 24
Finished Jul 24 06:00:23 PM PDT 24
Peak memory 218848 kb
Host smart-16090646-2be8-4f9a-84cb-98e33818d982
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524258839 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3524258839
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_genbits.1321918225
Short name T718
Test name
Test status
Simulation time 68426410 ps
CPU time 1.08 seconds
Started Jul 24 06:00:26 PM PDT 24
Finished Jul 24 06:00:28 PM PDT 24
Peak memory 220140 kb
Host smart-52403161-72c9-473a-b204-cbc79b281aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321918225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1321918225
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.201890695
Short name T897
Test name
Test status
Simulation time 44891900 ps
CPU time 0.91 seconds
Started Jul 24 06:00:22 PM PDT 24
Finished Jul 24 06:00:28 PM PDT 24
Peak memory 215588 kb
Host smart-4669342b-3847-4666-b10e-dced87bfc4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201890695 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.201890695
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1491341860
Short name T826
Test name
Test status
Simulation time 81075666 ps
CPU time 2.18 seconds
Started Jul 24 06:00:18 PM PDT 24
Finished Jul 24 06:00:21 PM PDT 24
Peak memory 217704 kb
Host smart-19a6ea73-8738-458c-b14c-700e2ff6133a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491341860 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1491341860
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2249936410
Short name T532
Test name
Test status
Simulation time 58117883576 ps
CPU time 748.48 seconds
Started Jul 24 06:00:26 PM PDT 24
Finished Jul 24 06:12:55 PM PDT 24
Peak memory 220704 kb
Host smart-04ed36d8-e65a-4f5f-a832-f45fd8102ce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249936410 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2249936410
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.192856351
Short name T729
Test name
Test status
Simulation time 50345844 ps
CPU time 1.25 seconds
Started Jul 24 06:01:44 PM PDT 24
Finished Jul 24 06:01:46 PM PDT 24
Peak memory 220048 kb
Host smart-ec0a9e73-6f5e-445b-8f82-d45462f3d62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192856351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.192856351
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.276055947
Short name T663
Test name
Test status
Simulation time 66947859 ps
CPU time 1.67 seconds
Started Jul 24 06:01:50 PM PDT 24
Finished Jul 24 06:01:52 PM PDT 24
Peak memory 218764 kb
Host smart-104e558a-940f-471c-b0f6-040249bb772e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276055947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.276055947
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.130635882
Short name T453
Test name
Test status
Simulation time 94516921 ps
CPU time 1.46 seconds
Started Jul 24 06:01:56 PM PDT 24
Finished Jul 24 06:01:57 PM PDT 24
Peak memory 218884 kb
Host smart-ed0d46c7-5e82-47df-9119-28edcc976b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130635882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.130635882
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3834638574
Short name T894
Test name
Test status
Simulation time 67502177 ps
CPU time 1.23 seconds
Started Jul 24 06:01:46 PM PDT 24
Finished Jul 24 06:01:48 PM PDT 24
Peak memory 219576 kb
Host smart-87eeb169-81ec-48da-9881-e7c0af7ca9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834638574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3834638574
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2668482259
Short name T580
Test name
Test status
Simulation time 56412780 ps
CPU time 1.01 seconds
Started Jul 24 06:01:58 PM PDT 24
Finished Jul 24 06:01:59 PM PDT 24
Peak memory 217500 kb
Host smart-1b3a195b-41c8-47cb-96ec-aee5d534cb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668482259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2668482259
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3525121852
Short name T62
Test name
Test status
Simulation time 71178647 ps
CPU time 0.95 seconds
Started Jul 24 06:01:46 PM PDT 24
Finished Jul 24 06:01:47 PM PDT 24
Peak memory 217892 kb
Host smart-5727b959-7dee-4f74-926b-aa1c2175a486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525121852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3525121852
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.450734137
Short name T765
Test name
Test status
Simulation time 35792140 ps
CPU time 1.32 seconds
Started Jul 24 06:01:43 PM PDT 24
Finished Jul 24 06:01:45 PM PDT 24
Peak memory 217576 kb
Host smart-040aa297-f8b2-49ea-a8f8-4c1cb804e5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450734137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.450734137
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.122481221
Short name T235
Test name
Test status
Simulation time 49202182 ps
CPU time 1.39 seconds
Started Jul 24 06:02:03 PM PDT 24
Finished Jul 24 06:02:05 PM PDT 24
Peak memory 219028 kb
Host smart-04dc1693-e956-40aa-b9d0-0ceaf4f88f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122481221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.122481221
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1733287062
Short name T625
Test name
Test status
Simulation time 33427816 ps
CPU time 1.3 seconds
Started Jul 24 06:02:03 PM PDT 24
Finished Jul 24 06:02:05 PM PDT 24
Peak memory 217692 kb
Host smart-f519748a-42d2-47fc-9b87-522a493215e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733287062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1733287062
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3531329128
Short name T548
Test name
Test status
Simulation time 242600486 ps
CPU time 1 seconds
Started Jul 24 06:01:45 PM PDT 24
Finished Jul 24 06:01:46 PM PDT 24
Peak memory 217492 kb
Host smart-0c71cc61-8568-480c-9f41-ae7d3550eb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531329128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3531329128
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3167902217
Short name T218
Test name
Test status
Simulation time 31454334 ps
CPU time 1.17 seconds
Started Jul 24 06:00:23 PM PDT 24
Finished Jul 24 06:00:25 PM PDT 24
Peak memory 219184 kb
Host smart-9f6c9b9a-35fa-4297-9b92-848294c6e99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167902217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3167902217
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2039041645
Short name T542
Test name
Test status
Simulation time 13429831 ps
CPU time 0.92 seconds
Started Jul 24 06:00:24 PM PDT 24
Finished Jul 24 06:00:25 PM PDT 24
Peak memory 207240 kb
Host smart-ef9e14af-80c9-4248-9495-15fd68965f47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039041645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2039041645
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1898723595
Short name T112
Test name
Test status
Simulation time 37119483 ps
CPU time 1.02 seconds
Started Jul 24 06:00:17 PM PDT 24
Finished Jul 24 06:00:18 PM PDT 24
Peak memory 217240 kb
Host smart-72afc0bc-024b-42ce-96b4-ad1bf4447c64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898723595 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1898723595
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3213448507
Short name T154
Test name
Test status
Simulation time 44580370 ps
CPU time 0.92 seconds
Started Jul 24 06:00:24 PM PDT 24
Finished Jul 24 06:00:26 PM PDT 24
Peak memory 224156 kb
Host smart-2991597f-dd21-45ec-adbf-512091e967c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213448507 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3213448507
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_intr.394680934
Short name T51
Test name
Test status
Simulation time 30699321 ps
CPU time 0.99 seconds
Started Jul 24 06:00:17 PM PDT 24
Finished Jul 24 06:00:18 PM PDT 24
Peak memory 224184 kb
Host smart-8cd83668-a5b9-43f0-9660-4c5196dd74c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394680934 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.394680934
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1724757860
Short name T594
Test name
Test status
Simulation time 50077587 ps
CPU time 0.92 seconds
Started Jul 24 06:00:26 PM PDT 24
Finished Jul 24 06:00:27 PM PDT 24
Peak memory 215536 kb
Host smart-1f04e8df-3589-43a9-9976-67eedae64c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724757860 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1724757860
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2628106811
Short name T573
Test name
Test status
Simulation time 157034466 ps
CPU time 1.53 seconds
Started Jul 24 06:00:24 PM PDT 24
Finished Jul 24 06:00:26 PM PDT 24
Peak memory 215608 kb
Host smart-a4b999b9-0f09-4636-9049-c85e6a9216dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628106811 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2628106811
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.268102038
Short name T823
Test name
Test status
Simulation time 506720802309 ps
CPU time 2761.73 seconds
Started Jul 24 06:00:27 PM PDT 24
Finished Jul 24 06:46:29 PM PDT 24
Peak memory 230532 kb
Host smart-f62078a3-1931-4ed0-942e-57345a1588d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268102038 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.268102038
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/241.edn_genbits.1000227712
Short name T335
Test name
Test status
Simulation time 63234755 ps
CPU time 2.22 seconds
Started Jul 24 06:01:49 PM PDT 24
Finished Jul 24 06:01:52 PM PDT 24
Peak memory 220584 kb
Host smart-4ab1bb10-04ef-48ee-bdef-305626338f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000227712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1000227712
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1772503296
Short name T407
Test name
Test status
Simulation time 41400564 ps
CPU time 1.03 seconds
Started Jul 24 06:01:43 PM PDT 24
Finished Jul 24 06:01:45 PM PDT 24
Peak memory 217564 kb
Host smart-b4e0f37c-0640-49f9-8a26-18284c08a900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772503296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1772503296
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3945883432
Short name T326
Test name
Test status
Simulation time 200972159 ps
CPU time 1.59 seconds
Started Jul 24 06:01:48 PM PDT 24
Finished Jul 24 06:01:49 PM PDT 24
Peak memory 219140 kb
Host smart-f28a2193-3f9e-4a70-901c-a782aa38a120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945883432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3945883432
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1533952988
Short name T352
Test name
Test status
Simulation time 38200344 ps
CPU time 1.34 seconds
Started Jul 24 06:01:58 PM PDT 24
Finished Jul 24 06:02:00 PM PDT 24
Peak memory 218916 kb
Host smart-51c575d7-fcde-46a9-a806-1ccf362334d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533952988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1533952988
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2647293950
Short name T888
Test name
Test status
Simulation time 86808567 ps
CPU time 1.23 seconds
Started Jul 24 06:01:45 PM PDT 24
Finished Jul 24 06:01:47 PM PDT 24
Peak memory 219132 kb
Host smart-226fa838-e426-497b-9abe-93f3a5530230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647293950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2647293950
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3229385936
Short name T529
Test name
Test status
Simulation time 39346665 ps
CPU time 1.06 seconds
Started Jul 24 06:01:49 PM PDT 24
Finished Jul 24 06:01:50 PM PDT 24
Peak memory 217584 kb
Host smart-5014094b-4858-4675-b093-bf7b20eef722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229385936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3229385936
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3739945877
Short name T519
Test name
Test status
Simulation time 107273645 ps
CPU time 1.5 seconds
Started Jul 24 06:02:00 PM PDT 24
Finished Jul 24 06:02:02 PM PDT 24
Peak memory 217872 kb
Host smart-9e17bdfb-a132-4f2a-b1ab-f39945be28ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739945877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3739945877
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3955513393
Short name T13
Test name
Test status
Simulation time 84722376 ps
CPU time 1.53 seconds
Started Jul 24 06:02:01 PM PDT 24
Finished Jul 24 06:02:03 PM PDT 24
Peak memory 219248 kb
Host smart-bc94b6aa-dc36-4a73-9cd3-9342613997cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955513393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3955513393
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3957324138
Short name T945
Test name
Test status
Simulation time 73447410 ps
CPU time 1.08 seconds
Started Jul 24 06:01:45 PM PDT 24
Finished Jul 24 06:01:47 PM PDT 24
Peak memory 217860 kb
Host smart-66c99d33-b88e-48a6-b41e-5ea71f4fb301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957324138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3957324138
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2323582471
Short name T208
Test name
Test status
Simulation time 53984952 ps
CPU time 1.25 seconds
Started Jul 24 06:00:21 PM PDT 24
Finished Jul 24 06:00:23 PM PDT 24
Peak memory 216064 kb
Host smart-c582fb60-6d4f-4c2a-a953-9d772f429c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323582471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2323582471
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1675560307
Short name T374
Test name
Test status
Simulation time 35819228 ps
CPU time 0.87 seconds
Started Jul 24 06:00:23 PM PDT 24
Finished Jul 24 06:00:24 PM PDT 24
Peak memory 207020 kb
Host smart-b7374e19-bae7-4b5a-9429-4a3fbe1af791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675560307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1675560307
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1665030137
Short name T176
Test name
Test status
Simulation time 19658238 ps
CPU time 0.85 seconds
Started Jul 24 06:00:22 PM PDT 24
Finished Jul 24 06:00:23 PM PDT 24
Peak memory 216560 kb
Host smart-e12595f1-38f1-4993-9cac-97798bfac5b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665030137 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1665030137
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1342746802
Short name T629
Test name
Test status
Simulation time 30876976 ps
CPU time 1.12 seconds
Started Jul 24 06:00:23 PM PDT 24
Finished Jul 24 06:00:25 PM PDT 24
Peak memory 217164 kb
Host smart-dd41d415-7fde-4417-8307-ecf7255b51f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342746802 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1342746802
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2719136700
Short name T345
Test name
Test status
Simulation time 23877132 ps
CPU time 1.13 seconds
Started Jul 24 06:00:28 PM PDT 24
Finished Jul 24 06:00:29 PM PDT 24
Peak memory 220220 kb
Host smart-3c0110a2-3c1e-4fcf-8fe6-44ad9c941878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719136700 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2719136700
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2808236190
Short name T887
Test name
Test status
Simulation time 23363005 ps
CPU time 1.07 seconds
Started Jul 24 06:00:21 PM PDT 24
Finished Jul 24 06:00:22 PM PDT 24
Peak memory 217628 kb
Host smart-dbea4322-6b58-4d11-8ff9-b2cb0a18b739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808236190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2808236190
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.4138373229
Short name T828
Test name
Test status
Simulation time 22045099 ps
CPU time 1.23 seconds
Started Jul 24 06:00:21 PM PDT 24
Finished Jul 24 06:00:22 PM PDT 24
Peak memory 224312 kb
Host smart-44ff9dcf-e492-4a21-855c-1d8587952d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138373229 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.4138373229
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.153714035
Short name T357
Test name
Test status
Simulation time 21433504 ps
CPU time 0.9 seconds
Started Jul 24 06:00:22 PM PDT 24
Finished Jul 24 06:00:23 PM PDT 24
Peak memory 215664 kb
Host smart-dee412d8-4c51-4ceb-9c9e-38b1dcb0b7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153714035 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.153714035
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3949934500
Short name T540
Test name
Test status
Simulation time 848057803 ps
CPU time 3.26 seconds
Started Jul 24 06:00:22 PM PDT 24
Finished Jul 24 06:00:26 PM PDT 24
Peak memory 215672 kb
Host smart-fc3768a3-7bd4-4586-8e8d-680191606877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949934500 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3949934500
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2469260542
Short name T220
Test name
Test status
Simulation time 55015196779 ps
CPU time 1164.5 seconds
Started Jul 24 06:00:32 PM PDT 24
Finished Jul 24 06:19:57 PM PDT 24
Peak memory 220088 kb
Host smart-9956a920-3b1c-43dc-bb20-7509cef79634
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469260542 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2469260542
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2178302939
Short name T447
Test name
Test status
Simulation time 63294042 ps
CPU time 1.24 seconds
Started Jul 24 06:01:45 PM PDT 24
Finished Jul 24 06:01:47 PM PDT 24
Peak memory 219124 kb
Host smart-6367e983-e0c5-4be4-85d2-5f343f681734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178302939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2178302939
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1388981305
Short name T880
Test name
Test status
Simulation time 57246145 ps
CPU time 1.05 seconds
Started Jul 24 06:01:46 PM PDT 24
Finished Jul 24 06:01:47 PM PDT 24
Peak memory 217628 kb
Host smart-e3a13217-c929-4940-b2d4-82132bf4fe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388981305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1388981305
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.252971016
Short name T423
Test name
Test status
Simulation time 34412386 ps
CPU time 1.26 seconds
Started Jul 24 06:01:58 PM PDT 24
Finished Jul 24 06:02:00 PM PDT 24
Peak memory 218656 kb
Host smart-0ee09e06-aa44-4ef3-ae5b-4376b1f07c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252971016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.252971016
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2858921400
Short name T977
Test name
Test status
Simulation time 155853378 ps
CPU time 1.23 seconds
Started Jul 24 06:01:53 PM PDT 24
Finished Jul 24 06:01:54 PM PDT 24
Peak memory 217532 kb
Host smart-8209a7d1-307d-4163-850b-9b855ab564fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858921400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2858921400
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2355917220
Short name T849
Test name
Test status
Simulation time 23774985 ps
CPU time 1.15 seconds
Started Jul 24 06:01:46 PM PDT 24
Finished Jul 24 06:01:47 PM PDT 24
Peak memory 217604 kb
Host smart-d12ad13e-6b3e-490d-ac70-45737372267c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355917220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2355917220
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.4070271665
Short name T405
Test name
Test status
Simulation time 29003665 ps
CPU time 1.32 seconds
Started Jul 24 06:01:46 PM PDT 24
Finished Jul 24 06:01:48 PM PDT 24
Peak memory 220012 kb
Host smart-233778d2-f0aa-4aed-9bd0-2cd5267cfd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070271665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.4070271665
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1491801176
Short name T336
Test name
Test status
Simulation time 50446838 ps
CPU time 1.57 seconds
Started Jul 24 06:01:51 PM PDT 24
Finished Jul 24 06:01:52 PM PDT 24
Peak memory 218820 kb
Host smart-2d757a1d-bdd8-4b5f-83c9-328124b96b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491801176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1491801176
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.866802273
Short name T356
Test name
Test status
Simulation time 60726188 ps
CPU time 1.76 seconds
Started Jul 24 06:01:45 PM PDT 24
Finished Jul 24 06:01:47 PM PDT 24
Peak memory 219156 kb
Host smart-bf8cbcb9-3997-4f58-9758-913be537f04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866802273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.866802273
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.576061579
Short name T91
Test name
Test status
Simulation time 156037460 ps
CPU time 2.56 seconds
Started Jul 24 06:02:06 PM PDT 24
Finished Jul 24 06:02:08 PM PDT 24
Peak memory 220648 kb
Host smart-b9e40cde-48f6-4043-9f3b-fc4348bb0a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576061579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.576061579
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.4156508692
Short name T730
Test name
Test status
Simulation time 58135325 ps
CPU time 1.12 seconds
Started Jul 24 06:02:03 PM PDT 24
Finished Jul 24 06:02:04 PM PDT 24
Peak memory 217576 kb
Host smart-150d5718-b96b-4d31-9cf7-bb0a8a774a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156508692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.4156508692
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1553961326
Short name T789
Test name
Test status
Simulation time 60707675 ps
CPU time 1.09 seconds
Started Jul 24 06:00:26 PM PDT 24
Finished Jul 24 06:00:27 PM PDT 24
Peak memory 220120 kb
Host smart-3a24e7ae-5241-4370-9376-6d9250fcaf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553961326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1553961326
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2509272791
Short name T474
Test name
Test status
Simulation time 44461500 ps
CPU time 0.91 seconds
Started Jul 24 06:00:22 PM PDT 24
Finished Jul 24 06:00:23 PM PDT 24
Peak memory 215444 kb
Host smart-cfeea8b6-eda8-4b0b-80d2-4ea864403901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509272791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2509272791
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3247300777
Short name T991
Test name
Test status
Simulation time 11772433 ps
CPU time 0.9 seconds
Started Jul 24 06:00:25 PM PDT 24
Finished Jul 24 06:00:26 PM PDT 24
Peak memory 215980 kb
Host smart-22d9558b-404e-49e0-a34c-9d50523aa665
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247300777 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3247300777
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.537581262
Short name T113
Test name
Test status
Simulation time 36171034 ps
CPU time 1.22 seconds
Started Jul 24 06:00:22 PM PDT 24
Finished Jul 24 06:00:23 PM PDT 24
Peak memory 217300 kb
Host smart-7c39f683-68c0-4009-ac26-202a1e3e9f4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537581262 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.537581262
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1918117019
Short name T510
Test name
Test status
Simulation time 25621709 ps
CPU time 1.04 seconds
Started Jul 24 06:00:26 PM PDT 24
Finished Jul 24 06:00:27 PM PDT 24
Peak memory 224276 kb
Host smart-fe372f9e-4205-493e-97d5-546f92c4cda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918117019 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1918117019
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2491485347
Short name T704
Test name
Test status
Simulation time 50929170 ps
CPU time 1.21 seconds
Started Jul 24 06:00:24 PM PDT 24
Finished Jul 24 06:00:25 PM PDT 24
Peak memory 217636 kb
Host smart-2aea8be8-57bc-4769-a220-159200e46f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491485347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2491485347
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1628936059
Short name T592
Test name
Test status
Simulation time 37237872 ps
CPU time 0.89 seconds
Started Jul 24 06:00:25 PM PDT 24
Finished Jul 24 06:00:26 PM PDT 24
Peak memory 215792 kb
Host smart-8271b680-7500-4735-88ff-809bf3c5642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628936059 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1628936059
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3028457766
Short name T517
Test name
Test status
Simulation time 17246952 ps
CPU time 1.07 seconds
Started Jul 24 06:00:23 PM PDT 24
Finished Jul 24 06:00:25 PM PDT 24
Peak memory 215596 kb
Host smart-ee5ff26c-37e3-4e6f-9934-ea01a38ccefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028457766 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3028457766
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1229940965
Short name T305
Test name
Test status
Simulation time 374750520 ps
CPU time 5.38 seconds
Started Jul 24 06:00:26 PM PDT 24
Finished Jul 24 06:00:32 PM PDT 24
Peak memory 217504 kb
Host smart-4704fdf3-f090-4770-be89-efbf7cc3fedf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229940965 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1229940965
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3945914602
Short name T233
Test name
Test status
Simulation time 542372401873 ps
CPU time 1398.28 seconds
Started Jul 24 06:00:32 PM PDT 24
Finished Jul 24 06:23:50 PM PDT 24
Peak memory 224048 kb
Host smart-2beef0e7-35ba-4dbc-b9b9-1ea14354c93c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945914602 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3945914602
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1810757807
Short name T338
Test name
Test status
Simulation time 45420789 ps
CPU time 1.57 seconds
Started Jul 24 06:02:03 PM PDT 24
Finished Jul 24 06:02:05 PM PDT 24
Peak memory 218972 kb
Host smart-3cf16bb1-8f3a-4d08-824e-9a68e6109b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810757807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1810757807
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.4121250271
Short name T302
Test name
Test status
Simulation time 115996316 ps
CPU time 1.15 seconds
Started Jul 24 06:02:00 PM PDT 24
Finished Jul 24 06:02:01 PM PDT 24
Peak memory 220092 kb
Host smart-23dab6fd-fb12-421a-b199-920ae4352079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121250271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.4121250271
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.4187909333
Short name T727
Test name
Test status
Simulation time 212306938 ps
CPU time 1.31 seconds
Started Jul 24 06:01:51 PM PDT 24
Finished Jul 24 06:01:52 PM PDT 24
Peak memory 217620 kb
Host smart-73f10c8d-95d3-411f-b0b9-3ec2ab77441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187909333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.4187909333
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.779567105
Short name T551
Test name
Test status
Simulation time 65494649 ps
CPU time 1.23 seconds
Started Jul 24 06:02:19 PM PDT 24
Finished Jul 24 06:02:21 PM PDT 24
Peak memory 220172 kb
Host smart-0ef9599e-1e67-491d-8f9d-7a39bcdc73d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779567105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.779567105
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.4010555049
Short name T457
Test name
Test status
Simulation time 96183510 ps
CPU time 1.04 seconds
Started Jul 24 06:02:04 PM PDT 24
Finished Jul 24 06:02:05 PM PDT 24
Peak memory 217604 kb
Host smart-ae066e91-4ba2-4107-99c4-3eb92b6b907c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010555049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.4010555049
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.296874406
Short name T535
Test name
Test status
Simulation time 67211135 ps
CPU time 1.37 seconds
Started Jul 24 06:02:01 PM PDT 24
Finished Jul 24 06:02:02 PM PDT 24
Peak memory 220156 kb
Host smart-557db33f-4bea-4ef2-80cb-c7990ae3a099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296874406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.296874406
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.380534887
Short name T982
Test name
Test status
Simulation time 511751342 ps
CPU time 4.25 seconds
Started Jul 24 06:02:12 PM PDT 24
Finished Jul 24 06:02:17 PM PDT 24
Peak memory 220816 kb
Host smart-23e73fbe-bb5b-4153-a2dc-1cd6fbd183db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380534887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.380534887
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2182746740
Short name T949
Test name
Test status
Simulation time 154645778 ps
CPU time 1.48 seconds
Started Jul 24 06:02:06 PM PDT 24
Finished Jul 24 06:02:08 PM PDT 24
Peak memory 219352 kb
Host smart-f95cc17a-6a09-4d4d-81c4-eebf1dcf74e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182746740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2182746740
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.4166964788
Short name T744
Test name
Test status
Simulation time 62467821 ps
CPU time 1.26 seconds
Started Jul 24 06:02:03 PM PDT 24
Finished Jul 24 06:02:05 PM PDT 24
Peak memory 218808 kb
Host smart-959626ce-cfae-4aaa-b6c7-917e9b5faf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166964788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.4166964788
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2994310107
Short name T684
Test name
Test status
Simulation time 27626920 ps
CPU time 1.2 seconds
Started Jul 24 06:02:06 PM PDT 24
Finished Jul 24 06:02:08 PM PDT 24
Peak memory 217852 kb
Host smart-f9b4befc-7cac-4a8e-a7aa-b504112e71f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994310107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2994310107
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.855319214
Short name T911
Test name
Test status
Simulation time 77848695 ps
CPU time 1.24 seconds
Started Jul 24 06:00:23 PM PDT 24
Finished Jul 24 06:00:25 PM PDT 24
Peak memory 219872 kb
Host smart-5e6a2d63-ca19-4526-80cc-34886144fa82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855319214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.855319214
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.72668845
Short name T398
Test name
Test status
Simulation time 17497339 ps
CPU time 0.99 seconds
Started Jul 24 06:00:21 PM PDT 24
Finished Jul 24 06:00:22 PM PDT 24
Peak memory 206996 kb
Host smart-3fc2a147-24ee-42e2-b6c4-5f1f34856447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72668845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.72668845
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.652604790
Short name T158
Test name
Test status
Simulation time 18365426 ps
CPU time 0.84 seconds
Started Jul 24 06:00:24 PM PDT 24
Finished Jul 24 06:00:25 PM PDT 24
Peak memory 216588 kb
Host smart-146445e6-2d52-4c62-bb1d-72a1059e3dce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652604790 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.652604790
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.4215954558
Short name T665
Test name
Test status
Simulation time 44389930 ps
CPU time 1.25 seconds
Started Jul 24 06:00:28 PM PDT 24
Finished Jul 24 06:00:30 PM PDT 24
Peak memory 218744 kb
Host smart-989ac2e8-9808-4c7a-9b26-090523f4d210
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215954558 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.4215954558
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_genbits.3855291750
Short name T387
Test name
Test status
Simulation time 61900948 ps
CPU time 1.34 seconds
Started Jul 24 06:00:21 PM PDT 24
Finished Jul 24 06:00:23 PM PDT 24
Peak memory 220348 kb
Host smart-883a8b6f-e6d9-4ebf-871e-f730cb20f265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855291750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3855291750
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2935063742
Short name T715
Test name
Test status
Simulation time 23877499 ps
CPU time 1.17 seconds
Started Jul 24 06:00:21 PM PDT 24
Finished Jul 24 06:00:22 PM PDT 24
Peak memory 224372 kb
Host smart-c6ffb4b3-8939-47f9-b0f5-23c877b20821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935063742 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2935063742
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3141074281
Short name T239
Test name
Test status
Simulation time 18366115 ps
CPU time 1 seconds
Started Jul 24 06:00:26 PM PDT 24
Finished Jul 24 06:00:27 PM PDT 24
Peak memory 215608 kb
Host smart-362e2d2a-0153-4385-a749-2f14a66fb47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141074281 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3141074281
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2009427183
Short name T720
Test name
Test status
Simulation time 134043193 ps
CPU time 1.91 seconds
Started Jul 24 06:00:24 PM PDT 24
Finished Jul 24 06:00:26 PM PDT 24
Peak memory 215692 kb
Host smart-b49255f1-10b6-434f-8914-f036f195db95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009427183 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2009427183
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.195057882
Short name T632
Test name
Test status
Simulation time 78830651256 ps
CPU time 1113.34 seconds
Started Jul 24 06:00:24 PM PDT 24
Finished Jul 24 06:18:58 PM PDT 24
Peak memory 224176 kb
Host smart-fb013a00-36c0-42e3-871c-72829d12f580
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195057882 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.195057882
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2399776855
Short name T987
Test name
Test status
Simulation time 86179366 ps
CPU time 1.39 seconds
Started Jul 24 06:02:06 PM PDT 24
Finished Jul 24 06:02:08 PM PDT 24
Peak memory 219076 kb
Host smart-c56fafe0-f247-4edd-8038-332cb272ee8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399776855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2399776855
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.4023603701
Short name T966
Test name
Test status
Simulation time 34791121 ps
CPU time 1.24 seconds
Started Jul 24 06:02:13 PM PDT 24
Finished Jul 24 06:02:15 PM PDT 24
Peak memory 217712 kb
Host smart-4ab3549a-c425-4e98-b3ac-5eec4afb1d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023603701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4023603701
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2560869304
Short name T931
Test name
Test status
Simulation time 33135517 ps
CPU time 1.31 seconds
Started Jul 24 06:01:49 PM PDT 24
Finished Jul 24 06:01:51 PM PDT 24
Peak memory 217804 kb
Host smart-24c051b9-684e-4f93-a81f-e46989bc9a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560869304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2560869304
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3978534078
Short name T344
Test name
Test status
Simulation time 28895817 ps
CPU time 1.26 seconds
Started Jul 24 06:02:06 PM PDT 24
Finished Jul 24 06:02:08 PM PDT 24
Peak memory 220556 kb
Host smart-ecb756e3-1aca-4b94-9afd-ce701452f918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978534078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3978534078
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1311397129
Short name T603
Test name
Test status
Simulation time 48672584 ps
CPU time 1.31 seconds
Started Jul 24 06:02:02 PM PDT 24
Finished Jul 24 06:02:03 PM PDT 24
Peak memory 218656 kb
Host smart-af3e7650-8e31-48e4-9803-1d031b274bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311397129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1311397129
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2297779226
Short name T747
Test name
Test status
Simulation time 214532939 ps
CPU time 1.37 seconds
Started Jul 24 06:01:51 PM PDT 24
Finished Jul 24 06:01:53 PM PDT 24
Peak memory 218964 kb
Host smart-e83393cd-5893-45a5-aef3-4771d66bc48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297779226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2297779226
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1325745749
Short name T850
Test name
Test status
Simulation time 42364117 ps
CPU time 1.53 seconds
Started Jul 24 06:02:09 PM PDT 24
Finished Jul 24 06:02:11 PM PDT 24
Peak memory 217788 kb
Host smart-d76c1cad-a475-429e-ac13-e7b7a6584efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325745749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1325745749
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3109973335
Short name T406
Test name
Test status
Simulation time 118954784 ps
CPU time 1.41 seconds
Started Jul 24 06:02:14 PM PDT 24
Finished Jul 24 06:02:16 PM PDT 24
Peak memory 220176 kb
Host smart-aabff1dc-5151-480d-a711-063a1e891861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109973335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3109973335
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2130965596
Short name T433
Test name
Test status
Simulation time 362113995 ps
CPU time 3.2 seconds
Started Jul 24 06:02:18 PM PDT 24
Finished Jul 24 06:02:21 PM PDT 24
Peak memory 218920 kb
Host smart-c4ebd1e8-c88a-4efd-a5e5-dcb973b4d299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130965596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2130965596
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.917593475
Short name T836
Test name
Test status
Simulation time 60496150 ps
CPU time 1.17 seconds
Started Jul 24 06:01:50 PM PDT 24
Finished Jul 24 06:01:52 PM PDT 24
Peak memory 220116 kb
Host smart-749b6139-a5aa-4b66-8370-55352b83262a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917593475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.917593475
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1284193306
Short name T244
Test name
Test status
Simulation time 29248955 ps
CPU time 1.29 seconds
Started Jul 24 06:00:28 PM PDT 24
Finished Jul 24 06:00:29 PM PDT 24
Peak memory 219952 kb
Host smart-94423a69-3575-4a29-8cc8-d62d9ae6aa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284193306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1284193306
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1031703545
Short name T553
Test name
Test status
Simulation time 15414704 ps
CPU time 0.94 seconds
Started Jul 24 06:00:35 PM PDT 24
Finished Jul 24 06:00:36 PM PDT 24
Peak memory 207024 kb
Host smart-ff5fc058-c72e-4fb4-a6d9-8328751458a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031703545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1031703545
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.160888387
Short name T175
Test name
Test status
Simulation time 27886296 ps
CPU time 0.84 seconds
Started Jul 24 06:00:23 PM PDT 24
Finished Jul 24 06:00:24 PM PDT 24
Peak memory 216568 kb
Host smart-fc4e598a-0033-4d34-93ea-3d88f58491e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160888387 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.160888387
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.4276712453
Short name T133
Test name
Test status
Simulation time 27904037 ps
CPU time 1.13 seconds
Started Jul 24 06:00:22 PM PDT 24
Finished Jul 24 06:00:24 PM PDT 24
Peak memory 217100 kb
Host smart-432be6df-0ab9-4087-9e7b-591ace380b40
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276712453 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.4276712453
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.887831870
Short name T195
Test name
Test status
Simulation time 23941790 ps
CPU time 1.02 seconds
Started Jul 24 06:00:25 PM PDT 24
Finished Jul 24 06:00:26 PM PDT 24
Peak memory 219804 kb
Host smart-22d5e8af-34df-48e0-8cf1-d76efc6d2920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887831870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.887831870
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.363943619
Short name T785
Test name
Test status
Simulation time 32629492 ps
CPU time 1.39 seconds
Started Jul 24 06:00:27 PM PDT 24
Finished Jul 24 06:00:29 PM PDT 24
Peak memory 218708 kb
Host smart-91585192-89e6-4fff-9bfc-7f60b96e693a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363943619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.363943619
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2165697433
Short name T377
Test name
Test status
Simulation time 28046709 ps
CPU time 0.98 seconds
Started Jul 24 06:00:27 PM PDT 24
Finished Jul 24 06:00:28 PM PDT 24
Peak memory 215848 kb
Host smart-6b9f7573-355f-482e-9d27-0b409b2991d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165697433 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2165697433
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.370933820
Short name T476
Test name
Test status
Simulation time 18926418 ps
CPU time 1.04 seconds
Started Jul 24 06:00:26 PM PDT 24
Finished Jul 24 06:00:28 PM PDT 24
Peak memory 215616 kb
Host smart-76140d72-a71c-49a7-9d73-62e2ab76f47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370933820 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.370933820
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.945324220
Short name T2
Test name
Test status
Simulation time 351652888 ps
CPU time 2.89 seconds
Started Jul 24 06:00:27 PM PDT 24
Finished Jul 24 06:00:30 PM PDT 24
Peak memory 215640 kb
Host smart-bfa486dc-c36f-4d31-ba68-eeaecff9b41d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945324220 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.945324220
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.4144838443
Short name T42
Test name
Test status
Simulation time 37381813087 ps
CPU time 272.91 seconds
Started Jul 24 06:00:26 PM PDT 24
Finished Jul 24 06:05:00 PM PDT 24
Peak memory 218504 kb
Host smart-be4ea95d-40ed-4772-8413-c0cc2127211e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144838443 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.4144838443
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3096960146
Short name T984
Test name
Test status
Simulation time 43098440 ps
CPU time 1.44 seconds
Started Jul 24 06:01:56 PM PDT 24
Finished Jul 24 06:01:57 PM PDT 24
Peak memory 218816 kb
Host smart-4cdabcb8-1509-4ceb-a02a-cb7efc538b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096960146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3096960146
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.4092211183
Short name T973
Test name
Test status
Simulation time 57950866 ps
CPU time 1.13 seconds
Started Jul 24 06:02:08 PM PDT 24
Finished Jul 24 06:02:10 PM PDT 24
Peak memory 217512 kb
Host smart-d7fc395b-8c37-4311-ad58-c48fc7bc3eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092211183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.4092211183
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1258322622
Short name T404
Test name
Test status
Simulation time 71305372 ps
CPU time 2.61 seconds
Started Jul 24 06:01:55 PM PDT 24
Finished Jul 24 06:01:57 PM PDT 24
Peak memory 219100 kb
Host smart-92ac1d1f-ced2-4316-ad9e-2a210cf385ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258322622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1258322622
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.4056461256
Short name T44
Test name
Test status
Simulation time 63866630 ps
CPU time 1.18 seconds
Started Jul 24 06:02:03 PM PDT 24
Finished Jul 24 06:02:04 PM PDT 24
Peak memory 217736 kb
Host smart-f285935c-4cd9-48c8-8cad-2ea4c61898a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056461256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.4056461256
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.4258676333
Short name T735
Test name
Test status
Simulation time 171193474 ps
CPU time 1.36 seconds
Started Jul 24 06:02:03 PM PDT 24
Finished Jul 24 06:02:04 PM PDT 24
Peak memory 217828 kb
Host smart-1483d9d7-6628-42ae-b03f-2838e3948b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258676333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.4258676333
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.536534439
Short name T467
Test name
Test status
Simulation time 101894361 ps
CPU time 1.26 seconds
Started Jul 24 06:02:00 PM PDT 24
Finished Jul 24 06:02:02 PM PDT 24
Peak memory 219888 kb
Host smart-02c71f92-a805-4aca-a411-15df0c833e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536534439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.536534439
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.133672917
Short name T644
Test name
Test status
Simulation time 86686565 ps
CPU time 2.97 seconds
Started Jul 24 06:01:52 PM PDT 24
Finished Jul 24 06:01:56 PM PDT 24
Peak memory 219860 kb
Host smart-16ce2e8f-d6f1-4199-b64c-1ece3e758b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133672917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.133672917
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.399521472
Short name T898
Test name
Test status
Simulation time 94651583 ps
CPU time 1.55 seconds
Started Jul 24 06:02:07 PM PDT 24
Finished Jul 24 06:02:09 PM PDT 24
Peak memory 219440 kb
Host smart-923c79f5-fcc1-4d21-83ab-c1f3fb6738c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399521472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.399521472
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.587374822
Short name T497
Test name
Test status
Simulation time 72005464 ps
CPU time 2.43 seconds
Started Jul 24 06:02:05 PM PDT 24
Finished Jul 24 06:02:07 PM PDT 24
Peak memory 219044 kb
Host smart-750b9bd8-5c0b-45bd-aea2-cd31cf61d357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587374822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.587374822
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3011510126
Short name T792
Test name
Test status
Simulation time 49144154 ps
CPU time 1.07 seconds
Started Jul 24 06:02:06 PM PDT 24
Finished Jul 24 06:02:08 PM PDT 24
Peak memory 217688 kb
Host smart-8024dd54-b0f3-4df4-b5a0-07b1abcd1b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011510126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3011510126
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.244187349
Short name T451
Test name
Test status
Simulation time 23828402 ps
CPU time 0.9 seconds
Started Jul 24 06:00:36 PM PDT 24
Finished Jul 24 06:00:37 PM PDT 24
Peak memory 215204 kb
Host smart-945c8877-cef6-4f86-9911-adf8ace46ca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244187349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.244187349
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3667890238
Short name T240
Test name
Test status
Simulation time 20625469 ps
CPU time 0.81 seconds
Started Jul 24 06:00:33 PM PDT 24
Finished Jul 24 06:00:34 PM PDT 24
Peak memory 216348 kb
Host smart-ad2c5ff0-0971-4b82-9d6a-48b9c2f7ae58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667890238 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3667890238
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1617342184
Short name T570
Test name
Test status
Simulation time 50123169 ps
CPU time 1.48 seconds
Started Jul 24 06:00:25 PM PDT 24
Finished Jul 24 06:00:27 PM PDT 24
Peak memory 217264 kb
Host smart-fc97d5fa-9b0a-4bdf-a501-6de8bf3369f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617342184 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1617342184
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2180362827
Short name T120
Test name
Test status
Simulation time 52290007 ps
CPU time 0.95 seconds
Started Jul 24 06:00:28 PM PDT 24
Finished Jul 24 06:00:29 PM PDT 24
Peak memory 220096 kb
Host smart-2f00a24c-b3b0-41d2-b2c9-c54ebd9ac6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180362827 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2180362827
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.4193934976
Short name T515
Test name
Test status
Simulation time 28690187 ps
CPU time 1.38 seconds
Started Jul 24 06:00:27 PM PDT 24
Finished Jul 24 06:00:29 PM PDT 24
Peak memory 218856 kb
Host smart-22ef5cb4-2960-4d64-a06f-ed6480794d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193934976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.4193934976
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2148335986
Short name T34
Test name
Test status
Simulation time 27904878 ps
CPU time 0.88 seconds
Started Jul 24 06:00:27 PM PDT 24
Finished Jul 24 06:00:28 PM PDT 24
Peak memory 215952 kb
Host smart-aab81589-45df-4a9c-bc2e-e56e62c03e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148335986 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2148335986
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2125952022
Short name T579
Test name
Test status
Simulation time 33431157 ps
CPU time 0.96 seconds
Started Jul 24 06:00:35 PM PDT 24
Finished Jul 24 06:00:36 PM PDT 24
Peak memory 215612 kb
Host smart-4f4b8ff4-5614-4e17-b7ab-6a8015284aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125952022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2125952022
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2697666857
Short name T637
Test name
Test status
Simulation time 133850024 ps
CPU time 1.77 seconds
Started Jul 24 06:00:33 PM PDT 24
Finished Jul 24 06:00:35 PM PDT 24
Peak memory 215568 kb
Host smart-91c35382-5e08-4019-9824-2670da4d7143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697666857 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2697666857
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2521257688
Short name T219
Test name
Test status
Simulation time 167614677756 ps
CPU time 2182.43 seconds
Started Jul 24 06:00:27 PM PDT 24
Finished Jul 24 06:36:50 PM PDT 24
Peak memory 231108 kb
Host smart-5859326a-660a-448a-9103-2a070b12c499
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521257688 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2521257688
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2070678108
Short name T450
Test name
Test status
Simulation time 51982203 ps
CPU time 1.21 seconds
Started Jul 24 06:02:09 PM PDT 24
Finished Jul 24 06:02:10 PM PDT 24
Peak memory 220280 kb
Host smart-9a9a81d3-1e2c-4d4d-ad38-a220e01a84ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070678108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2070678108
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3968196589
Short name T610
Test name
Test status
Simulation time 62606675 ps
CPU time 1.59 seconds
Started Jul 24 06:02:02 PM PDT 24
Finished Jul 24 06:02:03 PM PDT 24
Peak memory 218904 kb
Host smart-71213da7-d0e0-478e-a9e8-c702dc75f005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968196589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3968196589
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1857006284
Short name T273
Test name
Test status
Simulation time 28315816 ps
CPU time 1.16 seconds
Started Jul 24 06:01:49 PM PDT 24
Finished Jul 24 06:01:51 PM PDT 24
Peak memory 217604 kb
Host smart-e1c1f3ab-6cef-4c60-97a9-87b99c185189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857006284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1857006284
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3037813510
Short name T653
Test name
Test status
Simulation time 33921824 ps
CPU time 1.21 seconds
Started Jul 24 06:01:57 PM PDT 24
Finished Jul 24 06:01:59 PM PDT 24
Peak memory 219928 kb
Host smart-6aef8710-f608-40b6-ace8-71ad34a08fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037813510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3037813510
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1457076364
Short name T343
Test name
Test status
Simulation time 23873396 ps
CPU time 1.04 seconds
Started Jul 24 06:02:16 PM PDT 24
Finished Jul 24 06:02:17 PM PDT 24
Peak memory 217716 kb
Host smart-02eebd5c-2bf7-4433-a6b7-cdc98b87c7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457076364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1457076364
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2388746405
Short name T396
Test name
Test status
Simulation time 31922035 ps
CPU time 1.23 seconds
Started Jul 24 06:02:10 PM PDT 24
Finished Jul 24 06:02:11 PM PDT 24
Peak memory 217908 kb
Host smart-badc9f49-dd65-427d-a93e-0932a6d0abf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388746405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2388746405
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2947257769
Short name T320
Test name
Test status
Simulation time 119990824 ps
CPU time 1.75 seconds
Started Jul 24 06:02:06 PM PDT 24
Finished Jul 24 06:02:08 PM PDT 24
Peak memory 219196 kb
Host smart-708ec7aa-4eb3-4378-a480-a81ac9fe4620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947257769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2947257769
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3587273801
Short name T575
Test name
Test status
Simulation time 61180200 ps
CPU time 1.2 seconds
Started Jul 24 06:02:07 PM PDT 24
Finished Jul 24 06:02:09 PM PDT 24
Peak memory 219192 kb
Host smart-ccbbcd54-e638-4e0c-9aa6-e2fa3bbf3777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587273801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3587273801
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1333858950
Short name T64
Test name
Test status
Simulation time 43719157 ps
CPU time 1.29 seconds
Started Jul 24 06:02:14 PM PDT 24
Finished Jul 24 06:02:16 PM PDT 24
Peak memory 220152 kb
Host smart-dceb1843-39e1-45a3-af75-babe1a8f1032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333858950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1333858950
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3517686623
Short name T622
Test name
Test status
Simulation time 107262518 ps
CPU time 1.57 seconds
Started Jul 24 06:02:01 PM PDT 24
Finished Jul 24 06:02:03 PM PDT 24
Peak memory 220324 kb
Host smart-e7eeb9b2-991b-4cd5-a601-8975ee43b6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517686623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3517686623
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3773105391
Short name T804
Test name
Test status
Simulation time 28442621 ps
CPU time 1.32 seconds
Started Jul 24 05:59:59 PM PDT 24
Finished Jul 24 06:00:01 PM PDT 24
Peak memory 219516 kb
Host smart-38b696c8-8f0b-4857-9e68-eba58fab76f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773105391 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3773105391
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2707712763
Short name T737
Test name
Test status
Simulation time 38377972 ps
CPU time 0.9 seconds
Started Jul 24 05:59:57 PM PDT 24
Finished Jul 24 05:59:58 PM PDT 24
Peak memory 207056 kb
Host smart-b317e6f2-df50-4f11-82e2-af56a62c8ec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707712763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2707712763
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.4254531944
Short name T927
Test name
Test status
Simulation time 67575217 ps
CPU time 1.22 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:02 PM PDT 24
Peak memory 217332 kb
Host smart-da6cfda9-009e-4027-be49-445382240a7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254531944 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.4254531944
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1640420917
Short name T156
Test name
Test status
Simulation time 33051170 ps
CPU time 0.99 seconds
Started Jul 24 05:59:59 PM PDT 24
Finished Jul 24 06:00:00 PM PDT 24
Peak memory 218740 kb
Host smart-e1efe3fe-2b5b-4d6d-aea6-a8be2fc32b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640420917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1640420917
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.555221288
Short name T350
Test name
Test status
Simulation time 59790544 ps
CPU time 1.31 seconds
Started Jul 24 05:59:56 PM PDT 24
Finished Jul 24 05:59:58 PM PDT 24
Peak memory 218844 kb
Host smart-34773dd6-c842-4412-98bf-72ecf9cd7bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555221288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.555221288
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1266054003
Short name T513
Test name
Test status
Simulation time 36300590 ps
CPU time 0.94 seconds
Started Jul 24 05:59:58 PM PDT 24
Finished Jul 24 05:59:59 PM PDT 24
Peak memory 215544 kb
Host smart-baf74821-a767-423b-8adc-8c4e4996c1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266054003 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1266054003
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3224519083
Short name T731
Test name
Test status
Simulation time 15975754 ps
CPU time 0.99 seconds
Started Jul 24 05:59:59 PM PDT 24
Finished Jul 24 06:00:00 PM PDT 24
Peak memory 207464 kb
Host smart-fa76661b-91e6-47ea-aa21-3ea4206858e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224519083 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3224519083
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.3954010529
Short name T411
Test name
Test status
Simulation time 37469887 ps
CPU time 0.97 seconds
Started Jul 24 05:59:59 PM PDT 24
Finished Jul 24 06:00:01 PM PDT 24
Peak memory 215588 kb
Host smart-559bf05f-6b51-49b3-9e1f-608181f19e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954010529 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3954010529
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1883360834
Short name T813
Test name
Test status
Simulation time 106863242 ps
CPU time 1.75 seconds
Started Jul 24 05:59:55 PM PDT 24
Finished Jul 24 05:59:57 PM PDT 24
Peak memory 215620 kb
Host smart-89e915ab-fc12-4b8f-a955-c8b091bce7f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883360834 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1883360834
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1071902861
Short name T788
Test name
Test status
Simulation time 192715957570 ps
CPU time 1086.55 seconds
Started Jul 24 05:59:57 PM PDT 24
Finished Jul 24 06:18:04 PM PDT 24
Peak memory 224744 kb
Host smart-8c2cca8f-4b87-4fe9-878e-c7802f2be7e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071902861 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1071902861
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2309969145
Short name T614
Test name
Test status
Simulation time 25749757 ps
CPU time 1.31 seconds
Started Jul 24 06:00:37 PM PDT 24
Finished Jul 24 06:00:39 PM PDT 24
Peak memory 220032 kb
Host smart-c9ba32f0-11d4-455c-a3ff-7d3a5a509171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309969145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2309969145
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3773519093
Short name T696
Test name
Test status
Simulation time 13976154 ps
CPU time 0.91 seconds
Started Jul 24 06:00:32 PM PDT 24
Finished Jul 24 06:00:33 PM PDT 24
Peak memory 207020 kb
Host smart-c768613d-fb63-4d58-8f23-bb616b41daff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773519093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3773519093
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1930115064
Short name T719
Test name
Test status
Simulation time 16272954 ps
CPU time 0.89 seconds
Started Jul 24 06:00:27 PM PDT 24
Finished Jul 24 06:00:28 PM PDT 24
Peak memory 216760 kb
Host smart-f97e391d-997a-4152-a277-acbaab022850
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930115064 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1930115064
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.122729769
Short name T994
Test name
Test status
Simulation time 40734371 ps
CPU time 1.35 seconds
Started Jul 24 06:00:28 PM PDT 24
Finished Jul 24 06:00:30 PM PDT 24
Peak memory 217304 kb
Host smart-88a3dc24-8e87-4dc7-8b75-851dcd7f7218
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122729769 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.122729769
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3742465260
Short name T172
Test name
Test status
Simulation time 46206356 ps
CPU time 0.96 seconds
Started Jul 24 06:00:39 PM PDT 24
Finished Jul 24 06:00:40 PM PDT 24
Peak memory 218592 kb
Host smart-9d031abe-3861-4c57-9c9a-00ba78e9b98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742465260 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3742465260
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3519736684
Short name T654
Test name
Test status
Simulation time 40001905 ps
CPU time 1.46 seconds
Started Jul 24 06:00:25 PM PDT 24
Finished Jul 24 06:00:27 PM PDT 24
Peak memory 217684 kb
Host smart-540e4239-178a-423a-bdec-75f7e3ff1644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519736684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3519736684
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2192191333
Short name T682
Test name
Test status
Simulation time 19788078 ps
CPU time 1.14 seconds
Started Jul 24 06:00:33 PM PDT 24
Finished Jul 24 06:00:34 PM PDT 24
Peak memory 216328 kb
Host smart-353374f2-2b81-485b-b44c-3188f6ac586e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192191333 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2192191333
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2579208656
Short name T668
Test name
Test status
Simulation time 19788859 ps
CPU time 1 seconds
Started Jul 24 06:00:39 PM PDT 24
Finished Jul 24 06:00:41 PM PDT 24
Peak memory 207332 kb
Host smart-5e61fd3a-f44a-4e64-bd9b-faa7f6efaa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579208656 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2579208656
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.855850218
Short name T452
Test name
Test status
Simulation time 543680923904 ps
CPU time 1140.34 seconds
Started Jul 24 06:00:42 PM PDT 24
Finished Jul 24 06:19:43 PM PDT 24
Peak memory 223204 kb
Host smart-72968619-655b-49d6-92b9-eec85d2fbc12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855850218 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.855850218
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2990655454
Short name T857
Test name
Test status
Simulation time 47487570 ps
CPU time 1.19 seconds
Started Jul 24 06:00:29 PM PDT 24
Finished Jul 24 06:00:30 PM PDT 24
Peak memory 220404 kb
Host smart-253b4fd9-3984-43b5-a690-34c183ae3b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990655454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2990655454
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2954403684
Short name T560
Test name
Test status
Simulation time 25577765 ps
CPU time 0.91 seconds
Started Jul 24 06:00:36 PM PDT 24
Finished Jul 24 06:00:37 PM PDT 24
Peak memory 206980 kb
Host smart-36862142-060d-4c54-875a-b707aa6611a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954403684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2954403684
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3033589775
Short name T916
Test name
Test status
Simulation time 24905812 ps
CPU time 0.85 seconds
Started Jul 24 06:00:34 PM PDT 24
Finished Jul 24 06:00:35 PM PDT 24
Peak memory 216572 kb
Host smart-5ce8b41b-aa6f-4597-9690-2aa0cb084cd5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033589775 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3033589775
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2170379756
Short name T845
Test name
Test status
Simulation time 54393546 ps
CPU time 1.16 seconds
Started Jul 24 06:00:38 PM PDT 24
Finished Jul 24 06:00:39 PM PDT 24
Peak memory 217136 kb
Host smart-a976d14b-9544-479f-8120-3461ca5204a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170379756 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2170379756
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1888400927
Short name T656
Test name
Test status
Simulation time 30776288 ps
CPU time 0.97 seconds
Started Jul 24 06:00:28 PM PDT 24
Finished Jul 24 06:00:29 PM PDT 24
Peak memory 224292 kb
Host smart-d68bd461-c81e-4317-ba5a-1f5c4419f8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888400927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1888400927
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.480652229
Short name T292
Test name
Test status
Simulation time 66771550 ps
CPU time 1.87 seconds
Started Jul 24 06:00:25 PM PDT 24
Finished Jul 24 06:00:27 PM PDT 24
Peak memory 219104 kb
Host smart-44c76437-7b45-4f36-9c6f-370ccf4e65ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480652229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.480652229
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2607822316
Short name T40
Test name
Test status
Simulation time 23109256 ps
CPU time 0.99 seconds
Started Jul 24 06:00:40 PM PDT 24
Finished Jul 24 06:00:42 PM PDT 24
Peak memory 216292 kb
Host smart-d9a17788-423a-42e1-9ba9-3be42a9d793e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607822316 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2607822316
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1368936773
Short name T839
Test name
Test status
Simulation time 96627045 ps
CPU time 0.95 seconds
Started Jul 24 06:00:28 PM PDT 24
Finished Jul 24 06:00:29 PM PDT 24
Peak memory 215636 kb
Host smart-126420b4-24da-4db7-bfeb-bae00fb44b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368936773 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1368936773
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.987781984
Short name T766
Test name
Test status
Simulation time 785006420 ps
CPU time 4.9 seconds
Started Jul 24 06:00:25 PM PDT 24
Finished Jul 24 06:00:30 PM PDT 24
Peak memory 217516 kb
Host smart-3ccc5970-b787-4479-9ef7-e89604a3e049
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987781984 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.987781984
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1229202959
Short name T464
Test name
Test status
Simulation time 105807648844 ps
CPU time 887.36 seconds
Started Jul 24 06:00:28 PM PDT 24
Finished Jul 24 06:15:16 PM PDT 24
Peak memory 224004 kb
Host smart-9b00c28b-b019-4236-8baa-8879b782c73a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229202959 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1229202959
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2743050489
Short name T282
Test name
Test status
Simulation time 35242551 ps
CPU time 1.55 seconds
Started Jul 24 06:00:26 PM PDT 24
Finished Jul 24 06:00:27 PM PDT 24
Peak memory 220104 kb
Host smart-f72a0cd2-c6d8-4715-89b3-56c5bd42f42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743050489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2743050489
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2305029850
Short name T800
Test name
Test status
Simulation time 52394497 ps
CPU time 0.88 seconds
Started Jul 24 06:00:38 PM PDT 24
Finished Jul 24 06:00:39 PM PDT 24
Peak memory 206984 kb
Host smart-d4b160ed-cadc-4427-becf-0ce4292dfff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305029850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2305029850
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.55104636
Short name T194
Test name
Test status
Simulation time 40973055 ps
CPU time 0.81 seconds
Started Jul 24 06:00:28 PM PDT 24
Finished Jul 24 06:00:29 PM PDT 24
Peak memory 216704 kb
Host smart-e558df3f-1e1f-4459-b316-258cf3badacd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55104636 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.55104636
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.4175277394
Short name T122
Test name
Test status
Simulation time 22135779 ps
CPU time 1.06 seconds
Started Jul 24 06:00:33 PM PDT 24
Finished Jul 24 06:00:35 PM PDT 24
Peak memory 217268 kb
Host smart-7905b2ee-5883-4926-971b-6335c713c76b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175277394 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.4175277394
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3991310585
Short name T108
Test name
Test status
Simulation time 25831516 ps
CPU time 1.03 seconds
Started Jul 24 06:00:40 PM PDT 24
Finished Jul 24 06:00:41 PM PDT 24
Peak memory 220188 kb
Host smart-52323c69-e557-46c8-80cc-49d55d6c2a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991310585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3991310585
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3824497730
Short name T332
Test name
Test status
Simulation time 256472681 ps
CPU time 1.38 seconds
Started Jul 24 06:00:28 PM PDT 24
Finished Jul 24 06:00:29 PM PDT 24
Peak memory 219160 kb
Host smart-5a1110fd-f627-4c91-adbc-797f4bca818a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824497730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3824497730
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1689409073
Short name T33
Test name
Test status
Simulation time 46776103 ps
CPU time 0.98 seconds
Started Jul 24 06:00:26 PM PDT 24
Finished Jul 24 06:00:27 PM PDT 24
Peak memory 215836 kb
Host smart-c4416e65-65f1-4348-9118-2a95381996c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689409073 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1689409073
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2562764816
Short name T337
Test name
Test status
Simulation time 14504266 ps
CPU time 0.97 seconds
Started Jul 24 06:00:40 PM PDT 24
Finished Jul 24 06:00:41 PM PDT 24
Peak memory 215656 kb
Host smart-b167b27a-9c98-4a0c-a70f-8b3d54666eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562764816 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2562764816
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1373151584
Short name T280
Test name
Test status
Simulation time 131493737 ps
CPU time 1.95 seconds
Started Jul 24 06:00:36 PM PDT 24
Finished Jul 24 06:00:38 PM PDT 24
Peak memory 215772 kb
Host smart-6470a755-d17f-4380-85e2-6edd21df5b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373151584 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1373151584
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2492134143
Short name T230
Test name
Test status
Simulation time 96681881244 ps
CPU time 555.06 seconds
Started Jul 24 06:00:27 PM PDT 24
Finished Jul 24 06:09:43 PM PDT 24
Peak memory 219532 kb
Host smart-9ffe5130-e0cf-46b6-87d9-fb6932962509
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492134143 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2492134143
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert_test.890867763
Short name T599
Test name
Test status
Simulation time 41240361 ps
CPU time 0.91 seconds
Started Jul 24 06:00:38 PM PDT 24
Finished Jul 24 06:00:39 PM PDT 24
Peak memory 215040 kb
Host smart-d8851a1e-a79f-4891-836b-424a6cf1001e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890867763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.890867763
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1316259670
Short name T549
Test name
Test status
Simulation time 22958953 ps
CPU time 0.82 seconds
Started Jul 24 06:00:34 PM PDT 24
Finished Jul 24 06:00:35 PM PDT 24
Peak memory 216328 kb
Host smart-07bb520d-70d5-4a46-95a8-521e682c2af1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316259670 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1316259670
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2526807965
Short name T912
Test name
Test status
Simulation time 71637789 ps
CPU time 1.06 seconds
Started Jul 24 06:00:32 PM PDT 24
Finished Jul 24 06:00:34 PM PDT 24
Peak memory 217192 kb
Host smart-abad83f4-a505-4fa1-b1ef-82561168d3dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526807965 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2526807965
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.821818824
Short name T617
Test name
Test status
Simulation time 22150912 ps
CPU time 1.07 seconds
Started Jul 24 06:00:38 PM PDT 24
Finished Jul 24 06:00:39 PM PDT 24
Peak memory 224272 kb
Host smart-2f1901d0-4262-48bf-87cb-92dd8cafbd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821818824 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.821818824
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1262437165
Short name T471
Test name
Test status
Simulation time 86755817 ps
CPU time 1.35 seconds
Started Jul 24 06:00:37 PM PDT 24
Finished Jul 24 06:00:38 PM PDT 24
Peak memory 218928 kb
Host smart-379f1164-3d34-4cd6-a901-a1a19b08463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262437165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1262437165
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3669946658
Short name T99
Test name
Test status
Simulation time 25620700 ps
CPU time 0.97 seconds
Started Jul 24 06:00:45 PM PDT 24
Finished Jul 24 06:00:46 PM PDT 24
Peak memory 216292 kb
Host smart-4d590a99-ad4d-411b-9816-37b1208bc40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669946658 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3669946658
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.4019662818
Short name T873
Test name
Test status
Simulation time 111103954 ps
CPU time 0.87 seconds
Started Jul 24 06:00:33 PM PDT 24
Finished Jul 24 06:00:34 PM PDT 24
Peak memory 215616 kb
Host smart-e3fa6ff4-1526-430d-8242-facaa3e6f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019662818 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.4019662818
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.917795723
Short name T902
Test name
Test status
Simulation time 201112981 ps
CPU time 4.06 seconds
Started Jul 24 06:00:52 PM PDT 24
Finished Jul 24 06:00:56 PM PDT 24
Peak memory 217596 kb
Host smart-4ef6ee76-6d29-4154-8c85-b0303b70b518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917795723 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.917795723
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2076466062
Short name T322
Test name
Test status
Simulation time 18802913116 ps
CPU time 469.52 seconds
Started Jul 24 06:00:32 PM PDT 24
Finished Jul 24 06:08:22 PM PDT 24
Peak memory 224044 kb
Host smart-2ae083f1-bc47-4aeb-a620-91bbecbf8efe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076466062 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2076466062
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1330652865
Short name T552
Test name
Test status
Simulation time 25753445 ps
CPU time 1.3 seconds
Started Jul 24 06:00:35 PM PDT 24
Finished Jul 24 06:00:36 PM PDT 24
Peak memory 220508 kb
Host smart-b039c002-f57b-4814-b32c-8498a94008ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330652865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1330652865
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.873950665
Short name T393
Test name
Test status
Simulation time 63789139 ps
CPU time 0.98 seconds
Started Jul 24 06:00:38 PM PDT 24
Finished Jul 24 06:00:39 PM PDT 24
Peak memory 207044 kb
Host smart-29c5986e-7ef7-4b05-a454-0bdb870f7ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873950665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.873950665
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.462108767
Short name T772
Test name
Test status
Simulation time 12502546 ps
CPU time 0.92 seconds
Started Jul 24 06:00:30 PM PDT 24
Finished Jul 24 06:00:31 PM PDT 24
Peak memory 216496 kb
Host smart-6a39c47d-38ce-49fe-854a-865295cdd8ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462108767 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.462108767
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2443894208
Short name T954
Test name
Test status
Simulation time 21991794 ps
CPU time 1.1 seconds
Started Jul 24 06:00:54 PM PDT 24
Finished Jul 24 06:00:55 PM PDT 24
Peak memory 220064 kb
Host smart-2f3999ea-ae17-413e-a419-f94cdac77a24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443894208 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2443894208
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.4134476478
Short name T137
Test name
Test status
Simulation time 21999545 ps
CPU time 1.1 seconds
Started Jul 24 06:00:36 PM PDT 24
Finished Jul 24 06:00:38 PM PDT 24
Peak memory 219944 kb
Host smart-cb15bbfa-fab0-4cb2-b995-70e40aaa601f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134476478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4134476478
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1325587695
Short name T762
Test name
Test status
Simulation time 54852015 ps
CPU time 1.7 seconds
Started Jul 24 06:00:38 PM PDT 24
Finished Jul 24 06:00:40 PM PDT 24
Peak memory 219824 kb
Host smart-e6e0faf9-79a1-4171-8b20-6e9157ec314c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325587695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1325587695
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1929277417
Short name T362
Test name
Test status
Simulation time 35309067 ps
CPU time 0.88 seconds
Started Jul 24 06:00:36 PM PDT 24
Finished Jul 24 06:00:38 PM PDT 24
Peak memory 215732 kb
Host smart-00209adc-1131-48c4-a3f9-65a3963124bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929277417 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1929277417
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2003464636
Short name T401
Test name
Test status
Simulation time 85262884 ps
CPU time 0.98 seconds
Started Jul 24 06:00:41 PM PDT 24
Finished Jul 24 06:00:42 PM PDT 24
Peak memory 215624 kb
Host smart-96d02b3a-852d-413b-b8e9-628ff62a3ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003464636 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2003464636
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.512772886
Short name T726
Test name
Test status
Simulation time 113109276 ps
CPU time 1.67 seconds
Started Jul 24 06:00:37 PM PDT 24
Finished Jul 24 06:00:39 PM PDT 24
Peak memory 215616 kb
Host smart-1b8b4deb-4991-4188-9c60-56918b8fd6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512772886 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.512772886
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1038467802
Short name T232
Test name
Test status
Simulation time 90089288829 ps
CPU time 520.74 seconds
Started Jul 24 06:00:34 PM PDT 24
Finished Jul 24 06:09:15 PM PDT 24
Peak memory 224108 kb
Host smart-bb80db3c-0a1a-4711-a840-78ba7d198491
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038467802 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1038467802
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1891913214
Short name T248
Test name
Test status
Simulation time 53785377 ps
CPU time 1.23 seconds
Started Jul 24 06:00:57 PM PDT 24
Finished Jul 24 06:00:59 PM PDT 24
Peak memory 221060 kb
Host smart-18e1cf8d-ce5e-45e1-8043-0f55e7410f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891913214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1891913214
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1725248846
Short name T618
Test name
Test status
Simulation time 28716678 ps
CPU time 0.91 seconds
Started Jul 24 06:00:42 PM PDT 24
Finished Jul 24 06:00:43 PM PDT 24
Peak memory 207076 kb
Host smart-b0f6832f-cec0-42e6-a6d3-520e5b65ebe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725248846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1725248846
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3612395150
Short name T145
Test name
Test status
Simulation time 13164807 ps
CPU time 0.93 seconds
Started Jul 24 06:00:41 PM PDT 24
Finished Jul 24 06:00:42 PM PDT 24
Peak memory 215984 kb
Host smart-19c8c8a7-5306-4896-9fe0-bfe4bed4ad9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612395150 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3612395150
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1748714458
Short name T190
Test name
Test status
Simulation time 25576761 ps
CPU time 1.13 seconds
Started Jul 24 06:00:41 PM PDT 24
Finished Jul 24 06:00:42 PM PDT 24
Peak memory 218956 kb
Host smart-df5dc7d7-a13f-4926-8e4d-4c4411a465a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748714458 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1748714458
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3970767535
Short name T340
Test name
Test status
Simulation time 18699636 ps
CPU time 1.06 seconds
Started Jul 24 06:00:43 PM PDT 24
Finished Jul 24 06:00:45 PM PDT 24
Peak memory 218684 kb
Host smart-bac96c11-446a-486f-99cc-e84607e36916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970767535 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3970767535
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1504921786
Short name T761
Test name
Test status
Simulation time 89761547 ps
CPU time 1.18 seconds
Started Jul 24 06:00:39 PM PDT 24
Finished Jul 24 06:00:41 PM PDT 24
Peak memory 217760 kb
Host smart-45c661d3-97c3-4b2f-89c1-68adbfa3a13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504921786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1504921786
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1234967900
Short name T636
Test name
Test status
Simulation time 52099352 ps
CPU time 0.98 seconds
Started Jul 24 06:00:33 PM PDT 24
Finished Jul 24 06:00:34 PM PDT 24
Peak memory 224180 kb
Host smart-975646f5-49cc-4e0e-ac05-837321ab0941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234967900 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1234967900
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.188496396
Short name T341
Test name
Test status
Simulation time 57665586 ps
CPU time 0.93 seconds
Started Jul 24 06:00:37 PM PDT 24
Finished Jul 24 06:00:38 PM PDT 24
Peak memory 215516 kb
Host smart-c0bcb3d1-5955-48f9-9b2e-05aa78d4744b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188496396 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.188496396
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1094160100
Short name T381
Test name
Test status
Simulation time 465937619 ps
CPU time 4.85 seconds
Started Jul 24 06:00:33 PM PDT 24
Finished Jul 24 06:00:38 PM PDT 24
Peak memory 215732 kb
Host smart-5df42ac6-56af-4495-922e-f929c0936dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094160100 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1094160100
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2785353157
Short name T615
Test name
Test status
Simulation time 183044845050 ps
CPU time 993.7 seconds
Started Jul 24 06:00:42 PM PDT 24
Finished Jul 24 06:17:16 PM PDT 24
Peak memory 221696 kb
Host smart-8f0396ff-4737-4b49-b250-e2cbade8a527
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785353157 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2785353157
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2932804764
Short name T210
Test name
Test status
Simulation time 45269486 ps
CPU time 1.22 seconds
Started Jul 24 06:00:43 PM PDT 24
Finished Jul 24 06:00:44 PM PDT 24
Peak memory 219432 kb
Host smart-5e9706f7-bd98-4a53-8ebf-8b5a45c4777c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932804764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2932804764
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2060638470
Short name T907
Test name
Test status
Simulation time 20974843 ps
CPU time 1.02 seconds
Started Jul 24 06:00:40 PM PDT 24
Finished Jul 24 06:00:41 PM PDT 24
Peak memory 207008 kb
Host smart-c156a864-1f22-4ff4-98a2-40c2d3fca216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060638470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2060638470
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2185759787
Short name T149
Test name
Test status
Simulation time 10733501 ps
CPU time 0.87 seconds
Started Jul 24 06:00:37 PM PDT 24
Finished Jul 24 06:00:38 PM PDT 24
Peak memory 216576 kb
Host smart-6298f19d-f4f9-4711-ae98-664911f8dcd5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185759787 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2185759787
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2047883832
Short name T795
Test name
Test status
Simulation time 56238463 ps
CPU time 1.31 seconds
Started Jul 24 06:00:41 PM PDT 24
Finished Jul 24 06:00:42 PM PDT 24
Peak memory 217180 kb
Host smart-6b53f746-6d94-4c25-b089-0ea288495b0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047883832 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2047883832
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.120034346
Short name T163
Test name
Test status
Simulation time 18702543 ps
CPU time 1.14 seconds
Started Jul 24 06:00:33 PM PDT 24
Finished Jul 24 06:00:34 PM PDT 24
Peak memory 224272 kb
Host smart-dd418e28-1851-48ae-bdcd-98786b2f95b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120034346 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.120034346
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3244628614
Short name T913
Test name
Test status
Simulation time 35245311 ps
CPU time 1.3 seconds
Started Jul 24 06:00:43 PM PDT 24
Finished Jul 24 06:00:44 PM PDT 24
Peak memory 220372 kb
Host smart-e142775b-db3e-4a8f-a102-3f2220b9c36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244628614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3244628614
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.226566914
Short name T32
Test name
Test status
Simulation time 26856943 ps
CPU time 0.93 seconds
Started Jul 24 06:00:45 PM PDT 24
Finished Jul 24 06:00:46 PM PDT 24
Peak memory 216128 kb
Host smart-28490792-bc06-4d4c-81c1-074e0cdaccd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226566914 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.226566914
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1248969496
Short name T224
Test name
Test status
Simulation time 80609849 ps
CPU time 0.91 seconds
Started Jul 24 06:00:41 PM PDT 24
Finished Jul 24 06:00:42 PM PDT 24
Peak memory 215668 kb
Host smart-2a40d3dd-f405-48cf-9bc7-b7dd798bf7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248969496 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1248969496
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.4237800810
Short name T528
Test name
Test status
Simulation time 1812352359 ps
CPU time 5.2 seconds
Started Jul 24 06:00:42 PM PDT 24
Finished Jul 24 06:00:48 PM PDT 24
Peak memory 217412 kb
Host smart-fcab6967-ab8d-4ad8-9c3f-7e83033064bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237800810 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.4237800810
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2742315384
Short name T475
Test name
Test status
Simulation time 257635756898 ps
CPU time 723.18 seconds
Started Jul 24 06:00:42 PM PDT 24
Finished Jul 24 06:12:46 PM PDT 24
Peak memory 220052 kb
Host smart-d1155524-c393-47e0-8446-bab3dadfcac0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742315384 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2742315384
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1038783029
Short name T124
Test name
Test status
Simulation time 23300575 ps
CPU time 1.13 seconds
Started Jul 24 06:00:47 PM PDT 24
Finished Jul 24 06:00:49 PM PDT 24
Peak memory 220120 kb
Host smart-91c59d5a-7f35-4568-bea8-b163d8ea2a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038783029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1038783029
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.523286635
Short name T95
Test name
Test status
Simulation time 19108387 ps
CPU time 1 seconds
Started Jul 24 06:01:01 PM PDT 24
Finished Jul 24 06:01:02 PM PDT 24
Peak memory 207072 kb
Host smart-765f9eb8-abca-4829-8997-81401ce6d628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523286635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.523286635
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3520681587
Short name T488
Test name
Test status
Simulation time 18243641 ps
CPU time 0.86 seconds
Started Jul 24 06:00:51 PM PDT 24
Finished Jul 24 06:00:52 PM PDT 24
Peak memory 216424 kb
Host smart-5572617c-ec6d-43eb-ba55-43a1ff088227
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520681587 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3520681587
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.642074613
Short name T567
Test name
Test status
Simulation time 38123869 ps
CPU time 1.21 seconds
Started Jul 24 06:00:44 PM PDT 24
Finished Jul 24 06:00:45 PM PDT 24
Peak memory 217272 kb
Host smart-ee922f5f-e6f5-4ab2-9fcb-9516f8c97e02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642074613 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.642074613
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3238757989
Short name T184
Test name
Test status
Simulation time 21008270 ps
CPU time 1.17 seconds
Started Jul 24 06:00:54 PM PDT 24
Finished Jul 24 06:00:55 PM PDT 24
Peak memory 230076 kb
Host smart-781a1d1b-d97a-4242-9eea-6fc5a2dc3fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238757989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3238757989
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.67953061
Short name T674
Test name
Test status
Simulation time 19095190 ps
CPU time 1.16 seconds
Started Jul 24 06:00:51 PM PDT 24
Finished Jul 24 06:00:52 PM PDT 24
Peak memory 218840 kb
Host smart-9e79ae74-1a56-4a5d-a5a6-d34136a4da5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67953061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.67953061
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2252973738
Short name T798
Test name
Test status
Simulation time 38607233 ps
CPU time 0.9 seconds
Started Jul 24 06:00:47 PM PDT 24
Finished Jul 24 06:00:48 PM PDT 24
Peak memory 215912 kb
Host smart-a4cf4832-ed78-433a-bb22-95c91e68dc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252973738 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2252973738
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.674680559
Short name T964
Test name
Test status
Simulation time 38787943 ps
CPU time 0.9 seconds
Started Jul 24 06:00:34 PM PDT 24
Finished Jul 24 06:00:36 PM PDT 24
Peak memory 215804 kb
Host smart-05e42cf5-cb3b-4ec1-b81f-e2cdf1146818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674680559 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.674680559
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.933662784
Short name T351
Test name
Test status
Simulation time 700588854 ps
CPU time 3.93 seconds
Started Jul 24 06:00:42 PM PDT 24
Finished Jul 24 06:00:46 PM PDT 24
Peak memory 217520 kb
Host smart-75eb9db5-fa2e-4a16-9cad-10f0a50750f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933662784 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.933662784
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.956965398
Short name T742
Test name
Test status
Simulation time 118735032842 ps
CPU time 623.98 seconds
Started Jul 24 06:00:50 PM PDT 24
Finished Jul 24 06:11:14 PM PDT 24
Peak memory 224028 kb
Host smart-b64f240a-d0dc-41ad-a2ce-c671b31a8f01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956965398 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.956965398
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1575085307
Short name T155
Test name
Test status
Simulation time 101033123 ps
CPU time 1.26 seconds
Started Jul 24 06:00:46 PM PDT 24
Finished Jul 24 06:00:48 PM PDT 24
Peak memory 216044 kb
Host smart-9b00206c-82f6-4ce6-9e34-6b46087586ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575085307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1575085307
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.584349465
Short name T600
Test name
Test status
Simulation time 12733642 ps
CPU time 0.9 seconds
Started Jul 24 06:00:45 PM PDT 24
Finished Jul 24 06:00:46 PM PDT 24
Peak memory 206808 kb
Host smart-a5d68921-0531-4083-9b98-fdfcc1bb0bb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584349465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.584349465
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1297288364
Short name T159
Test name
Test status
Simulation time 13183287 ps
CPU time 0.86 seconds
Started Jul 24 06:00:54 PM PDT 24
Finished Jul 24 06:00:56 PM PDT 24
Peak memory 216608 kb
Host smart-b12309c6-d5f9-429e-b852-7989c4e317eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297288364 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1297288364
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.4189636648
Short name T688
Test name
Test status
Simulation time 55460540 ps
CPU time 1.17 seconds
Started Jul 24 06:00:43 PM PDT 24
Finished Jul 24 06:00:45 PM PDT 24
Peak memory 217340 kb
Host smart-422063c6-d17c-485a-864d-b1dcaaab4c12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189636648 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.4189636648
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1960793269
Short name T690
Test name
Test status
Simulation time 23037807 ps
CPU time 1.13 seconds
Started Jul 24 06:01:02 PM PDT 24
Finished Jul 24 06:01:03 PM PDT 24
Peak memory 224316 kb
Host smart-b50af633-5e2a-4cee-bbc2-aaf2805b5b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960793269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1960793269
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1374974976
Short name T417
Test name
Test status
Simulation time 27276198 ps
CPU time 1.21 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:00:55 PM PDT 24
Peak memory 217708 kb
Host smart-9ed2f393-a32c-42a6-8037-a35f6cbd5628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374974976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1374974976
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3663348586
Short name T923
Test name
Test status
Simulation time 36327816 ps
CPU time 0.99 seconds
Started Jul 24 06:00:47 PM PDT 24
Finished Jul 24 06:00:48 PM PDT 24
Peak memory 224332 kb
Host smart-993360f5-42f0-4641-9aca-ce03854bc4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663348586 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3663348586
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.96131316
Short name T717
Test name
Test status
Simulation time 17837026 ps
CPU time 0.96 seconds
Started Jul 24 06:01:01 PM PDT 24
Finished Jul 24 06:01:02 PM PDT 24
Peak memory 215632 kb
Host smart-8117d43e-b537-4818-82c1-b16f9ffab699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96131316 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.96131316
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1046354797
Short name T486
Test name
Test status
Simulation time 23548152 ps
CPU time 1.06 seconds
Started Jul 24 06:00:52 PM PDT 24
Finished Jul 24 06:00:53 PM PDT 24
Peak memory 215596 kb
Host smart-986bcd77-56bf-4777-bf1b-0f1f7e316477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046354797 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1046354797
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.675251948
Short name T695
Test name
Test status
Simulation time 50767102645 ps
CPU time 1268.96 seconds
Started Jul 24 06:00:44 PM PDT 24
Finished Jul 24 06:21:53 PM PDT 24
Peak memory 223432 kb
Host smart-91532024-5f15-4a20-a40e-6e6a4ea0a8f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675251948 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.675251948
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2167232566
Short name T290
Test name
Test status
Simulation time 123257753 ps
CPU time 1.19 seconds
Started Jul 24 06:00:51 PM PDT 24
Finished Jul 24 06:00:52 PM PDT 24
Peak memory 219936 kb
Host smart-6727018c-9d24-45bf-a42b-41207b4043fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167232566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2167232566
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1840664201
Short name T412
Test name
Test status
Simulation time 31576702 ps
CPU time 0.84 seconds
Started Jul 24 06:00:47 PM PDT 24
Finished Jul 24 06:00:48 PM PDT 24
Peak memory 207096 kb
Host smart-baf86e55-b747-482f-8b71-23b874ef7616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840664201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1840664201
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2578341903
Short name T739
Test name
Test status
Simulation time 47379886 ps
CPU time 1.09 seconds
Started Jul 24 06:00:44 PM PDT 24
Finished Jul 24 06:00:46 PM PDT 24
Peak memory 218960 kb
Host smart-8e7353d6-6c88-4055-8acc-6c8c310075d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578341903 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2578341903
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.4217748869
Short name T183
Test name
Test status
Simulation time 29867284 ps
CPU time 0.88 seconds
Started Jul 24 06:01:05 PM PDT 24
Finished Jul 24 06:01:06 PM PDT 24
Peak memory 219512 kb
Host smart-8eb1d477-101f-4531-b3bb-495bad37c961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217748869 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.4217748869
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3342528838
Short name T394
Test name
Test status
Simulation time 69513519 ps
CPU time 1.24 seconds
Started Jul 24 06:01:00 PM PDT 24
Finished Jul 24 06:01:01 PM PDT 24
Peak memory 219300 kb
Host smart-f29cdfc4-b557-4b45-99e3-e192fccad06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342528838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3342528838
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2426905784
Short name T403
Test name
Test status
Simulation time 20886086 ps
CPU time 1.08 seconds
Started Jul 24 06:00:47 PM PDT 24
Finished Jul 24 06:00:48 PM PDT 24
Peak memory 215736 kb
Host smart-605014b7-795c-496c-b722-b1ae9bc87d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426905784 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2426905784
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2624012350
Short name T370
Test name
Test status
Simulation time 19513343 ps
CPU time 1.04 seconds
Started Jul 24 06:00:41 PM PDT 24
Finished Jul 24 06:00:42 PM PDT 24
Peak memory 215664 kb
Host smart-bed23c49-2ed3-4d57-bd0e-43a10ee83671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624012350 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2624012350
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2142197498
Short name T782
Test name
Test status
Simulation time 419033158 ps
CPU time 6.32 seconds
Started Jul 24 06:00:46 PM PDT 24
Finished Jul 24 06:00:53 PM PDT 24
Peak memory 217488 kb
Host smart-7b0abbd8-4e03-4356-af89-238e9c739ad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142197498 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2142197498
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_alert.1237838637
Short name T947
Test name
Test status
Simulation time 24511840 ps
CPU time 1.2 seconds
Started Jul 24 05:59:59 PM PDT 24
Finished Jul 24 06:00:00 PM PDT 24
Peak memory 219948 kb
Host smart-7209cff8-5edc-4234-93d5-4af3709678a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237838637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1237838637
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1970208354
Short name T577
Test name
Test status
Simulation time 179348425 ps
CPU time 1.41 seconds
Started Jul 24 05:59:57 PM PDT 24
Finished Jul 24 05:59:59 PM PDT 24
Peak memory 207128 kb
Host smart-f24704cd-12b2-41b8-9dc9-fce82c8985f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970208354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1970208354
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.235964040
Short name T196
Test name
Test status
Simulation time 87601385 ps
CPU time 0.89 seconds
Started Jul 24 05:59:56 PM PDT 24
Finished Jul 24 05:59:58 PM PDT 24
Peak memory 216548 kb
Host smart-60011fdc-f3ed-453d-9e2c-3501926bb663
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235964040 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.235964040
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3893087771
Short name T69
Test name
Test status
Simulation time 53006753 ps
CPU time 1.23 seconds
Started Jul 24 05:59:56 PM PDT 24
Finished Jul 24 05:59:58 PM PDT 24
Peak memory 217204 kb
Host smart-ef0fc229-613b-40c6-8cf5-19522671e111
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893087771 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3893087771
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3829273881
Short name T462
Test name
Test status
Simulation time 24343546 ps
CPU time 0.94 seconds
Started Jul 24 05:59:55 PM PDT 24
Finished Jul 24 05:59:57 PM PDT 24
Peak memory 219676 kb
Host smart-06da1950-d80d-41b7-a6cd-b19462656606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829273881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3829273881
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.566211512
Short name T481
Test name
Test status
Simulation time 37827461 ps
CPU time 1.51 seconds
Started Jul 24 05:59:55 PM PDT 24
Finished Jul 24 05:59:57 PM PDT 24
Peak memory 217708 kb
Host smart-15828f0c-b59e-4a5e-bfff-00ff3b021990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566211512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.566211512
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2323058711
Short name T685
Test name
Test status
Simulation time 28304552 ps
CPU time 0.98 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:01 PM PDT 24
Peak memory 215968 kb
Host smart-269e0a6e-30c6-4cfd-a6e0-4d2e638db7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323058711 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2323058711
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3400801090
Short name T624
Test name
Test status
Simulation time 15069304 ps
CPU time 0.95 seconds
Started Jul 24 05:59:54 PM PDT 24
Finished Jul 24 05:59:56 PM PDT 24
Peak memory 207428 kb
Host smart-2748432b-ebcb-4e19-bb90-af4d4dd5ce15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400801090 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3400801090
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3266980531
Short name T15
Test name
Test status
Simulation time 1029134652 ps
CPU time 5.24 seconds
Started Jul 24 05:59:56 PM PDT 24
Finished Jul 24 06:00:02 PM PDT 24
Peak memory 237724 kb
Host smart-0fad469e-7d92-4f43-b6ea-8c63d80d1c89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266980531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3266980531
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3636372353
Short name T346
Test name
Test status
Simulation time 17707550 ps
CPU time 1.03 seconds
Started Jul 24 05:59:56 PM PDT 24
Finished Jul 24 05:59:57 PM PDT 24
Peak memory 215612 kb
Host smart-e75f003c-05a8-4086-b964-2175bedacc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636372353 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3636372353
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1770545755
Short name T238
Test name
Test status
Simulation time 296324191 ps
CPU time 5.84 seconds
Started Jul 24 05:59:57 PM PDT 24
Finished Jul 24 06:00:03 PM PDT 24
Peak memory 217384 kb
Host smart-f7a838bb-2c0c-4d91-aeda-d0539d006005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770545755 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1770545755
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3072269400
Short name T630
Test name
Test status
Simulation time 38283087435 ps
CPU time 985.9 seconds
Started Jul 24 05:59:53 PM PDT 24
Finished Jul 24 06:16:19 PM PDT 24
Peak memory 220808 kb
Host smart-973f7e5c-2ec1-4c09-b46a-565ea2867024
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072269400 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3072269400
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1466300470
Short name T922
Test name
Test status
Simulation time 84684491 ps
CPU time 1.17 seconds
Started Jul 24 06:00:47 PM PDT 24
Finished Jul 24 06:00:48 PM PDT 24
Peak memory 221128 kb
Host smart-4465f803-8271-4132-8ddc-90ed6cf5fac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466300470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1466300470
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3970860078
Short name T780
Test name
Test status
Simulation time 43592504 ps
CPU time 0.86 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:00:54 PM PDT 24
Peak memory 206884 kb
Host smart-bdbe1052-2f64-4749-8f6f-b9b3bda8ebea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970860078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3970860078
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3994082636
Short name T587
Test name
Test status
Simulation time 27899477 ps
CPU time 0.82 seconds
Started Jul 24 06:00:46 PM PDT 24
Finished Jul 24 06:00:47 PM PDT 24
Peak memory 216232 kb
Host smart-96581ee6-b745-47a9-ac2f-66030d06e437
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994082636 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3994082636
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.4169567619
Short name T402
Test name
Test status
Simulation time 52800409 ps
CPU time 1.06 seconds
Started Jul 24 06:00:48 PM PDT 24
Finished Jul 24 06:00:49 PM PDT 24
Peak memory 218476 kb
Host smart-4bc30350-3c66-47f3-9606-940d354c5874
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169567619 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.4169567619
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3297179920
Short name T185
Test name
Test status
Simulation time 25864733 ps
CPU time 1.04 seconds
Started Jul 24 06:00:47 PM PDT 24
Finished Jul 24 06:00:48 PM PDT 24
Peak memory 229844 kb
Host smart-b47a784b-b74f-4f52-9ac8-4f767cd4c9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297179920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3297179920
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3358557087
Short name T431
Test name
Test status
Simulation time 56431466 ps
CPU time 1.08 seconds
Started Jul 24 06:00:50 PM PDT 24
Finished Jul 24 06:00:52 PM PDT 24
Peak memory 217632 kb
Host smart-01e13883-d0c1-438a-a3c2-2645dbc681d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358557087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3358557087
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.203073945
Short name T877
Test name
Test status
Simulation time 61863059 ps
CPU time 0.92 seconds
Started Jul 24 06:00:45 PM PDT 24
Finished Jul 24 06:00:46 PM PDT 24
Peak memory 215544 kb
Host smart-03d36db7-7963-44de-a3c2-e140724e25f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203073945 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.203073945
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.4129704173
Short name T774
Test name
Test status
Simulation time 24301079 ps
CPU time 0.92 seconds
Started Jul 24 06:00:41 PM PDT 24
Finished Jul 24 06:00:42 PM PDT 24
Peak memory 215632 kb
Host smart-99d6560d-60b3-4206-94d3-1b5d3c9ba86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129704173 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.4129704173
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3517032916
Short name T593
Test name
Test status
Simulation time 386230742 ps
CPU time 5.26 seconds
Started Jul 24 06:01:01 PM PDT 24
Finished Jul 24 06:01:06 PM PDT 24
Peak memory 217372 kb
Host smart-ed7620d0-535b-4374-b5d4-dd719badcc63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517032916 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3517032916
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2503791456
Short name T883
Test name
Test status
Simulation time 116073277408 ps
CPU time 242.34 seconds
Started Jul 24 06:00:48 PM PDT 24
Finished Jul 24 06:04:51 PM PDT 24
Peak memory 218452 kb
Host smart-79fc92a4-d29d-4ba4-a995-aa07481bc62a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503791456 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2503791456
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1099064987
Short name T856
Test name
Test status
Simulation time 113893388 ps
CPU time 1.21 seconds
Started Jul 24 06:00:55 PM PDT 24
Finished Jul 24 06:00:57 PM PDT 24
Peak memory 216036 kb
Host smart-2025f2d8-0a4d-413e-a07c-f1f4e90249c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099064987 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1099064987
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.292228563
Short name T752
Test name
Test status
Simulation time 45187933 ps
CPU time 0.88 seconds
Started Jul 24 06:00:50 PM PDT 24
Finished Jul 24 06:00:52 PM PDT 24
Peak memory 215140 kb
Host smart-a5dcf760-c8cc-4915-8d93-51d204d44b6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292228563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.292228563
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1361415243
Short name T933
Test name
Test status
Simulation time 12421788 ps
CPU time 0.91 seconds
Started Jul 24 06:01:00 PM PDT 24
Finished Jul 24 06:01:01 PM PDT 24
Peak memory 215972 kb
Host smart-947553c2-471f-46f9-a0a9-4ee3daa8bd66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361415243 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1361415243
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.73912076
Short name T140
Test name
Test status
Simulation time 106955240 ps
CPU time 1.09 seconds
Started Jul 24 06:00:49 PM PDT 24
Finished Jul 24 06:00:51 PM PDT 24
Peak memory 219992 kb
Host smart-4895ac7b-9ef6-42ce-a3ac-7e6a76093d8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73912076 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_dis
able_auto_req_mode.73912076
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2115039567
Short name T521
Test name
Test status
Simulation time 54932236 ps
CPU time 1.03 seconds
Started Jul 24 06:00:48 PM PDT 24
Finished Jul 24 06:00:49 PM PDT 24
Peak memory 221200 kb
Host smart-1e481118-97ab-45e3-b1e3-0886d4ee7e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115039567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2115039567
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1448630237
Short name T83
Test name
Test status
Simulation time 390218715 ps
CPU time 1.42 seconds
Started Jul 24 06:00:54 PM PDT 24
Finished Jul 24 06:00:55 PM PDT 24
Peak memory 217940 kb
Host smart-5483570b-cecf-4290-9690-488ed56e2475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448630237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1448630237
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.725312474
Short name T891
Test name
Test status
Simulation time 56796960 ps
CPU time 0.88 seconds
Started Jul 24 06:01:13 PM PDT 24
Finished Jul 24 06:01:14 PM PDT 24
Peak memory 215592 kb
Host smart-9b1a023f-9da2-4db9-a361-c5de08ab1913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725312474 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.725312474
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.474480162
Short name T437
Test name
Test status
Simulation time 25016565 ps
CPU time 0.97 seconds
Started Jul 24 06:00:49 PM PDT 24
Finished Jul 24 06:00:50 PM PDT 24
Peak memory 215516 kb
Host smart-6166e332-b073-4813-a71a-2559de4bd105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474480162 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.474480162
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.228938570
Short name T303
Test name
Test status
Simulation time 982858843 ps
CPU time 4.62 seconds
Started Jul 24 06:00:51 PM PDT 24
Finished Jul 24 06:00:56 PM PDT 24
Peak memory 215580 kb
Host smart-36972df7-b445-47d0-8910-c38fefa06e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228938570 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.228938570
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3407648122
Short name T229
Test name
Test status
Simulation time 20474073708 ps
CPU time 446.85 seconds
Started Jul 24 06:00:50 PM PDT 24
Finished Jul 24 06:08:18 PM PDT 24
Peak memory 218456 kb
Host smart-de061aa7-2488-4ed2-8935-0cd9bd981556
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407648122 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3407648122
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1503935734
Short name T558
Test name
Test status
Simulation time 75805533 ps
CPU time 1.27 seconds
Started Jul 24 06:01:09 PM PDT 24
Finished Jul 24 06:01:10 PM PDT 24
Peak memory 220236 kb
Host smart-16085c51-b1f9-4c70-b268-6844b2670ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503935734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1503935734
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2697583774
Short name T520
Test name
Test status
Simulation time 25231085 ps
CPU time 0.86 seconds
Started Jul 24 06:01:07 PM PDT 24
Finished Jul 24 06:01:08 PM PDT 24
Peak memory 206980 kb
Host smart-accb0096-e76f-41c1-8d51-0b0d0e9a90b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697583774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2697583774
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3982500160
Short name T349
Test name
Test status
Simulation time 41314332 ps
CPU time 0.92 seconds
Started Jul 24 06:00:50 PM PDT 24
Finished Jul 24 06:00:51 PM PDT 24
Peak memory 216368 kb
Host smart-5e3d820b-d02e-4602-a2d2-89f42f2c3378
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982500160 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3982500160
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.4041476963
Short name T123
Test name
Test status
Simulation time 78513784 ps
CPU time 1.08 seconds
Started Jul 24 06:00:56 PM PDT 24
Finished Jul 24 06:00:57 PM PDT 24
Peak memory 218916 kb
Host smart-21c7288d-fba4-4f51-a403-f0a67d044075
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041476963 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.4041476963
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1199141790
Short name T793
Test name
Test status
Simulation time 118072058 ps
CPU time 1.14 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:00:54 PM PDT 24
Peak memory 225888 kb
Host smart-981aa4d0-8d9c-4f51-9614-9ea4643a9fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199141790 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1199141790
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2905264987
Short name T950
Test name
Test status
Simulation time 260287627 ps
CPU time 1.94 seconds
Started Jul 24 06:00:55 PM PDT 24
Finished Jul 24 06:00:57 PM PDT 24
Peak memory 219208 kb
Host smart-8da0b93c-cbf7-47bd-aebb-e403afb7c464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905264987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2905264987
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1868431494
Short name T410
Test name
Test status
Simulation time 23845814 ps
CPU time 1.14 seconds
Started Jul 24 06:00:51 PM PDT 24
Finished Jul 24 06:00:52 PM PDT 24
Peak memory 215720 kb
Host smart-ec5c0a95-2734-4926-911c-3759823be4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868431494 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1868431494
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.359168831
Short name T723
Test name
Test status
Simulation time 81614299 ps
CPU time 0.93 seconds
Started Jul 24 06:01:05 PM PDT 24
Finished Jul 24 06:01:06 PM PDT 24
Peak memory 215612 kb
Host smart-8c41b946-79ca-498e-89d2-ab05185550c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359168831 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.359168831
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2909135299
Short name T444
Test name
Test status
Simulation time 442078718 ps
CPU time 4.86 seconds
Started Jul 24 06:02:14 PM PDT 24
Finished Jul 24 06:02:19 PM PDT 24
Peak memory 215704 kb
Host smart-41ea492a-f7bd-4124-9e05-e39243655a49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909135299 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2909135299
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2216489195
Short name T331
Test name
Test status
Simulation time 66579319591 ps
CPU time 732.78 seconds
Started Jul 24 06:00:57 PM PDT 24
Finished Jul 24 06:13:10 PM PDT 24
Peak memory 220472 kb
Host smart-48e7d586-c2ba-48ed-8195-726bb87527e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216489195 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2216489195
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2590854431
Short name T160
Test name
Test status
Simulation time 49090432 ps
CPU time 1.17 seconds
Started Jul 24 06:01:05 PM PDT 24
Finished Jul 24 06:01:06 PM PDT 24
Peak memory 218760 kb
Host smart-c0f4841b-b55c-4906-8c83-902a2e97be7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590854431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2590854431
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.227597282
Short name T701
Test name
Test status
Simulation time 125329707 ps
CPU time 0.9 seconds
Started Jul 24 06:01:12 PM PDT 24
Finished Jul 24 06:01:13 PM PDT 24
Peak memory 215296 kb
Host smart-4ff6df0c-af0b-4cc1-a39d-650a4e5f77c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227597282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.227597282
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1838739362
Short name T647
Test name
Test status
Simulation time 18747011 ps
CPU time 0.88 seconds
Started Jul 24 06:00:56 PM PDT 24
Finished Jul 24 06:00:57 PM PDT 24
Peak memory 216704 kb
Host smart-7511383a-ccdb-44b9-a12d-2e517ae520b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838739362 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1838739362
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.4270136821
Short name T697
Test name
Test status
Simulation time 79934833 ps
CPU time 1.02 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:00:55 PM PDT 24
Peak memory 218820 kb
Host smart-4cec75d4-f78b-4428-ae4a-1c11bf002f9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270136821 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.4270136821
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.606187320
Short name T138
Test name
Test status
Simulation time 21515950 ps
CPU time 1.25 seconds
Started Jul 24 06:01:02 PM PDT 24
Finished Jul 24 06:01:03 PM PDT 24
Peak memory 229908 kb
Host smart-a03dda2d-d67f-414f-9546-9a620fee0778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606187320 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.606187320
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3490341554
Short name T317
Test name
Test status
Simulation time 42943333 ps
CPU time 1.5 seconds
Started Jul 24 06:00:51 PM PDT 24
Finished Jul 24 06:00:53 PM PDT 24
Peak memory 218764 kb
Host smart-cb1ddb7d-0fc5-4482-b9ba-55b4ad7df0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490341554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3490341554
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.4202156597
Short name T391
Test name
Test status
Simulation time 31698168 ps
CPU time 0.9 seconds
Started Jul 24 06:00:55 PM PDT 24
Finished Jul 24 06:00:56 PM PDT 24
Peak memory 215928 kb
Host smart-d5c87f2c-f77a-4fa6-b08b-46475c2da1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202156597 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.4202156597
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2823972964
Short name T375
Test name
Test status
Simulation time 25600111 ps
CPU time 0.91 seconds
Started Jul 24 06:00:49 PM PDT 24
Finished Jul 24 06:00:51 PM PDT 24
Peak memory 215640 kb
Host smart-49cd1b03-293e-49e7-be9d-274166e7c9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823972964 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2823972964
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1621046791
Short name T721
Test name
Test status
Simulation time 159036647 ps
CPU time 3.36 seconds
Started Jul 24 06:01:01 PM PDT 24
Finished Jul 24 06:01:04 PM PDT 24
Peak memory 220308 kb
Host smart-b2f5127a-2570-44c4-a38b-0f4e3378ac96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621046791 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1621046791
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3959794255
Short name T41
Test name
Test status
Simulation time 137651520958 ps
CPU time 806.4 seconds
Started Jul 24 06:00:55 PM PDT 24
Finished Jul 24 06:14:22 PM PDT 24
Peak memory 221160 kb
Host smart-d65231bf-239b-41e5-8bda-389cbbe09a86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959794255 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3959794255
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3068786793
Short name T806
Test name
Test status
Simulation time 52427156 ps
CPU time 1.32 seconds
Started Jul 24 06:00:52 PM PDT 24
Finished Jul 24 06:00:53 PM PDT 24
Peak memory 221172 kb
Host smart-cd1475b1-a060-4aad-ad50-01306abd2a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068786793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3068786793
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.951301405
Short name T983
Test name
Test status
Simulation time 18419319 ps
CPU time 0.98 seconds
Started Jul 24 06:01:00 PM PDT 24
Finished Jul 24 06:01:01 PM PDT 24
Peak memory 207068 kb
Host smart-e7d9ed7e-67d3-4156-9074-c9797b565d29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951301405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.951301405
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1488184872
Short name T921
Test name
Test status
Simulation time 109852179 ps
CPU time 0.84 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:00:54 PM PDT 24
Peak memory 215792 kb
Host smart-dd7b4cfe-d48e-4ebb-9117-57adbbaa6262
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488184872 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1488184872
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2287283693
Short name T555
Test name
Test status
Simulation time 25042687 ps
CPU time 1.04 seconds
Started Jul 24 06:00:49 PM PDT 24
Finished Jul 24 06:00:50 PM PDT 24
Peak memory 218920 kb
Host smart-da6b2315-84e6-4445-8cac-22d9154045de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287283693 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2287283693
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3755949430
Short name T745
Test name
Test status
Simulation time 44753598 ps
CPU time 1.23 seconds
Started Jul 24 06:01:01 PM PDT 24
Finished Jul 24 06:01:02 PM PDT 24
Peak memory 220148 kb
Host smart-a88cf4fd-9169-4412-9ca0-359c8354113b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755949430 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3755949430
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3185554134
Short name T440
Test name
Test status
Simulation time 56182075 ps
CPU time 1.33 seconds
Started Jul 24 06:00:58 PM PDT 24
Finished Jul 24 06:01:00 PM PDT 24
Peak memory 217740 kb
Host smart-1fedcf04-9dc8-4d0b-b472-f6c93ad4cd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185554134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3185554134
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.619345207
Short name T477
Test name
Test status
Simulation time 35780940 ps
CPU time 0.94 seconds
Started Jul 24 06:00:51 PM PDT 24
Finished Jul 24 06:00:52 PM PDT 24
Peak memory 215964 kb
Host smart-0ea9519b-6f44-4844-9c3e-149db20c2de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619345207 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.619345207
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2624958924
Short name T427
Test name
Test status
Simulation time 80877196 ps
CPU time 0.87 seconds
Started Jul 24 06:00:47 PM PDT 24
Finished Jul 24 06:00:48 PM PDT 24
Peak memory 215684 kb
Host smart-863679dc-46f5-452e-a2d2-18a8d0a5d207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624958924 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2624958924
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2622520275
Short name T554
Test name
Test status
Simulation time 478926983 ps
CPU time 3.05 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:00:57 PM PDT 24
Peak memory 217408 kb
Host smart-cea2b69b-f855-46cc-9730-674f44639b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622520275 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2622520275
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2557713719
Short name T639
Test name
Test status
Simulation time 56547451093 ps
CPU time 501.13 seconds
Started Jul 24 06:01:06 PM PDT 24
Finished Jul 24 06:09:27 PM PDT 24
Peak memory 218552 kb
Host smart-e38c1af9-4cc4-4873-ad2d-ec07fe49aef4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557713719 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2557713719
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.933989028
Short name T1
Test name
Test status
Simulation time 76291034 ps
CPU time 1.24 seconds
Started Jul 24 06:01:01 PM PDT 24
Finished Jul 24 06:01:02 PM PDT 24
Peak memory 219952 kb
Host smart-e75ac1ef-521f-4144-bf17-4b72f8f9941b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933989028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.933989028
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.462783034
Short name T814
Test name
Test status
Simulation time 26072037 ps
CPU time 0.88 seconds
Started Jul 24 06:00:54 PM PDT 24
Finished Jul 24 06:00:55 PM PDT 24
Peak memory 215288 kb
Host smart-50eb3a9f-b48e-49c9-a6b6-75b747971dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462783034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.462783034
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3519257602
Short name T165
Test name
Test status
Simulation time 87784345 ps
CPU time 0.93 seconds
Started Jul 24 06:01:00 PM PDT 24
Finished Jul 24 06:01:01 PM PDT 24
Peak memory 216604 kb
Host smart-fa3e636d-3380-4c19-9ee6-a3ac7f236c33
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519257602 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3519257602
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3345836217
Short name T627
Test name
Test status
Simulation time 101168042 ps
CPU time 1.25 seconds
Started Jul 24 06:01:08 PM PDT 24
Finished Jul 24 06:01:10 PM PDT 24
Peak memory 217160 kb
Host smart-48da8f45-eecc-47c1-a9e3-170750d2c919
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345836217 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3345836217
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3894981724
Short name T716
Test name
Test status
Simulation time 22389161 ps
CPU time 0.92 seconds
Started Jul 24 06:00:52 PM PDT 24
Finished Jul 24 06:00:53 PM PDT 24
Peak memory 218968 kb
Host smart-63a2a566-ea03-4b27-9f9a-a2e444b358e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894981724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3894981724
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2214274812
Short name T312
Test name
Test status
Simulation time 28531458 ps
CPU time 1.31 seconds
Started Jul 24 06:00:58 PM PDT 24
Finished Jul 24 06:00:59 PM PDT 24
Peak memory 218904 kb
Host smart-cc744688-420b-4944-8fd2-1ab9440f952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214274812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2214274812
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1241379280
Short name T910
Test name
Test status
Simulation time 21821810 ps
CPU time 1.04 seconds
Started Jul 24 06:02:26 PM PDT 24
Finished Jul 24 06:02:27 PM PDT 24
Peak memory 215908 kb
Host smart-23f25429-75a3-409e-8a0b-9e5ac1b4b644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241379280 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1241379280
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1711407842
Short name T694
Test name
Test status
Simulation time 47379794 ps
CPU time 0.93 seconds
Started Jul 24 06:00:59 PM PDT 24
Finished Jul 24 06:01:00 PM PDT 24
Peak memory 215580 kb
Host smart-37e7e860-7d2f-438f-82a4-bb14c0cad626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711407842 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1711407842
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1073381172
Short name T347
Test name
Test status
Simulation time 180248307 ps
CPU time 3.84 seconds
Started Jul 24 06:00:52 PM PDT 24
Finished Jul 24 06:00:56 PM PDT 24
Peak memory 218836 kb
Host smart-799429e8-f03a-41f3-8a83-6024193e76d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073381172 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1073381172
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.4146801786
Short name T314
Test name
Test status
Simulation time 435091693131 ps
CPU time 1369.58 seconds
Started Jul 24 06:01:04 PM PDT 24
Finished Jul 24 06:23:54 PM PDT 24
Peak memory 234480 kb
Host smart-8e4754c4-61fa-4cd2-a90d-6263bdbbcd51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146801786 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.4146801786
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1835410962
Short name T209
Test name
Test status
Simulation time 49689712 ps
CPU time 1.13 seconds
Started Jul 24 06:00:55 PM PDT 24
Finished Jul 24 06:00:56 PM PDT 24
Peak memory 219124 kb
Host smart-fdb44862-dee2-40aa-b394-61bad11a851a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835410962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1835410962
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3853141398
Short name T802
Test name
Test status
Simulation time 82947014 ps
CPU time 1.01 seconds
Started Jul 24 06:01:11 PM PDT 24
Finished Jul 24 06:01:12 PM PDT 24
Peak memory 207044 kb
Host smart-deedbb44-9483-4863-aa06-c8465157ae33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853141398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3853141398
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1367168797
Short name T505
Test name
Test status
Simulation time 142406343 ps
CPU time 0.89 seconds
Started Jul 24 06:01:12 PM PDT 24
Finished Jul 24 06:01:14 PM PDT 24
Peak memory 216356 kb
Host smart-d0bcfb15-a594-4d42-b0d5-dd5c0bafb0f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367168797 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1367168797
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1097921913
Short name T840
Test name
Test status
Simulation time 50378275 ps
CPU time 1.65 seconds
Started Jul 24 06:00:55 PM PDT 24
Finished Jul 24 06:00:57 PM PDT 24
Peak memory 217436 kb
Host smart-0f8de66b-a265-4e4f-b91c-5e2c93d4be27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097921913 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1097921913
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1573380974
Short name T199
Test name
Test status
Simulation time 21146226 ps
CPU time 1.15 seconds
Started Jul 24 06:01:08 PM PDT 24
Finished Jul 24 06:01:10 PM PDT 24
Peak memory 219632 kb
Host smart-89553023-4933-4577-ad0d-5790a4aa6134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573380974 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1573380974
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_intr.1047956754
Short name T687
Test name
Test status
Simulation time 77345357 ps
CPU time 0.81 seconds
Started Jul 24 06:00:49 PM PDT 24
Finished Jul 24 06:00:50 PM PDT 24
Peak memory 215900 kb
Host smart-9a06f1b9-1097-4bac-a2bb-c9b218d72eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047956754 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1047956754
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.164079715
Short name T225
Test name
Test status
Simulation time 27713209 ps
CPU time 0.92 seconds
Started Jul 24 06:01:09 PM PDT 24
Finished Jul 24 06:01:10 PM PDT 24
Peak memory 215596 kb
Host smart-7027e92e-1ccb-49b3-93bd-753a0d2d8733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164079715 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.164079715
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1505213611
Short name T88
Test name
Test status
Simulation time 957922684 ps
CPU time 3.37 seconds
Started Jul 24 06:01:03 PM PDT 24
Finished Jul 24 06:01:07 PM PDT 24
Peak memory 220436 kb
Host smart-e9049cf9-bdc1-44c2-b8fe-04fa0bcd7100
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505213611 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1505213611
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.895656811
Short name T881
Test name
Test status
Simulation time 14881134006 ps
CPU time 323.15 seconds
Started Jul 24 06:01:11 PM PDT 24
Finished Jul 24 06:06:34 PM PDT 24
Peak memory 218856 kb
Host smart-4d29fb39-2e88-43fd-b121-0d4c01314399
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895656811 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.895656811
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2152061942
Short name T178
Test name
Test status
Simulation time 24217854 ps
CPU time 1.12 seconds
Started Jul 24 06:01:04 PM PDT 24
Finished Jul 24 06:01:06 PM PDT 24
Peak memory 219116 kb
Host smart-e3d0e074-b1de-45e5-8b21-412d45c5cb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152061942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2152061942
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.4069290408
Short name T935
Test name
Test status
Simulation time 13092324 ps
CPU time 0.9 seconds
Started Jul 24 06:01:03 PM PDT 24
Finished Jul 24 06:01:04 PM PDT 24
Peak memory 215184 kb
Host smart-1955086c-640c-4836-95a6-6ce00ac150fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069290408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.4069290408
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.309818133
Short name T193
Test name
Test status
Simulation time 19912029 ps
CPU time 0.88 seconds
Started Jul 24 06:00:48 PM PDT 24
Finished Jul 24 06:00:49 PM PDT 24
Peak memory 216524 kb
Host smart-df8b04d7-f078-4d44-b4a6-4754331872e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309818133 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.309818133
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.3408474733
Short name T6
Test name
Test status
Simulation time 78192777 ps
CPU time 0.99 seconds
Started Jul 24 06:00:58 PM PDT 24
Finished Jul 24 06:00:59 PM PDT 24
Peak memory 220068 kb
Host smart-28d5608a-a613-4e1c-81fe-6c595546435b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408474733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3408474733
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2631898589
Short name T956
Test name
Test status
Simulation time 46401337 ps
CPU time 1.77 seconds
Started Jul 24 06:00:58 PM PDT 24
Finished Jul 24 06:01:00 PM PDT 24
Peak memory 218884 kb
Host smart-ac4da936-c2f6-47ac-8e1f-1c4aec5813d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631898589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2631898589
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2855652408
Short name T49
Test name
Test status
Simulation time 27849010 ps
CPU time 1.04 seconds
Started Jul 24 06:01:02 PM PDT 24
Finished Jul 24 06:01:04 PM PDT 24
Peak memory 224348 kb
Host smart-e2336bc6-53ce-46cd-b5b3-700e2dcce7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855652408 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2855652408
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.116876470
Short name T503
Test name
Test status
Simulation time 18103497 ps
CPU time 1 seconds
Started Jul 24 06:00:50 PM PDT 24
Finished Jul 24 06:00:52 PM PDT 24
Peak memory 215584 kb
Host smart-142bef61-e6b2-4eb7-9fe2-5e9f98d8db5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116876470 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.116876470
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1615819064
Short name T382
Test name
Test status
Simulation time 451102645 ps
CPU time 8.05 seconds
Started Jul 24 06:01:08 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 220836 kb
Host smart-2b74cba1-b744-4fdb-8176-8ce7822c042a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615819064 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1615819064
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1575560154
Short name T775
Test name
Test status
Simulation time 86842595268 ps
CPU time 1005.62 seconds
Started Jul 24 06:01:07 PM PDT 24
Finished Jul 24 06:17:52 PM PDT 24
Peak memory 223048 kb
Host smart-b11fe5cd-03df-4ebc-9126-f01a3acafbe0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575560154 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1575560154
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3178814282
Short name T670
Test name
Test status
Simulation time 64796980 ps
CPU time 1.17 seconds
Started Jul 24 06:00:52 PM PDT 24
Finished Jul 24 06:00:53 PM PDT 24
Peak memory 219548 kb
Host smart-19908a8b-4aea-48ad-bf7d-6c6e42f21f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178814282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3178814282
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2387110575
Short name T413
Test name
Test status
Simulation time 38301484 ps
CPU time 0.83 seconds
Started Jul 24 06:01:08 PM PDT 24
Finished Jul 24 06:01:09 PM PDT 24
Peak memory 207104 kb
Host smart-00d9b5cc-c7dc-4f05-85f1-07441e1a86d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387110575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2387110575
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3204412624
Short name T970
Test name
Test status
Simulation time 12072786 ps
CPU time 0.88 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:00:54 PM PDT 24
Peak memory 216396 kb
Host smart-0f4d5495-01ae-40ef-ab2e-41957bbbbd0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204412624 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3204412624
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2996102302
Short name T139
Test name
Test status
Simulation time 28768015 ps
CPU time 1.05 seconds
Started Jul 24 06:00:51 PM PDT 24
Finished Jul 24 06:00:52 PM PDT 24
Peak memory 217200 kb
Host smart-400d5683-214c-4b86-bd3e-75d4aa037db4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996102302 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2996102302
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3020619118
Short name T631
Test name
Test status
Simulation time 20855037 ps
CPU time 1.05 seconds
Started Jul 24 06:00:52 PM PDT 24
Finished Jul 24 06:00:54 PM PDT 24
Peak memory 224252 kb
Host smart-d594eaff-3c03-42c4-99a2-66ddafc57a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020619118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3020619118
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3830353794
Short name T770
Test name
Test status
Simulation time 30846717 ps
CPU time 1.36 seconds
Started Jul 24 06:01:14 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 218824 kb
Host smart-3d2e66ec-ab92-4410-9299-558eb6f497a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830353794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3830353794
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2936614596
Short name T36
Test name
Test status
Simulation time 32552523 ps
CPU time 0.99 seconds
Started Jul 24 06:01:02 PM PDT 24
Finished Jul 24 06:01:04 PM PDT 24
Peak memory 216220 kb
Host smart-0faf2f0d-2563-4217-9929-62c96a5d4503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936614596 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2936614596
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3113611496
Short name T978
Test name
Test status
Simulation time 53283862 ps
CPU time 0.97 seconds
Started Jul 24 06:01:02 PM PDT 24
Finished Jul 24 06:01:03 PM PDT 24
Peak memory 215600 kb
Host smart-aa43efbe-60b5-4da4-8afd-48789514c2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113611496 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3113611496
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2605497942
Short name T786
Test name
Test status
Simulation time 186906658 ps
CPU time 3.93 seconds
Started Jul 24 06:01:10 PM PDT 24
Finished Jul 24 06:01:14 PM PDT 24
Peak memory 219916 kb
Host smart-d38a35aa-020d-45fb-a73c-36aa0560cdc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605497942 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2605497942
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1836830776
Short name T71
Test name
Test status
Simulation time 162261664923 ps
CPU time 1858.01 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:31:52 PM PDT 24
Peak memory 226728 kb
Host smart-355257e5-0d96-4b2c-a4f5-5e469bdcd7b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836830776 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1836830776
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.665005782
Short name T649
Test name
Test status
Simulation time 68343198 ps
CPU time 1.28 seconds
Started Jul 24 06:01:14 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 219460 kb
Host smart-cf0b7a8e-6c5c-42c7-9536-fcb56803a88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665005782 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.665005782
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1046201828
Short name T572
Test name
Test status
Simulation time 13072091 ps
CPU time 0.89 seconds
Started Jul 24 06:01:10 PM PDT 24
Finished Jul 24 06:01:11 PM PDT 24
Peak memory 207024 kb
Host smart-3e161d82-b9be-4073-a11d-678a90655472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046201828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1046201828
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2145004357
Short name T146
Test name
Test status
Simulation time 14168416 ps
CPU time 0.94 seconds
Started Jul 24 06:01:03 PM PDT 24
Finished Jul 24 06:01:04 PM PDT 24
Peak memory 215964 kb
Host smart-e77dd2fb-e026-4d9b-bdcd-cb810fa7d5c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145004357 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2145004357
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.672228361
Short name T616
Test name
Test status
Simulation time 98754047 ps
CPU time 1.15 seconds
Started Jul 24 06:01:02 PM PDT 24
Finished Jul 24 06:01:03 PM PDT 24
Peak memory 217408 kb
Host smart-3e5a02e2-33c7-406a-9509-af3b829834d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672228361 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.672228361
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2035897399
Short name T708
Test name
Test status
Simulation time 22637544 ps
CPU time 0.99 seconds
Started Jul 24 06:01:11 PM PDT 24
Finished Jul 24 06:01:13 PM PDT 24
Peak memory 219876 kb
Host smart-e7c0a161-ab8c-4578-a20f-5a08c92ecb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035897399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2035897399
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_intr.1049644920
Short name T506
Test name
Test status
Simulation time 30352995 ps
CPU time 0.91 seconds
Started Jul 24 06:01:09 PM PDT 24
Finished Jul 24 06:01:10 PM PDT 24
Peak memory 215716 kb
Host smart-9864d11e-7d90-422d-85cd-54217a12c8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049644920 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1049644920
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2764959061
Short name T809
Test name
Test status
Simulation time 28283485 ps
CPU time 0.94 seconds
Started Jul 24 06:01:01 PM PDT 24
Finished Jul 24 06:01:02 PM PDT 24
Peak memory 215608 kb
Host smart-6b5e1c38-093f-4fa9-89d4-44043ee22bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764959061 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2764959061
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1327374967
Short name T367
Test name
Test status
Simulation time 247462350 ps
CPU time 3.13 seconds
Started Jul 24 06:01:12 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 215708 kb
Host smart-9cb13e19-4dce-45c4-a0e3-e8b23f110cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327374967 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1327374967
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2458210904
Short name T777
Test name
Test status
Simulation time 132609892681 ps
CPU time 755.81 seconds
Started Jul 24 06:01:04 PM PDT 24
Finished Jul 24 06:13:40 PM PDT 24
Peak memory 224148 kb
Host smart-9ae9c3db-5a4f-4cc4-a895-5cf3da489d38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458210904 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2458210904
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2379930138
Short name T300
Test name
Test status
Simulation time 96841622 ps
CPU time 1.21 seconds
Started Jul 24 05:59:55 PM PDT 24
Finished Jul 24 05:59:56 PM PDT 24
Peak memory 216072 kb
Host smart-c26dc45e-b936-45ec-8bae-f16c5b66a78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379930138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2379930138
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1090402046
Short name T733
Test name
Test status
Simulation time 51503255 ps
CPU time 0.91 seconds
Started Jul 24 06:00:03 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215492 kb
Host smart-ff12945e-24cc-4ae9-8239-9b96c0e16e58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090402046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1090402046
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1631310366
Short name T200
Test name
Test status
Simulation time 58267893 ps
CPU time 0.89 seconds
Started Jul 24 05:59:57 PM PDT 24
Finished Jul 24 05:59:58 PM PDT 24
Peak memory 216716 kb
Host smart-fee90768-9e0c-4c7e-ab53-2bdb9938c5a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631310366 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1631310366
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2389723080
Short name T738
Test name
Test status
Simulation time 103282711 ps
CPU time 1.08 seconds
Started Jul 24 06:00:04 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 218800 kb
Host smart-5f97acf0-1a28-40f0-bb6a-2d127094fcfd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389723080 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2389723080
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2534631016
Short name T116
Test name
Test status
Simulation time 24859309 ps
CPU time 1.02 seconds
Started Jul 24 05:59:57 PM PDT 24
Finished Jul 24 05:59:58 PM PDT 24
Peak memory 219864 kb
Host smart-66a7039e-a9d5-4968-88b8-4e8ac21259ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534631016 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2534631016
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2538807214
Short name T454
Test name
Test status
Simulation time 84384563 ps
CPU time 1.46 seconds
Started Jul 24 05:59:56 PM PDT 24
Finished Jul 24 05:59:58 PM PDT 24
Peak memory 219044 kb
Host smart-834eb077-f1c3-4840-9956-fc5789700ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538807214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2538807214
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2126638866
Short name T82
Test name
Test status
Simulation time 34461297 ps
CPU time 0.92 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:01 PM PDT 24
Peak memory 216280 kb
Host smart-a3835cd0-5ec9-41bb-a778-1a5ffd1bb40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126638866 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2126638866
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2863687568
Short name T31
Test name
Test status
Simulation time 55588143 ps
CPU time 0.94 seconds
Started Jul 24 05:59:56 PM PDT 24
Finished Jul 24 05:59:57 PM PDT 24
Peak memory 207408 kb
Host smart-a853df69-c18e-4043-b19c-4760b744f2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863687568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2863687568
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.953733404
Short name T829
Test name
Test status
Simulation time 24970713 ps
CPU time 1 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:01 PM PDT 24
Peak memory 215620 kb
Host smart-f60cfd65-3a04-4701-8b50-1aada2451026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953733404 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.953733404
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.165221959
Short name T237
Test name
Test status
Simulation time 136703216 ps
CPU time 1.55 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:02 PM PDT 24
Peak memory 206948 kb
Host smart-899d7cbc-9993-4caf-9e73-d6e474f068f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165221959 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.165221959
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3570915949
Short name T490
Test name
Test status
Simulation time 73412827999 ps
CPU time 431.49 seconds
Started Jul 24 05:59:54 PM PDT 24
Finished Jul 24 06:07:06 PM PDT 24
Peak memory 218616 kb
Host smart-66225aee-fd19-4205-8def-719dbb3931aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570915949 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3570915949
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.181784692
Short name T827
Test name
Test status
Simulation time 277974010 ps
CPU time 1.35 seconds
Started Jul 24 06:00:49 PM PDT 24
Finished Jul 24 06:00:51 PM PDT 24
Peak memory 219760 kb
Host smart-986802f8-ecc0-4cb8-8d40-26172305f5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181784692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.181784692
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.2977498433
Short name T173
Test name
Test status
Simulation time 20198293 ps
CPU time 1.1 seconds
Started Jul 24 06:00:52 PM PDT 24
Finished Jul 24 06:00:53 PM PDT 24
Peak memory 218856 kb
Host smart-782af776-b673-4d01-8847-f3479ddfba60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977498433 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2977498433
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3181387868
Short name T342
Test name
Test status
Simulation time 157617051 ps
CPU time 1.05 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:00:54 PM PDT 24
Peak memory 217620 kb
Host smart-2b95fd25-3850-40ae-bf39-f7d37e6454b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181387868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3181387868
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1768812907
Short name T909
Test name
Test status
Simulation time 30290143 ps
CPU time 1.46 seconds
Started Jul 24 06:01:12 PM PDT 24
Finished Jul 24 06:01:14 PM PDT 24
Peak memory 220656 kb
Host smart-ec762b90-abdc-4312-9216-82c8855d4402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768812907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1768812907
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.1640897698
Short name T918
Test name
Test status
Simulation time 22084272 ps
CPU time 1.11 seconds
Started Jul 24 06:01:03 PM PDT 24
Finished Jul 24 06:01:05 PM PDT 24
Peak memory 224276 kb
Host smart-77ce6fcf-1d28-4edc-afc4-50b8306c2b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640897698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1640897698
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.829439547
Short name T281
Test name
Test status
Simulation time 36612627 ps
CPU time 1.42 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:00:55 PM PDT 24
Peak memory 218840 kb
Host smart-e7f5e83f-ae03-4e24-ad84-a9f7ba78b690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829439547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.829439547
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.2196273545
Short name T478
Test name
Test status
Simulation time 36024120 ps
CPU time 1.05 seconds
Started Jul 24 06:01:09 PM PDT 24
Finished Jul 24 06:01:10 PM PDT 24
Peak memory 218808 kb
Host smart-acd0a8ed-6ded-453d-8d21-087d6b55ff0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196273545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.2196273545
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.1307055751
Short name T420
Test name
Test status
Simulation time 19089306 ps
CPU time 1.11 seconds
Started Jul 24 06:00:57 PM PDT 24
Finished Jul 24 06:00:59 PM PDT 24
Peak memory 218424 kb
Host smart-8d1e86fc-70fe-4fa5-8420-ca96f7308f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307055751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1307055751
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2604117882
Short name T325
Test name
Test status
Simulation time 50267939 ps
CPU time 1.42 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:00:55 PM PDT 24
Peak memory 219352 kb
Host smart-d5cbdb08-8522-4ec3-a3ff-e699a2b6041c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604117882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2604117882
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.3135288191
Short name T76
Test name
Test status
Simulation time 26702707 ps
CPU time 1.22 seconds
Started Jul 24 06:01:03 PM PDT 24
Finished Jul 24 06:01:04 PM PDT 24
Peak memory 220180 kb
Host smart-f727a42c-26a1-44e5-b576-9b29d84d7779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135288191 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3135288191
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.1269902403
Short name T148
Test name
Test status
Simulation time 92115020 ps
CPU time 1 seconds
Started Jul 24 06:01:09 PM PDT 24
Finished Jul 24 06:01:11 PM PDT 24
Peak memory 224096 kb
Host smart-f7975b5a-d9df-4934-bd28-d1182680d794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269902403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1269902403
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3158826389
Short name T808
Test name
Test status
Simulation time 105910651 ps
CPU time 2.1 seconds
Started Jul 24 06:01:04 PM PDT 24
Finished Jul 24 06:01:06 PM PDT 24
Peak memory 220068 kb
Host smart-e736b7cd-e7da-43d6-86b8-632b0b6b7749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158826389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3158826389
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.849946261
Short name T449
Test name
Test status
Simulation time 66143631 ps
CPU time 1.16 seconds
Started Jul 24 06:01:00 PM PDT 24
Finished Jul 24 06:01:01 PM PDT 24
Peak memory 219512 kb
Host smart-448b3e34-4d26-4141-b716-a08cab5939bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849946261 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.849946261
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.690940021
Short name T706
Test name
Test status
Simulation time 26590786 ps
CPU time 1.32 seconds
Started Jul 24 06:01:18 PM PDT 24
Finished Jul 24 06:01:19 PM PDT 24
Peak memory 219416 kb
Host smart-2bfbaa4d-c9c2-46fb-b854-63c89e15c583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690940021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.690940021
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2986723865
Short name T976
Test name
Test status
Simulation time 53510701 ps
CPU time 2.02 seconds
Started Jul 24 06:01:09 PM PDT 24
Finished Jul 24 06:01:11 PM PDT 24
Peak memory 220120 kb
Host smart-ddf21515-7f9d-49f8-baee-394107304db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986723865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2986723865
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.3515963114
Short name T743
Test name
Test status
Simulation time 25868579 ps
CPU time 1.14 seconds
Started Jul 24 06:01:14 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 218788 kb
Host smart-150eb7a6-c1d0-457d-9b31-3b3ddca1b9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515963114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.3515963114
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.492616494
Short name T110
Test name
Test status
Simulation time 160957481 ps
CPU time 1.06 seconds
Started Jul 24 06:01:06 PM PDT 24
Finished Jul 24 06:01:07 PM PDT 24
Peak memory 229972 kb
Host smart-51a46d8a-8081-49d0-8519-bfe24b1dad98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492616494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.492616494
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1732989060
Short name T667
Test name
Test status
Simulation time 108980749 ps
CPU time 0.97 seconds
Started Jul 24 06:01:10 PM PDT 24
Finished Jul 24 06:01:11 PM PDT 24
Peak memory 217652 kb
Host smart-4bc0b461-d2ff-4569-b243-8f760e7f0e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732989060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1732989060
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.3755507219
Short name T882
Test name
Test status
Simulation time 51725034 ps
CPU time 1.23 seconds
Started Jul 24 06:00:55 PM PDT 24
Finished Jul 24 06:00:56 PM PDT 24
Peak memory 219968 kb
Host smart-4099fb11-4aa4-4e00-b63e-8c917a396c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755507219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.3755507219
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.3467093195
Short name T924
Test name
Test status
Simulation time 19617151 ps
CPU time 1.15 seconds
Started Jul 24 06:01:12 PM PDT 24
Finished Jul 24 06:01:13 PM PDT 24
Peak memory 219028 kb
Host smart-fc015544-7e82-4622-9ba6-5162c4414676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467093195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3467093195
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/57.edn_alert.4216004077
Short name T609
Test name
Test status
Simulation time 85043195 ps
CPU time 1.11 seconds
Started Jul 24 06:00:55 PM PDT 24
Finished Jul 24 06:00:56 PM PDT 24
Peak memory 218988 kb
Host smart-5c701cac-3f40-4645-bae6-ead7a22eb142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216004077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.4216004077
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.4123564920
Short name T121
Test name
Test status
Simulation time 67178640 ps
CPU time 1.13 seconds
Started Jul 24 06:01:09 PM PDT 24
Finished Jul 24 06:01:10 PM PDT 24
Peak memory 229672 kb
Host smart-ee4ece75-8c4f-4f7a-8e6b-7132ddc070b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123564920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.4123564920
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2930635111
Short name T655
Test name
Test status
Simulation time 136378813 ps
CPU time 1.13 seconds
Started Jul 24 06:01:03 PM PDT 24
Finished Jul 24 06:01:05 PM PDT 24
Peak memory 217584 kb
Host smart-27d582a9-3703-468a-8e27-131df1d105a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930635111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2930635111
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.1387697648
Short name T566
Test name
Test status
Simulation time 25130742 ps
CPU time 1.2 seconds
Started Jul 24 06:01:18 PM PDT 24
Finished Jul 24 06:01:19 PM PDT 24
Peak memory 220188 kb
Host smart-54dbd018-ea08-45a2-b1f5-82c5f335c338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387697648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1387697648
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.1669372947
Short name T965
Test name
Test status
Simulation time 57762729 ps
CPU time 0.96 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:00:55 PM PDT 24
Peak memory 219000 kb
Host smart-44f7ce52-86b1-49e0-81c6-7864df247eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669372947 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1669372947
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2964976788
Short name T55
Test name
Test status
Simulation time 32876467 ps
CPU time 1.42 seconds
Started Jul 24 06:01:10 PM PDT 24
Finished Jul 24 06:01:12 PM PDT 24
Peak memory 218944 kb
Host smart-2b429a9f-3a1d-42d0-a05b-9d2b1885e851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964976788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2964976788
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.602445867
Short name T550
Test name
Test status
Simulation time 27889571 ps
CPU time 1.22 seconds
Started Jul 24 06:01:10 PM PDT 24
Finished Jul 24 06:01:12 PM PDT 24
Peak memory 220264 kb
Host smart-d92b33b3-a33d-4fc1-bed6-62f150e69ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602445867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.602445867
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.3658343133
Short name T98
Test name
Test status
Simulation time 96561332 ps
CPU time 0.94 seconds
Started Jul 24 06:01:12 PM PDT 24
Finished Jul 24 06:01:14 PM PDT 24
Peak memory 220024 kb
Host smart-5ac0ec25-3450-4aaf-87b6-f687cc48b700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658343133 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3658343133
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3159354552
Short name T315
Test name
Test status
Simulation time 54306697 ps
CPU time 1.19 seconds
Started Jul 24 06:00:55 PM PDT 24
Finished Jul 24 06:00:56 PM PDT 24
Peak memory 217484 kb
Host smart-52e5c574-2415-49b0-9df5-50d376c0b0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159354552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3159354552
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2218764957
Short name T635
Test name
Test status
Simulation time 64506359 ps
CPU time 1.09 seconds
Started Jul 24 06:00:02 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 219124 kb
Host smart-96e48d68-4eb9-401f-a725-d164fa6bd8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218764957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2218764957
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3897503235
Short name T414
Test name
Test status
Simulation time 34975089 ps
CPU time 0.92 seconds
Started Jul 24 05:59:59 PM PDT 24
Finished Jul 24 06:00:00 PM PDT 24
Peak memory 215492 kb
Host smart-e4b15f24-7486-4bf9-be3a-39e38af7d233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897503235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3897503235
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2052163616
Short name T783
Test name
Test status
Simulation time 15287284 ps
CPU time 0.87 seconds
Started Jul 24 05:59:59 PM PDT 24
Finished Jul 24 06:00:01 PM PDT 24
Peak memory 216604 kb
Host smart-1fb08842-3581-4fdb-aa3c-c261afeff6db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052163616 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2052163616
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.1639249921
Short name T763
Test name
Test status
Simulation time 19145756 ps
CPU time 1.07 seconds
Started Jul 24 06:00:06 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 219824 kb
Host smart-9a252fab-5e2b-4d5f-844e-605beaa22c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639249921 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1639249921
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.641387455
Short name T801
Test name
Test status
Simulation time 28001564 ps
CPU time 1.24 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:01 PM PDT 24
Peak memory 219252 kb
Host smart-14dacb0f-03ba-4e21-9065-c5e99beb0086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641387455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.641387455
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1412449041
Short name T485
Test name
Test status
Simulation time 20765393 ps
CPU time 1.13 seconds
Started Jul 24 06:00:02 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215956 kb
Host smart-e8ae0683-b45f-4ad0-8d3d-d13376c488d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412449041 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1412449041
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.303885538
Short name T293
Test name
Test status
Simulation time 16197429 ps
CPU time 1.09 seconds
Started Jul 24 06:00:01 PM PDT 24
Finished Jul 24 06:00:03 PM PDT 24
Peak memory 207436 kb
Host smart-30252bc4-8c26-4a50-a5f9-72f9f6fb1ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303885538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.303885538
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3359009022
Short name T601
Test name
Test status
Simulation time 14627338 ps
CPU time 0.95 seconds
Started Jul 24 06:00:05 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215776 kb
Host smart-c87bfefa-1bfe-40a1-a403-bccde1a903b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359009022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3359009022
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3873709530
Short name T487
Test name
Test status
Simulation time 251093171 ps
CPU time 5.05 seconds
Started Jul 24 05:59:58 PM PDT 24
Finished Jul 24 06:00:03 PM PDT 24
Peak memory 217580 kb
Host smart-ce81b12d-b9b5-4bc0-8cf8-48cd071a16a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873709530 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3873709530
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2393340924
Short name T373
Test name
Test status
Simulation time 178014137771 ps
CPU time 1011.67 seconds
Started Jul 24 06:00:01 PM PDT 24
Finished Jul 24 06:16:53 PM PDT 24
Peak memory 223092 kb
Host smart-ad2d2816-57eb-4110-a738-411b57607491
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393340924 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2393340924
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.323056483
Short name T386
Test name
Test status
Simulation time 80994252 ps
CPU time 1.15 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:00:54 PM PDT 24
Peak memory 219924 kb
Host smart-2a1999fe-53c2-4ab3-a818-06df10f2d249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323056483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.323056483
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.882026468
Short name T102
Test name
Test status
Simulation time 36231815 ps
CPU time 1.2 seconds
Started Jul 24 06:00:52 PM PDT 24
Finished Jul 24 06:00:54 PM PDT 24
Peak memory 229988 kb
Host smart-736598ae-43be-4382-902b-81fe52fa0b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882026468 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.882026468
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1896875327
Short name T395
Test name
Test status
Simulation time 105883589 ps
CPU time 1.07 seconds
Started Jul 24 06:00:52 PM PDT 24
Finished Jul 24 06:00:53 PM PDT 24
Peak memory 217576 kb
Host smart-05fcab5c-1aea-4a37-af48-b9b8720b1d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896875327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1896875327
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.4163076214
Short name T466
Test name
Test status
Simulation time 52662184 ps
CPU time 1.14 seconds
Started Jul 24 06:01:03 PM PDT 24
Finished Jul 24 06:01:05 PM PDT 24
Peak memory 219808 kb
Host smart-285cd836-f005-4f56-84ed-b98fd664fb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163076214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.4163076214
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.3029517502
Short name T939
Test name
Test status
Simulation time 22104388 ps
CPU time 1.03 seconds
Started Jul 24 06:00:56 PM PDT 24
Finished Jul 24 06:00:57 PM PDT 24
Peak memory 218972 kb
Host smart-3b7fbb3e-511d-4293-aa41-62232342e415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029517502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3029517502
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.780494718
Short name T848
Test name
Test status
Simulation time 35368999 ps
CPU time 1.27 seconds
Started Jul 24 06:00:57 PM PDT 24
Finished Jul 24 06:00:58 PM PDT 24
Peak memory 217688 kb
Host smart-589f90b7-8c22-4765-8cb3-ea3feb303470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780494718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.780494718
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.1962041858
Short name T768
Test name
Test status
Simulation time 44720619 ps
CPU time 1.2 seconds
Started Jul 24 06:01:09 PM PDT 24
Finished Jul 24 06:01:11 PM PDT 24
Peak memory 218736 kb
Host smart-0584a193-d1ff-4a12-8631-30394d1b585d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962041858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1962041858
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1378186444
Short name T713
Test name
Test status
Simulation time 20939169 ps
CPU time 1.06 seconds
Started Jul 24 06:00:54 PM PDT 24
Finished Jul 24 06:00:55 PM PDT 24
Peak memory 218824 kb
Host smart-2aab7c06-1e37-494d-996b-363dc9c534a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378186444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1378186444
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1661903636
Short name T677
Test name
Test status
Simulation time 52547650 ps
CPU time 1.15 seconds
Started Jul 24 06:01:12 PM PDT 24
Finished Jul 24 06:01:13 PM PDT 24
Peak memory 217544 kb
Host smart-d7873e0e-cafe-4342-bb74-c0f575859c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661903636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1661903636
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.800962936
Short name T134
Test name
Test status
Simulation time 57034911 ps
CPU time 1.33 seconds
Started Jul 24 06:00:51 PM PDT 24
Finished Jul 24 06:00:53 PM PDT 24
Peak memory 216060 kb
Host smart-a005dbce-fdc8-4c74-bfeb-65ef02a7e65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800962936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.800962936
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.181356129
Short name T35
Test name
Test status
Simulation time 18352273 ps
CPU time 1.03 seconds
Started Jul 24 06:01:04 PM PDT 24
Finished Jul 24 06:01:06 PM PDT 24
Peak memory 218868 kb
Host smart-efdfbbfc-806d-4a92-8a05-d46a4cf35b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181356129 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.181356129
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3803900874
Short name T878
Test name
Test status
Simulation time 45303496 ps
CPU time 1.49 seconds
Started Jul 24 06:01:10 PM PDT 24
Finished Jul 24 06:01:11 PM PDT 24
Peak memory 217500 kb
Host smart-08e1304c-95e8-4bdf-bfc6-6d95069211fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803900874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3803900874
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.890751223
Short name T75
Test name
Test status
Simulation time 30160600 ps
CPU time 1.35 seconds
Started Jul 24 06:00:56 PM PDT 24
Finished Jul 24 06:00:58 PM PDT 24
Peak memory 220036 kb
Host smart-908193b5-2018-4e37-8dab-f9f70c2e0ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890751223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.890751223
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.1629547769
Short name T596
Test name
Test status
Simulation time 25547472 ps
CPU time 1.2 seconds
Started Jul 24 06:00:56 PM PDT 24
Finished Jul 24 06:00:57 PM PDT 24
Peak memory 221044 kb
Host smart-27b99d05-15c1-4d3f-beec-40e0caf4be65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629547769 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1629547769
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1616430768
Short name T498
Test name
Test status
Simulation time 93517662 ps
CPU time 1.76 seconds
Started Jul 24 06:00:53 PM PDT 24
Finished Jul 24 06:00:55 PM PDT 24
Peak memory 218908 kb
Host smart-36d82fb7-5543-47c0-a167-c52a94e526fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616430768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1616430768
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.2067338118
Short name T117
Test name
Test status
Simulation time 26190488 ps
CPU time 1.25 seconds
Started Jul 24 06:01:07 PM PDT 24
Finished Jul 24 06:01:09 PM PDT 24
Peak memory 219040 kb
Host smart-101892f8-9fe0-4a57-a262-a3fdae643081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067338118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.2067338118
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.4200800910
Short name T204
Test name
Test status
Simulation time 66048000 ps
CPU time 1.04 seconds
Started Jul 24 06:00:52 PM PDT 24
Finished Jul 24 06:00:53 PM PDT 24
Peak memory 220188 kb
Host smart-a1e52390-36e7-4137-adb0-e0821e2ced7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200800910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4200800910
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.664416623
Short name T66
Test name
Test status
Simulation time 60865150 ps
CPU time 1.22 seconds
Started Jul 24 06:01:10 PM PDT 24
Finished Jul 24 06:01:12 PM PDT 24
Peak memory 218652 kb
Host smart-3f9f2d92-3836-4ea9-9601-2d4eac41453c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664416623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.664416623
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.3583661660
Short name T643
Test name
Test status
Simulation time 22573869 ps
CPU time 1.16 seconds
Started Jul 24 06:01:04 PM PDT 24
Finished Jul 24 06:01:05 PM PDT 24
Peak memory 219088 kb
Host smart-23833988-6a31-449d-9b31-3a547055e425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583661660 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.3583661660
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.501927004
Short name T192
Test name
Test status
Simulation time 23723874 ps
CPU time 1.06 seconds
Started Jul 24 06:01:05 PM PDT 24
Finished Jul 24 06:01:06 PM PDT 24
Peak memory 229784 kb
Host smart-3b9120da-e831-47f9-907d-daee51f529a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501927004 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.501927004
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1365272636
Short name T562
Test name
Test status
Simulation time 72402581 ps
CPU time 1.16 seconds
Started Jul 24 06:00:55 PM PDT 24
Finished Jul 24 06:00:56 PM PDT 24
Peak memory 217552 kb
Host smart-86e98c54-9013-4603-b6d6-4d1ebc5e6f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365272636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1365272636
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.4284144076
Short name T666
Test name
Test status
Simulation time 44185624 ps
CPU time 1.22 seconds
Started Jul 24 06:00:57 PM PDT 24
Finished Jul 24 06:00:58 PM PDT 24
Peak memory 219980 kb
Host smart-419b4dbe-1f27-4715-b144-c9a944ee7dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284144076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.4284144076
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.3213498087
Short name T971
Test name
Test status
Simulation time 29001250 ps
CPU time 0.89 seconds
Started Jul 24 06:00:56 PM PDT 24
Finished Jul 24 06:00:57 PM PDT 24
Peak memory 218692 kb
Host smart-5b5f4bbe-5372-4160-85c4-e256030e4553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213498087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3213498087
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3728613429
Short name T334
Test name
Test status
Simulation time 49627573 ps
CPU time 1.21 seconds
Started Jul 24 06:00:54 PM PDT 24
Finished Jul 24 06:00:56 PM PDT 24
Peak memory 220296 kb
Host smart-79bc1295-b568-49ff-9974-617d04844387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728613429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3728613429
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.858686186
Short name T289
Test name
Test status
Simulation time 30066438 ps
CPU time 1.31 seconds
Started Jul 24 06:01:20 PM PDT 24
Finished Jul 24 06:01:21 PM PDT 24
Peak memory 220068 kb
Host smart-c9f0aed9-8174-4a40-883e-3834b3c7ae37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858686186 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.858686186
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.540320323
Short name T203
Test name
Test status
Simulation time 19672295 ps
CPU time 1.08 seconds
Started Jul 24 06:00:59 PM PDT 24
Finished Jul 24 06:01:00 PM PDT 24
Peak memory 218928 kb
Host smart-89abf92d-82e5-4907-8876-c03889256c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540320323 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.540320323
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1899889304
Short name T385
Test name
Test status
Simulation time 77980456 ps
CPU time 1.36 seconds
Started Jul 24 06:01:00 PM PDT 24
Finished Jul 24 06:01:01 PM PDT 24
Peak memory 219048 kb
Host smart-c10a91cd-b673-4126-8fca-5064d011ef5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899889304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1899889304
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.1963867893
Short name T807
Test name
Test status
Simulation time 61481886 ps
CPU time 1.11 seconds
Started Jul 24 06:01:10 PM PDT 24
Finished Jul 24 06:01:11 PM PDT 24
Peak memory 219168 kb
Host smart-74517105-0764-472e-9f17-556610598fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963867893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.1963867893
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.568851369
Short name T834
Test name
Test status
Simulation time 27846409 ps
CPU time 1.2 seconds
Started Jul 24 06:01:10 PM PDT 24
Finished Jul 24 06:01:12 PM PDT 24
Peak memory 224264 kb
Host smart-500c2800-f2f0-45c7-88a0-6f4d89f4e656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568851369 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.568851369
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.1226623541
Short name T633
Test name
Test status
Simulation time 27550441 ps
CPU time 1.23 seconds
Started Jul 24 06:00:06 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 219056 kb
Host smart-c5eac9cd-57ee-4afd-b9ed-9c028c9b465e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226623541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1226623541
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2958825167
Short name T371
Test name
Test status
Simulation time 16802563 ps
CPU time 1.08 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:02 PM PDT 24
Peak memory 215432 kb
Host smart-920fdc24-2e4e-4eb2-95fb-ebcba8e25479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958825167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2958825167
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2842419201
Short name T748
Test name
Test status
Simulation time 120416931 ps
CPU time 1.26 seconds
Started Jul 24 06:00:03 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 218124 kb
Host smart-baf051be-18e1-4229-a09c-483f13c587a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842419201 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2842419201
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3446820797
Short name T831
Test name
Test status
Simulation time 25185293 ps
CPU time 1.17 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:02 PM PDT 24
Peak memory 224076 kb
Host smart-d7e43133-ffcf-44b2-ba03-c27881bbd66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446820797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3446820797
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.315018359
Short name T526
Test name
Test status
Simulation time 48981541 ps
CPU time 1.24 seconds
Started Jul 24 06:00:04 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 220156 kb
Host smart-5e72a453-fa94-4639-b4e9-567501bed27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315018359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.315018359
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2907816940
Short name T14
Test name
Test status
Simulation time 21562200 ps
CPU time 1.26 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:02 PM PDT 24
Peak memory 224284 kb
Host smart-dc074b1c-bfaf-4f1e-8534-d98d62b194fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907816940 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2907816940
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1936321568
Short name T781
Test name
Test status
Simulation time 17386270 ps
CPU time 0.99 seconds
Started Jul 24 06:00:03 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 207356 kb
Host smart-2ea6fa44-7518-4c5f-9492-4cde8425d535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936321568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1936321568
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1021132562
Short name T425
Test name
Test status
Simulation time 38272946 ps
CPU time 0.94 seconds
Started Jul 24 06:00:04 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215488 kb
Host smart-71544de4-c98a-42cf-96b3-8130cd0692e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021132562 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1021132562
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4107438266
Short name T561
Test name
Test status
Simulation time 196565286 ps
CPU time 4.03 seconds
Started Jul 24 06:00:08 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 215604 kb
Host smart-85cd9b20-ad96-4334-bfee-a5a6d20ee8db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107438266 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4107438266
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2198158682
Short name T358
Test name
Test status
Simulation time 96526869311 ps
CPU time 1107.17 seconds
Started Jul 24 06:00:01 PM PDT 24
Finished Jul 24 06:18:29 PM PDT 24
Peak memory 223668 kb
Host smart-cd1b3edd-3a7c-4c31-b27f-8eb6a5e4dc1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198158682 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2198158682
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.2782077726
Short name T790
Test name
Test status
Simulation time 25833281 ps
CPU time 1.3 seconds
Started Jul 24 06:01:14 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 220656 kb
Host smart-e64fb8f2-574d-4562-99c7-586ab4fbc241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782077726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2782077726
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.224077839
Short name T482
Test name
Test status
Simulation time 28258971 ps
CPU time 0.86 seconds
Started Jul 24 06:01:12 PM PDT 24
Finished Jul 24 06:01:14 PM PDT 24
Peak memory 218568 kb
Host smart-97421168-b9f7-4c96-a49d-cab0e5b9a5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224077839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.224077839
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1943444929
Short name T724
Test name
Test status
Simulation time 94388671 ps
CPU time 1.1 seconds
Started Jul 24 06:01:10 PM PDT 24
Finished Jul 24 06:01:12 PM PDT 24
Peak memory 219020 kb
Host smart-c09e29b0-d81e-4c82-8e43-63da7beaeb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943444929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1943444929
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.1992349092
Short name T217
Test name
Test status
Simulation time 54274534 ps
CPU time 1.15 seconds
Started Jul 24 06:01:07 PM PDT 24
Finished Jul 24 06:01:09 PM PDT 24
Peak memory 220760 kb
Host smart-4c9943e5-d323-41b9-9955-b2ddc79e0001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992349092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.1992349092
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.670183107
Short name T109
Test name
Test status
Simulation time 35292531 ps
CPU time 0.98 seconds
Started Jul 24 06:00:56 PM PDT 24
Finished Jul 24 06:00:57 PM PDT 24
Peak memory 219880 kb
Host smart-45e73f63-4eda-4f8e-9fe2-e4a87b82d06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670183107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.670183107
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.700721243
Short name T509
Test name
Test status
Simulation time 107506014 ps
CPU time 1.42 seconds
Started Jul 24 06:01:01 PM PDT 24
Finished Jul 24 06:01:02 PM PDT 24
Peak memory 219284 kb
Host smart-2059e23e-b7d8-41b0-b6a4-203efb2c8574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700721243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.700721243
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.2201435481
Short name T634
Test name
Test status
Simulation time 65535043 ps
CPU time 1.06 seconds
Started Jul 24 06:00:54 PM PDT 24
Finished Jul 24 06:00:55 PM PDT 24
Peak memory 220744 kb
Host smart-b92d2d47-9d9d-4a42-9688-98478bc7dff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201435481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.2201435481
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3926454179
Short name T844
Test name
Test status
Simulation time 34643016 ps
CPU time 1.1 seconds
Started Jul 24 06:01:13 PM PDT 24
Finished Jul 24 06:01:14 PM PDT 24
Peak memory 221164 kb
Host smart-e35e3591-f560-4318-bb9d-3bd045ce093d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926454179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3926454179
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2043738160
Short name T559
Test name
Test status
Simulation time 103829177 ps
CPU time 1.63 seconds
Started Jul 24 06:01:09 PM PDT 24
Finished Jul 24 06:01:11 PM PDT 24
Peak memory 217588 kb
Host smart-c1d0e70e-464f-4736-aacf-873130f808fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043738160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2043738160
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.243400752
Short name T167
Test name
Test status
Simulation time 58347591 ps
CPU time 1.28 seconds
Started Jul 24 06:01:15 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 216068 kb
Host smart-00ea3bb9-149a-4611-87b4-3751874c57f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243400752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.243400752
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1133262607
Short name T874
Test name
Test status
Simulation time 31218905 ps
CPU time 0.88 seconds
Started Jul 24 06:01:03 PM PDT 24
Finished Jul 24 06:01:04 PM PDT 24
Peak memory 218688 kb
Host smart-1015511a-8980-49ca-abdb-298a97d8f338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133262607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1133262607
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3661592097
Short name T392
Test name
Test status
Simulation time 75461838 ps
CPU time 1.43 seconds
Started Jul 24 06:00:56 PM PDT 24
Finished Jul 24 06:00:58 PM PDT 24
Peak memory 217628 kb
Host smart-e53377e3-ef8e-455c-9c4d-120650ab9d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661592097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3661592097
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.1098144520
Short name T92
Test name
Test status
Simulation time 236956081 ps
CPU time 1.14 seconds
Started Jul 24 06:00:57 PM PDT 24
Finished Jul 24 06:00:58 PM PDT 24
Peak memory 218608 kb
Host smart-bea0508a-2437-4b23-9b27-3dea62598edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098144520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.1098144520
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3727163194
Short name T164
Test name
Test status
Simulation time 23186150 ps
CPU time 0.96 seconds
Started Jul 24 06:01:09 PM PDT 24
Finished Jul 24 06:01:10 PM PDT 24
Peak memory 218816 kb
Host smart-97e63b21-0788-4fc8-9d52-48a2ca65a451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727163194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3727163194
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1602218147
Short name T693
Test name
Test status
Simulation time 87340171 ps
CPU time 0.98 seconds
Started Jul 24 06:01:05 PM PDT 24
Finished Jul 24 06:01:06 PM PDT 24
Peak memory 217588 kb
Host smart-0b035d5a-ba50-4cf9-8bd0-6da7cfd9f27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602218147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1602218147
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.1735302150
Short name T574
Test name
Test status
Simulation time 212989940 ps
CPU time 1.2 seconds
Started Jul 24 06:01:12 PM PDT 24
Finished Jul 24 06:01:14 PM PDT 24
Peak memory 219916 kb
Host smart-d0fe21fa-371d-4c17-98b6-f86cbd30fd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735302150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1735302150
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.2506607429
Short name T771
Test name
Test status
Simulation time 25789273 ps
CPU time 0.99 seconds
Started Jul 24 06:00:57 PM PDT 24
Finished Jul 24 06:00:58 PM PDT 24
Peak memory 219956 kb
Host smart-579e69a3-71eb-4d16-94ae-1e9d3e3191de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506607429 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2506607429
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2753857063
Short name T993
Test name
Test status
Simulation time 70172362 ps
CPU time 1.75 seconds
Started Jul 24 06:01:13 PM PDT 24
Finished Jul 24 06:01:15 PM PDT 24
Peak memory 219400 kb
Host smart-f0fafb22-15e4-42ae-ab59-573ee61f5cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753857063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2753857063
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.2319698089
Short name T851
Test name
Test status
Simulation time 29276947 ps
CPU time 1.24 seconds
Started Jul 24 06:00:56 PM PDT 24
Finished Jul 24 06:00:58 PM PDT 24
Peak memory 218860 kb
Host smart-07575cd3-a872-4dd3-bb2f-e91ea52a602b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319698089 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.2319698089
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.2560756598
Short name T127
Test name
Test status
Simulation time 40612669 ps
CPU time 0.93 seconds
Started Jul 24 06:00:56 PM PDT 24
Finished Jul 24 06:00:57 PM PDT 24
Peak memory 218768 kb
Host smart-bf6858e1-4a13-4ec6-b9eb-bb5af7539d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560756598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2560756598
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1928152867
Short name T773
Test name
Test status
Simulation time 50827911 ps
CPU time 1.8 seconds
Started Jul 24 06:01:09 PM PDT 24
Finished Jul 24 06:01:11 PM PDT 24
Peak memory 218788 kb
Host smart-4e9e6e56-4003-4b51-949f-7b31243607ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928152867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1928152867
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.646700766
Short name T435
Test name
Test status
Simulation time 42185565 ps
CPU time 1.11 seconds
Started Jul 24 06:01:02 PM PDT 24
Finished Jul 24 06:01:04 PM PDT 24
Peak memory 220140 kb
Host smart-01eb1c9a-873e-4c9c-bf09-3674b471ad39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646700766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.646700766
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.1926303007
Short name T153
Test name
Test status
Simulation time 27431527 ps
CPU time 0.84 seconds
Started Jul 24 06:01:04 PM PDT 24
Finished Jul 24 06:01:05 PM PDT 24
Peak memory 218500 kb
Host smart-66c2225b-b05e-4f5c-9a76-f336f0fb8518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926303007 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1926303007
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.379891883
Short name T241
Test name
Test status
Simulation time 46254279 ps
CPU time 1.52 seconds
Started Jul 24 06:00:57 PM PDT 24
Finished Jul 24 06:00:59 PM PDT 24
Peak memory 219084 kb
Host smart-c2ce8480-acfb-4c12-a6fb-a7f587560688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379891883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.379891883
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.101128804
Short name T419
Test name
Test status
Simulation time 24537557 ps
CPU time 1.21 seconds
Started Jul 24 06:01:11 PM PDT 24
Finished Jul 24 06:01:13 PM PDT 24
Peak memory 218856 kb
Host smart-8f712f8c-3de5-4f33-9342-067ef0465abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101128804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.101128804
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.1489261455
Short name T445
Test name
Test status
Simulation time 18144540 ps
CPU time 1.05 seconds
Started Jul 24 06:01:10 PM PDT 24
Finished Jul 24 06:01:11 PM PDT 24
Peak memory 218944 kb
Host smart-5937f10b-e396-4ae1-b5ba-04cf205dab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489261455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1489261455
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2230106190
Short name T25
Test name
Test status
Simulation time 130835635 ps
CPU time 1.52 seconds
Started Jul 24 06:01:00 PM PDT 24
Finished Jul 24 06:01:02 PM PDT 24
Peak memory 217592 kb
Host smart-aa58d736-254a-400c-a3f9-9e5515edc9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230106190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2230106190
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.2207624397
Short name T940
Test name
Test status
Simulation time 70113760 ps
CPU time 1.13 seconds
Started Jul 24 06:01:18 PM PDT 24
Finished Jul 24 06:01:19 PM PDT 24
Peak memory 220100 kb
Host smart-56531a8b-47d4-4866-825c-28a9a64403a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207624397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2207624397
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.3801163777
Short name T128
Test name
Test status
Simulation time 19111454 ps
CPU time 1.12 seconds
Started Jul 24 06:01:12 PM PDT 24
Finished Jul 24 06:01:13 PM PDT 24
Peak memory 218792 kb
Host smart-fb927702-1e20-4bab-9ce1-91e10fbe61a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801163777 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3801163777
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.69300549
Short name T536
Test name
Test status
Simulation time 64538476 ps
CPU time 1.01 seconds
Started Jul 24 06:01:17 PM PDT 24
Finished Jul 24 06:01:19 PM PDT 24
Peak memory 217560 kb
Host smart-8dd96e69-c9c9-42b7-bcf7-89340010cb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69300549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.69300549
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2887148324
Short name T136
Test name
Test status
Simulation time 46535895 ps
CPU time 1.22 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:02 PM PDT 24
Peak memory 219852 kb
Host smart-f9303860-566a-4f73-859c-8c84a46e425a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887148324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2887148324
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.587391686
Short name T955
Test name
Test status
Simulation time 20594629 ps
CPU time 0.93 seconds
Started Jul 24 06:00:01 PM PDT 24
Finished Jul 24 06:00:02 PM PDT 24
Peak memory 206816 kb
Host smart-ab6f6d97-209a-4b78-a8fd-c0f5e2729dd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587391686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.587391686
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.242488137
Short name T202
Test name
Test status
Simulation time 50914217 ps
CPU time 0.79 seconds
Started Jul 24 06:00:04 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 216948 kb
Host smart-7c1e00ec-8d59-42ca-add1-e0e2ba8ab6cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242488137 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.242488137
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.948016614
Short name T539
Test name
Test status
Simulation time 38008402 ps
CPU time 1.29 seconds
Started Jul 24 06:00:04 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 217324 kb
Host smart-d43d7c4f-6830-453c-a3de-6aed3b57e7f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948016614 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.948016614
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.355375743
Short name T494
Test name
Test status
Simulation time 27496755 ps
CPU time 1.1 seconds
Started Jul 24 06:00:03 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 218396 kb
Host smart-5d577db1-6d9c-4b4f-8d68-5409dd134ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355375743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.355375743
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1154356935
Short name T607
Test name
Test status
Simulation time 137224689 ps
CPU time 2.82 seconds
Started Jul 24 06:00:04 PM PDT 24
Finished Jul 24 06:00:13 PM PDT 24
Peak memory 219268 kb
Host smart-47ab8841-281a-4282-8f3a-7d38216c6390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154356935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1154356935
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.201916295
Short name T749
Test name
Test status
Simulation time 34514779 ps
CPU time 0.91 seconds
Started Jul 24 06:00:01 PM PDT 24
Finished Jul 24 06:00:09 PM PDT 24
Peak memory 215820 kb
Host smart-08583e97-30c6-46f6-a506-35617ffa81bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201916295 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.201916295
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.918977290
Short name T30
Test name
Test status
Simulation time 18274031 ps
CPU time 1 seconds
Started Jul 24 06:00:05 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 207392 kb
Host smart-7d3e7d2d-a51d-4040-b992-3a9bc7fb6a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918977290 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.918977290
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.4221576172
Short name T461
Test name
Test status
Simulation time 17439099 ps
CPU time 1.08 seconds
Started Jul 24 06:00:03 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215564 kb
Host smart-fc740376-8105-4de8-90df-3a0adbb0680a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221576172 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.4221576172
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2341046822
Short name T26
Test name
Test status
Simulation time 2170383556 ps
CPU time 3.59 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:04 PM PDT 24
Peak memory 215832 kb
Host smart-573cf103-5ad1-48d4-be93-b62a60da70c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341046822 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2341046822
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1682217942
Short name T641
Test name
Test status
Simulation time 23522623741 ps
CPU time 533.65 seconds
Started Jul 24 05:59:59 PM PDT 24
Finished Jul 24 06:08:53 PM PDT 24
Peak memory 224152 kb
Host smart-c3998de8-942a-4664-9717-f7a462c29409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682217942 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1682217942
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.4286614582
Short name T860
Test name
Test status
Simulation time 80028912 ps
CPU time 1.17 seconds
Started Jul 24 06:01:15 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 218988 kb
Host smart-2875600e-1190-4a4c-a29a-5f3c4d75c6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286614582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.4286614582
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.3758569196
Short name T746
Test name
Test status
Simulation time 25174213 ps
CPU time 1.17 seconds
Started Jul 24 06:01:18 PM PDT 24
Finished Jul 24 06:01:19 PM PDT 24
Peak memory 221044 kb
Host smart-7d92af7a-9cc3-4fb1-8264-f5fc369e2834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758569196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3758569196
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.617831047
Short name T852
Test name
Test status
Simulation time 79739065 ps
CPU time 1.19 seconds
Started Jul 24 06:01:14 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 219328 kb
Host smart-f05c8075-83a3-43ab-85ff-f0e8d52afd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617831047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.617831047
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.3597142067
Short name T815
Test name
Test status
Simulation time 71157571 ps
CPU time 1.06 seconds
Started Jul 24 06:01:11 PM PDT 24
Finished Jul 24 06:01:12 PM PDT 24
Peak memory 218832 kb
Host smart-39487605-c1aa-4b26-81bd-1e4bda365203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597142067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.3597142067
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.3654403503
Short name T869
Test name
Test status
Simulation time 20722238 ps
CPU time 1.04 seconds
Started Jul 24 06:01:16 PM PDT 24
Finished Jul 24 06:01:17 PM PDT 24
Peak memory 219800 kb
Host smart-55070b23-6083-4963-9151-9255a14efa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654403503 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3654403503
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.4252454785
Short name T479
Test name
Test status
Simulation time 48194473 ps
CPU time 1.28 seconds
Started Jul 24 06:01:17 PM PDT 24
Finished Jul 24 06:01:19 PM PDT 24
Peak memory 217752 kb
Host smart-da2b9db3-a0f8-4ebd-90ad-bcd97a5f86b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252454785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.4252454785
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.246784686
Short name T126
Test name
Test status
Simulation time 29135489 ps
CPU time 1.4 seconds
Started Jul 24 06:01:14 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 221120 kb
Host smart-1c19e742-07aa-47b9-8c4a-129c0067dfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246784686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.246784686
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.186300673
Short name T197
Test name
Test status
Simulation time 32560726 ps
CPU time 1.26 seconds
Started Jul 24 06:01:09 PM PDT 24
Finished Jul 24 06:01:11 PM PDT 24
Peak memory 220004 kb
Host smart-8518a7fb-86e5-4a1b-a336-95f82f5a571b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186300673 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.186300673
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1194132931
Short name T797
Test name
Test status
Simulation time 45931657 ps
CPU time 1.46 seconds
Started Jul 24 06:01:17 PM PDT 24
Finished Jul 24 06:01:18 PM PDT 24
Peak memory 217884 kb
Host smart-c8aa56d6-3bbc-4dce-86c6-b4d72ca22e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194132931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1194132931
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1951210284
Short name T886
Test name
Test status
Simulation time 42903553 ps
CPU time 1.13 seconds
Started Jul 24 06:01:04 PM PDT 24
Finished Jul 24 06:01:05 PM PDT 24
Peak memory 216068 kb
Host smart-0d278dbb-ce4f-4176-b388-5edc48167b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951210284 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1951210284
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.725549896
Short name T962
Test name
Test status
Simulation time 18269562 ps
CPU time 1.07 seconds
Started Jul 24 06:01:15 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 215892 kb
Host smart-ae3523b2-8dfd-404d-8c5c-c75c755f65b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725549896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.725549896
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3955300250
Short name T11
Test name
Test status
Simulation time 142590560 ps
CPU time 1.47 seconds
Started Jul 24 06:01:18 PM PDT 24
Finished Jul 24 06:01:20 PM PDT 24
Peak memory 220268 kb
Host smart-f629ebb1-0af3-4ea6-9890-02bd5626e08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955300250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3955300250
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.1667478166
Short name T171
Test name
Test status
Simulation time 26505726 ps
CPU time 1.26 seconds
Started Jul 24 06:01:12 PM PDT 24
Finished Jul 24 06:01:13 PM PDT 24
Peak memory 220116 kb
Host smart-f79efcf2-dced-4f25-9acb-bec4fbf315f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667478166 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1667478166
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3511419570
Short name T675
Test name
Test status
Simulation time 33064241 ps
CPU time 0.93 seconds
Started Jul 24 06:01:11 PM PDT 24
Finished Jul 24 06:01:12 PM PDT 24
Peak memory 218792 kb
Host smart-ba93d3da-e9c2-4470-8ff2-02c8c4fe5813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511419570 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3511419570
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2593433056
Short name T764
Test name
Test status
Simulation time 47235475 ps
CPU time 1.3 seconds
Started Jul 24 06:01:14 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 217576 kb
Host smart-071c21e7-768b-4bca-b708-222bd9cf2b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593433056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2593433056
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.2501783473
Short name T926
Test name
Test status
Simulation time 83174793 ps
CPU time 1.32 seconds
Started Jul 24 06:01:10 PM PDT 24
Finished Jul 24 06:01:12 PM PDT 24
Peak memory 216072 kb
Host smart-ae25385e-1bd8-474f-bc3c-4ae2a19f2d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501783473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2501783473
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1768905281
Short name T846
Test name
Test status
Simulation time 31527136 ps
CPU time 0.9 seconds
Started Jul 24 06:01:08 PM PDT 24
Finished Jul 24 06:01:09 PM PDT 24
Peak memory 218760 kb
Host smart-b2bcb3c9-9526-45f5-ace9-1af04e205058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768905281 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1768905281
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1751605057
Short name T79
Test name
Test status
Simulation time 85272356 ps
CPU time 1.32 seconds
Started Jul 24 06:01:09 PM PDT 24
Finished Jul 24 06:01:11 PM PDT 24
Peak memory 220100 kb
Host smart-1bb20b6a-5a18-40a4-9680-0c87a2162ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751605057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1751605057
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2967892533
Short name T107
Test name
Test status
Simulation time 61302093 ps
CPU time 1.18 seconds
Started Jul 24 06:01:04 PM PDT 24
Finished Jul 24 06:01:05 PM PDT 24
Peak memory 220312 kb
Host smart-71bcbf66-85c6-413c-9578-291625137d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967892533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2967892533
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.3522442945
Short name T7
Test name
Test status
Simulation time 34327654 ps
CPU time 1.05 seconds
Started Jul 24 06:01:08 PM PDT 24
Finished Jul 24 06:01:09 PM PDT 24
Peak memory 220212 kb
Host smart-d97cd592-b2b5-40cb-b693-6267a2fa9adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522442945 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3522442945
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3325893004
Short name T946
Test name
Test status
Simulation time 46272819 ps
CPU time 1.55 seconds
Started Jul 24 06:01:10 PM PDT 24
Finished Jul 24 06:01:12 PM PDT 24
Peak memory 218788 kb
Host smart-348395de-4cc5-4067-8bd4-c9d0aa5c32f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325893004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3325893004
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.4121087906
Short name T818
Test name
Test status
Simulation time 29836722 ps
CPU time 1.3 seconds
Started Jul 24 06:01:08 PM PDT 24
Finished Jul 24 06:01:10 PM PDT 24
Peak memory 219880 kb
Host smart-14c3d3ab-4353-4134-a838-e0a5c35ed210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121087906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.4121087906
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.1453196040
Short name T72
Test name
Test status
Simulation time 25489374 ps
CPU time 1 seconds
Started Jul 24 06:01:15 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 218860 kb
Host smart-40236c6a-0863-43d0-99b0-4965a121fc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453196040 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1453196040
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3335508405
Short name T514
Test name
Test status
Simulation time 80678409 ps
CPU time 1.17 seconds
Started Jul 24 06:01:11 PM PDT 24
Finished Jul 24 06:01:13 PM PDT 24
Peak memory 217672 kb
Host smart-3910a657-2e70-4b64-832c-75dce0ec8a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335508405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3335508405
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3684632196
Short name T213
Test name
Test status
Simulation time 24475423 ps
CPU time 1.24 seconds
Started Jul 24 06:01:18 PM PDT 24
Finished Jul 24 06:01:19 PM PDT 24
Peak memory 221172 kb
Host smart-288982fb-7e85-4f2c-8b8e-5bd1077abdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684632196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3684632196
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.4067790506
Short name T480
Test name
Test status
Simulation time 33561393 ps
CPU time 0.87 seconds
Started Jul 24 06:01:12 PM PDT 24
Finished Jul 24 06:01:13 PM PDT 24
Peak memory 218588 kb
Host smart-70a4f043-ebd0-43e2-919f-54bcb2f8d003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067790506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.4067790506
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.351684710
Short name T951
Test name
Test status
Simulation time 139057837 ps
CPU time 1.46 seconds
Started Jul 24 06:01:22 PM PDT 24
Finished Jul 24 06:01:23 PM PDT 24
Peak memory 217696 kb
Host smart-3eb01d3e-d31a-496f-a4f1-b968180ebc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351684710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.351684710
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2006938801
Short name T247
Test name
Test status
Simulation time 29277724 ps
CPU time 1.3 seconds
Started Jul 24 06:01:12 PM PDT 24
Finished Jul 24 06:01:14 PM PDT 24
Peak memory 220788 kb
Host smart-70082485-f6dc-4a9c-b3c3-12fe67cd1fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006938801 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2006938801
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.1279593710
Short name T469
Test name
Test status
Simulation time 45121780 ps
CPU time 0.88 seconds
Started Jul 24 06:01:18 PM PDT 24
Finished Jul 24 06:01:19 PM PDT 24
Peak memory 219760 kb
Host smart-f99f6528-453b-44f9-83ea-b7e8ef52d458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279593710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1279593710
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1152164538
Short name T709
Test name
Test status
Simulation time 56829149 ps
CPU time 1.39 seconds
Started Jul 24 06:01:17 PM PDT 24
Finished Jul 24 06:01:19 PM PDT 24
Peak memory 217820 kb
Host smart-9a9b678e-0225-4817-ab96-72bbdfee67d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152164538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1152164538
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1005920868
Short name T274
Test name
Test status
Simulation time 104176925 ps
CPU time 1.08 seconds
Started Jul 24 06:00:02 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 218712 kb
Host smart-e4d714e3-0453-4f93-9835-75ff5bc68c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005920868 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1005920868
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.4200440910
Short name T70
Test name
Test status
Simulation time 12366433 ps
CPU time 0.89 seconds
Started Jul 24 06:00:03 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 207196 kb
Host smart-3f68a650-4dfb-4e2d-a06f-e9e92ed1171a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200440910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.4200440910
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.985990208
Short name T489
Test name
Test status
Simulation time 34742167 ps
CPU time 1.2 seconds
Started Jul 24 06:00:04 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 218684 kb
Host smart-4eb19512-1f97-49b0-89f4-9ef1bf82f778
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985990208 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.985990208
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_genbits.2631786569
Short name T363
Test name
Test status
Simulation time 97580664 ps
CPU time 1.33 seconds
Started Jul 24 06:00:08 PM PDT 24
Finished Jul 24 06:00:12 PM PDT 24
Peak memory 218828 kb
Host smart-0ef11ab1-9186-4f50-bbc0-7cc55f3c3455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631786569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2631786569
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.645746932
Short name T619
Test name
Test status
Simulation time 20527158 ps
CPU time 1.23 seconds
Started Jul 24 06:00:01 PM PDT 24
Finished Jul 24 06:00:10 PM PDT 24
Peak memory 224316 kb
Host smart-14851159-623f-4f92-8843-cb52571a8923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645746932 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.645746932
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1182731826
Short name T692
Test name
Test status
Simulation time 15940382 ps
CPU time 0.95 seconds
Started Jul 24 06:00:00 PM PDT 24
Finished Jul 24 06:00:02 PM PDT 24
Peak memory 207432 kb
Host smart-e2c12dab-08f7-4d4a-be10-e3be133dbadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182731826 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1182731826
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1342960229
Short name T495
Test name
Test status
Simulation time 18992358 ps
CPU time 0.96 seconds
Started Jul 24 06:00:05 PM PDT 24
Finished Jul 24 06:00:11 PM PDT 24
Peak memory 215772 kb
Host smart-6d65748d-8774-4f85-a8bb-f190c730042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342960229 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1342960229
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2823272370
Short name T608
Test name
Test status
Simulation time 224108638 ps
CPU time 4.7 seconds
Started Jul 24 06:00:05 PM PDT 24
Finished Jul 24 06:00:14 PM PDT 24
Peak memory 217548 kb
Host smart-8bfeb605-66c7-445a-acd7-4d3d1769bc3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823272370 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2823272370
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1246942554
Short name T547
Test name
Test status
Simulation time 632697298222 ps
CPU time 1092.79 seconds
Started Jul 24 06:00:02 PM PDT 24
Finished Jul 24 06:18:23 PM PDT 24
Peak memory 224048 kb
Host smart-4a5e1f6d-aea5-4281-820e-63a13095683f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246942554 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1246942554
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.3376098283
Short name T885
Test name
Test status
Simulation time 25028986 ps
CPU time 1.21 seconds
Started Jul 24 06:01:13 PM PDT 24
Finished Jul 24 06:01:15 PM PDT 24
Peak memory 221136 kb
Host smart-14f795e3-1431-4bfd-b077-efc211ba7191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376098283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.3376098283
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.4256914199
Short name T67
Test name
Test status
Simulation time 24726500 ps
CPU time 0.99 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 218556 kb
Host smart-53e5222f-f457-4866-af5f-db274ab35f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256914199 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.4256914199
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1402587237
Short name T534
Test name
Test status
Simulation time 51358792 ps
CPU time 1.25 seconds
Started Jul 24 06:01:17 PM PDT 24
Finished Jul 24 06:01:18 PM PDT 24
Peak memory 219556 kb
Host smart-c2492ea7-14af-47e8-a630-d1dca8defefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402587237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1402587237
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.849725152
Short name T421
Test name
Test status
Simulation time 69509739 ps
CPU time 1.11 seconds
Started Jul 24 06:01:23 PM PDT 24
Finished Jul 24 06:01:24 PM PDT 24
Peak memory 219220 kb
Host smart-7dacfa65-4124-4cc0-9e32-8c0e24000c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849725152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.849725152
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.4005624137
Short name T590
Test name
Test status
Simulation time 37265547 ps
CPU time 1.08 seconds
Started Jul 24 06:01:10 PM PDT 24
Finished Jul 24 06:01:11 PM PDT 24
Peak memory 221028 kb
Host smart-7d159962-48de-4a05-b6c5-be920b5a8d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005624137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.4005624137
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2341297465
Short name T439
Test name
Test status
Simulation time 40231158 ps
CPU time 1.5 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 217564 kb
Host smart-3aa5c616-0d34-47e4-8525-6eb9706d86a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341297465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2341297465
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.2670368099
Short name T52
Test name
Test status
Simulation time 17999841 ps
CPU time 1.16 seconds
Started Jul 24 06:01:07 PM PDT 24
Finished Jul 24 06:01:08 PM PDT 24
Peak memory 233104 kb
Host smart-17983e3b-ed41-43ad-98b1-80098c0860c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670368099 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2670368099
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3741760008
Short name T680
Test name
Test status
Simulation time 55206207 ps
CPU time 1.13 seconds
Started Jul 24 06:01:11 PM PDT 24
Finished Jul 24 06:01:13 PM PDT 24
Peak memory 217608 kb
Host smart-3a034d81-4225-40db-b418-4e7a33eb453a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741760008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3741760008
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.767482888
Short name T369
Test name
Test status
Simulation time 29595192 ps
CPU time 1.32 seconds
Started Jul 24 06:01:23 PM PDT 24
Finished Jul 24 06:01:25 PM PDT 24
Peak memory 219532 kb
Host smart-d60538ad-26d1-4640-a4f1-f329c4faca82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767482888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.767482888
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.986412007
Short name T980
Test name
Test status
Simulation time 32583908 ps
CPU time 1.02 seconds
Started Jul 24 06:01:16 PM PDT 24
Finished Jul 24 06:01:17 PM PDT 24
Peak memory 220244 kb
Host smart-ff12594b-6088-4d7d-9861-bf891b6edf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986412007 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.986412007
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2177638059
Short name T388
Test name
Test status
Simulation time 45818111 ps
CPU time 1.6 seconds
Started Jul 24 06:01:13 PM PDT 24
Finished Jul 24 06:01:15 PM PDT 24
Peak memory 218824 kb
Host smart-7bdf5e9b-5bfc-4415-9dbf-c5cb5260b9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177638059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2177638059
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.3285278521
Short name T760
Test name
Test status
Simulation time 178285278 ps
CPU time 1.34 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 219984 kb
Host smart-79925fad-a70b-41b2-9d50-f08303b1d17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285278521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.3285278521
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1980966473
Short name T569
Test name
Test status
Simulation time 19098610 ps
CPU time 1.02 seconds
Started Jul 24 06:01:25 PM PDT 24
Finished Jul 24 06:01:26 PM PDT 24
Peak memory 218328 kb
Host smart-c8043be2-baf7-4856-926b-e20928088622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980966473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1980966473
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.947169670
Short name T355
Test name
Test status
Simulation time 108731260 ps
CPU time 1.05 seconds
Started Jul 24 06:01:09 PM PDT 24
Finished Jul 24 06:01:10 PM PDT 24
Peak memory 217568 kb
Host smart-f33c8847-9fce-4511-af85-c68c8085147c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947169670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.947169670
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.2757558755
Short name T245
Test name
Test status
Simulation time 112357487 ps
CPU time 1.24 seconds
Started Jul 24 06:01:13 PM PDT 24
Finished Jul 24 06:01:15 PM PDT 24
Peak memory 220104 kb
Host smart-17017b80-02ce-4fac-afee-dc30b7d4a3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757558755 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.2757558755
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.2927148253
Short name T147
Test name
Test status
Simulation time 18247737 ps
CPU time 1.12 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 218840 kb
Host smart-735d33a2-cd24-4a30-af56-1937f269c0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927148253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2927148253
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1208582098
Short name T46
Test name
Test status
Simulation time 71292758 ps
CPU time 1.14 seconds
Started Jul 24 06:01:17 PM PDT 24
Finished Jul 24 06:01:18 PM PDT 24
Peak memory 220304 kb
Host smart-b38e671e-8787-4bcb-bed0-2c7d7f8273c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208582098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1208582098
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.3261029527
Short name T361
Test name
Test status
Simulation time 91842328 ps
CPU time 1.24 seconds
Started Jul 24 06:01:19 PM PDT 24
Finished Jul 24 06:01:21 PM PDT 24
Peak memory 219944 kb
Host smart-8e5e863b-6ef7-4985-9413-50fc07727f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261029527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.3261029527
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1244904532
Short name T958
Test name
Test status
Simulation time 21199596 ps
CPU time 0.96 seconds
Started Jul 24 06:01:11 PM PDT 24
Finished Jul 24 06:01:13 PM PDT 24
Peak memory 218932 kb
Host smart-a4638d04-1a48-4855-942a-988aaf0280a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244904532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1244904532
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3522382736
Short name T899
Test name
Test status
Simulation time 91647297 ps
CPU time 1.16 seconds
Started Jul 24 06:01:12 PM PDT 24
Finished Jul 24 06:01:13 PM PDT 24
Peak memory 220508 kb
Host smart-5d7df14d-7cd8-4e00-a7df-c1c5c15a872c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522382736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3522382736
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.1840158298
Short name T936
Test name
Test status
Simulation time 39627002 ps
CPU time 1.27 seconds
Started Jul 24 06:01:14 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 220164 kb
Host smart-39b16ede-295e-4744-9386-b4567917bb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840158298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.1840158298
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.3647965373
Short name T703
Test name
Test status
Simulation time 134521754 ps
CPU time 1.09 seconds
Started Jul 24 06:01:24 PM PDT 24
Finished Jul 24 06:01:25 PM PDT 24
Peak memory 224304 kb
Host smart-6f48418a-cdf2-4547-9a84-61ce3ec5f3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647965373 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3647965373
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2680713522
Short name T463
Test name
Test status
Simulation time 67246052 ps
CPU time 1.18 seconds
Started Jul 24 06:01:15 PM PDT 24
Finished Jul 24 06:01:16 PM PDT 24
Peak memory 217580 kb
Host smart-f7bf1253-c972-4a34-89f2-85229ae38ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680713522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2680713522
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.3674864648
Short name T73
Test name
Test status
Simulation time 80555469 ps
CPU time 1.1 seconds
Started Jul 24 06:01:26 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 219868 kb
Host smart-28f7d0ed-7e17-4c63-85fd-1725537482f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674864648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.3674864648
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.2066508360
Short name T893
Test name
Test status
Simulation time 28141833 ps
CPU time 0.86 seconds
Started Jul 24 06:01:13 PM PDT 24
Finished Jul 24 06:01:14 PM PDT 24
Peak memory 218536 kb
Host smart-96aeb7b6-fd04-4cc0-861a-c4f6c57b4a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066508360 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2066508360
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3270026323
Short name T699
Test name
Test status
Simulation time 53593187 ps
CPU time 1.33 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:29 PM PDT 24
Peak memory 218936 kb
Host smart-5f08df1b-6ef0-40ab-8ab4-cd3a27632286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270026323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3270026323
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.1781849202
Short name T177
Test name
Test status
Simulation time 26167894 ps
CPU time 1.23 seconds
Started Jul 24 06:01:23 PM PDT 24
Finished Jul 24 06:01:24 PM PDT 24
Peak memory 219120 kb
Host smart-9d7b3425-996d-48a5-b7f7-04df6598a3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781849202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1781849202
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2414427947
Short name T523
Test name
Test status
Simulation time 56054422 ps
CPU time 0.84 seconds
Started Jul 24 06:01:27 PM PDT 24
Finished Jul 24 06:01:28 PM PDT 24
Peak memory 218640 kb
Host smart-f2f3ce3a-92dc-4433-ae00-9b4652e47148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414427947 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2414427947
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2624358348
Short name T822
Test name
Test status
Simulation time 44798189 ps
CPU time 1.45 seconds
Started Jul 24 06:01:13 PM PDT 24
Finished Jul 24 06:01:14 PM PDT 24
Peak memory 218792 kb
Host smart-884e5436-7f8d-4084-8891-587b06558a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624358348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2624358348
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%