Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.32 98.25 93.25 91.10 86.63 95.50 96.83 91.70


Total test records in report: 1125
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T253 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1266229641 Jul 25 05:58:55 PM PDT 24 Jul 25 05:58:56 PM PDT 24 31573615 ps
T1013 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1705926869 Jul 25 05:58:40 PM PDT 24 Jul 25 05:58:43 PM PDT 24 173362649 ps
T1014 /workspace/coverage/cover_reg_top/20.edn_intr_test.1730484393 Jul 25 05:58:59 PM PDT 24 Jul 25 05:59:00 PM PDT 24 24118293 ps
T254 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3957003967 Jul 25 05:58:49 PM PDT 24 Jul 25 05:58:50 PM PDT 24 100172086 ps
T255 /workspace/coverage/cover_reg_top/7.edn_csr_rw.676218194 Jul 25 05:58:54 PM PDT 24 Jul 25 05:58:55 PM PDT 24 34292915 ps
T245 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2977349095 Jul 25 05:58:41 PM PDT 24 Jul 25 05:58:42 PM PDT 24 72318831 ps
T1015 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2926730955 Jul 25 05:59:03 PM PDT 24 Jul 25 05:59:04 PM PDT 24 67373822 ps
T269 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.704170964 Jul 25 05:58:42 PM PDT 24 Jul 25 05:58:45 PM PDT 24 97612636 ps
T1016 /workspace/coverage/cover_reg_top/39.edn_intr_test.3739241044 Jul 25 05:59:14 PM PDT 24 Jul 25 05:59:15 PM PDT 24 32656160 ps
T1017 /workspace/coverage/cover_reg_top/22.edn_intr_test.614976889 Jul 25 05:59:00 PM PDT 24 Jul 25 05:59:01 PM PDT 24 17162911 ps
T1018 /workspace/coverage/cover_reg_top/1.edn_intr_test.3910827106 Jul 25 05:58:39 PM PDT 24 Jul 25 05:58:40 PM PDT 24 56001307 ps
T1019 /workspace/coverage/cover_reg_top/44.edn_intr_test.3161265825 Jul 25 05:59:14 PM PDT 24 Jul 25 05:59:15 PM PDT 24 13648263 ps
T1020 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1014925997 Jul 25 05:58:52 PM PDT 24 Jul 25 05:58:55 PM PDT 24 1060416323 ps
T1021 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3987882516 Jul 25 05:58:52 PM PDT 24 Jul 25 05:58:56 PM PDT 24 525751698 ps
T1022 /workspace/coverage/cover_reg_top/18.edn_intr_test.2363610569 Jul 25 05:58:58 PM PDT 24 Jul 25 05:58:58 PM PDT 24 124969931 ps
T1023 /workspace/coverage/cover_reg_top/3.edn_intr_test.1171118040 Jul 25 05:58:42 PM PDT 24 Jul 25 05:58:43 PM PDT 24 14346703 ps
T256 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.861296733 Jul 25 05:58:59 PM PDT 24 Jul 25 05:59:00 PM PDT 24 57758253 ps
T1024 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.829139234 Jul 25 05:58:43 PM PDT 24 Jul 25 05:58:44 PM PDT 24 50992331 ps
T1025 /workspace/coverage/cover_reg_top/0.edn_intr_test.559873831 Jul 25 05:58:40 PM PDT 24 Jul 25 05:58:41 PM PDT 24 43678870 ps
T1026 /workspace/coverage/cover_reg_top/48.edn_intr_test.2452400862 Jul 25 05:59:14 PM PDT 24 Jul 25 05:59:15 PM PDT 24 56147575 ps
T1027 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2820734780 Jul 25 05:58:39 PM PDT 24 Jul 25 05:58:40 PM PDT 24 17316912 ps
T1028 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.799360879 Jul 25 05:58:52 PM PDT 24 Jul 25 05:58:54 PM PDT 24 168160034 ps
T1029 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3145304697 Jul 25 05:59:02 PM PDT 24 Jul 25 05:59:03 PM PDT 24 71968147 ps
T1030 /workspace/coverage/cover_reg_top/47.edn_intr_test.40518735 Jul 25 05:59:14 PM PDT 24 Jul 25 05:59:15 PM PDT 24 45568431 ps
T1031 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3673394868 Jul 25 05:58:39 PM PDT 24 Jul 25 05:58:41 PM PDT 24 118578474 ps
T1032 /workspace/coverage/cover_reg_top/24.edn_intr_test.3007664042 Jul 25 05:59:02 PM PDT 24 Jul 25 05:59:03 PM PDT 24 51808499 ps
T1033 /workspace/coverage/cover_reg_top/36.edn_intr_test.2310059232 Jul 25 05:59:01 PM PDT 24 Jul 25 05:59:02 PM PDT 24 21571120 ps
T1034 /workspace/coverage/cover_reg_top/19.edn_intr_test.3898334610 Jul 25 05:58:59 PM PDT 24 Jul 25 05:59:00 PM PDT 24 25724247 ps
T1035 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2240765142 Jul 25 05:58:47 PM PDT 24 Jul 25 05:58:49 PM PDT 24 36958949 ps
T1036 /workspace/coverage/cover_reg_top/18.edn_tl_errors.4269824581 Jul 25 05:59:00 PM PDT 24 Jul 25 05:59:03 PM PDT 24 175657644 ps
T1037 /workspace/coverage/cover_reg_top/26.edn_intr_test.2427402343 Jul 25 05:59:00 PM PDT 24 Jul 25 05:59:01 PM PDT 24 11662644 ps
T1038 /workspace/coverage/cover_reg_top/11.edn_intr_test.384991782 Jul 25 05:58:49 PM PDT 24 Jul 25 05:58:50 PM PDT 24 14956058 ps
T1039 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4242433591 Jul 25 05:58:46 PM PDT 24 Jul 25 05:58:47 PM PDT 24 49623050 ps
T1040 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3609822415 Jul 25 05:58:51 PM PDT 24 Jul 25 05:58:52 PM PDT 24 40737948 ps
T1041 /workspace/coverage/cover_reg_top/15.edn_tl_errors.113474909 Jul 25 05:58:59 PM PDT 24 Jul 25 05:59:02 PM PDT 24 412903233 ps
T1042 /workspace/coverage/cover_reg_top/34.edn_intr_test.2197712294 Jul 25 05:59:07 PM PDT 24 Jul 25 05:59:08 PM PDT 24 24392540 ps
T270 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1037381753 Jul 25 05:59:03 PM PDT 24 Jul 25 05:59:05 PM PDT 24 132243799 ps
T1043 /workspace/coverage/cover_reg_top/17.edn_intr_test.2389662786 Jul 25 05:59:00 PM PDT 24 Jul 25 05:59:01 PM PDT 24 14821774 ps
T1044 /workspace/coverage/cover_reg_top/2.edn_intr_test.2972722763 Jul 25 05:58:40 PM PDT 24 Jul 25 05:58:41 PM PDT 24 15018658 ps
T1045 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3798009424 Jul 25 05:59:08 PM PDT 24 Jul 25 05:59:10 PM PDT 24 222726588 ps
T1046 /workspace/coverage/cover_reg_top/33.edn_intr_test.527240750 Jul 25 05:59:02 PM PDT 24 Jul 25 05:59:03 PM PDT 24 11408288 ps
T1047 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3262082550 Jul 25 05:58:49 PM PDT 24 Jul 25 05:58:50 PM PDT 24 80613324 ps
T1048 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3256731270 Jul 25 05:58:45 PM PDT 24 Jul 25 05:58:46 PM PDT 24 75577104 ps
T1049 /workspace/coverage/cover_reg_top/12.edn_tl_errors.449071507 Jul 25 05:58:57 PM PDT 24 Jul 25 05:58:59 PM PDT 24 27116909 ps
T1050 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2463440877 Jul 25 05:58:52 PM PDT 24 Jul 25 05:58:53 PM PDT 24 86815140 ps
T1051 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.747293000 Jul 25 05:59:02 PM PDT 24 Jul 25 05:59:04 PM PDT 24 96442935 ps
T1052 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4039005678 Jul 25 05:58:45 PM PDT 24 Jul 25 05:58:48 PM PDT 24 195117853 ps
T1053 /workspace/coverage/cover_reg_top/23.edn_intr_test.722476593 Jul 25 05:59:07 PM PDT 24 Jul 25 05:59:08 PM PDT 24 23637419 ps
T1054 /workspace/coverage/cover_reg_top/18.edn_csr_rw.712004364 Jul 25 05:59:03 PM PDT 24 Jul 25 05:59:04 PM PDT 24 27032752 ps
T271 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2747539668 Jul 25 05:58:37 PM PDT 24 Jul 25 05:58:39 PM PDT 24 50196748 ps
T1055 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3136702544 Jul 25 05:58:43 PM PDT 24 Jul 25 05:58:47 PM PDT 24 349970171 ps
T1056 /workspace/coverage/cover_reg_top/14.edn_intr_test.934303247 Jul 25 05:58:56 PM PDT 24 Jul 25 05:58:57 PM PDT 24 32200216 ps
T246 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1338187582 Jul 25 05:58:57 PM PDT 24 Jul 25 05:58:58 PM PDT 24 18674694 ps
T1057 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.263899488 Jul 25 05:58:43 PM PDT 24 Jul 25 05:58:44 PM PDT 24 32112715 ps
T1058 /workspace/coverage/cover_reg_top/8.edn_intr_test.2934211994 Jul 25 05:58:58 PM PDT 24 Jul 25 05:58:59 PM PDT 24 15327811 ps
T1059 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2434572681 Jul 25 05:59:07 PM PDT 24 Jul 25 05:59:08 PM PDT 24 61986623 ps
T1060 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1487630079 Jul 25 05:58:42 PM PDT 24 Jul 25 05:58:43 PM PDT 24 48685981 ps
T1061 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1486266177 Jul 25 05:58:57 PM PDT 24 Jul 25 05:58:59 PM PDT 24 83126641 ps
T1062 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3724320355 Jul 25 05:58:50 PM PDT 24 Jul 25 05:58:51 PM PDT 24 24850990 ps
T1063 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.296876770 Jul 25 05:58:42 PM PDT 24 Jul 25 05:58:46 PM PDT 24 368483183 ps
T1064 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.56947700 Jul 25 05:58:56 PM PDT 24 Jul 25 05:58:57 PM PDT 24 56445439 ps
T1065 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3693957398 Jul 25 05:59:01 PM PDT 24 Jul 25 05:59:02 PM PDT 24 111233684 ps
T1066 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2409262480 Jul 25 05:58:52 PM PDT 24 Jul 25 05:58:54 PM PDT 24 97172801 ps
T1067 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.354356461 Jul 25 05:58:52 PM PDT 24 Jul 25 05:58:54 PM PDT 24 174296671 ps
T1068 /workspace/coverage/cover_reg_top/5.edn_intr_test.2940305612 Jul 25 05:58:42 PM PDT 24 Jul 25 05:58:44 PM PDT 24 11071481 ps
T1069 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1610848459 Jul 25 05:58:39 PM PDT 24 Jul 25 05:58:43 PM PDT 24 83280719 ps
T1070 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3002625196 Jul 25 05:58:50 PM PDT 24 Jul 25 05:58:54 PM PDT 24 170391324 ps
T1071 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2524113453 Jul 25 05:58:43 PM PDT 24 Jul 25 05:58:47 PM PDT 24 1792837234 ps
T1072 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2441261197 Jul 25 05:59:00 PM PDT 24 Jul 25 05:59:01 PM PDT 24 79262012 ps
T1073 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1310191259 Jul 25 05:58:52 PM PDT 24 Jul 25 05:58:55 PM PDT 24 183896349 ps
T1074 /workspace/coverage/cover_reg_top/7.edn_intr_test.2728726756 Jul 25 05:58:48 PM PDT 24 Jul 25 05:58:49 PM PDT 24 56000898 ps
T1075 /workspace/coverage/cover_reg_top/4.edn_intr_test.1772354016 Jul 25 05:58:43 PM PDT 24 Jul 25 05:58:45 PM PDT 24 48479065 ps
T1076 /workspace/coverage/cover_reg_top/35.edn_intr_test.729719179 Jul 25 05:59:01 PM PDT 24 Jul 25 05:59:02 PM PDT 24 24666260 ps
T247 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2352268789 Jul 25 05:58:42 PM PDT 24 Jul 25 05:58:44 PM PDT 24 17523692 ps
T1077 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2293073344 Jul 25 05:58:52 PM PDT 24 Jul 25 05:58:54 PM PDT 24 28265866 ps
T1078 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3132886835 Jul 25 05:58:51 PM PDT 24 Jul 25 05:58:52 PM PDT 24 42004376 ps
T1079 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.579396459 Jul 25 05:58:56 PM PDT 24 Jul 25 05:58:57 PM PDT 24 32132037 ps
T1080 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1814793201 Jul 25 05:58:55 PM PDT 24 Jul 25 05:58:57 PM PDT 24 40156243 ps
T1081 /workspace/coverage/cover_reg_top/43.edn_intr_test.275505032 Jul 25 05:59:31 PM PDT 24 Jul 25 05:59:32 PM PDT 24 36464115 ps
T1082 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2451238217 Jul 25 05:58:50 PM PDT 24 Jul 25 05:58:52 PM PDT 24 115662873 ps
T1083 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3422022137 Jul 25 05:58:45 PM PDT 24 Jul 25 05:58:46 PM PDT 24 161489812 ps
T1084 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3948346767 Jul 25 05:58:51 PM PDT 24 Jul 25 05:58:52 PM PDT 24 39845192 ps
T1085 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2605937620 Jul 25 05:58:51 PM PDT 24 Jul 25 05:58:52 PM PDT 24 240698877 ps
T1086 /workspace/coverage/cover_reg_top/10.edn_intr_test.3893172956 Jul 25 05:58:52 PM PDT 24 Jul 25 05:58:53 PM PDT 24 32391446 ps
T1087 /workspace/coverage/cover_reg_top/45.edn_intr_test.1097896563 Jul 25 05:59:14 PM PDT 24 Jul 25 05:59:15 PM PDT 24 32930799 ps
T1088 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1295440287 Jul 25 05:59:02 PM PDT 24 Jul 25 05:59:04 PM PDT 24 66303394 ps
T1089 /workspace/coverage/cover_reg_top/31.edn_intr_test.2328551551 Jul 25 05:59:01 PM PDT 24 Jul 25 05:59:02 PM PDT 24 11923279 ps
T1090 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.901419840 Jul 25 05:58:42 PM PDT 24 Jul 25 05:58:44 PM PDT 24 145543061 ps
T1091 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3378685998 Jul 25 05:58:50 PM PDT 24 Jul 25 05:58:52 PM PDT 24 72966110 ps
T1092 /workspace/coverage/cover_reg_top/14.edn_tl_errors.422554196 Jul 25 05:58:55 PM PDT 24 Jul 25 05:58:57 PM PDT 24 100059209 ps
T1093 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.4266277280 Jul 25 05:58:42 PM PDT 24 Jul 25 05:58:45 PM PDT 24 37190793 ps
T1094 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1383450004 Jul 25 05:58:45 PM PDT 24 Jul 25 05:58:47 PM PDT 24 111975883 ps
T1095 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1181643361 Jul 25 05:58:42 PM PDT 24 Jul 25 05:58:44 PM PDT 24 21968378 ps
T1096 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1658186037 Jul 25 05:58:51 PM PDT 24 Jul 25 05:58:52 PM PDT 24 141823708 ps
T1097 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3442371731 Jul 25 05:58:50 PM PDT 24 Jul 25 05:58:52 PM PDT 24 59357196 ps
T1098 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2015033789 Jul 25 05:59:03 PM PDT 24 Jul 25 05:59:04 PM PDT 24 14871219 ps
T1099 /workspace/coverage/cover_reg_top/29.edn_intr_test.2243760501 Jul 25 05:59:07 PM PDT 24 Jul 25 05:59:08 PM PDT 24 33703557 ps
T1100 /workspace/coverage/cover_reg_top/8.edn_csr_rw.116753622 Jul 25 05:58:51 PM PDT 24 Jul 25 05:58:52 PM PDT 24 20601713 ps
T1101 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2952109308 Jul 25 05:58:55 PM PDT 24 Jul 25 05:58:56 PM PDT 24 36696089 ps
T1102 /workspace/coverage/cover_reg_top/38.edn_intr_test.1829741677 Jul 25 05:59:02 PM PDT 24 Jul 25 05:59:03 PM PDT 24 39149410 ps
T248 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3140126057 Jul 25 05:58:43 PM PDT 24 Jul 25 05:58:50 PM PDT 24 1786582525 ps
T1103 /workspace/coverage/cover_reg_top/19.edn_tl_errors.72844113 Jul 25 05:58:59 PM PDT 24 Jul 25 05:59:05 PM PDT 24 530912773 ps
T1104 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2986933743 Jul 25 05:58:43 PM PDT 24 Jul 25 05:58:46 PM PDT 24 343547065 ps
T1105 /workspace/coverage/cover_reg_top/21.edn_intr_test.3591549467 Jul 25 05:59:02 PM PDT 24 Jul 25 05:59:03 PM PDT 24 19976431 ps
T1106 /workspace/coverage/cover_reg_top/30.edn_intr_test.3076613301 Jul 25 05:59:01 PM PDT 24 Jul 25 05:59:02 PM PDT 24 40625252 ps
T1107 /workspace/coverage/cover_reg_top/16.edn_intr_test.1236554635 Jul 25 05:59:00 PM PDT 24 Jul 25 05:59:01 PM PDT 24 13174182 ps
T1108 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1771182020 Jul 25 05:58:42 PM PDT 24 Jul 25 05:58:43 PM PDT 24 36880976 ps
T1109 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1823204323 Jul 25 05:58:43 PM PDT 24 Jul 25 05:58:45 PM PDT 24 25780130 ps
T1110 /workspace/coverage/cover_reg_top/13.edn_intr_test.414712174 Jul 25 05:58:50 PM PDT 24 Jul 25 05:58:51 PM PDT 24 41231852 ps
T1111 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.768732058 Jul 25 05:58:43 PM PDT 24 Jul 25 05:58:44 PM PDT 24 57390810 ps
T1112 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3887089159 Jul 25 05:58:52 PM PDT 24 Jul 25 05:58:54 PM PDT 24 27954573 ps
T1113 /workspace/coverage/cover_reg_top/32.edn_intr_test.3413798861 Jul 25 05:59:02 PM PDT 24 Jul 25 05:59:03 PM PDT 24 24134176 ps
T1114 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1009057588 Jul 25 05:58:41 PM PDT 24 Jul 25 05:58:43 PM PDT 24 24587359 ps
T1115 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.104958318 Jul 25 05:58:43 PM PDT 24 Jul 25 05:58:44 PM PDT 24 63376472 ps
T1116 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2194656075 Jul 25 05:58:50 PM PDT 24 Jul 25 05:58:51 PM PDT 24 232988640 ps
T1117 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2270038955 Jul 25 05:58:39 PM PDT 24 Jul 25 05:58:40 PM PDT 24 189048182 ps
T1118 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.748524163 Jul 25 05:58:56 PM PDT 24 Jul 25 05:58:58 PM PDT 24 21044067 ps
T1119 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2912730646 Jul 25 05:58:55 PM PDT 24 Jul 25 05:58:56 PM PDT 24 21880101 ps
T1120 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1457757903 Jul 25 05:58:53 PM PDT 24 Jul 25 05:58:56 PM PDT 24 154672652 ps
T249 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3583455704 Jul 25 05:58:42 PM PDT 24 Jul 25 05:58:43 PM PDT 24 46423549 ps
T1121 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1500544386 Jul 25 05:58:52 PM PDT 24 Jul 25 05:58:53 PM PDT 24 23777359 ps
T1122 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1285722294 Jul 25 05:58:41 PM PDT 24 Jul 25 05:58:42 PM PDT 24 13288651 ps
T1123 /workspace/coverage/cover_reg_top/3.edn_tl_errors.768565387 Jul 25 05:58:43 PM PDT 24 Jul 25 05:58:48 PM PDT 24 216708723 ps
T1124 /workspace/coverage/cover_reg_top/2.edn_tl_errors.207650128 Jul 25 05:58:42 PM PDT 24 Jul 25 05:58:45 PM PDT 24 86366966 ps
T1125 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2356375204 Jul 25 05:59:00 PM PDT 24 Jul 25 05:59:03 PM PDT 24 225463195 ps

Test location /workspace/coverage/default/237.edn_genbits.1355376998
Short name T16
Test name
Test status
Simulation time 57961374 ps
CPU time 1.26 seconds
Started Jul 25 06:06:32 PM PDT 24
Finished Jul 25 06:06:34 PM PDT 24
Peak memory 219852 kb
Host smart-86ff2c40-94bc-4b45-bdde-0c7db35b2f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355376998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1355376998
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2009084859
Short name T4
Test name
Test status
Simulation time 25663680206 ps
CPU time 561.85 seconds
Started Jul 25 06:04:45 PM PDT 24
Finished Jul 25 06:14:07 PM PDT 24
Peak memory 218612 kb
Host smart-4f32704d-8690-4924-87a5-ef0773db9f2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009084859 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2009084859
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.250706327
Short name T2
Test name
Test status
Simulation time 23457961 ps
CPU time 1.25 seconds
Started Jul 25 06:04:53 PM PDT 24
Finished Jul 25 06:04:54 PM PDT 24
Peak memory 219116 kb
Host smart-28c255af-9e38-4c8c-9ae4-139aa0818dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250706327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.250706327
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/221.edn_genbits.3090580203
Short name T38
Test name
Test status
Simulation time 56803385 ps
CPU time 1.42 seconds
Started Jul 25 06:06:18 PM PDT 24
Finished Jul 25 06:06:20 PM PDT 24
Peak memory 218328 kb
Host smart-2ef7375b-ec6c-41c0-bba4-462dc4baaf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090580203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3090580203
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2568740067
Short name T14
Test name
Test status
Simulation time 29477432 ps
CPU time 0.96 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 223692 kb
Host smart-4b8ccc8d-47cd-468b-b7bc-5a19802c8c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568740067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2568740067
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1098183594
Short name T17
Test name
Test status
Simulation time 40510038 ps
CPU time 1.4 seconds
Started Jul 25 06:03:58 PM PDT 24
Finished Jul 25 06:04:00 PM PDT 24
Peak memory 216784 kb
Host smart-73021dd5-65d7-4aaa-930a-53c443882dbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098183594 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1098183594
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_stress_all.4015501799
Short name T108
Test name
Test status
Simulation time 512808893 ps
CPU time 5.07 seconds
Started Jul 25 06:04:18 PM PDT 24
Finished Jul 25 06:04:23 PM PDT 24
Peak memory 217304 kb
Host smart-68e2e108-e8c0-4d1c-ba6e-8973503c3f05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015501799 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.4015501799
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/56.edn_err.251088627
Short name T7
Test name
Test status
Simulation time 37315120 ps
CPU time 1.01 seconds
Started Jul 25 06:05:23 PM PDT 24
Finished Jul 25 06:05:24 PM PDT 24
Peak memory 224036 kb
Host smart-76b640aa-05db-4bd9-8346-bd619df8cab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251088627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.251088627
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/197.edn_alert.498239556
Short name T22
Test name
Test status
Simulation time 27671988 ps
CPU time 1.23 seconds
Started Jul 25 06:06:18 PM PDT 24
Finished Jul 25 06:06:19 PM PDT 24
Peak memory 219688 kb
Host smart-066ddcc9-d947-4692-94e3-98d324363b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498239556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.498239556
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert.320703667
Short name T65
Test name
Test status
Simulation time 94817892 ps
CPU time 1.16 seconds
Started Jul 25 06:03:55 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 218612 kb
Host smart-e6f069a7-b7fa-43b3-8106-9f165b701dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320703667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.320703667
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/1.edn_regwen.1552385508
Short name T77
Test name
Test status
Simulation time 16968423 ps
CPU time 1.03 seconds
Started Jul 25 06:03:42 PM PDT 24
Finished Jul 25 06:03:44 PM PDT 24
Peak memory 206968 kb
Host smart-1f24c442-89d1-4e92-9588-c9bdd6a4b375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552385508 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1552385508
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2601558962
Short name T93
Test name
Test status
Simulation time 46909156397 ps
CPU time 992.04 seconds
Started Jul 25 06:04:40 PM PDT 24
Finished Jul 25 06:21:12 PM PDT 24
Peak memory 223608 kb
Host smart-2b4cfd0a-b042-4d16-ae29-b1475c6c99b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601558962 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2601558962
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.edn_intr.1376610001
Short name T82
Test name
Test status
Simulation time 34905373 ps
CPU time 0.85 seconds
Started Jul 25 06:04:46 PM PDT 24
Finished Jul 25 06:04:47 PM PDT 24
Peak memory 215540 kb
Host smart-4c7d1167-9648-4138-840e-d3ec75f9a6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376610001 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1376610001
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/186.edn_alert.283218778
Short name T69
Test name
Test status
Simulation time 76117470 ps
CPU time 1.16 seconds
Started Jul 25 06:06:16 PM PDT 24
Finished Jul 25 06:06:17 PM PDT 24
Peak memory 219996 kb
Host smart-8e93f91e-00e9-4114-9b0c-cbd8b55875f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283218778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.283218778
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.499264514
Short name T215
Test name
Test status
Simulation time 174431208 ps
CPU time 2.34 seconds
Started Jul 25 05:58:51 PM PDT 24
Finished Jul 25 05:58:54 PM PDT 24
Peak memory 206844 kb
Host smart-82d088d9-ea0b-4a8a-90f8-3125524989d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499264514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.499264514
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/184.edn_alert.2978844412
Short name T170
Test name
Test status
Simulation time 61555182 ps
CPU time 1.33 seconds
Started Jul 25 06:06:12 PM PDT 24
Finished Jul 25 06:06:14 PM PDT 24
Peak memory 215544 kb
Host smart-8ff6fe47-181a-40ba-8e82-48aac8f472dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978844412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2978844412
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3759251180
Short name T240
Test name
Test status
Simulation time 16869469 ps
CPU time 0.84 seconds
Started Jul 25 05:58:56 PM PDT 24
Finished Jul 25 05:58:57 PM PDT 24
Peak memory 206188 kb
Host smart-2e6c142d-9791-4f36-8276-cba8d5b93cbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759251180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3759251180
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3632262210
Short name T68
Test name
Test status
Simulation time 81954762 ps
CPU time 1.09 seconds
Started Jul 25 06:04:46 PM PDT 24
Finished Jul 25 06:04:47 PM PDT 24
Peak memory 216832 kb
Host smart-973c2b80-c17d-4b29-b0f7-f46e8ebb9b57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632262210 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3632262210
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_intr.1078911908
Short name T59
Test name
Test status
Simulation time 33422809 ps
CPU time 0.93 seconds
Started Jul 25 06:04:52 PM PDT 24
Finished Jul 25 06:04:53 PM PDT 24
Peak memory 215588 kb
Host smart-4e81848b-96ab-44e4-ae30-0decd64418cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078911908 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1078911908
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/48.edn_genbits.2753279679
Short name T10
Test name
Test status
Simulation time 246495974 ps
CPU time 3.26 seconds
Started Jul 25 06:05:16 PM PDT 24
Finished Jul 25 06:05:19 PM PDT 24
Peak memory 219932 kb
Host smart-972f1b7a-fcaf-4218-b0ba-947b75c59f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753279679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2753279679
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.3051163954
Short name T73
Test name
Test status
Simulation time 23421076 ps
CPU time 1.22 seconds
Started Jul 25 06:05:33 PM PDT 24
Finished Jul 25 06:05:35 PM PDT 24
Peak memory 218636 kb
Host smart-85e948d2-7f51-40cc-acb3-44e1438077be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051163954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3051163954
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.2919267970
Short name T129
Test name
Test status
Simulation time 23359766 ps
CPU time 0.89 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:12 PM PDT 24
Peak memory 216044 kb
Host smart-0b1ba23c-3499-4c77-bad1-c1c924a3a2c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919267970 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2919267970
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable.3561768218
Short name T106
Test name
Test status
Simulation time 61245684 ps
CPU time 0.85 seconds
Started Jul 25 06:04:41 PM PDT 24
Finished Jul 25 06:04:42 PM PDT 24
Peak memory 216164 kb
Host smart-576c894b-fc97-4b7a-9291-13131e6f793c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561768218 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3561768218
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable.1451054290
Short name T128
Test name
Test status
Simulation time 62552808 ps
CPU time 0.82 seconds
Started Jul 25 06:03:54 PM PDT 24
Finished Jul 25 06:03:55 PM PDT 24
Peak memory 216088 kb
Host smart-b5141d47-72d9-4879-8331-371c667caff2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451054290 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1451054290
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable.3755161922
Short name T125
Test name
Test status
Simulation time 98399334 ps
CPU time 0.84 seconds
Started Jul 25 06:05:18 PM PDT 24
Finished Jul 25 06:05:19 PM PDT 24
Peak memory 216220 kb
Host smart-26301a63-39da-481b-b6c1-4506dfd79b42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755161922 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3755161922
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/169.edn_alert.1771736678
Short name T263
Test name
Test status
Simulation time 33182242 ps
CPU time 1.29 seconds
Started Jul 25 06:06:25 PM PDT 24
Finished Jul 25 06:06:26 PM PDT 24
Peak memory 215476 kb
Host smart-a12efaf2-a000-4b86-b945-5c38a96ab02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771736678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1771736678
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/183.edn_alert.460564316
Short name T158
Test name
Test status
Simulation time 26720900 ps
CPU time 1.26 seconds
Started Jul 25 06:06:16 PM PDT 24
Finished Jul 25 06:06:17 PM PDT 24
Peak memory 220420 kb
Host smart-76d37395-0021-4da4-bdd9-ec11b3651910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460564316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.460564316
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/20.edn_disable.3010343092
Short name T174
Test name
Test status
Simulation time 16488800 ps
CPU time 0.84 seconds
Started Jul 25 06:04:24 PM PDT 24
Finished Jul 25 06:04:25 PM PDT 24
Peak memory 215244 kb
Host smart-f5af9e83-fe66-4cf7-b002-809194f50e6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010343092 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3010343092
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/70.edn_alert.1869059374
Short name T196
Test name
Test status
Simulation time 49924629 ps
CPU time 1.23 seconds
Started Jul 25 06:05:31 PM PDT 24
Finished Jul 25 06:05:33 PM PDT 24
Peak memory 215564 kb
Host smart-83c67838-c999-4934-a7cc-a1632e072951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869059374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1869059374
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/65.edn_alert.3076489246
Short name T21
Test name
Test status
Simulation time 248398951 ps
CPU time 1.21 seconds
Started Jul 25 06:05:33 PM PDT 24
Finished Jul 25 06:05:35 PM PDT 24
Peak memory 218360 kb
Host smart-a6362331-fbea-47ae-99c4-142963a561c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076489246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3076489246
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/37.edn_err.1554444666
Short name T58
Test name
Test status
Simulation time 43227797 ps
CPU time 0.93 seconds
Started Jul 25 06:04:56 PM PDT 24
Finished Jul 25 06:04:57 PM PDT 24
Peak memory 219376 kb
Host smart-3b2fd11e-76f8-44db-ac23-a9640a2d50cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554444666 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1554444666
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/100.edn_alert.1032031324
Short name T165
Test name
Test status
Simulation time 42429670 ps
CPU time 1.23 seconds
Started Jul 25 06:05:46 PM PDT 24
Finished Jul 25 06:05:48 PM PDT 24
Peak memory 219252 kb
Host smart-1c1f5a37-56c8-4f85-9627-fbb3b430dcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032031324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.1032031324
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/59.edn_alert.2798321505
Short name T231
Test name
Test status
Simulation time 29156510 ps
CPU time 1.27 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:27 PM PDT 24
Peak memory 215576 kb
Host smart-c4cb5b7a-74e4-4dd9-a2cb-80c64860f78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798321505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2798321505
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.180406365
Short name T168
Test name
Test status
Simulation time 46028033 ps
CPU time 1.08 seconds
Started Jul 25 06:04:41 PM PDT 24
Finished Jul 25 06:04:42 PM PDT 24
Peak memory 216740 kb
Host smart-4f4fc004-cba5-4fe0-8493-3bcc8c539495
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180406365 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.180406365
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/72.edn_alert.1007544142
Short name T201
Test name
Test status
Simulation time 29241140 ps
CPU time 1.31 seconds
Started Jul 25 06:05:32 PM PDT 24
Finished Jul 25 06:05:33 PM PDT 24
Peak memory 220700 kb
Host smart-95f00b16-504b-4411-b15e-6c4676340963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007544142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1007544142
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/8.edn_genbits.2998568969
Short name T75
Test name
Test status
Simulation time 35238349 ps
CPU time 1.36 seconds
Started Jul 25 06:04:00 PM PDT 24
Finished Jul 25 06:04:02 PM PDT 24
Peak memory 219804 kb
Host smart-b990c1b9-bed4-4617-a50b-6dfa3bdcdc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998568969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2998568969
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_disable.2689757150
Short name T115
Test name
Test status
Simulation time 21804582 ps
CPU time 0.87 seconds
Started Jul 25 06:03:46 PM PDT 24
Finished Jul 25 06:03:47 PM PDT 24
Peak memory 216092 kb
Host smart-e095df5c-f39c-4b60-8fc0-709aa4254709
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689757150 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2689757150
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1456742123
Short name T447
Test name
Test status
Simulation time 30683111 ps
CPU time 1.17 seconds
Started Jul 25 06:04:12 PM PDT 24
Finished Jul 25 06:04:14 PM PDT 24
Peak memory 216800 kb
Host smart-a2971e20-7ece-44a4-91f6-7ab201fe7f1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456742123 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1456742123
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/104.edn_alert.316449445
Short name T84
Test name
Test status
Simulation time 49900988 ps
CPU time 1.32 seconds
Started Jul 25 06:05:44 PM PDT 24
Finished Jul 25 06:05:46 PM PDT 24
Peak memory 220672 kb
Host smart-ce1a7daa-14c5-4239-980c-01fe4a9ae957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316449445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.316449445
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/120.edn_alert.3671597613
Short name T190
Test name
Test status
Simulation time 99747978 ps
CPU time 1.1 seconds
Started Jul 25 06:05:51 PM PDT 24
Finished Jul 25 06:05:53 PM PDT 24
Peak memory 218504 kb
Host smart-f071a32a-94f7-40e1-9c9f-ca58a63d577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671597613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.3671597613
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.2879882893
Short name T938
Test name
Test status
Simulation time 71308716 ps
CPU time 0.78 seconds
Started Jul 25 06:04:12 PM PDT 24
Finished Jul 25 06:04:13 PM PDT 24
Peak memory 216160 kb
Host smart-46805146-4a70-482a-b17d-6f16e09905d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879882893 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2879882893
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/140.edn_alert.2072554456
Short name T184
Test name
Test status
Simulation time 28612364 ps
CPU time 1.22 seconds
Started Jul 25 06:06:05 PM PDT 24
Finished Jul 25 06:06:06 PM PDT 24
Peak memory 215600 kb
Host smart-a4ee3c0d-5996-46bd-a57e-ba4713eae83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072554456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.2072554456
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1639624425
Short name T150
Test name
Test status
Simulation time 42460719 ps
CPU time 1.06 seconds
Started Jul 25 06:04:32 PM PDT 24
Finished Jul 25 06:04:33 PM PDT 24
Peak memory 216784 kb
Host smart-074ca177-48d9-4d16-abe4-07cf1ca3c913
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639624425 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1639624425
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2285548789
Short name T120
Test name
Test status
Simulation time 63965084 ps
CPU time 1.15 seconds
Started Jul 25 06:04:44 PM PDT 24
Finished Jul 25 06:04:45 PM PDT 24
Peak memory 216768 kb
Host smart-3fa1835f-e0fb-4353-8b18-46cb97be6d9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285548789 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2285548789
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_disable.3047367469
Short name T107
Test name
Test status
Simulation time 12441653 ps
CPU time 0.9 seconds
Started Jul 25 06:04:56 PM PDT 24
Finished Jul 25 06:04:57 PM PDT 24
Peak memory 216332 kb
Host smart-6db18412-efad-44cf-b9b7-cf8bf2757aa8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047367469 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3047367469
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/51.edn_err.1949524050
Short name T118
Test name
Test status
Simulation time 25881257 ps
CPU time 1.03 seconds
Started Jul 25 06:05:23 PM PDT 24
Finished Jul 25 06:05:25 PM PDT 24
Peak memory 223896 kb
Host smart-12712742-a872-41a5-a844-feedf9842b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949524050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1949524050
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/10.edn_alert_test.2298628861
Short name T369
Test name
Test status
Simulation time 31960891 ps
CPU time 1.18 seconds
Started Jul 25 06:04:02 PM PDT 24
Finished Jul 25 06:04:03 PM PDT 24
Peak memory 206764 kb
Host smart-3f1fc66b-e58a-4584-8d13-584272b8a111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298628861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2298628861
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/232.edn_genbits.2545781276
Short name T63
Test name
Test status
Simulation time 69699154 ps
CPU time 1.62 seconds
Started Jul 25 06:06:22 PM PDT 24
Finished Jul 25 06:06:24 PM PDT 24
Peak memory 218740 kb
Host smart-07da7672-d943-480f-b493-b833be7b0c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545781276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2545781276
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/120.edn_genbits.3497590302
Short name T562
Test name
Test status
Simulation time 41165935 ps
CPU time 1.55 seconds
Started Jul 25 06:05:50 PM PDT 24
Finished Jul 25 06:05:52 PM PDT 24
Peak memory 217508 kb
Host smart-f934378e-ff2d-45e1-805f-13e89321515a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497590302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3497590302
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/100.edn_genbits.620218591
Short name T294
Test name
Test status
Simulation time 92468481 ps
CPU time 1.17 seconds
Started Jul 25 06:05:44 PM PDT 24
Finished Jul 25 06:05:45 PM PDT 24
Peak memory 218800 kb
Host smart-5bed45a3-c1f5-4908-a1cf-87d404da7aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620218591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.620218591
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1977071056
Short name T293
Test name
Test status
Simulation time 122845093 ps
CPU time 1.93 seconds
Started Jul 25 06:06:04 PM PDT 24
Finished Jul 25 06:06:06 PM PDT 24
Peak memory 220108 kb
Host smart-4046c188-7b1f-4a9b-97cf-bf7f4e4b3653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977071056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1977071056
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/280.edn_genbits.4081460906
Short name T313
Test name
Test status
Simulation time 222551168 ps
CPU time 3.15 seconds
Started Jul 25 06:06:36 PM PDT 24
Finished Jul 25 06:06:40 PM PDT 24
Peak memory 219116 kb
Host smart-a20eada0-51cb-4bb5-af9a-2ce2722abd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081460906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.4081460906
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3739785190
Short name T85
Test name
Test status
Simulation time 20854569 ps
CPU time 1.02 seconds
Started Jul 25 06:05:02 PM PDT 24
Finished Jul 25 06:05:03 PM PDT 24
Peak memory 215740 kb
Host smart-5cb6f627-b8dc-4349-ba9c-d9f2cd4ad0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739785190 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3739785190
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/49.edn_alert.4278988791
Short name T103
Test name
Test status
Simulation time 78405476 ps
CPU time 1.24 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 221392 kb
Host smart-e3b81cdf-8cf1-439e-b5ea-2885d763122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278988791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.4278988791
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3583455704
Short name T249
Test name
Test status
Simulation time 46423549 ps
CPU time 1.16 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:43 PM PDT 24
Peak memory 206476 kb
Host smart-6b5f6864-ad77-4c8f-9477-fc51f16d6601
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583455704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3583455704
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/12.edn_intr.1307659564
Short name T350
Test name
Test status
Simulation time 22391222 ps
CPU time 1.11 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:12 PM PDT 24
Peak memory 215408 kb
Host smart-876c6506-af68-486c-9581-adc2596089af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307659564 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1307659564
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2747539668
Short name T271
Test name
Test status
Simulation time 50196748 ps
CPU time 1.69 seconds
Started Jul 25 05:58:37 PM PDT 24
Finished Jul 25 05:58:39 PM PDT 24
Peak memory 206616 kb
Host smart-beaf134b-5739-44f2-9717-d71c1f13bf8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747539668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2747539668
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_stress_all.4170581705
Short name T576
Test name
Test status
Simulation time 320351973 ps
CPU time 3.94 seconds
Started Jul 25 06:03:44 PM PDT 24
Finished Jul 25 06:03:48 PM PDT 24
Peak memory 218408 kb
Host smart-14424574-0d3e-4e06-a15d-fedc88e49e78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170581705 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.4170581705
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_genbits.4259000630
Short name T301
Test name
Test status
Simulation time 127011753 ps
CPU time 1.26 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:12 PM PDT 24
Peak memory 218736 kb
Host smart-3ca3901c-f2c2-4e07-908b-b95d29d19cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259000630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.4259000630
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2965788891
Short name T694
Test name
Test status
Simulation time 94406958 ps
CPU time 1.59 seconds
Started Jul 25 06:05:45 PM PDT 24
Finished Jul 25 06:05:47 PM PDT 24
Peak memory 218800 kb
Host smart-899f47a7-86ea-4591-a8c7-91bf8e266d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965788891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2965788891
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1691380198
Short name T927
Test name
Test status
Simulation time 202950876 ps
CPU time 1.42 seconds
Started Jul 25 06:05:44 PM PDT 24
Finished Jul 25 06:05:45 PM PDT 24
Peak memory 218560 kb
Host smart-80f7b00f-64f2-4ef9-b3b7-2e359c6794b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691380198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1691380198
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2270366744
Short name T675
Test name
Test status
Simulation time 35737906 ps
CPU time 1.15 seconds
Started Jul 25 06:05:54 PM PDT 24
Finished Jul 25 06:05:55 PM PDT 24
Peak memory 217392 kb
Host smart-d50c5ea7-1e2f-4ad9-a524-f397eb76ba2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270366744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2270366744
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1599291164
Short name T298
Test name
Test status
Simulation time 37826788 ps
CPU time 1.49 seconds
Started Jul 25 06:05:50 PM PDT 24
Finished Jul 25 06:05:51 PM PDT 24
Peak memory 219616 kb
Host smart-d4c3a5c5-d09b-42c2-9193-66e5086ff11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599291164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1599291164
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.398398910
Short name T338
Test name
Test status
Simulation time 78761868 ps
CPU time 1.17 seconds
Started Jul 25 06:06:00 PM PDT 24
Finished Jul 25 06:06:02 PM PDT 24
Peak memory 217384 kb
Host smart-9869a679-1f56-4ebf-90a3-bd1492d240b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398398910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.398398910
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.4009479567
Short name T267
Test name
Test status
Simulation time 46736852 ps
CPU time 1.21 seconds
Started Jul 25 06:06:08 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 219700 kb
Host smart-b26d1758-8b4f-4bb4-9e12-9ae25033c4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009479567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.4009479567
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/15.edn_genbits.612297563
Short name T290
Test name
Test status
Simulation time 55166955 ps
CPU time 2.02 seconds
Started Jul 25 06:04:14 PM PDT 24
Finished Jul 25 06:04:16 PM PDT 24
Peak memory 218396 kb
Host smart-ef3f54c8-2a3e-48a4-bd3d-50ea41e8b908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612297563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.612297563
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_genbits.667036951
Short name T889
Test name
Test status
Simulation time 136800486 ps
CPU time 1.28 seconds
Started Jul 25 06:04:13 PM PDT 24
Finished Jul 25 06:04:15 PM PDT 24
Peak memory 215224 kb
Host smart-ac68e92f-8bb1-4ec3-9960-4ffd0c03c9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667036951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.667036951
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2061627342
Short name T312
Test name
Test status
Simulation time 38861794 ps
CPU time 1.61 seconds
Started Jul 25 06:06:12 PM PDT 24
Finished Jul 25 06:06:14 PM PDT 24
Peak memory 218324 kb
Host smart-b5806e69-73d9-42ff-adea-abd949c7a57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061627342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2061627342
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.307687644
Short name T87
Test name
Test status
Simulation time 25609623 ps
CPU time 0.98 seconds
Started Jul 25 06:04:09 PM PDT 24
Finished Jul 25 06:04:10 PM PDT 24
Peak memory 215712 kb
Host smart-46793f15-e4ad-4cf2-8686-b51f91b1f450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307687644 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.307687644
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/211.edn_genbits.1456122332
Short name T13
Test name
Test status
Simulation time 52221598 ps
CPU time 1.65 seconds
Started Jul 25 06:06:19 PM PDT 24
Finished Jul 25 06:06:21 PM PDT 24
Peak memory 219296 kb
Host smart-c2083a82-fa75-4e53-a141-c6bc75ed45bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456122332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1456122332
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2302794222
Short name T695
Test name
Test status
Simulation time 25740004 ps
CPU time 1.33 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:12 PM PDT 24
Peak memory 219068 kb
Host smart-34a5ca15-1220-48b0-9c1c-061973db7e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302794222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2302794222
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.3882288942
Short name T476
Test name
Test status
Simulation time 47751081 ps
CPU time 1.67 seconds
Started Jul 25 06:06:14 PM PDT 24
Finished Jul 25 06:06:16 PM PDT 24
Peak memory 220156 kb
Host smart-840fa5eb-bd95-45e4-9e0e-1e5f7f700940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882288942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3882288942
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.901419840
Short name T1090
Test name
Test status
Simulation time 145543061 ps
CPU time 1.98 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:44 PM PDT 24
Peak memory 206392 kb
Host smart-a546195a-3f69-4640-b20c-90ecabad4f8f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901419840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.901419840
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2352268789
Short name T247
Test name
Test status
Simulation time 17523692 ps
CPU time 0.99 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:44 PM PDT 24
Peak memory 206476 kb
Host smart-677b8ee9-2599-4873-ba8a-8cdee8746fe1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352268789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2352268789
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3422022137
Short name T1083
Test name
Test status
Simulation time 161489812 ps
CPU time 1.45 seconds
Started Jul 25 05:58:45 PM PDT 24
Finished Jul 25 05:58:46 PM PDT 24
Peak memory 214928 kb
Host smart-8f0faea2-644b-4b7e-93ef-93d264302237
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422022137 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3422022137
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1285722294
Short name T1122
Test name
Test status
Simulation time 13288651 ps
CPU time 0.88 seconds
Started Jul 25 05:58:41 PM PDT 24
Finished Jul 25 05:58:42 PM PDT 24
Peak memory 206472 kb
Host smart-2f2745c6-a863-41fd-b349-a70291b7de81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285722294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1285722294
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.559873831
Short name T1025
Test name
Test status
Simulation time 43678870 ps
CPU time 0.86 seconds
Started Jul 25 05:58:40 PM PDT 24
Finished Jul 25 05:58:41 PM PDT 24
Peak memory 206304 kb
Host smart-494f2706-47d2-476f-968f-97eb8a705ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559873831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.559873831
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3673394868
Short name T1031
Test name
Test status
Simulation time 118578474 ps
CPU time 1.47 seconds
Started Jul 25 05:58:39 PM PDT 24
Finished Jul 25 05:58:41 PM PDT 24
Peak memory 206692 kb
Host smart-dc5daa4c-841f-47a3-9335-ab0972029c92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673394868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3673394868
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2524113453
Short name T1071
Test name
Test status
Simulation time 1792837234 ps
CPU time 3.98 seconds
Started Jul 25 05:58:43 PM PDT 24
Finished Jul 25 05:58:47 PM PDT 24
Peak memory 214848 kb
Host smart-652c8ca9-2fde-480b-b309-f5322a87cbb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524113453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2524113453
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3256731270
Short name T1048
Test name
Test status
Simulation time 75577104 ps
CPU time 1.23 seconds
Started Jul 25 05:58:45 PM PDT 24
Finished Jul 25 05:58:46 PM PDT 24
Peak memory 206388 kb
Host smart-9080921f-5fe6-4e67-8431-a45cedd9b5e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256731270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3256731270
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3140126057
Short name T248
Test name
Test status
Simulation time 1786582525 ps
CPU time 6.49 seconds
Started Jul 25 05:58:43 PM PDT 24
Finished Jul 25 05:58:50 PM PDT 24
Peak memory 206444 kb
Host smart-ab15cac1-ebb6-4487-8367-fce4ce2ab7f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140126057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3140126057
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3177419552
Short name T988
Test name
Test status
Simulation time 204093524 ps
CPU time 0.92 seconds
Started Jul 25 05:58:45 PM PDT 24
Finished Jul 25 05:58:46 PM PDT 24
Peak memory 206272 kb
Host smart-43249917-2981-4503-a003-63b58ff55123
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177419552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3177419552
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1009057588
Short name T1114
Test name
Test status
Simulation time 24587359 ps
CPU time 1.3 seconds
Started Jul 25 05:58:41 PM PDT 24
Finished Jul 25 05:58:43 PM PDT 24
Peak memory 217188 kb
Host smart-ebc55eb4-49dc-49ad-ae77-263709fa99bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009057588 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1009057588
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2598163775
Short name T993
Test name
Test status
Simulation time 23081173 ps
CPU time 0.89 seconds
Started Jul 25 05:58:39 PM PDT 24
Finished Jul 25 05:58:40 PM PDT 24
Peak memory 206448 kb
Host smart-3ab6297c-ed7f-4e03-982e-c9c31d83909f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598163775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2598163775
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3910827106
Short name T1018
Test name
Test status
Simulation time 56001307 ps
CPU time 0.87 seconds
Started Jul 25 05:58:39 PM PDT 24
Finished Jul 25 05:58:40 PM PDT 24
Peak memory 206476 kb
Host smart-fd4f5fc1-13da-41fc-8ef0-abbfa3a3abc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910827106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3910827106
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.840689542
Short name T252
Test name
Test status
Simulation time 50425207 ps
CPU time 1.22 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:44 PM PDT 24
Peak memory 206660 kb
Host smart-ba16afb1-ff5f-4f92-8f3e-3d0240410043
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840689542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.840689542
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1610848459
Short name T1069
Test name
Test status
Simulation time 83280719 ps
CPU time 3.23 seconds
Started Jul 25 05:58:39 PM PDT 24
Finished Jul 25 05:58:43 PM PDT 24
Peak memory 214932 kb
Host smart-69752a3f-73bc-4570-a5d3-f008c4ab0a29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610848459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1610848459
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2986933743
Short name T1104
Test name
Test status
Simulation time 343547065 ps
CPU time 2.54 seconds
Started Jul 25 05:58:43 PM PDT 24
Finished Jul 25 05:58:46 PM PDT 24
Peak memory 206592 kb
Host smart-d6070175-2516-4931-9e5e-1a01db3df448
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986933743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2986933743
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.738140657
Short name T1005
Test name
Test status
Simulation time 34877862 ps
CPU time 1.33 seconds
Started Jul 25 05:58:53 PM PDT 24
Finished Jul 25 05:58:54 PM PDT 24
Peak memory 214912 kb
Host smart-c2ae737a-41ae-489b-b842-0b04ddabbd7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738140657 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.738140657
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2952109308
Short name T1101
Test name
Test status
Simulation time 36696089 ps
CPU time 0.89 seconds
Started Jul 25 05:58:55 PM PDT 24
Finished Jul 25 05:58:56 PM PDT 24
Peak memory 206448 kb
Host smart-d838f9a1-d828-4cd6-848a-ca2924521a40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952109308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2952109308
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3893172956
Short name T1086
Test name
Test status
Simulation time 32391446 ps
CPU time 0.8 seconds
Started Jul 25 05:58:52 PM PDT 24
Finished Jul 25 05:58:53 PM PDT 24
Peak memory 206240 kb
Host smart-70573047-75f7-4604-b24c-5897697d843c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893172956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3893172956
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1597791408
Short name T251
Test name
Test status
Simulation time 36014510 ps
CPU time 1.47 seconds
Started Jul 25 05:58:50 PM PDT 24
Finished Jul 25 05:58:51 PM PDT 24
Peak memory 206700 kb
Host smart-ce3c24b6-e8b8-4cb2-ae59-9ba8d6f39470
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597791408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1597791408
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2409262480
Short name T1066
Test name
Test status
Simulation time 97172801 ps
CPU time 2.19 seconds
Started Jul 25 05:58:52 PM PDT 24
Finished Jul 25 05:58:54 PM PDT 24
Peak memory 214964 kb
Host smart-0edd4169-969b-46ae-ba2a-a1167dc8d120
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409262480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2409262480
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1457757903
Short name T1120
Test name
Test status
Simulation time 154672652 ps
CPU time 3.54 seconds
Started Jul 25 05:58:53 PM PDT 24
Finished Jul 25 05:58:56 PM PDT 24
Peak memory 206968 kb
Host smart-3401ee0d-6fe9-4b05-9a45-7bcc2e0bdeef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457757903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1457757903
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2194656075
Short name T1116
Test name
Test status
Simulation time 232988640 ps
CPU time 1.66 seconds
Started Jul 25 05:58:50 PM PDT 24
Finished Jul 25 05:58:51 PM PDT 24
Peak memory 214792 kb
Host smart-caaa8522-c41d-41e6-9e72-9808a5e72d4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194656075 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2194656075
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1500544386
Short name T1121
Test name
Test status
Simulation time 23777359 ps
CPU time 0.92 seconds
Started Jul 25 05:58:52 PM PDT 24
Finished Jul 25 05:58:53 PM PDT 24
Peak memory 206444 kb
Host smart-da8416ca-5bc6-455a-9988-20c4f3d342a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500544386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1500544386
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.384991782
Short name T1038
Test name
Test status
Simulation time 14956058 ps
CPU time 0.79 seconds
Started Jul 25 05:58:49 PM PDT 24
Finished Jul 25 05:58:50 PM PDT 24
Peak memory 206316 kb
Host smart-ac443a79-c795-430a-82cc-823e4ea08154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384991782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.384991782
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3378685998
Short name T1091
Test name
Test status
Simulation time 72966110 ps
CPU time 1.55 seconds
Started Jul 25 05:58:50 PM PDT 24
Finished Jul 25 05:58:52 PM PDT 24
Peak memory 206636 kb
Host smart-a802b172-32c3-42a0-b101-20de54031464
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378685998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3378685998
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1837798856
Short name T1010
Test name
Test status
Simulation time 253516737 ps
CPU time 4.57 seconds
Started Jul 25 05:58:52 PM PDT 24
Finished Jul 25 05:58:56 PM PDT 24
Peak memory 223060 kb
Host smart-d2da39c7-f47b-4d74-9e15-28bc8c7fb72b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837798856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1837798856
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1486266177
Short name T1061
Test name
Test status
Simulation time 83126641 ps
CPU time 1.64 seconds
Started Jul 25 05:58:57 PM PDT 24
Finished Jul 25 05:58:59 PM PDT 24
Peak memory 206592 kb
Host smart-255befa2-4220-4bd2-be0e-140250633980
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486266177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1486266177
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3948346767
Short name T1084
Test name
Test status
Simulation time 39845192 ps
CPU time 0.92 seconds
Started Jul 25 05:58:51 PM PDT 24
Finished Jul 25 05:58:52 PM PDT 24
Peak memory 206640 kb
Host smart-ff0dc6a8-f463-400e-83de-4ab4f67ba7b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948346767 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3948346767
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1266229641
Short name T253
Test name
Test status
Simulation time 31573615 ps
CPU time 0.84 seconds
Started Jul 25 05:58:55 PM PDT 24
Finished Jul 25 05:58:56 PM PDT 24
Peak memory 206456 kb
Host smart-df9d100c-566b-4d20-8c1a-2f82e2c8e00b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266229641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1266229641
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3023762841
Short name T987
Test name
Test status
Simulation time 58139869 ps
CPU time 0.78 seconds
Started Jul 25 05:58:52 PM PDT 24
Finished Jul 25 05:58:53 PM PDT 24
Peak memory 206332 kb
Host smart-2a69e0bd-c908-48f7-a5c6-e950df735e48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023762841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3023762841
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3887089159
Short name T1112
Test name
Test status
Simulation time 27954573 ps
CPU time 1.38 seconds
Started Jul 25 05:58:52 PM PDT 24
Finished Jul 25 05:58:54 PM PDT 24
Peak memory 206560 kb
Host smart-d7bb1e34-60fd-4ea8-9e54-fee97e78d8a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887089159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3887089159
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.449071507
Short name T1049
Test name
Test status
Simulation time 27116909 ps
CPU time 1.83 seconds
Started Jul 25 05:58:57 PM PDT 24
Finished Jul 25 05:58:59 PM PDT 24
Peak memory 214908 kb
Host smart-c120ddff-4b2b-41ef-8908-9310fda9f25c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449071507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.449071507
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1310191259
Short name T1073
Test name
Test status
Simulation time 183896349 ps
CPU time 2.59 seconds
Started Jul 25 05:58:52 PM PDT 24
Finished Jul 25 05:58:55 PM PDT 24
Peak memory 206544 kb
Host smart-55cbfe4a-a136-4f7d-918a-e6dba6e594e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310191259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1310191259
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2434572681
Short name T1059
Test name
Test status
Simulation time 61986623 ps
CPU time 1.41 seconds
Started Jul 25 05:59:07 PM PDT 24
Finished Jul 25 05:59:08 PM PDT 24
Peak memory 223124 kb
Host smart-e4ababf0-1612-4c95-b600-0981bc548356
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434572681 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2434572681
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3957003967
Short name T254
Test name
Test status
Simulation time 100172086 ps
CPU time 0.9 seconds
Started Jul 25 05:58:49 PM PDT 24
Finished Jul 25 05:58:50 PM PDT 24
Peak memory 206416 kb
Host smart-64477aba-0a62-442d-9e05-6975012373ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957003967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3957003967
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.414712174
Short name T1110
Test name
Test status
Simulation time 41231852 ps
CPU time 0.85 seconds
Started Jul 25 05:58:50 PM PDT 24
Finished Jul 25 05:58:51 PM PDT 24
Peak memory 206236 kb
Host smart-e55064af-aa44-4330-a1b6-edb110ab3254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414712174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.414712174
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2912730646
Short name T1119
Test name
Test status
Simulation time 21880101 ps
CPU time 1.24 seconds
Started Jul 25 05:58:55 PM PDT 24
Finished Jul 25 05:58:56 PM PDT 24
Peak memory 206580 kb
Host smart-78e80b78-a6e6-4d93-9d69-b7243af105e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912730646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2912730646
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2888315154
Short name T994
Test name
Test status
Simulation time 61748993 ps
CPU time 2.54 seconds
Started Jul 25 05:59:07 PM PDT 24
Finished Jul 25 05:59:09 PM PDT 24
Peak memory 214904 kb
Host smart-5b7e5cba-225d-44e5-8c61-bfa9d6960b34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888315154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2888315154
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2956081118
Short name T214
Test name
Test status
Simulation time 85227801 ps
CPU time 1.53 seconds
Started Jul 25 05:58:57 PM PDT 24
Finished Jul 25 05:58:58 PM PDT 24
Peak memory 206544 kb
Host smart-52174ba9-f299-43ef-9542-43ee676c58a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956081118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2956081118
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2293073344
Short name T1077
Test name
Test status
Simulation time 28265866 ps
CPU time 1.11 seconds
Started Jul 25 05:58:52 PM PDT 24
Finished Jul 25 05:58:54 PM PDT 24
Peak memory 214892 kb
Host smart-a6cb166b-a16a-4c08-b888-bbb98f525b2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293073344 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2293073344
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1338187582
Short name T246
Test name
Test status
Simulation time 18674694 ps
CPU time 0.93 seconds
Started Jul 25 05:58:57 PM PDT 24
Finished Jul 25 05:58:58 PM PDT 24
Peak memory 206432 kb
Host smart-35445665-f433-4d40-ae98-4fdd28c7c87e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338187582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1338187582
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.934303247
Short name T1056
Test name
Test status
Simulation time 32200216 ps
CPU time 0.88 seconds
Started Jul 25 05:58:56 PM PDT 24
Finished Jul 25 05:58:57 PM PDT 24
Peak memory 206376 kb
Host smart-9ceaa642-b883-4ab9-84e2-0554f6081827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934303247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.934303247
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.56947700
Short name T1064
Test name
Test status
Simulation time 56445439 ps
CPU time 1.07 seconds
Started Jul 25 05:58:56 PM PDT 24
Finished Jul 25 05:58:57 PM PDT 24
Peak memory 206592 kb
Host smart-cf82b435-e011-4407-a175-4ef7c93403b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56947700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_out
standing.56947700
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.422554196
Short name T1092
Test name
Test status
Simulation time 100059209 ps
CPU time 1.95 seconds
Started Jul 25 05:58:55 PM PDT 24
Finished Jul 25 05:58:57 PM PDT 24
Peak memory 214928 kb
Host smart-12494f1a-8cd2-46f7-91df-6b551a204a76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422554196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.422554196
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1014925997
Short name T1020
Test name
Test status
Simulation time 1060416323 ps
CPU time 2.35 seconds
Started Jul 25 05:58:52 PM PDT 24
Finished Jul 25 05:58:55 PM PDT 24
Peak memory 214852 kb
Host smart-cad18e65-8397-4fbf-a3c3-9c4beb4b71dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014925997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1014925997
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.579396459
Short name T1079
Test name
Test status
Simulation time 32132037 ps
CPU time 1.06 seconds
Started Jul 25 05:58:56 PM PDT 24
Finished Jul 25 05:58:57 PM PDT 24
Peak memory 214868 kb
Host smart-5bd5c6a7-fbaa-49d2-b966-1e9491cab54a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579396459 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.579396459
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1956134894
Short name T995
Test name
Test status
Simulation time 14429400 ps
CPU time 0.87 seconds
Started Jul 25 05:58:53 PM PDT 24
Finished Jul 25 05:58:54 PM PDT 24
Peak memory 206468 kb
Host smart-6f51513e-a808-4052-ad6b-943248198cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956134894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1956134894
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.748524163
Short name T1118
Test name
Test status
Simulation time 21044067 ps
CPU time 1.1 seconds
Started Jul 25 05:58:56 PM PDT 24
Finished Jul 25 05:58:58 PM PDT 24
Peak memory 206500 kb
Host smart-f2f2de4c-76a4-4cb8-a643-05b9c31b57c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748524163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.748524163
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.113474909
Short name T1041
Test name
Test status
Simulation time 412903233 ps
CPU time 3.52 seconds
Started Jul 25 05:58:59 PM PDT 24
Finished Jul 25 05:59:02 PM PDT 24
Peak memory 214760 kb
Host smart-b6d94604-c51b-403d-a014-ea37a354533e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113474909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.113474909
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.354356461
Short name T1067
Test name
Test status
Simulation time 174296671 ps
CPU time 2.12 seconds
Started Jul 25 05:58:52 PM PDT 24
Finished Jul 25 05:58:54 PM PDT 24
Peak memory 206704 kb
Host smart-e6b4f5ba-73c6-41b3-8eae-7c05901d1795
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354356461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.354356461
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1681563254
Short name T1000
Test name
Test status
Simulation time 21820574 ps
CPU time 1.44 seconds
Started Jul 25 05:59:00 PM PDT 24
Finished Jul 25 05:59:01 PM PDT 24
Peak memory 214920 kb
Host smart-a95f1dba-0977-4de3-8408-ecd44c6c8ec4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681563254 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1681563254
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2868698987
Short name T243
Test name
Test status
Simulation time 11739353 ps
CPU time 0.92 seconds
Started Jul 25 05:59:01 PM PDT 24
Finished Jul 25 05:59:02 PM PDT 24
Peak memory 206392 kb
Host smart-57e2a3d1-1ec9-4796-b2ad-a453f084a2ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868698987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2868698987
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1236554635
Short name T1107
Test name
Test status
Simulation time 13174182 ps
CPU time 0.87 seconds
Started Jul 25 05:59:00 PM PDT 24
Finished Jul 25 05:59:01 PM PDT 24
Peak memory 206460 kb
Host smart-0ef25405-429d-4465-a918-a31ab3613309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236554635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1236554635
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3145304697
Short name T1029
Test name
Test status
Simulation time 71968147 ps
CPU time 1.03 seconds
Started Jul 25 05:59:02 PM PDT 24
Finished Jul 25 05:59:03 PM PDT 24
Peak memory 206608 kb
Host smart-8a16b6e5-8ba6-47ea-af40-0887bdefedb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145304697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3145304697
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2356375204
Short name T1125
Test name
Test status
Simulation time 225463195 ps
CPU time 2.65 seconds
Started Jul 25 05:59:00 PM PDT 24
Finished Jul 25 05:59:03 PM PDT 24
Peak memory 214796 kb
Host smart-fe8499d2-aee6-4583-8219-61085b68519c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356375204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2356375204
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1037381753
Short name T270
Test name
Test status
Simulation time 132243799 ps
CPU time 2.28 seconds
Started Jul 25 05:59:03 PM PDT 24
Finished Jul 25 05:59:05 PM PDT 24
Peak memory 206680 kb
Host smart-95fb94e2-8344-4c48-a27f-e28d2bcfc2db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037381753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1037381753
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2009766300
Short name T1012
Test name
Test status
Simulation time 35575572 ps
CPU time 1.62 seconds
Started Jul 25 05:59:00 PM PDT 24
Finished Jul 25 05:59:01 PM PDT 24
Peak memory 214884 kb
Host smart-ba1ca2d7-a998-4296-bd6a-c7e7a9f2ec7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009766300 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2009766300
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1606726274
Short name T992
Test name
Test status
Simulation time 20790697 ps
CPU time 0.79 seconds
Started Jul 25 05:58:58 PM PDT 24
Finished Jul 25 05:58:58 PM PDT 24
Peak memory 206284 kb
Host smart-cf7122b3-f94e-4591-93d2-c763419fd2b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606726274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1606726274
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2389662786
Short name T1043
Test name
Test status
Simulation time 14821774 ps
CPU time 0.92 seconds
Started Jul 25 05:59:00 PM PDT 24
Finished Jul 25 05:59:01 PM PDT 24
Peak memory 206472 kb
Host smart-53018949-72d5-45fc-957d-f2cd46b3162a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389662786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2389662786
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.861296733
Short name T256
Test name
Test status
Simulation time 57758253 ps
CPU time 1.16 seconds
Started Jul 25 05:58:59 PM PDT 24
Finished Jul 25 05:59:00 PM PDT 24
Peak memory 206592 kb
Host smart-11f5f5c0-e08e-4de1-8f3f-3fdbb0ebb5e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861296733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.861296733
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1005770150
Short name T990
Test name
Test status
Simulation time 204959775 ps
CPU time 2.85 seconds
Started Jul 25 05:59:08 PM PDT 24
Finished Jul 25 05:59:11 PM PDT 24
Peak memory 214888 kb
Host smart-81371585-246c-48cd-a9a2-f191c10a3878
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005770150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1005770150
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2852233028
Short name T272
Test name
Test status
Simulation time 373448526 ps
CPU time 2.39 seconds
Started Jul 25 05:59:01 PM PDT 24
Finished Jul 25 05:59:04 PM PDT 24
Peak memory 215396 kb
Host smart-8897541c-721c-4935-a5e9-a3ebb7ffa81e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852233028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2852233028
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2926730955
Short name T1015
Test name
Test status
Simulation time 67373822 ps
CPU time 1.2 seconds
Started Jul 25 05:59:03 PM PDT 24
Finished Jul 25 05:59:04 PM PDT 24
Peak memory 216556 kb
Host smart-a05cae81-4973-4274-8df6-b2c5a735b8df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926730955 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2926730955
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.712004364
Short name T1054
Test name
Test status
Simulation time 27032752 ps
CPU time 0.95 seconds
Started Jul 25 05:59:03 PM PDT 24
Finished Jul 25 05:59:04 PM PDT 24
Peak memory 206552 kb
Host smart-22d0c6c5-ed1e-406a-b935-c0b5cf0b2294
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712004364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.712004364
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2363610569
Short name T1022
Test name
Test status
Simulation time 124969931 ps
CPU time 0.78 seconds
Started Jul 25 05:58:58 PM PDT 24
Finished Jul 25 05:58:58 PM PDT 24
Peak memory 206268 kb
Host smart-d156898d-232a-4c22-924c-de6eee9ccabf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363610569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2363610569
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2015033789
Short name T1098
Test name
Test status
Simulation time 14871219 ps
CPU time 1.03 seconds
Started Jul 25 05:59:03 PM PDT 24
Finished Jul 25 05:59:04 PM PDT 24
Peak memory 206500 kb
Host smart-cc053062-d77e-42ea-8152-645c6d6de09c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015033789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2015033789
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.4269824581
Short name T1036
Test name
Test status
Simulation time 175657644 ps
CPU time 3.4 seconds
Started Jul 25 05:59:00 PM PDT 24
Finished Jul 25 05:59:03 PM PDT 24
Peak memory 214780 kb
Host smart-7c023475-903a-43f6-970b-36abc0964760
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269824581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.4269824581
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3798009424
Short name T1045
Test name
Test status
Simulation time 222726588 ps
CPU time 1.66 seconds
Started Jul 25 05:59:08 PM PDT 24
Finished Jul 25 05:59:10 PM PDT 24
Peak memory 206700 kb
Host smart-08172ac9-2ad3-4297-a43d-ecb9e0e5615c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798009424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3798009424
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2441261197
Short name T1072
Test name
Test status
Simulation time 79262012 ps
CPU time 1.22 seconds
Started Jul 25 05:59:00 PM PDT 24
Finished Jul 25 05:59:01 PM PDT 24
Peak memory 214844 kb
Host smart-49d9cb6c-773a-472f-84b2-569b787e57e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441261197 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2441261197
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3693957398
Short name T1065
Test name
Test status
Simulation time 111233684 ps
CPU time 0.9 seconds
Started Jul 25 05:59:01 PM PDT 24
Finished Jul 25 05:59:02 PM PDT 24
Peak memory 206312 kb
Host smart-ca33edba-45cf-48d1-a555-f1a6d62bf9bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693957398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3693957398
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3898334610
Short name T1034
Test name
Test status
Simulation time 25724247 ps
CPU time 0.87 seconds
Started Jul 25 05:58:59 PM PDT 24
Finished Jul 25 05:59:00 PM PDT 24
Peak memory 206376 kb
Host smart-829492a8-e439-4b44-83b9-ec1c171ed3bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898334610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3898334610
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1295440287
Short name T1088
Test name
Test status
Simulation time 66303394 ps
CPU time 1.11 seconds
Started Jul 25 05:59:02 PM PDT 24
Finished Jul 25 05:59:04 PM PDT 24
Peak memory 206636 kb
Host smart-0148cff9-f342-4340-be5e-e99126d3d6c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295440287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1295440287
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.72844113
Short name T1103
Test name
Test status
Simulation time 530912773 ps
CPU time 4.98 seconds
Started Jul 25 05:58:59 PM PDT 24
Finished Jul 25 05:59:05 PM PDT 24
Peak memory 223028 kb
Host smart-891137fd-bc4c-4c39-a019-fa5dc9285855
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72844113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.72844113
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.747293000
Short name T1051
Test name
Test status
Simulation time 96442935 ps
CPU time 2.63 seconds
Started Jul 25 05:59:02 PM PDT 24
Finished Jul 25 05:59:04 PM PDT 24
Peak memory 206600 kb
Host smart-cef6624f-e77d-4cd0-aa14-a752d5ecc4d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747293000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.747293000
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2505812979
Short name T241
Test name
Test status
Simulation time 124456569 ps
CPU time 1.46 seconds
Started Jul 25 05:58:41 PM PDT 24
Finished Jul 25 05:58:43 PM PDT 24
Peak memory 206520 kb
Host smart-36a48eaf-6491-437e-953f-78628233b45c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505812979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2505812979
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.296876770
Short name T1063
Test name
Test status
Simulation time 368483183 ps
CPU time 3.09 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:46 PM PDT 24
Peak memory 206444 kb
Host smart-21329be1-59f6-433c-858f-20db39ebdde9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296876770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.296876770
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2820734780
Short name T1027
Test name
Test status
Simulation time 17316912 ps
CPU time 0.99 seconds
Started Jul 25 05:58:39 PM PDT 24
Finished Jul 25 05:58:40 PM PDT 24
Peak memory 206480 kb
Host smart-7e9ef774-0384-497d-aa8c-5992583b3322
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820734780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2820734780
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1771182020
Short name T1108
Test name
Test status
Simulation time 36880976 ps
CPU time 1.27 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:43 PM PDT 24
Peak memory 214940 kb
Host smart-342bd9dd-2e7e-4d15-9bf7-09e816b942cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771182020 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1771182020
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.4103774095
Short name T250
Test name
Test status
Simulation time 16287540 ps
CPU time 1 seconds
Started Jul 25 05:58:40 PM PDT 24
Finished Jul 25 05:58:42 PM PDT 24
Peak memory 206512 kb
Host smart-382f49c8-8654-4656-b217-165efd7c8fb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103774095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.4103774095
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2972722763
Short name T1044
Test name
Test status
Simulation time 15018658 ps
CPU time 0.91 seconds
Started Jul 25 05:58:40 PM PDT 24
Finished Jul 25 05:58:41 PM PDT 24
Peak memory 206520 kb
Host smart-ccebb338-4d39-40f7-b2df-dff1a35b6e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972722763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2972722763
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4242433591
Short name T1039
Test name
Test status
Simulation time 49623050 ps
CPU time 1.31 seconds
Started Jul 25 05:58:46 PM PDT 24
Finished Jul 25 05:58:47 PM PDT 24
Peak memory 206588 kb
Host smart-18a98fd9-849c-4672-bafc-219383a73574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242433591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.4242433591
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.207650128
Short name T1124
Test name
Test status
Simulation time 86366966 ps
CPU time 3.13 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:45 PM PDT 24
Peak memory 214928 kb
Host smart-cd46d57b-0d51-4c03-942d-bfb8de33a00a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207650128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.207650128
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2270038955
Short name T1117
Test name
Test status
Simulation time 189048182 ps
CPU time 1.71 seconds
Started Jul 25 05:58:39 PM PDT 24
Finished Jul 25 05:58:40 PM PDT 24
Peak memory 206712 kb
Host smart-7255121a-a20f-4efa-8ccd-25d7d4d6cad9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270038955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2270038955
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1730484393
Short name T1014
Test name
Test status
Simulation time 24118293 ps
CPU time 0.88 seconds
Started Jul 25 05:58:59 PM PDT 24
Finished Jul 25 05:59:00 PM PDT 24
Peak memory 206452 kb
Host smart-37c20a32-c474-45af-9e4c-280a33291d6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730484393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1730484393
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3591549467
Short name T1105
Test name
Test status
Simulation time 19976431 ps
CPU time 0.82 seconds
Started Jul 25 05:59:02 PM PDT 24
Finished Jul 25 05:59:03 PM PDT 24
Peak memory 206276 kb
Host smart-62cdd378-510d-4225-8eb0-b99d1c134025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591549467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3591549467
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.614976889
Short name T1017
Test name
Test status
Simulation time 17162911 ps
CPU time 0.81 seconds
Started Jul 25 05:59:00 PM PDT 24
Finished Jul 25 05:59:01 PM PDT 24
Peak memory 206328 kb
Host smart-ebd1eecf-a5f5-4327-89af-4fb5601a0d30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614976889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.614976889
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.722476593
Short name T1053
Test name
Test status
Simulation time 23637419 ps
CPU time 0.87 seconds
Started Jul 25 05:59:07 PM PDT 24
Finished Jul 25 05:59:08 PM PDT 24
Peak memory 206592 kb
Host smart-8086f394-9a70-4d9c-b5dc-e6a0456127ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722476593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.722476593
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3007664042
Short name T1032
Test name
Test status
Simulation time 51808499 ps
CPU time 0.91 seconds
Started Jul 25 05:59:02 PM PDT 24
Finished Jul 25 05:59:03 PM PDT 24
Peak memory 206452 kb
Host smart-f2d32331-2c83-4c0e-b57d-c6cad85f8908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007664042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3007664042
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3400215975
Short name T1007
Test name
Test status
Simulation time 46427318 ps
CPU time 0.85 seconds
Started Jul 25 05:59:00 PM PDT 24
Finished Jul 25 05:59:01 PM PDT 24
Peak memory 206444 kb
Host smart-cbd62ff3-b47e-488c-a8f4-10d4cccf5296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400215975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3400215975
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2427402343
Short name T1037
Test name
Test status
Simulation time 11662644 ps
CPU time 0.87 seconds
Started Jul 25 05:59:00 PM PDT 24
Finished Jul 25 05:59:01 PM PDT 24
Peak memory 206416 kb
Host smart-0c3b4ebc-7ac2-4915-8565-2d464d039918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427402343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2427402343
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2310493404
Short name T1002
Test name
Test status
Simulation time 14660911 ps
CPU time 0.92 seconds
Started Jul 25 05:59:00 PM PDT 24
Finished Jul 25 05:59:01 PM PDT 24
Peak memory 206464 kb
Host smart-6c2cf624-079d-433f-8de9-fd3c2d6e825c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310493404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2310493404
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1960511554
Short name T1003
Test name
Test status
Simulation time 58369792 ps
CPU time 0.81 seconds
Started Jul 25 05:59:01 PM PDT 24
Finished Jul 25 05:59:02 PM PDT 24
Peak memory 206276 kb
Host smart-b2f569c6-7bdd-4a2c-a2f2-c69424266d44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960511554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1960511554
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2243760501
Short name T1099
Test name
Test status
Simulation time 33703557 ps
CPU time 0.82 seconds
Started Jul 25 05:59:07 PM PDT 24
Finished Jul 25 05:59:08 PM PDT 24
Peak memory 206312 kb
Host smart-aab8bead-2095-4cbf-b752-3747a6644dc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243760501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2243760501
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.4266277280
Short name T1093
Test name
Test status
Simulation time 37190793 ps
CPU time 1.56 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:45 PM PDT 24
Peak memory 206452 kb
Host smart-d631861f-363a-4f8c-9115-b70811c257af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266277280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.4266277280
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1705926869
Short name T1013
Test name
Test status
Simulation time 173362649 ps
CPU time 2.92 seconds
Started Jul 25 05:58:40 PM PDT 24
Finished Jul 25 05:58:43 PM PDT 24
Peak memory 206448 kb
Host smart-b1c24812-8881-4ba7-af60-f98fc63ff5cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705926869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1705926869
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3976655446
Short name T1009
Test name
Test status
Simulation time 52420578 ps
CPU time 0.92 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:44 PM PDT 24
Peak memory 206484 kb
Host smart-52680d01-51fb-4dea-b9a3-35e0192d2d50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976655446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3976655446
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.768732058
Short name T1111
Test name
Test status
Simulation time 57390810 ps
CPU time 1.3 seconds
Started Jul 25 05:58:43 PM PDT 24
Finished Jul 25 05:58:44 PM PDT 24
Peak memory 214844 kb
Host smart-b67ad1ff-6dfd-4139-b134-7c49f450dc84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768732058 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.768732058
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1014275880
Short name T242
Test name
Test status
Simulation time 42610303 ps
CPU time 0.85 seconds
Started Jul 25 05:58:44 PM PDT 24
Finished Jul 25 05:58:45 PM PDT 24
Peak memory 206488 kb
Host smart-35d21cbc-10e1-41d2-bc6a-40d733e92d7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014275880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1014275880
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1171118040
Short name T1023
Test name
Test status
Simulation time 14346703 ps
CPU time 0.86 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:43 PM PDT 24
Peak memory 206480 kb
Host smart-d06fa22c-14cb-4a19-ba77-0e4eca4b693f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171118040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1171118040
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1823204323
Short name T1109
Test name
Test status
Simulation time 25780130 ps
CPU time 1.13 seconds
Started Jul 25 05:58:43 PM PDT 24
Finished Jul 25 05:58:45 PM PDT 24
Peak memory 206576 kb
Host smart-89ae5ffb-4407-4efa-b0d1-c1ad7c8f50f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823204323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1823204323
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.768565387
Short name T1123
Test name
Test status
Simulation time 216708723 ps
CPU time 4.08 seconds
Started Jul 25 05:58:43 PM PDT 24
Finished Jul 25 05:58:48 PM PDT 24
Peak memory 214908 kb
Host smart-136d546b-0293-4010-a5ed-980c4d4ce62d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768565387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.768565387
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.704170964
Short name T269
Test name
Test status
Simulation time 97612636 ps
CPU time 2.68 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:45 PM PDT 24
Peak memory 206684 kb
Host smart-2077b42c-4236-4e44-b88c-8bc1355a25f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704170964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.704170964
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3076613301
Short name T1106
Test name
Test status
Simulation time 40625252 ps
CPU time 0.83 seconds
Started Jul 25 05:59:01 PM PDT 24
Finished Jul 25 05:59:02 PM PDT 24
Peak memory 206316 kb
Host smart-0d58bb39-d0e7-4f56-9fd3-efce32b00f8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076613301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3076613301
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2328551551
Short name T1089
Test name
Test status
Simulation time 11923279 ps
CPU time 0.87 seconds
Started Jul 25 05:59:01 PM PDT 24
Finished Jul 25 05:59:02 PM PDT 24
Peak memory 206484 kb
Host smart-6f78be4e-1d38-4e3e-b57d-2f016aa21a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328551551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2328551551
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3413798861
Short name T1113
Test name
Test status
Simulation time 24134176 ps
CPU time 0.92 seconds
Started Jul 25 05:59:02 PM PDT 24
Finished Jul 25 05:59:03 PM PDT 24
Peak memory 206380 kb
Host smart-37086b12-a3b6-4e94-b9d8-b7fe2215b5c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413798861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3413798861
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.527240750
Short name T1046
Test name
Test status
Simulation time 11408288 ps
CPU time 0.84 seconds
Started Jul 25 05:59:02 PM PDT 24
Finished Jul 25 05:59:03 PM PDT 24
Peak memory 206456 kb
Host smart-7a0cceeb-26f5-40be-b301-8f2442b8d8fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527240750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.527240750
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2197712294
Short name T1042
Test name
Test status
Simulation time 24392540 ps
CPU time 0.86 seconds
Started Jul 25 05:59:07 PM PDT 24
Finished Jul 25 05:59:08 PM PDT 24
Peak memory 206484 kb
Host smart-97762832-fd59-45a0-b2af-fd80289757b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197712294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2197712294
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.729719179
Short name T1076
Test name
Test status
Simulation time 24666260 ps
CPU time 0.86 seconds
Started Jul 25 05:59:01 PM PDT 24
Finished Jul 25 05:59:02 PM PDT 24
Peak memory 206468 kb
Host smart-84a477de-d1c5-4fa3-af6f-d0ac21404e6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729719179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.729719179
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2310059232
Short name T1033
Test name
Test status
Simulation time 21571120 ps
CPU time 0.86 seconds
Started Jul 25 05:59:01 PM PDT 24
Finished Jul 25 05:59:02 PM PDT 24
Peak memory 206396 kb
Host smart-1071698b-dd26-45aa-b4bb-f4d5deed1a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310059232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2310059232
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2608914924
Short name T991
Test name
Test status
Simulation time 40264448 ps
CPU time 0.85 seconds
Started Jul 25 05:59:02 PM PDT 24
Finished Jul 25 05:59:03 PM PDT 24
Peak memory 206264 kb
Host smart-202913ba-11f5-4845-aec7-061f0d56676d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608914924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2608914924
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1829741677
Short name T1102
Test name
Test status
Simulation time 39149410 ps
CPU time 0.92 seconds
Started Jul 25 05:59:02 PM PDT 24
Finished Jul 25 05:59:03 PM PDT 24
Peak memory 206444 kb
Host smart-5d5c4733-5cb4-40b0-8897-c28dee78d11d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829741677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1829741677
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3739241044
Short name T1016
Test name
Test status
Simulation time 32656160 ps
CPU time 0.77 seconds
Started Jul 25 05:59:14 PM PDT 24
Finished Jul 25 05:59:15 PM PDT 24
Peak memory 206240 kb
Host smart-824719c8-85e3-4bd5-ac0f-5af4ac6e9d58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739241044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3739241044
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2240765142
Short name T1035
Test name
Test status
Simulation time 36958949 ps
CPU time 1.64 seconds
Started Jul 25 05:58:47 PM PDT 24
Finished Jul 25 05:58:49 PM PDT 24
Peak memory 206448 kb
Host smart-62a00740-dc11-403f-99e7-025d79c85dc4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240765142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2240765142
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4039005678
Short name T1052
Test name
Test status
Simulation time 195117853 ps
CPU time 3.42 seconds
Started Jul 25 05:58:45 PM PDT 24
Finished Jul 25 05:58:48 PM PDT 24
Peak memory 206388 kb
Host smart-74f000a8-dc78-4cf1-8c28-8c3cb2afa3f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039005678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.4039005678
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.263899488
Short name T1057
Test name
Test status
Simulation time 32112715 ps
CPU time 0.82 seconds
Started Jul 25 05:58:43 PM PDT 24
Finished Jul 25 05:58:44 PM PDT 24
Peak memory 206292 kb
Host smart-fb9bab58-d0a7-4ae1-b852-bb58ced3fca7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263899488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.263899488
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.104958318
Short name T1115
Test name
Test status
Simulation time 63376472 ps
CPU time 1.27 seconds
Started Jul 25 05:58:43 PM PDT 24
Finished Jul 25 05:58:44 PM PDT 24
Peak memory 214844 kb
Host smart-ccf8f6c6-34c6-4eb7-bd6c-04ba12fb3aad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104958318 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.104958318
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2977349095
Short name T245
Test name
Test status
Simulation time 72318831 ps
CPU time 0.86 seconds
Started Jul 25 05:58:41 PM PDT 24
Finished Jul 25 05:58:42 PM PDT 24
Peak memory 206456 kb
Host smart-7e4c2bb9-9df4-4931-b7d2-6ae39c400bef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977349095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2977349095
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1772354016
Short name T1075
Test name
Test status
Simulation time 48479065 ps
CPU time 0.93 seconds
Started Jul 25 05:58:43 PM PDT 24
Finished Jul 25 05:58:45 PM PDT 24
Peak memory 206312 kb
Host smart-69d8314e-5338-40cc-a78b-b69aaf773e2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772354016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1772354016
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.829139234
Short name T1024
Test name
Test status
Simulation time 50992331 ps
CPU time 1.1 seconds
Started Jul 25 05:58:43 PM PDT 24
Finished Jul 25 05:58:44 PM PDT 24
Peak memory 206572 kb
Host smart-b026286b-28da-44d0-9d54-d03c20d905e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829139234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.829139234
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2203575367
Short name T1011
Test name
Test status
Simulation time 91477711 ps
CPU time 1.72 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:44 PM PDT 24
Peak memory 214876 kb
Host smart-b113d2a2-158e-4851-ab73-728ac5debe32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203575367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2203575367
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2073293521
Short name T268
Test name
Test status
Simulation time 98977033 ps
CPU time 1.61 seconds
Started Jul 25 05:58:44 PM PDT 24
Finished Jul 25 05:58:46 PM PDT 24
Peak memory 206720 kb
Host smart-15259f84-c221-47c4-b7ab-30c44baf6b42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073293521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2073293521
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3068481508
Short name T1004
Test name
Test status
Simulation time 14161031 ps
CPU time 0.89 seconds
Started Jul 25 05:59:16 PM PDT 24
Finished Jul 25 05:59:17 PM PDT 24
Peak memory 206416 kb
Host smart-73eeae62-2d7a-4025-9f41-84de63ed6175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068481508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3068481508
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3779731643
Short name T997
Test name
Test status
Simulation time 19582203 ps
CPU time 0.82 seconds
Started Jul 25 05:59:14 PM PDT 24
Finished Jul 25 05:59:15 PM PDT 24
Peak memory 206220 kb
Host smart-47b2311a-edde-46da-9112-87004756cb22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779731643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3779731643
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1614438192
Short name T1006
Test name
Test status
Simulation time 16414468 ps
CPU time 0.95 seconds
Started Jul 25 05:59:16 PM PDT 24
Finished Jul 25 05:59:17 PM PDT 24
Peak memory 206396 kb
Host smart-0313821e-66eb-4b2d-bd10-33b58727ad60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614438192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1614438192
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.275505032
Short name T1081
Test name
Test status
Simulation time 36464115 ps
CPU time 0.82 seconds
Started Jul 25 05:59:31 PM PDT 24
Finished Jul 25 05:59:32 PM PDT 24
Peak memory 206268 kb
Host smart-5220693c-6240-4f41-918f-13b0fafc7560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275505032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.275505032
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3161265825
Short name T1019
Test name
Test status
Simulation time 13648263 ps
CPU time 0.87 seconds
Started Jul 25 05:59:14 PM PDT 24
Finished Jul 25 05:59:15 PM PDT 24
Peak memory 206500 kb
Host smart-1c16a0e2-afa9-47fd-8893-258a60d39df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161265825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3161265825
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1097896563
Short name T1087
Test name
Test status
Simulation time 32930799 ps
CPU time 0.8 seconds
Started Jul 25 05:59:14 PM PDT 24
Finished Jul 25 05:59:15 PM PDT 24
Peak memory 206276 kb
Host smart-4db5b5d5-3e82-41cf-a14b-2492d37e6556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097896563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1097896563
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3640112883
Short name T1001
Test name
Test status
Simulation time 31022019 ps
CPU time 0.79 seconds
Started Jul 25 05:59:19 PM PDT 24
Finished Jul 25 05:59:20 PM PDT 24
Peak memory 206288 kb
Host smart-3ce2ea98-8dac-479b-8b52-adbd24fd0127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640112883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3640112883
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.40518735
Short name T1030
Test name
Test status
Simulation time 45568431 ps
CPU time 0.93 seconds
Started Jul 25 05:59:14 PM PDT 24
Finished Jul 25 05:59:15 PM PDT 24
Peak memory 206460 kb
Host smart-1a5a8f5a-d9aa-47ed-adac-d0b4a2137708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40518735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.40518735
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2452400862
Short name T1026
Test name
Test status
Simulation time 56147575 ps
CPU time 0.91 seconds
Started Jul 25 05:59:14 PM PDT 24
Finished Jul 25 05:59:15 PM PDT 24
Peak memory 206424 kb
Host smart-619f5a6c-2cbe-4ee8-ba20-fee0e40cda87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452400862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2452400862
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2639260741
Short name T996
Test name
Test status
Simulation time 41584776 ps
CPU time 0.81 seconds
Started Jul 25 05:59:15 PM PDT 24
Finished Jul 25 05:59:16 PM PDT 24
Peak memory 206576 kb
Host smart-88d78290-59c9-431b-bc37-ac91e85f4a2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639260741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2639260741
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1383450004
Short name T1094
Test name
Test status
Simulation time 111975883 ps
CPU time 1.7 seconds
Started Jul 25 05:58:45 PM PDT 24
Finished Jul 25 05:58:47 PM PDT 24
Peak memory 214776 kb
Host smart-7cc8ec20-495d-4427-a77e-40c25a053d9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383450004 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1383450004
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1487630079
Short name T1060
Test name
Test status
Simulation time 48685981 ps
CPU time 0.86 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:43 PM PDT 24
Peak memory 206456 kb
Host smart-3f0523f1-2a95-42af-9a68-8f00bf223668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487630079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1487630079
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2940305612
Short name T1068
Test name
Test status
Simulation time 11071481 ps
CPU time 0.85 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:44 PM PDT 24
Peak memory 206460 kb
Host smart-ad292340-3a66-427c-b2b4-efc0954e0bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940305612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2940305612
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1181643361
Short name T1095
Test name
Test status
Simulation time 21968378 ps
CPU time 1.19 seconds
Started Jul 25 05:58:42 PM PDT 24
Finished Jul 25 05:58:44 PM PDT 24
Peak memory 206636 kb
Host smart-547c70d9-04d8-4425-9210-05a08e2f1534
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181643361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1181643361
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3136702544
Short name T1055
Test name
Test status
Simulation time 349970171 ps
CPU time 3.24 seconds
Started Jul 25 05:58:43 PM PDT 24
Finished Jul 25 05:58:47 PM PDT 24
Peak memory 214788 kb
Host smart-5a606061-354a-427c-b983-0c3b2aeec178
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136702544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3136702544
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2917476223
Short name T213
Test name
Test status
Simulation time 185141183 ps
CPU time 1.8 seconds
Started Jul 25 05:58:43 PM PDT 24
Finished Jul 25 05:58:45 PM PDT 24
Peak memory 206608 kb
Host smart-6fb09020-827a-432e-8a7b-7a2c99997d18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917476223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2917476223
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1813978772
Short name T998
Test name
Test status
Simulation time 18332442 ps
CPU time 1.07 seconds
Started Jul 25 05:58:51 PM PDT 24
Finished Jul 25 05:58:52 PM PDT 24
Peak memory 206664 kb
Host smart-2eb37b84-677f-4dc5-ad9f-523df3de937f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813978772 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1813978772
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3679422703
Short name T244
Test name
Test status
Simulation time 13940975 ps
CPU time 0.87 seconds
Started Jul 25 05:58:48 PM PDT 24
Finished Jul 25 05:58:49 PM PDT 24
Peak memory 206460 kb
Host smart-e376c3cd-ef76-4668-a06d-d466313f78eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679422703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3679422703
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.506834725
Short name T989
Test name
Test status
Simulation time 14806332 ps
CPU time 0.82 seconds
Started Jul 25 05:58:51 PM PDT 24
Finished Jul 25 05:58:52 PM PDT 24
Peak memory 206464 kb
Host smart-64070112-3494-4146-9537-faaee5a52ca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506834725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.506834725
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2605937620
Short name T1085
Test name
Test status
Simulation time 240698877 ps
CPU time 1.08 seconds
Started Jul 25 05:58:51 PM PDT 24
Finished Jul 25 05:58:52 PM PDT 24
Peak memory 206640 kb
Host smart-dbbb69d2-4608-437c-a59a-36b8f77f4ecb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605937620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2605937620
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3002625196
Short name T1070
Test name
Test status
Simulation time 170391324 ps
CPU time 3.76 seconds
Started Jul 25 05:58:50 PM PDT 24
Finished Jul 25 05:58:54 PM PDT 24
Peak memory 214888 kb
Host smart-85766225-3725-4b66-b1d1-a4693c488bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002625196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3002625196
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.799360879
Short name T1028
Test name
Test status
Simulation time 168160034 ps
CPU time 1.59 seconds
Started Jul 25 05:58:52 PM PDT 24
Finished Jul 25 05:58:54 PM PDT 24
Peak memory 206580 kb
Host smart-da3357ba-1307-4055-8a31-12e66fa38be1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799360879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.799360879
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2451238217
Short name T1082
Test name
Test status
Simulation time 115662873 ps
CPU time 1.21 seconds
Started Jul 25 05:58:50 PM PDT 24
Finished Jul 25 05:58:52 PM PDT 24
Peak memory 214864 kb
Host smart-c6b80d81-85be-47c6-b7a5-f73dff64bd58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451238217 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2451238217
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.676218194
Short name T255
Test name
Test status
Simulation time 34292915 ps
CPU time 0.82 seconds
Started Jul 25 05:58:54 PM PDT 24
Finished Jul 25 05:58:55 PM PDT 24
Peak memory 206264 kb
Host smart-c18e0da3-13d2-4e74-b028-7e0226f29dd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676218194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.676218194
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2728726756
Short name T1074
Test name
Test status
Simulation time 56000898 ps
CPU time 0.83 seconds
Started Jul 25 05:58:48 PM PDT 24
Finished Jul 25 05:58:49 PM PDT 24
Peak memory 206292 kb
Host smart-69206cb3-aba0-481c-95cd-59cda9ee6389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728726756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2728726756
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3609822415
Short name T1040
Test name
Test status
Simulation time 40737948 ps
CPU time 1.58 seconds
Started Jul 25 05:58:51 PM PDT 24
Finished Jul 25 05:58:52 PM PDT 24
Peak memory 206672 kb
Host smart-bd791c67-2d74-4e88-986a-1f4fba89aa71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609822415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3609822415
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1814793201
Short name T1080
Test name
Test status
Simulation time 40156243 ps
CPU time 1.72 seconds
Started Jul 25 05:58:55 PM PDT 24
Finished Jul 25 05:58:57 PM PDT 24
Peak memory 214908 kb
Host smart-edbdf0fa-0430-4c35-9fe6-ebb946446f3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814793201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1814793201
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2783516742
Short name T273
Test name
Test status
Simulation time 333578514 ps
CPU time 2.52 seconds
Started Jul 25 05:58:50 PM PDT 24
Finished Jul 25 05:58:52 PM PDT 24
Peak memory 206696 kb
Host smart-b3f34a97-5582-4e83-944b-a209149d09f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783516742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2783516742
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3262082550
Short name T1047
Test name
Test status
Simulation time 80613324 ps
CPU time 1.12 seconds
Started Jul 25 05:58:49 PM PDT 24
Finished Jul 25 05:58:50 PM PDT 24
Peak memory 214888 kb
Host smart-4f7350e5-9433-45a9-a3ba-afb81a438770
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262082550 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3262082550
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.116753622
Short name T1100
Test name
Test status
Simulation time 20601713 ps
CPU time 0.84 seconds
Started Jul 25 05:58:51 PM PDT 24
Finished Jul 25 05:58:52 PM PDT 24
Peak memory 206488 kb
Host smart-b5d6913f-1bf3-410e-a0e9-e730b4dc8f5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116753622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.116753622
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2934211994
Short name T1058
Test name
Test status
Simulation time 15327811 ps
CPU time 0.9 seconds
Started Jul 25 05:58:58 PM PDT 24
Finished Jul 25 05:58:59 PM PDT 24
Peak memory 206452 kb
Host smart-e3bed0bf-032f-4d99-b1e7-d332ed3098b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934211994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2934211994
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3132886835
Short name T1078
Test name
Test status
Simulation time 42004376 ps
CPU time 1.15 seconds
Started Jul 25 05:58:51 PM PDT 24
Finished Jul 25 05:58:52 PM PDT 24
Peak memory 206584 kb
Host smart-a8666ae4-a3e3-4f28-ad1b-76230fd66331
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132886835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3132886835
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3987882516
Short name T1021
Test name
Test status
Simulation time 525751698 ps
CPU time 3.57 seconds
Started Jul 25 05:58:52 PM PDT 24
Finished Jul 25 05:58:56 PM PDT 24
Peak memory 215032 kb
Host smart-ab8eef56-19cc-4d9c-946c-02d1a90f5767
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987882516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3987882516
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3442371731
Short name T1097
Test name
Test status
Simulation time 59357196 ps
CPU time 1.61 seconds
Started Jul 25 05:58:50 PM PDT 24
Finished Jul 25 05:58:52 PM PDT 24
Peak memory 206632 kb
Host smart-82b9776c-d057-40cf-a6f3-abb47cfee4c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442371731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3442371731
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2463440877
Short name T1050
Test name
Test status
Simulation time 86815140 ps
CPU time 1.31 seconds
Started Jul 25 05:58:52 PM PDT 24
Finished Jul 25 05:58:53 PM PDT 24
Peak memory 214904 kb
Host smart-4da1ac46-269e-43eb-ac7c-fcc846636642
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463440877 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2463440877
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1658186037
Short name T1096
Test name
Test status
Simulation time 141823708 ps
CPU time 0.89 seconds
Started Jul 25 05:58:51 PM PDT 24
Finished Jul 25 05:58:52 PM PDT 24
Peak memory 206456 kb
Host smart-e093e9e0-492c-42bf-b5ca-cdbb2bf1efce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658186037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1658186037
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.4284301098
Short name T1008
Test name
Test status
Simulation time 48744941 ps
CPU time 0.88 seconds
Started Jul 25 05:58:51 PM PDT 24
Finished Jul 25 05:58:52 PM PDT 24
Peak memory 206488 kb
Host smart-96bed33a-1e95-48b1-83f3-fceaca44d04b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284301098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4284301098
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3724320355
Short name T1062
Test name
Test status
Simulation time 24850990 ps
CPU time 1.16 seconds
Started Jul 25 05:58:50 PM PDT 24
Finished Jul 25 05:58:51 PM PDT 24
Peak memory 206680 kb
Host smart-0beb83b8-644d-4c2c-bfbb-7cf058eb0011
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724320355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3724320355
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.851527535
Short name T999
Test name
Test status
Simulation time 110763169 ps
CPU time 4.11 seconds
Started Jul 25 05:58:51 PM PDT 24
Finished Jul 25 05:58:55 PM PDT 24
Peak memory 214840 kb
Host smart-1137faa2-95a6-41a9-b004-8513d7221c7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851527535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.851527535
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/default/0.edn_alert.3479739453
Short name T715
Test name
Test status
Simulation time 30520516 ps
CPU time 1.32 seconds
Started Jul 25 06:03:47 PM PDT 24
Finished Jul 25 06:03:48 PM PDT 24
Peak memory 219216 kb
Host smart-211052fb-8cd5-439f-8288-2ddb29374d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479739453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3479739453
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2322937595
Short name T720
Test name
Test status
Simulation time 23719753 ps
CPU time 1.08 seconds
Started Jul 25 06:03:51 PM PDT 24
Finished Jul 25 06:03:52 PM PDT 24
Peak memory 214812 kb
Host smart-f0fecb38-eaa1-4409-aefa-d3ce941206d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322937595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2322937595
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.4251973019
Short name T210
Test name
Test status
Simulation time 23240049 ps
CPU time 0.87 seconds
Started Jul 25 06:03:43 PM PDT 24
Finished Jul 25 06:03:44 PM PDT 24
Peak memory 215392 kb
Host smart-52af8ab3-a34e-4601-8320-857c35b3554f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251973019 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.4251973019
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1650847112
Short name T931
Test name
Test status
Simulation time 43423992 ps
CPU time 1.27 seconds
Started Jul 25 06:03:42 PM PDT 24
Finished Jul 25 06:03:43 PM PDT 24
Peak memory 216916 kb
Host smart-564028b1-5ea2-4193-991e-e0772a743690
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650847112 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1650847112
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2078720698
Short name T515
Test name
Test status
Simulation time 27511626 ps
CPU time 0.86 seconds
Started Jul 25 06:03:43 PM PDT 24
Finished Jul 25 06:03:44 PM PDT 24
Peak memory 218336 kb
Host smart-4730cc70-e4fe-40d1-9a12-f0e7134f8c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078720698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2078720698
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1307397476
Short name T455
Test name
Test status
Simulation time 43168826 ps
CPU time 1.38 seconds
Started Jul 25 06:03:42 PM PDT 24
Finished Jul 25 06:03:43 PM PDT 24
Peak memory 218192 kb
Host smart-92a341ee-dcae-4adf-a02a-c2de523a2449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307397476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1307397476
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3003785251
Short name T88
Test name
Test status
Simulation time 44542165 ps
CPU time 0.83 seconds
Started Jul 25 06:03:40 PM PDT 24
Finished Jul 25 06:03:41 PM PDT 24
Peak memory 215540 kb
Host smart-2a3c1cf2-77b6-4163-a75d-39236a6c681b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003785251 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3003785251
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.691677608
Short name T278
Test name
Test status
Simulation time 18337290 ps
CPU time 0.98 seconds
Started Jul 25 06:03:42 PM PDT 24
Finished Jul 25 06:03:43 PM PDT 24
Peak memory 206996 kb
Host smart-ac7d306a-7830-4d01-add3-de3e0bf47edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691677608 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.691677608
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.819832255
Short name T438
Test name
Test status
Simulation time 16300647 ps
CPU time 0.99 seconds
Started Jul 25 06:03:42 PM PDT 24
Finished Jul 25 06:03:44 PM PDT 24
Peak memory 215160 kb
Host smart-ae1fe167-fce9-4a09-adaa-cab1c726e341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819832255 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.819832255
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3458795961
Short name T780
Test name
Test status
Simulation time 24767840195 ps
CPU time 630.84 seconds
Started Jul 25 06:03:43 PM PDT 24
Finished Jul 25 06:14:14 PM PDT 24
Peak memory 223760 kb
Host smart-81254886-50b1-4eaa-9324-5759cfb0c014
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458795961 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3458795961
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1193925017
Short name T461
Test name
Test status
Simulation time 92947734 ps
CPU time 1.13 seconds
Started Jul 25 06:03:43 PM PDT 24
Finished Jul 25 06:03:44 PM PDT 24
Peak memory 219484 kb
Host smart-f91a111b-fb3c-479f-b2e7-beb888ff4cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193925017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1193925017
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.944061105
Short name T569
Test name
Test status
Simulation time 42477384 ps
CPU time 0.85 seconds
Started Jul 25 06:03:43 PM PDT 24
Finished Jul 25 06:03:44 PM PDT 24
Peak memory 214752 kb
Host smart-7260f22c-0fcd-493e-b917-856e7b3b07e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944061105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.944061105
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1000170243
Short name T907
Test name
Test status
Simulation time 34213241 ps
CPU time 1.21 seconds
Started Jul 25 06:03:45 PM PDT 24
Finished Jul 25 06:03:46 PM PDT 24
Peak memory 216652 kb
Host smart-2947cbcb-474a-44a8-8caa-2c89368c0096
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000170243 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1000170243
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1792079807
Short name T41
Test name
Test status
Simulation time 27194303 ps
CPU time 1.14 seconds
Started Jul 25 06:03:41 PM PDT 24
Finished Jul 25 06:03:42 PM PDT 24
Peak memory 223928 kb
Host smart-566f4a21-673e-4bb6-b51a-b17d71f9ece2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792079807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1792079807
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.1808260296
Short name T612
Test name
Test status
Simulation time 37260988 ps
CPU time 1.23 seconds
Started Jul 25 06:03:43 PM PDT 24
Finished Jul 25 06:03:44 PM PDT 24
Peak memory 217180 kb
Host smart-d47136be-f903-42f2-ac5e-be9890e780fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808260296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1808260296
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2305286022
Short name T966
Test name
Test status
Simulation time 28196858 ps
CPU time 0.84 seconds
Started Jul 25 06:03:40 PM PDT 24
Finished Jul 25 06:03:41 PM PDT 24
Peak memory 215500 kb
Host smart-bf2605b9-e82a-4d2d-848c-ac4580d00ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305286022 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2305286022
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_smoke.3709360165
Short name T758
Test name
Test status
Simulation time 19300667 ps
CPU time 1 seconds
Started Jul 25 06:03:46 PM PDT 24
Finished Jul 25 06:03:47 PM PDT 24
Peak memory 215176 kb
Host smart-68fea7f6-050e-440a-8015-1365971b5f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709360165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3709360165
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1352553114
Short name T871
Test name
Test status
Simulation time 476801536 ps
CPU time 3.65 seconds
Started Jul 25 06:03:43 PM PDT 24
Finished Jul 25 06:03:47 PM PDT 24
Peak memory 216940 kb
Host smart-3547af7d-38fe-4dd6-9dab-5bae87aa4c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352553114 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1352553114
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3002067521
Short name T224
Test name
Test status
Simulation time 60692338193 ps
CPU time 702.36 seconds
Started Jul 25 06:03:46 PM PDT 24
Finished Jul 25 06:15:28 PM PDT 24
Peak memory 218696 kb
Host smart-f04b459e-a153-461d-9902-090baff30d59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002067521 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3002067521
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1086456521
Short name T559
Test name
Test status
Simulation time 31013987 ps
CPU time 1.31 seconds
Started Jul 25 06:04:02 PM PDT 24
Finished Jul 25 06:04:04 PM PDT 24
Peak memory 219784 kb
Host smart-6dc30e5c-ec0a-4b62-a3a8-1f4ff6a4327f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086456521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1086456521
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_err.3129518752
Short name T171
Test name
Test status
Simulation time 82550574 ps
CPU time 1.06 seconds
Started Jul 25 06:04:05 PM PDT 24
Finished Jul 25 06:04:07 PM PDT 24
Peak memory 219648 kb
Host smart-53fb7f2c-1922-4eb7-a6f8-f030af59dd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129518752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3129518752
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.1913459373
Short name T89
Test name
Test status
Simulation time 27745773 ps
CPU time 0.85 seconds
Started Jul 25 06:04:08 PM PDT 24
Finished Jul 25 06:04:09 PM PDT 24
Peak memory 215548 kb
Host smart-36dba211-8aae-49a2-a790-165363834347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913459373 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1913459373
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2884174140
Short name T432
Test name
Test status
Simulation time 27405912 ps
CPU time 0.98 seconds
Started Jul 25 06:04:09 PM PDT 24
Finished Jul 25 06:04:10 PM PDT 24
Peak memory 215272 kb
Host smart-9fe27bfd-aab4-4924-ae78-8f3fa7472965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884174140 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2884174140
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3996924802
Short name T626
Test name
Test status
Simulation time 306920967 ps
CPU time 2.22 seconds
Started Jul 25 06:04:00 PM PDT 24
Finished Jul 25 06:04:02 PM PDT 24
Peak memory 217164 kb
Host smart-c1af0b21-859f-4f3d-8ff3-1641f3c75590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996924802 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3996924802
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.41655524
Short name T483
Test name
Test status
Simulation time 52157337915 ps
CPU time 643.99 seconds
Started Jul 25 06:04:19 PM PDT 24
Finished Jul 25 06:15:04 PM PDT 24
Peak memory 219652 kb
Host smart-8e35b68f-c356-4c1f-b364-44a1b33b2cab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41655524 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.41655524
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.edn_alert.3580355879
Short name T693
Test name
Test status
Simulation time 40597709 ps
CPU time 1.14 seconds
Started Jul 25 06:05:46 PM PDT 24
Finished Jul 25 06:05:47 PM PDT 24
Peak memory 218600 kb
Host smart-fce5f0e0-7acd-44af-aaf2-e39782246860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580355879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.3580355879
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.1976010359
Short name T363
Test name
Test status
Simulation time 20639893 ps
CPU time 1.12 seconds
Started Jul 25 06:05:46 PM PDT 24
Finished Jul 25 06:05:48 PM PDT 24
Peak memory 217256 kb
Host smart-b70857b0-650a-4c4e-b717-7ef364788c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976010359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1976010359
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.515115748
Short name T832
Test name
Test status
Simulation time 28896632 ps
CPU time 1.3 seconds
Started Jul 25 06:05:45 PM PDT 24
Finished Jul 25 06:05:47 PM PDT 24
Peak memory 219788 kb
Host smart-fa2e62f4-6b65-49ce-9d44-a43b62a3ae77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515115748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.515115748
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2282126392
Short name T419
Test name
Test status
Simulation time 320320697 ps
CPU time 2.1 seconds
Started Jul 25 06:05:44 PM PDT 24
Finished Jul 25 06:05:47 PM PDT 24
Peak memory 219056 kb
Host smart-19da4229-5cb4-4da7-a23d-c19de83bc388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282126392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2282126392
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.1375795626
Short name T211
Test name
Test status
Simulation time 76460409 ps
CPU time 1.2 seconds
Started Jul 25 06:05:47 PM PDT 24
Finished Jul 25 06:05:48 PM PDT 24
Peak memory 219744 kb
Host smart-48e2ea98-46c6-4adc-be00-1a0c2b1b723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375795626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1375795626
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/105.edn_alert.863167425
Short name T155
Test name
Test status
Simulation time 75664081 ps
CPU time 1.29 seconds
Started Jul 25 06:05:53 PM PDT 24
Finished Jul 25 06:05:55 PM PDT 24
Peak memory 219756 kb
Host smart-d3841a94-4cd9-4692-a0b7-111fa935c3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863167425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.863167425
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.2653711188
Short name T451
Test name
Test status
Simulation time 58342491 ps
CPU time 1.45 seconds
Started Jul 25 06:05:47 PM PDT 24
Finished Jul 25 06:05:48 PM PDT 24
Peak memory 218348 kb
Host smart-282bc361-dffd-4795-818a-1eb9d052f920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653711188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2653711188
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2371226069
Short name T521
Test name
Test status
Simulation time 26224281 ps
CPU time 1.28 seconds
Started Jul 25 06:05:45 PM PDT 24
Finished Jul 25 06:05:47 PM PDT 24
Peak memory 219600 kb
Host smart-d01282c3-edcd-4dad-8f5e-71a39f71620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371226069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2371226069
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.2547745217
Short name T877
Test name
Test status
Simulation time 51738063 ps
CPU time 1.6 seconds
Started Jul 25 06:05:44 PM PDT 24
Finished Jul 25 06:05:46 PM PDT 24
Peak memory 219260 kb
Host smart-77f6440b-8e17-44ce-936f-fafe90b8d526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547745217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2547745217
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.53837996
Short name T156
Test name
Test status
Simulation time 81420464 ps
CPU time 1.21 seconds
Started Jul 25 06:05:45 PM PDT 24
Finished Jul 25 06:05:47 PM PDT 24
Peak memory 219360 kb
Host smart-52e36e0b-4861-42eb-9b55-67863280863c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53837996 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.53837996
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/108.edn_alert.2232190730
Short name T773
Test name
Test status
Simulation time 57483587 ps
CPU time 1.28 seconds
Started Jul 25 06:05:53 PM PDT 24
Finished Jul 25 06:05:55 PM PDT 24
Peak memory 219932 kb
Host smart-33c6312a-b8cb-4ce9-918e-fe7433855e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232190730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2232190730
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.4084523013
Short name T536
Test name
Test status
Simulation time 37330168 ps
CPU time 1.46 seconds
Started Jul 25 06:05:47 PM PDT 24
Finished Jul 25 06:05:48 PM PDT 24
Peak memory 219808 kb
Host smart-2d0a6e15-d558-4897-9ab8-f00fe71a144b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084523013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.4084523013
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.154470773
Short name T606
Test name
Test status
Simulation time 159906245 ps
CPU time 1.14 seconds
Started Jul 25 06:05:45 PM PDT 24
Finished Jul 25 06:05:46 PM PDT 24
Peak memory 219560 kb
Host smart-9145e444-2156-4f7c-bc68-7f0135ef7f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154470773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.154470773
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.428100765
Short name T401
Test name
Test status
Simulation time 52296014 ps
CPU time 1.52 seconds
Started Jul 25 06:05:44 PM PDT 24
Finished Jul 25 06:05:45 PM PDT 24
Peak memory 218228 kb
Host smart-3aa9059a-2645-4c52-999b-46ed62598371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428100765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.428100765
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.3370272858
Short name T399
Test name
Test status
Simulation time 67385833 ps
CPU time 1.18 seconds
Started Jul 25 06:04:04 PM PDT 24
Finished Jul 25 06:04:06 PM PDT 24
Peak memory 220332 kb
Host smart-fa014009-9ed1-47cd-bedf-50dbe4d2ca3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370272858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3370272858
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1038745696
Short name T876
Test name
Test status
Simulation time 22429420 ps
CPU time 0.9 seconds
Started Jul 25 06:04:01 PM PDT 24
Finished Jul 25 06:04:02 PM PDT 24
Peak memory 206728 kb
Host smart-d10d4828-1f5b-486d-ad9e-d9626b6e36b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038745696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1038745696
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3448927068
Short name T352
Test name
Test status
Simulation time 34414418 ps
CPU time 0.81 seconds
Started Jul 25 06:04:07 PM PDT 24
Finished Jul 25 06:04:08 PM PDT 24
Peak memory 215812 kb
Host smart-86729915-f778-47c4-842a-ed237c5b64b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448927068 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3448927068
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.875423620
Short name T74
Test name
Test status
Simulation time 39748350 ps
CPU time 1.1 seconds
Started Jul 25 06:04:05 PM PDT 24
Finished Jul 25 06:04:06 PM PDT 24
Peak memory 218376 kb
Host smart-275145d3-89ef-4142-a5e9-e2cec9489bbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875423620 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.875423620
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1095974582
Short name T955
Test name
Test status
Simulation time 39175708 ps
CPU time 0.89 seconds
Started Jul 25 06:04:08 PM PDT 24
Finished Jul 25 06:04:09 PM PDT 24
Peak memory 218412 kb
Host smart-79c4ae37-b202-442d-ae24-189c0e95246a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095974582 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1095974582
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.4041130857
Short name T888
Test name
Test status
Simulation time 44608378 ps
CPU time 1.96 seconds
Started Jul 25 06:04:03 PM PDT 24
Finished Jul 25 06:04:05 PM PDT 24
Peak memory 218416 kb
Host smart-108b95f0-1f22-46f8-91b1-58994f17f24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041130857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.4041130857
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.61438045
Short name T604
Test name
Test status
Simulation time 17078165 ps
CPU time 0.99 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:12 PM PDT 24
Peak memory 215188 kb
Host smart-87b58819-7b49-40af-af20-80c4d7e4dec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61438045 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.61438045
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1678175166
Short name T668
Test name
Test status
Simulation time 70379968 ps
CPU time 1.82 seconds
Started Jul 25 06:04:00 PM PDT 24
Finished Jul 25 06:04:02 PM PDT 24
Peak memory 215188 kb
Host smart-de9186b1-9dac-4f94-87ca-98404da02ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678175166 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1678175166
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2839282349
Short name T547
Test name
Test status
Simulation time 47934557859 ps
CPU time 866.43 seconds
Started Jul 25 06:04:01 PM PDT 24
Finished Jul 25 06:18:28 PM PDT 24
Peak memory 223740 kb
Host smart-e5ad25de-184e-476f-8418-dbac462df196
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839282349 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2839282349
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.3601243935
Short name T868
Test name
Test status
Simulation time 41157194 ps
CPU time 1.14 seconds
Started Jul 25 06:05:54 PM PDT 24
Finished Jul 25 06:05:55 PM PDT 24
Peak memory 219676 kb
Host smart-23e6d436-f7bc-42d5-ac11-d5889d70dcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601243935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.3601243935
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.4193980587
Short name T986
Test name
Test status
Simulation time 28553826 ps
CPU time 1.26 seconds
Started Jul 25 06:05:54 PM PDT 24
Finished Jul 25 06:05:55 PM PDT 24
Peak memory 217256 kb
Host smart-9b0feb59-fa98-4112-97ea-5f8f434e5278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193980587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.4193980587
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.2974325509
Short name T958
Test name
Test status
Simulation time 27443058 ps
CPU time 1.2 seconds
Started Jul 25 06:05:48 PM PDT 24
Finished Jul 25 06:05:50 PM PDT 24
Peak memory 219672 kb
Host smart-bc4f7023-4dad-44f7-821b-bed99fba0904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974325509 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2974325509
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.1229826011
Short name T386
Test name
Test status
Simulation time 226035391 ps
CPU time 1.53 seconds
Started Jul 25 06:05:45 PM PDT 24
Finished Jul 25 06:05:47 PM PDT 24
Peak memory 219660 kb
Host smart-e3e2903e-be84-4333-8664-35e047ed8998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229826011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1229826011
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3907631984
Short name T96
Test name
Test status
Simulation time 78754678 ps
CPU time 1.19 seconds
Started Jul 25 06:05:49 PM PDT 24
Finished Jul 25 06:05:50 PM PDT 24
Peak memory 218348 kb
Host smart-d7eb3086-6e54-44d2-aa19-d71bf76a08c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907631984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3907631984
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/113.edn_alert.2093778015
Short name T973
Test name
Test status
Simulation time 23036977 ps
CPU time 1.27 seconds
Started Jul 25 06:06:02 PM PDT 24
Finished Jul 25 06:06:04 PM PDT 24
Peak memory 218524 kb
Host smart-b647b64d-597d-44a3-b1b5-e55cc50873fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093778015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2093778015
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.4138645444
Short name T413
Test name
Test status
Simulation time 38763980 ps
CPU time 1.42 seconds
Started Jul 25 06:05:53 PM PDT 24
Finished Jul 25 06:05:54 PM PDT 24
Peak memory 218416 kb
Host smart-6fa70de2-280b-477c-8a15-2e8f2d3c467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138645444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4138645444
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.1536870258
Short name T696
Test name
Test status
Simulation time 44235334 ps
CPU time 1.18 seconds
Started Jul 25 06:05:56 PM PDT 24
Finished Jul 25 06:05:58 PM PDT 24
Peak memory 218624 kb
Host smart-c89643ae-107b-4601-81c8-9323e0310347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536870258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.1536870258
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3179511747
Short name T756
Test name
Test status
Simulation time 70688223 ps
CPU time 1.4 seconds
Started Jul 25 06:05:52 PM PDT 24
Finished Jul 25 06:05:54 PM PDT 24
Peak memory 218632 kb
Host smart-3b4cb896-d1e0-4a79-a336-7cf231aafc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179511747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3179511747
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.2007130646
Short name T376
Test name
Test status
Simulation time 87872310 ps
CPU time 1.25 seconds
Started Jul 25 06:05:55 PM PDT 24
Finished Jul 25 06:05:56 PM PDT 24
Peak memory 219684 kb
Host smart-d7737ce5-e39e-4811-b539-e45a30cf4c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007130646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.2007130646
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.4107025711
Short name T364
Test name
Test status
Simulation time 76751012 ps
CPU time 1.18 seconds
Started Jul 25 06:05:53 PM PDT 24
Finished Jul 25 06:05:55 PM PDT 24
Peak memory 217312 kb
Host smart-14873ad5-7e01-4356-9d2e-2d0e007f80e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107025711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.4107025711
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1999919720
Short name T200
Test name
Test status
Simulation time 42913193 ps
CPU time 1.17 seconds
Started Jul 25 06:05:56 PM PDT 24
Finished Jul 25 06:05:57 PM PDT 24
Peak memory 219088 kb
Host smart-d433abeb-0b52-4da9-8d17-3e57965f29f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999919720 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1999919720
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.335720771
Short name T500
Test name
Test status
Simulation time 83604854 ps
CPU time 1.15 seconds
Started Jul 25 06:05:56 PM PDT 24
Finished Jul 25 06:05:57 PM PDT 24
Peak memory 217044 kb
Host smart-56ab4953-1a8b-49ea-9203-68efd6e8860c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335720771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.335720771
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.2647368371
Short name T809
Test name
Test status
Simulation time 87661569 ps
CPU time 1.21 seconds
Started Jul 25 06:05:52 PM PDT 24
Finished Jul 25 06:05:54 PM PDT 24
Peak memory 218288 kb
Host smart-0c45104c-6db0-46cc-9544-2c31c4c34c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647368371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.2647368371
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.3803148649
Short name T423
Test name
Test status
Simulation time 40250629 ps
CPU time 1.7 seconds
Started Jul 25 06:06:01 PM PDT 24
Finished Jul 25 06:06:03 PM PDT 24
Peak memory 217320 kb
Host smart-8e6a341c-e18c-47ae-80bb-0fa8583b8e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803148649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3803148649
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.1844936084
Short name T741
Test name
Test status
Simulation time 63027663 ps
CPU time 1.17 seconds
Started Jul 25 06:05:52 PM PDT 24
Finished Jul 25 06:05:54 PM PDT 24
Peak memory 218384 kb
Host smart-ad75c363-dc2c-45ca-8dbe-9b8a25f755d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844936084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1844936084
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.1848669717
Short name T331
Test name
Test status
Simulation time 137795769 ps
CPU time 1.15 seconds
Started Jul 25 06:05:52 PM PDT 24
Finished Jul 25 06:05:54 PM PDT 24
Peak memory 217348 kb
Host smart-72091b3a-a621-4dd6-8279-5aa9ef5fe1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848669717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1848669717
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.3465630843
Short name T711
Test name
Test status
Simulation time 79012899 ps
CPU time 1.12 seconds
Started Jul 25 06:05:50 PM PDT 24
Finished Jul 25 06:05:51 PM PDT 24
Peak memory 220276 kb
Host smart-fa6b5bf7-7215-4b8e-ad36-c34bdc504898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465630843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3465630843
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.2273369593
Short name T880
Test name
Test status
Simulation time 66070719 ps
CPU time 1.58 seconds
Started Jul 25 06:05:51 PM PDT 24
Finished Jul 25 06:05:53 PM PDT 24
Peak memory 218684 kb
Host smart-7615696e-4571-40b5-a70d-8a8a86d95201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273369593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2273369593
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.2701636274
Short name T449
Test name
Test status
Simulation time 16868661 ps
CPU time 0.96 seconds
Started Jul 25 06:04:01 PM PDT 24
Finished Jul 25 06:04:02 PM PDT 24
Peak memory 214840 kb
Host smart-a16774f3-2680-41d8-8ecf-3ffbac0a282a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701636274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2701636274
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1373105982
Short name T29
Test name
Test status
Simulation time 35019143 ps
CPU time 0.86 seconds
Started Jul 25 06:04:03 PM PDT 24
Finished Jul 25 06:04:04 PM PDT 24
Peak memory 215844 kb
Host smart-e345206e-17f5-4b04-aabe-e9e894b8705f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373105982 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1373105982
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.4010859162
Short name T678
Test name
Test status
Simulation time 120073067 ps
CPU time 1.12 seconds
Started Jul 25 06:04:05 PM PDT 24
Finished Jul 25 06:04:07 PM PDT 24
Peak memory 216892 kb
Host smart-6a5700fa-6aae-475c-be5a-7d52c8a72c4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010859162 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.4010859162
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2801719758
Short name T143
Test name
Test status
Simulation time 36845504 ps
CPU time 1.08 seconds
Started Jul 25 06:04:05 PM PDT 24
Finished Jul 25 06:04:06 PM PDT 24
Peak memory 220448 kb
Host smart-5df907a3-f0dc-41c7-a804-f34bbbb1c6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801719758 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2801719758
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3143266086
Short name T937
Test name
Test status
Simulation time 112935501 ps
CPU time 1.37 seconds
Started Jul 25 06:04:05 PM PDT 24
Finished Jul 25 06:04:07 PM PDT 24
Peak memory 220140 kb
Host smart-5b34a198-b982-4b66-84b5-d215e5748900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143266086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3143266086
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.2021984018
Short name T946
Test name
Test status
Simulation time 36941273 ps
CPU time 0.86 seconds
Started Jul 25 06:04:08 PM PDT 24
Finished Jul 25 06:04:09 PM PDT 24
Peak memory 215188 kb
Host smart-3317ff2f-4da6-4fb8-830e-a24da176b7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021984018 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2021984018
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1712033745
Short name T400
Test name
Test status
Simulation time 955808152 ps
CPU time 5.4 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:16 PM PDT 24
Peak memory 215236 kb
Host smart-bf10d60a-8115-4fed-813d-b15e9d0c3d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712033745 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1712033745
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3561770493
Short name T479
Test name
Test status
Simulation time 68191128341 ps
CPU time 1431.24 seconds
Started Jul 25 06:04:07 PM PDT 24
Finished Jul 25 06:27:59 PM PDT 24
Peak memory 222744 kb
Host smart-02275637-4e31-47cc-9d32-7b545b5ac855
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561770493 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3561770493
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.edn_alert.246569543
Short name T360
Test name
Test status
Simulation time 24065567 ps
CPU time 1.28 seconds
Started Jul 25 06:06:01 PM PDT 24
Finished Jul 25 06:06:03 PM PDT 24
Peak memory 219320 kb
Host smart-6e98d439-17f0-4320-a97b-a82dd631c64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246569543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.246569543
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.700796792
Short name T733
Test name
Test status
Simulation time 141404654 ps
CPU time 1.03 seconds
Started Jul 25 06:05:52 PM PDT 24
Finished Jul 25 06:05:54 PM PDT 24
Peak memory 217272 kb
Host smart-b2ac1be8-1a27-4c62-b35c-76280dc10862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700796792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.700796792
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.3016430728
Short name T748
Test name
Test status
Simulation time 238417335 ps
CPU time 1.26 seconds
Started Jul 25 06:05:53 PM PDT 24
Finished Jul 25 06:05:54 PM PDT 24
Peak memory 218472 kb
Host smart-9e475f8b-4489-4525-871a-d4f3b2391c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016430728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3016430728
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.2551325488
Short name T34
Test name
Test status
Simulation time 49606845 ps
CPU time 1.02 seconds
Started Jul 25 06:05:54 PM PDT 24
Finished Jul 25 06:05:55 PM PDT 24
Peak memory 217040 kb
Host smart-a987eb2a-757b-4d1c-b13b-2fb89e7bb348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551325488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2551325488
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2492276392
Short name T192
Test name
Test status
Simulation time 24452108 ps
CPU time 1.24 seconds
Started Jul 25 06:05:52 PM PDT 24
Finished Jul 25 06:05:53 PM PDT 24
Peak memory 219632 kb
Host smart-1f121320-17a8-4faf-b9e1-673bc8d11c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492276392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2492276392
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.653684213
Short name T560
Test name
Test status
Simulation time 111967262 ps
CPU time 1.27 seconds
Started Jul 25 06:05:56 PM PDT 24
Finished Jul 25 06:05:58 PM PDT 24
Peak memory 218196 kb
Host smart-bdc37b99-3a36-494d-ae8d-0f9e35e7b721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653684213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.653684213
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.3718111860
Short name T844
Test name
Test status
Simulation time 99809517 ps
CPU time 1.22 seconds
Started Jul 25 06:05:53 PM PDT 24
Finished Jul 25 06:05:54 PM PDT 24
Peak memory 218316 kb
Host smart-6e6e7375-bf2b-4f01-a8c2-931b2bfcc17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718111860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.3718111860
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.1610246123
Short name T833
Test name
Test status
Simulation time 34310488 ps
CPU time 1.43 seconds
Started Jul 25 06:05:54 PM PDT 24
Finished Jul 25 06:05:55 PM PDT 24
Peak memory 219784 kb
Host smart-cf0a3049-7572-4cbf-9ded-eeb908c4b415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610246123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1610246123
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.1442568892
Short name T388
Test name
Test status
Simulation time 31383656 ps
CPU time 1.28 seconds
Started Jul 25 06:05:51 PM PDT 24
Finished Jul 25 06:05:52 PM PDT 24
Peak memory 219408 kb
Host smart-024220d3-f562-4bce-926e-ade2c733ae68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442568892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1442568892
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.2281119942
Short name T415
Test name
Test status
Simulation time 44009015 ps
CPU time 1.78 seconds
Started Jul 25 06:05:55 PM PDT 24
Finished Jul 25 06:05:57 PM PDT 24
Peak memory 218412 kb
Host smart-2dccc002-8074-4734-b080-70266a2db8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281119942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2281119942
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.1616027738
Short name T261
Test name
Test status
Simulation time 28072509 ps
CPU time 1.3 seconds
Started Jul 25 06:05:52 PM PDT 24
Finished Jul 25 06:05:54 PM PDT 24
Peak memory 219324 kb
Host smart-7f854172-f50c-41d1-89a4-7a5598df44d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616027738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.1616027738
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/127.edn_alert.159048385
Short name T862
Test name
Test status
Simulation time 27022254 ps
CPU time 1.26 seconds
Started Jul 25 06:05:51 PM PDT 24
Finished Jul 25 06:05:53 PM PDT 24
Peak memory 219892 kb
Host smart-97981361-5f59-4fa7-95c9-f19a0ed57f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159048385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.159048385
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.2338533333
Short name T39
Test name
Test status
Simulation time 44433249 ps
CPU time 1.83 seconds
Started Jul 25 06:06:02 PM PDT 24
Finished Jul 25 06:06:04 PM PDT 24
Peak memory 217476 kb
Host smart-c94fda01-20ce-49bc-828a-370d59abab84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338533333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2338533333
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2211153106
Short name T502
Test name
Test status
Simulation time 55117297 ps
CPU time 1.26 seconds
Started Jul 25 06:05:51 PM PDT 24
Finished Jul 25 06:05:52 PM PDT 24
Peak memory 215616 kb
Host smart-e460f9f8-e864-420b-81f9-0937856b48ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211153106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2211153106
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.3047391822
Short name T621
Test name
Test status
Simulation time 124708828 ps
CPU time 3.09 seconds
Started Jul 25 06:05:53 PM PDT 24
Finished Jul 25 06:05:57 PM PDT 24
Peak memory 219960 kb
Host smart-76623ba7-057e-4398-86cd-8effde36eaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047391822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3047391822
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.2917776794
Short name T283
Test name
Test status
Simulation time 34314330 ps
CPU time 1.12 seconds
Started Jul 25 06:06:01 PM PDT 24
Finished Jul 25 06:06:02 PM PDT 24
Peak memory 219588 kb
Host smart-4a9f1657-782f-43c8-91d5-f6a0112b72da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917776794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.2917776794
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.2465867015
Short name T731
Test name
Test status
Simulation time 25912702 ps
CPU time 1.27 seconds
Started Jul 25 06:05:51 PM PDT 24
Finished Jul 25 06:05:52 PM PDT 24
Peak memory 218584 kb
Host smart-b800a35f-9628-4ab0-8cb1-20887b49193d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465867015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2465867015
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1429376025
Short name T209
Test name
Test status
Simulation time 92668644 ps
CPU time 1.24 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:12 PM PDT 24
Peak memory 219636 kb
Host smart-35e3de69-6f39-42a8-855d-dd588acbdf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429376025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1429376025
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.274369460
Short name T743
Test name
Test status
Simulation time 64390275 ps
CPU time 0.93 seconds
Started Jul 25 06:04:13 PM PDT 24
Finished Jul 25 06:04:14 PM PDT 24
Peak memory 214916 kb
Host smart-6118364b-6468-45e9-91fa-2ba0ea0d06dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274369460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.274369460
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3628805974
Short name T407
Test name
Test status
Simulation time 30662689 ps
CPU time 1.15 seconds
Started Jul 25 06:04:12 PM PDT 24
Finished Jul 25 06:04:14 PM PDT 24
Peak memory 218172 kb
Host smart-4b2bfec4-93ee-40c1-84e9-5ee03ad2c7b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628805974 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3628805974
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1056638521
Short name T161
Test name
Test status
Simulation time 23582957 ps
CPU time 1.01 seconds
Started Jul 25 06:04:12 PM PDT 24
Finished Jul 25 06:04:13 PM PDT 24
Peak memory 218292 kb
Host smart-9e09efbd-7476-47b7-b33f-5f8696186688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056638521 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1056638521
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1095899504
Short name T688
Test name
Test status
Simulation time 50937288 ps
CPU time 1.55 seconds
Started Jul 25 06:04:00 PM PDT 24
Finished Jul 25 06:04:02 PM PDT 24
Peak memory 218352 kb
Host smart-370594b1-9e28-4d20-84e6-28b82539ee1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095899504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1095899504
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3699579779
Short name T467
Test name
Test status
Simulation time 66843845 ps
CPU time 0.89 seconds
Started Jul 25 06:04:03 PM PDT 24
Finished Jul 25 06:04:04 PM PDT 24
Peak memory 215384 kb
Host smart-c9f62a3a-ed2d-4576-b3f3-6c1539803fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699579779 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3699579779
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1207672562
Short name T728
Test name
Test status
Simulation time 15505672 ps
CPU time 0.97 seconds
Started Jul 25 06:04:06 PM PDT 24
Finished Jul 25 06:04:07 PM PDT 24
Peak memory 215188 kb
Host smart-170d7bf7-5493-4116-9738-9c5de23c0eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207672562 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1207672562
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.160329785
Short name T379
Test name
Test status
Simulation time 611704105 ps
CPU time 4.6 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:16 PM PDT 24
Peak memory 215292 kb
Host smart-07db2518-0659-483e-b63f-819de75398bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160329785 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.160329785
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.4248258008
Short name T6
Test name
Test status
Simulation time 124167424672 ps
CPU time 721.85 seconds
Started Jul 25 06:04:08 PM PDT 24
Finished Jul 25 06:16:10 PM PDT 24
Peak memory 228424 kb
Host smart-b6173949-960a-4f78-9674-e7daf6949e7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248258008 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.4248258008
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.1679645595
Short name T212
Test name
Test status
Simulation time 161015042 ps
CPU time 1.34 seconds
Started Jul 25 06:06:02 PM PDT 24
Finished Jul 25 06:06:03 PM PDT 24
Peak memory 220624 kb
Host smart-5903c952-004e-44d4-bd54-c49a226ad8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679645595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.1679645595
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2901707986
Short name T510
Test name
Test status
Simulation time 34534581 ps
CPU time 1.31 seconds
Started Jul 25 06:06:00 PM PDT 24
Finished Jul 25 06:06:02 PM PDT 24
Peak memory 218416 kb
Host smart-cb7f9bb2-cb6d-437e-aeb2-2aa201787dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901707986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2901707986
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.951264028
Short name T558
Test name
Test status
Simulation time 112601008 ps
CPU time 1.18 seconds
Started Jul 25 06:06:08 PM PDT 24
Finished Jul 25 06:06:09 PM PDT 24
Peak memory 215628 kb
Host smart-90428b9b-3073-440c-90f7-c4eed12fdbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951264028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.951264028
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.2028698654
Short name T752
Test name
Test status
Simulation time 60488844 ps
CPU time 1.51 seconds
Started Jul 25 06:05:58 PM PDT 24
Finished Jul 25 06:06:00 PM PDT 24
Peak memory 218680 kb
Host smart-0cac1268-b9e0-4f70-80b2-0139341e7c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028698654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2028698654
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.3014542258
Short name T262
Test name
Test status
Simulation time 104399472 ps
CPU time 1.19 seconds
Started Jul 25 06:05:58 PM PDT 24
Finished Jul 25 06:06:00 PM PDT 24
Peak memory 218508 kb
Host smart-2a78b4b6-530a-44cb-9c91-2d4243dde19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014542258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3014542258
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.1365932662
Short name T812
Test name
Test status
Simulation time 52917133 ps
CPU time 1.33 seconds
Started Jul 25 06:05:59 PM PDT 24
Finished Jul 25 06:06:01 PM PDT 24
Peak memory 217336 kb
Host smart-aa9c898a-f363-4da7-80b5-abb8167865ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365932662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1365932662
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.369357798
Short name T1
Test name
Test status
Simulation time 44631148 ps
CPU time 1.2 seconds
Started Jul 25 06:06:00 PM PDT 24
Finished Jul 25 06:06:02 PM PDT 24
Peak memory 220044 kb
Host smart-41ac8a7d-27c8-4c28-ba61-2533799cb330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369357798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.369357798
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.1073451153
Short name T942
Test name
Test status
Simulation time 105222561 ps
CPU time 1.09 seconds
Started Jul 25 06:06:05 PM PDT 24
Finished Jul 25 06:06:06 PM PDT 24
Peak memory 217284 kb
Host smart-71648d28-3854-4c05-a582-de4d89f1d3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073451153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1073451153
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1082669477
Short name T613
Test name
Test status
Simulation time 48185513 ps
CPU time 1.28 seconds
Started Jul 25 06:06:00 PM PDT 24
Finished Jul 25 06:06:01 PM PDT 24
Peak memory 218388 kb
Host smart-0adf7558-3b76-4366-9733-bd976f27eca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082669477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1082669477
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3142069386
Short name T398
Test name
Test status
Simulation time 47195041 ps
CPU time 1.75 seconds
Started Jul 25 06:05:57 PM PDT 24
Finished Jul 25 06:05:59 PM PDT 24
Peak memory 218452 kb
Host smart-60dfc042-070b-4575-84cd-88213aff2dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142069386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3142069386
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.1645674673
Short name T154
Test name
Test status
Simulation time 26142834 ps
CPU time 1.28 seconds
Started Jul 25 06:06:02 PM PDT 24
Finished Jul 25 06:06:03 PM PDT 24
Peak memory 219468 kb
Host smart-5cd0f41e-198c-489e-903f-40eb7e66b592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645674673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.1645674673
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.2522442726
Short name T66
Test name
Test status
Simulation time 40289356 ps
CPU time 1.37 seconds
Started Jul 25 06:05:58 PM PDT 24
Finished Jul 25 06:06:00 PM PDT 24
Peak memory 217152 kb
Host smart-16904c94-87fd-41fe-9510-48be9d27e727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522442726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2522442726
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.2570048837
Short name T890
Test name
Test status
Simulation time 45660255 ps
CPU time 1.18 seconds
Started Jul 25 06:06:06 PM PDT 24
Finished Jul 25 06:06:07 PM PDT 24
Peak memory 220044 kb
Host smart-27746f55-78cb-4785-967a-d2cb167b3422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570048837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.2570048837
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.3966515470
Short name T444
Test name
Test status
Simulation time 41714534 ps
CPU time 1.61 seconds
Started Jul 25 06:05:56 PM PDT 24
Finished Jul 25 06:05:58 PM PDT 24
Peak memory 218252 kb
Host smart-8414681e-7e78-4cdc-8f07-325c31b72eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966515470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3966515470
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.1443144368
Short name T104
Test name
Test status
Simulation time 90833243 ps
CPU time 1.37 seconds
Started Jul 25 06:06:00 PM PDT 24
Finished Jul 25 06:06:02 PM PDT 24
Peak memory 215532 kb
Host smart-ef803049-5474-4b41-a159-94c2b86dfb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443144368 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.1443144368
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.3369867354
Short name T308
Test name
Test status
Simulation time 44777413 ps
CPU time 1.47 seconds
Started Jul 25 06:05:59 PM PDT 24
Finished Jul 25 06:06:00 PM PDT 24
Peak memory 218484 kb
Host smart-f716daff-a22f-4c53-b946-9478403ad5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369867354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3369867354
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2542437520
Short name T906
Test name
Test status
Simulation time 237753358 ps
CPU time 1.23 seconds
Started Jul 25 06:06:07 PM PDT 24
Finished Jul 25 06:06:09 PM PDT 24
Peak memory 220704 kb
Host smart-7c124e8a-b4f3-40e3-9da3-b179b1a1743d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542437520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2542437520
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.2102838372
Short name T487
Test name
Test status
Simulation time 53170437 ps
CPU time 1.75 seconds
Started Jul 25 06:06:00 PM PDT 24
Finished Jul 25 06:06:02 PM PDT 24
Peak memory 219736 kb
Host smart-91441e01-6cb8-47dd-bbb2-5b4c4b091e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102838372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2102838372
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.4222417667
Short name T552
Test name
Test status
Simulation time 90200819 ps
CPU time 1.15 seconds
Started Jul 25 06:04:13 PM PDT 24
Finished Jul 25 06:04:14 PM PDT 24
Peak memory 215544 kb
Host smart-f92f2045-ca79-4db8-8169-80ba6719ff0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222417667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.4222417667
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.93267173
Short name T852
Test name
Test status
Simulation time 17350299 ps
CPU time 1.02 seconds
Started Jul 25 06:04:11 PM PDT 24
Finished Jul 25 06:04:12 PM PDT 24
Peak memory 206692 kb
Host smart-bc90530e-c9e9-4e8a-b579-fc9f3e77ef16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93267173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.93267173
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3616691085
Short name T189
Test name
Test status
Simulation time 17856597 ps
CPU time 0.87 seconds
Started Jul 25 06:04:16 PM PDT 24
Finished Jul 25 06:04:17 PM PDT 24
Peak memory 216088 kb
Host smart-66bf685b-fbb4-4cc9-8dbf-df9153496b63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616691085 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3616691085
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.841597287
Short name T469
Test name
Test status
Simulation time 39969623 ps
CPU time 1.04 seconds
Started Jul 25 06:04:12 PM PDT 24
Finished Jul 25 06:04:13 PM PDT 24
Peak memory 216828 kb
Host smart-b10a7ef9-6957-4781-ab71-cca33d03fb0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841597287 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.841597287
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3130983561
Short name T416
Test name
Test status
Simulation time 69872131 ps
CPU time 1.03 seconds
Started Jul 25 06:04:14 PM PDT 24
Finished Jul 25 06:04:15 PM PDT 24
Peak memory 219496 kb
Host smart-93666ed6-c615-48c3-a733-64d84de94230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130983561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3130983561
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3064049037
Short name T921
Test name
Test status
Simulation time 77664019 ps
CPU time 1.27 seconds
Started Jul 25 06:04:16 PM PDT 24
Finished Jul 25 06:04:17 PM PDT 24
Peak memory 218432 kb
Host smart-5268687e-8a03-422a-bc47-7471ce8d3e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064049037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3064049037
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2210967983
Short name T929
Test name
Test status
Simulation time 21017771 ps
CPU time 1.11 seconds
Started Jul 25 06:04:14 PM PDT 24
Finished Jul 25 06:04:15 PM PDT 24
Peak memory 215348 kb
Host smart-ffdd8c59-9374-4124-bae9-789aa9043653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210967983 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2210967983
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2084037041
Short name T980
Test name
Test status
Simulation time 76148725 ps
CPU time 0.89 seconds
Started Jul 25 06:04:11 PM PDT 24
Finished Jul 25 06:04:13 PM PDT 24
Peak memory 215140 kb
Host smart-dd73c640-c702-49b1-a11e-9f8c8df7d0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084037041 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2084037041
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3087080693
Short name T468
Test name
Test status
Simulation time 51690701 ps
CPU time 1.54 seconds
Started Jul 25 06:04:13 PM PDT 24
Finished Jul 25 06:04:15 PM PDT 24
Peak memory 218352 kb
Host smart-7bfc6899-1a46-4e6c-a0f2-554395f5d856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087080693 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3087080693
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2639315414
Short name T217
Test name
Test status
Simulation time 24378423299 ps
CPU time 648.7 seconds
Started Jul 25 06:04:13 PM PDT 24
Finished Jul 25 06:15:02 PM PDT 24
Peak memory 223564 kb
Host smart-b5c50d8c-e3ff-46d2-a116-55e693a257d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639315414 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2639315414
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2663886111
Short name T905
Test name
Test status
Simulation time 40929350 ps
CPU time 1.08 seconds
Started Jul 25 06:05:59 PM PDT 24
Finished Jul 25 06:06:00 PM PDT 24
Peak memory 217356 kb
Host smart-f4cad089-1b62-40e7-810c-fedadc3718ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663886111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2663886111
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.3845092295
Short name T97
Test name
Test status
Simulation time 102822105 ps
CPU time 1.34 seconds
Started Jul 25 06:06:06 PM PDT 24
Finished Jul 25 06:06:07 PM PDT 24
Peak memory 215556 kb
Host smart-dbc99a34-72d8-4dd3-9cef-6c0330857c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845092295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.3845092295
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.156897502
Short name T265
Test name
Test status
Simulation time 100563225 ps
CPU time 1.22 seconds
Started Jul 25 06:06:05 PM PDT 24
Finished Jul 25 06:06:06 PM PDT 24
Peak memory 218372 kb
Host smart-a3252c4d-f9b5-41fc-a890-00d32239f944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156897502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.156897502
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.640522281
Short name T159
Test name
Test status
Simulation time 48987954 ps
CPU time 1.14 seconds
Started Jul 25 06:06:07 PM PDT 24
Finished Jul 25 06:06:08 PM PDT 24
Peak memory 219432 kb
Host smart-bdcefce3-d870-4a74-a1fa-fb8638283ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640522281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.640522281
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.3219921006
Short name T259
Test name
Test status
Simulation time 101819858 ps
CPU time 1.43 seconds
Started Jul 25 06:06:05 PM PDT 24
Finished Jul 25 06:06:06 PM PDT 24
Peak memory 217336 kb
Host smart-dc76b135-fc41-4cdb-9bc2-07da78ee5598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219921006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3219921006
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.176420939
Short name T48
Test name
Test status
Simulation time 94675273 ps
CPU time 1.16 seconds
Started Jul 25 06:06:06 PM PDT 24
Finished Jul 25 06:06:07 PM PDT 24
Peak memory 215700 kb
Host smart-cb5ab061-ea16-4176-abd7-9a4d18a07295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176420939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.176420939
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.38991431
Short name T620
Test name
Test status
Simulation time 48590039 ps
CPU time 1.53 seconds
Started Jul 25 06:06:07 PM PDT 24
Finished Jul 25 06:06:09 PM PDT 24
Peak memory 218292 kb
Host smart-9e3c739d-9ee7-4b51-88b3-b8b8fee967ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38991431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.38991431
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.2524511403
Short name T764
Test name
Test status
Simulation time 168577064 ps
CPU time 1.26 seconds
Started Jul 25 06:06:05 PM PDT 24
Finished Jul 25 06:06:06 PM PDT 24
Peak memory 219000 kb
Host smart-5fa9820d-3b77-480f-8ffb-656fd7970d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524511403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.2524511403
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.1107324726
Short name T235
Test name
Test status
Simulation time 76777008 ps
CPU time 1.16 seconds
Started Jul 25 06:06:06 PM PDT 24
Finished Jul 25 06:06:08 PM PDT 24
Peak memory 218724 kb
Host smart-fe388886-5a0d-4c26-956c-d64bde574690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107324726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1107324726
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.372384621
Short name T489
Test name
Test status
Simulation time 42280042 ps
CPU time 1.17 seconds
Started Jul 25 06:06:09 PM PDT 24
Finished Jul 25 06:06:11 PM PDT 24
Peak memory 221196 kb
Host smart-41c24523-7d03-45a1-91d7-8673c682f38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372384621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.372384621
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.4236825974
Short name T807
Test name
Test status
Simulation time 40416096 ps
CPU time 1.44 seconds
Started Jul 25 06:06:07 PM PDT 24
Finished Jul 25 06:06:08 PM PDT 24
Peak memory 218324 kb
Host smart-9413d88a-b016-469d-9ac1-9f45ff0dc2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236825974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4236825974
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.1646514405
Short name T284
Test name
Test status
Simulation time 89472318 ps
CPU time 1.15 seconds
Started Jul 25 06:06:08 PM PDT 24
Finished Jul 25 06:06:09 PM PDT 24
Peak memory 219436 kb
Host smart-5824846d-f13c-48fd-acaa-9de1c5c6afe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646514405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.1646514405
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2272617150
Short name T714
Test name
Test status
Simulation time 50568334 ps
CPU time 1.54 seconds
Started Jul 25 06:06:08 PM PDT 24
Finished Jul 25 06:06:09 PM PDT 24
Peak memory 218276 kb
Host smart-9ae142b0-581c-48a1-bba8-c26249038a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272617150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2272617150
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.1015097427
Short name T180
Test name
Test status
Simulation time 24423526 ps
CPU time 1.19 seconds
Started Jul 25 06:06:27 PM PDT 24
Finished Jul 25 06:06:28 PM PDT 24
Peak memory 218324 kb
Host smart-fd50de22-d75a-4660-8ba8-7a7f4b1a656b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015097427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1015097427
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.1105452621
Short name T916
Test name
Test status
Simulation time 115772318 ps
CPU time 1.24 seconds
Started Jul 25 06:06:09 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 217360 kb
Host smart-e0e5a8b0-c793-4a8d-93f6-5acd6933f5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105452621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1105452621
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.2163921549
Short name T285
Test name
Test status
Simulation time 26351935 ps
CPU time 1.17 seconds
Started Jul 25 06:06:04 PM PDT 24
Finished Jul 25 06:06:06 PM PDT 24
Peak memory 218448 kb
Host smart-0fe93a4e-5795-4b4c-a580-fba5d08f9ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163921549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.2163921549
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.1831736957
Short name T233
Test name
Test status
Simulation time 81542573 ps
CPU time 1.1 seconds
Started Jul 25 06:06:07 PM PDT 24
Finished Jul 25 06:06:09 PM PDT 24
Peak memory 217300 kb
Host smart-fb202247-9e1d-488e-9327-dd88370063a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831736957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1831736957
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.2316971504
Short name T790
Test name
Test status
Simulation time 95805155 ps
CPU time 1.2 seconds
Started Jul 25 06:06:06 PM PDT 24
Finished Jul 25 06:06:07 PM PDT 24
Peak memory 219272 kb
Host smart-94f66c61-7149-4ef7-b0cc-b41156fa252a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316971504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.2316971504
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.2027389428
Short name T761
Test name
Test status
Simulation time 71896524 ps
CPU time 1.22 seconds
Started Jul 25 06:06:07 PM PDT 24
Finished Jul 25 06:06:08 PM PDT 24
Peak memory 215256 kb
Host smart-0b4c13c9-b947-4a9d-af04-44471eb3f7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027389428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2027389428
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3733859496
Short name T551
Test name
Test status
Simulation time 44319537 ps
CPU time 1.24 seconds
Started Jul 25 06:04:12 PM PDT 24
Finished Jul 25 06:04:14 PM PDT 24
Peak memory 219724 kb
Host smart-a940e7fb-e3a0-4936-b05c-c93727bdef27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733859496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3733859496
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.895746718
Short name T452
Test name
Test status
Simulation time 29065285 ps
CPU time 0.95 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:12 PM PDT 24
Peak memory 215076 kb
Host smart-b3cc82bd-ec85-47b1-87a3-e742c384c959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895746718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.895746718
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3327645742
Short name T691
Test name
Test status
Simulation time 154369440 ps
CPU time 0.92 seconds
Started Jul 25 06:04:15 PM PDT 24
Finished Jul 25 06:04:16 PM PDT 24
Peak memory 215856 kb
Host smart-62fb9ddb-d256-47bb-b918-a1548915421e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327645742 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3327645742
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3136187687
Short name T545
Test name
Test status
Simulation time 47189677 ps
CPU time 0.97 seconds
Started Jul 25 06:04:13 PM PDT 24
Finished Jul 25 06:04:14 PM PDT 24
Peak memory 216724 kb
Host smart-fa6d3215-c90f-447f-a54b-53f52f35fe46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136187687 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3136187687
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2808915290
Short name T577
Test name
Test status
Simulation time 26028601 ps
CPU time 1.25 seconds
Started Jul 25 06:04:20 PM PDT 24
Finished Jul 25 06:04:22 PM PDT 24
Peak memory 220664 kb
Host smart-d4e70a3c-9eb1-4e70-a1cd-cdd2b6921a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808915290 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2808915290
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_intr.500201582
Short name T605
Test name
Test status
Simulation time 42011443 ps
CPU time 1 seconds
Started Jul 25 06:04:11 PM PDT 24
Finished Jul 25 06:04:13 PM PDT 24
Peak memory 223840 kb
Host smart-5afd5929-8853-4b68-96f1-0c372c5761bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500201582 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.500201582
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1554277877
Short name T424
Test name
Test status
Simulation time 63123158 ps
CPU time 0.86 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:12 PM PDT 24
Peak memory 215184 kb
Host smart-1e2e95b2-522f-4294-bcf2-fa6e68125071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554277877 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1554277877
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2220100767
Short name T52
Test name
Test status
Simulation time 674004461 ps
CPU time 2.69 seconds
Started Jul 25 06:04:19 PM PDT 24
Finished Jul 25 06:04:22 PM PDT 24
Peak memory 217080 kb
Host smart-404b105e-cc95-4ed2-bf68-9447b4ea8b18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220100767 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2220100767
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2757329429
Short name T219
Test name
Test status
Simulation time 185753488028 ps
CPU time 647.94 seconds
Started Jul 25 06:04:12 PM PDT 24
Finished Jul 25 06:15:00 PM PDT 24
Peak memory 221744 kb
Host smart-a3fb30d5-2828-42cb-b465-598399dce8e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757329429 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2757329429
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2170243870
Short name T195
Test name
Test status
Simulation time 79493342 ps
CPU time 1.19 seconds
Started Jul 25 06:06:09 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 219936 kb
Host smart-0bdb7015-b512-4e97-9406-7d52c36013df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170243870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2170243870
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.4260926329
Short name T596
Test name
Test status
Simulation time 45230788 ps
CPU time 1.27 seconds
Started Jul 25 06:06:08 PM PDT 24
Finished Jul 25 06:06:09 PM PDT 24
Peak memory 218652 kb
Host smart-334400a2-78e0-4c6b-8a36-427b433b3649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260926329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.4260926329
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.2284345947
Short name T185
Test name
Test status
Simulation time 120228806 ps
CPU time 1.16 seconds
Started Jul 25 06:06:07 PM PDT 24
Finished Jul 25 06:06:08 PM PDT 24
Peak memory 219592 kb
Host smart-a0abd994-a8e6-4165-8a7d-29933c3f06ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284345947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.2284345947
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.1399044870
Short name T26
Test name
Test status
Simulation time 48783986 ps
CPU time 1.09 seconds
Started Jul 25 06:06:06 PM PDT 24
Finished Jul 25 06:06:08 PM PDT 24
Peak memory 217284 kb
Host smart-9f696fe7-5965-4a4b-bf33-45366d5b69fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399044870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1399044870
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3822800375
Short name T794
Test name
Test status
Simulation time 92816524 ps
CPU time 1.37 seconds
Started Jul 25 06:06:08 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 219748 kb
Host smart-730d90a6-7acb-4607-9c33-33b89af49608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822800375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3822800375
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.2282884288
Short name T670
Test name
Test status
Simulation time 33843455 ps
CPU time 1.06 seconds
Started Jul 25 06:06:06 PM PDT 24
Finished Jul 25 06:06:07 PM PDT 24
Peak memory 219620 kb
Host smart-0423c5c3-e98d-4227-8246-924b81cd4adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282884288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2282884288
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1184843296
Short name T801
Test name
Test status
Simulation time 24797491 ps
CPU time 1.22 seconds
Started Jul 25 06:06:08 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 220352 kb
Host smart-86f8d17b-c27b-433e-ae06-0c938f4db285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184843296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1184843296
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.4107991837
Short name T466
Test name
Test status
Simulation time 433484473 ps
CPU time 1.33 seconds
Started Jul 25 06:06:05 PM PDT 24
Finished Jul 25 06:06:06 PM PDT 24
Peak memory 217484 kb
Host smart-dfeb99b1-767a-4538-b8a6-7c6d074179e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107991837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.4107991837
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.1164674298
Short name T405
Test name
Test status
Simulation time 24468697 ps
CPU time 1.23 seconds
Started Jul 25 06:06:09 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 218452 kb
Host smart-c7656f9c-e0fb-403e-8d4e-78a9d47065b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164674298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1164674298
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1147894130
Short name T490
Test name
Test status
Simulation time 43488075 ps
CPU time 1.17 seconds
Started Jul 25 06:06:09 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 218780 kb
Host smart-a826cfcd-ff49-4e82-befc-09a5c62fcf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147894130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1147894130
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.4098550329
Short name T238
Test name
Test status
Simulation time 86246571 ps
CPU time 1.21 seconds
Started Jul 25 06:06:07 PM PDT 24
Finished Jul 25 06:06:08 PM PDT 24
Peak memory 218440 kb
Host smart-5f9971dd-6af6-42d1-b915-505303960217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098550329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.4098550329
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1919224953
Short name T751
Test name
Test status
Simulation time 40195361 ps
CPU time 1.28 seconds
Started Jul 25 06:06:09 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 217164 kb
Host smart-f52e907b-d957-4ecb-8c4b-19a3943b7d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919224953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1919224953
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.3379011544
Short name T176
Test name
Test status
Simulation time 321025263 ps
CPU time 1.23 seconds
Started Jul 25 06:06:11 PM PDT 24
Finished Jul 25 06:06:12 PM PDT 24
Peak memory 219588 kb
Host smart-ba42575f-20a9-4ce1-bcff-997e15498622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379011544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3379011544
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.1235766591
Short name T494
Test name
Test status
Simulation time 81811594 ps
CPU time 1.54 seconds
Started Jul 25 06:06:06 PM PDT 24
Finished Jul 25 06:06:08 PM PDT 24
Peak memory 218308 kb
Host smart-238030fd-3d48-40e4-b15a-b62f984c01d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235766591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1235766591
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.611957593
Short name T353
Test name
Test status
Simulation time 27545116 ps
CPU time 1.21 seconds
Started Jul 25 06:06:08 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 218512 kb
Host smart-92220335-1523-460c-8967-b5002a6a3bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611957593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.611957593
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.2444770399
Short name T975
Test name
Test status
Simulation time 101782787 ps
CPU time 1.64 seconds
Started Jul 25 06:06:06 PM PDT 24
Finished Jul 25 06:06:08 PM PDT 24
Peak memory 218444 kb
Host smart-1b936911-8206-45ba-9238-f006c5cc90d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444770399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2444770399
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.4187286356
Short name T227
Test name
Test status
Simulation time 101420905 ps
CPU time 1.3 seconds
Started Jul 25 06:06:08 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 218164 kb
Host smart-ba061fb2-0a31-48d9-aca1-ff2475337b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187286356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.4187286356
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.2525613495
Short name T303
Test name
Test status
Simulation time 62021555 ps
CPU time 2.29 seconds
Started Jul 25 06:06:09 PM PDT 24
Finished Jul 25 06:06:11 PM PDT 24
Peak memory 219812 kb
Host smart-082606a7-8114-4674-939f-b6d487d62cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525613495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2525613495
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.1414376249
Short name T382
Test name
Test status
Simulation time 71129947 ps
CPU time 1.12 seconds
Started Jul 25 06:06:11 PM PDT 24
Finished Jul 25 06:06:13 PM PDT 24
Peak memory 218412 kb
Host smart-8340908f-c5d6-4175-a00d-9ea28471fabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414376249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.1414376249
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1861099721
Short name T824
Test name
Test status
Simulation time 60791200 ps
CPU time 2.2 seconds
Started Jul 25 06:06:08 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 220192 kb
Host smart-99a0bc6a-b63d-44bc-91f3-09a7dd0ff34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861099721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1861099721
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.508590446
Short name T377
Test name
Test status
Simulation time 29292771 ps
CPU time 1.12 seconds
Started Jul 25 06:04:12 PM PDT 24
Finished Jul 25 06:04:13 PM PDT 24
Peak memory 218420 kb
Host smart-acc795e7-5f72-41fb-81e3-e2ae3ed63d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508590446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.508590446
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1052268315
Short name T417
Test name
Test status
Simulation time 20643742 ps
CPU time 1.05 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:12 PM PDT 24
Peak memory 206668 kb
Host smart-0c2d38b6-e982-406e-9aeb-c847bb9eae20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052268315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1052268315
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.495040539
Short name T199
Test name
Test status
Simulation time 12441555 ps
CPU time 0.9 seconds
Started Jul 25 06:04:11 PM PDT 24
Finished Jul 25 06:04:13 PM PDT 24
Peak memory 216396 kb
Host smart-565722a7-b23a-4f09-9373-b81fa58b3640
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495040539 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.495040539
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.4000751492
Short name T744
Test name
Test status
Simulation time 26114527 ps
CPU time 1.15 seconds
Started Jul 25 06:04:12 PM PDT 24
Finished Jul 25 06:04:14 PM PDT 24
Peak memory 218240 kb
Host smart-6e6ed4e0-872e-42fd-ba7c-136813689317
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000751492 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.4000751492
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.921544910
Short name T429
Test name
Test status
Simulation time 49083955 ps
CPU time 1.18 seconds
Started Jul 25 06:04:11 PM PDT 24
Finished Jul 25 06:04:12 PM PDT 24
Peak memory 225532 kb
Host smart-c974a4d1-f06a-4dd7-b205-443d9a1af0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921544910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.921544910
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.100008471
Short name T505
Test name
Test status
Simulation time 77886199 ps
CPU time 1.07 seconds
Started Jul 25 06:04:13 PM PDT 24
Finished Jul 25 06:04:14 PM PDT 24
Peak memory 217132 kb
Host smart-c41dc3d9-1197-45b5-83fc-1c520d5d02f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100008471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.100008471
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1474795404
Short name T831
Test name
Test status
Simulation time 40500689 ps
CPU time 0.84 seconds
Started Jul 25 06:04:13 PM PDT 24
Finished Jul 25 06:04:14 PM PDT 24
Peak memory 215560 kb
Host smart-585bbadc-2cc1-48d1-8c99-1356bf439fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474795404 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1474795404
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1127429799
Short name T763
Test name
Test status
Simulation time 30504385 ps
CPU time 0.94 seconds
Started Jul 25 06:04:12 PM PDT 24
Finished Jul 25 06:04:14 PM PDT 24
Peak memory 215152 kb
Host smart-e276bd1d-1a5a-4077-bf86-d509fc9ac7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127429799 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1127429799
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2241763376
Short name T225
Test name
Test status
Simulation time 430485029 ps
CPU time 8.05 seconds
Started Jul 25 06:04:13 PM PDT 24
Finished Jul 25 06:04:21 PM PDT 24
Peak memory 215184 kb
Host smart-f0506868-3459-4e6c-9db1-22582761babc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241763376 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2241763376
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2994734155
Short name T304
Test name
Test status
Simulation time 170463185310 ps
CPU time 960.39 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:20:10 PM PDT 24
Peak memory 223528 kb
Host smart-72c51d23-ecb8-444f-895b-f9470ea71200
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994734155 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2994734155
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3309298320
Short name T749
Test name
Test status
Simulation time 285635297 ps
CPU time 1.35 seconds
Started Jul 25 06:06:06 PM PDT 24
Finished Jul 25 06:06:07 PM PDT 24
Peak memory 219168 kb
Host smart-40249f72-6fe7-4489-8eb5-25cea462bab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309298320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3309298320
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.2060238961
Short name T554
Test name
Test status
Simulation time 143724052 ps
CPU time 1.12 seconds
Started Jul 25 06:06:07 PM PDT 24
Finished Jul 25 06:06:09 PM PDT 24
Peak memory 217072 kb
Host smart-89e35093-e88d-49f2-b0dc-846f66d4389b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060238961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2060238961
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.3135604520
Short name T952
Test name
Test status
Simulation time 29203418 ps
CPU time 1.24 seconds
Started Jul 25 06:06:09 PM PDT 24
Finished Jul 25 06:06:11 PM PDT 24
Peak memory 219456 kb
Host smart-0b4779df-7955-455f-b618-dd780b79774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135604520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3135604520
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.2793512484
Short name T341
Test name
Test status
Simulation time 51346222 ps
CPU time 1.36 seconds
Started Jul 25 06:06:07 PM PDT 24
Finished Jul 25 06:06:09 PM PDT 24
Peak memory 218776 kb
Host smart-ddea0d26-e765-4b08-82c7-a8fe4f77608b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793512484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2793512484
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.1544012018
Short name T277
Test name
Test status
Simulation time 26255547 ps
CPU time 1.21 seconds
Started Jul 25 06:06:11 PM PDT 24
Finished Jul 25 06:06:12 PM PDT 24
Peak memory 218580 kb
Host smart-956efe46-9732-48f3-ad23-20fc612e2b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544012018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1544012018
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.1580072758
Short name T614
Test name
Test status
Simulation time 106003986 ps
CPU time 1.14 seconds
Started Jul 25 06:06:27 PM PDT 24
Finished Jul 25 06:06:28 PM PDT 24
Peak memory 217304 kb
Host smart-c4eeff0b-5790-4771-853e-f9ab2db9c9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580072758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1580072758
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.2930479462
Short name T681
Test name
Test status
Simulation time 27090252 ps
CPU time 1.24 seconds
Started Jul 25 06:06:06 PM PDT 24
Finished Jul 25 06:06:08 PM PDT 24
Peak memory 219620 kb
Host smart-e2d2d862-107e-476e-9284-484e18172bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930479462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.2930479462
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.434849438
Short name T945
Test name
Test status
Simulation time 36214827 ps
CPU time 1.54 seconds
Started Jul 25 06:06:07 PM PDT 24
Finished Jul 25 06:06:08 PM PDT 24
Peak memory 218404 kb
Host smart-9c3bd03e-635e-421e-adb4-4e3142340570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434849438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.434849438
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2897558088
Short name T539
Test name
Test status
Simulation time 84216881 ps
CPU time 1.14 seconds
Started Jul 25 06:06:11 PM PDT 24
Finished Jul 25 06:06:13 PM PDT 24
Peak memory 219684 kb
Host smart-ebb5b7e1-5ec5-49d1-a688-e3774d13554f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897558088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2897558088
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.1039930724
Short name T318
Test name
Test status
Simulation time 47959583 ps
CPU time 1.31 seconds
Started Jul 25 06:06:10 PM PDT 24
Finished Jul 25 06:06:11 PM PDT 24
Peak memory 218536 kb
Host smart-083322fd-c5cf-439d-bc33-322076a3f0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039930724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1039930724
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.1846298797
Short name T550
Test name
Test status
Simulation time 27153356 ps
CPU time 1.29 seconds
Started Jul 25 06:06:08 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 218376 kb
Host smart-98656f69-a26e-4aac-bf1d-8c7d13ba133a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846298797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.1846298797
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.910921862
Short name T512
Test name
Test status
Simulation time 71842165 ps
CPU time 1.52 seconds
Started Jul 25 06:06:27 PM PDT 24
Finished Jul 25 06:06:28 PM PDT 24
Peak memory 215104 kb
Host smart-9faed184-f3b3-4421-8dca-e5bdaa9acc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910921862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.910921862
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3728975363
Short name T984
Test name
Test status
Simulation time 49966401 ps
CPU time 1.23 seconds
Started Jul 25 06:06:09 PM PDT 24
Finished Jul 25 06:06:11 PM PDT 24
Peak memory 220900 kb
Host smart-e49decc8-08ac-4028-9921-d56df203cfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728975363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3728975363
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.43307061
Short name T406
Test name
Test status
Simulation time 106733676 ps
CPU time 2.73 seconds
Started Jul 25 06:06:07 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 219488 kb
Host smart-2e509903-06c7-46e7-b320-8453447f8256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43307061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.43307061
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2567740506
Short name T917
Test name
Test status
Simulation time 28678028 ps
CPU time 1.34 seconds
Started Jul 25 06:06:08 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 220896 kb
Host smart-34ec7796-feee-41ec-9aba-67bad0b4fbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567740506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2567740506
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1866296011
Short name T373
Test name
Test status
Simulation time 78375089 ps
CPU time 1.19 seconds
Started Jul 25 06:06:08 PM PDT 24
Finished Jul 25 06:06:10 PM PDT 24
Peak memory 217256 kb
Host smart-ef7789ef-58ad-47cc-b3aa-70975a106dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866296011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1866296011
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.1008394452
Short name T689
Test name
Test status
Simulation time 54531373 ps
CPU time 1.11 seconds
Started Jul 25 06:06:05 PM PDT 24
Finished Jul 25 06:06:06 PM PDT 24
Peak memory 218716 kb
Host smart-fa92c6eb-3dd5-47d5-9476-915fb8c87238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008394452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1008394452
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1107122427
Short name T465
Test name
Test status
Simulation time 88050878 ps
CPU time 1.1 seconds
Started Jul 25 06:06:12 PM PDT 24
Finished Jul 25 06:06:13 PM PDT 24
Peak memory 217208 kb
Host smart-b70054c2-f3f4-4618-a4c3-c04f19be46b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107122427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1107122427
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.4277228228
Short name T851
Test name
Test status
Simulation time 66855876 ps
CPU time 1.33 seconds
Started Jul 25 06:06:06 PM PDT 24
Finished Jul 25 06:06:07 PM PDT 24
Peak memory 215172 kb
Host smart-2108ef90-b460-4f12-8e8f-2c8301beedff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277228228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.4277228228
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.895955386
Short name T581
Test name
Test status
Simulation time 39852256 ps
CPU time 1.11 seconds
Started Jul 25 06:04:11 PM PDT 24
Finished Jul 25 06:04:13 PM PDT 24
Peak memory 218500 kb
Host smart-31a573ca-256d-4062-9990-32306d9e697b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895955386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.895955386
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2268637940
Short name T853
Test name
Test status
Simulation time 20310964 ps
CPU time 1.01 seconds
Started Jul 25 06:04:12 PM PDT 24
Finished Jul 25 06:04:13 PM PDT 24
Peak memory 214816 kb
Host smart-d059910e-f170-4476-85bf-15f7adb31606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268637940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2268637940
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2907996227
Short name T531
Test name
Test status
Simulation time 32118313 ps
CPU time 0.86 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:11 PM PDT 24
Peak memory 216076 kb
Host smart-11bc0e93-679c-4397-95d7-fafca2c6ccb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907996227 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2907996227
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3218160385
Short name T384
Test name
Test status
Simulation time 64124419 ps
CPU time 1.26 seconds
Started Jul 25 06:04:14 PM PDT 24
Finished Jul 25 06:04:15 PM PDT 24
Peak memory 216856 kb
Host smart-cff8f523-490e-461d-bda8-06c572b1f355
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218160385 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3218160385
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1808542870
Short name T855
Test name
Test status
Simulation time 18698066 ps
CPU time 1.03 seconds
Started Jul 25 06:04:12 PM PDT 24
Finished Jul 25 06:04:14 PM PDT 24
Peak memory 218756 kb
Host smart-bddd23f2-e343-4c5c-9169-bb6579caef57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808542870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1808542870
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.2326662006
Short name T897
Test name
Test status
Simulation time 23388262 ps
CPU time 0.93 seconds
Started Jul 25 06:04:11 PM PDT 24
Finished Jul 25 06:04:12 PM PDT 24
Peak memory 215276 kb
Host smart-c2f70e11-be8e-406d-985a-95735934558d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326662006 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2326662006
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3155956472
Short name T511
Test name
Test status
Simulation time 23310363 ps
CPU time 0.93 seconds
Started Jul 25 06:04:15 PM PDT 24
Finished Jul 25 06:04:16 PM PDT 24
Peak memory 215320 kb
Host smart-9d73181d-8dc8-45a0-8742-a5f77a27ac9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155956472 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3155956472
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3625372637
Short name T221
Test name
Test status
Simulation time 175366563545 ps
CPU time 982.02 seconds
Started Jul 25 06:04:16 PM PDT 24
Finished Jul 25 06:20:38 PM PDT 24
Peak memory 221088 kb
Host smart-417ee3cb-06cf-4a44-af0c-421609094c69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625372637 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3625372637
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.774184355
Short name T488
Test name
Test status
Simulation time 24388981 ps
CPU time 1.2 seconds
Started Jul 25 06:06:08 PM PDT 24
Finished Jul 25 06:06:09 PM PDT 24
Peak memory 219788 kb
Host smart-5f66483f-38f2-47a2-935b-653136aafb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774184355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.774184355
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.2699750019
Short name T747
Test name
Test status
Simulation time 96357374 ps
CPU time 1.34 seconds
Started Jul 25 06:06:06 PM PDT 24
Finished Jul 25 06:06:08 PM PDT 24
Peak memory 218520 kb
Host smart-4d278d9c-1cc2-440f-bf23-2bfea7dd5649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699750019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2699750019
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.4225746584
Short name T925
Test name
Test status
Simulation time 28901522 ps
CPU time 1.21 seconds
Started Jul 25 06:06:07 PM PDT 24
Finished Jul 25 06:06:09 PM PDT 24
Peak memory 219496 kb
Host smart-3f756f3b-d0f4-4763-a7ea-e76fc2d96faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225746584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.4225746584
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.204944040
Short name T818
Test name
Test status
Simulation time 64532196 ps
CPU time 1.16 seconds
Started Jul 25 06:06:27 PM PDT 24
Finished Jul 25 06:06:28 PM PDT 24
Peak memory 217148 kb
Host smart-aaa7bee7-6b78-486b-9bf9-541e8bd8717f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204944040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.204944040
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1826173926
Short name T236
Test name
Test status
Simulation time 104357844 ps
CPU time 1.36 seconds
Started Jul 25 06:06:16 PM PDT 24
Finished Jul 25 06:06:17 PM PDT 24
Peak memory 219608 kb
Host smart-07dbdba7-7c7f-4060-8f31-ee2ad7908d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826173926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1826173926
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.796594990
Short name T983
Test name
Test status
Simulation time 68351631 ps
CPU time 1.62 seconds
Started Jul 25 06:06:13 PM PDT 24
Finished Jul 25 06:06:15 PM PDT 24
Peak memory 218732 kb
Host smart-ff5c29c1-396d-4945-91a0-bc1e2be2e441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796594990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.796594990
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.572288534
Short name T674
Test name
Test status
Simulation time 89171950 ps
CPU time 1.19 seconds
Started Jul 25 06:06:10 PM PDT 24
Finished Jul 25 06:06:12 PM PDT 24
Peak memory 219520 kb
Host smart-c7b49f78-247a-4d49-9c1f-6acc74fb2c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572288534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.572288534
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.4139363708
Short name T317
Test name
Test status
Simulation time 69741925 ps
CPU time 1.26 seconds
Started Jul 25 06:06:15 PM PDT 24
Finished Jul 25 06:06:17 PM PDT 24
Peak memory 218560 kb
Host smart-87235a5e-018d-4cb9-b7e5-f01dbe242a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139363708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.4139363708
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.989564360
Short name T800
Test name
Test status
Simulation time 36653305 ps
CPU time 1.11 seconds
Started Jul 25 06:06:17 PM PDT 24
Finished Jul 25 06:06:18 PM PDT 24
Peak memory 219208 kb
Host smart-08dda5b7-f38d-49bf-8332-ccf0d3a75e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989564360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.989564360
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2399643362
Short name T334
Test name
Test status
Simulation time 54571857 ps
CPU time 2.14 seconds
Started Jul 25 06:06:13 PM PDT 24
Finished Jul 25 06:06:15 PM PDT 24
Peak memory 219952 kb
Host smart-bfd52d4f-cce4-4ad0-975d-58cbc1f6fe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399643362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2399643362
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.1383965924
Short name T160
Test name
Test status
Simulation time 26057311 ps
CPU time 1.23 seconds
Started Jul 25 06:06:13 PM PDT 24
Finished Jul 25 06:06:15 PM PDT 24
Peak memory 220360 kb
Host smart-12977577-c7ba-4f94-a732-b8f950d75392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383965924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1383965924
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.3341818748
Short name T578
Test name
Test status
Simulation time 51367071 ps
CPU time 1.84 seconds
Started Jul 25 06:06:11 PM PDT 24
Finished Jul 25 06:06:13 PM PDT 24
Peak memory 218356 kb
Host smart-e0310ef9-db37-4556-a124-0f64ab6b4eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341818748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3341818748
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1899287412
Short name T762
Test name
Test status
Simulation time 27907890 ps
CPU time 1.23 seconds
Started Jul 25 06:06:14 PM PDT 24
Finished Jul 25 06:06:16 PM PDT 24
Peak memory 215600 kb
Host smart-4722b71b-8e7a-4f9f-b8fe-06856e41ee38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899287412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1899287412
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.3854107164
Short name T470
Test name
Test status
Simulation time 82878760 ps
CPU time 2.74 seconds
Started Jul 25 06:06:17 PM PDT 24
Finished Jul 25 06:06:19 PM PDT 24
Peak memory 219656 kb
Host smart-ad078d5a-bd87-4287-831d-e4bbd60386ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854107164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3854107164
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.1045055595
Short name T863
Test name
Test status
Simulation time 27955442 ps
CPU time 1.28 seconds
Started Jul 25 06:06:14 PM PDT 24
Finished Jul 25 06:06:16 PM PDT 24
Peak memory 219460 kb
Host smart-62eee806-e1ac-4939-b601-4bcfd3910df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045055595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.1045055595
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.2488981911
Short name T941
Test name
Test status
Simulation time 56240876 ps
CPU time 1.25 seconds
Started Jul 25 06:06:15 PM PDT 24
Finished Jul 25 06:06:17 PM PDT 24
Peak memory 218328 kb
Host smart-0238575e-207c-43b2-9fef-d464f0e55dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488981911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2488981911
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.1313742388
Short name T141
Test name
Test status
Simulation time 71527287 ps
CPU time 1.11 seconds
Started Jul 25 06:06:11 PM PDT 24
Finished Jul 25 06:06:12 PM PDT 24
Peak memory 219260 kb
Host smart-93cde4ac-7a1b-4a25-929f-bb1ad62ddd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313742388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.1313742388
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3152154860
Short name T563
Test name
Test status
Simulation time 64589535 ps
CPU time 1.46 seconds
Started Jul 25 06:06:12 PM PDT 24
Finished Jul 25 06:06:14 PM PDT 24
Peak memory 218312 kb
Host smart-63d2b545-4cd9-44cc-805b-3a8529174454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152154860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3152154860
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2107284546
Short name T628
Test name
Test status
Simulation time 27583537 ps
CPU time 1.3 seconds
Started Jul 25 06:06:12 PM PDT 24
Finished Jul 25 06:06:13 PM PDT 24
Peak memory 215496 kb
Host smart-60a9a4b7-d356-4720-a3ad-d70f3f563265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107284546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2107284546
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2150581625
Short name T348
Test name
Test status
Simulation time 75331967 ps
CPU time 1.52 seconds
Started Jul 25 06:06:09 PM PDT 24
Finished Jul 25 06:06:11 PM PDT 24
Peak memory 219308 kb
Host smart-5660c377-24be-4fac-ae98-6baea129c75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150581625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2150581625
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1203184130
Short name T796
Test name
Test status
Simulation time 24052410 ps
CPU time 1.17 seconds
Started Jul 25 06:04:12 PM PDT 24
Finished Jul 25 06:04:14 PM PDT 24
Peak memory 219704 kb
Host smart-2d81c4bf-ad7b-4bd3-90f0-a86a654cc35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203184130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1203184130
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.925160159
Short name T473
Test name
Test status
Simulation time 47485111 ps
CPU time 0.83 seconds
Started Jul 25 06:04:23 PM PDT 24
Finished Jul 25 06:04:24 PM PDT 24
Peak memory 206456 kb
Host smart-8d12b38c-7eb3-4fb2-93ee-e7f4300a66f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925160159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.925160159
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.420986716
Short name T136
Test name
Test status
Simulation time 54177645 ps
CPU time 0.85 seconds
Started Jul 25 06:04:20 PM PDT 24
Finished Jul 25 06:04:21 PM PDT 24
Peak memory 216116 kb
Host smart-cd4e77ac-d2ec-44ac-a5f6-6cbc65f01069
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420986716 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.420986716
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2700293818
Short name T94
Test name
Test status
Simulation time 97612349 ps
CPU time 1.11 seconds
Started Jul 25 06:04:22 PM PDT 24
Finished Jul 25 06:04:24 PM PDT 24
Peak memory 216796 kb
Host smart-9f96967e-80ed-421d-9b84-53bbdbac678b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700293818 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2700293818
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1644898472
Short name T144
Test name
Test status
Simulation time 25510138 ps
CPU time 1.23 seconds
Started Jul 25 06:04:19 PM PDT 24
Finished Jul 25 06:04:20 PM PDT 24
Peak memory 219516 kb
Host smart-95dc7fc8-bd2e-4585-a741-dd12db690a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644898472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1644898472
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1592123878
Short name T503
Test name
Test status
Simulation time 67871222 ps
CPU time 1.09 seconds
Started Jul 25 06:04:11 PM PDT 24
Finished Jul 25 06:04:13 PM PDT 24
Peak memory 217168 kb
Host smart-36201e61-db12-448c-9243-c8b6536763b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592123878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1592123878
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1904705381
Short name T46
Test name
Test status
Simulation time 23069496 ps
CPU time 1.22 seconds
Started Jul 25 06:04:20 PM PDT 24
Finished Jul 25 06:04:22 PM PDT 24
Peak memory 223944 kb
Host smart-b7ae1cf5-e476-4d6b-ac7f-19aca61b0ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904705381 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1904705381
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2580816797
Short name T327
Test name
Test status
Simulation time 16906803 ps
CPU time 0.99 seconds
Started Jul 25 06:04:12 PM PDT 24
Finished Jul 25 06:04:14 PM PDT 24
Peak memory 215204 kb
Host smart-76ebb10d-4a1e-448d-a1f6-d0a98ea9b555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580816797 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2580816797
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2665233764
Short name T501
Test name
Test status
Simulation time 160513239 ps
CPU time 3.48 seconds
Started Jul 25 06:04:11 PM PDT 24
Finished Jul 25 06:04:15 PM PDT 24
Peak memory 219752 kb
Host smart-c9ebd4d6-dda8-4836-9d08-a58fb5a36797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665233764 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2665233764
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.990874329
Short name T879
Test name
Test status
Simulation time 59770420153 ps
CPU time 1422.66 seconds
Started Jul 25 06:04:14 PM PDT 24
Finished Jul 25 06:27:57 PM PDT 24
Peak memory 223768 kb
Host smart-49903637-2733-4e86-a2e3-d135540ba10b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990874329 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.990874329
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.2163097604
Short name T532
Test name
Test status
Simulation time 36240503 ps
CPU time 1.26 seconds
Started Jul 25 06:06:16 PM PDT 24
Finished Jul 25 06:06:17 PM PDT 24
Peak memory 219272 kb
Host smart-a98066c5-be71-4dee-a27c-44ca68e704a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163097604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2163097604
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.466959423
Short name T411
Test name
Test status
Simulation time 84775959 ps
CPU time 1.22 seconds
Started Jul 25 06:06:19 PM PDT 24
Finished Jul 25 06:06:20 PM PDT 24
Peak memory 217320 kb
Host smart-dd903b5c-e4fd-484d-97fa-4db949496574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466959423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.466959423
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1220010800
Short name T608
Test name
Test status
Simulation time 144078070 ps
CPU time 1.39 seconds
Started Jul 25 06:06:13 PM PDT 24
Finished Jul 25 06:06:15 PM PDT 24
Peak memory 219608 kb
Host smart-1fa4a279-11e7-45bd-bbba-ba976b58982f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220010800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1220010800
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.891712347
Short name T450
Test name
Test status
Simulation time 93745157 ps
CPU time 1.04 seconds
Started Jul 25 06:06:17 PM PDT 24
Finished Jul 25 06:06:18 PM PDT 24
Peak memory 217248 kb
Host smart-39b39a73-1410-41e6-ab50-9a9cdbe57478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891712347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.891712347
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3593707184
Short name T623
Test name
Test status
Simulation time 26732357 ps
CPU time 1.18 seconds
Started Jul 25 06:06:17 PM PDT 24
Finished Jul 25 06:06:19 PM PDT 24
Peak memory 219428 kb
Host smart-83311826-3b9a-486b-9606-63e63d3a8e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593707184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3593707184
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.887130569
Short name T587
Test name
Test status
Simulation time 100252892 ps
CPU time 1.54 seconds
Started Jul 25 06:06:13 PM PDT 24
Finished Jul 25 06:06:14 PM PDT 24
Peak memory 218568 kb
Host smart-9cf29fbf-5b74-42db-af2b-ef09190ebef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887130569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.887130569
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.1939448183
Short name T742
Test name
Test status
Simulation time 94626049 ps
CPU time 1.24 seconds
Started Jul 25 06:06:18 PM PDT 24
Finished Jul 25 06:06:19 PM PDT 24
Peak memory 217340 kb
Host smart-c65e62c1-97ad-4426-8081-e1e22dbbacdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939448183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1939448183
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2901464899
Short name T616
Test name
Test status
Simulation time 64409662 ps
CPU time 1.16 seconds
Started Jul 25 06:06:16 PM PDT 24
Finished Jul 25 06:06:17 PM PDT 24
Peak memory 218908 kb
Host smart-aed1a337-ad80-4e2e-bcef-182c8af8ece9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901464899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2901464899
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.690515372
Short name T548
Test name
Test status
Simulation time 75669196 ps
CPU time 1.06 seconds
Started Jul 25 06:06:12 PM PDT 24
Finished Jul 25 06:06:13 PM PDT 24
Peak memory 218372 kb
Host smart-65b1349d-a6fe-4b2a-9f96-2e06558ff67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690515372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.690515372
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.3208397054
Short name T286
Test name
Test status
Simulation time 2207598685 ps
CPU time 64.88 seconds
Started Jul 25 06:06:13 PM PDT 24
Finished Jul 25 06:07:18 PM PDT 24
Peak memory 220136 kb
Host smart-b721438f-6c00-4273-84ea-36ffc569d59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208397054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3208397054
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.792508801
Short name T397
Test name
Test status
Simulation time 58680848 ps
CPU time 1.36 seconds
Started Jul 25 06:06:15 PM PDT 24
Finished Jul 25 06:06:17 PM PDT 24
Peak memory 220016 kb
Host smart-d53247b1-2dec-48fc-b94e-aa0bf0c283d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792508801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.792508801
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.3953216607
Short name T717
Test name
Test status
Simulation time 38383337 ps
CPU time 1.16 seconds
Started Jul 25 06:06:14 PM PDT 24
Finished Jul 25 06:06:16 PM PDT 24
Peak memory 219308 kb
Host smart-3a82e118-d8da-40f3-aa97-064d50ae306c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953216607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3953216607
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/188.edn_alert.332343124
Short name T965
Test name
Test status
Simulation time 24500314 ps
CPU time 1.18 seconds
Started Jul 25 06:06:13 PM PDT 24
Finished Jul 25 06:06:14 PM PDT 24
Peak memory 219300 kb
Host smart-3e83bfd5-bfb1-49f0-8de6-1404c9d0e76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332343124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.332343124
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3434021867
Short name T837
Test name
Test status
Simulation time 96213413 ps
CPU time 1.53 seconds
Started Jul 25 06:06:16 PM PDT 24
Finished Jul 25 06:06:17 PM PDT 24
Peak memory 218580 kb
Host smart-bc24802e-8dd5-4843-a58c-1d9523c73a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434021867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3434021867
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3794734166
Short name T806
Test name
Test status
Simulation time 64031634 ps
CPU time 1.13 seconds
Started Jul 25 06:06:13 PM PDT 24
Finished Jul 25 06:06:15 PM PDT 24
Peak memory 218444 kb
Host smart-a0e884b0-4b64-4ee4-8e4a-53780b8c426d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794734166 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3794734166
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.788537632
Short name T667
Test name
Test status
Simulation time 39537242 ps
CPU time 1.14 seconds
Started Jul 25 06:06:16 PM PDT 24
Finished Jul 25 06:06:17 PM PDT 24
Peak memory 218696 kb
Host smart-5f5baf20-9eec-48c8-89c0-988c1310544a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788537632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.788537632
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1587892988
Short name T100
Test name
Test status
Simulation time 38506494 ps
CPU time 1.13 seconds
Started Jul 25 06:04:23 PM PDT 24
Finished Jul 25 06:04:24 PM PDT 24
Peak memory 218480 kb
Host smart-9fdacac8-0e64-46b5-bc97-35f18d1453d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587892988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1587892988
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2663083076
Short name T472
Test name
Test status
Simulation time 13916455 ps
CPU time 0.89 seconds
Started Jul 25 06:04:21 PM PDT 24
Finished Jul 25 06:04:22 PM PDT 24
Peak memory 214740 kb
Host smart-82a5889c-0d8d-485d-ae35-5914a1d06c04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663083076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2663083076
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2475443857
Short name T351
Test name
Test status
Simulation time 26776782 ps
CPU time 0.84 seconds
Started Jul 25 06:04:29 PM PDT 24
Finished Jul 25 06:04:30 PM PDT 24
Peak memory 215844 kb
Host smart-ff338f9c-368b-4f0f-bd94-fcdad4ce2b47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475443857 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2475443857
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2080538533
Short name T739
Test name
Test status
Simulation time 26470031 ps
CPU time 1.12 seconds
Started Jul 25 06:04:22 PM PDT 24
Finished Jul 25 06:04:23 PM PDT 24
Peak memory 218392 kb
Host smart-394e3b1b-c569-4566-867d-40550f3da02d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080538533 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2080538533
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.942523248
Short name T774
Test name
Test status
Simulation time 19221706 ps
CPU time 1.08 seconds
Started Jul 25 06:04:21 PM PDT 24
Finished Jul 25 06:04:22 PM PDT 24
Peak memory 218580 kb
Host smart-41eff39b-9624-420e-902e-e26c835ced5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942523248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.942523248
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2862912015
Short name T426
Test name
Test status
Simulation time 45473521 ps
CPU time 1.71 seconds
Started Jul 25 06:04:22 PM PDT 24
Finished Jul 25 06:04:24 PM PDT 24
Peak memory 217280 kb
Host smart-c87e5117-d48f-49ec-a303-1a83bfcadeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862912015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2862912015
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3506031739
Short name T5
Test name
Test status
Simulation time 38169468 ps
CPU time 0.88 seconds
Started Jul 25 06:04:20 PM PDT 24
Finished Jul 25 06:04:21 PM PDT 24
Peak memory 215556 kb
Host smart-8ea6fac1-265e-4936-a2d6-585f9d98d00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506031739 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3506031739
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.771733545
Short name T346
Test name
Test status
Simulation time 43364402 ps
CPU time 0.94 seconds
Started Jul 25 06:04:23 PM PDT 24
Finished Jul 25 06:04:24 PM PDT 24
Peak memory 215168 kb
Host smart-315cd6fb-defe-405b-948e-4b0e1270f494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771733545 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.771733545
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1957954490
Short name T534
Test name
Test status
Simulation time 142478909 ps
CPU time 3.02 seconds
Started Jul 25 06:04:20 PM PDT 24
Finished Jul 25 06:04:23 PM PDT 24
Peak memory 218420 kb
Host smart-40226d4a-25d2-4860-8750-d0a2844f540a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957954490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1957954490
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2973906354
Short name T409
Test name
Test status
Simulation time 35552679657 ps
CPU time 746.06 seconds
Started Jul 25 06:04:18 PM PDT 24
Finished Jul 25 06:16:45 PM PDT 24
Peak memory 223600 kb
Host smart-89cb5d1d-ec77-43ef-977d-e814a20c6344
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973906354 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2973906354
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.3277460771
Short name T64
Test name
Test status
Simulation time 27367841 ps
CPU time 1.24 seconds
Started Jul 25 06:06:11 PM PDT 24
Finished Jul 25 06:06:13 PM PDT 24
Peak memory 220092 kb
Host smart-b6bdcce8-6cbb-477d-a74e-c29a084a9b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277460771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.3277460771
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.1964686395
Short name T12
Test name
Test status
Simulation time 36719569 ps
CPU time 1.41 seconds
Started Jul 25 06:06:13 PM PDT 24
Finished Jul 25 06:06:14 PM PDT 24
Peak memory 218480 kb
Host smart-ea5a03ae-7153-42f6-a8e8-35e404e07827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964686395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1964686395
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.13127404
Short name T475
Test name
Test status
Simulation time 96405970 ps
CPU time 1.12 seconds
Started Jul 25 06:06:13 PM PDT 24
Finished Jul 25 06:06:14 PM PDT 24
Peak memory 219988 kb
Host smart-beaef5c1-7448-4844-a663-90bbf52ca219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13127404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.13127404
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/192.edn_alert.674576212
Short name T47
Test name
Test status
Simulation time 37794506 ps
CPU time 1.15 seconds
Started Jul 25 06:06:18 PM PDT 24
Finished Jul 25 06:06:19 PM PDT 24
Peak memory 219232 kb
Host smart-e5d5c14e-9380-4851-86de-cad59234ca28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674576212 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.674576212
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2326125008
Short name T435
Test name
Test status
Simulation time 89397997 ps
CPU time 3.06 seconds
Started Jul 25 06:06:14 PM PDT 24
Finished Jul 25 06:06:17 PM PDT 24
Peak memory 215288 kb
Host smart-38b04dbe-805d-4e86-ac7e-8ed53c13d8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326125008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2326125008
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.3423558838
Short name T699
Test name
Test status
Simulation time 40643405 ps
CPU time 1.12 seconds
Started Jul 25 06:06:17 PM PDT 24
Finished Jul 25 06:06:18 PM PDT 24
Peak memory 218480 kb
Host smart-31674e2d-a430-43df-a371-06190a91688d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423558838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.3423558838
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.2526456081
Short name T603
Test name
Test status
Simulation time 39031354 ps
CPU time 1.05 seconds
Started Jul 25 06:06:13 PM PDT 24
Finished Jul 25 06:06:14 PM PDT 24
Peak memory 217244 kb
Host smart-eeb62918-82a3-4c78-bed5-f51727563202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526456081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2526456081
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2498982578
Short name T393
Test name
Test status
Simulation time 73175767 ps
CPU time 1.3 seconds
Started Jul 25 06:06:16 PM PDT 24
Finished Jul 25 06:06:17 PM PDT 24
Peak memory 219992 kb
Host smart-8fd17e5a-0f3b-4c22-96a2-9ec92649a136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498982578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2498982578
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.442413613
Short name T345
Test name
Test status
Simulation time 79694306 ps
CPU time 2.07 seconds
Started Jul 25 06:06:14 PM PDT 24
Finished Jul 25 06:06:16 PM PDT 24
Peak memory 219992 kb
Host smart-7aaeacc8-e64f-4721-9dbc-f41c90c89627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442413613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.442413613
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.1193887344
Short name T669
Test name
Test status
Simulation time 25768253 ps
CPU time 1.08 seconds
Started Jul 25 06:06:17 PM PDT 24
Finished Jul 25 06:06:18 PM PDT 24
Peak memory 218444 kb
Host smart-2389218c-a51a-4b7e-88b5-ab7235cbb7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193887344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.1193887344
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.2504196379
Short name T895
Test name
Test status
Simulation time 60032550 ps
CPU time 2.2 seconds
Started Jul 25 06:06:16 PM PDT 24
Finished Jul 25 06:06:18 PM PDT 24
Peak memory 218388 kb
Host smart-24c7a623-ec4c-41d9-b69d-cacfe2e7c628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504196379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2504196379
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.3606366105
Short name T662
Test name
Test status
Simulation time 25846422 ps
CPU time 1.15 seconds
Started Jul 25 06:06:17 PM PDT 24
Finished Jul 25 06:06:19 PM PDT 24
Peak memory 215596 kb
Host smart-1975a71d-79f3-413c-b252-316065c53e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606366105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.3606366105
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3293785696
Short name T538
Test name
Test status
Simulation time 29038456 ps
CPU time 1.23 seconds
Started Jul 25 06:06:14 PM PDT 24
Finished Jul 25 06:06:16 PM PDT 24
Peak memory 219840 kb
Host smart-42b59dfc-55d3-4ff2-aa05-b6bd83186630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293785696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3293785696
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.350685155
Short name T659
Test name
Test status
Simulation time 37938513 ps
CPU time 1.35 seconds
Started Jul 25 06:06:17 PM PDT 24
Finished Jul 25 06:06:18 PM PDT 24
Peak memory 217028 kb
Host smart-2246f3aa-9870-4700-9603-3e6e4d27d56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350685155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.350685155
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.310887658
Short name T446
Test name
Test status
Simulation time 37699409 ps
CPU time 1.13 seconds
Started Jul 25 06:06:16 PM PDT 24
Finished Jul 25 06:06:17 PM PDT 24
Peak memory 219816 kb
Host smart-8fb8c648-7b6e-45fc-b839-2699ed20c7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310887658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.310887658
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.377627389
Short name T319
Test name
Test status
Simulation time 102190786 ps
CPU time 1.38 seconds
Started Jul 25 06:06:13 PM PDT 24
Finished Jul 25 06:06:14 PM PDT 24
Peak memory 217196 kb
Host smart-b2792631-d656-4cec-a2a3-6f19cf1ed670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377627389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.377627389
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1833404003
Short name T781
Test name
Test status
Simulation time 21435166 ps
CPU time 1.11 seconds
Started Jul 25 06:06:12 PM PDT 24
Finished Jul 25 06:06:13 PM PDT 24
Peak memory 220632 kb
Host smart-c53ea2e9-10c5-43e8-bbd2-3fbb5276ad02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833404003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1833404003
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.1336268607
Short name T953
Test name
Test status
Simulation time 50754480 ps
CPU time 1.59 seconds
Started Jul 25 06:06:15 PM PDT 24
Finished Jul 25 06:06:16 PM PDT 24
Peak memory 217032 kb
Host smart-3a43aa67-c8d0-4f75-8ceb-6ea192a74f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336268607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1336268607
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1530297914
Short name T162
Test name
Test status
Simulation time 73641664 ps
CPU time 1.11 seconds
Started Jul 25 06:03:53 PM PDT 24
Finished Jul 25 06:03:54 PM PDT 24
Peak memory 220504 kb
Host smart-82f7d3b4-4b61-46fa-8c1c-0fdbb4601bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530297914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1530297914
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2339537234
Short name T595
Test name
Test status
Simulation time 17526716 ps
CPU time 0.98 seconds
Started Jul 25 06:03:55 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 214856 kb
Host smart-9255fae3-3b6a-4908-b3a7-543d1cdffe2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339537234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2339537234
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2948612367
Short name T724
Test name
Test status
Simulation time 12567272 ps
CPU time 0.9 seconds
Started Jul 25 06:03:52 PM PDT 24
Finished Jul 25 06:03:53 PM PDT 24
Peak memory 215996 kb
Host smart-f6eb7b17-874f-4e4b-9ff4-8b70959bce33
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948612367 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2948612367
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2282256894
Short name T705
Test name
Test status
Simulation time 30379140 ps
CPU time 1.15 seconds
Started Jul 25 06:03:54 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 216704 kb
Host smart-34e413b4-ee5e-4f28-8ac7-84c9e44f4fce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282256894 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2282256894
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3330002195
Short name T579
Test name
Test status
Simulation time 88546941 ps
CPU time 1.19 seconds
Started Jul 25 06:03:55 PM PDT 24
Finished Jul 25 06:03:57 PM PDT 24
Peak memory 225680 kb
Host smart-f16dde75-a94a-4cc3-b711-30ae6e7ee49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330002195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3330002195
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.54981363
Short name T275
Test name
Test status
Simulation time 110227075 ps
CPU time 2.7 seconds
Started Jul 25 06:03:44 PM PDT 24
Finished Jul 25 06:03:47 PM PDT 24
Peak memory 219384 kb
Host smart-788d3238-619a-436a-9c75-a02cb27948c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54981363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.54981363
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.805526106
Short name T870
Test name
Test status
Simulation time 23560238 ps
CPU time 1 seconds
Started Jul 25 06:03:56 PM PDT 24
Finished Jul 25 06:03:57 PM PDT 24
Peak memory 215768 kb
Host smart-e180f371-503d-4ee1-9857-4bedc5fccde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805526106 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.805526106
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1359317549
Short name T79
Test name
Test status
Simulation time 63636955 ps
CPU time 0.91 seconds
Started Jul 25 06:03:44 PM PDT 24
Finished Jul 25 06:03:45 PM PDT 24
Peak memory 206956 kb
Host smart-f90a9eda-02fd-4309-aa09-513091677d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359317549 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1359317549
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.1406202344
Short name T815
Test name
Test status
Simulation time 40625689 ps
CPU time 0.89 seconds
Started Jul 25 06:03:41 PM PDT 24
Finished Jul 25 06:03:42 PM PDT 24
Peak memory 215200 kb
Host smart-537b6ca5-63ef-4b7f-bf91-d01b2490b0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406202344 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1406202344
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3468581397
Short name T380
Test name
Test status
Simulation time 493989852 ps
CPU time 3.22 seconds
Started Jul 25 06:03:50 PM PDT 24
Finished Jul 25 06:03:54 PM PDT 24
Peak memory 217052 kb
Host smart-2b62d40f-a88f-433f-ba86-bbe9bcb1f4d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468581397 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3468581397
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1999665539
Short name T617
Test name
Test status
Simulation time 152738680553 ps
CPU time 1883.15 seconds
Started Jul 25 06:03:53 PM PDT 24
Finished Jul 25 06:35:16 PM PDT 24
Peak memory 226304 kb
Host smart-017301e2-9e9b-473d-a952-93778a69afa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999665539 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1999665539
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3556441825
Short name T260
Test name
Test status
Simulation time 91442373 ps
CPU time 1.19 seconds
Started Jul 25 06:04:33 PM PDT 24
Finished Jul 25 06:04:34 PM PDT 24
Peak memory 218296 kb
Host smart-e2472da6-f4c3-4ba9-91e1-8c1839e7c293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556441825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3556441825
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1848286631
Short name T908
Test name
Test status
Simulation time 30765347 ps
CPU time 0.81 seconds
Started Jul 25 06:04:22 PM PDT 24
Finished Jul 25 06:04:23 PM PDT 24
Peak memory 206248 kb
Host smart-12aae199-08f6-4f62-ada3-e98aed4b00f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848286631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1848286631
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2220318410
Short name T835
Test name
Test status
Simulation time 64822674 ps
CPU time 1.22 seconds
Started Jul 25 06:04:21 PM PDT 24
Finished Jul 25 06:04:22 PM PDT 24
Peak memory 216900 kb
Host smart-bc1f6075-8e8c-4be8-8511-22b519551726
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220318410 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2220318410
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3906881350
Short name T187
Test name
Test status
Simulation time 18089648 ps
CPU time 1.13 seconds
Started Jul 25 06:04:21 PM PDT 24
Finished Jul 25 06:04:23 PM PDT 24
Peak memory 223912 kb
Host smart-8f997082-dba9-4f1a-b1ab-3559b0f94f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906881350 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3906881350
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1499177916
Short name T493
Test name
Test status
Simulation time 34381536 ps
CPU time 1.26 seconds
Started Jul 25 06:04:21 PM PDT 24
Finished Jul 25 06:04:22 PM PDT 24
Peak memory 218268 kb
Host smart-d8fae535-9330-4261-a0e4-7559fea89ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499177916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1499177916
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.225485515
Short name T820
Test name
Test status
Simulation time 48492392 ps
CPU time 0.83 seconds
Started Jul 25 06:04:21 PM PDT 24
Finished Jul 25 06:04:22 PM PDT 24
Peak memory 215428 kb
Host smart-b29ecce4-4796-4f9e-9bfc-bddd83ed8f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225485515 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.225485515
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.727161387
Short name T977
Test name
Test status
Simulation time 14669778 ps
CPU time 1 seconds
Started Jul 25 06:04:22 PM PDT 24
Finished Jul 25 06:04:23 PM PDT 24
Peak memory 215180 kb
Host smart-f3340f9f-8473-49ac-a4a2-349c53596421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727161387 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.727161387
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2744769044
Short name T951
Test name
Test status
Simulation time 194713576 ps
CPU time 3.07 seconds
Started Jul 25 06:04:21 PM PDT 24
Finished Jul 25 06:04:24 PM PDT 24
Peak memory 218356 kb
Host smart-2bf94b4c-c181-4fb9-a32d-67e659b4efcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744769044 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2744769044
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1779199848
Short name T223
Test name
Test status
Simulation time 122224603431 ps
CPU time 1650.79 seconds
Started Jul 25 06:04:29 PM PDT 24
Finished Jul 25 06:32:00 PM PDT 24
Peak memory 224760 kb
Host smart-f2e98d84-b907-4796-9bb0-ed258c932c79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779199848 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1779199848
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.4138413452
Short name T309
Test name
Test status
Simulation time 285675613 ps
CPU time 1.13 seconds
Started Jul 25 06:06:19 PM PDT 24
Finished Jul 25 06:06:20 PM PDT 24
Peak memory 217088 kb
Host smart-cd26a7df-8aee-42f0-aa8f-9c942df822a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138413452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.4138413452
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2198591470
Short name T357
Test name
Test status
Simulation time 39391312 ps
CPU time 1.38 seconds
Started Jul 25 06:06:18 PM PDT 24
Finished Jul 25 06:06:20 PM PDT 24
Peak memory 218220 kb
Host smart-58f8a65e-3c77-428f-a9b5-a7ef53b064d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198591470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2198591470
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3896880796
Short name T627
Test name
Test status
Simulation time 67955787 ps
CPU time 1.11 seconds
Started Jul 25 06:06:15 PM PDT 24
Finished Jul 25 06:06:16 PM PDT 24
Peak memory 217076 kb
Host smart-0bea7be0-aeb0-4a9f-a757-4fffa1c2fd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896880796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3896880796
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2533561216
Short name T777
Test name
Test status
Simulation time 115274063 ps
CPU time 1.53 seconds
Started Jul 25 06:06:20 PM PDT 24
Finished Jul 25 06:06:21 PM PDT 24
Peak memory 219640 kb
Host smart-f27f9b8c-2bfe-433d-a5eb-9960e243b695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533561216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2533561216
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2139501801
Short name T933
Test name
Test status
Simulation time 94998993 ps
CPU time 1.41 seconds
Started Jul 25 06:06:18 PM PDT 24
Finished Jul 25 06:06:20 PM PDT 24
Peak memory 218396 kb
Host smart-99f2cba9-6986-407a-bc4f-e11c12167458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139501801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2139501801
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.4095771838
Short name T477
Test name
Test status
Simulation time 41755717 ps
CPU time 1.46 seconds
Started Jul 25 06:06:19 PM PDT 24
Finished Jul 25 06:06:21 PM PDT 24
Peak memory 218384 kb
Host smart-bfdf1a49-13d5-4f2e-aec3-b33e9dac1cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095771838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.4095771838
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1459181239
Short name T326
Test name
Test status
Simulation time 71650691 ps
CPU time 1.22 seconds
Started Jul 25 06:06:20 PM PDT 24
Finished Jul 25 06:06:21 PM PDT 24
Peak memory 218372 kb
Host smart-27b6b255-44d1-42c2-a4ba-c9794b49c4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459181239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1459181239
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2270793258
Short name T305
Test name
Test status
Simulation time 36578841 ps
CPU time 1.44 seconds
Started Jul 25 06:06:22 PM PDT 24
Finished Jul 25 06:06:23 PM PDT 24
Peak memory 218500 kb
Host smart-322ff5b5-94a1-421d-a542-e2bf94b4654e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270793258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2270793258
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2083051458
Short name T421
Test name
Test status
Simulation time 41278053 ps
CPU time 1.54 seconds
Started Jul 25 06:06:20 PM PDT 24
Finished Jul 25 06:06:22 PM PDT 24
Peak memory 218552 kb
Host smart-f8a5106a-1313-46c0-8b46-7b7f3b47c6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083051458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2083051458
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1850880122
Short name T858
Test name
Test status
Simulation time 79220826 ps
CPU time 1.17 seconds
Started Jul 25 06:06:19 PM PDT 24
Finished Jul 25 06:06:20 PM PDT 24
Peak memory 219808 kb
Host smart-d0ad57d8-bf1e-47bf-a53e-5312bf8c63be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850880122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1850880122
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.584724641
Short name T898
Test name
Test status
Simulation time 243530664 ps
CPU time 1.27 seconds
Started Jul 25 06:04:21 PM PDT 24
Finished Jul 25 06:04:22 PM PDT 24
Peak memory 220996 kb
Host smart-0fd2afe0-adda-4fda-854d-981f497726e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584724641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.584724641
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2017564424
Short name T893
Test name
Test status
Simulation time 15817545 ps
CPU time 0.91 seconds
Started Jul 25 06:04:23 PM PDT 24
Finished Jul 25 06:04:24 PM PDT 24
Peak memory 206644 kb
Host smart-e4a4b889-2320-4d01-ada4-b6dce79087ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017564424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2017564424
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2906157270
Short name T198
Test name
Test status
Simulation time 13638696 ps
CPU time 0.89 seconds
Started Jul 25 06:04:23 PM PDT 24
Finished Jul 25 06:04:24 PM PDT 24
Peak memory 216360 kb
Host smart-f9ffd456-0175-4d27-b046-3c8f35905b47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906157270 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2906157270
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1305392408
Short name T53
Test name
Test status
Simulation time 58215929 ps
CPU time 1.18 seconds
Started Jul 25 06:04:25 PM PDT 24
Finished Jul 25 06:04:26 PM PDT 24
Peak memory 216704 kb
Host smart-4472299f-84f8-4e65-bc6e-9666b96cfb24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305392408 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1305392408
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1108488204
Short name T111
Test name
Test status
Simulation time 29541502 ps
CPU time 0.91 seconds
Started Jul 25 06:04:19 PM PDT 24
Finished Jul 25 06:04:21 PM PDT 24
Peak memory 218184 kb
Host smart-37c274b7-f1df-45d3-9ac6-16be5abb13fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108488204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1108488204
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3290298212
Short name T291
Test name
Test status
Simulation time 63751276 ps
CPU time 1.03 seconds
Started Jul 25 06:04:21 PM PDT 24
Finished Jul 25 06:04:22 PM PDT 24
Peak memory 217268 kb
Host smart-9bf42e12-f68a-4e89-88eb-866badd03dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290298212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3290298212
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1326767832
Short name T86
Test name
Test status
Simulation time 102693418 ps
CPU time 0.81 seconds
Started Jul 25 06:04:23 PM PDT 24
Finished Jul 25 06:04:24 PM PDT 24
Peak memory 215416 kb
Host smart-97f7b872-bf17-407a-8153-381fcc9384a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326767832 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1326767832
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1688947953
Short name T95
Test name
Test status
Simulation time 19033550 ps
CPU time 0.92 seconds
Started Jul 25 06:04:25 PM PDT 24
Finished Jul 25 06:04:26 PM PDT 24
Peak memory 215192 kb
Host smart-f4c35f19-fc4f-4a52-a99c-a58bcc9d240a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688947953 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1688947953
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3511766597
Short name T745
Test name
Test status
Simulation time 395904353 ps
CPU time 2.6 seconds
Started Jul 25 06:04:29 PM PDT 24
Finished Jul 25 06:04:31 PM PDT 24
Peak memory 215212 kb
Host smart-94b33784-8897-4d1d-9723-385df090f2f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511766597 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3511766597
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3959561652
Short name T24
Test name
Test status
Simulation time 11108563180 ps
CPU time 259.5 seconds
Started Jul 25 06:04:23 PM PDT 24
Finished Jul 25 06:08:43 PM PDT 24
Peak memory 222172 kb
Host smart-7471f06c-bbe0-41b9-a48a-46b4e96e2089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959561652 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3959561652
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.52881341
Short name T365
Test name
Test status
Simulation time 211400526 ps
CPU time 1.71 seconds
Started Jul 25 06:06:21 PM PDT 24
Finished Jul 25 06:06:23 PM PDT 24
Peak memory 218752 kb
Host smart-41d40b7e-ebe6-4d76-8dcb-7ee9c2b3c3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52881341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.52881341
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2547768920
Short name T788
Test name
Test status
Simulation time 61930534 ps
CPU time 0.95 seconds
Started Jul 25 06:06:18 PM PDT 24
Finished Jul 25 06:06:19 PM PDT 24
Peak memory 217368 kb
Host smart-ead00949-8979-41a2-ba6a-297dd54064f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547768920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2547768920
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3587629351
Short name T729
Test name
Test status
Simulation time 100540214 ps
CPU time 1.29 seconds
Started Jul 25 06:06:17 PM PDT 24
Finished Jul 25 06:06:19 PM PDT 24
Peak memory 218388 kb
Host smart-f3983b21-66f8-4b99-8c96-acc293bb35a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587629351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3587629351
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2987427202
Short name T71
Test name
Test status
Simulation time 75463037 ps
CPU time 1.77 seconds
Started Jul 25 06:06:18 PM PDT 24
Finished Jul 25 06:06:20 PM PDT 24
Peak memory 219936 kb
Host smart-dc84249a-4c12-4c61-9dea-cbdc67bb5071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987427202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2987427202
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1303975882
Short name T36
Test name
Test status
Simulation time 47784440 ps
CPU time 1.3 seconds
Started Jul 25 06:06:20 PM PDT 24
Finished Jul 25 06:06:22 PM PDT 24
Peak memory 219476 kb
Host smart-77febabc-9b12-4760-a48b-2613a03d9a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303975882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1303975882
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.209583656
Short name T697
Test name
Test status
Simulation time 97338073 ps
CPU time 2.1 seconds
Started Jul 25 06:06:21 PM PDT 24
Finished Jul 25 06:06:23 PM PDT 24
Peak memory 218572 kb
Host smart-cd520477-3a33-452a-8350-c211f2ccc17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209583656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.209583656
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1457067805
Short name T339
Test name
Test status
Simulation time 62774882 ps
CPU time 1.29 seconds
Started Jul 25 06:06:19 PM PDT 24
Finished Jul 25 06:06:20 PM PDT 24
Peak memory 217128 kb
Host smart-ffda5e9e-03cf-48c2-998d-292c35a84fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457067805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1457067805
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2095184948
Short name T709
Test name
Test status
Simulation time 174180656 ps
CPU time 2.13 seconds
Started Jul 25 06:06:20 PM PDT 24
Finished Jul 25 06:06:22 PM PDT 24
Peak memory 219104 kb
Host smart-cd5eb401-1ef2-4b85-b6c6-89298f6bbdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095184948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2095184948
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1570718746
Short name T823
Test name
Test status
Simulation time 228197257 ps
CPU time 2.98 seconds
Started Jul 25 06:06:19 PM PDT 24
Finished Jul 25 06:06:22 PM PDT 24
Peak memory 219900 kb
Host smart-3238fb0e-f3d9-4dce-a4dd-a5dcf8204076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570718746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1570718746
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1771781055
Short name T183
Test name
Test status
Simulation time 62644284 ps
CPU time 1.11 seconds
Started Jul 25 06:04:29 PM PDT 24
Finished Jul 25 06:04:30 PM PDT 24
Peak memory 219660 kb
Host smart-e76e39df-8a06-4f67-bf28-fa0ef27daf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771781055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1771781055
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3446954475
Short name T778
Test name
Test status
Simulation time 29599994 ps
CPU time 0.91 seconds
Started Jul 25 06:04:31 PM PDT 24
Finished Jul 25 06:04:32 PM PDT 24
Peak memory 206628 kb
Host smart-d51b60b2-b164-4c0a-a70a-8db915c98a39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446954475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3446954475
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3364075003
Short name T126
Test name
Test status
Simulation time 14457500 ps
CPU time 0.87 seconds
Started Jul 25 06:04:31 PM PDT 24
Finished Jul 25 06:04:32 PM PDT 24
Peak memory 216112 kb
Host smart-888f4a6c-993e-40d2-8175-6170ff476d2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364075003 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3364075003
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2342628786
Short name T642
Test name
Test status
Simulation time 23680125 ps
CPU time 0.95 seconds
Started Jul 25 06:04:30 PM PDT 24
Finished Jul 25 06:04:31 PM PDT 24
Peak memory 219656 kb
Host smart-7358263d-5758-450c-8de1-6947572aa998
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342628786 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2342628786
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2506341636
Short name T529
Test name
Test status
Simulation time 30331946 ps
CPU time 1.19 seconds
Started Jul 25 06:04:32 PM PDT 24
Finished Jul 25 06:04:33 PM PDT 24
Peak memory 219556 kb
Host smart-c92be52f-1563-4f21-9459-381e471981c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506341636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2506341636
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.118408759
Short name T315
Test name
Test status
Simulation time 265526614 ps
CPU time 3.86 seconds
Started Jul 25 06:04:23 PM PDT 24
Finished Jul 25 06:04:27 PM PDT 24
Peak memory 217588 kb
Host smart-0c584595-e93a-4f2b-9fda-0a069d37c70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118408759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.118408759
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2640298621
Short name T737
Test name
Test status
Simulation time 81244230 ps
CPU time 0.85 seconds
Started Jul 25 06:04:25 PM PDT 24
Finished Jul 25 06:04:26 PM PDT 24
Peak memory 215256 kb
Host smart-63ce9f9a-a643-44a1-9d1c-f5750b0d67fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640298621 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2640298621
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3154762040
Short name T750
Test name
Test status
Simulation time 55961621 ps
CPU time 0.91 seconds
Started Jul 25 06:04:21 PM PDT 24
Finished Jul 25 06:04:22 PM PDT 24
Peak memory 215112 kb
Host smart-a87b39f1-b1eb-45e9-b31f-0bd740b46ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154762040 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3154762040
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3637903760
Short name T337
Test name
Test status
Simulation time 114491458 ps
CPU time 2.4 seconds
Started Jul 25 06:04:20 PM PDT 24
Finished Jul 25 06:04:23 PM PDT 24
Peak memory 217164 kb
Host smart-7961b580-eaad-4058-92bc-fcbdac338996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637903760 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3637903760
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.961184165
Short name T218
Test name
Test status
Simulation time 19871947267 ps
CPU time 506.31 seconds
Started Jul 25 06:04:23 PM PDT 24
Finished Jul 25 06:12:49 PM PDT 24
Peak memory 216712 kb
Host smart-64759819-5d18-4f07-a433-65db4c90cb49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961184165 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.961184165
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3889967946
Short name T677
Test name
Test status
Simulation time 49022212 ps
CPU time 1.72 seconds
Started Jul 25 06:06:16 PM PDT 24
Finished Jul 25 06:06:18 PM PDT 24
Peak memory 217440 kb
Host smart-a839483d-e6fc-4d16-8e4d-e51e8463b5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889967946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3889967946
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2545830661
Short name T525
Test name
Test status
Simulation time 29837669 ps
CPU time 1.26 seconds
Started Jul 25 06:06:21 PM PDT 24
Finished Jul 25 06:06:23 PM PDT 24
Peak memory 218268 kb
Host smart-d1b0776c-22b7-4968-9e7a-772300c96b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545830661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2545830661
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.727269448
Short name T443
Test name
Test status
Simulation time 83810219 ps
CPU time 1.28 seconds
Started Jul 25 06:06:19 PM PDT 24
Finished Jul 25 06:06:20 PM PDT 24
Peak memory 217200 kb
Host smart-5dc20615-6b32-4519-944a-b142ac36d900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727269448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.727269448
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3195282831
Short name T513
Test name
Test status
Simulation time 27857057 ps
CPU time 1.18 seconds
Started Jul 25 06:06:17 PM PDT 24
Finished Jul 25 06:06:18 PM PDT 24
Peak memory 217208 kb
Host smart-712aee70-f9b9-4b80-8303-a8def4696c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195282831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3195282831
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.659862915
Short name T387
Test name
Test status
Simulation time 35347228 ps
CPU time 1.64 seconds
Started Jul 25 06:06:19 PM PDT 24
Finished Jul 25 06:06:21 PM PDT 24
Peak memory 218400 kb
Host smart-4cb0ddce-ffec-4dcb-a6f8-3781e98671cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659862915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.659862915
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1144138355
Short name T981
Test name
Test status
Simulation time 143714721 ps
CPU time 1.12 seconds
Started Jul 25 06:06:21 PM PDT 24
Finished Jul 25 06:06:23 PM PDT 24
Peak memory 217288 kb
Host smart-30836245-2a56-41bf-a302-311315a90d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144138355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1144138355
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.993149164
Short name T295
Test name
Test status
Simulation time 43745127 ps
CPU time 1.71 seconds
Started Jul 25 06:06:23 PM PDT 24
Finished Jul 25 06:06:25 PM PDT 24
Peak memory 218560 kb
Host smart-f2314751-eaf9-4c9b-8bc2-ecf925b3b2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993149164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.993149164
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.4094848499
Short name T329
Test name
Test status
Simulation time 125195943 ps
CPU time 2.55 seconds
Started Jul 25 06:06:20 PM PDT 24
Finished Jul 25 06:06:23 PM PDT 24
Peak memory 218688 kb
Host smart-a6ae08d4-a8a6-4471-bddc-5fbc302dab97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094848499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.4094848499
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2883481608
Short name T923
Test name
Test status
Simulation time 114466449 ps
CPU time 1.34 seconds
Started Jul 25 06:06:19 PM PDT 24
Finished Jul 25 06:06:20 PM PDT 24
Peak memory 217112 kb
Host smart-759601a4-2789-4e9d-bcdf-add913e1e4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883481608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2883481608
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1725677657
Short name T665
Test name
Test status
Simulation time 86040432 ps
CPU time 1.21 seconds
Started Jul 25 06:04:32 PM PDT 24
Finished Jul 25 06:04:33 PM PDT 24
Peak memory 218780 kb
Host smart-5ce66987-8200-4b7a-b7fc-810f3fff63d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725677657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1725677657
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.937523960
Short name T522
Test name
Test status
Simulation time 21830998 ps
CPU time 0.92 seconds
Started Jul 25 06:04:33 PM PDT 24
Finished Jul 25 06:04:34 PM PDT 24
Peak memory 214812 kb
Host smart-26eab2c2-4807-4d2f-9abf-f3e9a2281710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937523960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.937523960
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2566253593
Short name T528
Test name
Test status
Simulation time 10335142 ps
CPU time 0.88 seconds
Started Jul 25 06:04:29 PM PDT 24
Finished Jul 25 06:04:30 PM PDT 24
Peak memory 216116 kb
Host smart-2740a561-9760-403f-a9bc-b660643556b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566253593 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2566253593
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.769045818
Short name T119
Test name
Test status
Simulation time 84650910 ps
CPU time 1.22 seconds
Started Jul 25 06:04:31 PM PDT 24
Finished Jul 25 06:04:32 PM PDT 24
Peak memory 219456 kb
Host smart-ddd04470-666c-45ac-aa85-871506c0718c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769045818 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.769045818
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1221423375
Short name T784
Test name
Test status
Simulation time 38921789 ps
CPU time 1.3 seconds
Started Jul 25 06:04:34 PM PDT 24
Finished Jul 25 06:04:35 PM PDT 24
Peak memory 219848 kb
Host smart-05e06fa8-0cbf-450f-b403-17c712f280a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221423375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1221423375
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.129737611
Short name T970
Test name
Test status
Simulation time 23948967 ps
CPU time 0.97 seconds
Started Jul 25 06:04:31 PM PDT 24
Finished Jul 25 06:04:32 PM PDT 24
Peak memory 215804 kb
Host smart-d75354ae-3032-4ccd-9623-7eaef3924c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129737611 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.129737611
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2382562145
Short name T686
Test name
Test status
Simulation time 36196572 ps
CPU time 0.95 seconds
Started Jul 25 06:04:32 PM PDT 24
Finished Jul 25 06:04:33 PM PDT 24
Peak memory 215184 kb
Host smart-3da159c1-bed1-42a5-b07f-0b7e312932fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382562145 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2382562145
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.969697506
Short name T288
Test name
Test status
Simulation time 151317830 ps
CPU time 3.45 seconds
Started Jul 25 06:04:36 PM PDT 24
Finished Jul 25 06:04:39 PM PDT 24
Peak memory 218160 kb
Host smart-ff96b05f-739a-48b4-b203-a83374c5287f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969697506 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.969697506
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2280667218
Short name T573
Test name
Test status
Simulation time 70321074534 ps
CPU time 310.95 seconds
Started Jul 25 06:04:34 PM PDT 24
Finished Jul 25 06:09:45 PM PDT 24
Peak memory 218436 kb
Host smart-810e3456-7d92-42bf-90db-62c8933c2f7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280667218 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2280667218
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1816748714
Short name T543
Test name
Test status
Simulation time 50406488 ps
CPU time 1.37 seconds
Started Jul 25 06:06:20 PM PDT 24
Finished Jul 25 06:06:21 PM PDT 24
Peak memory 218508 kb
Host smart-128c56ea-55c4-423c-a187-1d14b1eb352a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816748714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1816748714
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3333834968
Short name T687
Test name
Test status
Simulation time 107024105 ps
CPU time 1.06 seconds
Started Jul 25 06:06:19 PM PDT 24
Finished Jul 25 06:06:20 PM PDT 24
Peak memory 217092 kb
Host smart-ea503dff-2d58-45b9-8455-ff2dc7178e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333834968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3333834968
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2780827021
Short name T631
Test name
Test status
Simulation time 45798961 ps
CPU time 1.24 seconds
Started Jul 25 06:06:24 PM PDT 24
Finished Jul 25 06:06:25 PM PDT 24
Peak memory 219600 kb
Host smart-5cb7f573-5a26-4a94-a1fa-e165fc708780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780827021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2780827021
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.385633420
Short name T321
Test name
Test status
Simulation time 193184088 ps
CPU time 2.62 seconds
Started Jul 25 06:06:24 PM PDT 24
Finished Jul 25 06:06:27 PM PDT 24
Peak memory 219984 kb
Host smart-befe4c14-5ec4-4782-93d8-05bef4db523c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385633420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.385633420
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1238996939
Short name T845
Test name
Test status
Simulation time 44070551 ps
CPU time 1.54 seconds
Started Jul 25 06:06:26 PM PDT 24
Finished Jul 25 06:06:27 PM PDT 24
Peak memory 218440 kb
Host smart-4ac3ad68-9244-4c9d-8b7c-a716aa18c48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238996939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1238996939
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.599117449
Short name T926
Test name
Test status
Simulation time 125361934 ps
CPU time 1.48 seconds
Started Jul 25 06:06:30 PM PDT 24
Finished Jul 25 06:06:32 PM PDT 24
Peak memory 218916 kb
Host smart-a3e09aa9-22d5-47c0-850c-b067a0f1e5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599117449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.599117449
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2277287942
Short name T428
Test name
Test status
Simulation time 41306281 ps
CPU time 1.38 seconds
Started Jul 25 06:06:39 PM PDT 24
Finished Jul 25 06:06:40 PM PDT 24
Peak memory 217104 kb
Host smart-b0082da2-363e-42a8-907f-538800dd8c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277287942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2277287942
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2172607821
Short name T954
Test name
Test status
Simulation time 78338575 ps
CPU time 1.14 seconds
Started Jul 25 06:06:32 PM PDT 24
Finished Jul 25 06:06:33 PM PDT 24
Peak memory 217272 kb
Host smart-fd30cbb9-ea2f-4888-8941-89085a98684f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172607821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2172607821
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.978968659
Short name T664
Test name
Test status
Simulation time 45780089 ps
CPU time 1.05 seconds
Started Jul 25 06:04:31 PM PDT 24
Finished Jul 25 06:04:33 PM PDT 24
Peak memory 218520 kb
Host smart-296bb56b-b2b3-4e45-90a1-2d728398db0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978968659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.978968659
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3518929077
Short name T526
Test name
Test status
Simulation time 16104032 ps
CPU time 0.91 seconds
Started Jul 25 06:04:32 PM PDT 24
Finished Jul 25 06:04:33 PM PDT 24
Peak memory 206664 kb
Host smart-398b47eb-b850-4a0f-a105-13eba9733c95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518929077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3518929077
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.239154250
Short name T109
Test name
Test status
Simulation time 33294673 ps
CPU time 0.82 seconds
Started Jul 25 06:04:32 PM PDT 24
Finished Jul 25 06:04:33 PM PDT 24
Peak memory 216056 kb
Host smart-beb8263e-5a12-4d24-b8e8-44df3176ed22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239154250 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.239154250
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.398097863
Short name T361
Test name
Test status
Simulation time 68176160 ps
CPU time 1.07 seconds
Started Jul 25 06:04:32 PM PDT 24
Finished Jul 25 06:04:33 PM PDT 24
Peak memory 216888 kb
Host smart-625dc154-71ec-4303-9067-c4779c84133c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398097863 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.398097863
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.215865552
Short name T20
Test name
Test status
Simulation time 85545853 ps
CPU time 1.1 seconds
Started Jul 25 06:04:32 PM PDT 24
Finished Jul 25 06:04:33 PM PDT 24
Peak memory 219392 kb
Host smart-d8c08807-3fef-41b6-b1a9-dc231d96f9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215865552 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.215865552
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3383006939
Short name T934
Test name
Test status
Simulation time 44639046 ps
CPU time 1.35 seconds
Started Jul 25 06:04:32 PM PDT 24
Finished Jul 25 06:04:34 PM PDT 24
Peak memory 218488 kb
Host smart-95f07ae4-8957-492e-b231-12e150f2bb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383006939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3383006939
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2600919629
Short name T564
Test name
Test status
Simulation time 28885583 ps
CPU time 1.07 seconds
Started Jul 25 06:04:43 PM PDT 24
Finished Jul 25 06:04:44 PM PDT 24
Peak memory 223948 kb
Host smart-9d45e809-4fdf-410d-ad7e-d1be4571826a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600919629 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2600919629
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.620594574
Short name T462
Test name
Test status
Simulation time 32062404 ps
CPU time 0.96 seconds
Started Jul 25 06:04:32 PM PDT 24
Finished Jul 25 06:04:33 PM PDT 24
Peak memory 215176 kb
Host smart-a29d90f7-c43a-4f6a-a6d4-b27572f451e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620594574 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.620594574
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2955971331
Short name T568
Test name
Test status
Simulation time 749242533 ps
CPU time 3.56 seconds
Started Jul 25 06:04:34 PM PDT 24
Finished Jul 25 06:04:37 PM PDT 24
Peak memory 215244 kb
Host smart-13ab6778-bcac-4d9d-b8fa-ae2a6613c024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955971331 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2955971331
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2010840737
Short name T220
Test name
Test status
Simulation time 117207512291 ps
CPU time 2514.82 seconds
Started Jul 25 06:04:30 PM PDT 24
Finished Jul 25 06:46:25 PM PDT 24
Peak memory 228580 kb
Host smart-faec6826-10e7-4062-a21a-e4cc2a4f3e58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010840737 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2010840737
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1297293160
Short name T484
Test name
Test status
Simulation time 64191523 ps
CPU time 1.33 seconds
Started Jul 25 06:06:26 PM PDT 24
Finished Jul 25 06:06:28 PM PDT 24
Peak memory 218296 kb
Host smart-c6fe82fb-72e6-4158-a3f0-bcdcca46b993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297293160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1297293160
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1580791206
Short name T28
Test name
Test status
Simulation time 49152040 ps
CPU time 1.66 seconds
Started Jul 25 06:06:26 PM PDT 24
Finished Jul 25 06:06:27 PM PDT 24
Peak memory 217184 kb
Host smart-1c059c64-12e2-4546-8cbf-6f8776e6abc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580791206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1580791206
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.763880362
Short name T755
Test name
Test status
Simulation time 47132053 ps
CPU time 1.51 seconds
Started Jul 25 06:06:34 PM PDT 24
Finished Jul 25 06:06:35 PM PDT 24
Peak memory 218236 kb
Host smart-08960f75-5fe2-4d74-b249-450675bb1e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763880362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.763880362
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.816186705
Short name T425
Test name
Test status
Simulation time 51960407 ps
CPU time 1.98 seconds
Started Jul 25 06:06:27 PM PDT 24
Finished Jul 25 06:06:29 PM PDT 24
Peak memory 218520 kb
Host smart-073e1a77-967c-424c-81cd-facac5e266db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816186705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.816186705
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1860546488
Short name T336
Test name
Test status
Simulation time 152506373 ps
CPU time 1.52 seconds
Started Jul 25 06:06:25 PM PDT 24
Finished Jul 25 06:06:26 PM PDT 24
Peak memory 218860 kb
Host smart-cb320ca1-61fa-4df3-87a2-48f0f2a11052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860546488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1860546488
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.991940865
Short name T266
Test name
Test status
Simulation time 58875867 ps
CPU time 1.21 seconds
Started Jul 25 06:06:32 PM PDT 24
Finished Jul 25 06:06:34 PM PDT 24
Peak memory 218364 kb
Host smart-e2183aca-fb05-42fd-9200-6ecc292e1744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991940865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.991940865
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1593905199
Short name T810
Test name
Test status
Simulation time 39877692 ps
CPU time 1.2 seconds
Started Jul 25 06:06:28 PM PDT 24
Finished Jul 25 06:06:30 PM PDT 24
Peak memory 217544 kb
Host smart-0b1e4bf2-a243-42af-bf34-6df1141a3f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593905199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1593905199
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1970056931
Short name T296
Test name
Test status
Simulation time 33665804 ps
CPU time 1.47 seconds
Started Jul 25 06:06:26 PM PDT 24
Finished Jul 25 06:06:28 PM PDT 24
Peak memory 217408 kb
Host smart-2b3606d5-f038-4bfa-aa3f-034993b0bb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970056931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1970056931
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3116126236
Short name T701
Test name
Test status
Simulation time 35455577 ps
CPU time 1.6 seconds
Started Jul 25 06:06:29 PM PDT 24
Finished Jul 25 06:06:31 PM PDT 24
Peak memory 218504 kb
Host smart-72ace6bf-96c5-4cda-a322-fecc383d476a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116126236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3116126236
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2287986377
Short name T599
Test name
Test status
Simulation time 68051047 ps
CPU time 1.06 seconds
Started Jul 25 06:06:30 PM PDT 24
Finished Jul 25 06:06:31 PM PDT 24
Peak memory 217224 kb
Host smart-2b67ec21-9e70-4bbf-b28b-91e0d17077b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287986377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2287986377
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1864929732
Short name T175
Test name
Test status
Simulation time 67667954 ps
CPU time 1.18 seconds
Started Jul 25 06:04:46 PM PDT 24
Finished Jul 25 06:04:47 PM PDT 24
Peak memory 219644 kb
Host smart-300f78db-b3c6-4242-803a-14ec2616f4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864929732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1864929732
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.4096654618
Short name T607
Test name
Test status
Simulation time 118826543 ps
CPU time 0.89 seconds
Started Jul 25 06:04:41 PM PDT 24
Finished Jul 25 06:04:43 PM PDT 24
Peak memory 206692 kb
Host smart-e8632a2b-4790-45cb-82cf-438f2a9bca99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096654618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.4096654618
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2535311899
Short name T692
Test name
Test status
Simulation time 30448306 ps
CPU time 0.81 seconds
Started Jul 25 06:04:43 PM PDT 24
Finished Jul 25 06:04:44 PM PDT 24
Peak memory 215296 kb
Host smart-50b82113-f313-4665-a843-387fe596b647
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535311899 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2535311899
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.989491565
Short name T727
Test name
Test status
Simulation time 53202737 ps
CPU time 1.11 seconds
Started Jul 25 06:04:41 PM PDT 24
Finished Jul 25 06:04:42 PM PDT 24
Peak memory 218392 kb
Host smart-71a32b0d-c84c-492c-afa3-ad71661d5e35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989491565 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.989491565
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.341911500
Short name T204
Test name
Test status
Simulation time 33656211 ps
CPU time 1.01 seconds
Started Jul 25 06:04:42 PM PDT 24
Finished Jul 25 06:04:43 PM PDT 24
Peak memory 229312 kb
Host smart-822fea44-9c72-4b8f-a332-28f703cc667c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341911500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.341911500
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.337273019
Short name T292
Test name
Test status
Simulation time 45926609 ps
CPU time 1.11 seconds
Started Jul 25 06:04:33 PM PDT 24
Finished Jul 25 06:04:34 PM PDT 24
Peak memory 217204 kb
Host smart-b6701607-a26a-401c-96e9-d37aa50e5521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337273019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.337273019
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.726713325
Short name T372
Test name
Test status
Simulation time 21715650 ps
CPU time 1.11 seconds
Started Jul 25 06:04:46 PM PDT 24
Finished Jul 25 06:04:47 PM PDT 24
Peak memory 215268 kb
Host smart-d6a2b44e-7997-448f-9cd3-c81c1b495fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726713325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.726713325
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1650473157
Short name T549
Test name
Test status
Simulation time 47844899 ps
CPU time 0.89 seconds
Started Jul 25 06:04:31 PM PDT 24
Finished Jul 25 06:04:32 PM PDT 24
Peak memory 215160 kb
Host smart-eb3b1a05-49b0-4bcc-b432-195428b86777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650473157 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1650473157
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.193469579
Short name T782
Test name
Test status
Simulation time 120401223 ps
CPU time 1.84 seconds
Started Jul 25 06:04:32 PM PDT 24
Finished Jul 25 06:04:34 PM PDT 24
Peak memory 217100 kb
Host smart-6951d10b-6c1b-47c1-a60c-2c60a4b4b69a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193469579 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.193469579
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3252136356
Short name T485
Test name
Test status
Simulation time 303661551292 ps
CPU time 1974.55 seconds
Started Jul 25 06:04:33 PM PDT 24
Finished Jul 25 06:37:27 PM PDT 24
Peak memory 229124 kb
Host smart-94cb8171-a001-4352-afe2-becef58cec15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252136356 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3252136356
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1632300831
Short name T427
Test name
Test status
Simulation time 58969636 ps
CPU time 1.17 seconds
Started Jul 25 06:06:34 PM PDT 24
Finished Jul 25 06:06:36 PM PDT 24
Peak memory 218476 kb
Host smart-67d385a2-a172-425d-bdd0-e2adce9ee3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632300831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1632300831
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.3986764839
Short name T803
Test name
Test status
Simulation time 48499660 ps
CPU time 1.27 seconds
Started Jul 25 06:06:28 PM PDT 24
Finished Jul 25 06:06:29 PM PDT 24
Peak memory 219416 kb
Host smart-71ecdc70-789a-4b63-8cfc-8febfff227de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986764839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3986764839
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3991576633
Short name T672
Test name
Test status
Simulation time 54091191 ps
CPU time 1.32 seconds
Started Jul 25 06:06:27 PM PDT 24
Finished Jul 25 06:06:28 PM PDT 24
Peak memory 219836 kb
Host smart-29c7e466-7c6e-4bc8-9290-96da3cfc7c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991576633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3991576633
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2216139685
Short name T819
Test name
Test status
Simulation time 169494233 ps
CPU time 3.42 seconds
Started Jul 25 06:06:30 PM PDT 24
Finished Jul 25 06:06:34 PM PDT 24
Peak memory 217324 kb
Host smart-6d9d09cc-22f7-4c88-a3f0-1913c481b335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216139685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2216139685
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1097428422
Short name T535
Test name
Test status
Simulation time 69450169 ps
CPU time 1.45 seconds
Started Jul 25 06:06:30 PM PDT 24
Finished Jul 25 06:06:32 PM PDT 24
Peak memory 217280 kb
Host smart-e546ba6f-a059-4b85-8660-e56b266a8944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097428422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1097428422
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.4062860552
Short name T50
Test name
Test status
Simulation time 35623683 ps
CPU time 1.4 seconds
Started Jul 25 06:06:27 PM PDT 24
Finished Jul 25 06:06:29 PM PDT 24
Peak memory 218256 kb
Host smart-2e9476e1-1456-47a2-bb8d-ea435643aaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062860552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.4062860552
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.880500185
Short name T571
Test name
Test status
Simulation time 137806696 ps
CPU time 2.31 seconds
Started Jul 25 06:06:26 PM PDT 24
Finished Jul 25 06:06:28 PM PDT 24
Peak memory 217660 kb
Host smart-f9b28327-73d5-4f35-acbb-3fe06756e52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880500185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.880500185
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.514642948
Short name T960
Test name
Test status
Simulation time 49549056 ps
CPU time 1.47 seconds
Started Jul 25 06:06:34 PM PDT 24
Finished Jul 25 06:06:36 PM PDT 24
Peak memory 218280 kb
Host smart-51deee1e-424b-42c0-be0d-112479daf00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514642948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.514642948
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1925418863
Short name T414
Test name
Test status
Simulation time 33073363 ps
CPU time 1.29 seconds
Started Jul 25 06:06:27 PM PDT 24
Finished Jul 25 06:06:28 PM PDT 24
Peak memory 218532 kb
Host smart-498c90ee-b6b3-45d2-ba37-8c785e2bd61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925418863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1925418863
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.4112028820
Short name T770
Test name
Test status
Simulation time 180773615 ps
CPU time 1.41 seconds
Started Jul 25 06:06:28 PM PDT 24
Finished Jul 25 06:06:30 PM PDT 24
Peak memory 218724 kb
Host smart-8647f14a-013b-4b70-9ebd-17f2e1c3a98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112028820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.4112028820
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2679865774
Short name T418
Test name
Test status
Simulation time 31940336 ps
CPU time 1.27 seconds
Started Jul 25 06:04:42 PM PDT 24
Finished Jul 25 06:04:43 PM PDT 24
Peak memory 219224 kb
Host smart-3b4bb2cc-b28d-449f-9467-0b09f944c464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679865774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2679865774
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1757371776
Short name T565
Test name
Test status
Simulation time 18266724 ps
CPU time 0.96 seconds
Started Jul 25 06:04:40 PM PDT 24
Finished Jul 25 06:04:41 PM PDT 24
Peak memory 206760 kb
Host smart-a6384173-7bfb-4f46-9224-e1553c463449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757371776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1757371776
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1617524730
Short name T757
Test name
Test status
Simulation time 39136728 ps
CPU time 0.83 seconds
Started Jul 25 06:04:41 PM PDT 24
Finished Jul 25 06:04:42 PM PDT 24
Peak memory 215900 kb
Host smart-d138bac6-abc9-4073-b051-533e7c67a7dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617524730 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1617524730
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.1382643948
Short name T580
Test name
Test status
Simulation time 30450574 ps
CPU time 1.25 seconds
Started Jul 25 06:04:45 PM PDT 24
Finished Jul 25 06:04:46 PM PDT 24
Peak memory 219620 kb
Host smart-ce245030-bc24-42cb-8cff-ecb703b1eaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382643948 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1382643948
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2668517548
Short name T842
Test name
Test status
Simulation time 25554255 ps
CPU time 1.18 seconds
Started Jul 25 06:04:42 PM PDT 24
Finished Jul 25 06:04:44 PM PDT 24
Peak memory 219784 kb
Host smart-f04c1b75-ae86-42cb-bf17-f6c7132da59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668517548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2668517548
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3535750293
Short name T865
Test name
Test status
Simulation time 23259823 ps
CPU time 1.24 seconds
Started Jul 25 06:04:41 PM PDT 24
Finished Jul 25 06:04:43 PM PDT 24
Peak memory 223952 kb
Host smart-3b134ee8-1aa7-4ae6-8e21-a118ddc02023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535750293 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3535750293
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3740524864
Short name T891
Test name
Test status
Simulation time 25139165 ps
CPU time 0.93 seconds
Started Jul 25 06:04:41 PM PDT 24
Finished Jul 25 06:04:42 PM PDT 24
Peak memory 215240 kb
Host smart-7b1b10aa-29cc-48a9-ae82-8439118e7b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740524864 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3740524864
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.4231856743
Short name T939
Test name
Test status
Simulation time 298714799 ps
CPU time 2.09 seconds
Started Jul 25 06:04:43 PM PDT 24
Finished Jul 25 06:04:46 PM PDT 24
Peak memory 215332 kb
Host smart-76b3a575-eb1f-4872-a5d1-91f5277eb099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231856743 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.4231856743
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1278263149
Short name T216
Test name
Test status
Simulation time 24671996953 ps
CPU time 543.67 seconds
Started Jul 25 06:04:44 PM PDT 24
Finished Jul 25 06:13:48 PM PDT 24
Peak memory 220572 kb
Host smart-09b533ee-b6da-4106-922d-abd22d8f5f7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278263149 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1278263149
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.876775318
Short name T524
Test name
Test status
Simulation time 71122434 ps
CPU time 1.07 seconds
Started Jul 25 06:06:30 PM PDT 24
Finished Jul 25 06:06:31 PM PDT 24
Peak memory 217144 kb
Host smart-0988d292-f31f-4d24-bb2c-17685d13ab36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876775318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.876775318
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2419704045
Short name T459
Test name
Test status
Simulation time 33475770 ps
CPU time 1.05 seconds
Started Jul 25 06:06:38 PM PDT 24
Finished Jul 25 06:06:39 PM PDT 24
Peak memory 219824 kb
Host smart-5146ce17-891b-40a1-a6ac-9efb808220f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419704045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2419704045
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3312268295
Short name T19
Test name
Test status
Simulation time 337101444 ps
CPU time 3.44 seconds
Started Jul 25 06:06:28 PM PDT 24
Finished Jul 25 06:06:32 PM PDT 24
Peak memory 218860 kb
Host smart-796fba84-f409-40cb-a722-1c6ef905c229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312268295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3312268295
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1972429719
Short name T597
Test name
Test status
Simulation time 46604834 ps
CPU time 1.58 seconds
Started Jul 25 06:06:30 PM PDT 24
Finished Jul 25 06:06:32 PM PDT 24
Peak memory 218364 kb
Host smart-729800d7-31a3-4561-b9ad-c4b2a47eb487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972429719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1972429719
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1799600760
Short name T32
Test name
Test status
Simulation time 36251346 ps
CPU time 1.28 seconds
Started Jul 25 06:06:34 PM PDT 24
Finished Jul 25 06:06:36 PM PDT 24
Peak memory 217208 kb
Host smart-734d1a08-7608-4230-9ead-45a2bcdbf66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799600760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1799600760
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.4215820862
Short name T850
Test name
Test status
Simulation time 49677873 ps
CPU time 0.96 seconds
Started Jul 25 06:06:27 PM PDT 24
Finished Jul 25 06:06:28 PM PDT 24
Peak memory 217192 kb
Host smart-09deb248-d632-470a-9e57-fb7c89d32aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215820862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.4215820862
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1453159335
Short name T629
Test name
Test status
Simulation time 151598831 ps
CPU time 3.05 seconds
Started Jul 25 06:06:26 PM PDT 24
Finished Jul 25 06:06:29 PM PDT 24
Peak memory 219752 kb
Host smart-a692d4d6-3639-45e7-bd9e-55f792a3bc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453159335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1453159335
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1800625606
Short name T507
Test name
Test status
Simulation time 55174762 ps
CPU time 1.22 seconds
Started Jul 25 06:06:28 PM PDT 24
Finished Jul 25 06:06:29 PM PDT 24
Peak memory 217224 kb
Host smart-b77624df-2123-4210-a3eb-657bb3bdedec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800625606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1800625606
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1773717765
Short name T660
Test name
Test status
Simulation time 56798504 ps
CPU time 1.38 seconds
Started Jul 25 06:06:26 PM PDT 24
Finished Jul 25 06:06:28 PM PDT 24
Peak memory 219784 kb
Host smart-65fcce9f-57d7-48e8-a34d-cd4d51fdfb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773717765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1773717765
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.4164384477
Short name T719
Test name
Test status
Simulation time 60408321 ps
CPU time 1.5 seconds
Started Jul 25 06:06:28 PM PDT 24
Finished Jul 25 06:06:30 PM PDT 24
Peak memory 218436 kb
Host smart-e4efff3d-bd4c-410c-bf6a-00062746e396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164384477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.4164384477
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.679301634
Short name T264
Test name
Test status
Simulation time 27485418 ps
CPU time 1.24 seconds
Started Jul 25 06:04:43 PM PDT 24
Finished Jul 25 06:04:45 PM PDT 24
Peak memory 219792 kb
Host smart-9e62126a-c073-4cec-93eb-d6892965dcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679301634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.679301634
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1202339970
Short name T732
Test name
Test status
Simulation time 14911858 ps
CPU time 0.95 seconds
Started Jul 25 06:04:43 PM PDT 24
Finished Jul 25 06:04:44 PM PDT 24
Peak memory 206592 kb
Host smart-eb2cffd1-ff9d-4ef6-9ab3-d88aaac8295a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202339970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1202339970
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.4286176047
Short name T583
Test name
Test status
Simulation time 37855073 ps
CPU time 1.28 seconds
Started Jul 25 06:04:42 PM PDT 24
Finished Jul 25 06:04:44 PM PDT 24
Peak memory 216748 kb
Host smart-5f374324-aaab-4811-9617-7458e340d8a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286176047 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.4286176047
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2028911671
Short name T42
Test name
Test status
Simulation time 19619548 ps
CPU time 1.19 seconds
Started Jul 25 06:04:44 PM PDT 24
Finished Jul 25 06:04:45 PM PDT 24
Peak memory 223856 kb
Host smart-f086df44-1e39-45a2-b9ea-3ff6362b27fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028911671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2028911671
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.4176297998
Short name T340
Test name
Test status
Simulation time 98316839 ps
CPU time 1.12 seconds
Started Jul 25 06:04:39 PM PDT 24
Finished Jul 25 06:04:40 PM PDT 24
Peak memory 218288 kb
Host smart-ccbf5bca-5475-4afb-883c-ba4872ea154a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176297998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.4176297998
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1144223913
Short name T506
Test name
Test status
Simulation time 103280718 ps
CPU time 0.92 seconds
Started Jul 25 06:04:43 PM PDT 24
Finished Jul 25 06:04:44 PM PDT 24
Peak memory 223700 kb
Host smart-3ced9914-e8bf-4e24-9246-15a5891dbcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144223913 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1144223913
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.261044684
Short name T930
Test name
Test status
Simulation time 19137154 ps
CPU time 1.09 seconds
Started Jul 25 06:04:45 PM PDT 24
Finished Jul 25 06:04:46 PM PDT 24
Peak memory 215256 kb
Host smart-3e9329a0-3264-4bd8-bc50-8e6435343b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261044684 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.261044684
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.473727597
Short name T985
Test name
Test status
Simulation time 140438372 ps
CPU time 1.25 seconds
Started Jul 25 06:04:42 PM PDT 24
Finished Jul 25 06:04:44 PM PDT 24
Peak memory 218408 kb
Host smart-4aece4ad-30ce-4b15-9614-7e8e0f3c44d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473727597 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.473727597
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1178302421
Short name T634
Test name
Test status
Simulation time 183943785167 ps
CPU time 1621.79 seconds
Started Jul 25 06:04:42 PM PDT 24
Finished Jul 25 06:31:44 PM PDT 24
Peak memory 224352 kb
Host smart-2acfb653-f6fb-473c-bb4c-5b56b1771c7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178302421 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1178302421
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3179357902
Short name T594
Test name
Test status
Simulation time 44191695 ps
CPU time 1.53 seconds
Started Jul 25 06:06:34 PM PDT 24
Finished Jul 25 06:06:36 PM PDT 24
Peak memory 217080 kb
Host smart-b06dcaa3-00f3-42dc-b9f6-9da2c19d028e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179357902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3179357902
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2391049006
Short name T491
Test name
Test status
Simulation time 71534617 ps
CPU time 1.46 seconds
Started Jul 25 06:06:33 PM PDT 24
Finished Jul 25 06:06:35 PM PDT 24
Peak memory 218456 kb
Host smart-601a8329-ffd9-4cc3-8333-e2f47638e0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391049006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2391049006
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.610669282
Short name T368
Test name
Test status
Simulation time 48127539 ps
CPU time 1.52 seconds
Started Jul 25 06:06:35 PM PDT 24
Finished Jul 25 06:06:37 PM PDT 24
Peak memory 218184 kb
Host smart-a372fbf2-3c3d-4565-b252-1a5a773e1f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610669282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.610669282
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.703938935
Short name T843
Test name
Test status
Simulation time 60110259 ps
CPU time 1.37 seconds
Started Jul 25 06:06:34 PM PDT 24
Finished Jul 25 06:06:36 PM PDT 24
Peak memory 218600 kb
Host smart-42a193a5-c295-4bcc-a476-1c28b62fd61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703938935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.703938935
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1734292591
Short name T307
Test name
Test status
Simulation time 42977333 ps
CPU time 1.69 seconds
Started Jul 25 06:06:34 PM PDT 24
Finished Jul 25 06:06:35 PM PDT 24
Peak memory 218332 kb
Host smart-0252a40e-a37f-498f-883e-7a835bde6b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734292591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1734292591
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2703431205
Short name T492
Test name
Test status
Simulation time 44898894 ps
CPU time 1.27 seconds
Started Jul 25 06:06:35 PM PDT 24
Finished Jul 25 06:06:36 PM PDT 24
Peak memory 218364 kb
Host smart-602c909b-1287-4309-b24b-1d4b9eb6d7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703431205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2703431205
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3177371099
Short name T771
Test name
Test status
Simulation time 38359875 ps
CPU time 1.53 seconds
Started Jul 25 06:06:34 PM PDT 24
Finished Jul 25 06:06:36 PM PDT 24
Peak memory 218500 kb
Host smart-db7023e6-708a-4233-9016-f16dd2082959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177371099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3177371099
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.72571370
Short name T735
Test name
Test status
Simulation time 188437549 ps
CPU time 2.41 seconds
Started Jul 25 06:06:35 PM PDT 24
Finished Jul 25 06:06:37 PM PDT 24
Peak memory 220268 kb
Host smart-761a7487-32c9-4ded-a81c-2dea16a22f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72571370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.72571370
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1331868688
Short name T541
Test name
Test status
Simulation time 39788070 ps
CPU time 1.4 seconds
Started Jul 25 06:06:38 PM PDT 24
Finished Jul 25 06:06:40 PM PDT 24
Peak memory 218512 kb
Host smart-a9a4cd7c-4090-4a50-96cf-7400bf0eacb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331868688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1331868688
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1908519630
Short name T287
Test name
Test status
Simulation time 36357925 ps
CPU time 1.41 seconds
Started Jul 25 06:06:33 PM PDT 24
Finished Jul 25 06:06:35 PM PDT 24
Peak memory 218416 kb
Host smart-be1b9a29-6ea9-4ac9-b297-900f0292dbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908519630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1908519630
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.137582034
Short name T706
Test name
Test status
Simulation time 25254475 ps
CPU time 1.2 seconds
Started Jul 25 06:04:41 PM PDT 24
Finished Jul 25 06:04:42 PM PDT 24
Peak memory 218464 kb
Host smart-836037d2-2920-4380-b910-7450f8a3b26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137582034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.137582034
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2324096773
Short name T374
Test name
Test status
Simulation time 24591944 ps
CPU time 0.86 seconds
Started Jul 25 06:04:45 PM PDT 24
Finished Jul 25 06:04:46 PM PDT 24
Peak memory 214860 kb
Host smart-a17b70da-3a7b-438c-b76a-2e40e7b43a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324096773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2324096773
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1158217635
Short name T178
Test name
Test status
Simulation time 27148266 ps
CPU time 0.86 seconds
Started Jul 25 06:04:42 PM PDT 24
Finished Jul 25 06:04:43 PM PDT 24
Peak memory 216144 kb
Host smart-1ebf8539-2a64-473b-9d14-bd86695e1fb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158217635 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1158217635
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1977986621
Short name T546
Test name
Test status
Simulation time 58294475 ps
CPU time 1.23 seconds
Started Jul 25 06:04:42 PM PDT 24
Finished Jul 25 06:04:43 PM PDT 24
Peak memory 216652 kb
Host smart-4a0604f1-2302-47ea-ba1d-74b1aab3456f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977986621 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1977986621
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2228562751
Short name T768
Test name
Test status
Simulation time 31685604 ps
CPU time 0.97 seconds
Started Jul 25 06:05:11 PM PDT 24
Finished Jul 25 06:05:12 PM PDT 24
Peak memory 223704 kb
Host smart-f7876369-acd4-4ecc-a8a9-0bdd1f7e6245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228562751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2228562751
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2864148382
Short name T589
Test name
Test status
Simulation time 34698660 ps
CPU time 1.41 seconds
Started Jul 25 06:04:42 PM PDT 24
Finished Jul 25 06:04:44 PM PDT 24
Peak memory 218384 kb
Host smart-d5f6f20f-72d0-4583-a32a-507711e7e623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864148382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2864148382
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_smoke.3330035793
Short name T736
Test name
Test status
Simulation time 88179745 ps
CPU time 0.91 seconds
Started Jul 25 06:04:40 PM PDT 24
Finished Jul 25 06:04:41 PM PDT 24
Peak memory 215152 kb
Host smart-cd0cb9fa-19ed-4a8c-a10d-a91885b6b5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330035793 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3330035793
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.333295447
Short name T527
Test name
Test status
Simulation time 243317579 ps
CPU time 5.16 seconds
Started Jul 25 06:04:47 PM PDT 24
Finished Jul 25 06:04:53 PM PDT 24
Peak memory 215132 kb
Host smart-f2371844-1261-4a1b-8ad6-4c5f77c048d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333295447 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.333295447
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2110932164
Short name T618
Test name
Test status
Simulation time 75871522547 ps
CPU time 1672.43 seconds
Started Jul 25 06:04:41 PM PDT 24
Finished Jul 25 06:32:34 PM PDT 24
Peak memory 224648 kb
Host smart-f0d64cda-e75b-4399-adb8-73b86a2d9ec4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110932164 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2110932164
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/281.edn_genbits.3719625591
Short name T542
Test name
Test status
Simulation time 36442061 ps
CPU time 1.6 seconds
Started Jul 25 06:06:37 PM PDT 24
Finished Jul 25 06:06:38 PM PDT 24
Peak memory 218676 kb
Host smart-8fbe0f53-006f-4508-9707-48e67fcef4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719625591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3719625591
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1574275112
Short name T619
Test name
Test status
Simulation time 54790483 ps
CPU time 1.05 seconds
Started Jul 25 06:06:33 PM PDT 24
Finished Jul 25 06:06:35 PM PDT 24
Peak memory 217240 kb
Host smart-05d4bf69-a664-4757-8aef-405d241be832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574275112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1574275112
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1187715471
Short name T968
Test name
Test status
Simulation time 110070480 ps
CPU time 1.01 seconds
Started Jul 25 06:06:38 PM PDT 24
Finished Jul 25 06:06:39 PM PDT 24
Peak memory 217156 kb
Host smart-e445f04a-5fb2-4043-a046-6d09506463ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187715471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1187715471
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1702933066
Short name T909
Test name
Test status
Simulation time 87369681 ps
CPU time 1.29 seconds
Started Jul 25 06:06:34 PM PDT 24
Finished Jul 25 06:06:35 PM PDT 24
Peak memory 218692 kb
Host smart-e982ccc1-e66d-492c-b79d-e85da29b93f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702933066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1702933066
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1166869590
Short name T649
Test name
Test status
Simulation time 96349421 ps
CPU time 2.35 seconds
Started Jul 25 06:06:37 PM PDT 24
Finished Jul 25 06:06:39 PM PDT 24
Peak memory 219912 kb
Host smart-53036a12-a398-4a94-986c-52a1a269150f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166869590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1166869590
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2437211683
Short name T299
Test name
Test status
Simulation time 27437594 ps
CPU time 1.13 seconds
Started Jul 25 06:06:37 PM PDT 24
Finished Jul 25 06:06:38 PM PDT 24
Peak memory 218264 kb
Host smart-8601301e-2d08-48ef-a46f-ad59fb2a11b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437211683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2437211683
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3232861428
Short name T553
Test name
Test status
Simulation time 91938125 ps
CPU time 1.44 seconds
Started Jul 25 06:06:33 PM PDT 24
Finished Jul 25 06:06:34 PM PDT 24
Peak memory 218692 kb
Host smart-67100577-d599-46cd-b269-30ebe2584584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232861428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3232861428
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3956428424
Short name T899
Test name
Test status
Simulation time 64422785 ps
CPU time 2.26 seconds
Started Jul 25 06:06:33 PM PDT 24
Finished Jul 25 06:06:36 PM PDT 24
Peak memory 219880 kb
Host smart-48e97a6c-bfc3-41e5-86ee-1b11625b18b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956428424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3956428424
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2745065851
Short name T289
Test name
Test status
Simulation time 162363032 ps
CPU time 1.14 seconds
Started Jul 25 06:06:38 PM PDT 24
Finished Jul 25 06:06:39 PM PDT 24
Peak memory 217100 kb
Host smart-7f960144-722d-4a2e-b334-c7cf0351f56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745065851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2745065851
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1647283592
Short name T151
Test name
Test status
Simulation time 88250611 ps
CPU time 1.23 seconds
Started Jul 25 06:04:42 PM PDT 24
Finished Jul 25 06:04:43 PM PDT 24
Peak memory 219620 kb
Host smart-53680559-baa9-4f77-9656-6d54d9b6e819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647283592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1647283592
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2906878108
Short name T40
Test name
Test status
Simulation time 14342348 ps
CPU time 0.95 seconds
Started Jul 25 06:04:44 PM PDT 24
Finished Jul 25 06:04:45 PM PDT 24
Peak memory 206656 kb
Host smart-238d739b-b652-43c8-b80c-736306177bf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906878108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2906878108
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2620267166
Short name T173
Test name
Test status
Simulation time 12080073 ps
CPU time 0.91 seconds
Started Jul 25 06:04:42 PM PDT 24
Finished Jul 25 06:04:44 PM PDT 24
Peak memory 215464 kb
Host smart-f375c643-34e0-4970-8211-2d8099bc103c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620267166 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2620267166
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.1101389237
Short name T776
Test name
Test status
Simulation time 20039455 ps
CPU time 1.15 seconds
Started Jul 25 06:04:40 PM PDT 24
Finished Jul 25 06:04:41 PM PDT 24
Peak memory 223992 kb
Host smart-6a262916-c49d-4566-9f1e-6180b44b0075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101389237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1101389237
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2493719162
Short name T371
Test name
Test status
Simulation time 46605659 ps
CPU time 1.86 seconds
Started Jul 25 06:04:44 PM PDT 24
Finished Jul 25 06:04:46 PM PDT 24
Peak memory 218484 kb
Host smart-05c5a517-c4f4-4acf-ba2f-132f139e23de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493719162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2493719162
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2478548512
Short name T700
Test name
Test status
Simulation time 21367927 ps
CPU time 1.14 seconds
Started Jul 25 06:04:40 PM PDT 24
Finished Jul 25 06:04:41 PM PDT 24
Peak memory 215764 kb
Host smart-38d6d081-29dd-44eb-987d-7ffa319fd791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478548512 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2478548512
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2462010669
Short name T867
Test name
Test status
Simulation time 15932609 ps
CPU time 0.97 seconds
Started Jul 25 06:04:41 PM PDT 24
Finished Jul 25 06:04:42 PM PDT 24
Peak memory 206956 kb
Host smart-df6d1dde-6016-467d-b459-67ee2e940ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462010669 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2462010669
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.4169400293
Short name T226
Test name
Test status
Simulation time 870103946 ps
CPU time 4.5 seconds
Started Jul 25 06:04:42 PM PDT 24
Finished Jul 25 06:04:47 PM PDT 24
Peak memory 215216 kb
Host smart-9cdd9333-4b56-44d1-bf1e-97078d9ddd68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169400293 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.4169400293
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/290.edn_genbits.2862932452
Short name T793
Test name
Test status
Simulation time 449359018 ps
CPU time 2.72 seconds
Started Jul 25 06:06:36 PM PDT 24
Finished Jul 25 06:06:39 PM PDT 24
Peak memory 217592 kb
Host smart-bae906f7-08c9-4c82-b204-9480fa3034f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862932452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2862932452
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1969058445
Short name T359
Test name
Test status
Simulation time 43009904 ps
CPU time 1.67 seconds
Started Jul 25 06:06:37 PM PDT 24
Finished Jul 25 06:06:39 PM PDT 24
Peak memory 218384 kb
Host smart-b756a94c-bb8e-4497-92a5-c0ee54e3fe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969058445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1969058445
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.413710518
Short name T928
Test name
Test status
Simulation time 38993215 ps
CPU time 1.52 seconds
Started Jul 25 06:06:35 PM PDT 24
Finished Jul 25 06:06:37 PM PDT 24
Peak memory 219796 kb
Host smart-f9a7039f-8c07-4b2d-98c3-5468cd88057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413710518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.413710518
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.140915178
Short name T354
Test name
Test status
Simulation time 46331420 ps
CPU time 1.45 seconds
Started Jul 25 06:06:36 PM PDT 24
Finished Jul 25 06:06:37 PM PDT 24
Peak memory 218680 kb
Host smart-133b71e5-d111-46cf-b672-ce5448520f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140915178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.140915178
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3708731539
Short name T875
Test name
Test status
Simulation time 76403659 ps
CPU time 1.03 seconds
Started Jul 25 06:06:34 PM PDT 24
Finished Jul 25 06:06:35 PM PDT 24
Peak memory 217316 kb
Host smart-f985cd3a-1c59-4eac-b459-22df96e71d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708731539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3708731539
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1798184722
Short name T795
Test name
Test status
Simulation time 35092886 ps
CPU time 1.46 seconds
Started Jul 25 06:06:42 PM PDT 24
Finished Jul 25 06:06:44 PM PDT 24
Peak memory 218356 kb
Host smart-0983e8d8-6cc1-4862-92b1-a6807c3e1a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798184722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1798184722
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3164295440
Short name T962
Test name
Test status
Simulation time 37248593 ps
CPU time 1.3 seconds
Started Jul 25 06:06:35 PM PDT 24
Finished Jul 25 06:06:37 PM PDT 24
Peak memory 219372 kb
Host smart-32c30891-baf3-4df6-b713-7fdfee3c07c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164295440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3164295440
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3494852288
Short name T903
Test name
Test status
Simulation time 72734732 ps
CPU time 1.09 seconds
Started Jul 25 06:06:35 PM PDT 24
Finished Jul 25 06:06:37 PM PDT 24
Peak memory 217208 kb
Host smart-92723e87-6c1b-4bda-b7e4-1e92f3c4a8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494852288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3494852288
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.4033634260
Short name T355
Test name
Test status
Simulation time 48625804 ps
CPU time 1.61 seconds
Started Jul 25 06:06:35 PM PDT 24
Finished Jul 25 06:06:36 PM PDT 24
Peak memory 218464 kb
Host smart-87e284fb-405e-439e-ac33-d17d5216f89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033634260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.4033634260
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2427313641
Short name T311
Test name
Test status
Simulation time 66596429 ps
CPU time 1.25 seconds
Started Jul 25 06:06:38 PM PDT 24
Finished Jul 25 06:06:39 PM PDT 24
Peak memory 218780 kb
Host smart-0fe8f7d0-7773-4e27-a869-aace505f236a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427313641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2427313641
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.326513716
Short name T799
Test name
Test status
Simulation time 53825204 ps
CPU time 1.24 seconds
Started Jul 25 06:03:56 PM PDT 24
Finished Jul 25 06:03:57 PM PDT 24
Peak memory 215496 kb
Host smart-84e38b90-fb6d-4317-916a-a8f21a7f4ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326513716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.326513716
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2688374714
Short name T624
Test name
Test status
Simulation time 25638755 ps
CPU time 0.91 seconds
Started Jul 25 06:03:52 PM PDT 24
Finished Jul 25 06:03:54 PM PDT 24
Peak memory 215100 kb
Host smart-764e5d14-0380-437c-b994-d715b07e15ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688374714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2688374714
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.65295059
Short name T276
Test name
Test status
Simulation time 34762411 ps
CPU time 1.21 seconds
Started Jul 25 06:03:55 PM PDT 24
Finished Jul 25 06:03:57 PM PDT 24
Peak memory 216676 kb
Host smart-c2fb4d7b-57be-4daa-97b2-c6946691b26f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65295059 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disa
ble_auto_req_mode.65295059
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1727077340
Short name T680
Test name
Test status
Simulation time 32967896 ps
CPU time 1.11 seconds
Started Jul 25 06:03:57 PM PDT 24
Finished Jul 25 06:03:58 PM PDT 24
Peak memory 220340 kb
Host smart-6105b07f-f1f8-4180-b029-6337f12be17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727077340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1727077340
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.776469580
Short name T753
Test name
Test status
Simulation time 56398426 ps
CPU time 1.78 seconds
Started Jul 25 06:03:54 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 215200 kb
Host smart-bdb5bb7e-540a-49c2-aabc-5d4ef6801b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776469580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.776469580
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2996314931
Short name T402
Test name
Test status
Simulation time 22453860 ps
CPU time 1.07 seconds
Started Jul 25 06:03:56 PM PDT 24
Finished Jul 25 06:03:57 PM PDT 24
Peak memory 215800 kb
Host smart-980a419b-cecc-41ec-8eb5-10405abbae96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996314931 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2996314931
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.880436186
Short name T882
Test name
Test status
Simulation time 21067289 ps
CPU time 0.94 seconds
Started Jul 25 06:03:55 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 206996 kb
Host smart-5d3f83f6-76e3-4bc9-b5c2-f87e4e0f4b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880436186 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.880436186
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.1297337635
Short name T342
Test name
Test status
Simulation time 16984004 ps
CPU time 0.95 seconds
Started Jul 25 06:03:51 PM PDT 24
Finished Jul 25 06:03:52 PM PDT 24
Peak memory 215164 kb
Host smart-26be087f-3f14-4d98-8845-ff55abf7b413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297337635 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1297337635
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2720238529
Short name T230
Test name
Test status
Simulation time 152846874 ps
CPU time 3.66 seconds
Started Jul 25 06:03:54 PM PDT 24
Finished Jul 25 06:03:58 PM PDT 24
Peak memory 215148 kb
Host smart-85eeae53-ec42-4a50-bef0-339f0f7e6300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720238529 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2720238529
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3751674991
Short name T792
Test name
Test status
Simulation time 73880288266 ps
CPU time 815.25 seconds
Started Jul 25 06:03:55 PM PDT 24
Finished Jul 25 06:17:31 PM PDT 24
Peak memory 220652 kb
Host smart-f1e0e9e0-0d06-4a3f-aa16-d7d1c91f8a7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751674991 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3751674991
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2169805281
Short name T105
Test name
Test status
Simulation time 52769942 ps
CPU time 1.21 seconds
Started Jul 25 06:04:46 PM PDT 24
Finished Jul 25 06:04:48 PM PDT 24
Peak memory 215676 kb
Host smart-23801e7f-6627-4251-8cf3-15d30ab20ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169805281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2169805281
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1038532609
Short name T760
Test name
Test status
Simulation time 23181296 ps
CPU time 0.85 seconds
Started Jul 25 06:04:44 PM PDT 24
Finished Jul 25 06:04:45 PM PDT 24
Peak memory 206648 kb
Host smart-0f926f8c-3953-48fb-9651-c56dc1630e84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038532609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1038532609
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.20675051
Short name T533
Test name
Test status
Simulation time 44577240 ps
CPU time 0.83 seconds
Started Jul 25 06:04:45 PM PDT 24
Finished Jul 25 06:04:46 PM PDT 24
Peak memory 215920 kb
Host smart-05eb2110-fbd4-4216-ba59-44bc36d83c31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20675051 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.20675051
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.581847093
Short name T18
Test name
Test status
Simulation time 65683844 ps
CPU time 1.1 seconds
Started Jul 25 06:04:45 PM PDT 24
Finished Jul 25 06:04:47 PM PDT 24
Peak memory 216828 kb
Host smart-56f05d67-ea37-4bbd-9388-e5373ba20ced
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581847093 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.581847093
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.4005914901
Short name T574
Test name
Test status
Simulation time 37598678 ps
CPU time 0.86 seconds
Started Jul 25 06:04:44 PM PDT 24
Finished Jul 25 06:04:45 PM PDT 24
Peak memory 218184 kb
Host smart-a3c755d3-9f15-4f24-b733-ad758e2c3478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005914901 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.4005914901
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1883294330
Short name T956
Test name
Test status
Simulation time 139845884 ps
CPU time 3.03 seconds
Started Jul 25 06:04:52 PM PDT 24
Finished Jul 25 06:04:55 PM PDT 24
Peak memory 219864 kb
Host smart-94b5887b-1bdd-433c-9155-f5361256c412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883294330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1883294330
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1774797242
Short name T433
Test name
Test status
Simulation time 22750225 ps
CPU time 1.16 seconds
Started Jul 25 06:04:43 PM PDT 24
Finished Jul 25 06:04:45 PM PDT 24
Peak memory 223952 kb
Host smart-715bd2dc-acb7-4127-8c28-6cd1e246b24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774797242 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1774797242
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1734400545
Short name T394
Test name
Test status
Simulation time 23397754 ps
CPU time 0.93 seconds
Started Jul 25 06:04:42 PM PDT 24
Finished Jul 25 06:04:43 PM PDT 24
Peak memory 215160 kb
Host smart-891e3aa1-372d-46c2-84fc-fab7e7dbb75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734400545 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1734400545
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.530911125
Short name T544
Test name
Test status
Simulation time 546210746 ps
CPU time 6.11 seconds
Started Jul 25 06:04:44 PM PDT 24
Finished Jul 25 06:04:50 PM PDT 24
Peak memory 217088 kb
Host smart-289fcd35-26c5-41b6-8c08-e773b33f8622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530911125 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.530911125
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_alert.2990344196
Short name T163
Test name
Test status
Simulation time 24891449 ps
CPU time 1.17 seconds
Started Jul 25 06:04:43 PM PDT 24
Finished Jul 25 06:04:44 PM PDT 24
Peak memory 218468 kb
Host smart-53991ed2-461b-46ac-9b80-74bdf502aa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990344196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2990344196
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3963927449
Short name T708
Test name
Test status
Simulation time 13549488 ps
CPU time 0.85 seconds
Started Jul 25 06:04:44 PM PDT 24
Finished Jul 25 06:04:45 PM PDT 24
Peak memory 206596 kb
Host smart-176f38c6-614c-4e38-98bd-e0c724933f54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963927449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3963927449
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2852462874
Short name T207
Test name
Test status
Simulation time 13270081 ps
CPU time 0.91 seconds
Started Jul 25 06:04:46 PM PDT 24
Finished Jul 25 06:04:47 PM PDT 24
Peak memory 215440 kb
Host smart-e23c803f-a65d-4926-a87a-1ebaf0a87c30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852462874 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2852462874
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.3679010040
Short name T137
Test name
Test status
Simulation time 20087005 ps
CPU time 1.08 seconds
Started Jul 25 06:04:48 PM PDT 24
Finished Jul 25 06:04:49 PM PDT 24
Peak memory 217648 kb
Host smart-0be2885a-d54b-4e48-9d14-d6efa95449d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679010040 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3679010040
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2618756000
Short name T322
Test name
Test status
Simulation time 26760225 ps
CPU time 1.3 seconds
Started Jul 25 06:04:44 PM PDT 24
Finished Jul 25 06:04:45 PM PDT 24
Peak memory 219804 kb
Host smart-db079eeb-35ed-4bed-a975-c46c3ecdc43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618756000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2618756000
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2364927410
Short name T57
Test name
Test status
Simulation time 26030841 ps
CPU time 1.07 seconds
Started Jul 25 06:04:43 PM PDT 24
Finished Jul 25 06:04:44 PM PDT 24
Peak memory 215288 kb
Host smart-34887134-3404-4553-a498-4a2241a78268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364927410 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2364927410
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.251881712
Short name T323
Test name
Test status
Simulation time 31847026 ps
CPU time 0.92 seconds
Started Jul 25 06:04:47 PM PDT 24
Finished Jul 25 06:04:48 PM PDT 24
Peak memory 215180 kb
Host smart-92a0f5c3-ae98-40fe-b629-a620a8c45282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251881712 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.251881712
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1196405728
Short name T811
Test name
Test status
Simulation time 334317608 ps
CPU time 3.07 seconds
Started Jul 25 06:04:48 PM PDT 24
Finished Jul 25 06:04:51 PM PDT 24
Peak memory 214460 kb
Host smart-e255e436-daf4-4e6f-a6b4-baec3df18bb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196405728 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1196405728
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2013756871
Short name T651
Test name
Test status
Simulation time 36581969227 ps
CPU time 833.39 seconds
Started Jul 25 06:04:46 PM PDT 24
Finished Jul 25 06:18:39 PM PDT 24
Peak memory 218024 kb
Host smart-f00b366b-b507-4111-966e-47c66cca65d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013756871 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2013756871
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.928087361
Short name T237
Test name
Test status
Simulation time 77163589 ps
CPU time 1.16 seconds
Started Jul 25 06:04:45 PM PDT 24
Finished Jul 25 06:04:47 PM PDT 24
Peak memory 218556 kb
Host smart-d4fa7996-6dc6-431a-8853-ef56845a7aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928087361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.928087361
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3653818055
Short name T99
Test name
Test status
Simulation time 25936289 ps
CPU time 1 seconds
Started Jul 25 06:04:55 PM PDT 24
Finished Jul 25 06:04:56 PM PDT 24
Peak memory 206704 kb
Host smart-6930e5a7-d4c1-49d7-87f8-e883402657a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653818055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3653818055
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3470600516
Short name T798
Test name
Test status
Simulation time 14099240 ps
CPU time 0.94 seconds
Started Jul 25 06:04:50 PM PDT 24
Finished Jul 25 06:04:51 PM PDT 24
Peak memory 216304 kb
Host smart-610aff7a-5716-424a-a474-1770c88b6192
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470600516 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3470600516
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2333293048
Short name T894
Test name
Test status
Simulation time 129722692 ps
CPU time 1.21 seconds
Started Jul 25 06:04:56 PM PDT 24
Finished Jul 25 06:04:57 PM PDT 24
Peak memory 216892 kb
Host smart-373f8580-7160-4b74-ba53-f9805ddef1ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333293048 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2333293048
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2568168645
Short name T982
Test name
Test status
Simulation time 28844475 ps
CPU time 1.03 seconds
Started Jul 25 06:04:52 PM PDT 24
Finished Jul 25 06:04:53 PM PDT 24
Peak memory 219444 kb
Host smart-62c17c85-af1b-4eb5-81de-aa337fb7660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568168645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2568168645
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3017168469
Short name T234
Test name
Test status
Simulation time 50244809 ps
CPU time 0.93 seconds
Started Jul 25 06:04:50 PM PDT 24
Finished Jul 25 06:04:51 PM PDT 24
Peak memory 217168 kb
Host smart-69339bdb-a6f5-4b7e-b5f4-9c9ad67ad69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017168469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3017168469
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3320966795
Short name T912
Test name
Test status
Simulation time 37209611 ps
CPU time 0.87 seconds
Started Jul 25 06:04:48 PM PDT 24
Finished Jul 25 06:04:49 PM PDT 24
Peak memory 215112 kb
Host smart-ed60df91-6d56-4978-844d-d179256b1ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320966795 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3320966795
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1726869080
Short name T324
Test name
Test status
Simulation time 38769292 ps
CPU time 0.86 seconds
Started Jul 25 06:04:46 PM PDT 24
Finished Jul 25 06:04:47 PM PDT 24
Peak memory 214940 kb
Host smart-677ed005-a593-4b25-b814-5afc3439be84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726869080 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1726869080
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1187382538
Short name T690
Test name
Test status
Simulation time 174573148 ps
CPU time 2.36 seconds
Started Jul 25 06:04:46 PM PDT 24
Finished Jul 25 06:04:49 PM PDT 24
Peak memory 215324 kb
Host smart-a9887f64-1605-4789-9b91-09d2cba2e956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187382538 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1187382538
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.106835228
Short name T381
Test name
Test status
Simulation time 54369534195 ps
CPU time 303.33 seconds
Started Jul 25 06:04:46 PM PDT 24
Finished Jul 25 06:09:49 PM PDT 24
Peak memory 218692 kb
Host smart-8aff7f22-0c6c-4d34-8682-6ffe98e15c11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106835228 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.106835228
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1768358492
Short name T3
Test name
Test status
Simulation time 44056468 ps
CPU time 1.17 seconds
Started Jul 25 06:04:52 PM PDT 24
Finished Jul 25 06:04:53 PM PDT 24
Peak memory 220480 kb
Host smart-2189a058-baa2-4943-9c4f-f345269e9a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768358492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1768358492
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1418254169
Short name T517
Test name
Test status
Simulation time 46311440 ps
CPU time 0.87 seconds
Started Jul 25 06:04:53 PM PDT 24
Finished Jul 25 06:04:54 PM PDT 24
Peak memory 206680 kb
Host smart-484f826a-b7c2-45ff-adf4-f36be234916e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418254169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1418254169
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.109647875
Short name T932
Test name
Test status
Simulation time 42432311 ps
CPU time 1.09 seconds
Started Jul 25 06:04:50 PM PDT 24
Finished Jul 25 06:04:52 PM PDT 24
Peak memory 216812 kb
Host smart-d0b92a02-9c98-414b-a8f9-d3ae61a85a06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109647875 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.109647875
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.504147449
Short name T740
Test name
Test status
Simulation time 79886681 ps
CPU time 1.07 seconds
Started Jul 25 06:04:51 PM PDT 24
Finished Jul 25 06:04:53 PM PDT 24
Peak memory 219572 kb
Host smart-a82dad00-95da-498e-8a78-c5bc9d262af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504147449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.504147449
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.539548343
Short name T650
Test name
Test status
Simulation time 22744173 ps
CPU time 1.32 seconds
Started Jul 25 06:04:49 PM PDT 24
Finished Jul 25 06:04:50 PM PDT 24
Peak memory 217616 kb
Host smart-d539accc-f6f7-4435-a74c-0c2dd1c5bfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539548343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.539548343
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1706111228
Short name T15
Test name
Test status
Simulation time 27099963 ps
CPU time 1.05 seconds
Started Jul 25 06:04:51 PM PDT 24
Finished Jul 25 06:04:53 PM PDT 24
Peak memory 223976 kb
Host smart-e33c7ca5-9caa-4e40-964d-58e76d0dd308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706111228 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1706111228
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.851027517
Short name T924
Test name
Test status
Simulation time 18370504 ps
CPU time 1.03 seconds
Started Jul 25 06:04:51 PM PDT 24
Finished Jul 25 06:04:52 PM PDT 24
Peak memory 215108 kb
Host smart-35dd0219-92f6-4d49-a39c-b97ac01cbde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851027517 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.851027517
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.876339009
Short name T229
Test name
Test status
Simulation time 1068337552 ps
CPU time 6.25 seconds
Started Jul 25 06:04:51 PM PDT 24
Finished Jul 25 06:04:58 PM PDT 24
Peak memory 215252 kb
Host smart-e3682822-9e73-40fa-a516-d49229ea15cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876339009 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.876339009
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.534563290
Short name T639
Test name
Test status
Simulation time 463994447066 ps
CPU time 2840.43 seconds
Started Jul 25 06:04:50 PM PDT 24
Finished Jul 25 06:52:11 PM PDT 24
Peak memory 229392 kb
Host smart-9077752d-46f1-4ce2-8588-7af350a05fc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534563290 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.534563290
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3150494229
Short name T205
Test name
Test status
Simulation time 58521757 ps
CPU time 1.3 seconds
Started Jul 25 06:04:51 PM PDT 24
Finished Jul 25 06:04:52 PM PDT 24
Peak memory 219580 kb
Host smart-0b7d31ea-80bd-4a1c-8360-ee06cc4a7583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150494229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3150494229
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.4269746150
Short name T885
Test name
Test status
Simulation time 56132931 ps
CPU time 0.93 seconds
Started Jul 25 06:04:50 PM PDT 24
Finished Jul 25 06:04:51 PM PDT 24
Peak memory 214848 kb
Host smart-3fde450d-1b97-4bcb-9410-631392e9f1b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269746150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.4269746150
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1773681300
Short name T208
Test name
Test status
Simulation time 11452078 ps
CPU time 0.89 seconds
Started Jul 25 06:04:53 PM PDT 24
Finished Jul 25 06:04:54 PM PDT 24
Peak memory 215408 kb
Host smart-67e51e4a-d8e2-4e0c-b27f-a6fe53aa7655
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773681300 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1773681300
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.4277311732
Short name T684
Test name
Test status
Simulation time 101088795 ps
CPU time 1.15 seconds
Started Jul 25 06:04:51 PM PDT 24
Finished Jul 25 06:04:52 PM PDT 24
Peak memory 216692 kb
Host smart-49ec5ef1-e851-4570-b5cc-0fbb158aa388
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277311732 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.4277311732
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.560108575
Short name T474
Test name
Test status
Simulation time 107213888 ps
CPU time 1.1 seconds
Started Jul 25 06:04:52 PM PDT 24
Finished Jul 25 06:04:53 PM PDT 24
Peak memory 219596 kb
Host smart-9e9d7757-896a-45e4-95e8-6d408ca6ac07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560108575 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.560108575
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1025153833
Short name T685
Test name
Test status
Simulation time 82955894 ps
CPU time 1.11 seconds
Started Jul 25 06:04:50 PM PDT 24
Finished Jul 25 06:04:51 PM PDT 24
Peak memory 218760 kb
Host smart-a40a1b13-8787-4221-8a83-f6bb8cc4f1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025153833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1025153833
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.842320100
Short name T557
Test name
Test status
Simulation time 22370223 ps
CPU time 1.14 seconds
Started Jul 25 06:04:51 PM PDT 24
Finished Jul 25 06:04:52 PM PDT 24
Peak memory 215312 kb
Host smart-1205b948-4284-498c-825b-1908b14357af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842320100 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.842320100
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3883842786
Short name T509
Test name
Test status
Simulation time 25995249 ps
CPU time 0.93 seconds
Started Jul 25 06:04:55 PM PDT 24
Finished Jul 25 06:04:56 PM PDT 24
Peak memory 215156 kb
Host smart-b4451905-d053-4b76-bfbe-8e0b7dd4f6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883842786 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3883842786
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.394123348
Short name T630
Test name
Test status
Simulation time 647170141 ps
CPU time 3.77 seconds
Started Jul 25 06:04:53 PM PDT 24
Finished Jul 25 06:04:57 PM PDT 24
Peak memory 219812 kb
Host smart-16d0cc41-bb3b-4895-80fe-a6a4b1bd84d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394123348 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.394123348
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3032875035
Short name T943
Test name
Test status
Simulation time 327938168157 ps
CPU time 885.28 seconds
Started Jul 25 06:04:57 PM PDT 24
Finished Jul 25 06:19:42 PM PDT 24
Peak memory 220848 kb
Host smart-e6eb7425-45f5-4b6a-9367-f95fa4970f74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032875035 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3032875035
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.488142955
Short name T647
Test name
Test status
Simulation time 47508011 ps
CPU time 1.19 seconds
Started Jul 25 06:04:51 PM PDT 24
Finished Jul 25 06:04:52 PM PDT 24
Peak memory 220052 kb
Host smart-02b8a8fe-2ca3-4940-8507-07f8e6d8d3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488142955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.488142955
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2159512450
Short name T726
Test name
Test status
Simulation time 20406315 ps
CPU time 1.03 seconds
Started Jul 25 06:04:54 PM PDT 24
Finished Jul 25 06:04:55 PM PDT 24
Peak memory 215208 kb
Host smart-e91f7671-8caf-4b8e-a70d-8d7ac003738e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159512450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2159512450
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.966351344
Short name T131
Test name
Test status
Simulation time 23649114 ps
CPU time 0.82 seconds
Started Jul 25 06:04:55 PM PDT 24
Finished Jul 25 06:04:56 PM PDT 24
Peak memory 216148 kb
Host smart-f92f489c-a2b4-4431-a6bc-9c788b449575
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966351344 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.966351344
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3340662518
Short name T964
Test name
Test status
Simulation time 49145157 ps
CPU time 1.21 seconds
Started Jul 25 06:04:56 PM PDT 24
Finished Jul 25 06:04:57 PM PDT 24
Peak memory 219536 kb
Host smart-26f14a7d-f741-4304-b156-7ab7bb7aa747
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340662518 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3340662518
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.5332476
Short name T123
Test name
Test status
Simulation time 37414600 ps
CPU time 1.17 seconds
Started Jul 25 06:04:56 PM PDT 24
Finished Jul 25 06:04:57 PM PDT 24
Peak memory 220760 kb
Host smart-50e00179-d5c0-43cc-bb7a-e8d43a96a7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5332476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.5332476
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1833396946
Short name T839
Test name
Test status
Simulation time 108513945 ps
CPU time 1.05 seconds
Started Jul 25 06:04:52 PM PDT 24
Finished Jul 25 06:04:53 PM PDT 24
Peak memory 217344 kb
Host smart-a7a2e799-53aa-412e-8ac6-be4f55808d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833396946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1833396946
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3695412445
Short name T81
Test name
Test status
Simulation time 21022192 ps
CPU time 1.1 seconds
Started Jul 25 06:04:50 PM PDT 24
Finished Jul 25 06:04:51 PM PDT 24
Peak memory 215792 kb
Host smart-33f7f652-5d6b-462d-bd31-7c0a5a0a6fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695412445 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3695412445
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1606802708
Short name T530
Test name
Test status
Simulation time 79890538 ps
CPU time 0.94 seconds
Started Jul 25 06:04:49 PM PDT 24
Finished Jul 25 06:04:50 PM PDT 24
Peak memory 215160 kb
Host smart-6f3deafa-0b41-4a1d-a003-db9b9c65928c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606802708 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1606802708
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1212669462
Short name T935
Test name
Test status
Simulation time 494310012 ps
CPU time 1.47 seconds
Started Jul 25 06:04:51 PM PDT 24
Finished Jul 25 06:04:53 PM PDT 24
Peak memory 217316 kb
Host smart-006b9364-4cd5-4b73-a51a-daffc7391b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212669462 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1212669462
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.411105643
Short name T723
Test name
Test status
Simulation time 176881841850 ps
CPU time 722.56 seconds
Started Jul 25 06:04:54 PM PDT 24
Finished Jul 25 06:16:56 PM PDT 24
Peak memory 223596 kb
Host smart-f160707f-9bc4-469f-8962-283490e5c6bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411105643 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.411105643
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.192092138
Short name T239
Test name
Test status
Simulation time 49171715 ps
CPU time 1.3 seconds
Started Jul 25 06:04:54 PM PDT 24
Finished Jul 25 06:04:55 PM PDT 24
Peak memory 219336 kb
Host smart-97906198-ae08-4ff4-9ae3-cd48cce5d2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192092138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.192092138
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2713923871
Short name T391
Test name
Test status
Simulation time 23956504 ps
CPU time 0.92 seconds
Started Jul 25 06:04:50 PM PDT 24
Finished Jul 25 06:04:51 PM PDT 24
Peak memory 206580 kb
Host smart-0647d5df-3f6c-40c6-8c83-873b7b73fe25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713923871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2713923871
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3720801376
Short name T976
Test name
Test status
Simulation time 114119414 ps
CPU time 0.89 seconds
Started Jul 25 06:04:50 PM PDT 24
Finished Jul 25 06:04:51 PM PDT 24
Peak memory 216044 kb
Host smart-07344936-36eb-484c-9962-dcfc852c4753
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720801376 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3720801376
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3892419198
Short name T602
Test name
Test status
Simulation time 160596256 ps
CPU time 1.09 seconds
Started Jul 25 06:04:55 PM PDT 24
Finished Jul 25 06:04:56 PM PDT 24
Peak memory 216708 kb
Host smart-e844d78a-dd58-4f30-b321-04148f55a538
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892419198 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3892419198
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2089960598
Short name T974
Test name
Test status
Simulation time 49560815 ps
CPU time 0.99 seconds
Started Jul 25 06:04:50 PM PDT 24
Finished Jul 25 06:04:51 PM PDT 24
Peak memory 223720 kb
Host smart-fba8d686-e7a0-46f6-b874-9c0c192f4e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089960598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2089960598
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.344806585
Short name T940
Test name
Test status
Simulation time 62784707 ps
CPU time 1.29 seconds
Started Jul 25 06:04:51 PM PDT 24
Finished Jul 25 06:04:52 PM PDT 24
Peak memory 218308 kb
Host smart-fe22ad05-880b-4e06-aafb-9a91896ef3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344806585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.344806585
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1532761514
Short name T55
Test name
Test status
Simulation time 43482372 ps
CPU time 0.87 seconds
Started Jul 25 06:04:52 PM PDT 24
Finished Jul 25 06:04:53 PM PDT 24
Peak memory 215248 kb
Host smart-0b72720d-2699-44aa-a8b2-5938156c7ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532761514 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1532761514
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.967169328
Short name T971
Test name
Test status
Simulation time 40014700 ps
CPU time 0.88 seconds
Started Jul 25 06:04:50 PM PDT 24
Finished Jul 25 06:04:51 PM PDT 24
Peak memory 215164 kb
Host smart-48ac7049-7eb7-4d85-9749-13c280073d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967169328 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.967169328
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.306140958
Short name T431
Test name
Test status
Simulation time 284395821 ps
CPU time 5.98 seconds
Started Jul 25 06:04:57 PM PDT 24
Finished Jul 25 06:05:03 PM PDT 24
Peak memory 218500 kb
Host smart-13f39d7d-15f1-4b48-9f62-23f0dc3d5572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306140958 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.306140958
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.4190453330
Short name T556
Test name
Test status
Simulation time 194731232238 ps
CPU time 1224.86 seconds
Started Jul 25 06:04:50 PM PDT 24
Finished Jul 25 06:25:15 PM PDT 24
Peak memory 222580 kb
Host smart-e2109e8a-87d1-468f-8219-66a2f6cb5350
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190453330 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.4190453330
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1379754322
Short name T826
Test name
Test status
Simulation time 25046022 ps
CPU time 1.28 seconds
Started Jul 25 06:04:55 PM PDT 24
Finished Jul 25 06:04:57 PM PDT 24
Peak memory 219764 kb
Host smart-5a711b6f-d791-4098-bb0c-74641796cc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379754322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1379754322
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.674472786
Short name T830
Test name
Test status
Simulation time 22430667 ps
CPU time 0.88 seconds
Started Jul 25 06:04:56 PM PDT 24
Finished Jul 25 06:04:57 PM PDT 24
Peak memory 206468 kb
Host smart-ffa46c20-4c23-4abc-9d13-fa2f59aa31d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674472786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.674472786
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2790520133
Short name T481
Test name
Test status
Simulation time 36179653 ps
CPU time 0.82 seconds
Started Jul 25 06:04:55 PM PDT 24
Finished Jul 25 06:04:56 PM PDT 24
Peak memory 215804 kb
Host smart-d87f280b-19db-4d94-9b9d-8f966700e527
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790520133 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2790520133
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2904037779
Short name T31
Test name
Test status
Simulation time 38325819 ps
CPU time 1.16 seconds
Started Jul 25 06:04:56 PM PDT 24
Finished Jul 25 06:04:57 PM PDT 24
Peak memory 216784 kb
Host smart-3e95deb5-790e-442b-8a25-932c18f987d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904037779 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2904037779
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_genbits.451073106
Short name T959
Test name
Test status
Simulation time 34474381 ps
CPU time 1.33 seconds
Started Jul 25 06:04:54 PM PDT 24
Finished Jul 25 06:04:55 PM PDT 24
Peak memory 217212 kb
Host smart-6936cc83-9f9d-42df-8152-cafc2e8d6cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451073106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.451073106
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2262808487
Short name T508
Test name
Test status
Simulation time 23285591 ps
CPU time 1.21 seconds
Started Jul 25 06:05:10 PM PDT 24
Finished Jul 25 06:05:11 PM PDT 24
Peak memory 223872 kb
Host smart-3ad0fe25-dbf4-42b7-be47-0f0570ee8cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262808487 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2262808487
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.4074198333
Short name T486
Test name
Test status
Simulation time 28125650 ps
CPU time 0.95 seconds
Started Jul 25 06:04:49 PM PDT 24
Finished Jul 25 06:04:50 PM PDT 24
Peak memory 215184 kb
Host smart-6fa13cc2-4bf3-4fdf-a9b9-1d449be16932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074198333 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.4074198333
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2446029745
Short name T370
Test name
Test status
Simulation time 344650228 ps
CPU time 2.52 seconds
Started Jul 25 06:04:57 PM PDT 24
Finished Jul 25 06:05:00 PM PDT 24
Peak memory 215172 kb
Host smart-36ca09e4-a6cf-4a8e-bd08-520b7e5daa5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446029745 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2446029745
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1204941845
Short name T881
Test name
Test status
Simulation time 91820137310 ps
CPU time 2364.89 seconds
Started Jul 25 06:04:53 PM PDT 24
Finished Jul 25 06:44:19 PM PDT 24
Peak memory 231492 kb
Host smart-f1cea960-d248-49e5-92b4-976b218ae6fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204941845 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1204941845
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert_test.3271651904
Short name T922
Test name
Test status
Simulation time 15550866 ps
CPU time 0.96 seconds
Started Jul 25 06:04:57 PM PDT 24
Finished Jul 25 06:04:58 PM PDT 24
Peak memory 214864 kb
Host smart-65812671-1ea5-417c-8f5d-f1918cb4b526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271651904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3271651904
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2406854058
Short name T72
Test name
Test status
Simulation time 10863542 ps
CPU time 0.88 seconds
Started Jul 25 06:04:55 PM PDT 24
Finished Jul 25 06:04:56 PM PDT 24
Peak memory 215896 kb
Host smart-9ba4bb08-ec2b-4a81-aab7-056ed730c9bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406854058 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2406854058
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3471488832
Short name T124
Test name
Test status
Simulation time 136280703 ps
CPU time 1.24 seconds
Started Jul 25 06:04:54 PM PDT 24
Finished Jul 25 06:04:56 PM PDT 24
Peak memory 216732 kb
Host smart-239b70f3-7d85-4f0b-82b8-0c8cf80a8c39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471488832 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3471488832
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3245969068
Short name T181
Test name
Test status
Simulation time 18138897 ps
CPU time 1.09 seconds
Started Jul 25 06:04:52 PM PDT 24
Finished Jul 25 06:04:54 PM PDT 24
Peak memory 218268 kb
Host smart-9e3bf2c9-7767-409e-81f8-8255881a3f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245969068 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3245969068
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.449905985
Short name T915
Test name
Test status
Simulation time 37992103 ps
CPU time 1.17 seconds
Started Jul 25 06:04:56 PM PDT 24
Finished Jul 25 06:04:57 PM PDT 24
Peak memory 217260 kb
Host smart-b6b65873-c69c-4cce-bc96-586f9db9e6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449905985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.449905985
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_smoke.789809274
Short name T869
Test name
Test status
Simulation time 20489910 ps
CPU time 1.06 seconds
Started Jul 25 06:04:53 PM PDT 24
Finished Jul 25 06:04:55 PM PDT 24
Peak memory 215160 kb
Host smart-349d0a6d-ce40-41bb-8aa4-29602cc7d009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789809274 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.789809274
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3234760981
Short name T911
Test name
Test status
Simulation time 158374851 ps
CPU time 2.14 seconds
Started Jul 25 06:04:54 PM PDT 24
Finished Jul 25 06:04:56 PM PDT 24
Peak memory 219620 kb
Host smart-81df9cea-e34e-4f35-a875-f74b4ea1f7e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234760981 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3234760981
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3509432607
Short name T222
Test name
Test status
Simulation time 430056973403 ps
CPU time 1522.49 seconds
Started Jul 25 06:04:52 PM PDT 24
Finished Jul 25 06:30:15 PM PDT 24
Peak memory 223116 kb
Host smart-3eeffb01-2e3e-4acc-9725-35683a88497b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509432607 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3509432607
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1575016525
Short name T828
Test name
Test status
Simulation time 37724416 ps
CPU time 1.14 seconds
Started Jul 25 06:05:05 PM PDT 24
Finished Jul 25 06:05:06 PM PDT 24
Peak memory 220132 kb
Host smart-ada004f0-94d8-4595-a73e-b9b0c057cdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575016525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1575016525
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3202936502
Short name T592
Test name
Test status
Simulation time 22166137 ps
CPU time 0.85 seconds
Started Jul 25 06:05:05 PM PDT 24
Finished Jul 25 06:05:06 PM PDT 24
Peak memory 206712 kb
Host smart-aa82f080-749f-4318-ad7c-e350d9c58382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202936502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3202936502
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.881979225
Short name T30
Test name
Test status
Simulation time 11325781 ps
CPU time 0.89 seconds
Started Jul 25 06:05:03 PM PDT 24
Finished Jul 25 06:05:04 PM PDT 24
Peak memory 215800 kb
Host smart-a9ad8092-50d4-4899-a00e-927f02077e9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881979225 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.881979225
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1001342429
Short name T857
Test name
Test status
Simulation time 44043016 ps
CPU time 1.1 seconds
Started Jul 25 06:05:03 PM PDT 24
Finished Jul 25 06:05:04 PM PDT 24
Peak memory 218240 kb
Host smart-fe58f80b-d07a-42fd-a82d-937b816cf3f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001342429 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1001342429
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3118023526
Short name T633
Test name
Test status
Simulation time 18919111 ps
CPU time 1.18 seconds
Started Jul 25 06:05:03 PM PDT 24
Finished Jul 25 06:05:04 PM PDT 24
Peak memory 223864 kb
Host smart-6a31170c-d596-46a3-9527-433cb146edf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118023526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3118023526
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3844628949
Short name T519
Test name
Test status
Simulation time 32851548 ps
CPU time 1.34 seconds
Started Jul 25 06:04:52 PM PDT 24
Finished Jul 25 06:04:54 PM PDT 24
Peak memory 219936 kb
Host smart-4ddd7290-cf22-4257-a512-83a6a5c2760e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844628949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3844628949
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_smoke.3839806921
Short name T704
Test name
Test status
Simulation time 31497814 ps
CPU time 0.97 seconds
Started Jul 25 06:04:52 PM PDT 24
Finished Jul 25 06:04:53 PM PDT 24
Peak memory 215156 kb
Host smart-8901a257-bd47-442e-b497-30888d9d54eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839806921 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3839806921
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3857930128
Short name T646
Test name
Test status
Simulation time 104261303 ps
CPU time 1.62 seconds
Started Jul 25 06:05:06 PM PDT 24
Finished Jul 25 06:05:08 PM PDT 24
Peak memory 217156 kb
Host smart-70e606c0-d851-42eb-b418-4b1a40a4a6b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857930128 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3857930128
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3855146122
Short name T496
Test name
Test status
Simulation time 24238808254 ps
CPU time 557.46 seconds
Started Jul 25 06:05:06 PM PDT 24
Finished Jul 25 06:14:24 PM PDT 24
Peak memory 223556 kb
Host smart-341ab545-2b6e-4172-90f9-3b90c218c3b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855146122 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3855146122
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2171399029
Short name T98
Test name
Test status
Simulation time 64168402 ps
CPU time 1.07 seconds
Started Jul 25 06:03:54 PM PDT 24
Finished Jul 25 06:03:55 PM PDT 24
Peak memory 215524 kb
Host smart-6d7d066f-fce4-4c38-95ee-63fc0c423824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171399029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2171399029
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1981416396
Short name T874
Test name
Test status
Simulation time 17609226 ps
CPU time 0.89 seconds
Started Jul 25 06:03:56 PM PDT 24
Finished Jul 25 06:03:57 PM PDT 24
Peak memory 206628 kb
Host smart-3657b748-f118-4518-a9d8-67fe9f91ab4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981416396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1981416396
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2925462998
Short name T358
Test name
Test status
Simulation time 13930509 ps
CPU time 0.89 seconds
Started Jul 25 06:03:55 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 216004 kb
Host smart-488d4683-2ce9-4dc1-9dc5-24efdddbdc9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925462998 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2925462998
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.1127018515
Short name T112
Test name
Test status
Simulation time 31978837 ps
CPU time 0.82 seconds
Started Jul 25 06:03:54 PM PDT 24
Finished Jul 25 06:03:55 PM PDT 24
Peak memory 217848 kb
Host smart-46f34aed-e9c1-4a82-882a-370513cbaadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127018515 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1127018515
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1977697264
Short name T349
Test name
Test status
Simulation time 86484838 ps
CPU time 1.14 seconds
Started Jul 25 06:03:54 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 219820 kb
Host smart-af6f07dc-4305-41f2-9948-a4acd2258c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977697264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1977697264
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2199447535
Short name T611
Test name
Test status
Simulation time 27902389 ps
CPU time 0.87 seconds
Started Jul 25 06:03:51 PM PDT 24
Finished Jul 25 06:03:52 PM PDT 24
Peak memory 215620 kb
Host smart-cdbf3398-abb2-4aef-a309-7ce7fe4e9a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199447535 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2199447535
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2275555828
Short name T274
Test name
Test status
Simulation time 15894106 ps
CPU time 0.99 seconds
Started Jul 25 06:03:56 PM PDT 24
Finished Jul 25 06:03:57 PM PDT 24
Peak memory 206948 kb
Host smart-314ff85a-21f4-4237-be5b-f00ee62d4b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275555828 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2275555828
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.2173058259
Short name T343
Test name
Test status
Simulation time 16268151 ps
CPU time 0.99 seconds
Started Jul 25 06:03:55 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 215208 kb
Host smart-5c080735-d7cd-428a-af17-9b911425a8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173058259 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2173058259
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.4161531629
Short name T637
Test name
Test status
Simulation time 369307838 ps
CPU time 6.97 seconds
Started Jul 25 06:03:52 PM PDT 24
Finished Jul 25 06:03:59 PM PDT 24
Peak memory 215284 kb
Host smart-6ce92764-a023-423c-bdf6-d5f4a7343204
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161531629 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.4161531629
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.4008085462
Short name T884
Test name
Test status
Simulation time 55488740733 ps
CPU time 1370.45 seconds
Started Jul 25 06:03:54 PM PDT 24
Finished Jul 25 06:26:45 PM PDT 24
Peak memory 224248 kb
Host smart-473d2347-d424-4a02-89cc-9412a758e6d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008085462 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.4008085462
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.642071698
Short name T779
Test name
Test status
Simulation time 67271021 ps
CPU time 1.08 seconds
Started Jul 25 06:05:11 PM PDT 24
Finished Jul 25 06:05:13 PM PDT 24
Peak memory 218552 kb
Host smart-f473c91d-aac6-47af-b08b-1bbc3ad44c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642071698 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.642071698
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1963297198
Short name T910
Test name
Test status
Simulation time 57202534 ps
CPU time 0.96 seconds
Started Jul 25 06:05:04 PM PDT 24
Finished Jul 25 06:05:05 PM PDT 24
Peak memory 214872 kb
Host smart-0142ecad-072a-4747-bf72-bed98fbe4669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963297198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1963297198
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.520164208
Short name T113
Test name
Test status
Simulation time 19512503 ps
CPU time 0.92 seconds
Started Jul 25 06:05:03 PM PDT 24
Finished Jul 25 06:05:04 PM PDT 24
Peak memory 216192 kb
Host smart-432fad96-da60-485a-a049-10b4cda13a98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520164208 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.520164208
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3289210226
Short name T148
Test name
Test status
Simulation time 165464758 ps
CPU time 1.01 seconds
Started Jul 25 06:05:03 PM PDT 24
Finished Jul 25 06:05:04 PM PDT 24
Peak memory 216728 kb
Host smart-27d8f50b-1dd5-40d7-b997-cc5e9cb92876
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289210226 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3289210226
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.4106781625
Short name T864
Test name
Test status
Simulation time 19935144 ps
CPU time 1.14 seconds
Started Jul 25 06:05:06 PM PDT 24
Finished Jul 25 06:05:07 PM PDT 24
Peak memory 219524 kb
Host smart-0a532009-8bb9-450a-a939-41c890342cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106781625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.4106781625
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2106407987
Short name T344
Test name
Test status
Simulation time 42603475 ps
CPU time 1.21 seconds
Started Jul 25 06:05:03 PM PDT 24
Finished Jul 25 06:05:05 PM PDT 24
Peak memory 217036 kb
Host smart-62646f9e-9fa9-4ecd-ac17-ab0069acebd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106407987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2106407987
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1878457934
Short name T43
Test name
Test status
Simulation time 61892477 ps
CPU time 0.98 seconds
Started Jul 25 06:05:02 PM PDT 24
Finished Jul 25 06:05:03 PM PDT 24
Peak memory 223736 kb
Host smart-c256428a-bec2-43eb-9b7f-8ae9a03a24fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878457934 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1878457934
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.838522628
Short name T679
Test name
Test status
Simulation time 24064086 ps
CPU time 0.94 seconds
Started Jul 25 06:05:04 PM PDT 24
Finished Jul 25 06:05:05 PM PDT 24
Peak memory 215184 kb
Host smart-23ba6414-ba33-4bcd-a3bf-38dfaf702434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838522628 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.838522628
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3201203063
Short name T457
Test name
Test status
Simulation time 667757451 ps
CPU time 4.32 seconds
Started Jul 25 06:05:07 PM PDT 24
Finished Jul 25 06:05:12 PM PDT 24
Peak memory 217248 kb
Host smart-c6f2c7b5-3cc5-46c2-a7ca-c5422e08af91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201203063 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3201203063
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3034098058
Short name T91
Test name
Test status
Simulation time 326482463755 ps
CPU time 957.57 seconds
Started Jul 25 06:05:05 PM PDT 24
Finished Jul 25 06:21:02 PM PDT 24
Peak memory 222320 kb
Host smart-2fbdd32e-97b9-4ed5-9f1f-73da3b1fec16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034098058 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3034098058
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3134849704
Short name T725
Test name
Test status
Simulation time 32553660 ps
CPU time 1.37 seconds
Started Jul 25 06:05:03 PM PDT 24
Finished Jul 25 06:05:04 PM PDT 24
Peak memory 219892 kb
Host smart-0a8a16c6-15da-4f24-ba26-851f2e0aea37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134849704 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3134849704
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1863648162
Short name T54
Test name
Test status
Simulation time 33516621 ps
CPU time 0.98 seconds
Started Jul 25 06:05:03 PM PDT 24
Finished Jul 25 06:05:04 PM PDT 24
Peak memory 214868 kb
Host smart-2651f533-7257-4751-b3bc-f494f1623222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863648162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1863648162
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2245978363
Short name T625
Test name
Test status
Simulation time 33251925 ps
CPU time 0.82 seconds
Started Jul 25 06:05:03 PM PDT 24
Finished Jul 25 06:05:04 PM PDT 24
Peak memory 216164 kb
Host smart-7edf95d0-a798-4d77-ae99-d7ac2f60757e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245978363 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2245978363
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2601223691
Short name T130
Test name
Test status
Simulation time 36352602 ps
CPU time 1.29 seconds
Started Jul 25 06:05:08 PM PDT 24
Finished Jul 25 06:05:09 PM PDT 24
Peak memory 219276 kb
Host smart-d41597f6-03b2-4e43-a2f5-79ef45f0d97a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601223691 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2601223691
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2237456897
Short name T44
Test name
Test status
Simulation time 18097167 ps
CPU time 1.16 seconds
Started Jul 25 06:05:07 PM PDT 24
Finished Jul 25 06:05:08 PM PDT 24
Peak memory 232832 kb
Host smart-00559be7-a91a-4dd5-9966-2457e01cb92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237456897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2237456897
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.878076060
Short name T404
Test name
Test status
Simulation time 53747577 ps
CPU time 1.85 seconds
Started Jul 25 06:05:06 PM PDT 24
Finished Jul 25 06:05:08 PM PDT 24
Peak memory 219620 kb
Host smart-f3c9ed6a-a152-4165-b55a-68ba9ff024f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878076060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.878076060
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.66430677
Short name T836
Test name
Test status
Simulation time 22649629 ps
CPU time 1.11 seconds
Started Jul 25 06:05:02 PM PDT 24
Finished Jul 25 06:05:04 PM PDT 24
Peak memory 215304 kb
Host smart-1ae701c4-6c60-48e9-8903-2bf9bac3eab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66430677 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.66430677
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2658217844
Short name T840
Test name
Test status
Simulation time 29359093 ps
CPU time 0.96 seconds
Started Jul 25 06:05:03 PM PDT 24
Finished Jul 25 06:05:04 PM PDT 24
Peak memory 215208 kb
Host smart-dc512984-ffe8-4034-bcc2-bb270647096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658217844 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2658217844
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3729752684
Short name T848
Test name
Test status
Simulation time 231448305 ps
CPU time 2.37 seconds
Started Jul 25 06:05:07 PM PDT 24
Finished Jul 25 06:05:10 PM PDT 24
Peak memory 219408 kb
Host smart-b2b8f581-9ca5-405c-ae80-d887db56e18d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729752684 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3729752684
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2979003560
Short name T412
Test name
Test status
Simulation time 32636734561 ps
CPU time 378.04 seconds
Started Jul 25 06:05:08 PM PDT 24
Finished Jul 25 06:11:26 PM PDT 24
Peak memory 223612 kb
Host smart-f05e945a-568b-4455-a180-43bd38869992
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979003560 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2979003560
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2962441463
Short name T886
Test name
Test status
Simulation time 393827593 ps
CPU time 1.37 seconds
Started Jul 25 06:05:00 PM PDT 24
Finished Jul 25 06:05:01 PM PDT 24
Peak memory 218356 kb
Host smart-0682b9f7-02ac-4bbd-bdf4-96b5da513d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962441463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2962441463
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1444881252
Short name T787
Test name
Test status
Simulation time 42922062 ps
CPU time 0.88 seconds
Started Jul 25 06:05:11 PM PDT 24
Finished Jul 25 06:05:12 PM PDT 24
Peak memory 215024 kb
Host smart-ccb4fee8-2b47-41c5-b0d6-b8d6f2b57bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444881252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1444881252
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.196531832
Short name T460
Test name
Test status
Simulation time 16666909 ps
CPU time 0.88 seconds
Started Jul 25 06:05:01 PM PDT 24
Finished Jul 25 06:05:02 PM PDT 24
Peak memory 216040 kb
Host smart-bacc5bc3-8f36-45d6-beba-17ec5d795924
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196531832 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.196531832
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2640854555
Short name T420
Test name
Test status
Simulation time 39167963 ps
CPU time 1.35 seconds
Started Jul 25 06:05:04 PM PDT 24
Finished Jul 25 06:05:05 PM PDT 24
Peak memory 216692 kb
Host smart-bf60a5f1-0cc9-482e-9cc5-380ad78336cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640854555 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2640854555
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1912894714
Short name T140
Test name
Test status
Simulation time 26759161 ps
CPU time 1.04 seconds
Started Jul 25 06:05:03 PM PDT 24
Finished Jul 25 06:05:04 PM PDT 24
Peak memory 219696 kb
Host smart-6afa69b5-23e1-4a7e-aa68-fc0b86a6ee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912894714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1912894714
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.555460773
Short name T396
Test name
Test status
Simulation time 84340739 ps
CPU time 1.25 seconds
Started Jul 25 06:05:03 PM PDT 24
Finished Jul 25 06:05:05 PM PDT 24
Peak memory 218496 kb
Host smart-41911f33-65cc-4510-b0ec-cdff6a82aa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555460773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.555460773
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1587482729
Short name T83
Test name
Test status
Simulation time 20849950 ps
CPU time 1.11 seconds
Started Jul 25 06:05:05 PM PDT 24
Finished Jul 25 06:05:06 PM PDT 24
Peak memory 215772 kb
Host smart-a5c92f0f-5069-4ad4-ae50-7fccf1f35fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587482729 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1587482729
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2625565580
Short name T375
Test name
Test status
Simulation time 95508959 ps
CPU time 0.91 seconds
Started Jul 25 06:05:01 PM PDT 24
Finished Jul 25 06:05:02 PM PDT 24
Peak memory 215176 kb
Host smart-c4e9627d-2387-483d-a7c9-96f8df515242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625565580 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2625565580
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1685333283
Short name T765
Test name
Test status
Simulation time 143079877 ps
CPU time 3.31 seconds
Started Jul 25 06:05:11 PM PDT 24
Finished Jul 25 06:05:15 PM PDT 24
Peak memory 215136 kb
Host smart-c328db89-f93c-4e68-bf4b-1296325c9ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685333283 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1685333283
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2800868668
Short name T498
Test name
Test status
Simulation time 201369912039 ps
CPU time 468.87 seconds
Started Jul 25 06:05:07 PM PDT 24
Finished Jul 25 06:12:56 PM PDT 24
Peak memory 232228 kb
Host smart-c96e9104-7b28-476e-bd73-b15db9d803d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800868668 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2800868668
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2299835792
Short name T805
Test name
Test status
Simulation time 41492797 ps
CPU time 1.2 seconds
Started Jul 25 06:05:03 PM PDT 24
Finished Jul 25 06:05:04 PM PDT 24
Peak memory 220412 kb
Host smart-ab708850-da6b-4cf4-90f4-34b5883e7dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299835792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2299835792
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2616128828
Short name T950
Test name
Test status
Simulation time 16440624 ps
CPU time 1 seconds
Started Jul 25 06:05:10 PM PDT 24
Finished Jul 25 06:05:11 PM PDT 24
Peak memory 206640 kb
Host smart-4bf10f76-9ba7-4f68-a696-7ed7ea46bd12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616128828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2616128828
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3200387377
Short name T188
Test name
Test status
Simulation time 12663374 ps
CPU time 0.93 seconds
Started Jul 25 06:05:09 PM PDT 24
Finished Jul 25 06:05:10 PM PDT 24
Peak memory 216288 kb
Host smart-53ed67d9-31a9-4e28-a404-8ad058ceded6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200387377 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3200387377
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.628479412
Short name T169
Test name
Test status
Simulation time 88994870 ps
CPU time 1.05 seconds
Started Jul 25 06:05:04 PM PDT 24
Finished Jul 25 06:05:05 PM PDT 24
Peak memory 216920 kb
Host smart-2be9faa2-5b7e-4181-b68b-40210f29b7fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628479412 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.628479412
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3708956325
Short name T586
Test name
Test status
Simulation time 40596961 ps
CPU time 0.9 seconds
Started Jul 25 06:05:05 PM PDT 24
Finished Jul 25 06:05:06 PM PDT 24
Peak memory 219576 kb
Host smart-8458d798-708f-4dd9-81db-95e120ba6da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708956325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3708956325
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2002430041
Short name T904
Test name
Test status
Simulation time 60081494 ps
CPU time 1.05 seconds
Started Jul 25 06:05:04 PM PDT 24
Finished Jul 25 06:05:05 PM PDT 24
Peak memory 217108 kb
Host smart-ecdc21d1-082a-4a0e-b90b-8152f9907c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002430041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2002430041
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1263258577
Short name T978
Test name
Test status
Simulation time 23195484 ps
CPU time 0.94 seconds
Started Jul 25 06:05:06 PM PDT 24
Finished Jul 25 06:05:07 PM PDT 24
Peak memory 215828 kb
Host smart-5fc551d5-f3dd-440d-a200-0ed7ef402dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263258577 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1263258577
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2008140838
Short name T789
Test name
Test status
Simulation time 18011443 ps
CPU time 1.03 seconds
Started Jul 25 06:05:03 PM PDT 24
Finished Jul 25 06:05:04 PM PDT 24
Peak memory 215152 kb
Host smart-4de00080-91d5-4c8c-b3bc-8ee26875e356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008140838 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2008140838
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.955418027
Short name T638
Test name
Test status
Simulation time 734253487 ps
CPU time 2.58 seconds
Started Jul 25 06:05:04 PM PDT 24
Finished Jul 25 06:05:06 PM PDT 24
Peak memory 217048 kb
Host smart-8b12358c-de11-4ff4-a2ec-5eb492e9a2a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955418027 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.955418027
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2351433353
Short name T92
Test name
Test status
Simulation time 134266682961 ps
CPU time 886.05 seconds
Started Jul 25 06:05:06 PM PDT 24
Finished Jul 25 06:19:52 PM PDT 24
Peak memory 223648 kb
Host smart-6dcd2508-97ee-4e9f-9681-ed1b450bcd76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351433353 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2351433353
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2200171914
Short name T453
Test name
Test status
Simulation time 148636293 ps
CPU time 1.35 seconds
Started Jul 25 06:05:13 PM PDT 24
Finished Jul 25 06:05:15 PM PDT 24
Peak memory 220496 kb
Host smart-adc2dae7-9ac6-4a32-8df4-e53896715a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200171914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2200171914
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3741902235
Short name T847
Test name
Test status
Simulation time 55450253 ps
CPU time 0.91 seconds
Started Jul 25 06:05:14 PM PDT 24
Finished Jul 25 06:05:15 PM PDT 24
Peak memory 214760 kb
Host smart-90ff12ec-5a0b-43f4-8e91-4e5922762071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741902235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3741902235
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1154331880
Short name T827
Test name
Test status
Simulation time 19299349 ps
CPU time 0.86 seconds
Started Jul 25 06:05:16 PM PDT 24
Finished Jul 25 06:05:17 PM PDT 24
Peak memory 216128 kb
Host smart-34b00142-ccb0-4026-a046-8cc78b542e73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154331880 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1154331880
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2998629396
Short name T390
Test name
Test status
Simulation time 20675238 ps
CPU time 1.06 seconds
Started Jul 25 06:05:13 PM PDT 24
Finished Jul 25 06:05:14 PM PDT 24
Peak memory 217996 kb
Host smart-1400f5ed-11a5-4058-b9de-2cd05ce450d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998629396 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2998629396
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.694450677
Short name T961
Test name
Test status
Simulation time 18748914 ps
CPU time 1.06 seconds
Started Jul 25 06:05:24 PM PDT 24
Finished Jul 25 06:05:25 PM PDT 24
Peak memory 218584 kb
Host smart-c711b3ca-80d9-4b4f-b2b9-c3d526f0df51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694450677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.694450677
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.4063157811
Short name T590
Test name
Test status
Simulation time 35403733 ps
CPU time 1.29 seconds
Started Jul 25 06:05:08 PM PDT 24
Finished Jul 25 06:05:10 PM PDT 24
Peak memory 217124 kb
Host smart-b5c89c92-9bf0-4d4c-86b1-5dc2594c9d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063157811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.4063157811
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3055265962
Short name T555
Test name
Test status
Simulation time 39186727 ps
CPU time 0.9 seconds
Started Jul 25 06:05:17 PM PDT 24
Finished Jul 25 06:05:18 PM PDT 24
Peak memory 215432 kb
Host smart-14eb740a-3a68-4c3a-95d1-006733e936d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055265962 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3055265962
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3708416020
Short name T325
Test name
Test status
Simulation time 21555782 ps
CPU time 0.92 seconds
Started Jul 25 06:05:09 PM PDT 24
Finished Jul 25 06:05:10 PM PDT 24
Peak memory 207004 kb
Host smart-15c88537-a61b-41a8-b9ae-a8d7d0169a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708416020 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3708416020
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1434023282
Short name T615
Test name
Test status
Simulation time 323055925 ps
CPU time 3.8 seconds
Started Jul 25 06:05:09 PM PDT 24
Finished Jul 25 06:05:12 PM PDT 24
Peak memory 215204 kb
Host smart-4570efc7-51c4-40e5-8326-5ad8ac351e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434023282 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1434023282
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1708892831
Short name T901
Test name
Test status
Simulation time 74210339722 ps
CPU time 1072.26 seconds
Started Jul 25 06:05:14 PM PDT 24
Finished Jul 25 06:23:06 PM PDT 24
Peak memory 221704 kb
Host smart-e85681f0-292c-4bbe-8238-48733253b7cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708892831 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1708892831
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1328447469
Short name T636
Test name
Test status
Simulation time 45337433 ps
CPU time 1.21 seconds
Started Jul 25 06:05:15 PM PDT 24
Finished Jul 25 06:05:16 PM PDT 24
Peak memory 220952 kb
Host smart-bcc6d571-9d0d-4b81-9adf-571d54a12508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328447469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1328447469
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3224886617
Short name T913
Test name
Test status
Simulation time 21134076 ps
CPU time 1.03 seconds
Started Jul 25 06:05:18 PM PDT 24
Finished Jul 25 06:05:19 PM PDT 24
Peak memory 206616 kb
Host smart-1c6dbda8-46c7-45a8-ac64-6db820ad4387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224886617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3224886617
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2036054440
Short name T116
Test name
Test status
Simulation time 20594938 ps
CPU time 0.87 seconds
Started Jul 25 06:05:14 PM PDT 24
Finished Jul 25 06:05:15 PM PDT 24
Peak memory 216104 kb
Host smart-3588ead4-5dfe-4224-9bb8-865b2bae610b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036054440 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2036054440
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.4008516031
Short name T228
Test name
Test status
Simulation time 42600995 ps
CPU time 0.98 seconds
Started Jul 25 06:05:29 PM PDT 24
Finished Jul 25 06:05:30 PM PDT 24
Peak memory 218248 kb
Host smart-3f946d20-cd66-44b7-940b-6a1961756683
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008516031 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.4008516031
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2980381191
Short name T132
Test name
Test status
Simulation time 47316442 ps
CPU time 1.18 seconds
Started Jul 25 06:05:14 PM PDT 24
Finished Jul 25 06:05:16 PM PDT 24
Peak memory 219568 kb
Host smart-60ba2fb3-daf1-4bd1-9738-1520b02440ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980381191 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2980381191
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.935426825
Short name T302
Test name
Test status
Simulation time 76216961 ps
CPU time 2.81 seconds
Started Jul 25 06:05:20 PM PDT 24
Finished Jul 25 06:05:23 PM PDT 24
Peak memory 220000 kb
Host smart-9756aa77-8ceb-4944-8fac-c6d9a4f461a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935426825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.935426825
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.996761794
Short name T813
Test name
Test status
Simulation time 21546095 ps
CPU time 1.05 seconds
Started Jul 25 06:05:14 PM PDT 24
Finished Jul 25 06:05:15 PM PDT 24
Peak memory 215340 kb
Host smart-6f9d2174-6928-4218-a397-3453cba82d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996761794 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.996761794
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2415833186
Short name T783
Test name
Test status
Simulation time 16040204 ps
CPU time 0.96 seconds
Started Jul 25 06:05:15 PM PDT 24
Finished Jul 25 06:05:16 PM PDT 24
Peak memory 215160 kb
Host smart-9456c9f8-16e2-4d46-bc80-b5cd28e32f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415833186 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2415833186
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1722344687
Short name T436
Test name
Test status
Simulation time 151695149 ps
CPU time 3.23 seconds
Started Jul 25 06:05:29 PM PDT 24
Finished Jul 25 06:05:32 PM PDT 24
Peak memory 217080 kb
Host smart-1d078c42-16e5-4585-ae55-033d8b0d26f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722344687 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1722344687
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.793044601
Short name T320
Test name
Test status
Simulation time 132419916252 ps
CPU time 1737.29 seconds
Started Jul 25 06:05:14 PM PDT 24
Finished Jul 25 06:34:12 PM PDT 24
Peak memory 227760 kb
Host smart-6dfa51aa-14fc-4d41-b6b3-ea633efd05a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793044601 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.793044601
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3275111008
Short name T883
Test name
Test status
Simulation time 25940402 ps
CPU time 1.29 seconds
Started Jul 25 06:05:16 PM PDT 24
Finished Jul 25 06:05:17 PM PDT 24
Peak memory 218812 kb
Host smart-c793da8a-f69a-44a3-8e0a-566cbee3aefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275111008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3275111008
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3057685516
Short name T572
Test name
Test status
Simulation time 19925365 ps
CPU time 1.01 seconds
Started Jul 25 06:05:14 PM PDT 24
Finished Jul 25 06:05:15 PM PDT 24
Peak memory 214836 kb
Host smart-332f1da2-128d-445a-a30f-6c404f42b8c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057685516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3057685516
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.776553280
Short name T648
Test name
Test status
Simulation time 11520587 ps
CPU time 0.88 seconds
Started Jul 25 06:05:14 PM PDT 24
Finished Jul 25 06:05:15 PM PDT 24
Peak memory 215956 kb
Host smart-1e7a2f93-4c52-46c3-a85b-41f60ad2a901
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776553280 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.776553280
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3799098793
Short name T51
Test name
Test status
Simulation time 104035235 ps
CPU time 1.23 seconds
Started Jul 25 06:05:20 PM PDT 24
Finished Jul 25 06:05:21 PM PDT 24
Peak memory 216808 kb
Host smart-0e55c991-2305-4930-bfa8-51b92f6c372b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799098793 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3799098793
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2570173097
Short name T203
Test name
Test status
Simulation time 21664003 ps
CPU time 1.1 seconds
Started Jul 25 06:05:20 PM PDT 24
Finished Jul 25 06:05:22 PM PDT 24
Peak memory 219276 kb
Host smart-a06d6e3e-4c26-419d-9b9a-45ef9e147e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570173097 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2570173097
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.896431399
Short name T609
Test name
Test status
Simulation time 65181808 ps
CPU time 1.07 seconds
Started Jul 25 06:05:29 PM PDT 24
Finished Jul 25 06:05:30 PM PDT 24
Peak memory 220248 kb
Host smart-8564cb62-a814-466e-8980-75edbab6da87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896431399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.896431399
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1033756449
Short name T56
Test name
Test status
Simulation time 26184951 ps
CPU time 0.86 seconds
Started Jul 25 06:05:13 PM PDT 24
Finished Jul 25 06:05:14 PM PDT 24
Peak memory 215696 kb
Host smart-f624d270-8a8c-4a6e-9381-3108b3b7689d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033756449 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1033756449
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1168438435
Short name T332
Test name
Test status
Simulation time 18829523 ps
CPU time 0.99 seconds
Started Jul 25 06:05:14 PM PDT 24
Finished Jul 25 06:05:15 PM PDT 24
Peak memory 215148 kb
Host smart-00664583-f05a-43aa-a9cf-71d3f19cb1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168438435 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1168438435
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.46350985
Short name T389
Test name
Test status
Simulation time 263530946 ps
CPU time 5.76 seconds
Started Jul 25 06:05:12 PM PDT 24
Finished Jul 25 06:05:18 PM PDT 24
Peak memory 215136 kb
Host smart-8ae1a570-9883-40ff-9e5d-e53315b4c6ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46350985 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.46350985
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3690891490
Short name T518
Test name
Test status
Simulation time 244817150700 ps
CPU time 1399.47 seconds
Started Jul 25 06:05:12 PM PDT 24
Finished Jul 25 06:28:32 PM PDT 24
Peak memory 224016 kb
Host smart-090084f3-2706-4caf-81c6-c978f7b73f2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690891490 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3690891490
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3770526558
Short name T197
Test name
Test status
Simulation time 37061705 ps
CPU time 1.11 seconds
Started Jul 25 06:05:14 PM PDT 24
Finished Jul 25 06:05:16 PM PDT 24
Peak memory 220068 kb
Host smart-baab2706-44da-4111-8429-b8381024dc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770526558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3770526558
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.874901181
Short name T878
Test name
Test status
Simulation time 49519894 ps
CPU time 0.91 seconds
Started Jul 25 06:05:18 PM PDT 24
Finished Jul 25 06:05:19 PM PDT 24
Peak memory 206608 kb
Host smart-a64a6175-2c83-40ea-a98e-66573dd5dfc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874901181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.874901181
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1742902125
Short name T149
Test name
Test status
Simulation time 40361400 ps
CPU time 1.23 seconds
Started Jul 25 06:05:12 PM PDT 24
Finished Jul 25 06:05:13 PM PDT 24
Peak memory 216788 kb
Host smart-23edd341-fdb5-4bf3-8397-b94132b3b427
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742902125 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1742902125
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3043571937
Short name T133
Test name
Test status
Simulation time 19104267 ps
CPU time 1.05 seconds
Started Jul 25 06:05:14 PM PDT 24
Finished Jul 25 06:05:16 PM PDT 24
Peak memory 218468 kb
Host smart-feebea07-87e4-4315-87da-6dff1c665e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043571937 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3043571937
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1785487842
Short name T661
Test name
Test status
Simulation time 54834557 ps
CPU time 1.88 seconds
Started Jul 25 06:05:17 PM PDT 24
Finished Jul 25 06:05:19 PM PDT 24
Peak memory 220092 kb
Host smart-2c9a6a81-e2a0-4ee6-9a6b-d251bfd5f7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785487842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1785487842
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1205275798
Short name T422
Test name
Test status
Simulation time 28833647 ps
CPU time 0.98 seconds
Started Jul 25 06:05:21 PM PDT 24
Finished Jul 25 06:05:22 PM PDT 24
Peak memory 215360 kb
Host smart-f9192bb8-9bbe-447d-ae1c-5cee6e097128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205275798 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1205275798
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3196626870
Short name T471
Test name
Test status
Simulation time 20458994 ps
CPU time 0.89 seconds
Started Jul 25 06:05:21 PM PDT 24
Finished Jul 25 06:05:22 PM PDT 24
Peak memory 215148 kb
Host smart-ca5b8bac-e882-4440-96ee-285cd14d8dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196626870 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3196626870
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1786222228
Short name T367
Test name
Test status
Simulation time 1122201366 ps
CPU time 4.89 seconds
Started Jul 25 06:05:18 PM PDT 24
Finished Jul 25 06:05:23 PM PDT 24
Peak memory 217140 kb
Host smart-e0012319-b361-4890-b3f7-bf82801d7cec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786222228 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1786222228
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2814000004
Short name T448
Test name
Test status
Simulation time 169324055633 ps
CPU time 996.48 seconds
Started Jul 25 06:05:10 PM PDT 24
Finished Jul 25 06:21:47 PM PDT 24
Peak memory 221452 kb
Host smart-fa1ade42-3dbf-4a01-8c42-bc13adbfed64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814000004 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2814000004
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1473678290
Short name T673
Test name
Test status
Simulation time 26215532 ps
CPU time 1.27 seconds
Started Jul 25 06:05:21 PM PDT 24
Finished Jul 25 06:05:23 PM PDT 24
Peak memory 219008 kb
Host smart-e012da32-0327-4a53-ac77-165fd15bb80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473678290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1473678290
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1319665766
Short name T454
Test name
Test status
Simulation time 59809545 ps
CPU time 0.87 seconds
Started Jul 25 06:05:14 PM PDT 24
Finished Jul 25 06:05:15 PM PDT 24
Peak memory 206476 kb
Host smart-1a48b3aa-bd31-4423-a01b-e05f6ebc3197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319665766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1319665766
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1859824821
Short name T600
Test name
Test status
Simulation time 13558082 ps
CPU time 0.88 seconds
Started Jul 25 06:05:22 PM PDT 24
Finished Jul 25 06:05:23 PM PDT 24
Peak memory 216284 kb
Host smart-7cd4c978-c3bc-464f-bedf-909fe3cb7a7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859824821 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1859824821
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3605247723
Short name T657
Test name
Test status
Simulation time 112551930 ps
CPU time 1.13 seconds
Started Jul 25 06:05:16 PM PDT 24
Finished Jul 25 06:05:18 PM PDT 24
Peak memory 216856 kb
Host smart-6804c52a-575c-4188-9f0b-2e2794c93562
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605247723 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3605247723
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3335231331
Short name T785
Test name
Test status
Simulation time 48067913 ps
CPU time 0.82 seconds
Started Jul 25 06:05:23 PM PDT 24
Finished Jul 25 06:05:24 PM PDT 24
Peak memory 218332 kb
Host smart-6f2c3357-0c00-4852-863b-240cb13c941e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335231331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3335231331
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_intr.3015439842
Short name T585
Test name
Test status
Simulation time 44172979 ps
CPU time 0.97 seconds
Started Jul 25 06:05:14 PM PDT 24
Finished Jul 25 06:05:15 PM PDT 24
Peak memory 223736 kb
Host smart-6caf8ecb-dd38-4533-8411-95b5f5bd22a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015439842 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3015439842
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3994197065
Short name T430
Test name
Test status
Simulation time 60639815 ps
CPU time 0.94 seconds
Started Jul 25 06:05:14 PM PDT 24
Finished Jul 25 06:05:16 PM PDT 24
Peak memory 215260 kb
Host smart-a840b846-7e1e-4cda-8319-cdffddd1a964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994197065 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3994197065
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.4170608267
Short name T458
Test name
Test status
Simulation time 386488391 ps
CPU time 2.82 seconds
Started Jul 25 06:05:11 PM PDT 24
Finished Jul 25 06:05:14 PM PDT 24
Peak memory 215236 kb
Host smart-ce39ff83-201b-40b3-835c-0f6f70cf1a1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170608267 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.4170608267
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3670315107
Short name T683
Test name
Test status
Simulation time 121811678351 ps
CPU time 1520.98 seconds
Started Jul 25 06:05:29 PM PDT 24
Finished Jul 25 06:30:50 PM PDT 24
Peak memory 227220 kb
Host smart-ff8489e2-8fc0-4ea4-9ec1-25dba1bc1a3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670315107 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3670315107
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert_test.744148527
Short name T385
Test name
Test status
Simulation time 25509740 ps
CPU time 0.86 seconds
Started Jul 25 06:05:26 PM PDT 24
Finished Jul 25 06:05:27 PM PDT 24
Peak memory 206692 kb
Host smart-a9d86877-d3b6-457e-8656-4e1ff8ccb497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744148527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.744148527
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.717433971
Short name T838
Test name
Test status
Simulation time 22274242 ps
CPU time 0.88 seconds
Started Jul 25 06:05:23 PM PDT 24
Finished Jul 25 06:05:24 PM PDT 24
Peak memory 215800 kb
Host smart-18137140-0cca-4777-940b-c27dce0048bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717433971 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.717433971
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2888136223
Short name T157
Test name
Test status
Simulation time 99284904 ps
CPU time 1.22 seconds
Started Jul 25 06:05:26 PM PDT 24
Finished Jul 25 06:05:28 PM PDT 24
Peak memory 219420 kb
Host smart-f97b3db5-4b07-4d73-b051-7b6555b16b98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888136223 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2888136223
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.267583920
Short name T117
Test name
Test status
Simulation time 32286105 ps
CPU time 0.9 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 215212 kb
Host smart-a36ae3f6-c9f8-4e81-90b1-57d87479098e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267583920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.267583920
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3239333605
Short name T300
Test name
Test status
Simulation time 79739321 ps
CPU time 1.46 seconds
Started Jul 25 06:05:13 PM PDT 24
Finished Jul 25 06:05:15 PM PDT 24
Peak memory 218480 kb
Host smart-0e28ee19-a680-4c25-a6a0-c6a4518506cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239333605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3239333605
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2053348530
Short name T537
Test name
Test status
Simulation time 39848990 ps
CPU time 0.9 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 215620 kb
Host smart-4abd4016-d7ea-4a71-9648-768ce2b404bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053348530 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2053348530
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2356785770
Short name T49
Test name
Test status
Simulation time 18069659 ps
CPU time 0.99 seconds
Started Jul 25 06:05:21 PM PDT 24
Finished Jul 25 06:05:22 PM PDT 24
Peak memory 215128 kb
Host smart-1caa7840-2b4e-4e89-9776-7753e74bd91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356785770 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2356785770
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3000728171
Short name T593
Test name
Test status
Simulation time 446725885 ps
CPU time 6.12 seconds
Started Jul 25 06:05:31 PM PDT 24
Finished Jul 25 06:05:37 PM PDT 24
Peak memory 215172 kb
Host smart-93e0591f-5a7e-43a3-9fd1-a67ad2d22740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000728171 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3000728171
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1833183133
Short name T746
Test name
Test status
Simulation time 107712301595 ps
CPU time 671.41 seconds
Started Jul 25 06:05:22 PM PDT 24
Finished Jul 25 06:16:34 PM PDT 24
Peak memory 220036 kb
Host smart-fea5bfc2-8217-43dc-a29b-81ded2362e50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833183133 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1833183133
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2871835898
Short name T775
Test name
Test status
Simulation time 47862813 ps
CPU time 1.16 seconds
Started Jul 25 06:03:53 PM PDT 24
Finished Jul 25 06:03:54 PM PDT 24
Peak memory 219304 kb
Host smart-71854ce3-a46b-4817-a962-35b480a2b088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871835898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2871835898
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1657352738
Short name T856
Test name
Test status
Simulation time 18099174 ps
CPU time 1 seconds
Started Jul 25 06:03:54 PM PDT 24
Finished Jul 25 06:03:55 PM PDT 24
Peak memory 206652 kb
Host smart-a5c8f8f9-8047-4262-a855-36ae83588dfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657352738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1657352738
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.4050781421
Short name T135
Test name
Test status
Simulation time 13818056 ps
CPU time 0.94 seconds
Started Jul 25 06:03:56 PM PDT 24
Finished Jul 25 06:03:58 PM PDT 24
Peak memory 216368 kb
Host smart-082e2e02-a4ff-45fc-883c-546fd64f29ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050781421 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.4050781421
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1447204723
Short name T949
Test name
Test status
Simulation time 26027226 ps
CPU time 1.04 seconds
Started Jul 25 06:03:55 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 218432 kb
Host smart-84aa020f-8193-47cc-b893-b44a0403e9c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447204723 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1447204723
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3748790677
Short name T873
Test name
Test status
Simulation time 51538987 ps
CPU time 0.98 seconds
Started Jul 25 06:03:52 PM PDT 24
Finished Jul 25 06:03:54 PM PDT 24
Peak memory 223720 kb
Host smart-a6a31259-27e3-4da0-a7fb-432298fc4d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748790677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3748790677
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1674319095
Short name T33
Test name
Test status
Simulation time 213459454 ps
CPU time 3.18 seconds
Started Jul 25 06:03:53 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 220244 kb
Host smart-3c2faed3-de80-472f-bb4f-ed4606a635bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674319095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1674319095
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2311224067
Short name T383
Test name
Test status
Simulation time 20964117 ps
CPU time 1.09 seconds
Started Jul 25 06:03:57 PM PDT 24
Finished Jul 25 06:03:58 PM PDT 24
Peak memory 215320 kb
Host smart-c25cbc2e-72a5-4e05-9492-fdeb71f5076f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311224067 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2311224067
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2920671111
Short name T716
Test name
Test status
Simulation time 14897408 ps
CPU time 1.02 seconds
Started Jul 25 06:03:58 PM PDT 24
Finished Jul 25 06:03:59 PM PDT 24
Peak memory 207096 kb
Host smart-47bb32d8-b0c9-45b8-a3e8-65a1152fbea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920671111 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2920671111
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.950816312
Short name T328
Test name
Test status
Simulation time 21347935 ps
CPU time 0.9 seconds
Started Jul 25 06:03:54 PM PDT 24
Finished Jul 25 06:03:55 PM PDT 24
Peak memory 215144 kb
Host smart-efa57865-317e-4fc2-ab7d-752485400b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950816312 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.950816312
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2395453551
Short name T347
Test name
Test status
Simulation time 90694555 ps
CPU time 1.42 seconds
Started Jul 25 06:03:54 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 215232 kb
Host smart-40768ec9-0d8c-4444-857a-8c9e857f2569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395453551 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2395453551
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2806001907
Short name T919
Test name
Test status
Simulation time 47216167796 ps
CPU time 1009.19 seconds
Started Jul 25 06:03:56 PM PDT 24
Finished Jul 25 06:20:46 PM PDT 24
Peak memory 218748 kb
Host smart-772d76a7-de39-4250-aeed-e8de61817b91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806001907 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2806001907
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.3439591432
Short name T279
Test name
Test status
Simulation time 26432619 ps
CPU time 1.23 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 218456 kb
Host smart-b6e9a80f-1e8b-4f95-b47a-9d5dabf3cc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439591432 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.3439591432
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.3303649855
Short name T859
Test name
Test status
Simulation time 25947338 ps
CPU time 1.06 seconds
Started Jul 25 06:05:24 PM PDT 24
Finished Jul 25 06:05:25 PM PDT 24
Peak memory 219508 kb
Host smart-8db62fa1-e589-4470-92a7-ec4e0e8a59f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303649855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3303649855
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.789607184
Short name T948
Test name
Test status
Simulation time 28472181 ps
CPU time 1.24 seconds
Started Jul 25 06:05:28 PM PDT 24
Finished Jul 25 06:05:30 PM PDT 24
Peak memory 219912 kb
Host smart-3b67bd6c-7387-4d9a-8686-c61b2a2c5881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789607184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.789607184
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.94419036
Short name T146
Test name
Test status
Simulation time 67765691 ps
CPU time 1.24 seconds
Started Jul 25 06:05:24 PM PDT 24
Finished Jul 25 06:05:25 PM PDT 24
Peak memory 220000 kb
Host smart-bedaf731-8d79-4d4b-90e0-481164776869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94419036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.94419036
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_genbits.3640958064
Short name T11
Test name
Test status
Simulation time 28460187 ps
CPU time 1.23 seconds
Started Jul 25 06:05:24 PM PDT 24
Finished Jul 25 06:05:25 PM PDT 24
Peak memory 219756 kb
Host smart-2000aed5-7a22-4d77-b528-35b76f658268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640958064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3640958064
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1048851300
Short name T841
Test name
Test status
Simulation time 22765419 ps
CPU time 1.19 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 220380 kb
Host smart-3531f00f-3a73-49a6-94f4-b4403f748e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048851300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1048851300
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.1773748165
Short name T972
Test name
Test status
Simulation time 28803287 ps
CPU time 0.91 seconds
Started Jul 25 06:05:24 PM PDT 24
Finished Jul 25 06:05:25 PM PDT 24
Peak memory 218220 kb
Host smart-e1b25e18-d411-4252-bba5-9f9f6a790b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773748165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1773748165
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2461567499
Short name T333
Test name
Test status
Simulation time 108235586 ps
CPU time 1.48 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:27 PM PDT 24
Peak memory 218712 kb
Host smart-0e134cde-2731-4e7b-afcd-d309ca2eb4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461567499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2461567499
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2429304623
Short name T825
Test name
Test status
Simulation time 105995567 ps
CPU time 1.16 seconds
Started Jul 25 06:05:23 PM PDT 24
Finished Jul 25 06:05:24 PM PDT 24
Peak memory 220964 kb
Host smart-2b7f934b-6e68-4d9e-ae12-0c79b27d27b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429304623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2429304623
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_genbits.1857521907
Short name T610
Test name
Test status
Simulation time 52549904 ps
CPU time 1.27 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 217184 kb
Host smart-ba006dd7-7f8a-44d2-b74f-24be686913d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857521907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1857521907
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3502515146
Short name T703
Test name
Test status
Simulation time 26807797 ps
CPU time 1.18 seconds
Started Jul 25 06:05:20 PM PDT 24
Finished Jul 25 06:05:21 PM PDT 24
Peak memory 219532 kb
Host smart-c4de4bdb-4136-4fa1-a218-13bad23e429a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502515146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3502515146
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.1617349073
Short name T786
Test name
Test status
Simulation time 29230871 ps
CPU time 1.25 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 219284 kb
Host smart-3e08f6f8-18cc-48d3-a0dd-36f89c05c8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617349073 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1617349073
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1727381782
Short name T25
Test name
Test status
Simulation time 48714107 ps
CPU time 1.6 seconds
Started Jul 25 06:05:22 PM PDT 24
Finished Jul 25 06:05:24 PM PDT 24
Peak memory 218432 kb
Host smart-edcd1822-272f-41a1-9648-1831a1aca32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727381782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1727381782
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.381934667
Short name T281
Test name
Test status
Simulation time 67610698 ps
CPU time 1.12 seconds
Started Jul 25 06:05:26 PM PDT 24
Finished Jul 25 06:05:27 PM PDT 24
Peak memory 218988 kb
Host smart-ef61e89a-ec51-400b-8fb1-70a5d326d010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381934667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.381934667
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2811366945
Short name T60
Test name
Test status
Simulation time 25905515 ps
CPU time 1.12 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 218200 kb
Host smart-d935662f-638f-46ef-94e6-fe95180711b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811366945 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2811366945
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3012781921
Short name T27
Test name
Test status
Simulation time 35764745 ps
CPU time 1.43 seconds
Started Jul 25 06:05:23 PM PDT 24
Finished Jul 25 06:05:24 PM PDT 24
Peak memory 217508 kb
Host smart-997f681c-c6d2-4bbe-bf81-430e7da6870d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012781921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3012781921
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2184196273
Short name T442
Test name
Test status
Simulation time 32206044 ps
CPU time 1.23 seconds
Started Jul 25 06:06:06 PM PDT 24
Finished Jul 25 06:06:08 PM PDT 24
Peak memory 219512 kb
Host smart-77a180ce-e6b3-4657-96b3-d7c1f9816f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184196273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2184196273
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_genbits.2005224892
Short name T410
Test name
Test status
Simulation time 34834903 ps
CPU time 1.02 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 217168 kb
Host smart-3876d69b-5a13-47e7-99a2-8dd98c9913ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005224892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2005224892
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.2510579458
Short name T734
Test name
Test status
Simulation time 92337875 ps
CPU time 1.23 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 219520 kb
Host smart-aac2c25c-ca82-4420-bf8f-02df2be13eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510579458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2510579458
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.2749980902
Short name T441
Test name
Test status
Simulation time 26187959 ps
CPU time 1.28 seconds
Started Jul 25 06:05:24 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 218660 kb
Host smart-7056cce5-87ba-425f-ab40-dc90f5bf1d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749980902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2749980902
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1646619668
Short name T445
Test name
Test status
Simulation time 56906032 ps
CPU time 1.75 seconds
Started Jul 25 06:05:26 PM PDT 24
Finished Jul 25 06:05:28 PM PDT 24
Peak memory 215184 kb
Host smart-d56fc199-b77d-4b81-998c-6bb2bf638fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646619668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1646619668
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3325634815
Short name T523
Test name
Test status
Simulation time 22920512 ps
CPU time 1.21 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 220216 kb
Host smart-01ef7c83-67e9-43c8-889b-d0c809d647dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325634815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3325634815
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2876189345
Short name T582
Test name
Test status
Simulation time 18432916 ps
CPU time 1.04 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 218320 kb
Host smart-a9fbc258-3e6e-4f0d-96d7-b1dd56f0369b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876189345 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2876189345
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1209290613
Short name T591
Test name
Test status
Simulation time 66864484 ps
CPU time 1.14 seconds
Started Jul 25 06:05:24 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 217272 kb
Host smart-f24f59b7-703a-45e0-89d7-670cd58192c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209290613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1209290613
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1633008491
Short name T134
Test name
Test status
Simulation time 69900146 ps
CPU time 1.05 seconds
Started Jul 25 06:05:27 PM PDT 24
Finished Jul 25 06:05:28 PM PDT 24
Peak memory 219640 kb
Host smart-1304a19d-dcd1-48c9-a030-2a80a7f14bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633008491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1633008491
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.4097346242
Short name T766
Test name
Test status
Simulation time 67386583 ps
CPU time 1.32 seconds
Started Jul 25 06:05:24 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 218192 kb
Host smart-f7757707-6e9b-4216-a256-86b390284e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097346242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.4097346242
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert_test.4167159306
Short name T601
Test name
Test status
Simulation time 17929188 ps
CPU time 1 seconds
Started Jul 25 06:03:55 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 206672 kb
Host smart-420e0f4a-1ddc-4559-9d59-f0b658d4129c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167159306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.4167159306
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.790240250
Short name T635
Test name
Test status
Simulation time 108618343 ps
CPU time 0.86 seconds
Started Jul 25 06:03:56 PM PDT 24
Finished Jul 25 06:03:57 PM PDT 24
Peak memory 215200 kb
Host smart-36f6614d-f575-4886-99fb-e12ca80afbcf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790240250 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.790240250
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3884633423
Short name T403
Test name
Test status
Simulation time 23289947 ps
CPU time 1.02 seconds
Started Jul 25 06:03:53 PM PDT 24
Finished Jul 25 06:03:54 PM PDT 24
Peak memory 218548 kb
Host smart-b7b7602e-0641-4467-a087-f2a496c17190
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884633423 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3884633423
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.4209130767
Short name T655
Test name
Test status
Simulation time 32075815 ps
CPU time 0.93 seconds
Started Jul 25 06:03:51 PM PDT 24
Finished Jul 25 06:03:52 PM PDT 24
Peak memory 218452 kb
Host smart-5e2c0661-808e-460e-8ae7-f4730499d671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209130767 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.4209130767
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.160287591
Short name T713
Test name
Test status
Simulation time 82028293 ps
CPU time 1.5 seconds
Started Jul 25 06:03:58 PM PDT 24
Finished Jul 25 06:04:00 PM PDT 24
Peak memory 218832 kb
Host smart-6de77c37-366e-4fea-a6fc-c54bb813c069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160287591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.160287591
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1015401320
Short name T90
Test name
Test status
Simulation time 23446833 ps
CPU time 1.01 seconds
Started Jul 25 06:03:57 PM PDT 24
Finished Jul 25 06:03:58 PM PDT 24
Peak memory 215752 kb
Host smart-a7f4beb3-175f-43ee-ad65-ba2c59c41f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015401320 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1015401320
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3472330927
Short name T280
Test name
Test status
Simulation time 30106050 ps
CPU time 0.91 seconds
Started Jul 25 06:03:55 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 207008 kb
Host smart-315857ed-13b9-4de7-a56e-f570bb4e5fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472330927 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3472330927
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.277348197
Short name T872
Test name
Test status
Simulation time 27889132 ps
CPU time 0.96 seconds
Started Jul 25 06:03:54 PM PDT 24
Finished Jul 25 06:03:55 PM PDT 24
Peak memory 215148 kb
Host smart-243a1af9-aab4-4975-aadc-ef667416e535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277348197 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.277348197
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1745627617
Short name T110
Test name
Test status
Simulation time 92873384 ps
CPU time 2.27 seconds
Started Jul 25 06:03:54 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 217088 kb
Host smart-61ae39b6-fe7e-4a82-9bf1-d5215256b065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745627617 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1745627617
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.301712877
Short name T641
Test name
Test status
Simulation time 53737477167 ps
CPU time 668.21 seconds
Started Jul 25 06:03:57 PM PDT 24
Finished Jul 25 06:15:05 PM PDT 24
Peak memory 218704 kb
Host smart-68a58775-07a6-4032-8084-5e363bab412f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301712877 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.301712877
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1108058499
Short name T730
Test name
Test status
Simulation time 30399883 ps
CPU time 1.33 seconds
Started Jul 25 06:05:24 PM PDT 24
Finished Jul 25 06:05:25 PM PDT 24
Peak memory 215588 kb
Host smart-724abbb3-90d2-4e17-9ebb-efd914575811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108058499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1108058499
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.533658143
Short name T846
Test name
Test status
Simulation time 28606527 ps
CPU time 1.23 seconds
Started Jul 25 06:05:27 PM PDT 24
Finished Jul 25 06:05:28 PM PDT 24
Peak memory 220456 kb
Host smart-243ba78a-6098-4bc1-9064-ce8d1bab87c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533658143 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.533658143
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.435544400
Short name T392
Test name
Test status
Simulation time 56706544 ps
CPU time 1.07 seconds
Started Jul 25 06:05:27 PM PDT 24
Finished Jul 25 06:05:28 PM PDT 24
Peak memory 219752 kb
Host smart-0ffe998c-6dfb-4167-8f58-6ef1f627b591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435544400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.435544400
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.508074678
Short name T101
Test name
Test status
Simulation time 25668922 ps
CPU time 1.32 seconds
Started Jul 25 06:05:29 PM PDT 24
Finished Jul 25 06:05:31 PM PDT 24
Peak memory 218588 kb
Host smart-c922010a-2b8f-4639-9ceb-2e476d370f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508074678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.508074678
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1723225615
Short name T666
Test name
Test status
Simulation time 64273220 ps
CPU time 1.18 seconds
Started Jul 25 06:05:29 PM PDT 24
Finished Jul 25 06:05:30 PM PDT 24
Peak memory 220588 kb
Host smart-5f9803f7-9e6e-49ea-81c7-804a6c2e2ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723225615 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1723225615
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2088987071
Short name T682
Test name
Test status
Simulation time 86151338 ps
CPU time 1.19 seconds
Started Jul 25 06:05:25 PM PDT 24
Finished Jul 25 06:05:27 PM PDT 24
Peak memory 217056 kb
Host smart-5117f367-5c42-4b84-b92b-b0ae33e7e025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088987071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2088987071
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.2858585253
Short name T767
Test name
Test status
Simulation time 145357127 ps
CPU time 1.17 seconds
Started Jul 25 06:05:27 PM PDT 24
Finished Jul 25 06:05:29 PM PDT 24
Peak memory 220112 kb
Host smart-74dd1a83-c7cb-4bf6-9ddb-d9f487d5e391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858585253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2858585253
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.3557124701
Short name T139
Test name
Test status
Simulation time 21869086 ps
CPU time 1.01 seconds
Started Jul 25 06:05:26 PM PDT 24
Finished Jul 25 06:05:27 PM PDT 24
Peak memory 223896 kb
Host smart-a75f41a9-1cdb-407d-a5b0-89e830004061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557124701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3557124701
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3594018791
Short name T232
Test name
Test status
Simulation time 253126137 ps
CPU time 3.74 seconds
Started Jul 25 06:05:26 PM PDT 24
Finished Jul 25 06:05:30 PM PDT 24
Peak memory 220196 kb
Host smart-23a8ca0c-0b23-4193-8fdc-508c78e90905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594018791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3594018791
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2421825313
Short name T499
Test name
Test status
Simulation time 27861219 ps
CPU time 1.29 seconds
Started Jul 25 06:05:23 PM PDT 24
Finished Jul 25 06:05:25 PM PDT 24
Peak memory 219620 kb
Host smart-a7a21b71-699f-4f11-b1a9-6292ff58a46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421825313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2421825313
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1398706689
Short name T166
Test name
Test status
Simulation time 25340020 ps
CPU time 1.01 seconds
Started Jul 25 06:05:24 PM PDT 24
Finished Jul 25 06:05:26 PM PDT 24
Peak memory 219600 kb
Host smart-df717513-3c52-4771-9f21-9f7828415e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398706689 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1398706689
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3107115150
Short name T598
Test name
Test status
Simulation time 38464714 ps
CPU time 1.52 seconds
Started Jul 25 06:05:24 PM PDT 24
Finished Jul 25 06:05:25 PM PDT 24
Peak memory 215308 kb
Host smart-7cfee38a-dc14-4503-a48b-7967a3e66ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107115150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3107115150
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.594483267
Short name T62
Test name
Test status
Simulation time 67485843 ps
CPU time 1.12 seconds
Started Jul 25 06:05:27 PM PDT 24
Finished Jul 25 06:05:28 PM PDT 24
Peak memory 218640 kb
Host smart-54b38a7d-730c-4325-a0f6-8be197b52c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594483267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.594483267
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.3207135526
Short name T947
Test name
Test status
Simulation time 31523815 ps
CPU time 1.03 seconds
Started Jul 25 06:05:26 PM PDT 24
Finished Jul 25 06:05:28 PM PDT 24
Peak memory 218476 kb
Host smart-bca9a1e7-5f44-4df2-b15c-71af00be2178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207135526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3207135526
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1961413677
Short name T306
Test name
Test status
Simulation time 52573031 ps
CPU time 1.86 seconds
Started Jul 25 06:05:27 PM PDT 24
Finished Jul 25 06:05:29 PM PDT 24
Peak memory 218380 kb
Host smart-26cbdcc1-65bb-4d8b-9c1e-a40550c20bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961413677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1961413677
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2490167008
Short name T759
Test name
Test status
Simulation time 100094917 ps
CPU time 1.1 seconds
Started Jul 25 06:05:31 PM PDT 24
Finished Jul 25 06:05:32 PM PDT 24
Peak memory 220600 kb
Host smart-47308658-380c-403a-80b6-01a36f7c6beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490167008 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2490167008
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.4193548055
Short name T258
Test name
Test status
Simulation time 79711332 ps
CPU time 2.67 seconds
Started Jul 25 06:05:29 PM PDT 24
Finished Jul 25 06:05:32 PM PDT 24
Peak memory 219848 kb
Host smart-f8dc70c2-048f-4790-b883-f14c6f3cfd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193548055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.4193548055
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.3494117304
Short name T654
Test name
Test status
Simulation time 25798788 ps
CPU time 1.24 seconds
Started Jul 25 06:05:32 PM PDT 24
Finished Jul 25 06:05:33 PM PDT 24
Peak memory 219776 kb
Host smart-d0a9c8f5-e86d-466b-91a3-3de18bbf4d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494117304 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.3494117304
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.647194194
Short name T849
Test name
Test status
Simulation time 18177715 ps
CPU time 1.06 seconds
Started Jul 25 06:05:29 PM PDT 24
Finished Jul 25 06:05:30 PM PDT 24
Peak memory 218264 kb
Host smart-94cba056-1ead-4c4f-b7ea-904de4100a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647194194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.647194194
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1266524457
Short name T314
Test name
Test status
Simulation time 208765375 ps
CPU time 1.41 seconds
Started Jul 25 06:05:35 PM PDT 24
Finished Jul 25 06:05:36 PM PDT 24
Peak memory 217408 kb
Host smart-5dcac61a-0f5e-449d-af32-137f20fa73c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266524457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1266524457
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.595910818
Short name T861
Test name
Test status
Simulation time 84583996 ps
CPU time 1.12 seconds
Started Jul 25 06:05:30 PM PDT 24
Finished Jul 25 06:05:31 PM PDT 24
Peak memory 218456 kb
Host smart-0c7d8ad5-46b8-4fd0-9fa6-42f4288d3e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595910818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.595910818
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.3419619164
Short name T138
Test name
Test status
Simulation time 29349514 ps
CPU time 0.9 seconds
Started Jul 25 06:05:35 PM PDT 24
Finished Jul 25 06:05:36 PM PDT 24
Peak memory 218872 kb
Host smart-3493331e-4498-4422-8163-37a78ffb374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419619164 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3419619164
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.495130694
Short name T896
Test name
Test status
Simulation time 102451239 ps
CPU time 1.21 seconds
Started Jul 25 06:05:30 PM PDT 24
Finished Jul 25 06:05:31 PM PDT 24
Peak memory 217104 kb
Host smart-d5ba7474-bde6-4df5-b71a-1a6638b61e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495130694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.495130694
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1663601545
Short name T802
Test name
Test status
Simulation time 191686521 ps
CPU time 1.33 seconds
Started Jul 25 06:05:30 PM PDT 24
Finished Jul 25 06:05:31 PM PDT 24
Peak memory 215556 kb
Host smart-601d02b7-d575-4c6b-97f5-76157f366330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663601545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1663601545
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.3092826256
Short name T194
Test name
Test status
Simulation time 19148980 ps
CPU time 1.17 seconds
Started Jul 25 06:05:31 PM PDT 24
Finished Jul 25 06:05:32 PM PDT 24
Peak memory 223928 kb
Host smart-68268465-9832-45e1-86dc-a611ac98466a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092826256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3092826256
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.102264560
Short name T963
Test name
Test status
Simulation time 46081353 ps
CPU time 1.21 seconds
Started Jul 25 06:05:36 PM PDT 24
Finished Jul 25 06:05:37 PM PDT 24
Peak memory 218400 kb
Host smart-814303ee-9a26-44f5-8d39-51a1b68f97d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102264560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.102264560
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.1974345416
Short name T202
Test name
Test status
Simulation time 87683150 ps
CPU time 1.22 seconds
Started Jul 25 06:05:30 PM PDT 24
Finished Jul 25 06:05:32 PM PDT 24
Peak memory 220012 kb
Host smart-28502730-2241-4740-9e72-1f91f13987f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974345416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.1974345416
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.431346402
Short name T167
Test name
Test status
Simulation time 21833563 ps
CPU time 1.13 seconds
Started Jul 25 06:05:29 PM PDT 24
Finished Jul 25 06:05:31 PM PDT 24
Peak memory 219776 kb
Host smart-cc95c3fc-1ca6-4996-bcc4-240abd284ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431346402 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.431346402
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1725678001
Short name T35
Test name
Test status
Simulation time 53279183 ps
CPU time 1.32 seconds
Started Jul 25 06:05:30 PM PDT 24
Finished Jul 25 06:05:32 PM PDT 24
Peak memory 218220 kb
Host smart-c6fc22c8-b06b-43d4-a3df-f2d230099ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725678001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1725678001
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2464711598
Short name T866
Test name
Test status
Simulation time 139114384 ps
CPU time 1.16 seconds
Started Jul 25 06:03:56 PM PDT 24
Finished Jul 25 06:03:58 PM PDT 24
Peak memory 215580 kb
Host smart-41cade0e-d1ef-494b-88a3-caa2bc38fea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464711598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2464711598
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.876319032
Short name T497
Test name
Test status
Simulation time 47639031 ps
CPU time 0.85 seconds
Started Jul 25 06:03:57 PM PDT 24
Finished Jul 25 06:03:58 PM PDT 24
Peak memory 214828 kb
Host smart-3119d61a-f7a1-4571-a2a0-0801a84b86dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876319032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.876319032
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3611297297
Short name T892
Test name
Test status
Simulation time 13936395 ps
CPU time 0.91 seconds
Started Jul 25 06:03:57 PM PDT 24
Finished Jul 25 06:03:58 PM PDT 24
Peak memory 215444 kb
Host smart-68100913-1e34-4044-b815-5edfee0ca774
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611297297 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3611297297
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.4218172443
Short name T834
Test name
Test status
Simulation time 37631736 ps
CPU time 1.04 seconds
Started Jul 25 06:03:57 PM PDT 24
Finished Jul 25 06:03:59 PM PDT 24
Peak memory 216648 kb
Host smart-f23daef6-6597-4b6f-b957-ee2c81792a36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218172443 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.4218172443
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.232433526
Short name T718
Test name
Test status
Simulation time 232695024 ps
CPU time 1.33 seconds
Started Jul 25 06:04:00 PM PDT 24
Finished Jul 25 06:04:02 PM PDT 24
Peak memory 225604 kb
Host smart-380fe11c-df09-4e01-b73a-d165c2cab940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232433526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.232433526
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3620285584
Short name T671
Test name
Test status
Simulation time 36635981 ps
CPU time 1.42 seconds
Started Jul 25 06:03:59 PM PDT 24
Finished Jul 25 06:04:00 PM PDT 24
Peak memory 218540 kb
Host smart-7526f81f-97b6-41e1-aacf-1651a0b4f3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620285584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3620285584
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1135314452
Short name T80
Test name
Test status
Simulation time 20112623 ps
CPU time 1.08 seconds
Started Jul 25 06:03:59 PM PDT 24
Finished Jul 25 06:04:00 PM PDT 24
Peak memory 215744 kb
Host smart-ef7b5744-b1ca-402d-8c7e-903e81c1a61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135314452 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1135314452
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.4269610502
Short name T78
Test name
Test status
Simulation time 22114880 ps
CPU time 0.94 seconds
Started Jul 25 06:04:00 PM PDT 24
Finished Jul 25 06:04:01 PM PDT 24
Peak memory 206972 kb
Host smart-b5d164e6-dd3c-44b9-a407-c116a5dda423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269610502 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.4269610502
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.81965146
Short name T504
Test name
Test status
Simulation time 41465380 ps
CPU time 0.92 seconds
Started Jul 25 06:03:55 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 215204 kb
Host smart-3cabe2fe-cca3-4d2f-b8f2-81497b9b6af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81965146 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.81965146
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2567991315
Short name T721
Test name
Test status
Simulation time 602524005 ps
CPU time 3.57 seconds
Started Jul 25 06:03:52 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 217240 kb
Host smart-4194b621-bd5e-4d8f-a808-f127c31354ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567991315 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2567991315
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2690076477
Short name T814
Test name
Test status
Simulation time 14831398900 ps
CPU time 315.61 seconds
Started Jul 25 06:03:59 PM PDT 24
Finished Jul 25 06:09:15 PM PDT 24
Peak memory 221672 kb
Host smart-525b117a-f176-4eeb-9441-38444f0ebecc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690076477 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2690076477
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1779697618
Short name T769
Test name
Test status
Simulation time 32362944 ps
CPU time 1.29 seconds
Started Jul 25 06:05:34 PM PDT 24
Finished Jul 25 06:05:35 PM PDT 24
Peak memory 225736 kb
Host smart-7a605271-5d2e-4134-84ba-5ced2e91511d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779697618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1779697618
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.4026381615
Short name T67
Test name
Test status
Simulation time 61583541 ps
CPU time 1.06 seconds
Started Jul 25 06:05:30 PM PDT 24
Finished Jul 25 06:05:31 PM PDT 24
Peak memory 215188 kb
Host smart-185d8362-b193-4646-a947-b3f15e0e12c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026381615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.4026381615
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2290674908
Short name T640
Test name
Test status
Simulation time 41374644 ps
CPU time 1.13 seconds
Started Jul 25 06:05:30 PM PDT 24
Finished Jul 25 06:05:31 PM PDT 24
Peak memory 219872 kb
Host smart-645367ac-47b8-41ef-8b1c-8bbafbf88904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290674908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2290674908
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.5931560
Short name T45
Test name
Test status
Simulation time 23461747 ps
CPU time 1.04 seconds
Started Jul 25 06:05:33 PM PDT 24
Finished Jul 25 06:05:34 PM PDT 24
Peak memory 223916 kb
Host smart-1de02001-efb0-4ad5-9461-c4966776addb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5931560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.5931560
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.833742270
Short name T644
Test name
Test status
Simulation time 31220727 ps
CPU time 1.33 seconds
Started Jul 25 06:05:28 PM PDT 24
Finished Jul 25 06:05:30 PM PDT 24
Peak memory 218524 kb
Host smart-98eaa127-9e55-45bf-9280-e9938c2a2e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833742270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.833742270
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.2773288848
Short name T102
Test name
Test status
Simulation time 29735246 ps
CPU time 1.22 seconds
Started Jul 25 06:05:31 PM PDT 24
Finished Jul 25 06:05:32 PM PDT 24
Peak memory 217204 kb
Host smart-d6b030ae-242d-4723-99d8-f7e5a91fc934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773288848 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2773288848
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1764841309
Short name T887
Test name
Test status
Simulation time 158656289 ps
CPU time 1.09 seconds
Started Jul 25 06:05:31 PM PDT 24
Finished Jul 25 06:05:32 PM PDT 24
Peak memory 217108 kb
Host smart-04b35230-156a-4269-bb4f-dccc4dccfe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764841309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1764841309
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3247975023
Short name T566
Test name
Test status
Simulation time 35501319 ps
CPU time 1.12 seconds
Started Jul 25 06:05:36 PM PDT 24
Finished Jul 25 06:05:37 PM PDT 24
Peak memory 219824 kb
Host smart-18bf8a40-ac2f-4b5a-946b-4cf8b3922b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247975023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3247975023
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.4062613335
Short name T979
Test name
Test status
Simulation time 18248441 ps
CPU time 1.1 seconds
Started Jul 25 06:05:33 PM PDT 24
Finished Jul 25 06:05:34 PM PDT 24
Peak memory 218544 kb
Host smart-79e14cdc-b8f1-4099-9293-80c19d62c3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062613335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.4062613335
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3663353133
Short name T316
Test name
Test status
Simulation time 58749517 ps
CPU time 1.31 seconds
Started Jul 25 06:05:32 PM PDT 24
Finished Jul 25 06:05:34 PM PDT 24
Peak memory 218404 kb
Host smart-435e6c0d-8109-40ee-a6e8-46ee51e384f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663353133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3663353133
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.3411473927
Short name T514
Test name
Test status
Simulation time 25202156 ps
CPU time 1.25 seconds
Started Jul 25 06:05:34 PM PDT 24
Finished Jul 25 06:05:35 PM PDT 24
Peak memory 218536 kb
Host smart-e6b1dd88-dfe2-4d45-90d5-7acdec907ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411473927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.3411473927
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.703703906
Short name T153
Test name
Test status
Simulation time 20565792 ps
CPU time 1.25 seconds
Started Jul 25 06:05:30 PM PDT 24
Finished Jul 25 06:05:31 PM PDT 24
Peak memory 229552 kb
Host smart-1962b64a-944a-48f2-b76d-c5f8b627f830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703703906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.703703906
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.628844361
Short name T37
Test name
Test status
Simulation time 28515465 ps
CPU time 1.26 seconds
Started Jul 25 06:05:31 PM PDT 24
Finished Jul 25 06:05:33 PM PDT 24
Peak memory 218480 kb
Host smart-765e0f91-2d1d-494a-880f-d2e91ebf5075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628844361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.628844361
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.830078217
Short name T622
Test name
Test status
Simulation time 37775504 ps
CPU time 1.09 seconds
Started Jul 25 06:05:35 PM PDT 24
Finished Jul 25 06:05:36 PM PDT 24
Peak memory 218196 kb
Host smart-27c39b7a-861e-456a-a544-c57d7fac8fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830078217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.830078217
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.2207938745
Short name T193
Test name
Test status
Simulation time 35250923 ps
CPU time 0.89 seconds
Started Jul 25 06:05:35 PM PDT 24
Finished Jul 25 06:05:36 PM PDT 24
Peak memory 218168 kb
Host smart-9c7cbafb-7575-46d2-aa5d-02d6fce724b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207938745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2207938745
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.774868388
Short name T520
Test name
Test status
Simulation time 86612637 ps
CPU time 1.48 seconds
Started Jul 25 06:05:32 PM PDT 24
Finished Jul 25 06:05:33 PM PDT 24
Peak memory 220192 kb
Host smart-492de724-1a6f-46f1-8447-624fe4944146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774868388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.774868388
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3244193959
Short name T121
Test name
Test status
Simulation time 27027806 ps
CPU time 0.88 seconds
Started Jul 25 06:05:35 PM PDT 24
Finished Jul 25 06:05:36 PM PDT 24
Peak memory 218440 kb
Host smart-f640d43b-b247-4ff6-b1b7-9a04012f599c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244193959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3244193959
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3670789439
Short name T969
Test name
Test status
Simulation time 53024489 ps
CPU time 1.21 seconds
Started Jul 25 06:05:33 PM PDT 24
Finished Jul 25 06:05:34 PM PDT 24
Peak memory 218744 kb
Host smart-a8c3d0b5-813d-4556-be1a-8dd29da156b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670789439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3670789439
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.1780644149
Short name T516
Test name
Test status
Simulation time 27627322 ps
CPU time 1.06 seconds
Started Jul 25 06:05:30 PM PDT 24
Finished Jul 25 06:05:31 PM PDT 24
Peak memory 218408 kb
Host smart-bdda0a5b-34b5-4489-9078-d8f3df585e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780644149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.1780644149
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3850714277
Short name T164
Test name
Test status
Simulation time 38084381 ps
CPU time 1.26 seconds
Started Jul 25 06:05:33 PM PDT 24
Finished Jul 25 06:05:34 PM PDT 24
Peak memory 229656 kb
Host smart-64e2dcbc-d5c6-4a81-9b07-de629958266b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850714277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3850714277
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.914748835
Short name T967
Test name
Test status
Simulation time 107270903 ps
CPU time 1.36 seconds
Started Jul 25 06:05:32 PM PDT 24
Finished Jul 25 06:05:33 PM PDT 24
Peak memory 219112 kb
Host smart-2fa6dc34-0c67-4385-868e-2e0fce69084c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914748835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.914748835
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.2593080950
Short name T702
Test name
Test status
Simulation time 43785456 ps
CPU time 1.22 seconds
Started Jul 25 06:05:32 PM PDT 24
Finished Jul 25 06:05:33 PM PDT 24
Peak memory 218620 kb
Host smart-94c32e66-ccef-404e-8667-15bd87e2e55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593080950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.2593080950
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.333919292
Short name T179
Test name
Test status
Simulation time 40736343 ps
CPU time 0.87 seconds
Started Jul 25 06:05:32 PM PDT 24
Finished Jul 25 06:05:33 PM PDT 24
Peak memory 218300 kb
Host smart-81200e6f-3927-4e8d-b45e-93e678a6b10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333919292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.333919292
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3115179064
Short name T707
Test name
Test status
Simulation time 103546934 ps
CPU time 1.04 seconds
Started Jul 25 06:05:36 PM PDT 24
Finished Jul 25 06:05:37 PM PDT 24
Peak memory 217088 kb
Host smart-c70dfab2-6177-47db-b1a6-8d68b7e30440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115179064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3115179064
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.3513991341
Short name T860
Test name
Test status
Simulation time 52176683 ps
CPU time 1.32 seconds
Started Jul 25 06:05:30 PM PDT 24
Finished Jul 25 06:05:31 PM PDT 24
Peak memory 220240 kb
Host smart-4c3ad60a-701e-4566-8408-f9e5539dfcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513991341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.3513991341
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.233282153
Short name T918
Test name
Test status
Simulation time 20051491 ps
CPU time 1.06 seconds
Started Jul 25 06:05:35 PM PDT 24
Finished Jul 25 06:05:36 PM PDT 24
Peak memory 218424 kb
Host smart-211a2c0a-3b6a-470e-974c-14ac9147c0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233282153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.233282153
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1075113232
Short name T330
Test name
Test status
Simulation time 38479149 ps
CPU time 1.62 seconds
Started Jul 25 06:05:30 PM PDT 24
Finished Jul 25 06:05:32 PM PDT 24
Peak memory 218308 kb
Host smart-06cc19ea-0104-436c-91fa-5bec2a701317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075113232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1075113232
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.780115172
Short name T206
Test name
Test status
Simulation time 23794224 ps
CPU time 1.18 seconds
Started Jul 25 06:04:01 PM PDT 24
Finished Jul 25 06:04:02 PM PDT 24
Peak memory 219628 kb
Host smart-521147ff-cf05-4397-842c-55ba92ba458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780115172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.780115172
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2396062834
Short name T676
Test name
Test status
Simulation time 31961011 ps
CPU time 0.94 seconds
Started Jul 25 06:04:08 PM PDT 24
Finished Jul 25 06:04:10 PM PDT 24
Peak memory 206644 kb
Host smart-64118332-ba72-42d8-95c7-6f0e7a54ce61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396062834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2396062834
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1354139846
Short name T177
Test name
Test status
Simulation time 15835760 ps
CPU time 0.84 seconds
Started Jul 25 06:04:19 PM PDT 24
Finished Jul 25 06:04:20 PM PDT 24
Peak memory 216004 kb
Host smart-7ed3361b-9f4f-4fc7-bf75-6c852426a695
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354139846 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1354139846
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1341830391
Short name T643
Test name
Test status
Simulation time 62663501 ps
CPU time 1.29 seconds
Started Jul 25 06:04:19 PM PDT 24
Finished Jul 25 06:04:21 PM PDT 24
Peak memory 216728 kb
Host smart-c2325587-f6c5-41bf-a385-9e0fe3bc5dab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341830391 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1341830391
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3801877681
Short name T8
Test name
Test status
Simulation time 48973469 ps
CPU time 0.85 seconds
Started Jul 25 06:04:04 PM PDT 24
Finished Jul 25 06:04:05 PM PDT 24
Peak memory 219328 kb
Host smart-24936e08-654c-4358-80d4-1d20d52cb674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801877681 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3801877681
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_intr.3806417619
Short name T804
Test name
Test status
Simulation time 20712563 ps
CPU time 1.03 seconds
Started Jul 25 06:04:04 PM PDT 24
Finished Jul 25 06:04:05 PM PDT 24
Peak memory 215756 kb
Host smart-a5fdf2c9-bc6a-4d16-9a40-23c619d6c1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806417619 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3806417619
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1657284263
Short name T808
Test name
Test status
Simulation time 137432003 ps
CPU time 0.94 seconds
Started Jul 25 06:04:08 PM PDT 24
Finished Jul 25 06:04:09 PM PDT 24
Peak memory 206984 kb
Host smart-a7ec473b-3631-4472-bfa5-347f050298de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657284263 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1657284263
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2747856663
Short name T335
Test name
Test status
Simulation time 17113823 ps
CPU time 0.98 seconds
Started Jul 25 06:03:56 PM PDT 24
Finished Jul 25 06:03:57 PM PDT 24
Peak memory 215160 kb
Host smart-8aab2dc2-e99e-40c2-bc55-bae59a3672ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747856663 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2747856663
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2268900490
Short name T900
Test name
Test status
Simulation time 518756033 ps
CPU time 2.68 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:13 PM PDT 24
Peak memory 217264 kb
Host smart-4cb8fb3a-a452-47aa-a4cc-1c2ba5851554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268900490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2268900490
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1497959528
Short name T561
Test name
Test status
Simulation time 540484233856 ps
CPU time 3392.22 seconds
Started Jul 25 06:04:04 PM PDT 24
Finished Jul 25 07:00:37 PM PDT 24
Peak memory 237748 kb
Host smart-db374aa4-0016-43ee-a756-662e3dfd10e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497959528 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1497959528
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2664297826
Short name T478
Test name
Test status
Simulation time 108868007 ps
CPU time 1.25 seconds
Started Jul 25 06:05:35 PM PDT 24
Finished Jul 25 06:05:36 PM PDT 24
Peak memory 215640 kb
Host smart-4c187752-9992-4884-928e-5334cdf1e634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664297826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2664297826
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.4172374656
Short name T114
Test name
Test status
Simulation time 30445588 ps
CPU time 1.01 seconds
Started Jul 25 06:05:33 PM PDT 24
Finished Jul 25 06:05:34 PM PDT 24
Peak memory 219640 kb
Host smart-b939163d-fdad-4b28-aaad-d5fdd073222b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172374656 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.4172374656
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.448412364
Short name T902
Test name
Test status
Simulation time 51996914 ps
CPU time 1.26 seconds
Started Jul 25 06:05:34 PM PDT 24
Finished Jul 25 06:05:35 PM PDT 24
Peak memory 218488 kb
Host smart-fc65a4b7-22f4-4d3b-95b1-8a92fcc9e525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448412364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.448412364
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1622940509
Short name T822
Test name
Test status
Simulation time 28758503 ps
CPU time 1.24 seconds
Started Jul 25 06:05:30 PM PDT 24
Finished Jul 25 06:05:32 PM PDT 24
Peak memory 218592 kb
Host smart-d424253a-28d3-49bb-ab6d-fbdc233b58fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622940509 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1622940509
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2998874838
Short name T439
Test name
Test status
Simulation time 28044179 ps
CPU time 0.86 seconds
Started Jul 25 06:05:30 PM PDT 24
Finished Jul 25 06:05:31 PM PDT 24
Peak memory 219364 kb
Host smart-08e6826b-a0bd-4368-9edd-c4782dc5bd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998874838 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2998874838
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.44503624
Short name T772
Test name
Test status
Simulation time 53193692 ps
CPU time 1.6 seconds
Started Jul 25 06:05:35 PM PDT 24
Finished Jul 25 06:05:37 PM PDT 24
Peak memory 219788 kb
Host smart-f40a0664-c62d-455d-bf4b-6ecda837013e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44503624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.44503624
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.4210473834
Short name T588
Test name
Test status
Simulation time 85014669 ps
CPU time 1.11 seconds
Started Jul 25 06:05:31 PM PDT 24
Finished Jul 25 06:05:32 PM PDT 24
Peak memory 220096 kb
Host smart-e62674c6-a688-4d87-9478-d0785bbb9790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210473834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.4210473834
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3555570838
Short name T9
Test name
Test status
Simulation time 40135406 ps
CPU time 1.14 seconds
Started Jul 25 06:05:36 PM PDT 24
Finished Jul 25 06:05:37 PM PDT 24
Peak memory 229572 kb
Host smart-35f5ae8f-40f0-4b18-a453-d236ef497f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555570838 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3555570838
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2729977884
Short name T829
Test name
Test status
Simulation time 31276670 ps
CPU time 1.25 seconds
Started Jul 25 06:05:32 PM PDT 24
Finished Jul 25 06:05:34 PM PDT 24
Peak memory 218604 kb
Host smart-afc35e55-3596-4549-8103-670d38b537da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729977884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2729977884
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.562041144
Short name T944
Test name
Test status
Simulation time 94601342 ps
CPU time 1.16 seconds
Started Jul 25 06:05:32 PM PDT 24
Finished Jul 25 06:05:33 PM PDT 24
Peak memory 220364 kb
Host smart-d753e171-1778-40a4-b532-f247003e1f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562041144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.562041144
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.3051417404
Short name T632
Test name
Test status
Simulation time 70609639 ps
CPU time 1.27 seconds
Started Jul 25 06:05:32 PM PDT 24
Finished Jul 25 06:05:34 PM PDT 24
Peak memory 225748 kb
Host smart-17cdc0e1-9846-4dc8-be52-d60ce215181a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051417404 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3051417404
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.738460786
Short name T395
Test name
Test status
Simulation time 150917432 ps
CPU time 2.77 seconds
Started Jul 25 06:05:35 PM PDT 24
Finished Jul 25 06:05:38 PM PDT 24
Peak memory 219956 kb
Host smart-2fd249b0-1cc5-4480-abe7-401b8f91ae4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738460786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.738460786
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.243540373
Short name T738
Test name
Test status
Simulation time 32240857 ps
CPU time 1.26 seconds
Started Jul 25 06:05:35 PM PDT 24
Finished Jul 25 06:05:36 PM PDT 24
Peak memory 215500 kb
Host smart-826e0921-53e5-43a4-9502-e2a9f62298a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243540373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.243540373
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.2080396038
Short name T147
Test name
Test status
Simulation time 50803067 ps
CPU time 1.01 seconds
Started Jul 25 06:05:35 PM PDT 24
Finished Jul 25 06:05:36 PM PDT 24
Peak memory 219800 kb
Host smart-383d6d39-433e-4660-8e08-30d97ba2e6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080396038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2080396038
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1623109386
Short name T710
Test name
Test status
Simulation time 47688155 ps
CPU time 1.12 seconds
Started Jul 25 06:05:30 PM PDT 24
Finished Jul 25 06:05:32 PM PDT 24
Peak memory 217236 kb
Host smart-d02a7f03-3538-43c3-a97a-fa1410441a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623109386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1623109386
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.2129019042
Short name T816
Test name
Test status
Simulation time 215780204 ps
CPU time 1.17 seconds
Started Jul 25 06:05:37 PM PDT 24
Finished Jul 25 06:05:38 PM PDT 24
Peak memory 219484 kb
Host smart-0462ff84-47c7-4a1e-9aea-317d5fd04c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129019042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2129019042
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3954602136
Short name T712
Test name
Test status
Simulation time 34551765 ps
CPU time 1.11 seconds
Started Jul 25 06:05:42 PM PDT 24
Finished Jul 25 06:05:44 PM PDT 24
Peak memory 223924 kb
Host smart-a7e2874d-3471-479f-8491-297352dae1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954602136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3954602136
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1330878003
Short name T854
Test name
Test status
Simulation time 91390095 ps
CPU time 1.64 seconds
Started Jul 25 06:05:36 PM PDT 24
Finished Jul 25 06:05:37 PM PDT 24
Peak memory 218588 kb
Host smart-996ac0ac-3660-4da2-acba-2fe9f0e99221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330878003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1330878003
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.4049182301
Short name T540
Test name
Test status
Simulation time 67391599 ps
CPU time 1.12 seconds
Started Jul 25 06:05:43 PM PDT 24
Finished Jul 25 06:05:45 PM PDT 24
Peak memory 219448 kb
Host smart-8d013847-0f86-4d72-9e7d-6896f70a9143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049182301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.4049182301
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.1850346540
Short name T652
Test name
Test status
Simulation time 20808513 ps
CPU time 1.08 seconds
Started Jul 25 06:05:37 PM PDT 24
Finished Jul 25 06:05:39 PM PDT 24
Peak memory 218568 kb
Host smart-19101573-da2e-4c61-b27d-fd100a6e0ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850346540 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1850346540
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1463101534
Short name T440
Test name
Test status
Simulation time 100225368 ps
CPU time 2.3 seconds
Started Jul 25 06:05:39 PM PDT 24
Finished Jul 25 06:05:41 PM PDT 24
Peak memory 217420 kb
Host smart-915ea6df-50bd-443c-a3fb-ae8c71321c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463101534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1463101534
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.227084633
Short name T570
Test name
Test status
Simulation time 78382955 ps
CPU time 1.18 seconds
Started Jul 25 06:05:39 PM PDT 24
Finished Jul 25 06:05:40 PM PDT 24
Peak memory 221552 kb
Host smart-a0c9f4e0-f705-47b5-b184-d8bdcb921250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227084633 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.227084633
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.1252803625
Short name T127
Test name
Test status
Simulation time 32876122 ps
CPU time 0.87 seconds
Started Jul 25 06:05:44 PM PDT 24
Finished Jul 25 06:05:45 PM PDT 24
Peak memory 218452 kb
Host smart-048e9379-dea0-4901-af48-623bc7d3918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252803625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1252803625
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.4189650167
Short name T653
Test name
Test status
Simulation time 62264797 ps
CPU time 1.37 seconds
Started Jul 25 06:05:43 PM PDT 24
Finished Jul 25 06:05:44 PM PDT 24
Peak memory 217268 kb
Host smart-1dccc0aa-c152-46b6-a09c-a3271e1c4a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189650167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.4189650167
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.291205607
Short name T663
Test name
Test status
Simulation time 63907266 ps
CPU time 1.07 seconds
Started Jul 25 06:05:39 PM PDT 24
Finished Jul 25 06:05:40 PM PDT 24
Peak memory 219736 kb
Host smart-b116c9ec-caf5-4fa3-9c3d-df458ea5c609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291205607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.291205607
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.1314888210
Short name T186
Test name
Test status
Simulation time 24557937 ps
CPU time 1.01 seconds
Started Jul 25 06:05:39 PM PDT 24
Finished Jul 25 06:05:40 PM PDT 24
Peak memory 223732 kb
Host smart-c4693af2-242e-46e4-9bb9-31dbedc1c884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314888210 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1314888210
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.45640900
Short name T366
Test name
Test status
Simulation time 69133718 ps
CPU time 1.43 seconds
Started Jul 25 06:05:39 PM PDT 24
Finished Jul 25 06:05:41 PM PDT 24
Peak memory 218304 kb
Host smart-c34d75cf-5e37-4700-8230-0486e819d697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45640900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.45640900
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2217444127
Short name T463
Test name
Test status
Simulation time 354973347 ps
CPU time 1.31 seconds
Started Jul 25 06:05:37 PM PDT 24
Finished Jul 25 06:05:38 PM PDT 24
Peak memory 219032 kb
Host smart-038da232-97aa-4498-93ec-1644d32ab12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217444127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2217444127
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.3631210566
Short name T182
Test name
Test status
Simulation time 23726257 ps
CPU time 0.95 seconds
Started Jul 25 06:05:38 PM PDT 24
Finished Jul 25 06:05:39 PM PDT 24
Peak memory 218608 kb
Host smart-d7a5680c-707c-43c8-bda6-0e08003befdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631210566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3631210566
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.409673570
Short name T434
Test name
Test status
Simulation time 76120418 ps
CPU time 1.08 seconds
Started Jul 25 06:05:42 PM PDT 24
Finished Jul 25 06:05:43 PM PDT 24
Peak memory 217524 kb
Host smart-8d293a65-ba13-45a6-9f7f-5195dd2330d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409673570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.409673570
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1917536870
Short name T70
Test name
Test status
Simulation time 54051655 ps
CPU time 1.34 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:11 PM PDT 24
Peak memory 215580 kb
Host smart-baee86b5-dff1-4e08-bb7a-6686b8606255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917536870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1917536870
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1135628338
Short name T567
Test name
Test status
Simulation time 14736537 ps
CPU time 0.93 seconds
Started Jul 25 06:04:19 PM PDT 24
Finished Jul 25 06:04:20 PM PDT 24
Peak memory 214716 kb
Host smart-4e0416bc-f33b-42ac-85c4-095c228674b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135628338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1135628338
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3047062654
Short name T356
Test name
Test status
Simulation time 22894150 ps
CPU time 0.88 seconds
Started Jul 25 06:04:04 PM PDT 24
Finished Jul 25 06:04:05 PM PDT 24
Peak memory 215816 kb
Host smart-5b0d70d1-0e7b-4fb5-91f2-b347600f0667
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047062654 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3047062654
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2943092182
Short name T957
Test name
Test status
Simulation time 38009585 ps
CPU time 0.97 seconds
Started Jul 25 06:04:01 PM PDT 24
Finished Jul 25 06:04:02 PM PDT 24
Peak memory 218344 kb
Host smart-4231b01b-58e0-4960-80e0-536cb63a578a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943092182 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2943092182
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2444935044
Short name T122
Test name
Test status
Simulation time 32615141 ps
CPU time 1.27 seconds
Started Jul 25 06:04:01 PM PDT 24
Finished Jul 25 06:04:03 PM PDT 24
Peak memory 225700 kb
Host smart-9c2b1546-912c-4514-b152-8cee6c263804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444935044 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2444935044
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1864379536
Short name T754
Test name
Test status
Simulation time 77302182 ps
CPU time 1.58 seconds
Started Jul 25 06:04:05 PM PDT 24
Finished Jul 25 06:04:07 PM PDT 24
Peak memory 218596 kb
Host smart-2d057781-348a-46ee-84a1-392065d9c3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864379536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1864379536
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1023178127
Short name T464
Test name
Test status
Simulation time 23102979 ps
CPU time 1.2 seconds
Started Jul 25 06:04:04 PM PDT 24
Finished Jul 25 06:04:06 PM PDT 24
Peak memory 223944 kb
Host smart-588bc4ff-cdb4-495e-9bda-e2d574cb2464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023178127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1023178127
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.4089205059
Short name T656
Test name
Test status
Simulation time 14592289 ps
CPU time 0.99 seconds
Started Jul 25 06:04:03 PM PDT 24
Finished Jul 25 06:04:04 PM PDT 24
Peak memory 206980 kb
Host smart-3edec19a-4e74-4c04-b98b-88fc698d8757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089205059 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.4089205059
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.270876855
Short name T23
Test name
Test status
Simulation time 27099439 ps
CPU time 1.06 seconds
Started Jul 25 06:04:10 PM PDT 24
Finished Jul 25 06:04:12 PM PDT 24
Peak memory 215212 kb
Host smart-f2b3527d-c481-4178-922d-0564d0b23ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270876855 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.270876855
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1605153562
Short name T495
Test name
Test status
Simulation time 51128178 ps
CPU time 1.2 seconds
Started Jul 25 06:04:05 PM PDT 24
Finished Jul 25 06:04:07 PM PDT 24
Peak memory 217236 kb
Host smart-ca096935-9cc2-4e73-be3f-de28e7d0802b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605153562 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1605153562
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3723463542
Short name T456
Test name
Test status
Simulation time 42829108318 ps
CPU time 527.28 seconds
Started Jul 25 06:04:04 PM PDT 24
Finished Jul 25 06:12:51 PM PDT 24
Peak memory 218372 kb
Host smart-aac374a1-df46-489f-965b-23e4ce08ee4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723463542 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3723463542
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.3107061523
Short name T76
Test name
Test status
Simulation time 40301978 ps
CPU time 1.14 seconds
Started Jul 25 06:05:43 PM PDT 24
Finished Jul 25 06:05:45 PM PDT 24
Peak memory 219548 kb
Host smart-e5333a68-f4d3-4c81-b990-a5a96af48d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107061523 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.3107061523
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.1182506597
Short name T482
Test name
Test status
Simulation time 52553706 ps
CPU time 0.99 seconds
Started Jul 25 06:05:41 PM PDT 24
Finished Jul 25 06:05:42 PM PDT 24
Peak memory 223728 kb
Host smart-17e62d47-fde0-440d-994f-ff9c8734eb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182506597 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1182506597
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1230081536
Short name T310
Test name
Test status
Simulation time 37897060 ps
CPU time 1.43 seconds
Started Jul 25 06:05:37 PM PDT 24
Finished Jul 25 06:05:39 PM PDT 24
Peak memory 218548 kb
Host smart-fec1efea-7039-41e7-93be-4abed4b9c193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230081536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1230081536
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.739367620
Short name T145
Test name
Test status
Simulation time 161331965 ps
CPU time 1.15 seconds
Started Jul 25 06:05:41 PM PDT 24
Finished Jul 25 06:05:43 PM PDT 24
Peak memory 218344 kb
Host smart-2e5a5b38-621c-4238-b225-dd700df7fd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739367620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.739367620
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.586397972
Short name T408
Test name
Test status
Simulation time 43572936 ps
CPU time 1.07 seconds
Started Jul 25 06:05:39 PM PDT 24
Finished Jul 25 06:05:40 PM PDT 24
Peak memory 219536 kb
Host smart-d52c9503-9bf4-4829-86d9-fc6bcceeefcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586397972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.586397972
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1046939223
Short name T297
Test name
Test status
Simulation time 39617816 ps
CPU time 1.13 seconds
Started Jul 25 06:05:40 PM PDT 24
Finished Jul 25 06:05:41 PM PDT 24
Peak memory 218792 kb
Host smart-bd148db0-f3bf-43fb-8b8c-394960565825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046939223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1046939223
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.1135435376
Short name T152
Test name
Test status
Simulation time 44208921 ps
CPU time 1.26 seconds
Started Jul 25 06:05:44 PM PDT 24
Finished Jul 25 06:05:46 PM PDT 24
Peak memory 219036 kb
Host smart-f1d7399e-e937-4879-9531-bfe90bbb3f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135435376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.1135435376
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3389158921
Short name T61
Test name
Test status
Simulation time 28362545 ps
CPU time 1.2 seconds
Started Jul 25 06:05:39 PM PDT 24
Finished Jul 25 06:05:40 PM PDT 24
Peak memory 219460 kb
Host smart-866f065f-617f-421e-b12b-6e30df04a567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389158921 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3389158921
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.4031998277
Short name T362
Test name
Test status
Simulation time 94410034 ps
CPU time 1.64 seconds
Started Jul 25 06:05:41 PM PDT 24
Finished Jul 25 06:05:43 PM PDT 24
Peak memory 218740 kb
Host smart-21890fd5-b69a-4179-b1bd-265a4d8eb0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031998277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.4031998277
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2217615787
Short name T282
Test name
Test status
Simulation time 77066388 ps
CPU time 1.17 seconds
Started Jul 25 06:05:39 PM PDT 24
Finished Jul 25 06:05:40 PM PDT 24
Peak memory 218580 kb
Host smart-7fc95ca5-301a-45bb-93de-1e4635110712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217615787 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2217615787
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.799876942
Short name T645
Test name
Test status
Simulation time 31561113 ps
CPU time 1.12 seconds
Started Jul 25 06:05:40 PM PDT 24
Finished Jul 25 06:05:41 PM PDT 24
Peak memory 223880 kb
Host smart-f159f4fa-baad-4a96-9fdd-005f9a1f94f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799876942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.799876942
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.4223980014
Short name T722
Test name
Test status
Simulation time 82919941 ps
CPU time 1.73 seconds
Started Jul 25 06:05:36 PM PDT 24
Finished Jul 25 06:05:38 PM PDT 24
Peak memory 218580 kb
Host smart-d60b3acd-796d-4e28-a492-04688b7df127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223980014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4223980014
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.664602602
Short name T797
Test name
Test status
Simulation time 77179054 ps
CPU time 1.14 seconds
Started Jul 25 06:05:40 PM PDT 24
Finished Jul 25 06:05:41 PM PDT 24
Peak memory 221436 kb
Host smart-c1df0b28-7924-4126-85cf-71bd5bac62e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664602602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.664602602
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1776726880
Short name T821
Test name
Test status
Simulation time 20415742 ps
CPU time 1.22 seconds
Started Jul 25 06:05:44 PM PDT 24
Finished Jul 25 06:05:46 PM PDT 24
Peak memory 229484 kb
Host smart-3f559e9d-e746-4c25-8084-ff0ac9c0f74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776726880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1776726880
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.678816406
Short name T257
Test name
Test status
Simulation time 43533418 ps
CPU time 1.34 seconds
Started Jul 25 06:05:43 PM PDT 24
Finished Jul 25 06:05:45 PM PDT 24
Peak memory 218556 kb
Host smart-5434e008-f542-4aad-ac9d-f12d1ee8aea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678816406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.678816406
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.624288003
Short name T920
Test name
Test status
Simulation time 42137349 ps
CPU time 1.2 seconds
Started Jul 25 06:05:40 PM PDT 24
Finished Jul 25 06:05:41 PM PDT 24
Peak memory 218744 kb
Host smart-e6863ef5-e7ca-43f6-ac14-b66d165e03d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624288003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.624288003
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.2230015458
Short name T658
Test name
Test status
Simulation time 21523393 ps
CPU time 1.05 seconds
Started Jul 25 06:05:38 PM PDT 24
Finished Jul 25 06:05:39 PM PDT 24
Peak memory 218560 kb
Host smart-b9cb4792-c884-47c0-9311-26b1297bec39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230015458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2230015458
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3516793374
Short name T437
Test name
Test status
Simulation time 37242162 ps
CPU time 1.05 seconds
Started Jul 25 06:05:44 PM PDT 24
Finished Jul 25 06:05:45 PM PDT 24
Peak memory 215268 kb
Host smart-78b3fe45-2ab9-475e-a189-d070ebbc942c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516793374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3516793374
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.302002819
Short name T791
Test name
Test status
Simulation time 27265720 ps
CPU time 1.23 seconds
Started Jul 25 06:05:43 PM PDT 24
Finished Jul 25 06:05:44 PM PDT 24
Peak memory 220648 kb
Host smart-2adaece6-201a-4c08-9fe9-f99ed1ebf080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302002819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.302002819
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3976479839
Short name T698
Test name
Test status
Simulation time 23844372 ps
CPU time 0.97 seconds
Started Jul 25 06:05:45 PM PDT 24
Finished Jul 25 06:05:46 PM PDT 24
Peak memory 218448 kb
Host smart-bdc57ff8-c143-4844-aa8c-1be68efbd386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976479839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3976479839
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.656118727
Short name T936
Test name
Test status
Simulation time 68308192 ps
CPU time 2.12 seconds
Started Jul 25 06:05:41 PM PDT 24
Finished Jul 25 06:05:43 PM PDT 24
Peak memory 215196 kb
Host smart-19eb8af9-eb15-46b2-927a-b60492f4b060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656118727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.656118727
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2775987066
Short name T817
Test name
Test status
Simulation time 29924433 ps
CPU time 1.14 seconds
Started Jul 25 06:05:44 PM PDT 24
Finished Jul 25 06:05:45 PM PDT 24
Peak memory 219596 kb
Host smart-bab12b58-ae10-4e73-b427-893ffbdd2bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775987066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2775987066
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.3630275196
Short name T914
Test name
Test status
Simulation time 19009377 ps
CPU time 1.08 seconds
Started Jul 25 06:05:45 PM PDT 24
Finished Jul 25 06:05:47 PM PDT 24
Peak memory 218564 kb
Host smart-4d6ca806-f2c8-4e19-9155-54a60335e24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630275196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3630275196
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.4180654051
Short name T480
Test name
Test status
Simulation time 40760724 ps
CPU time 1.63 seconds
Started Jul 25 06:05:45 PM PDT 24
Finished Jul 25 06:05:46 PM PDT 24
Peak memory 218520 kb
Host smart-cbf27163-3e63-4443-ae2f-c1effe19d004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180654051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.4180654051
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.3636300998
Short name T575
Test name
Test status
Simulation time 29544417 ps
CPU time 1.26 seconds
Started Jul 25 06:05:54 PM PDT 24
Finished Jul 25 06:05:56 PM PDT 24
Peak memory 219664 kb
Host smart-0e83ea72-9263-4f84-b5b5-7ef10513a70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636300998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.3636300998
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.2094065411
Short name T142
Test name
Test status
Simulation time 56299384 ps
CPU time 1.01 seconds
Started Jul 25 06:05:48 PM PDT 24
Finished Jul 25 06:05:50 PM PDT 24
Peak memory 219752 kb
Host smart-17db1455-2a8e-4790-b0aa-7ab9d0aaccdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094065411 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2094065411
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2932755991
Short name T584
Test name
Test status
Simulation time 38798013 ps
CPU time 1.15 seconds
Started Jul 25 06:05:54 PM PDT 24
Finished Jul 25 06:05:55 PM PDT 24
Peak memory 218576 kb
Host smart-2d046994-3ecc-4d36-9dce-b34b57dbcd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932755991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2932755991
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2743349907
Short name T191
Test name
Test status
Simulation time 38822534 ps
CPU time 1.17 seconds
Started Jul 25 06:05:44 PM PDT 24
Finished Jul 25 06:05:46 PM PDT 24
Peak memory 218400 kb
Host smart-dfbdd444-9265-4bda-9292-19d2c7c2f118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743349907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2743349907
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2430331792
Short name T172
Test name
Test status
Simulation time 32288944 ps
CPU time 1 seconds
Started Jul 25 06:05:45 PM PDT 24
Finished Jul 25 06:05:46 PM PDT 24
Peak memory 223740 kb
Host smart-7ba7a9f8-e53e-4c37-85d4-31f8b18a5cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430331792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2430331792
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.898161480
Short name T378
Test name
Test status
Simulation time 150042345 ps
CPU time 3.31 seconds
Started Jul 25 06:05:45 PM PDT 24
Finished Jul 25 06:05:48 PM PDT 24
Peak memory 220268 kb
Host smart-937ef156-203b-4eff-a9e5-93285c43976a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898161480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.898161480
Directory /workspace/99.edn_genbits/latest
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