Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.71 98.25 93.31 90.85 89.53 95.50 96.83 91.70


Total test records in report: 1125
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T1018 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.265702946 Jul 26 05:41:17 PM PDT 24 Jul 26 05:41:19 PM PDT 24 159606241 ps
T1019 /workspace/coverage/cover_reg_top/30.edn_intr_test.1021421429 Jul 26 05:41:52 PM PDT 24 Jul 26 05:41:53 PM PDT 24 46103893 ps
T1020 /workspace/coverage/cover_reg_top/48.edn_intr_test.2398965579 Jul 26 05:41:44 PM PDT 24 Jul 26 05:41:46 PM PDT 24 15031998 ps
T1021 /workspace/coverage/cover_reg_top/15.edn_csr_rw.279607963 Jul 26 05:41:26 PM PDT 24 Jul 26 05:41:27 PM PDT 24 16535006 ps
T1022 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1041219550 Jul 26 05:41:31 PM PDT 24 Jul 26 05:41:32 PM PDT 24 61487047 ps
T1023 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1209411340 Jul 26 05:41:30 PM PDT 24 Jul 26 05:41:32 PM PDT 24 52398346 ps
T1024 /workspace/coverage/cover_reg_top/23.edn_intr_test.4046063160 Jul 26 05:41:39 PM PDT 24 Jul 26 05:41:40 PM PDT 24 12716839 ps
T1025 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2616909116 Jul 26 05:41:22 PM PDT 24 Jul 26 05:41:23 PM PDT 24 183740232 ps
T1026 /workspace/coverage/cover_reg_top/17.edn_csr_rw.681166354 Jul 26 05:41:28 PM PDT 24 Jul 26 05:41:30 PM PDT 24 14177026 ps
T1027 /workspace/coverage/cover_reg_top/9.edn_intr_test.3923908917 Jul 26 05:41:20 PM PDT 24 Jul 26 05:41:21 PM PDT 24 44112235 ps
T1028 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1051032275 Jul 26 05:41:17 PM PDT 24 Jul 26 05:41:22 PM PDT 24 675687754 ps
T1029 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1641088855 Jul 26 05:41:40 PM PDT 24 Jul 26 05:41:41 PM PDT 24 26515613 ps
T1030 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2716050864 Jul 26 05:41:22 PM PDT 24 Jul 26 05:41:26 PM PDT 24 160497673 ps
T1031 /workspace/coverage/cover_reg_top/11.edn_intr_test.1640730905 Jul 26 05:41:30 PM PDT 24 Jul 26 05:41:31 PM PDT 24 12963710 ps
T1032 /workspace/coverage/cover_reg_top/37.edn_intr_test.958590909 Jul 26 05:41:39 PM PDT 24 Jul 26 05:41:40 PM PDT 24 33241407 ps
T261 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.139575683 Jul 26 05:41:20 PM PDT 24 Jul 26 05:41:21 PM PDT 24 34138817 ps
T1033 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2899738011 Jul 26 05:41:30 PM PDT 24 Jul 26 05:41:34 PM PDT 24 422975799 ps
T1034 /workspace/coverage/cover_reg_top/2.edn_tl_errors.4203494345 Jul 26 05:41:24 PM PDT 24 Jul 26 05:41:28 PM PDT 24 466086262 ps
T1035 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1781003419 Jul 26 05:41:20 PM PDT 24 Jul 26 05:41:26 PM PDT 24 186557301 ps
T1036 /workspace/coverage/cover_reg_top/27.edn_intr_test.3374499425 Jul 26 05:41:38 PM PDT 24 Jul 26 05:41:39 PM PDT 24 13769694 ps
T262 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1978424041 Jul 26 05:41:28 PM PDT 24 Jul 26 05:41:29 PM PDT 24 48455004 ps
T1037 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.337662851 Jul 26 05:41:33 PM PDT 24 Jul 26 05:41:34 PM PDT 24 25698093 ps
T1038 /workspace/coverage/cover_reg_top/3.edn_tl_errors.906044374 Jul 26 05:41:21 PM PDT 24 Jul 26 05:41:24 PM PDT 24 77579208 ps
T295 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.622161898 Jul 26 05:41:20 PM PDT 24 Jul 26 05:41:22 PM PDT 24 64157259 ps
T1039 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2387387288 Jul 26 05:41:22 PM PDT 24 Jul 26 05:41:25 PM PDT 24 153429239 ps
T1040 /workspace/coverage/cover_reg_top/45.edn_intr_test.2002434456 Jul 26 05:41:56 PM PDT 24 Jul 26 05:41:57 PM PDT 24 24674226 ps
T1041 /workspace/coverage/cover_reg_top/12.edn_intr_test.1435402791 Jul 26 05:41:28 PM PDT 24 Jul 26 05:41:29 PM PDT 24 27753680 ps
T1042 /workspace/coverage/cover_reg_top/46.edn_intr_test.4138900593 Jul 26 05:41:41 PM PDT 24 Jul 26 05:41:42 PM PDT 24 12106548 ps
T1043 /workspace/coverage/cover_reg_top/44.edn_intr_test.217278608 Jul 26 05:41:41 PM PDT 24 Jul 26 05:41:42 PM PDT 24 29345529 ps
T1044 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1516781770 Jul 26 05:41:23 PM PDT 24 Jul 26 05:41:27 PM PDT 24 87412074 ps
T1045 /workspace/coverage/cover_reg_top/35.edn_intr_test.2527951761 Jul 26 05:41:41 PM PDT 24 Jul 26 05:41:42 PM PDT 24 41146270 ps
T1046 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1585154735 Jul 26 05:41:22 PM PDT 24 Jul 26 05:41:23 PM PDT 24 15970979 ps
T1047 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1117218290 Jul 26 05:41:24 PM PDT 24 Jul 26 05:41:25 PM PDT 24 73821700 ps
T1048 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2335450926 Jul 26 05:41:32 PM PDT 24 Jul 26 05:41:33 PM PDT 24 70110921 ps
T296 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3397761492 Jul 26 05:41:28 PM PDT 24 Jul 26 05:41:29 PM PDT 24 129887100 ps
T1049 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2630009692 Jul 26 05:41:17 PM PDT 24 Jul 26 05:41:18 PM PDT 24 20343221 ps
T1050 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1274278224 Jul 26 05:41:30 PM PDT 24 Jul 26 05:41:31 PM PDT 24 41960375 ps
T299 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.303372918 Jul 26 05:41:26 PM PDT 24 Jul 26 05:41:27 PM PDT 24 121285450 ps
T1051 /workspace/coverage/cover_reg_top/34.edn_intr_test.1921537028 Jul 26 05:41:37 PM PDT 24 Jul 26 05:41:38 PM PDT 24 11835802 ps
T1052 /workspace/coverage/cover_reg_top/13.edn_intr_test.3928201548 Jul 26 05:41:28 PM PDT 24 Jul 26 05:41:29 PM PDT 24 31618219 ps
T1053 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1282533518 Jul 26 05:41:30 PM PDT 24 Jul 26 05:41:34 PM PDT 24 126043731 ps
T1054 /workspace/coverage/cover_reg_top/7.edn_intr_test.511593914 Jul 26 05:41:18 PM PDT 24 Jul 26 05:41:19 PM PDT 24 121365830 ps
T1055 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.13762766 Jul 26 05:41:26 PM PDT 24 Jul 26 05:41:28 PM PDT 24 128498235 ps
T1056 /workspace/coverage/cover_reg_top/19.edn_intr_test.2088839560 Jul 26 05:41:40 PM PDT 24 Jul 26 05:41:41 PM PDT 24 17488480 ps
T1057 /workspace/coverage/cover_reg_top/29.edn_intr_test.3038307358 Jul 26 05:41:37 PM PDT 24 Jul 26 05:41:38 PM PDT 24 18981155 ps
T1058 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3737688236 Jul 26 05:41:24 PM PDT 24 Jul 26 05:41:32 PM PDT 24 169888121 ps
T1059 /workspace/coverage/cover_reg_top/1.edn_intr_test.2858772564 Jul 26 05:41:22 PM PDT 24 Jul 26 05:41:23 PM PDT 24 14607131 ps
T1060 /workspace/coverage/cover_reg_top/43.edn_intr_test.2063625045 Jul 26 05:41:39 PM PDT 24 Jul 26 05:41:40 PM PDT 24 11606266 ps
T1061 /workspace/coverage/cover_reg_top/47.edn_intr_test.653477541 Jul 26 05:41:39 PM PDT 24 Jul 26 05:41:40 PM PDT 24 15149241 ps
T1062 /workspace/coverage/cover_reg_top/12.edn_csr_rw.255259681 Jul 26 05:41:28 PM PDT 24 Jul 26 05:41:29 PM PDT 24 22512812 ps
T1063 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.4148249391 Jul 26 05:41:21 PM PDT 24 Jul 26 05:41:22 PM PDT 24 140741794 ps
T1064 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1401717981 Jul 26 05:41:30 PM PDT 24 Jul 26 05:41:35 PM PDT 24 246542383 ps
T1065 /workspace/coverage/cover_reg_top/4.edn_intr_test.1475762558 Jul 26 05:41:16 PM PDT 24 Jul 26 05:41:17 PM PDT 24 72763762 ps
T1066 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2338765249 Jul 26 05:41:16 PM PDT 24 Jul 26 05:41:18 PM PDT 24 56814044 ps
T297 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1559325694 Jul 26 05:41:42 PM PDT 24 Jul 26 05:41:44 PM PDT 24 153791664 ps
T1067 /workspace/coverage/cover_reg_top/0.edn_tl_errors.486798228 Jul 26 05:41:18 PM PDT 24 Jul 26 05:41:21 PM PDT 24 193166056 ps
T1068 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.728010766 Jul 26 05:41:20 PM PDT 24 Jul 26 05:41:21 PM PDT 24 24626137 ps
T1069 /workspace/coverage/cover_reg_top/19.edn_csr_rw.4193947494 Jul 26 05:41:40 PM PDT 24 Jul 26 05:41:41 PM PDT 24 13728082 ps
T1070 /workspace/coverage/cover_reg_top/15.edn_intr_test.3416072794 Jul 26 05:41:27 PM PDT 24 Jul 26 05:41:28 PM PDT 24 14740252 ps
T1071 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3114763731 Jul 26 05:41:27 PM PDT 24 Jul 26 05:41:29 PM PDT 24 48781558 ps
T300 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3256416745 Jul 26 05:41:29 PM PDT 24 Jul 26 05:41:31 PM PDT 24 842661479 ps
T263 /workspace/coverage/cover_reg_top/11.edn_csr_rw.53935169 Jul 26 05:41:28 PM PDT 24 Jul 26 05:41:29 PM PDT 24 22038296 ps
T1072 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1518103869 Jul 26 05:41:27 PM PDT 24 Jul 26 05:41:30 PM PDT 24 193519751 ps
T1073 /workspace/coverage/cover_reg_top/32.edn_intr_test.3199053595 Jul 26 05:41:36 PM PDT 24 Jul 26 05:41:37 PM PDT 24 35852725 ps
T264 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1437803021 Jul 26 05:41:18 PM PDT 24 Jul 26 05:41:19 PM PDT 24 25217339 ps
T1074 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1667804511 Jul 26 05:41:28 PM PDT 24 Jul 26 05:41:29 PM PDT 24 43546891 ps
T1075 /workspace/coverage/cover_reg_top/16.edn_intr_test.3933650376 Jul 26 05:41:30 PM PDT 24 Jul 26 05:41:31 PM PDT 24 14211947 ps
T1076 /workspace/coverage/cover_reg_top/2.edn_intr_test.1338586037 Jul 26 05:41:20 PM PDT 24 Jul 26 05:41:21 PM PDT 24 22018842 ps
T1077 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2083617667 Jul 26 05:41:28 PM PDT 24 Jul 26 05:41:29 PM PDT 24 25267401 ps
T1078 /workspace/coverage/cover_reg_top/17.edn_intr_test.721570517 Jul 26 05:41:28 PM PDT 24 Jul 26 05:41:29 PM PDT 24 34271042 ps
T1079 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.897966058 Jul 26 05:41:28 PM PDT 24 Jul 26 05:41:30 PM PDT 24 122054243 ps
T1080 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.838531051 Jul 26 05:41:16 PM PDT 24 Jul 26 05:41:17 PM PDT 24 54668724 ps
T265 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4140524492 Jul 26 05:41:17 PM PDT 24 Jul 26 05:41:18 PM PDT 24 21854041 ps
T1081 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2800211604 Jul 26 05:41:30 PM PDT 24 Jul 26 05:41:32 PM PDT 24 104648974 ps
T1082 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1393512171 Jul 26 05:41:21 PM PDT 24 Jul 26 05:41:23 PM PDT 24 201275141 ps
T1083 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1059277874 Jul 26 05:41:20 PM PDT 24 Jul 26 05:41:22 PM PDT 24 44286570 ps
T1084 /workspace/coverage/cover_reg_top/9.edn_tl_errors.4038232887 Jul 26 05:41:28 PM PDT 24 Jul 26 05:41:30 PM PDT 24 356243313 ps
T269 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3922686278 Jul 26 05:41:23 PM PDT 24 Jul 26 05:41:26 PM PDT 24 193037088 ps
T1085 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.401797919 Jul 26 05:41:22 PM PDT 24 Jul 26 05:41:23 PM PDT 24 259762098 ps
T266 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2498996437 Jul 26 05:41:18 PM PDT 24 Jul 26 05:41:19 PM PDT 24 19832488 ps
T1086 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1183027885 Jul 26 05:41:37 PM PDT 24 Jul 26 05:41:38 PM PDT 24 120244320 ps
T1087 /workspace/coverage/cover_reg_top/42.edn_intr_test.3201907450 Jul 26 05:41:40 PM PDT 24 Jul 26 05:41:41 PM PDT 24 19106379 ps
T1088 /workspace/coverage/cover_reg_top/22.edn_intr_test.3325346857 Jul 26 05:41:36 PM PDT 24 Jul 26 05:41:37 PM PDT 24 13188520 ps
T1089 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1527359796 Jul 26 05:41:40 PM PDT 24 Jul 26 05:41:41 PM PDT 24 58349349 ps
T1090 /workspace/coverage/cover_reg_top/16.edn_csr_rw.150559145 Jul 26 05:41:29 PM PDT 24 Jul 26 05:41:30 PM PDT 24 14378054 ps
T267 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2950489551 Jul 26 05:41:21 PM PDT 24 Jul 26 05:41:22 PM PDT 24 22063050 ps
T1091 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.714786429 Jul 26 05:41:19 PM PDT 24 Jul 26 05:41:21 PM PDT 24 24441873 ps
T1092 /workspace/coverage/cover_reg_top/13.edn_tl_errors.4291702238 Jul 26 05:41:31 PM PDT 24 Jul 26 05:41:34 PM PDT 24 79441524 ps
T1093 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1596131828 Jul 26 05:41:24 PM PDT 24 Jul 26 05:41:26 PM PDT 24 49871326 ps
T1094 /workspace/coverage/cover_reg_top/36.edn_intr_test.3040020239 Jul 26 05:41:39 PM PDT 24 Jul 26 05:41:40 PM PDT 24 46842715 ps
T268 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1634143751 Jul 26 05:41:16 PM PDT 24 Jul 26 05:41:17 PM PDT 24 13502373 ps
T1095 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1716929341 Jul 26 05:41:24 PM PDT 24 Jul 26 05:41:25 PM PDT 24 66788059 ps
T301 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.4281258004 Jul 26 05:41:30 PM PDT 24 Jul 26 05:41:33 PM PDT 24 177017315 ps
T270 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2523660279 Jul 26 05:41:21 PM PDT 24 Jul 26 05:41:22 PM PDT 24 26217703 ps
T1096 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2907158582 Jul 26 05:41:23 PM PDT 24 Jul 26 05:41:24 PM PDT 24 13960522 ps
T1097 /workspace/coverage/cover_reg_top/10.edn_intr_test.336580549 Jul 26 05:41:22 PM PDT 24 Jul 26 05:41:23 PM PDT 24 46171404 ps
T1098 /workspace/coverage/cover_reg_top/21.edn_intr_test.879798402 Jul 26 05:41:44 PM PDT 24 Jul 26 05:41:45 PM PDT 24 19810286 ps
T1099 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2289219203 Jul 26 05:41:29 PM PDT 24 Jul 26 05:41:31 PM PDT 24 107222251 ps
T1100 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3271387025 Jul 26 05:41:11 PM PDT 24 Jul 26 05:41:13 PM PDT 24 333713139 ps
T1101 /workspace/coverage/cover_reg_top/24.edn_intr_test.3366975450 Jul 26 05:41:53 PM PDT 24 Jul 26 05:41:54 PM PDT 24 20495860 ps
T1102 /workspace/coverage/cover_reg_top/33.edn_intr_test.1744877349 Jul 26 05:41:40 PM PDT 24 Jul 26 05:41:41 PM PDT 24 45226301 ps
T1103 /workspace/coverage/cover_reg_top/26.edn_intr_test.3483571796 Jul 26 05:41:46 PM PDT 24 Jul 26 05:41:47 PM PDT 24 28507675 ps
T1104 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2073404342 Jul 26 05:41:26 PM PDT 24 Jul 26 05:41:30 PM PDT 24 159392375 ps
T1105 /workspace/coverage/cover_reg_top/41.edn_intr_test.94912736 Jul 26 05:41:38 PM PDT 24 Jul 26 05:41:39 PM PDT 24 18541482 ps
T1106 /workspace/coverage/cover_reg_top/5.edn_intr_test.1764731985 Jul 26 05:41:21 PM PDT 24 Jul 26 05:41:22 PM PDT 24 65464827 ps
T1107 /workspace/coverage/cover_reg_top/11.edn_tl_errors.344206045 Jul 26 05:41:31 PM PDT 24 Jul 26 05:41:33 PM PDT 24 294031982 ps
T1108 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3890488624 Jul 26 05:41:16 PM PDT 24 Jul 26 05:41:17 PM PDT 24 45838796 ps
T1109 /workspace/coverage/cover_reg_top/6.edn_intr_test.3749411253 Jul 26 05:41:22 PM PDT 24 Jul 26 05:41:23 PM PDT 24 55323215 ps
T1110 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1892069885 Jul 26 05:41:44 PM PDT 24 Jul 26 05:41:45 PM PDT 24 23173985 ps
T1111 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4171656471 Jul 26 05:41:17 PM PDT 24 Jul 26 05:41:18 PM PDT 24 139692843 ps
T1112 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3917371761 Jul 26 05:41:30 PM PDT 24 Jul 26 05:41:34 PM PDT 24 269907383 ps
T1113 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3173121493 Jul 26 05:41:29 PM PDT 24 Jul 26 05:41:31 PM PDT 24 75400154 ps
T1114 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1344207327 Jul 26 05:41:26 PM PDT 24 Jul 26 05:41:27 PM PDT 24 95579255 ps
T1115 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.51895958 Jul 26 05:41:28 PM PDT 24 Jul 26 05:41:29 PM PDT 24 85952070 ps
T1116 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.869892341 Jul 26 05:41:20 PM PDT 24 Jul 26 05:41:22 PM PDT 24 320206272 ps
T1117 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3676462371 Jul 26 05:41:28 PM PDT 24 Jul 26 05:41:30 PM PDT 24 23785289 ps
T271 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2743417746 Jul 26 05:41:26 PM PDT 24 Jul 26 05:41:27 PM PDT 24 12158235 ps
T1118 /workspace/coverage/cover_reg_top/38.edn_intr_test.171188412 Jul 26 05:41:44 PM PDT 24 Jul 26 05:41:46 PM PDT 24 14574105 ps
T1119 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2675909941 Jul 26 05:41:24 PM PDT 24 Jul 26 05:41:26 PM PDT 24 68240614 ps
T1120 /workspace/coverage/cover_reg_top/14.edn_intr_test.3242461906 Jul 26 05:41:29 PM PDT 24 Jul 26 05:41:30 PM PDT 24 24670051 ps
T1121 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2702052980 Jul 26 05:41:16 PM PDT 24 Jul 26 05:41:17 PM PDT 24 28111975 ps
T1122 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1662342376 Jul 26 05:42:00 PM PDT 24 Jul 26 05:42:04 PM PDT 24 184322378 ps
T1123 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3967841711 Jul 26 05:41:14 PM PDT 24 Jul 26 05:41:16 PM PDT 24 36616194 ps
T1124 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3645968151 Jul 26 05:41:24 PM PDT 24 Jul 26 05:41:25 PM PDT 24 88685862 ps
T1125 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3794640572 Jul 26 05:41:39 PM PDT 24 Jul 26 05:41:41 PM PDT 24 29860606 ps

Test location /workspace/coverage/default/137.edn_alert.416666510
Short name T1
Test name
Test status
Simulation time 26864460 ps
CPU time 1.24 seconds
Started Jul 26 05:44:15 PM PDT 24
Finished Jul 26 05:44:17 PM PDT 24
Peak memory 218992 kb
Host smart-96c313b8-0fde-4067-8cee-abf2bd2e092e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416666510 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.416666510
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3343003297
Short name T25
Test name
Test status
Simulation time 71985882 ps
CPU time 1.22 seconds
Started Jul 26 05:44:26 PM PDT 24
Finished Jul 26 05:44:28 PM PDT 24
Peak memory 217372 kb
Host smart-a8b85b20-7b0a-4a32-9828-34be1502bb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343003297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3343003297
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.343587775
Short name T21
Test name
Test status
Simulation time 297083171834 ps
CPU time 746.55 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:55:26 PM PDT 24
Peak memory 220152 kb
Host smart-63f038c7-0ec1-43fb-8a22-877a1c9fdbf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343587775 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.343587775
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.edn_err.362100205
Short name T49
Test name
Test status
Simulation time 34530072 ps
CPU time 0.88 seconds
Started Jul 26 05:43:46 PM PDT 24
Finished Jul 26 05:43:47 PM PDT 24
Peak memory 218516 kb
Host smart-e7309328-cda3-441a-b51c-c340a743ad94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362100205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.362100205
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1448276271
Short name T15
Test name
Test status
Simulation time 77802644 ps
CPU time 1.52 seconds
Started Jul 26 05:42:23 PM PDT 24
Finished Jul 26 05:42:25 PM PDT 24
Peak memory 216832 kb
Host smart-440dd14e-e70e-4bea-b063-e3afc5ff5012
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448276271 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1448276271
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.885861363
Short name T42
Test name
Test status
Simulation time 51792849 ps
CPU time 0.95 seconds
Started Jul 26 05:42:18 PM PDT 24
Finished Jul 26 05:42:19 PM PDT 24
Peak memory 223576 kb
Host smart-3710239b-9c2c-48a2-83a8-913815a4093d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885861363 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.885861363
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.917054966
Short name T94
Test name
Test status
Simulation time 235802594 ps
CPU time 1.09 seconds
Started Jul 26 05:43:10 PM PDT 24
Finished Jul 26 05:43:12 PM PDT 24
Peak memory 219668 kb
Host smart-4d39e1e0-0c19-47a9-9777-6e4bcc22a60b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917054966 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.917054966
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_alert.41386121
Short name T31
Test name
Test status
Simulation time 131843232 ps
CPU time 1.15 seconds
Started Jul 26 05:43:39 PM PDT 24
Finished Jul 26 05:43:40 PM PDT 24
Peak memory 219320 kb
Host smart-275b9364-bd59-42c4-a27f-c130d4822a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41386121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.41386121
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.3910965969
Short name T61
Test name
Test status
Simulation time 119360444 ps
CPU time 1.27 seconds
Started Jul 26 05:44:20 PM PDT 24
Finished Jul 26 05:44:22 PM PDT 24
Peak memory 217560 kb
Host smart-b57f78f8-8153-48e9-a882-e79b67fa7089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910965969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3910965969
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.922429817
Short name T187
Test name
Test status
Simulation time 37659651 ps
CPU time 1.35 seconds
Started Jul 26 05:44:23 PM PDT 24
Finished Jul 26 05:44:25 PM PDT 24
Peak memory 215720 kb
Host smart-b6eafb90-4ca0-4dc8-a9c3-8520e3c81868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922429817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.922429817
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/4.edn_regwen.1695946074
Short name T339
Test name
Test status
Simulation time 118378005 ps
CPU time 0.91 seconds
Started Jul 26 05:42:24 PM PDT 24
Finished Jul 26 05:42:25 PM PDT 24
Peak memory 206920 kb
Host smart-c70c95b6-aa0c-45d3-8cc1-7045256b3534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695946074 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1695946074
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/25.edn_intr.3086327385
Short name T80
Test name
Test status
Simulation time 87619853 ps
CPU time 0.92 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 215448 kb
Host smart-15d4aa1b-25f6-4089-b81e-a543a50feb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086327385 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3086327385
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/22.edn_alert.1433447830
Short name T190
Test name
Test status
Simulation time 95015300 ps
CPU time 1.17 seconds
Started Jul 26 05:42:55 PM PDT 24
Finished Jul 26 05:42:56 PM PDT 24
Peak memory 220956 kb
Host smart-086abc4a-7ee5-4ca4-8e44-1cb4f479d9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433447830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1433447830
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3397761492
Short name T296
Test name
Test status
Simulation time 129887100 ps
CPU time 1.48 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 206564 kb
Host smart-7e2a1e8d-3ff3-4fbf-a18c-687b1b802c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397761492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3397761492
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/default/26.edn_disable.3760494447
Short name T32
Test name
Test status
Simulation time 12462046 ps
CPU time 0.97 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 216264 kb
Host smart-0c52b97f-960d-4278-a66c-c81a386ec458
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760494447 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3760494447
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1123791249
Short name T135
Test name
Test status
Simulation time 48803555972 ps
CPU time 1236.97 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 06:03:36 PM PDT 24
Peak memory 222492 kb
Host smart-f8928b0e-4fce-4abf-9bfa-cf8ae3e921e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123791249 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1123791249
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/109.edn_alert.3948614026
Short name T141
Test name
Test status
Simulation time 46898775 ps
CPU time 1.3 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:03 PM PDT 24
Peak memory 218748 kb
Host smart-96c3816d-df19-417c-85e7-55ffa137d5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948614026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3948614026
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/28.edn_err.858432965
Short name T69
Test name
Test status
Simulation time 48231635 ps
CPU time 0.94 seconds
Started Jul 26 05:43:06 PM PDT 24
Finished Jul 26 05:43:12 PM PDT 24
Peak memory 219616 kb
Host smart-39cc5b8b-04da-476a-908d-88a1cc362454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858432965 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.858432965
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.945656724
Short name T119
Test name
Test status
Simulation time 135568034 ps
CPU time 1.31 seconds
Started Jul 26 05:42:44 PM PDT 24
Finished Jul 26 05:42:46 PM PDT 24
Peak memory 216800 kb
Host smart-b88d20a7-7d51-46fe-8795-302d87f470e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945656724 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.945656724
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_disable.3457440375
Short name T125
Test name
Test status
Simulation time 26486116 ps
CPU time 0.89 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:42:59 PM PDT 24
Peak memory 216084 kb
Host smart-0d172dab-4c4b-47c0-a17b-2300e32c5f10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457440375 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3457440375
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/0.edn_intr.417798414
Short name T88
Test name
Test status
Simulation time 28750948 ps
CPU time 0.88 seconds
Started Jul 26 05:42:16 PM PDT 24
Finished Jul 26 05:42:17 PM PDT 24
Peak memory 215652 kb
Host smart-4238216c-7f21-4440-8573-07e2d56027db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417798414 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.417798414
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.389590936
Short name T166
Test name
Test status
Simulation time 61806818 ps
CPU time 1.21 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 219520 kb
Host smart-e383ca6c-d9ce-470b-b966-17953821e859
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389590936 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.389590936
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/75.edn_alert.1424930289
Short name T283
Test name
Test status
Simulation time 67151994 ps
CPU time 1.25 seconds
Started Jul 26 05:43:43 PM PDT 24
Finished Jul 26 05:43:45 PM PDT 24
Peak memory 219632 kb
Host smart-48397fa5-44f4-4641-a5f0-5d6d263eb371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424930289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1424930289
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.139575683
Short name T261
Test name
Test status
Simulation time 34138817 ps
CPU time 0.94 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:21 PM PDT 24
Peak memory 206456 kb
Host smart-052feccc-19cf-413e-89b9-c0d4dcfab6a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139575683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.139575683
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/243.edn_genbits.3587842508
Short name T247
Test name
Test status
Simulation time 44070704 ps
CPU time 1.77 seconds
Started Jul 26 05:44:43 PM PDT 24
Finished Jul 26 05:44:45 PM PDT 24
Peak memory 218440 kb
Host smart-bfd43d0d-7994-4b5c-b478-58c65abc67ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587842508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3587842508
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.29163377
Short name T10
Test name
Test status
Simulation time 241899235 ps
CPU time 1.24 seconds
Started Jul 26 05:44:29 PM PDT 24
Finished Jul 26 05:44:30 PM PDT 24
Peak memory 218924 kb
Host smart-0fb1a556-0c61-40dd-96dc-0092a7c4fe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29163377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.29163377
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.348611322
Short name T161
Test name
Test status
Simulation time 204768055 ps
CPU time 1.27 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:52 PM PDT 24
Peak memory 219556 kb
Host smart-b9b6aeea-f798-468d-a5d5-c18a0c6c7c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348611322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.348611322
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/110.edn_alert.1872396807
Short name T222
Test name
Test status
Simulation time 22179811 ps
CPU time 1.21 seconds
Started Jul 26 05:43:56 PM PDT 24
Finished Jul 26 05:43:57 PM PDT 24
Peak memory 219780 kb
Host smart-7773292d-727f-4bfa-af21-c0fa1d6935fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872396807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1872396807
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/80.edn_alert.2706271000
Short name T755
Test name
Test status
Simulation time 196231616 ps
CPU time 1.47 seconds
Started Jul 26 05:43:55 PM PDT 24
Finished Jul 26 05:43:57 PM PDT 24
Peak memory 215616 kb
Host smart-1cbfd2b9-a582-4d6d-a3e6-bbb45b8e49f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706271000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2706271000
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/163.edn_alert.2302308574
Short name T254
Test name
Test status
Simulation time 33026405 ps
CPU time 1.33 seconds
Started Jul 26 05:44:15 PM PDT 24
Finished Jul 26 05:44:17 PM PDT 24
Peak memory 215484 kb
Host smart-1b3f5deb-2761-4fe3-ad44-75307cf0d8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302308574 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.2302308574
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert.825962380
Short name T340
Test name
Test status
Simulation time 68031046 ps
CPU time 1.1 seconds
Started Jul 26 05:42:11 PM PDT 24
Finished Jul 26 05:42:12 PM PDT 24
Peak memory 219532 kb
Host smart-c862d37b-7d51-4a7f-b2ce-954ab0b6c205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825962380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.825962380
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/139.edn_alert.616847616
Short name T346
Test name
Test status
Simulation time 156349541 ps
CPU time 1.17 seconds
Started Jul 26 05:44:02 PM PDT 24
Finished Jul 26 05:44:03 PM PDT 24
Peak memory 220548 kb
Host smart-37cba170-a363-4170-858e-2d31570ca117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616847616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.616847616
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert.3351097830
Short name T416
Test name
Test status
Simulation time 70779309 ps
CPU time 1.08 seconds
Started Jul 26 05:42:57 PM PDT 24
Finished Jul 26 05:42:58 PM PDT 24
Peak memory 218380 kb
Host smart-3d660431-0277-42a4-accc-8a886b8e275c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351097830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3351097830
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/90.edn_alert.972992179
Short name T341
Test name
Test status
Simulation time 23036463 ps
CPU time 1.1 seconds
Started Jul 26 05:43:54 PM PDT 24
Finished Jul 26 05:43:56 PM PDT 24
Peak memory 218348 kb
Host smart-3e0452d2-a8dd-4163-8577-eb47adeeace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972992179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.972992179
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable.4135295720
Short name T62
Test name
Test status
Simulation time 48605371 ps
CPU time 0.89 seconds
Started Jul 26 05:42:56 PM PDT 24
Finished Jul 26 05:42:57 PM PDT 24
Peak memory 216036 kb
Host smart-1577098c-1255-4bd2-9c7e-d11ad8bb14ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135295720 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.4135295720
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/229.edn_genbits.1255189040
Short name T336
Test name
Test status
Simulation time 30414697 ps
CPU time 1.24 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:44:54 PM PDT 24
Peak memory 217108 kb
Host smart-86f78387-4ff6-40d5-92d2-7f8b93c648f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255189040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1255189040
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.960444069
Short name T209
Test name
Test status
Simulation time 42629410 ps
CPU time 1.29 seconds
Started Jul 26 05:42:37 PM PDT 24
Finished Jul 26 05:42:38 PM PDT 24
Peak memory 215564 kb
Host smart-e29c46af-b96e-4df7-87bc-b3ec0463bf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960444069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.960444069
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/39.edn_disable.3536788415
Short name T106
Test name
Test status
Simulation time 13809656 ps
CPU time 0.84 seconds
Started Jul 26 05:43:32 PM PDT 24
Finished Jul 26 05:43:33 PM PDT 24
Peak memory 216160 kb
Host smart-571c8645-c0ec-4c8f-a76a-647e4956864a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536788415 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3536788415
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/114.edn_alert.1979925420
Short name T3
Test name
Test status
Simulation time 50106539 ps
CPU time 1.18 seconds
Started Jul 26 05:44:12 PM PDT 24
Finished Jul 26 05:44:14 PM PDT 24
Peak memory 215444 kb
Host smart-7b081770-9266-4c43-bb99-6ed66130a1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979925420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.1979925420
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3587483869
Short name T113
Test name
Test status
Simulation time 26001228 ps
CPU time 1.1 seconds
Started Jul 26 05:42:11 PM PDT 24
Finished Jul 26 05:42:13 PM PDT 24
Peak memory 216652 kb
Host smart-d58b9d50-61bf-4c58-a5dc-bad19d818696
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587483869 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3587483869
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_disable.170693539
Short name T91
Test name
Test status
Simulation time 22459393 ps
CPU time 0.89 seconds
Started Jul 26 05:42:37 PM PDT 24
Finished Jul 26 05:42:38 PM PDT 24
Peak memory 216076 kb
Host smart-e5e1ee44-3f89-4636-9789-2d8313a7f596
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170693539 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.170693539
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_intr.3567908908
Short name T377
Test name
Test status
Simulation time 77850086 ps
CPU time 0.9 seconds
Started Jul 26 05:42:34 PM PDT 24
Finished Jul 26 05:42:36 PM PDT 24
Peak memory 215108 kb
Host smart-6be9677c-5721-410c-8127-69511705bd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567908908 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3567908908
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/13.edn_disable.1765597788
Short name T199
Test name
Test status
Simulation time 30592295 ps
CPU time 0.91 seconds
Started Jul 26 05:42:44 PM PDT 24
Finished Jul 26 05:42:45 PM PDT 24
Peak memory 216132 kb
Host smart-1326f39c-fb37-469a-9d2a-0969a6523204
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765597788 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1765597788
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2208101259
Short name T98
Test name
Test status
Simulation time 93071055 ps
CPU time 1.17 seconds
Started Jul 26 05:42:40 PM PDT 24
Finished Jul 26 05:42:41 PM PDT 24
Peak memory 219484 kb
Host smart-80690426-be34-4df4-a965-39d0ade4a588
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208101259 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2208101259
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3370404079
Short name T759
Test name
Test status
Simulation time 80614243 ps
CPU time 1.06 seconds
Started Jul 26 05:42:56 PM PDT 24
Finished Jul 26 05:42:57 PM PDT 24
Peak memory 216652 kb
Host smart-c406536d-597e-4cdd-95e1-0e4873ce474f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370404079 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3370404079
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable.3342783483
Short name T184
Test name
Test status
Simulation time 28229256 ps
CPU time 0.82 seconds
Started Jul 26 05:42:54 PM PDT 24
Finished Jul 26 05:42:55 PM PDT 24
Peak memory 215256 kb
Host smart-d4b7aaea-d590-4bb9-9cb1-527d4ef83bef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342783483 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3342783483
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.2008287330
Short name T751
Test name
Test status
Simulation time 18485101 ps
CPU time 1.17 seconds
Started Jul 26 05:42:55 PM PDT 24
Finished Jul 26 05:42:56 PM PDT 24
Peak memory 223908 kb
Host smart-3787a4d5-56f9-472e-ac12-87a1e8129b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008287330 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2008287330
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/20.edn_disable.3393521222
Short name T92
Test name
Test status
Simulation time 12786232 ps
CPU time 0.89 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:01 PM PDT 24
Peak memory 216036 kb
Host smart-e987ef22-bc42-4bc5-8981-45d0dc5c674a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393521222 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3393521222
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1707491357
Short name T178
Test name
Test status
Simulation time 89414665 ps
CPU time 1.1 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:02 PM PDT 24
Peak memory 216680 kb
Host smart-99f7053c-a363-4500-8b63-873d65318bff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707491357 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1707491357
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2609145117
Short name T214
Test name
Test status
Simulation time 20218481 ps
CPU time 1.06 seconds
Started Jul 26 05:43:16 PM PDT 24
Finished Jul 26 05:43:17 PM PDT 24
Peak memory 219208 kb
Host smart-1a0750ed-2245-476a-99f0-b1bff7fb97a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609145117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2609145117
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/42.edn_disable.3150823073
Short name T103
Test name
Test status
Simulation time 46728544 ps
CPU time 0.89 seconds
Started Jul 26 05:43:16 PM PDT 24
Finished Jul 26 05:43:17 PM PDT 24
Peak memory 216172 kb
Host smart-88b64b17-5a0a-49ba-a93d-4ce35dc00bb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150823073 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3150823073
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.4080896745
Short name T129
Test name
Test status
Simulation time 26488675080 ps
CPU time 665.83 seconds
Started Jul 26 05:43:36 PM PDT 24
Finished Jul 26 05:54:42 PM PDT 24
Peak memory 218164 kb
Host smart-c4b95637-240d-4404-a977-56a8aaa6fc15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080896745 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.4080896745
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_disable.885496793
Short name T117
Test name
Test status
Simulation time 10703971 ps
CPU time 0.89 seconds
Started Jul 26 05:43:29 PM PDT 24
Finished Jul 26 05:43:30 PM PDT 24
Peak memory 216088 kb
Host smart-13a985f0-2257-4a9f-9f96-9abfadd8e351
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885496793 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.885496793
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/294.edn_genbits.2433993047
Short name T350
Test name
Test status
Simulation time 147293688 ps
CPU time 1.5 seconds
Started Jul 26 05:44:44 PM PDT 24
Finished Jul 26 05:44:46 PM PDT 24
Peak memory 219900 kb
Host smart-dbd6f44a-8fde-4bf2-aefb-4c9e3b549575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433993047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2433993047
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_alert_test.1556476049
Short name T355
Test name
Test status
Simulation time 52210845 ps
CPU time 0.86 seconds
Started Jul 26 05:42:16 PM PDT 24
Finished Jul 26 05:42:17 PM PDT 24
Peak memory 214548 kb
Host smart-8e84ac97-8b3a-4ed8-a7b9-1834bb4a711d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556476049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1556476049
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/99.edn_genbits.1699257237
Short name T307
Test name
Test status
Simulation time 102111137 ps
CPU time 1.13 seconds
Started Jul 26 05:43:49 PM PDT 24
Finished Jul 26 05:43:51 PM PDT 24
Peak memory 217164 kb
Host smart-0de7384b-3330-4ae8-b685-b5802bdfcf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699257237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1699257237
Directory /workspace/99.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.3106278018
Short name T64
Test name
Test status
Simulation time 70874646 ps
CPU time 1.41 seconds
Started Jul 26 05:44:35 PM PDT 24
Finished Jul 26 05:44:37 PM PDT 24
Peak memory 218692 kb
Host smart-da87526e-014e-4d26-aaa6-5a32ae68fdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106278018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3106278018
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.3794279289
Short name T304
Test name
Test status
Simulation time 59965340 ps
CPU time 1.18 seconds
Started Jul 26 05:44:02 PM PDT 24
Finished Jul 26 05:44:03 PM PDT 24
Peak memory 215460 kb
Host smart-c388f631-06da-4012-9bbe-e2755ec3fdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794279289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.3794279289
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.405896936
Short name T319
Test name
Test status
Simulation time 68256440 ps
CPU time 1.16 seconds
Started Jul 26 05:44:07 PM PDT 24
Finished Jul 26 05:44:08 PM PDT 24
Peak memory 218656 kb
Host smart-18508bdb-df5a-43fd-b8a7-bb91fd84f2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405896936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.405896936
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.144808296
Short name T334
Test name
Test status
Simulation time 52373056 ps
CPU time 1.36 seconds
Started Jul 26 05:44:39 PM PDT 24
Finished Jul 26 05:44:40 PM PDT 24
Peak memory 219752 kb
Host smart-03d57732-8c6a-4ff2-86e1-910e6abb71d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144808296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.144808296
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.327522208
Short name T227
Test name
Test status
Simulation time 25804612135 ps
CPU time 538.51 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:52:02 PM PDT 24
Peak memory 217724 kb
Host smart-43583034-18f1-4c4a-b7b0-611e6e3eebff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327522208 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.327522208
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.edn_alert.1425936600
Short name T287
Test name
Test status
Simulation time 27027376 ps
CPU time 1.22 seconds
Started Jul 26 05:44:27 PM PDT 24
Finished Jul 26 05:44:29 PM PDT 24
Peak memory 219612 kb
Host smart-f71b5252-a522-4608-8d4f-c8f99a31efbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425936600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.1425936600
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/27.edn_intr.4185503517
Short name T86
Test name
Test status
Simulation time 25271579 ps
CPU time 0.95 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:02 PM PDT 24
Peak memory 215636 kb
Host smart-b76cbbaa-15e1-4fdc-9cce-5066c4136f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185503517 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.4185503517
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.53935169
Short name T263
Test name
Test status
Simulation time 22038296 ps
CPU time 0.83 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 206280 kb
Host smart-7bf2caae-6efb-42e0-93bb-d12361bfd131
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53935169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.53935169
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2101303088
Short name T277
Test name
Test status
Simulation time 40269038 ps
CPU time 0.91 seconds
Started Jul 26 05:41:31 PM PDT 24
Finished Jul 26 05:41:32 PM PDT 24
Peak memory 206456 kb
Host smart-a6f3940f-841a-466d-8389-61b8902bff9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101303088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2101303088
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3271387025
Short name T1100
Test name
Test status
Simulation time 333713139 ps
CPU time 2.21 seconds
Started Jul 26 05:41:11 PM PDT 24
Finished Jul 26 05:41:13 PM PDT 24
Peak memory 206720 kb
Host smart-51c10bb4-47f6-4f84-8375-c0022f3667e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271387025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3271387025
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_genbits.986449995
Short name T733
Test name
Test status
Simulation time 50756437 ps
CPU time 1.09 seconds
Started Jul 26 05:42:09 PM PDT 24
Finished Jul 26 05:42:11 PM PDT 24
Peak memory 217308 kb
Host smart-b25d0a70-0561-449a-a736-f7b932fb7647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986449995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.986449995
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.3233939837
Short name T960
Test name
Test status
Simulation time 24284862 ps
CPU time 1.17 seconds
Started Jul 26 05:43:59 PM PDT 24
Finished Jul 26 05:44:00 PM PDT 24
Peak memory 217228 kb
Host smart-7ac05196-cd8b-486b-8d23-240ea84b11b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233939837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3233939837
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/130.edn_genbits.3412306858
Short name T316
Test name
Test status
Simulation time 28651982 ps
CPU time 1.26 seconds
Started Jul 26 05:44:16 PM PDT 24
Finished Jul 26 05:44:17 PM PDT 24
Peak memory 219444 kb
Host smart-9da8cf0f-c133-4943-bcb0-448887e6d08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412306858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3412306858
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.4092412541
Short name T329
Test name
Test status
Simulation time 88789772 ps
CPU time 1.36 seconds
Started Jul 26 05:44:17 PM PDT 24
Finished Jul 26 05:44:18 PM PDT 24
Peak memory 218736 kb
Host smart-03711531-a755-4caa-b9ca-485cbefdc291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092412541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.4092412541
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/180.edn_genbits.1177727230
Short name T17
Test name
Test status
Simulation time 386162559 ps
CPU time 1.36 seconds
Started Jul 26 05:44:16 PM PDT 24
Finished Jul 26 05:44:18 PM PDT 24
Peak memory 217364 kb
Host smart-48d5c2cc-178c-4a9b-974e-582baaf6bcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177727230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1177727230
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1673087755
Short name T180
Test name
Test status
Simulation time 47126414 ps
CPU time 1.2 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:52 PM PDT 24
Peak memory 218780 kb
Host smart-71ba35ab-456e-4dad-bc81-47ef762ce8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673087755 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1673087755
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/79.edn_genbits.4092818979
Short name T325
Test name
Test status
Simulation time 228950689 ps
CPU time 1.21 seconds
Started Jul 26 05:44:00 PM PDT 24
Finished Jul 26 05:44:01 PM PDT 24
Peak memory 219412 kb
Host smart-2f80b1b8-e815-4721-a7b2-6fa8114f9331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092818979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.4092818979
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_genbits.4157269834
Short name T333
Test name
Test status
Simulation time 89735764 ps
CPU time 1.26 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 218684 kb
Host smart-34ff0ede-1f0c-4eb8-8cdb-1cf1b566d58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157269834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.4157269834
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1291975380
Short name T880
Test name
Test status
Simulation time 25030482 ps
CPU time 0.97 seconds
Started Jul 26 05:42:40 PM PDT 24
Finished Jul 26 05:42:41 PM PDT 24
Peak memory 215796 kb
Host smart-30ca22f4-1cab-455c-b25b-ea595cc0e69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291975380 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1291975380
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/131.edn_alert.3590984962
Short name T143
Test name
Test status
Simulation time 69193088 ps
CPU time 1.29 seconds
Started Jul 26 05:44:13 PM PDT 24
Finished Jul 26 05:44:14 PM PDT 24
Peak memory 219752 kb
Host smart-5d186474-4db3-4208-84da-4d4143b8bbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590984962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3590984962
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2788150272
Short name T258
Test name
Test status
Simulation time 68480463 ps
CPU time 1.05 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:21 PM PDT 24
Peak memory 206484 kb
Host smart-23a38c5a-c5a1-4d31-a85f-a5142a2ecef4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788150272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2788150272
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.773983851
Short name T1012
Test name
Test status
Simulation time 192529387 ps
CPU time 3.38 seconds
Started Jul 26 05:41:05 PM PDT 24
Finished Jul 26 05:41:08 PM PDT 24
Peak memory 206388 kb
Host smart-2ee78d31-6822-4734-b678-168a8a8cd858
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773983851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.773983851
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4140524492
Short name T265
Test name
Test status
Simulation time 21854041 ps
CPU time 1 seconds
Started Jul 26 05:41:17 PM PDT 24
Finished Jul 26 05:41:18 PM PDT 24
Peak memory 206500 kb
Host smart-0362aa20-4c7e-426b-97f2-f863269ef96b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140524492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.4140524492
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.4148249391
Short name T1063
Test name
Test status
Simulation time 140741794 ps
CPU time 1.12 seconds
Started Jul 26 05:41:21 PM PDT 24
Finished Jul 26 05:41:22 PM PDT 24
Peak memory 214936 kb
Host smart-5df12084-0d49-43a6-b97c-747cf801cd1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148249391 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.4148249391
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2523660279
Short name T270
Test name
Test status
Simulation time 26217703 ps
CPU time 0.92 seconds
Started Jul 26 05:41:21 PM PDT 24
Finished Jul 26 05:41:22 PM PDT 24
Peak memory 206476 kb
Host smart-ff3d80ec-8426-4889-9c8b-5821aa2bd5c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523660279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2523660279
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1707248069
Short name T1007
Test name
Test status
Simulation time 57826568 ps
CPU time 0.92 seconds
Started Jul 26 05:41:18 PM PDT 24
Finished Jul 26 05:41:19 PM PDT 24
Peak memory 206428 kb
Host smart-4f8ea15c-e45f-4584-8825-67e8c32ef053
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707248069 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1707248069
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3645968151
Short name T1124
Test name
Test status
Simulation time 88685862 ps
CPU time 1.3 seconds
Started Jul 26 05:41:24 PM PDT 24
Finished Jul 26 05:41:25 PM PDT 24
Peak memory 206564 kb
Host smart-083b8f8c-30c2-4d65-8242-d72adc9ed85e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645968151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3645968151
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.486798228
Short name T1067
Test name
Test status
Simulation time 193166056 ps
CPU time 3.37 seconds
Started Jul 26 05:41:18 PM PDT 24
Finished Jul 26 05:41:21 PM PDT 24
Peak memory 214852 kb
Host smart-0d9ee651-aeac-4c43-924d-39c1175f03aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486798228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.486798228
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.56197409
Short name T1014
Test name
Test status
Simulation time 170167124 ps
CPU time 1.02 seconds
Started Jul 26 05:41:16 PM PDT 24
Finished Jul 26 05:41:18 PM PDT 24
Peak memory 206304 kb
Host smart-ef881909-94ac-47d9-a1b3-aebb7262b4f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56197409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.56197409
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2675909941
Short name T1119
Test name
Test status
Simulation time 68240614 ps
CPU time 2.01 seconds
Started Jul 26 05:41:24 PM PDT 24
Finished Jul 26 05:41:26 PM PDT 24
Peak memory 206420 kb
Host smart-5c17e1d1-82fa-4314-ab2f-56310e14b0cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675909941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2675909941
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.714786429
Short name T1091
Test name
Test status
Simulation time 24441873 ps
CPU time 1.74 seconds
Started Jul 26 05:41:19 PM PDT 24
Finished Jul 26 05:41:21 PM PDT 24
Peak memory 214824 kb
Host smart-d1aa92f9-abbb-49d0-9119-0be26d430bfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714786429 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.714786429
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2907158582
Short name T1096
Test name
Test status
Simulation time 13960522 ps
CPU time 0.9 seconds
Started Jul 26 05:41:23 PM PDT 24
Finished Jul 26 05:41:24 PM PDT 24
Peak memory 206388 kb
Host smart-54021401-d1ff-44fc-9621-99f3a74f62cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907158582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2907158582
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2858772564
Short name T1059
Test name
Test status
Simulation time 14607131 ps
CPU time 0.92 seconds
Started Jul 26 05:41:22 PM PDT 24
Finished Jul 26 05:41:23 PM PDT 24
Peak memory 206492 kb
Host smart-b8223970-bd7a-4ef5-951b-9b03e623d259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858772564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2858772564
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4171656471
Short name T1111
Test name
Test status
Simulation time 139692843 ps
CPU time 1 seconds
Started Jul 26 05:41:17 PM PDT 24
Finished Jul 26 05:41:18 PM PDT 24
Peak memory 206568 kb
Host smart-c1052968-03fd-46bc-8575-8c42e79c77cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171656471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.4171656471
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3737688236
Short name T1058
Test name
Test status
Simulation time 169888121 ps
CPU time 1.99 seconds
Started Jul 26 05:41:24 PM PDT 24
Finished Jul 26 05:41:32 PM PDT 24
Peak memory 214900 kb
Host smart-8efdaf0f-8f2d-4b36-8cce-7ee1c59e6578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737688236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3737688236
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1393512171
Short name T1082
Test name
Test status
Simulation time 201275141 ps
CPU time 1.55 seconds
Started Jul 26 05:41:21 PM PDT 24
Finished Jul 26 05:41:23 PM PDT 24
Peak memory 214844 kb
Host smart-4611641b-f978-4256-9190-6ee65a8a564b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393512171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1393512171
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1101459882
Short name T998
Test name
Test status
Simulation time 77663061 ps
CPU time 1.12 seconds
Started Jul 26 05:41:33 PM PDT 24
Finished Jul 26 05:41:34 PM PDT 24
Peak memory 216696 kb
Host smart-ba67cf5b-7573-486c-a99a-8f2e24fc0b29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101459882 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1101459882
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1344207327
Short name T1114
Test name
Test status
Simulation time 95579255 ps
CPU time 0.9 seconds
Started Jul 26 05:41:26 PM PDT 24
Finished Jul 26 05:41:27 PM PDT 24
Peak memory 206460 kb
Host smart-e3c754f2-31bf-42d4-8e84-f74377e18cf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344207327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1344207327
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.336580549
Short name T1097
Test name
Test status
Simulation time 46171404 ps
CPU time 0.87 seconds
Started Jul 26 05:41:22 PM PDT 24
Finished Jul 26 05:41:23 PM PDT 24
Peak memory 206460 kb
Host smart-bbf53ecc-101f-4d8a-ab6e-8be1345e2e17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336580549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.336580549
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2616909116
Short name T1025
Test name
Test status
Simulation time 183740232 ps
CPU time 1.3 seconds
Started Jul 26 05:41:22 PM PDT 24
Finished Jul 26 05:41:23 PM PDT 24
Peak memory 206744 kb
Host smart-3ceb41b5-f6fe-4d46-b57f-2691bc299604
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616909116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2616909116
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3173121493
Short name T1113
Test name
Test status
Simulation time 75400154 ps
CPU time 1.62 seconds
Started Jul 26 05:41:29 PM PDT 24
Finished Jul 26 05:41:31 PM PDT 24
Peak memory 214812 kb
Host smart-2f9618d3-a429-49f5-b7da-30400a51de76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173121493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3173121493
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3256416745
Short name T300
Test name
Test status
Simulation time 842661479 ps
CPU time 1.94 seconds
Started Jul 26 05:41:29 PM PDT 24
Finished Jul 26 05:41:31 PM PDT 24
Peak memory 206524 kb
Host smart-6e884330-1df0-4ce5-8824-5f077ef203ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256416745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3256416745
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2718800434
Short name T1010
Test name
Test status
Simulation time 29365327 ps
CPU time 1.56 seconds
Started Jul 26 05:41:27 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 214764 kb
Host smart-dccd9a48-1b17-4c52-8890-7ed4a3479a4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718800434 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2718800434
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1640730905
Short name T1031
Test name
Test status
Simulation time 12963710 ps
CPU time 0.87 seconds
Started Jul 26 05:41:30 PM PDT 24
Finished Jul 26 05:41:31 PM PDT 24
Peak memory 206444 kb
Host smart-bc440aad-8a7d-4c60-a78a-c67a7274c931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640730905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1640730905
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2335450926
Short name T1048
Test name
Test status
Simulation time 70110921 ps
CPU time 1.17 seconds
Started Jul 26 05:41:32 PM PDT 24
Finished Jul 26 05:41:33 PM PDT 24
Peak memory 206644 kb
Host smart-6ae99efa-770f-44c0-8125-d3c8345a175b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335450926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2335450926
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.344206045
Short name T1107
Test name
Test status
Simulation time 294031982 ps
CPU time 2.23 seconds
Started Jul 26 05:41:31 PM PDT 24
Finished Jul 26 05:41:33 PM PDT 24
Peak memory 214848 kb
Host smart-8b140e33-b827-4e05-a93a-4c29819abd94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344206045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.344206045
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3577739984
Short name T225
Test name
Test status
Simulation time 152504532 ps
CPU time 2.16 seconds
Started Jul 26 05:41:29 PM PDT 24
Finished Jul 26 05:41:32 PM PDT 24
Peak memory 206592 kb
Host smart-59196971-3ffb-491e-8b0d-2647c1918c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577739984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3577739984
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1274278224
Short name T1050
Test name
Test status
Simulation time 41960375 ps
CPU time 1.09 seconds
Started Jul 26 05:41:30 PM PDT 24
Finished Jul 26 05:41:31 PM PDT 24
Peak memory 214796 kb
Host smart-ca1f5252-ac05-412f-823f-c87b7ecd09f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274278224 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1274278224
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.255259681
Short name T1062
Test name
Test status
Simulation time 22512812 ps
CPU time 0.86 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 206440 kb
Host smart-6c52b4d3-5e87-4cbf-bce2-1a1c7255bedf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255259681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.255259681
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1435402791
Short name T1041
Test name
Test status
Simulation time 27753680 ps
CPU time 0.87 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 206464 kb
Host smart-668280e0-a0d4-402a-b692-e5f911cacada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435402791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1435402791
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1041219550
Short name T1022
Test name
Test status
Simulation time 61487047 ps
CPU time 1.08 seconds
Started Jul 26 05:41:31 PM PDT 24
Finished Jul 26 05:41:32 PM PDT 24
Peak memory 206456 kb
Host smart-65955c23-ba91-4b90-b3e7-06f16df55ff9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041219550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1041219550
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3401656207
Short name T999
Test name
Test status
Simulation time 172707279 ps
CPU time 5.27 seconds
Started Jul 26 05:41:29 PM PDT 24
Finished Jul 26 05:41:34 PM PDT 24
Peak memory 215040 kb
Host smart-d8aecdb8-692f-4e98-9a38-f7c882226de5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401656207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3401656207
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2800211604
Short name T1081
Test name
Test status
Simulation time 104648974 ps
CPU time 1.57 seconds
Started Jul 26 05:41:30 PM PDT 24
Finished Jul 26 05:41:32 PM PDT 24
Peak memory 206900 kb
Host smart-40ab1aee-d805-4844-b523-56331512afe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800211604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2800211604
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3794640572
Short name T1125
Test name
Test status
Simulation time 29860606 ps
CPU time 1.33 seconds
Started Jul 26 05:41:39 PM PDT 24
Finished Jul 26 05:41:41 PM PDT 24
Peak memory 214840 kb
Host smart-1ae66f30-f17f-4489-90de-ee2495c0ca9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794640572 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3794640572
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3928201548
Short name T1052
Test name
Test status
Simulation time 31618219 ps
CPU time 0.88 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 206428 kb
Host smart-3a991a48-32ef-4a49-ab16-2eb9fe9f2b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928201548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3928201548
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.249782549
Short name T257
Test name
Test status
Simulation time 36470282 ps
CPU time 1.09 seconds
Started Jul 26 05:41:34 PM PDT 24
Finished Jul 26 05:41:35 PM PDT 24
Peak memory 206536 kb
Host smart-c45d5a6c-1d26-49ac-92c0-f9953cb689f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249782549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.249782549
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.4291702238
Short name T1092
Test name
Test status
Simulation time 79441524 ps
CPU time 2.88 seconds
Started Jul 26 05:41:31 PM PDT 24
Finished Jul 26 05:41:34 PM PDT 24
Peak memory 214960 kb
Host smart-0ae2ade8-ca17-4765-b03d-c731efb150e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291702238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.4291702238
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.4281258004
Short name T301
Test name
Test status
Simulation time 177017315 ps
CPU time 2.57 seconds
Started Jul 26 05:41:30 PM PDT 24
Finished Jul 26 05:41:33 PM PDT 24
Peak memory 215308 kb
Host smart-3bbd29aa-e12a-423e-a865-f4e3b9b36ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281258004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.4281258004
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.963055092
Short name T1017
Test name
Test status
Simulation time 44085480 ps
CPU time 1.2 seconds
Started Jul 26 05:41:27 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 214908 kb
Host smart-c71b4a78-766e-490f-8238-e47425820136
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963055092 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.963055092
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1892069885
Short name T1110
Test name
Test status
Simulation time 23173985 ps
CPU time 0.96 seconds
Started Jul 26 05:41:44 PM PDT 24
Finished Jul 26 05:41:45 PM PDT 24
Peak memory 206480 kb
Host smart-45e6df03-7925-4406-a9d5-a277e3a7339f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892069885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1892069885
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3242461906
Short name T1120
Test name
Test status
Simulation time 24670051 ps
CPU time 0.82 seconds
Started Jul 26 05:41:29 PM PDT 24
Finished Jul 26 05:41:30 PM PDT 24
Peak memory 206420 kb
Host smart-d3fb1ff4-5a61-409d-a781-82b32339e724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242461906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3242461906
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2083617667
Short name T1077
Test name
Test status
Simulation time 25267401 ps
CPU time 0.94 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 206532 kb
Host smart-ab5c40f0-a577-48d3-921c-334f0cd7d23d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083617667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2083617667
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1282533518
Short name T1053
Test name
Test status
Simulation time 126043731 ps
CPU time 4.21 seconds
Started Jul 26 05:41:30 PM PDT 24
Finished Jul 26 05:41:34 PM PDT 24
Peak memory 214852 kb
Host smart-4a5b6075-29b0-4077-97fb-34abcad5b0fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282533518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1282533518
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.804543402
Short name T224
Test name
Test status
Simulation time 133030767 ps
CPU time 1.61 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:30 PM PDT 24
Peak memory 206624 kb
Host smart-0b4e8d53-744c-4a6b-aea3-fe47576228ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804543402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.804543402
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3676462371
Short name T1117
Test name
Test status
Simulation time 23785289 ps
CPU time 1.48 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:30 PM PDT 24
Peak memory 214808 kb
Host smart-b10505d9-2f37-40c9-bf66-89e27dfd5378
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676462371 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3676462371
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.279607963
Short name T1021
Test name
Test status
Simulation time 16535006 ps
CPU time 0.86 seconds
Started Jul 26 05:41:26 PM PDT 24
Finished Jul 26 05:41:27 PM PDT 24
Peak memory 206436 kb
Host smart-2ab6cbdf-65b2-4ee5-aea3-57c2e13ad1ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279607963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.279607963
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3416072794
Short name T1070
Test name
Test status
Simulation time 14740252 ps
CPU time 1 seconds
Started Jul 26 05:41:27 PM PDT 24
Finished Jul 26 05:41:28 PM PDT 24
Peak memory 206436 kb
Host smart-4ec34982-20f9-4788-b85e-11aeaf516f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416072794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3416072794
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3880350216
Short name T256
Test name
Test status
Simulation time 23990577 ps
CPU time 1.12 seconds
Started Jul 26 05:41:27 PM PDT 24
Finished Jul 26 05:41:28 PM PDT 24
Peak memory 206560 kb
Host smart-9a3f8882-0c00-4d68-b3ed-ff3ae4aec232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880350216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3880350216
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2899738011
Short name T1033
Test name
Test status
Simulation time 422975799 ps
CPU time 4.04 seconds
Started Jul 26 05:41:30 PM PDT 24
Finished Jul 26 05:41:34 PM PDT 24
Peak memory 214832 kb
Host smart-43efbf35-ffe9-46f2-ad51-24f591f513e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899738011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2899738011
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2289219203
Short name T1099
Test name
Test status
Simulation time 107222251 ps
CPU time 1.17 seconds
Started Jul 26 05:41:29 PM PDT 24
Finished Jul 26 05:41:31 PM PDT 24
Peak memory 214764 kb
Host smart-5b68dc13-20c5-4b21-a6e5-26fa607cbae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289219203 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2289219203
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.150559145
Short name T1090
Test name
Test status
Simulation time 14378054 ps
CPU time 0.92 seconds
Started Jul 26 05:41:29 PM PDT 24
Finished Jul 26 05:41:30 PM PDT 24
Peak memory 206352 kb
Host smart-06794ec7-34f6-4651-9d74-b2eb42e6d8d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150559145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.150559145
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3933650376
Short name T1075
Test name
Test status
Simulation time 14211947 ps
CPU time 0.86 seconds
Started Jul 26 05:41:30 PM PDT 24
Finished Jul 26 05:41:31 PM PDT 24
Peak memory 206440 kb
Host smart-26dbe068-e8ef-42e1-a2ad-cc1170a595ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933650376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3933650376
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1667804511
Short name T1074
Test name
Test status
Simulation time 43546891 ps
CPU time 0.92 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 206608 kb
Host smart-92aa77df-4ce6-432b-bf32-cc4a05f00060
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667804511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1667804511
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1518103869
Short name T1072
Test name
Test status
Simulation time 193519751 ps
CPU time 2.26 seconds
Started Jul 26 05:41:27 PM PDT 24
Finished Jul 26 05:41:30 PM PDT 24
Peak memory 214768 kb
Host smart-ae4d6e78-1d14-4152-9f9c-d13040459b79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518103869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1518103869
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1209411340
Short name T1023
Test name
Test status
Simulation time 52398346 ps
CPU time 1.72 seconds
Started Jul 26 05:41:30 PM PDT 24
Finished Jul 26 05:41:32 PM PDT 24
Peak memory 206820 kb
Host smart-4c806d17-38bf-4f42-b65b-22d12985ec30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209411340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1209411340
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1527359796
Short name T1089
Test name
Test status
Simulation time 58349349 ps
CPU time 1.09 seconds
Started Jul 26 05:41:40 PM PDT 24
Finished Jul 26 05:41:41 PM PDT 24
Peak memory 214956 kb
Host smart-b2aba1a9-a771-4bff-a340-24a0464a05d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527359796 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1527359796
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.681166354
Short name T1026
Test name
Test status
Simulation time 14177026 ps
CPU time 0.9 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:30 PM PDT 24
Peak memory 206484 kb
Host smart-ad11a811-f865-4cdf-ba7e-3d7d75630341
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681166354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.681166354
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.721570517
Short name T1078
Test name
Test status
Simulation time 34271042 ps
CPU time 0.81 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 206384 kb
Host smart-44615ba6-4668-4906-909f-9e79e4d9b76c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721570517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.721570517
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.337662851
Short name T1037
Test name
Test status
Simulation time 25698093 ps
CPU time 0.95 seconds
Started Jul 26 05:41:33 PM PDT 24
Finished Jul 26 05:41:34 PM PDT 24
Peak memory 206628 kb
Host smart-733e1cb7-d36a-4d8e-b9f2-557080781760
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337662851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.337662851
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1401717981
Short name T1064
Test name
Test status
Simulation time 246542383 ps
CPU time 4.31 seconds
Started Jul 26 05:41:30 PM PDT 24
Finished Jul 26 05:41:35 PM PDT 24
Peak memory 214832 kb
Host smart-fdc01e7e-9c0f-4ecb-a8a4-14d874097350
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401717981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1401717981
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1559325694
Short name T297
Test name
Test status
Simulation time 153791664 ps
CPU time 2.35 seconds
Started Jul 26 05:41:42 PM PDT 24
Finished Jul 26 05:41:44 PM PDT 24
Peak memory 206464 kb
Host smart-114fe89d-0d25-4081-aa58-446091e3308e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559325694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1559325694
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1641088855
Short name T1029
Test name
Test status
Simulation time 26515613 ps
CPU time 1.24 seconds
Started Jul 26 05:41:40 PM PDT 24
Finished Jul 26 05:41:41 PM PDT 24
Peak memory 214852 kb
Host smart-8b192b52-5f7b-4d19-a1a1-87f51ea9fca2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641088855 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1641088855
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.4249151567
Short name T1008
Test name
Test status
Simulation time 31542553 ps
CPU time 0.81 seconds
Started Jul 26 05:41:34 PM PDT 24
Finished Jul 26 05:41:35 PM PDT 24
Peak memory 206296 kb
Host smart-1ed977e3-bbdd-4409-9151-da24cb592bc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249151567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.4249151567
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3998500952
Short name T1004
Test name
Test status
Simulation time 21047055 ps
CPU time 0.82 seconds
Started Jul 26 05:41:29 PM PDT 24
Finished Jul 26 05:41:30 PM PDT 24
Peak memory 206396 kb
Host smart-23c08a6a-dbed-49af-99b6-1c2319d7df65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998500952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3998500952
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3904486685
Short name T272
Test name
Test status
Simulation time 36034359 ps
CPU time 1.04 seconds
Started Jul 26 05:41:33 PM PDT 24
Finished Jul 26 05:41:34 PM PDT 24
Peak memory 206620 kb
Host smart-7e391b34-916d-48f0-92b6-3b697d07b634
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904486685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3904486685
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3917371761
Short name T1112
Test name
Test status
Simulation time 269907383 ps
CPU time 3.86 seconds
Started Jul 26 05:41:30 PM PDT 24
Finished Jul 26 05:41:34 PM PDT 24
Peak memory 214912 kb
Host smart-a77c1bcb-39c7-411c-a6ae-33d86a2d6a65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917371761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3917371761
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2073404342
Short name T1104
Test name
Test status
Simulation time 159392375 ps
CPU time 3.63 seconds
Started Jul 26 05:41:26 PM PDT 24
Finished Jul 26 05:41:30 PM PDT 24
Peak memory 206572 kb
Host smart-a36f0480-1fc5-4d18-b2f1-1bbf33371191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073404342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2073404342
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3259439637
Short name T996
Test name
Test status
Simulation time 104779495 ps
CPU time 1.49 seconds
Started Jul 26 05:41:49 PM PDT 24
Finished Jul 26 05:41:51 PM PDT 24
Peak memory 214872 kb
Host smart-f4c7756b-4731-4dcb-b131-1fa422903f06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259439637 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3259439637
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.4193947494
Short name T1069
Test name
Test status
Simulation time 13728082 ps
CPU time 0.89 seconds
Started Jul 26 05:41:40 PM PDT 24
Finished Jul 26 05:41:41 PM PDT 24
Peak memory 206440 kb
Host smart-0e2cb37f-b0c8-4109-87fd-c87bb8b8aee4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193947494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.4193947494
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2088839560
Short name T1056
Test name
Test status
Simulation time 17488480 ps
CPU time 0.93 seconds
Started Jul 26 05:41:40 PM PDT 24
Finished Jul 26 05:41:41 PM PDT 24
Peak memory 206448 kb
Host smart-6be84298-bb53-4c80-8d45-79cb6d40e6d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088839560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2088839560
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.630335403
Short name T278
Test name
Test status
Simulation time 22628302 ps
CPU time 1.22 seconds
Started Jul 26 05:41:45 PM PDT 24
Finished Jul 26 05:41:46 PM PDT 24
Peak memory 206648 kb
Host smart-9448d7d7-7ba3-4a99-b717-ee4e63751913
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630335403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.630335403
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1662342376
Short name T1122
Test name
Test status
Simulation time 184322378 ps
CPU time 3.27 seconds
Started Jul 26 05:42:00 PM PDT 24
Finished Jul 26 05:42:04 PM PDT 24
Peak memory 214928 kb
Host smart-a98f5227-35d7-4aab-b082-182ffe5ef8d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662342376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1662342376
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1183027885
Short name T1086
Test name
Test status
Simulation time 120244320 ps
CPU time 1.4 seconds
Started Jul 26 05:41:37 PM PDT 24
Finished Jul 26 05:41:38 PM PDT 24
Peak memory 206496 kb
Host smart-6b600530-afc0-4bc8-b3a8-07a7a6b4a960
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183027885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1183027885
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.265702946
Short name T1018
Test name
Test status
Simulation time 159606241 ps
CPU time 1.73 seconds
Started Jul 26 05:41:17 PM PDT 24
Finished Jul 26 05:41:19 PM PDT 24
Peak memory 206440 kb
Host smart-efbf3ad6-4450-4373-b766-52de80784911
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265702946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.265702946
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3922686278
Short name T269
Test name
Test status
Simulation time 193037088 ps
CPU time 3.19 seconds
Started Jul 26 05:41:23 PM PDT 24
Finished Jul 26 05:41:26 PM PDT 24
Peak memory 206524 kb
Host smart-51280752-5cc6-41d1-8500-e9c1b812ab26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922686278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3922686278
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1634143751
Short name T268
Test name
Test status
Simulation time 13502373 ps
CPU time 0.87 seconds
Started Jul 26 05:41:16 PM PDT 24
Finished Jul 26 05:41:17 PM PDT 24
Peak memory 206412 kb
Host smart-74dfc2e6-f613-4537-be9b-a8896738d924
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634143751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1634143751
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1596131828
Short name T1093
Test name
Test status
Simulation time 49871326 ps
CPU time 1.86 seconds
Started Jul 26 05:41:24 PM PDT 24
Finished Jul 26 05:41:26 PM PDT 24
Peak memory 214812 kb
Host smart-3c41b718-9cb6-4992-843c-03dc056d2b92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596131828 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1596131828
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1437803021
Short name T264
Test name
Test status
Simulation time 25217339 ps
CPU time 0.93 seconds
Started Jul 26 05:41:18 PM PDT 24
Finished Jul 26 05:41:19 PM PDT 24
Peak memory 206708 kb
Host smart-fceaeb67-f629-44d6-881e-d45970732fb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437803021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1437803021
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1338586037
Short name T1076
Test name
Test status
Simulation time 22018842 ps
CPU time 0.86 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:21 PM PDT 24
Peak memory 206424 kb
Host smart-de597aeb-79e1-4d5c-a5bb-9d9fce40ce41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338586037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1338586037
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1117218290
Short name T1047
Test name
Test status
Simulation time 73821700 ps
CPU time 1.09 seconds
Started Jul 26 05:41:24 PM PDT 24
Finished Jul 26 05:41:25 PM PDT 24
Peak memory 206652 kb
Host smart-2d186e5e-ae7e-4458-9b9f-6b6201e48d4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117218290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1117218290
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.4203494345
Short name T1034
Test name
Test status
Simulation time 466086262 ps
CPU time 3.51 seconds
Started Jul 26 05:41:24 PM PDT 24
Finished Jul 26 05:41:28 PM PDT 24
Peak memory 214880 kb
Host smart-846ccfcf-b55e-4c15-bb2c-ae939f21eff6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203494345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4203494345
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.622161898
Short name T295
Test name
Test status
Simulation time 64157259 ps
CPU time 1.95 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:22 PM PDT 24
Peak memory 206604 kb
Host smart-8d27d655-7c11-4425-98de-def7ec4e77a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622161898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.622161898
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2253284575
Short name T1016
Test name
Test status
Simulation time 12784317 ps
CPU time 0.85 seconds
Started Jul 26 05:41:38 PM PDT 24
Finished Jul 26 05:41:39 PM PDT 24
Peak memory 206468 kb
Host smart-12878fa4-12aa-4c82-8f6d-1a45c545b60e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253284575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2253284575
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.879798402
Short name T1098
Test name
Test status
Simulation time 19810286 ps
CPU time 0.85 seconds
Started Jul 26 05:41:44 PM PDT 24
Finished Jul 26 05:41:45 PM PDT 24
Peak memory 206276 kb
Host smart-9c0235d8-e2f8-4f0e-a947-9890410ce981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879798402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.879798402
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3325346857
Short name T1088
Test name
Test status
Simulation time 13188520 ps
CPU time 0.89 seconds
Started Jul 26 05:41:36 PM PDT 24
Finished Jul 26 05:41:37 PM PDT 24
Peak memory 206700 kb
Host smart-352e161b-c540-4a32-b478-d364adeb2d98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325346857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3325346857
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.4046063160
Short name T1024
Test name
Test status
Simulation time 12716839 ps
CPU time 0.9 seconds
Started Jul 26 05:41:39 PM PDT 24
Finished Jul 26 05:41:40 PM PDT 24
Peak memory 206432 kb
Host smart-455cc193-a442-48ac-aca4-08fd9d95cee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046063160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.4046063160
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3366975450
Short name T1101
Test name
Test status
Simulation time 20495860 ps
CPU time 0.81 seconds
Started Jul 26 05:41:53 PM PDT 24
Finished Jul 26 05:41:54 PM PDT 24
Peak memory 206264 kb
Host smart-9ab61f28-c46a-4cae-ad6d-7d071e587e33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366975450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3366975450
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.554841173
Short name T1011
Test name
Test status
Simulation time 47004649 ps
CPU time 0.9 seconds
Started Jul 26 05:41:35 PM PDT 24
Finished Jul 26 05:41:36 PM PDT 24
Peak memory 206696 kb
Host smart-030e6f04-8257-42ec-a2cd-5c25138e89c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554841173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.554841173
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3483571796
Short name T1103
Test name
Test status
Simulation time 28507675 ps
CPU time 0.81 seconds
Started Jul 26 05:41:46 PM PDT 24
Finished Jul 26 05:41:47 PM PDT 24
Peak memory 206288 kb
Host smart-b7a93f0c-1ea0-4495-8c8d-59e4924a87d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483571796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3483571796
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3374499425
Short name T1036
Test name
Test status
Simulation time 13769694 ps
CPU time 0.91 seconds
Started Jul 26 05:41:38 PM PDT 24
Finished Jul 26 05:41:39 PM PDT 24
Peak memory 206388 kb
Host smart-ddbc7ecb-f9dd-48c7-8639-aa26864034b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374499425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3374499425
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2046680234
Short name T1001
Test name
Test status
Simulation time 33456305 ps
CPU time 0.76 seconds
Started Jul 26 05:41:45 PM PDT 24
Finished Jul 26 05:41:46 PM PDT 24
Peak memory 206284 kb
Host smart-7ac5afaf-8d7f-4b38-b0e2-2653e31d37a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046680234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2046680234
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3038307358
Short name T1057
Test name
Test status
Simulation time 18981155 ps
CPU time 0.83 seconds
Started Jul 26 05:41:37 PM PDT 24
Finished Jul 26 05:41:38 PM PDT 24
Peak memory 206468 kb
Host smart-5b4f708e-04e3-4392-a9b4-cd615878ce76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038307358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3038307358
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.728010766
Short name T1068
Test name
Test status
Simulation time 24626137 ps
CPU time 1.17 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:21 PM PDT 24
Peak memory 206444 kb
Host smart-22209308-0882-4fb7-9592-2766a53c5628
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728010766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.728010766
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1781003419
Short name T1035
Test name
Test status
Simulation time 186557301 ps
CPU time 5.4 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:26 PM PDT 24
Peak memory 206444 kb
Host smart-b2ca1fc9-aa87-4d7d-8971-18aead54bd27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781003419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1781003419
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2950489551
Short name T267
Test name
Test status
Simulation time 22063050 ps
CPU time 0.87 seconds
Started Jul 26 05:41:21 PM PDT 24
Finished Jul 26 05:41:22 PM PDT 24
Peak memory 206456 kb
Host smart-31c592c4-f712-4c09-a10c-9bc1e05f1b9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950489551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2950489551
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3967841711
Short name T1123
Test name
Test status
Simulation time 36616194 ps
CPU time 1.1 seconds
Started Jul 26 05:41:14 PM PDT 24
Finished Jul 26 05:41:16 PM PDT 24
Peak memory 216524 kb
Host smart-d76d0dbb-84ca-44cb-869b-81cb2320dfd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967841711 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3967841711
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2498996437
Short name T266
Test name
Test status
Simulation time 19832488 ps
CPU time 0.86 seconds
Started Jul 26 05:41:18 PM PDT 24
Finished Jul 26 05:41:19 PM PDT 24
Peak memory 206260 kb
Host smart-15036c59-346d-43ed-a975-e44ca2c266af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498996437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2498996437
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.488609196
Short name T1009
Test name
Test status
Simulation time 14999720 ps
CPU time 0.88 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:21 PM PDT 24
Peak memory 206480 kb
Host smart-08b958c6-56d6-4025-b2d3-51e9d9f45c2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488609196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.488609196
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2338765249
Short name T1066
Test name
Test status
Simulation time 56814044 ps
CPU time 1.18 seconds
Started Jul 26 05:41:16 PM PDT 24
Finished Jul 26 05:41:18 PM PDT 24
Peak memory 206564 kb
Host smart-93ecec30-9595-4430-9534-bc954b576aea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338765249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2338765249
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.906044374
Short name T1038
Test name
Test status
Simulation time 77579208 ps
CPU time 2.99 seconds
Started Jul 26 05:41:21 PM PDT 24
Finished Jul 26 05:41:24 PM PDT 24
Peak memory 214832 kb
Host smart-fa0a85e2-49f3-4d0a-bb39-2520d9f8715a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906044374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.906044374
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1051827567
Short name T226
Test name
Test status
Simulation time 62799597 ps
CPU time 1.81 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:22 PM PDT 24
Peak memory 214784 kb
Host smart-1d4ee118-d5bf-4816-915b-82ad2da94e84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051827567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1051827567
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1021421429
Short name T1019
Test name
Test status
Simulation time 46103893 ps
CPU time 0.86 seconds
Started Jul 26 05:41:52 PM PDT 24
Finished Jul 26 05:41:53 PM PDT 24
Peak memory 206356 kb
Host smart-6558f95f-6226-41b4-9a7b-c7633e9556a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021421429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1021421429
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2455750263
Short name T1003
Test name
Test status
Simulation time 59220808 ps
CPU time 0.95 seconds
Started Jul 26 05:41:42 PM PDT 24
Finished Jul 26 05:41:43 PM PDT 24
Peak memory 206432 kb
Host smart-539d84e8-d3fc-4267-b645-f4a8992b9168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455750263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2455750263
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3199053595
Short name T1073
Test name
Test status
Simulation time 35852725 ps
CPU time 0.77 seconds
Started Jul 26 05:41:36 PM PDT 24
Finished Jul 26 05:41:37 PM PDT 24
Peak memory 206232 kb
Host smart-8ee41138-33cf-46a3-b828-fa92b60cdea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199053595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3199053595
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1744877349
Short name T1102
Test name
Test status
Simulation time 45226301 ps
CPU time 0.86 seconds
Started Jul 26 05:41:40 PM PDT 24
Finished Jul 26 05:41:41 PM PDT 24
Peak memory 206440 kb
Host smart-06eb2ca3-7f23-4c35-9ebd-25b73af57641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744877349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1744877349
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1921537028
Short name T1051
Test name
Test status
Simulation time 11835802 ps
CPU time 0.86 seconds
Started Jul 26 05:41:37 PM PDT 24
Finished Jul 26 05:41:38 PM PDT 24
Peak memory 206492 kb
Host smart-ead6a63d-47c3-4d28-9de8-f184b41725c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921537028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1921537028
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2527951761
Short name T1045
Test name
Test status
Simulation time 41146270 ps
CPU time 0.84 seconds
Started Jul 26 05:41:41 PM PDT 24
Finished Jul 26 05:41:42 PM PDT 24
Peak memory 206452 kb
Host smart-23dda262-b104-4092-8193-dbb3c17928de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527951761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2527951761
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3040020239
Short name T1094
Test name
Test status
Simulation time 46842715 ps
CPU time 0.84 seconds
Started Jul 26 05:41:39 PM PDT 24
Finished Jul 26 05:41:40 PM PDT 24
Peak memory 206444 kb
Host smart-e4653216-0b11-4964-9c64-1aa1adf03bc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040020239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3040020239
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.958590909
Short name T1032
Test name
Test status
Simulation time 33241407 ps
CPU time 0.86 seconds
Started Jul 26 05:41:39 PM PDT 24
Finished Jul 26 05:41:40 PM PDT 24
Peak memory 206428 kb
Host smart-5767be2a-87b7-47d4-9a6c-49e89b65d246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958590909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.958590909
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.171188412
Short name T1118
Test name
Test status
Simulation time 14574105 ps
CPU time 0.91 seconds
Started Jul 26 05:41:44 PM PDT 24
Finished Jul 26 05:41:46 PM PDT 24
Peak memory 206468 kb
Host smart-0ae3e752-6d50-424c-9f21-0cc0b42aa9aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171188412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.171188412
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3184143729
Short name T997
Test name
Test status
Simulation time 26459976 ps
CPU time 0.87 seconds
Started Jul 26 05:41:47 PM PDT 24
Finished Jul 26 05:41:48 PM PDT 24
Peak memory 206480 kb
Host smart-75a97305-e806-4ae1-a386-01e71dd95883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184143729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3184143729
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1092405357
Short name T259
Test name
Test status
Simulation time 63321258 ps
CPU time 1.5 seconds
Started Jul 26 05:41:16 PM PDT 24
Finished Jul 26 05:41:18 PM PDT 24
Peak memory 206448 kb
Host smart-37178e78-ed60-4e2b-8adc-1b8a1fa559ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092405357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1092405357
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1051032275
Short name T1028
Test name
Test status
Simulation time 675687754 ps
CPU time 5.31 seconds
Started Jul 26 05:41:17 PM PDT 24
Finished Jul 26 05:41:22 PM PDT 24
Peak memory 206488 kb
Host smart-a355664f-3490-4bc3-b17a-9eb5c752868a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051032275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1051032275
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2630009692
Short name T1049
Test name
Test status
Simulation time 20343221 ps
CPU time 0.84 seconds
Started Jul 26 05:41:17 PM PDT 24
Finished Jul 26 05:41:18 PM PDT 24
Peak memory 206248 kb
Host smart-025fcd11-1e85-4937-8dc4-8939f4b7605e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630009692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2630009692
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.838531051
Short name T1080
Test name
Test status
Simulation time 54668724 ps
CPU time 1.08 seconds
Started Jul 26 05:41:16 PM PDT 24
Finished Jul 26 05:41:17 PM PDT 24
Peak memory 216148 kb
Host smart-072d29e4-7af2-43e9-91af-34eacb7c928e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838531051 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.838531051
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1585154735
Short name T1046
Test name
Test status
Simulation time 15970979 ps
CPU time 0.9 seconds
Started Jul 26 05:41:22 PM PDT 24
Finished Jul 26 05:41:23 PM PDT 24
Peak memory 206384 kb
Host smart-1241ce60-9be0-4021-adb0-c223dfbbaad0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585154735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1585154735
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1475762558
Short name T1065
Test name
Test status
Simulation time 72763762 ps
CPU time 0.9 seconds
Started Jul 26 05:41:16 PM PDT 24
Finished Jul 26 05:41:17 PM PDT 24
Peak memory 206240 kb
Host smart-3eb27657-cb07-405e-9f9e-6337111743c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475762558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1475762558
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.401797919
Short name T1085
Test name
Test status
Simulation time 259762098 ps
CPU time 1.5 seconds
Started Jul 26 05:41:22 PM PDT 24
Finished Jul 26 05:41:23 PM PDT 24
Peak memory 206572 kb
Host smart-f521e6d0-c9bf-4d45-9c17-1db21745cd9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401797919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.401797919
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3183198595
Short name T1006
Test name
Test status
Simulation time 199517750 ps
CPU time 2.76 seconds
Started Jul 26 05:41:17 PM PDT 24
Finished Jul 26 05:41:20 PM PDT 24
Peak memory 214776 kb
Host smart-549b1963-0c45-45c8-a6da-0c3a5e0ecafb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183198595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3183198595
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2264393061
Short name T298
Test name
Test status
Simulation time 98757168 ps
CPU time 2.63 seconds
Started Jul 26 05:41:26 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 206596 kb
Host smart-fe66d254-e851-45f1-a662-1461f48f0816
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264393061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2264393061
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.503329451
Short name T1005
Test name
Test status
Simulation time 20339550 ps
CPU time 0.86 seconds
Started Jul 26 05:41:50 PM PDT 24
Finished Jul 26 05:41:51 PM PDT 24
Peak memory 206464 kb
Host smart-c0cf5a07-3048-4668-b361-14ec2fa14b5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503329451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.503329451
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.94912736
Short name T1105
Test name
Test status
Simulation time 18541482 ps
CPU time 0.79 seconds
Started Jul 26 05:41:38 PM PDT 24
Finished Jul 26 05:41:39 PM PDT 24
Peak memory 206296 kb
Host smart-94720c0d-f619-4986-b48f-fe5ccdcd8762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94912736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.94912736
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3201907450
Short name T1087
Test name
Test status
Simulation time 19106379 ps
CPU time 0.81 seconds
Started Jul 26 05:41:40 PM PDT 24
Finished Jul 26 05:41:41 PM PDT 24
Peak memory 206260 kb
Host smart-d25b55cb-7e77-4907-8347-e076060f0a86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201907450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3201907450
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2063625045
Short name T1060
Test name
Test status
Simulation time 11606266 ps
CPU time 0.81 seconds
Started Jul 26 05:41:39 PM PDT 24
Finished Jul 26 05:41:40 PM PDT 24
Peak memory 206428 kb
Host smart-f8a75ec5-d968-4667-9556-13d03c39bd4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063625045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2063625045
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.217278608
Short name T1043
Test name
Test status
Simulation time 29345529 ps
CPU time 0.91 seconds
Started Jul 26 05:41:41 PM PDT 24
Finished Jul 26 05:41:42 PM PDT 24
Peak memory 206480 kb
Host smart-e3a49955-b01e-4bf2-9433-36ba93452d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217278608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.217278608
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2002434456
Short name T1040
Test name
Test status
Simulation time 24674226 ps
CPU time 0.84 seconds
Started Jul 26 05:41:56 PM PDT 24
Finished Jul 26 05:41:57 PM PDT 24
Peak memory 206452 kb
Host smart-c4295232-074f-48a8-a7a0-e5e1cbe89fa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002434456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2002434456
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.4138900593
Short name T1042
Test name
Test status
Simulation time 12106548 ps
CPU time 0.89 seconds
Started Jul 26 05:41:41 PM PDT 24
Finished Jul 26 05:41:42 PM PDT 24
Peak memory 206380 kb
Host smart-70fa4a20-dfda-4d7a-9624-c6edc6f8d565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138900593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.4138900593
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.653477541
Short name T1061
Test name
Test status
Simulation time 15149241 ps
CPU time 0.88 seconds
Started Jul 26 05:41:39 PM PDT 24
Finished Jul 26 05:41:40 PM PDT 24
Peak memory 206424 kb
Host smart-29e3e273-4f5d-4168-8687-0836d5e9cb22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653477541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.653477541
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2398965579
Short name T1020
Test name
Test status
Simulation time 15031998 ps
CPU time 1 seconds
Started Jul 26 05:41:44 PM PDT 24
Finished Jul 26 05:41:46 PM PDT 24
Peak memory 206484 kb
Host smart-794ba4cd-a55d-4a4e-953d-467af1752a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398965579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2398965579
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.196161298
Short name T1015
Test name
Test status
Simulation time 38127924 ps
CPU time 0.88 seconds
Started Jul 26 05:41:57 PM PDT 24
Finished Jul 26 05:41:58 PM PDT 24
Peak memory 206460 kb
Host smart-45154276-4cec-42ad-b970-4e63476b8053
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196161298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.196161298
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3890488624
Short name T1108
Test name
Test status
Simulation time 45838796 ps
CPU time 1.17 seconds
Started Jul 26 05:41:16 PM PDT 24
Finished Jul 26 05:41:17 PM PDT 24
Peak memory 214796 kb
Host smart-c09ea737-a7c5-46ab-bce6-e6086ce5ce15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890488624 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3890488624
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3624435742
Short name T273
Test name
Test status
Simulation time 50290759 ps
CPU time 0.9 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:21 PM PDT 24
Peak memory 206476 kb
Host smart-63946a93-9d16-41ad-a5c3-0db4f57cc3d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624435742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3624435742
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1764731985
Short name T1106
Test name
Test status
Simulation time 65464827 ps
CPU time 0.85 seconds
Started Jul 26 05:41:21 PM PDT 24
Finished Jul 26 05:41:22 PM PDT 24
Peak memory 206260 kb
Host smart-5da8ed2e-c2de-4936-ad38-183ae4d62b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764731985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1764731985
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.55366673
Short name T255
Test name
Test status
Simulation time 257545355 ps
CPU time 1.24 seconds
Started Jul 26 05:41:14 PM PDT 24
Finished Jul 26 05:41:15 PM PDT 24
Peak memory 206520 kb
Host smart-0c5714db-62ee-47d4-bfeb-5060893056b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55366673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outs
tanding.55366673
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2716050864
Short name T1030
Test name
Test status
Simulation time 160497673 ps
CPU time 3.68 seconds
Started Jul 26 05:41:22 PM PDT 24
Finished Jul 26 05:41:26 PM PDT 24
Peak memory 214844 kb
Host smart-3faf01ca-b399-4e8f-a973-529c8f8cfe1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716050864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2716050864
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2387387288
Short name T1039
Test name
Test status
Simulation time 153429239 ps
CPU time 3.57 seconds
Started Jul 26 05:41:22 PM PDT 24
Finished Jul 26 05:41:25 PM PDT 24
Peak memory 206664 kb
Host smart-cf3ed9db-29df-4b92-923c-9789141a21bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387387288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2387387288
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1517196028
Short name T1000
Test name
Test status
Simulation time 26136171 ps
CPU time 1.31 seconds
Started Jul 26 05:41:18 PM PDT 24
Finished Jul 26 05:41:19 PM PDT 24
Peak memory 214948 kb
Host smart-e07c120d-011c-46fe-a730-8b5faf0af5ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517196028 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1517196028
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.775439751
Short name T260
Test name
Test status
Simulation time 148777954 ps
CPU time 0.87 seconds
Started Jul 26 05:41:19 PM PDT 24
Finished Jul 26 05:41:20 PM PDT 24
Peak memory 206288 kb
Host smart-3b79baac-5279-4b63-8e93-2ba0f3182c8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775439751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.775439751
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3749411253
Short name T1109
Test name
Test status
Simulation time 55323215 ps
CPU time 0.92 seconds
Started Jul 26 05:41:22 PM PDT 24
Finished Jul 26 05:41:23 PM PDT 24
Peak memory 206388 kb
Host smart-d7851566-fe1e-4085-98e8-b4cdeb2bb062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749411253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3749411253
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4021398468
Short name T275
Test name
Test status
Simulation time 43238083 ps
CPU time 1.08 seconds
Started Jul 26 05:41:19 PM PDT 24
Finished Jul 26 05:41:21 PM PDT 24
Peak memory 206540 kb
Host smart-f047bdfc-d7cc-4c7d-a91c-366ed673a46b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021398468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.4021398468
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1716929341
Short name T1095
Test name
Test status
Simulation time 66788059 ps
CPU time 1.48 seconds
Started Jul 26 05:41:24 PM PDT 24
Finished Jul 26 05:41:25 PM PDT 24
Peak memory 214932 kb
Host smart-3b7b1dc9-68a4-43ea-9e84-11a5b2995384
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716929341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1716929341
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.869892341
Short name T1116
Test name
Test status
Simulation time 320206272 ps
CPU time 1.71 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:22 PM PDT 24
Peak memory 214764 kb
Host smart-ee777fbc-cdd2-44f9-8a59-0dd4dc91822f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869892341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.869892341
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.51895958
Short name T1115
Test name
Test status
Simulation time 85952070 ps
CPU time 1.47 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 214820 kb
Host smart-b3c89a9b-9e59-4c46-8419-29eb97710d20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51895958 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.51895958
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2702052980
Short name T1121
Test name
Test status
Simulation time 28111975 ps
CPU time 0.89 seconds
Started Jul 26 05:41:16 PM PDT 24
Finished Jul 26 05:41:17 PM PDT 24
Peak memory 206328 kb
Host smart-75eb44c4-bb9c-4d4e-8718-21d43033e21c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702052980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2702052980
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.511593914
Short name T1054
Test name
Test status
Simulation time 121365830 ps
CPU time 0.81 seconds
Started Jul 26 05:41:18 PM PDT 24
Finished Jul 26 05:41:19 PM PDT 24
Peak memory 206472 kb
Host smart-49232ffb-aac0-4f67-a4f7-04d8b2666605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511593914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.511593914
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1653969193
Short name T276
Test name
Test status
Simulation time 31844813 ps
CPU time 1.34 seconds
Started Jul 26 05:41:36 PM PDT 24
Finished Jul 26 05:41:37 PM PDT 24
Peak memory 206640 kb
Host smart-bc49b250-76e7-4cd1-b4ff-d3db68234662
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653969193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1653969193
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1874519350
Short name T1013
Test name
Test status
Simulation time 34568923 ps
CPU time 1.59 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:22 PM PDT 24
Peak memory 214900 kb
Host smart-fd80ae0e-1f25-4919-b535-4e4969097046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874519350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1874519350
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1745481102
Short name T294
Test name
Test status
Simulation time 285883203 ps
CPU time 2.49 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:22 PM PDT 24
Peak memory 206560 kb
Host smart-253b013f-cac0-4d81-b46b-41dda258dca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745481102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1745481102
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.13762766
Short name T1055
Test name
Test status
Simulation time 128498235 ps
CPU time 1.59 seconds
Started Jul 26 05:41:26 PM PDT 24
Finished Jul 26 05:41:28 PM PDT 24
Peak memory 214916 kb
Host smart-36c3160c-e701-4c40-8c32-17e7d5bc129d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13762766 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.13762766
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2743417746
Short name T271
Test name
Test status
Simulation time 12158235 ps
CPU time 0.89 seconds
Started Jul 26 05:41:26 PM PDT 24
Finished Jul 26 05:41:27 PM PDT 24
Peak memory 206468 kb
Host smart-f96977d4-08d0-4c5d-b5fb-ec4ee1e617c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743417746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2743417746
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2882766609
Short name T1002
Test name
Test status
Simulation time 28515528 ps
CPU time 0.9 seconds
Started Jul 26 05:41:24 PM PDT 24
Finished Jul 26 05:41:25 PM PDT 24
Peak memory 206464 kb
Host smart-da334049-e67e-45a9-bf6a-a05aaeab3d05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882766609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2882766609
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1059277874
Short name T1083
Test name
Test status
Simulation time 44286570 ps
CPU time 1.13 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:22 PM PDT 24
Peak memory 206580 kb
Host smart-43149914-01fe-4245-9469-ee1b710cbc14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059277874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1059277874
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1516781770
Short name T1044
Test name
Test status
Simulation time 87412074 ps
CPU time 3.3 seconds
Started Jul 26 05:41:23 PM PDT 24
Finished Jul 26 05:41:27 PM PDT 24
Peak memory 214916 kb
Host smart-843a8b41-7ea8-469c-8a58-5115502a7a98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516781770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1516781770
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.303372918
Short name T299
Test name
Test status
Simulation time 121285450 ps
CPU time 1.5 seconds
Started Jul 26 05:41:26 PM PDT 24
Finished Jul 26 05:41:27 PM PDT 24
Peak memory 206668 kb
Host smart-9804bc53-a02f-47e8-a458-175b267e00cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303372918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.303372918
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.897966058
Short name T1079
Test name
Test status
Simulation time 122054243 ps
CPU time 1.78 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:30 PM PDT 24
Peak memory 214740 kb
Host smart-cc817512-c8d8-4056-9971-e7f48bb7a615
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897966058 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.897966058
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1978424041
Short name T262
Test name
Test status
Simulation time 48455004 ps
CPU time 0.92 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 206340 kb
Host smart-32934b60-5585-43d4-8a05-5007b407ecd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978424041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1978424041
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3923908917
Short name T1027
Test name
Test status
Simulation time 44112235 ps
CPU time 0.84 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:21 PM PDT 24
Peak memory 206448 kb
Host smart-373194eb-048c-42db-8712-4e734e9612dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923908917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3923908917
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1953472718
Short name T274
Test name
Test status
Simulation time 18149168 ps
CPU time 0.95 seconds
Started Jul 26 05:41:27 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 206464 kb
Host smart-673d6bfb-ea86-4278-b27d-9b86a4aee944
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953472718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1953472718
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4038232887
Short name T1084
Test name
Test status
Simulation time 356243313 ps
CPU time 2.21 seconds
Started Jul 26 05:41:28 PM PDT 24
Finished Jul 26 05:41:30 PM PDT 24
Peak memory 222992 kb
Host smart-61d979e2-b35c-4ba6-8ec2-ebc57f29b7c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038232887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4038232887
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3114763731
Short name T1071
Test name
Test status
Simulation time 48781558 ps
CPU time 1.56 seconds
Started Jul 26 05:41:27 PM PDT 24
Finished Jul 26 05:41:29 PM PDT 24
Peak memory 206460 kb
Host smart-4490b3e4-daa5-464f-9153-8ff9dcc0b31f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114763731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3114763731
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3339589906
Short name T738
Test name
Test status
Simulation time 141941918 ps
CPU time 1.2 seconds
Started Jul 26 05:42:09 PM PDT 24
Finished Jul 26 05:42:11 PM PDT 24
Peak memory 220312 kb
Host smart-449fe2aa-c7a8-4902-bd6e-21d7096cc6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339589906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3339589906
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1630273931
Short name T481
Test name
Test status
Simulation time 38400883 ps
CPU time 0.88 seconds
Started Jul 26 05:42:11 PM PDT 24
Finished Jul 26 05:42:12 PM PDT 24
Peak memory 215052 kb
Host smart-6c5ea627-f7e9-47a3-bbfe-bdd2782aea36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630273931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1630273931
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.4224108030
Short name T687
Test name
Test status
Simulation time 27557350 ps
CPU time 0.84 seconds
Started Jul 26 05:42:12 PM PDT 24
Finished Jul 26 05:42:13 PM PDT 24
Peak memory 216016 kb
Host smart-2658dd2a-3a5f-42dc-b44a-4d6f935fa342
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224108030 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.4224108030
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3156746318
Short name T885
Test name
Test status
Simulation time 35824147 ps
CPU time 1.24 seconds
Started Jul 26 05:42:15 PM PDT 24
Finished Jul 26 05:42:16 PM PDT 24
Peak memory 218304 kb
Host smart-f045ded6-c7bd-4cb5-9726-892f58b19cba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156746318 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3156746318
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.3988231221
Short name T182
Test name
Test status
Simulation time 77318414 ps
CPU time 1.22 seconds
Started Jul 26 05:42:09 PM PDT 24
Finished Jul 26 05:42:11 PM PDT 24
Peak memory 225716 kb
Host smart-010ca0c6-7311-4b8e-a9ef-a3e6f0563eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988231221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3988231221
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1362253748
Short name T495
Test name
Test status
Simulation time 84172837 ps
CPU time 1.11 seconds
Started Jul 26 05:42:18 PM PDT 24
Finished Jul 26 05:42:20 PM PDT 24
Peak memory 219720 kb
Host smart-8126b684-5fdd-4a54-a97a-13f6ef1aaf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362253748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1362253748
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.3552380405
Short name T928
Test name
Test status
Simulation time 20610112 ps
CPU time 1 seconds
Started Jul 26 05:42:20 PM PDT 24
Finished Jul 26 05:42:21 PM PDT 24
Peak memory 206880 kb
Host smart-f1cf87e7-9d04-4853-861c-89ad10b9e9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552380405 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3552380405
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.2999018547
Short name T354
Test name
Test status
Simulation time 84131103 ps
CPU time 0.94 seconds
Started Jul 26 05:42:11 PM PDT 24
Finished Jul 26 05:42:12 PM PDT 24
Peak memory 215140 kb
Host smart-956f0bb6-d1fc-4b3b-9be1-33044d17eda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999018547 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2999018547
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.4165245632
Short name T913
Test name
Test status
Simulation time 229497255 ps
CPU time 4.3 seconds
Started Jul 26 05:42:17 PM PDT 24
Finished Jul 26 05:42:21 PM PDT 24
Peak memory 217176 kb
Host smart-a22864b9-03b3-46fe-8d15-570a4f0fb720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165245632 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.4165245632
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1387593448
Short name T884
Test name
Test status
Simulation time 539761636788 ps
CPU time 3303.57 seconds
Started Jul 26 05:42:16 PM PDT 24
Finished Jul 26 06:37:20 PM PDT 24
Peak memory 236364 kb
Host smart-5746a563-af76-46d3-b6dd-14afb5e3740f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387593448 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1387593448
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_disable.3718448790
Short name T993
Test name
Test status
Simulation time 22286192 ps
CPU time 0.87 seconds
Started Jul 26 05:42:11 PM PDT 24
Finished Jul 26 05:42:12 PM PDT 24
Peak memory 216076 kb
Host smart-cd128bce-8f9d-4914-9405-1945edfa839c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718448790 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3718448790
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_intr.798276345
Short name T63
Test name
Test status
Simulation time 38639121 ps
CPU time 0.87 seconds
Started Jul 26 05:42:20 PM PDT 24
Finished Jul 26 05:42:21 PM PDT 24
Peak memory 215264 kb
Host smart-59f05d0e-a44b-47ea-bbe5-a9d433fe8a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798276345 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.798276345
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.4158916169
Short name T338
Test name
Test status
Simulation time 31090633 ps
CPU time 1.01 seconds
Started Jul 26 05:42:20 PM PDT 24
Finished Jul 26 05:42:21 PM PDT 24
Peak memory 206828 kb
Host smart-f1f84140-b31d-4723-b25e-51b49f5409cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158916169 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.4158916169
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.1625343379
Short name T645
Test name
Test status
Simulation time 15627231 ps
CPU time 0.95 seconds
Started Jul 26 05:42:20 PM PDT 24
Finished Jul 26 05:42:21 PM PDT 24
Peak memory 215076 kb
Host smart-c36eecb6-c1ea-4076-9e9f-429deff69535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625343379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1625343379
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3769884066
Short name T804
Test name
Test status
Simulation time 99476984 ps
CPU time 1.66 seconds
Started Jul 26 05:42:19 PM PDT 24
Finished Jul 26 05:42:21 PM PDT 24
Peak memory 219776 kb
Host smart-9818d676-b1cc-43ef-9581-474e8e1199d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769884066 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3769884066
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3254799856
Short name T234
Test name
Test status
Simulation time 218630222433 ps
CPU time 1252.26 seconds
Started Jul 26 05:42:12 PM PDT 24
Finished Jul 26 06:03:04 PM PDT 24
Peak memory 223624 kb
Host smart-75c6cf6f-9942-4682-ab4e-6c62aaf14dc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254799856 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3254799856
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2771153934
Short name T532
Test name
Test status
Simulation time 74705534 ps
CPU time 1.08 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 05:42:42 PM PDT 24
Peak memory 218152 kb
Host smart-b16ea658-0efe-4311-8339-640b666fc2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771153934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2771153934
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2412435214
Short name T855
Test name
Test status
Simulation time 50163502 ps
CPU time 0.89 seconds
Started Jul 26 05:42:36 PM PDT 24
Finished Jul 26 05:42:37 PM PDT 24
Peak memory 206548 kb
Host smart-52f0e787-2c57-4f86-9724-1896c1370178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412435214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2412435214
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.674240248
Short name T126
Test name
Test status
Simulation time 11999954 ps
CPU time 0.94 seconds
Started Jul 26 05:42:40 PM PDT 24
Finished Jul 26 05:42:41 PM PDT 24
Peak memory 215440 kb
Host smart-de3d3158-bc29-4fa9-8414-bebfb7cad93a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674240248 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.674240248
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.2334333717
Short name T148
Test name
Test status
Simulation time 40575370 ps
CPU time 1.01 seconds
Started Jul 26 05:42:43 PM PDT 24
Finished Jul 26 05:42:44 PM PDT 24
Peak memory 219428 kb
Host smart-07d1cc59-7db5-4677-89ff-c81b7d54d1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334333717 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2334333717
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1355975129
Short name T709
Test name
Test status
Simulation time 67912946 ps
CPU time 1.37 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 05:42:42 PM PDT 24
Peak memory 218900 kb
Host smart-d7eea203-34da-47f9-b1a9-a04f9e21b2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355975129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1355975129
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2557607817
Short name T89
Test name
Test status
Simulation time 24155338 ps
CPU time 0.95 seconds
Started Jul 26 05:42:40 PM PDT 24
Finished Jul 26 05:42:41 PM PDT 24
Peak memory 215872 kb
Host smart-9e22ed20-5cb7-444a-9ad0-e1d286856cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557607817 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2557607817
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2027084358
Short name T397
Test name
Test status
Simulation time 96046512 ps
CPU time 0.92 seconds
Started Jul 26 05:42:31 PM PDT 24
Finished Jul 26 05:42:32 PM PDT 24
Peak memory 215044 kb
Host smart-c4212110-1295-4e5b-b406-289a0222e341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027084358 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2027084358
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3858081189
Short name T430
Test name
Test status
Simulation time 178621634 ps
CPU time 3.84 seconds
Started Jul 26 05:42:44 PM PDT 24
Finished Jul 26 05:42:48 PM PDT 24
Peak memory 217132 kb
Host smart-98cf480c-518b-4757-ae07-e11cecf823b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858081189 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3858081189
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.792890483
Short name T538
Test name
Test status
Simulation time 369808023776 ps
CPU time 1175.94 seconds
Started Jul 26 05:42:44 PM PDT 24
Finished Jul 26 06:02:20 PM PDT 24
Peak memory 232240 kb
Host smart-3a2b9884-d4e4-4a8b-9028-372a55d9e47c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792890483 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.792890483
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.4116635789
Short name T343
Test name
Test status
Simulation time 75207088 ps
CPU time 1.12 seconds
Started Jul 26 05:43:54 PM PDT 24
Finished Jul 26 05:43:56 PM PDT 24
Peak memory 220612 kb
Host smart-8d8e34cc-d54c-4b75-8035-2ee58a82ba57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116635789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.4116635789
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.3566068362
Short name T499
Test name
Test status
Simulation time 72576492 ps
CPU time 1.51 seconds
Started Jul 26 05:44:04 PM PDT 24
Finished Jul 26 05:44:06 PM PDT 24
Peak memory 218424 kb
Host smart-6f31be0b-a8c0-422a-955f-62627d95099f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566068362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3566068362
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.4222638849
Short name T630
Test name
Test status
Simulation time 85140283 ps
CPU time 1.17 seconds
Started Jul 26 05:44:03 PM PDT 24
Finished Jul 26 05:44:04 PM PDT 24
Peak memory 218768 kb
Host smart-3c59e784-cede-48e0-bd63-9919e1fcaec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222638849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.4222638849
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.3221100278
Short name T583
Test name
Test status
Simulation time 98428826 ps
CPU time 1.23 seconds
Started Jul 26 05:43:53 PM PDT 24
Finished Jul 26 05:43:54 PM PDT 24
Peak memory 218320 kb
Host smart-6300feb2-8c58-4eb2-9281-b2effb9e5c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221100278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3221100278
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.1839517479
Short name T811
Test name
Test status
Simulation time 46012425 ps
CPU time 1.22 seconds
Started Jul 26 05:43:59 PM PDT 24
Finished Jul 26 05:44:01 PM PDT 24
Peak memory 218388 kb
Host smart-6654e070-1d82-412b-be8c-8fe2bda3d615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839517479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1839517479
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2980624888
Short name T358
Test name
Test status
Simulation time 25095607 ps
CPU time 1.09 seconds
Started Jul 26 05:44:08 PM PDT 24
Finished Jul 26 05:44:09 PM PDT 24
Peak memory 217244 kb
Host smart-c6f2ccf3-25af-41e2-a4dd-53bd27f09940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980624888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2980624888
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.1292197665
Short name T945
Test name
Test status
Simulation time 24281275 ps
CPU time 1.24 seconds
Started Jul 26 05:43:58 PM PDT 24
Finished Jul 26 05:43:59 PM PDT 24
Peak memory 218440 kb
Host smart-2879c71c-be3f-4b94-8424-46a149bc7a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292197665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1292197665
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.1108059110
Short name T595
Test name
Test status
Simulation time 131330251 ps
CPU time 1.31 seconds
Started Jul 26 05:44:06 PM PDT 24
Finished Jul 26 05:44:07 PM PDT 24
Peak memory 218708 kb
Host smart-61141ef0-377b-462b-8633-900c320aa859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108059110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1108059110
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.3206417967
Short name T473
Test name
Test status
Simulation time 72237183 ps
CPU time 1.14 seconds
Started Jul 26 05:43:53 PM PDT 24
Finished Jul 26 05:43:54 PM PDT 24
Peak memory 218772 kb
Host smart-2ac46c43-fb88-4f70-9bd6-84670b461b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206417967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.3206417967
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.1861317570
Short name T633
Test name
Test status
Simulation time 41155253 ps
CPU time 1.11 seconds
Started Jul 26 05:44:08 PM PDT 24
Finished Jul 26 05:44:09 PM PDT 24
Peak memory 219812 kb
Host smart-4388e75a-c9cd-4a86-b581-fe688f1dce77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861317570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1861317570
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.2443792438
Short name T946
Test name
Test status
Simulation time 30360106 ps
CPU time 1.09 seconds
Started Jul 26 05:43:53 PM PDT 24
Finished Jul 26 05:43:54 PM PDT 24
Peak memory 218688 kb
Host smart-97cb70d3-2521-4428-a362-e7dfbc6bc9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443792438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.2443792438
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.2307301749
Short name T926
Test name
Test status
Simulation time 89357862 ps
CPU time 1.05 seconds
Started Jul 26 05:44:04 PM PDT 24
Finished Jul 26 05:44:05 PM PDT 24
Peak memory 217316 kb
Host smart-1eaee520-41c0-432c-80cd-f6fcb7016f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307301749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2307301749
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.1188284309
Short name T619
Test name
Test status
Simulation time 115485034 ps
CPU time 1.15 seconds
Started Jul 26 05:44:04 PM PDT 24
Finished Jul 26 05:44:05 PM PDT 24
Peak memory 219436 kb
Host smart-41c8aa80-f6e4-49e2-9bd1-3f14e9b781ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188284309 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.1188284309
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.1865966814
Short name T703
Test name
Test status
Simulation time 69932939 ps
CPU time 1.03 seconds
Started Jul 26 05:44:08 PM PDT 24
Finished Jul 26 05:44:09 PM PDT 24
Peak memory 219040 kb
Host smart-3b2de4c4-440d-4d4b-909a-539a473f3299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865966814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1865966814
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.2359034116
Short name T991
Test name
Test status
Simulation time 43780674 ps
CPU time 1.06 seconds
Started Jul 26 05:44:00 PM PDT 24
Finished Jul 26 05:44:01 PM PDT 24
Peak memory 219276 kb
Host smart-833e0b6f-0c54-4615-8de3-84838b398815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359034116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2359034116
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.1357793980
Short name T404
Test name
Test status
Simulation time 65375555 ps
CPU time 1.33 seconds
Started Jul 26 05:44:03 PM PDT 24
Finished Jul 26 05:44:04 PM PDT 24
Peak memory 219256 kb
Host smart-73459e84-580b-4bc0-8c43-e512e27a2932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357793980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1357793980
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.4037530700
Short name T766
Test name
Test status
Simulation time 63739837 ps
CPU time 1.02 seconds
Started Jul 26 05:44:11 PM PDT 24
Finished Jul 26 05:44:12 PM PDT 24
Peak memory 220516 kb
Host smart-469b35d2-547f-4256-9b24-fb9946b146dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037530700 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.4037530700
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.1002062826
Short name T26
Test name
Test status
Simulation time 57972211 ps
CPU time 1.43 seconds
Started Jul 26 05:44:02 PM PDT 24
Finished Jul 26 05:44:04 PM PDT 24
Peak memory 218848 kb
Host smart-2d022183-bbe2-4e76-b6ee-53b3403249f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002062826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1002062826
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.2445771849
Short name T34
Test name
Test status
Simulation time 111540928 ps
CPU time 1.37 seconds
Started Jul 26 05:43:55 PM PDT 24
Finished Jul 26 05:43:57 PM PDT 24
Peak memory 218548 kb
Host smart-ed078c30-2598-4997-82d2-ff712ea072af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445771849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2445771849
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.3089943598
Short name T405
Test name
Test status
Simulation time 20124438 ps
CPU time 1.01 seconds
Started Jul 26 05:42:35 PM PDT 24
Finished Jul 26 05:42:36 PM PDT 24
Peak memory 214764 kb
Host smart-db71efe9-85f5-485b-b3c1-29047954226a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089943598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3089943598
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1010498978
Short name T749
Test name
Test status
Simulation time 31353497 ps
CPU time 1.06 seconds
Started Jul 26 05:42:34 PM PDT 24
Finished Jul 26 05:42:35 PM PDT 24
Peak memory 218296 kb
Host smart-2ebe79f2-cd11-4ad3-9bb8-af753fe3acb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010498978 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1010498978
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.734185735
Short name T894
Test name
Test status
Simulation time 44721812 ps
CPU time 1.14 seconds
Started Jul 26 05:42:39 PM PDT 24
Finished Jul 26 05:42:40 PM PDT 24
Peak memory 215404 kb
Host smart-4054c356-fb45-45bc-8b24-d6816239aa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734185735 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.734185735
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2189953978
Short name T555
Test name
Test status
Simulation time 64444709 ps
CPU time 1.12 seconds
Started Jul 26 05:42:43 PM PDT 24
Finished Jul 26 05:42:44 PM PDT 24
Peak memory 217112 kb
Host smart-154804c1-c568-4ffe-a5d4-9cff18cdd8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189953978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2189953978
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.2900464342
Short name T577
Test name
Test status
Simulation time 15135197 ps
CPU time 0.99 seconds
Started Jul 26 05:42:42 PM PDT 24
Finished Jul 26 05:42:43 PM PDT 24
Peak memory 215144 kb
Host smart-71b07aba-331c-4cf3-a362-5b4fab918ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900464342 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2900464342
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.489009215
Short name T590
Test name
Test status
Simulation time 166988848 ps
CPU time 3.6 seconds
Started Jul 26 05:42:43 PM PDT 24
Finished Jul 26 05:42:47 PM PDT 24
Peak memory 215140 kb
Host smart-a0a2aeec-b178-4d1b-ac6e-ce592b27dd9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489009215 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.489009215
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1317648525
Short name T729
Test name
Test status
Simulation time 148969404930 ps
CPU time 1100.34 seconds
Started Jul 26 05:42:37 PM PDT 24
Finished Jul 26 06:00:58 PM PDT 24
Peak memory 224596 kb
Host smart-aef2d9a2-be61-4152-9b60-46323bc52603
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317648525 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1317648525
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.3475351573
Short name T24
Test name
Test status
Simulation time 74917359 ps
CPU time 1.19 seconds
Started Jul 26 05:43:52 PM PDT 24
Finished Jul 26 05:43:53 PM PDT 24
Peak memory 218612 kb
Host smart-50fd852e-8ed2-4dd2-9979-d62809d67745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475351573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3475351573
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.2846494964
Short name T936
Test name
Test status
Simulation time 23556603 ps
CPU time 1.21 seconds
Started Jul 26 05:44:02 PM PDT 24
Finished Jul 26 05:44:04 PM PDT 24
Peak memory 218600 kb
Host smart-84b28141-72c2-4258-a7a4-85f1b234f006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846494964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2846494964
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.1846491800
Short name T727
Test name
Test status
Simulation time 46762925 ps
CPU time 1.47 seconds
Started Jul 26 05:43:58 PM PDT 24
Finished Jul 26 05:44:00 PM PDT 24
Peak memory 218484 kb
Host smart-6f183b11-c34f-4fa4-bab9-41d7dcbc16d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846491800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1846491800
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.710889528
Short name T158
Test name
Test status
Simulation time 51706667 ps
CPU time 1.08 seconds
Started Jul 26 05:43:56 PM PDT 24
Finished Jul 26 05:43:57 PM PDT 24
Peak memory 219628 kb
Host smart-8aa9833d-1a42-43a1-9d9d-bd41fa8a14b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710889528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.710889528
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.2378887896
Short name T399
Test name
Test status
Simulation time 34449872 ps
CPU time 1.38 seconds
Started Jul 26 05:43:56 PM PDT 24
Finished Jul 26 05:43:57 PM PDT 24
Peak memory 218300 kb
Host smart-c3b4ca4a-580f-4969-8647-c19839011d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378887896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2378887896
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2888600458
Short name T451
Test name
Test status
Simulation time 86320113 ps
CPU time 1.11 seconds
Started Jul 26 05:44:09 PM PDT 24
Finished Jul 26 05:44:10 PM PDT 24
Peak memory 219428 kb
Host smart-d124cddb-17fe-4761-882b-49bd66e5197e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888600458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2888600458
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.3890709477
Short name T863
Test name
Test status
Simulation time 40341790 ps
CPU time 1.35 seconds
Started Jul 26 05:44:21 PM PDT 24
Finished Jul 26 05:44:23 PM PDT 24
Peak memory 218436 kb
Host smart-5a40ca54-c44e-45f2-849f-1b52d46f42b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890709477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3890709477
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3648947390
Short name T857
Test name
Test status
Simulation time 141289726 ps
CPU time 3.07 seconds
Started Jul 26 05:44:16 PM PDT 24
Finished Jul 26 05:44:19 PM PDT 24
Peak memory 217368 kb
Host smart-8b3dd473-185a-441c-827a-e79824327a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648947390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3648947390
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.1306313056
Short name T448
Test name
Test status
Simulation time 38035152 ps
CPU time 1.19 seconds
Started Jul 26 05:44:00 PM PDT 24
Finished Jul 26 05:44:01 PM PDT 24
Peak memory 219476 kb
Host smart-afc1b0cf-65f6-483e-9c5d-80bc6c6eecf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306313056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.1306313056
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3529189880
Short name T378
Test name
Test status
Simulation time 30132815 ps
CPU time 1.2 seconds
Started Jul 26 05:43:55 PM PDT 24
Finished Jul 26 05:43:56 PM PDT 24
Peak memory 218392 kb
Host smart-86ef1cbd-44b6-4f20-90a9-fe896aa7b5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529189880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3529189880
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1954386559
Short name T167
Test name
Test status
Simulation time 25439898 ps
CPU time 1.14 seconds
Started Jul 26 05:43:58 PM PDT 24
Finished Jul 26 05:43:59 PM PDT 24
Peak memory 220680 kb
Host smart-cdf1d720-f23e-42d9-9dc0-0b1fbb63a0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954386559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1954386559
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/117.edn_alert.119766137
Short name T39
Test name
Test status
Simulation time 60898443 ps
CPU time 1.17 seconds
Started Jul 26 05:44:00 PM PDT 24
Finished Jul 26 05:44:01 PM PDT 24
Peak memory 219392 kb
Host smart-ab3b4f67-c6c3-4c4d-b212-7f8ec473e58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119766137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.119766137
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.3960013224
Short name T447
Test name
Test status
Simulation time 33539103 ps
CPU time 1.42 seconds
Started Jul 26 05:43:59 PM PDT 24
Finished Jul 26 05:44:01 PM PDT 24
Peak memory 219608 kb
Host smart-5ccfe049-1f85-4ce2-a5ef-3bf7cb2d4ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960013224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3960013224
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.3795444967
Short name T152
Test name
Test status
Simulation time 89284822 ps
CPU time 1.1 seconds
Started Jul 26 05:44:04 PM PDT 24
Finished Jul 26 05:44:05 PM PDT 24
Peak memory 219512 kb
Host smart-c3d2228a-6b5b-4855-b72a-9efdcf5b44c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795444967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.3795444967
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.1155957549
Short name T289
Test name
Test status
Simulation time 91848237 ps
CPU time 1.23 seconds
Started Jul 26 05:44:00 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 217156 kb
Host smart-850ff8d9-0558-48fd-91c8-10a63674dce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155957549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1155957549
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1303458033
Short name T306
Test name
Test status
Simulation time 24793054 ps
CPU time 1.17 seconds
Started Jul 26 05:43:58 PM PDT 24
Finished Jul 26 05:44:00 PM PDT 24
Peak memory 219688 kb
Host smart-ee6e0e35-9151-41a7-b430-00768947919f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303458033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1303458033
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3936294135
Short name T513
Test name
Test status
Simulation time 61873168 ps
CPU time 1.15 seconds
Started Jul 26 05:44:02 PM PDT 24
Finished Jul 26 05:44:04 PM PDT 24
Peak memory 217212 kb
Host smart-71a6570a-5d26-47d1-a7df-5ece18e1fc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936294135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3936294135
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3776927717
Short name T210
Test name
Test status
Simulation time 76188279 ps
CPU time 1.13 seconds
Started Jul 26 05:42:40 PM PDT 24
Finished Jul 26 05:42:41 PM PDT 24
Peak memory 220496 kb
Host smart-b831260b-4116-49bf-9024-fccb6c75c67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776927717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3776927717
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.989978064
Short name T494
Test name
Test status
Simulation time 29506361 ps
CPU time 0.9 seconds
Started Jul 26 05:42:38 PM PDT 24
Finished Jul 26 05:42:39 PM PDT 24
Peak memory 206628 kb
Host smart-1deac348-87f5-4cae-8011-2be46d67cff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989978064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.989978064
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2432573304
Short name T217
Test name
Test status
Simulation time 22525568 ps
CPU time 0.96 seconds
Started Jul 26 05:42:36 PM PDT 24
Finished Jul 26 05:42:37 PM PDT 24
Peak memory 216164 kb
Host smart-89b57305-65f1-42da-8bcf-2489a6e96d4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432573304 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2432573304
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.301108655
Short name T282
Test name
Test status
Simulation time 62108486 ps
CPU time 1.03 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 05:42:42 PM PDT 24
Peak memory 216704 kb
Host smart-6b8b7517-27c7-42c7-bde2-c0bb87e08950
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301108655 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.301108655
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3260692141
Short name T163
Test name
Test status
Simulation time 23859724 ps
CPU time 1.31 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 05:42:43 PM PDT 24
Peak memory 229540 kb
Host smart-05b87251-0f82-430e-b520-791aa54cd2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260692141 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3260692141
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2671295162
Short name T313
Test name
Test status
Simulation time 39304772 ps
CPU time 1.61 seconds
Started Jul 26 05:42:40 PM PDT 24
Finished Jul 26 05:42:42 PM PDT 24
Peak memory 218480 kb
Host smart-4fc926a7-1e15-49cb-a668-cfa3fa4f5441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671295162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2671295162
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.50624649
Short name T461
Test name
Test status
Simulation time 67650842 ps
CPU time 0.91 seconds
Started Jul 26 05:42:37 PM PDT 24
Finished Jul 26 05:42:38 PM PDT 24
Peak memory 215088 kb
Host smart-a379de84-b22f-43db-bff2-e106b07a411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50624649 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.50624649
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1549751519
Short name T662
Test name
Test status
Simulation time 349141472 ps
CPU time 6.25 seconds
Started Jul 26 05:42:39 PM PDT 24
Finished Jul 26 05:42:45 PM PDT 24
Peak memory 217088 kb
Host smart-4a1042aa-fd09-4eb2-b89a-bd4e4887932a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549751519 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1549751519
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3337690416
Short name T454
Test name
Test status
Simulation time 140560746714 ps
CPU time 818.05 seconds
Started Jul 26 05:42:39 PM PDT 24
Finished Jul 26 05:56:17 PM PDT 24
Peak memory 223580 kb
Host smart-5d8b63a1-a44b-4f43-a4df-04191384cba4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337690416 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3337690416
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.1319805831
Short name T823
Test name
Test status
Simulation time 37814824 ps
CPU time 1.16 seconds
Started Jul 26 05:43:57 PM PDT 24
Finished Jul 26 05:43:59 PM PDT 24
Peak memory 218368 kb
Host smart-2f66aefc-ee22-4232-9693-e6f15961576a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319805831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1319805831
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.720378133
Short name T967
Test name
Test status
Simulation time 45671855 ps
CPU time 1.56 seconds
Started Jul 26 05:44:03 PM PDT 24
Finished Jul 26 05:44:05 PM PDT 24
Peak memory 217404 kb
Host smart-2653bfa5-35e2-4ba9-b48a-b32fd8f097b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720378133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.720378133
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.1566532947
Short name T788
Test name
Test status
Simulation time 46366190 ps
CPU time 1.19 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 215560 kb
Host smart-6f4b0238-21c2-45e8-8e97-8a46b2b68cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566532947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1566532947
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.4194931203
Short name T814
Test name
Test status
Simulation time 70371302 ps
CPU time 1.25 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 217396 kb
Host smart-a5551302-85ec-4665-909d-b663fae247a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194931203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.4194931203
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.2214748232
Short name T974
Test name
Test status
Simulation time 54028724 ps
CPU time 1.22 seconds
Started Jul 26 05:43:56 PM PDT 24
Finished Jul 26 05:43:57 PM PDT 24
Peak memory 219156 kb
Host smart-f0fcd407-fd8f-4c08-a45e-e02a18bec3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214748232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2214748232
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.2026702452
Short name T488
Test name
Test status
Simulation time 98341168 ps
CPU time 1.21 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 218744 kb
Host smart-5ea009b0-48a8-48cd-a199-fe8b6c4783d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026702452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2026702452
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.1415645428
Short name T675
Test name
Test status
Simulation time 25499082 ps
CPU time 1.15 seconds
Started Jul 26 05:43:58 PM PDT 24
Finished Jul 26 05:44:00 PM PDT 24
Peak memory 218456 kb
Host smart-5e12ef7b-340a-4c58-92e0-587724060e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415645428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.1415645428
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.1062658348
Short name T764
Test name
Test status
Simulation time 96936254 ps
CPU time 1.14 seconds
Started Jul 26 05:43:55 PM PDT 24
Finished Jul 26 05:43:56 PM PDT 24
Peak memory 217032 kb
Host smart-43709232-59b5-45d6-89ea-8edb0ac23623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062658348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1062658348
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.302630605
Short name T698
Test name
Test status
Simulation time 93297532 ps
CPU time 1.18 seconds
Started Jul 26 05:44:02 PM PDT 24
Finished Jul 26 05:44:04 PM PDT 24
Peak memory 219456 kb
Host smart-50479a74-3461-4cc3-bb12-7bf86d774ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302630605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.302630605
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.3011881713
Short name T983
Test name
Test status
Simulation time 189766320 ps
CPU time 2.36 seconds
Started Jul 26 05:44:02 PM PDT 24
Finished Jul 26 05:44:05 PM PDT 24
Peak memory 218480 kb
Host smart-ac01a0c1-6442-4704-aa87-b1cd6e67178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011881713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3011881713
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2914540280
Short name T29
Test name
Test status
Simulation time 27934982 ps
CPU time 1.17 seconds
Started Jul 26 05:44:00 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 218660 kb
Host smart-90097bc8-e3da-438d-8065-de669aaab2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914540280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2914540280
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.3576614399
Short name T734
Test name
Test status
Simulation time 80048526 ps
CPU time 1.17 seconds
Started Jul 26 05:44:02 PM PDT 24
Finished Jul 26 05:44:03 PM PDT 24
Peak memory 217372 kb
Host smart-4d63a08a-3e77-4bb5-9622-13f8e2359bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576614399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3576614399
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.1094741285
Short name T891
Test name
Test status
Simulation time 25775060 ps
CPU time 1.2 seconds
Started Jul 26 05:44:09 PM PDT 24
Finished Jul 26 05:44:11 PM PDT 24
Peak memory 218484 kb
Host smart-3ebbb800-373b-436a-a609-a538f50bbba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094741285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.1094741285
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.3943553738
Short name T523
Test name
Test status
Simulation time 84544474 ps
CPU time 1.54 seconds
Started Jul 26 05:44:23 PM PDT 24
Finished Jul 26 05:44:25 PM PDT 24
Peak memory 218776 kb
Host smart-e1f22ec0-a97a-43c2-b169-6a49b2471832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943553738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3943553738
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.95021276
Short name T852
Test name
Test status
Simulation time 90323834 ps
CPU time 1.25 seconds
Started Jul 26 05:44:02 PM PDT 24
Finished Jul 26 05:44:04 PM PDT 24
Peak memory 220516 kb
Host smart-f046b094-d91f-4fba-88b0-d18799e1c350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95021276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.95021276
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.218049589
Short name T563
Test name
Test status
Simulation time 90525856 ps
CPU time 1.14 seconds
Started Jul 26 05:43:57 PM PDT 24
Finished Jul 26 05:43:59 PM PDT 24
Peak memory 217264 kb
Host smart-7a974a55-4867-4c09-b343-f3bd0bfbb3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218049589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.218049589
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2822986443
Short name T605
Test name
Test status
Simulation time 71618294 ps
CPU time 1.1 seconds
Started Jul 26 05:44:04 PM PDT 24
Finished Jul 26 05:44:05 PM PDT 24
Peak memory 219552 kb
Host smart-b266d351-66c2-4343-ac2d-c740825f927e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822986443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2822986443
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.2916350816
Short name T731
Test name
Test status
Simulation time 60698577 ps
CPU time 1.26 seconds
Started Jul 26 05:44:02 PM PDT 24
Finished Jul 26 05:44:04 PM PDT 24
Peak memory 217304 kb
Host smart-4141910d-f825-4718-bdca-b8001326bad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916350816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2916350816
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.386415993
Short name T281
Test name
Test status
Simulation time 87465361 ps
CPU time 1.26 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:53 PM PDT 24
Peak memory 219552 kb
Host smart-879c3092-c4af-473a-8761-be9f7a7d256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386415993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.386415993
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.3403000892
Short name T384
Test name
Test status
Simulation time 48244930 ps
CPU time 1.79 seconds
Started Jul 26 05:44:02 PM PDT 24
Finished Jul 26 05:44:04 PM PDT 24
Peak memory 218568 kb
Host smart-1d85166c-8573-434e-bacf-6da2be2daeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403000892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3403000892
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.581239409
Short name T284
Test name
Test status
Simulation time 55764038 ps
CPU time 1.28 seconds
Started Jul 26 05:42:34 PM PDT 24
Finished Jul 26 05:42:35 PM PDT 24
Peak memory 219680 kb
Host smart-67fe561c-3a17-4c6e-96ea-434ae2fe694d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581239409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.581239409
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2260348571
Short name T651
Test name
Test status
Simulation time 47275369 ps
CPU time 0.89 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 05:42:42 PM PDT 24
Peak memory 206648 kb
Host smart-7de29fbe-0fac-43cd-bf62-90154492339b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260348571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2260348571
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_err.814079274
Short name T154
Test name
Test status
Simulation time 39160227 ps
CPU time 1.03 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 05:42:43 PM PDT 24
Peak memory 229528 kb
Host smart-41ae3ae0-2cf4-443a-a52f-527ab19cda32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814079274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.814079274
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3465642743
Short name T682
Test name
Test status
Simulation time 214508394 ps
CPU time 1.64 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 05:42:43 PM PDT 24
Peak memory 218780 kb
Host smart-d4a979f6-9a91-42c3-a0ff-d76e20cfa277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465642743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3465642743
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.340681895
Short name T758
Test name
Test status
Simulation time 31234230 ps
CPU time 1.23 seconds
Started Jul 26 05:42:34 PM PDT 24
Finished Jul 26 05:42:35 PM PDT 24
Peak memory 216588 kb
Host smart-2f389d6f-01f2-4996-b4c6-797b03427427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340681895 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.340681895
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2891863085
Short name T492
Test name
Test status
Simulation time 92986658 ps
CPU time 0.94 seconds
Started Jul 26 05:42:40 PM PDT 24
Finished Jul 26 05:42:41 PM PDT 24
Peak memory 214972 kb
Host smart-0c48d5ab-7c89-47b2-9dff-5b131500c793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891863085 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2891863085
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3922104957
Short name T821
Test name
Test status
Simulation time 170660129 ps
CPU time 3.8 seconds
Started Jul 26 05:42:44 PM PDT 24
Finished Jul 26 05:42:48 PM PDT 24
Peak memory 216956 kb
Host smart-f3dc274f-400b-4806-a008-2f6ff5adccef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922104957 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3922104957
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3571782828
Short name T238
Test name
Test status
Simulation time 59635187892 ps
CPU time 1274.68 seconds
Started Jul 26 05:42:42 PM PDT 24
Finished Jul 26 06:03:57 PM PDT 24
Peak memory 221516 kb
Host smart-2f7ba010-48e3-4bb0-88a9-2814b38c03b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571782828 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3571782828
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.321172785
Short name T980
Test name
Test status
Simulation time 32433414 ps
CPU time 1.32 seconds
Started Jul 26 05:44:20 PM PDT 24
Finished Jul 26 05:44:22 PM PDT 24
Peak memory 221952 kb
Host smart-628c9d4a-743c-464c-8075-e998ab3cf922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321172785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.321172785
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.265345630
Short name T585
Test name
Test status
Simulation time 76892624 ps
CPU time 2.9 seconds
Started Jul 26 05:44:19 PM PDT 24
Finished Jul 26 05:44:22 PM PDT 24
Peak memory 220256 kb
Host smart-dc4e10dd-150e-418e-9141-000a810976ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265345630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.265345630
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.4232087596
Short name T253
Test name
Test status
Simulation time 28879532 ps
CPU time 1.27 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:03 PM PDT 24
Peak memory 220216 kb
Host smart-80f92191-99fb-4236-a673-af72d9270aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232087596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.4232087596
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.1362114182
Short name T962
Test name
Test status
Simulation time 40102275 ps
CPU time 1.61 seconds
Started Jul 26 05:44:08 PM PDT 24
Finished Jul 26 05:44:09 PM PDT 24
Peak memory 218504 kb
Host smart-660a9ecb-1f94-4e59-9510-30fd3d885440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362114182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1362114182
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1287189634
Short name T748
Test name
Test status
Simulation time 39898566 ps
CPU time 1.69 seconds
Started Jul 26 05:44:15 PM PDT 24
Finished Jul 26 05:44:17 PM PDT 24
Peak memory 218384 kb
Host smart-50babf4b-e46a-4e62-a073-59abf1bff818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287189634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1287189634
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.2110343941
Short name T900
Test name
Test status
Simulation time 57280643 ps
CPU time 1.25 seconds
Started Jul 26 05:44:08 PM PDT 24
Finished Jul 26 05:44:10 PM PDT 24
Peak memory 219820 kb
Host smart-adda96f3-53a2-41a7-9e74-75218dac08ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110343941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2110343941
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.1799445568
Short name T873
Test name
Test status
Simulation time 54602174 ps
CPU time 1.18 seconds
Started Jul 26 05:44:07 PM PDT 24
Finished Jul 26 05:44:09 PM PDT 24
Peak memory 218256 kb
Host smart-b31a5b30-5b99-46c6-a6e1-c47a3ad86e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799445568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1799445568
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.2299834264
Short name T831
Test name
Test status
Simulation time 61355413 ps
CPU time 1.02 seconds
Started Jul 26 05:44:12 PM PDT 24
Finished Jul 26 05:44:13 PM PDT 24
Peak memory 218396 kb
Host smart-3ac8d5c1-a47f-4e21-809d-66c9349d8dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299834264 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2299834264
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.3394613977
Short name T438
Test name
Test status
Simulation time 58861697 ps
CPU time 1.65 seconds
Started Jul 26 05:44:27 PM PDT 24
Finished Jul 26 05:44:29 PM PDT 24
Peak memory 218692 kb
Host smart-7d1bcac3-fa9f-46c4-ba9a-6670b0d2e9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394613977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3394613977
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1712372214
Short name T162
Test name
Test status
Simulation time 94266931 ps
CPU time 1.25 seconds
Started Jul 26 05:44:08 PM PDT 24
Finished Jul 26 05:44:10 PM PDT 24
Peak memory 218484 kb
Host smart-edfb108d-7754-4a92-a354-b747ec44c979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712372214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1712372214
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.976624546
Short name T326
Test name
Test status
Simulation time 86969687 ps
CPU time 1.01 seconds
Started Jul 26 05:44:07 PM PDT 24
Finished Jul 26 05:44:08 PM PDT 24
Peak memory 217208 kb
Host smart-07364213-9dfe-4dd2-a74f-cc8ec3dbf091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976624546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.976624546
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.200424104
Short name T829
Test name
Test status
Simulation time 40198878 ps
CPU time 1.32 seconds
Started Jul 26 05:44:03 PM PDT 24
Finished Jul 26 05:44:04 PM PDT 24
Peak memory 218800 kb
Host smart-b6e81ab7-eaa2-4bdf-8aa9-c750c4930fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200424104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.200424104
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.2688051446
Short name T582
Test name
Test status
Simulation time 90351409 ps
CPU time 1.21 seconds
Started Jul 26 05:44:07 PM PDT 24
Finished Jul 26 05:44:08 PM PDT 24
Peak memory 220128 kb
Host smart-618b5bcb-eac7-4d4b-9096-89ce0baecee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688051446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.2688051446
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1835574720
Short name T959
Test name
Test status
Simulation time 72887533 ps
CPU time 1.16 seconds
Started Jul 26 05:44:11 PM PDT 24
Finished Jul 26 05:44:13 PM PDT 24
Peak memory 217216 kb
Host smart-47bc23e9-55e7-4bd4-9def-78dac56c4f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835574720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1835574720
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.748742792
Short name T471
Test name
Test status
Simulation time 34012328 ps
CPU time 1.5 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:03 PM PDT 24
Peak memory 218672 kb
Host smart-204e29fe-b190-4205-9975-688166d601e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748742792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.748742792
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2789283901
Short name T520
Test name
Test status
Simulation time 55193583 ps
CPU time 1.27 seconds
Started Jul 26 05:42:43 PM PDT 24
Finished Jul 26 05:42:44 PM PDT 24
Peak memory 215500 kb
Host smart-16e854cb-63ed-40b6-90f4-d3f68e119f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789283901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2789283901
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2751412833
Short name T667
Test name
Test status
Simulation time 29250632 ps
CPU time 0.96 seconds
Started Jul 26 05:42:56 PM PDT 24
Finished Jul 26 05:42:57 PM PDT 24
Peak memory 206624 kb
Host smart-97da9a1b-4a4f-482f-8d8f-11170ad1f6e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751412833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2751412833
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1142980652
Short name T674
Test name
Test status
Simulation time 12498245 ps
CPU time 0.88 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 05:42:43 PM PDT 24
Peak memory 215932 kb
Host smart-aa5b6c2a-b9f6-4eda-a5e2-e02e83c21cf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142980652 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1142980652
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.1021555361
Short name T192
Test name
Test status
Simulation time 19929516 ps
CPU time 1.06 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 05:42:43 PM PDT 24
Peak memory 218372 kb
Host smart-3349afd9-a927-4b5b-a287-c8966ab9b1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021555361 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1021555361
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.4060939696
Short name T689
Test name
Test status
Simulation time 30917674 ps
CPU time 1.27 seconds
Started Jul 26 05:42:33 PM PDT 24
Finished Jul 26 05:42:34 PM PDT 24
Peak memory 217224 kb
Host smart-29c294f7-2170-4830-89ff-666d5e4d4148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060939696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.4060939696
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1130903945
Short name T77
Test name
Test status
Simulation time 21941223 ps
CPU time 1.06 seconds
Started Jul 26 05:42:37 PM PDT 24
Finished Jul 26 05:42:38 PM PDT 24
Peak memory 215680 kb
Host smart-4582ba82-829d-4a3b-a3a2-bb9a77697891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130903945 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1130903945
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3572356723
Short name T697
Test name
Test status
Simulation time 45237565 ps
CPU time 0.91 seconds
Started Jul 26 05:42:44 PM PDT 24
Finished Jul 26 05:42:46 PM PDT 24
Peak memory 215076 kb
Host smart-0e5e7623-4779-4e18-80af-81e0eb7a6d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572356723 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3572356723
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.411483160
Short name T635
Test name
Test status
Simulation time 412083173 ps
CPU time 3.96 seconds
Started Jul 26 05:42:39 PM PDT 24
Finished Jul 26 05:42:43 PM PDT 24
Peak memory 217068 kb
Host smart-595d0f92-6c3e-4a30-9be6-bd01338ed6d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411483160 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.411483160
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3914030629
Short name T497
Test name
Test status
Simulation time 52264557693 ps
CPU time 1180.56 seconds
Started Jul 26 05:42:39 PM PDT 24
Finished Jul 26 06:02:20 PM PDT 24
Peak memory 219828 kb
Host smart-98fe85eb-5216-4e91-b981-df15bee9d489
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914030629 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3914030629
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.1500022368
Short name T8
Test name
Test status
Simulation time 148124120 ps
CPU time 1.2 seconds
Started Jul 26 05:44:06 PM PDT 24
Finished Jul 26 05:44:07 PM PDT 24
Peak memory 218332 kb
Host smart-4047a2b4-530c-41a4-a86f-ffe0e00b7d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500022368 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1500022368
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3153476017
Short name T835
Test name
Test status
Simulation time 31378495 ps
CPU time 1.21 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 217156 kb
Host smart-02dc3b04-4884-4eb3-9f8b-dcee96bc31a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153476017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3153476017
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2987771053
Short name T968
Test name
Test status
Simulation time 29083337 ps
CPU time 1.35 seconds
Started Jul 26 05:44:06 PM PDT 24
Finished Jul 26 05:44:07 PM PDT 24
Peak memory 218992 kb
Host smart-9651a205-c963-4642-9046-1cb0548dc0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987771053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2987771053
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.3375853048
Short name T937
Test name
Test status
Simulation time 37439359 ps
CPU time 1.31 seconds
Started Jul 26 05:44:13 PM PDT 24
Finished Jul 26 05:44:14 PM PDT 24
Peak memory 218344 kb
Host smart-c4f3c1d7-ccf0-4b6c-a313-57f1746a6b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375853048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3375853048
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3510718260
Short name T285
Test name
Test status
Simulation time 27982987 ps
CPU time 1.26 seconds
Started Jul 26 05:44:09 PM PDT 24
Finished Jul 26 05:44:11 PM PDT 24
Peak memory 218524 kb
Host smart-24f194f0-017c-4a6e-b3b0-93a7f02f9e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510718260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3510718260
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.895265696
Short name T745
Test name
Test status
Simulation time 77959215 ps
CPU time 1.47 seconds
Started Jul 26 05:44:07 PM PDT 24
Finished Jul 26 05:44:09 PM PDT 24
Peak memory 218940 kb
Host smart-6ec758fe-99fb-4aec-932c-28c00abe2063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895265696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.895265696
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.367119263
Short name T302
Test name
Test status
Simulation time 90817856 ps
CPU time 1.27 seconds
Started Jul 26 05:44:09 PM PDT 24
Finished Jul 26 05:44:11 PM PDT 24
Peak memory 220716 kb
Host smart-e55476d3-1373-4986-b448-2af7f4739dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367119263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.367119263
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.95049966
Short name T732
Test name
Test status
Simulation time 49360298 ps
CPU time 1.23 seconds
Started Jul 26 05:44:02 PM PDT 24
Finished Jul 26 05:44:04 PM PDT 24
Peak memory 217208 kb
Host smart-2e0857cb-ef83-4d4f-8f15-20dc0f8617ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95049966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.95049966
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.271392459
Short name T204
Test name
Test status
Simulation time 275740475 ps
CPU time 1.18 seconds
Started Jul 26 05:44:16 PM PDT 24
Finished Jul 26 05:44:17 PM PDT 24
Peak memory 219528 kb
Host smart-05d28742-e4a0-4fec-ad52-202fc0248cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271392459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.271392459
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/145.edn_alert.2425690449
Short name T175
Test name
Test status
Simulation time 74949011 ps
CPU time 1.11 seconds
Started Jul 26 05:44:09 PM PDT 24
Finished Jul 26 05:44:10 PM PDT 24
Peak memory 219316 kb
Host smart-8747afd6-8e4c-4f14-bbbd-b04e8e84c151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425690449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2425690449
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.356102228
Short name T742
Test name
Test status
Simulation time 37071789 ps
CPU time 1.52 seconds
Started Jul 26 05:44:08 PM PDT 24
Finished Jul 26 05:44:10 PM PDT 24
Peak memory 218204 kb
Host smart-00387920-af93-4603-b12f-f91c710c493f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356102228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.356102228
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.673204962
Short name T205
Test name
Test status
Simulation time 130950970 ps
CPU time 1.13 seconds
Started Jul 26 05:44:31 PM PDT 24
Finished Jul 26 05:44:33 PM PDT 24
Peak memory 220388 kb
Host smart-c17d2ff3-9b6c-4f46-a5b9-1e74214f6e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673204962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.673204962
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2065786000
Short name T528
Test name
Test status
Simulation time 177927702 ps
CPU time 1.12 seconds
Started Jul 26 05:44:17 PM PDT 24
Finished Jul 26 05:44:18 PM PDT 24
Peak memory 217228 kb
Host smart-ba6024d4-d557-461d-829e-7df636cfe68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065786000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2065786000
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.1366701785
Short name T360
Test name
Test status
Simulation time 25152184 ps
CPU time 1.24 seconds
Started Jul 26 05:44:09 PM PDT 24
Finished Jul 26 05:44:10 PM PDT 24
Peak memory 219208 kb
Host smart-bdd13047-5491-4c89-985b-545b4f4f4199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366701785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1366701785
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.2979157280
Short name T506
Test name
Test status
Simulation time 48185954 ps
CPU time 1.14 seconds
Started Jul 26 05:44:22 PM PDT 24
Finished Jul 26 05:44:24 PM PDT 24
Peak memory 219756 kb
Host smart-2cf7ff8c-1c8b-4528-bebe-8a7e334bb444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979157280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2979157280
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.1116439166
Short name T467
Test name
Test status
Simulation time 28166616 ps
CPU time 1.29 seconds
Started Jul 26 05:44:20 PM PDT 24
Finished Jul 26 05:44:21 PM PDT 24
Peak memory 220548 kb
Host smart-abb94946-d9d7-4a91-9bdf-17b66b8b7170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116439166 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1116439166
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.1381876118
Short name T678
Test name
Test status
Simulation time 57171716 ps
CPU time 1.24 seconds
Started Jul 26 05:44:09 PM PDT 24
Finished Jul 26 05:44:11 PM PDT 24
Peak memory 217056 kb
Host smart-7764bbec-ea64-4c35-9dcf-1b9c1091488a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381876118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1381876118
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.356504712
Short name T639
Test name
Test status
Simulation time 37216446 ps
CPU time 1.09 seconds
Started Jul 26 05:44:15 PM PDT 24
Finished Jul 26 05:44:16 PM PDT 24
Peak memory 219312 kb
Host smart-213f1d82-cc1f-46de-93ec-349d5430002f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356504712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.356504712
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.4290961216
Short name T290
Test name
Test status
Simulation time 89824101 ps
CPU time 1.54 seconds
Started Jul 26 05:44:19 PM PDT 24
Finished Jul 26 05:44:21 PM PDT 24
Peak memory 218568 kb
Host smart-fa2ea898-a30c-42fb-bb25-086fd561e251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290961216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.4290961216
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3052882857
Short name T221
Test name
Test status
Simulation time 65410339 ps
CPU time 1.11 seconds
Started Jul 26 05:42:57 PM PDT 24
Finished Jul 26 05:42:58 PM PDT 24
Peak memory 218476 kb
Host smart-34c362c2-c45e-4f53-bb0c-9e5662ff099e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052882857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3052882857
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3875994354
Short name T363
Test name
Test status
Simulation time 18649544 ps
CPU time 0.93 seconds
Started Jul 26 05:42:55 PM PDT 24
Finished Jul 26 05:42:56 PM PDT 24
Peak memory 214832 kb
Host smart-0ee2c698-26f5-425f-9103-276787b582fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875994354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3875994354
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1567523718
Short name T718
Test name
Test status
Simulation time 114387574 ps
CPU time 1.11 seconds
Started Jul 26 05:42:56 PM PDT 24
Finished Jul 26 05:42:58 PM PDT 24
Peak memory 219428 kb
Host smart-80b6c3af-abaf-474b-b751-ed3a8c084905
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567523718 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1567523718
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1653529476
Short name T115
Test name
Test status
Simulation time 120080684 ps
CPU time 0.97 seconds
Started Jul 26 05:42:57 PM PDT 24
Finished Jul 26 05:42:58 PM PDT 24
Peak memory 219656 kb
Host smart-36d76d06-86ff-46d8-9fee-871dd287716c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653529476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1653529476
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2311264076
Short name T672
Test name
Test status
Simulation time 212954452 ps
CPU time 1.54 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 218880 kb
Host smart-7b03ff14-209d-455a-a99a-b4c409208e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311264076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2311264076
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3953224637
Short name T369
Test name
Test status
Simulation time 22072527 ps
CPU time 1.07 seconds
Started Jul 26 05:42:56 PM PDT 24
Finished Jul 26 05:42:57 PM PDT 24
Peak memory 215368 kb
Host smart-f5a9359f-21b8-40d0-a949-da713e2392fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953224637 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3953224637
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3819534786
Short name T782
Test name
Test status
Simulation time 18754629 ps
CPU time 1.02 seconds
Started Jul 26 05:42:56 PM PDT 24
Finished Jul 26 05:42:57 PM PDT 24
Peak memory 215040 kb
Host smart-d690e576-a257-4425-9135-55cbbdf1329f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819534786 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3819534786
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.87833578
Short name T686
Test name
Test status
Simulation time 346696793 ps
CPU time 3.66 seconds
Started Jul 26 05:42:55 PM PDT 24
Finished Jul 26 05:42:59 PM PDT 24
Peak memory 217032 kb
Host smart-5cc7cb15-7a2f-4be3-bc21-8228a86ba0a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87833578 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.87833578
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2246069147
Short name T740
Test name
Test status
Simulation time 155302832953 ps
CPU time 373.24 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:49:14 PM PDT 24
Peak memory 229648 kb
Host smart-fbbd5e0b-3245-409a-b186-43d7b86b9982
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246069147 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2246069147
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.779981983
Short name T478
Test name
Test status
Simulation time 88918129 ps
CPU time 1.23 seconds
Started Jul 26 05:44:26 PM PDT 24
Finished Jul 26 05:44:27 PM PDT 24
Peak memory 219620 kb
Host smart-aece8d6c-e3b7-4d8c-a9a5-1b9af506feb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779981983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.779981983
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.283152875
Short name T514
Test name
Test status
Simulation time 48830807 ps
CPU time 1.58 seconds
Started Jul 26 05:44:29 PM PDT 24
Finished Jul 26 05:44:31 PM PDT 24
Peak memory 218448 kb
Host smart-8a30a506-e2e6-4d66-a65f-43ec8668e57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283152875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.283152875
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.3200887606
Short name T765
Test name
Test status
Simulation time 139993889 ps
CPU time 1.31 seconds
Started Jul 26 05:44:18 PM PDT 24
Finished Jul 26 05:44:19 PM PDT 24
Peak memory 220160 kb
Host smart-a5157ade-da18-4e2e-b723-1075e5322ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200887606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.3200887606
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.2304526927
Short name T871
Test name
Test status
Simulation time 63177015 ps
CPU time 1.01 seconds
Started Jul 26 05:44:23 PM PDT 24
Finished Jul 26 05:44:25 PM PDT 24
Peak memory 217204 kb
Host smart-d0afb318-e3a6-4d07-ac74-7aaba972e273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304526927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2304526927
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.2032039643
Short name T906
Test name
Test status
Simulation time 27197640 ps
CPU time 1.21 seconds
Started Jul 26 05:44:31 PM PDT 24
Finished Jul 26 05:44:33 PM PDT 24
Peak memory 218624 kb
Host smart-7c1e9bab-b325-4a80-b588-88fd48bdbc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032039643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2032039643
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.2539128207
Short name T812
Test name
Test status
Simulation time 116196165 ps
CPU time 1.31 seconds
Started Jul 26 05:44:24 PM PDT 24
Finished Jul 26 05:44:26 PM PDT 24
Peak memory 218420 kb
Host smart-bd5a7ccb-545b-4a98-ae52-667dcc04bd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539128207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2539128207
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.3570209788
Short name T472
Test name
Test status
Simulation time 83887664 ps
CPU time 1.28 seconds
Started Jul 26 05:44:32 PM PDT 24
Finished Jul 26 05:44:34 PM PDT 24
Peak memory 220632 kb
Host smart-39177383-6328-43f9-b247-7a6fa721134e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570209788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3570209788
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.1563140049
Short name T677
Test name
Test status
Simulation time 53281653 ps
CPU time 1.25 seconds
Started Jul 26 05:44:36 PM PDT 24
Finished Jul 26 05:44:37 PM PDT 24
Peak memory 218756 kb
Host smart-be6cd66d-1591-4ece-a2e5-2d776596991f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563140049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1563140049
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.3283307922
Short name T498
Test name
Test status
Simulation time 85936489 ps
CPU time 1.09 seconds
Started Jul 26 05:44:11 PM PDT 24
Finished Jul 26 05:44:13 PM PDT 24
Peak memory 219380 kb
Host smart-51f28d65-5161-496e-a423-3fc6fd4d21a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283307922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3283307922
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1752471487
Short name T828
Test name
Test status
Simulation time 65906348 ps
CPU time 1.42 seconds
Started Jul 26 05:44:12 PM PDT 24
Finished Jul 26 05:44:13 PM PDT 24
Peak memory 217204 kb
Host smart-718ebac3-b636-4e78-aacd-b77018d978af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752471487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1752471487
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.4044347971
Short name T992
Test name
Test status
Simulation time 56577326 ps
CPU time 1.11 seconds
Started Jul 26 05:44:27 PM PDT 24
Finished Jul 26 05:44:29 PM PDT 24
Peak memory 219364 kb
Host smart-80893f15-2d61-47d6-8e85-c2a2b729a3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044347971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.4044347971
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.3776327345
Short name T905
Test name
Test status
Simulation time 54451078 ps
CPU time 1.54 seconds
Started Jul 26 05:44:14 PM PDT 24
Finished Jul 26 05:44:16 PM PDT 24
Peak memory 218480 kb
Host smart-29cac174-83e2-43ed-bcdc-7667365adf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776327345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3776327345
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.327065532
Short name T342
Test name
Test status
Simulation time 31796629 ps
CPU time 1.49 seconds
Started Jul 26 05:44:25 PM PDT 24
Finished Jul 26 05:44:26 PM PDT 24
Peak memory 215496 kb
Host smart-d6eaa60b-06d8-4b7c-a4ac-73271135e590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327065532 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.327065532
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2995439771
Short name T413
Test name
Test status
Simulation time 52841247 ps
CPU time 1.7 seconds
Started Jul 26 05:44:20 PM PDT 24
Finished Jul 26 05:44:22 PM PDT 24
Peak memory 218252 kb
Host smart-c86ffc95-63f8-4694-b4c3-b3c7a1fc0aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995439771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2995439771
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.4375767
Short name T676
Test name
Test status
Simulation time 35291284 ps
CPU time 1.05 seconds
Started Jul 26 05:44:18 PM PDT 24
Finished Jul 26 05:44:19 PM PDT 24
Peak memory 218752 kb
Host smart-16860f8a-087f-4dfb-ab87-eeca967f3125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4375767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.4375767
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.165921471
Short name T315
Test name
Test status
Simulation time 35115303 ps
CPU time 1.54 seconds
Started Jul 26 05:44:18 PM PDT 24
Finished Jul 26 05:44:20 PM PDT 24
Peak memory 217228 kb
Host smart-e236a0ff-0453-4ac6-934f-e7196f486102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165921471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.165921471
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3512730741
Short name T975
Test name
Test status
Simulation time 70765359 ps
CPU time 1.11 seconds
Started Jul 26 05:44:14 PM PDT 24
Finished Jul 26 05:44:15 PM PDT 24
Peak memory 219372 kb
Host smart-a5e7e76b-ec5d-4510-a35a-9a929f88f78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512730741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3512730741
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.3653335757
Short name T830
Test name
Test status
Simulation time 50294912 ps
CPU time 1.73 seconds
Started Jul 26 05:44:10 PM PDT 24
Finished Jul 26 05:44:12 PM PDT 24
Peak memory 217220 kb
Host smart-fcd0d044-72de-478e-b4b2-b2165059f7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653335757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3653335757
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.917448881
Short name T981
Test name
Test status
Simulation time 128628469 ps
CPU time 1.17 seconds
Started Jul 26 05:44:28 PM PDT 24
Finished Jul 26 05:44:30 PM PDT 24
Peak memory 220204 kb
Host smart-d53a5d57-92d8-4f84-accd-014a0e81f173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917448881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.917448881
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1211782553
Short name T445
Test name
Test status
Simulation time 55446842 ps
CPU time 1.37 seconds
Started Jul 26 05:44:15 PM PDT 24
Finished Jul 26 05:44:16 PM PDT 24
Peak memory 218624 kb
Host smart-ef05292a-fd19-4f17-b37b-04865a9d057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211782553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1211782553
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3751395897
Short name T72
Test name
Test status
Simulation time 35378236 ps
CPU time 1.17 seconds
Started Jul 26 05:42:57 PM PDT 24
Finished Jul 26 05:42:59 PM PDT 24
Peak memory 219508 kb
Host smart-371ab08e-f782-489d-95ca-09bb1c284962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751395897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3751395897
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.4241531108
Short name T890
Test name
Test status
Simulation time 16389265 ps
CPU time 0.97 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 206660 kb
Host smart-fcc09969-46cf-4b1a-9ff0-51709051ac62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241531108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.4241531108
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3870575412
Short name T839
Test name
Test status
Simulation time 27903239 ps
CPU time 1.12 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 216484 kb
Host smart-e8b4f326-5547-4390-a3b2-cc175bd65299
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870575412 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3870575412
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2762325844
Short name T13
Test name
Test status
Simulation time 68796940 ps
CPU time 1.19 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:42:59 PM PDT 24
Peak memory 225520 kb
Host smart-b0d18896-1f5d-4470-a57a-0f4066811d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762325844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2762325844
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2993653069
Short name T389
Test name
Test status
Simulation time 45908257 ps
CPU time 1.21 seconds
Started Jul 26 05:42:57 PM PDT 24
Finished Jul 26 05:42:58 PM PDT 24
Peak memory 218472 kb
Host smart-15de9bf6-5181-4cc8-9bd3-dabad5b3fb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993653069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2993653069
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.4126313809
Short name T958
Test name
Test status
Simulation time 23459952 ps
CPU time 0.94 seconds
Started Jul 26 05:42:56 PM PDT 24
Finished Jul 26 05:42:57 PM PDT 24
Peak memory 215676 kb
Host smart-c10be446-b614-4b43-91f0-4b01dc3d499a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126313809 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.4126313809
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3293292967
Short name T586
Test name
Test status
Simulation time 44223240 ps
CPU time 0.91 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:02 PM PDT 24
Peak memory 215152 kb
Host smart-39ed8d64-5d3b-4a67-b623-6ceab6248c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293292967 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3293292967
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3052015805
Short name T650
Test name
Test status
Simulation time 307168305 ps
CPU time 1.48 seconds
Started Jul 26 05:42:55 PM PDT 24
Finished Jul 26 05:42:57 PM PDT 24
Peak memory 207024 kb
Host smart-94e4c09d-6172-4c2f-9f58-456030f6d2d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052015805 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3052015805
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_alert.2997529550
Short name T305
Test name
Test status
Simulation time 41702063 ps
CPU time 1.07 seconds
Started Jul 26 05:44:13 PM PDT 24
Finished Jul 26 05:44:14 PM PDT 24
Peak memory 220824 kb
Host smart-b0d23b2b-8e01-4cf8-bc03-4b2ed9c0f533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997529550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.2997529550
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1971153863
Short name T515
Test name
Test status
Simulation time 22916818 ps
CPU time 1.12 seconds
Started Jul 26 05:44:15 PM PDT 24
Finished Jul 26 05:44:17 PM PDT 24
Peak memory 217280 kb
Host smart-21dd9872-8ea5-4161-8839-21349c1dedf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971153863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1971153863
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.356043877
Short name T591
Test name
Test status
Simulation time 272052702 ps
CPU time 1.36 seconds
Started Jul 26 05:44:17 PM PDT 24
Finished Jul 26 05:44:18 PM PDT 24
Peak memory 220700 kb
Host smart-6d344311-a816-482b-a7e4-731c827cd361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356043877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.356043877
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.415908231
Short name T947
Test name
Test status
Simulation time 141425314 ps
CPU time 1.59 seconds
Started Jul 26 05:44:21 PM PDT 24
Finished Jul 26 05:44:23 PM PDT 24
Peak memory 219736 kb
Host smart-41efc389-3774-4097-abfc-418806d223f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415908231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.415908231
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.1067462144
Short name T195
Test name
Test status
Simulation time 33069031 ps
CPU time 1.25 seconds
Started Jul 26 05:44:11 PM PDT 24
Finished Jul 26 05:44:13 PM PDT 24
Peak memory 218424 kb
Host smart-6e49f2b6-a78c-4202-8421-13220cfb673a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067462144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1067462144
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.4090296232
Short name T966
Test name
Test status
Simulation time 12164524607 ps
CPU time 142.02 seconds
Started Jul 26 05:44:13 PM PDT 24
Finished Jul 26 05:46:35 PM PDT 24
Peak memory 220372 kb
Host smart-d44d0697-1db7-4452-b515-e16ca07da60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090296232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.4090296232
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2963924897
Short name T919
Test name
Test status
Simulation time 26280285 ps
CPU time 1.03 seconds
Started Jul 26 05:44:13 PM PDT 24
Finished Jul 26 05:44:15 PM PDT 24
Peak memory 217260 kb
Host smart-67769af4-b4a6-4a52-b886-f4c7dd25b522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963924897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2963924897
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2124799382
Short name T668
Test name
Test status
Simulation time 21393528 ps
CPU time 1.11 seconds
Started Jul 26 05:44:34 PM PDT 24
Finished Jul 26 05:44:35 PM PDT 24
Peak memory 218404 kb
Host smart-420d7af0-cf82-4a19-b3b1-a3ad809bc2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124799382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2124799382
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2447051021
Short name T352
Test name
Test status
Simulation time 37319238 ps
CPU time 1.13 seconds
Started Jul 26 05:44:36 PM PDT 24
Finished Jul 26 05:44:37 PM PDT 24
Peak memory 219864 kb
Host smart-2d19ed8e-e6ab-46b3-b1c0-e65616df8e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447051021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2447051021
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3650022278
Short name T827
Test name
Test status
Simulation time 140529884 ps
CPU time 1.14 seconds
Started Jul 26 05:44:15 PM PDT 24
Finished Jul 26 05:44:16 PM PDT 24
Peak memory 220544 kb
Host smart-325ced59-1bd5-4ce1-b0ca-45913643e4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650022278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3650022278
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.2646300007
Short name T396
Test name
Test status
Simulation time 52410604 ps
CPU time 2.01 seconds
Started Jul 26 05:44:15 PM PDT 24
Finished Jul 26 05:44:17 PM PDT 24
Peak memory 218348 kb
Host smart-9d834075-f775-408c-8fbc-b189eefe9e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646300007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2646300007
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.1702547296
Short name T715
Test name
Test status
Simulation time 49296481 ps
CPU time 1.21 seconds
Started Jul 26 05:44:17 PM PDT 24
Finished Jul 26 05:44:18 PM PDT 24
Peak memory 219516 kb
Host smart-4c8425d6-44ab-4135-97df-08b5af8cb759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702547296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.1702547296
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.1383254104
Short name T588
Test name
Test status
Simulation time 67302135 ps
CPU time 1.68 seconds
Started Jul 26 05:44:14 PM PDT 24
Finished Jul 26 05:44:16 PM PDT 24
Peak memory 218304 kb
Host smart-3651a436-d71a-424f-b98d-dd8ce41c4789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383254104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1383254104
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.451523444
Short name T867
Test name
Test status
Simulation time 22369838 ps
CPU time 1.14 seconds
Started Jul 26 05:44:13 PM PDT 24
Finished Jul 26 05:44:15 PM PDT 24
Peak memory 219700 kb
Host smart-54c89803-6fe1-4e96-a530-9212b0a6b0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451523444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.451523444
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2670261644
Short name T949
Test name
Test status
Simulation time 74841296 ps
CPU time 2.15 seconds
Started Jul 26 05:44:19 PM PDT 24
Finished Jul 26 05:44:21 PM PDT 24
Peak memory 220140 kb
Host smart-af47f218-fc81-4c95-a18a-3a4de02d338b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670261644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2670261644
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.2398513872
Short name T883
Test name
Test status
Simulation time 52302524 ps
CPU time 1.19 seconds
Started Jul 26 05:44:35 PM PDT 24
Finished Jul 26 05:44:36 PM PDT 24
Peak memory 215544 kb
Host smart-c18fc4e8-220f-4db5-adf9-16c075d904f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398513872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.2398513872
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/169.edn_alert.3562872543
Short name T579
Test name
Test status
Simulation time 25399429 ps
CPU time 1.2 seconds
Started Jul 26 05:44:38 PM PDT 24
Finished Jul 26 05:44:39 PM PDT 24
Peak memory 215404 kb
Host smart-889b8799-1e3f-4c97-83de-f14e7d1e0ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562872543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.3562872543
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert.175431576
Short name T861
Test name
Test status
Simulation time 45045394 ps
CPU time 1.18 seconds
Started Jul 26 05:42:55 PM PDT 24
Finished Jul 26 05:42:56 PM PDT 24
Peak memory 221040 kb
Host smart-6a98412c-d58b-4d3c-ae51-7aa2a0840cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175431576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.175431576
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1326823470
Short name T391
Test name
Test status
Simulation time 19155173 ps
CPU time 0.99 seconds
Started Jul 26 05:42:55 PM PDT 24
Finished Jul 26 05:42:56 PM PDT 24
Peak memory 206672 kb
Host smart-343f6798-de51-4b46-ad4d-7bc7d369f1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326823470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1326823470
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.4023817365
Short name T601
Test name
Test status
Simulation time 76396617 ps
CPU time 0.81 seconds
Started Jul 26 05:42:56 PM PDT 24
Finished Jul 26 05:42:57 PM PDT 24
Peak memory 216200 kb
Host smart-eabd830e-dc57-4194-b2a0-9b2712483518
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023817365 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.4023817365
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3134269884
Short name T546
Test name
Test status
Simulation time 26665494 ps
CPU time 1.08 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 218280 kb
Host smart-ed380aad-905c-44c4-8665-6841ed6664de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134269884 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3134269884
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.2371666796
Short name T562
Test name
Test status
Simulation time 21839266 ps
CPU time 1.09 seconds
Started Jul 26 05:42:57 PM PDT 24
Finished Jul 26 05:42:58 PM PDT 24
Peak memory 219456 kb
Host smart-4261e965-c85e-4dc9-ba26-65630e9068e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371666796 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2371666796
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1112396293
Short name T616
Test name
Test status
Simulation time 30505059 ps
CPU time 1.28 seconds
Started Jul 26 05:42:56 PM PDT 24
Finished Jul 26 05:42:58 PM PDT 24
Peak memory 216920 kb
Host smart-34960d74-6a05-4636-8df4-86e0cde8acda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112396293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1112396293
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1032507841
Short name T875
Test name
Test status
Simulation time 29419686 ps
CPU time 1.07 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 223888 kb
Host smart-c474e555-5715-44a3-931b-006fba5c8731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032507841 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1032507841
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1308019453
Short name T608
Test name
Test status
Simulation time 16642339 ps
CPU time 1.04 seconds
Started Jul 26 05:42:56 PM PDT 24
Finished Jul 26 05:42:57 PM PDT 24
Peak memory 215168 kb
Host smart-5caa82f0-17fd-4934-956a-5ae9af278c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308019453 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1308019453
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3064583332
Short name T604
Test name
Test status
Simulation time 23842330 ps
CPU time 0.91 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 206448 kb
Host smart-08e098d4-2ac2-4d13-877f-05eac6bfebcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064583332 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3064583332
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3501773691
Short name T309
Test name
Test status
Simulation time 79568928465 ps
CPU time 1021.84 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 06:00:00 PM PDT 24
Peak memory 223816 kb
Host smart-0baf887c-e199-4389-8f7b-c8df4a35c740
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501773691 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3501773691
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.2969899968
Short name T27
Test name
Test status
Simulation time 22611579 ps
CPU time 1.21 seconds
Started Jul 26 05:44:18 PM PDT 24
Finished Jul 26 05:44:19 PM PDT 24
Peak memory 219640 kb
Host smart-9001b7dd-3253-499e-ac6b-f1981d695b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969899968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2969899968
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1241161530
Short name T661
Test name
Test status
Simulation time 115010726 ps
CPU time 1.27 seconds
Started Jul 26 05:44:26 PM PDT 24
Finished Jul 26 05:44:28 PM PDT 24
Peak memory 217212 kb
Host smart-4682c621-bc5f-47d6-9d29-00162d42e72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241161530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1241161530
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.2527248610
Short name T910
Test name
Test status
Simulation time 36360935 ps
CPU time 1.12 seconds
Started Jul 26 05:44:15 PM PDT 24
Finished Jul 26 05:44:17 PM PDT 24
Peak memory 218380 kb
Host smart-d5f68626-ad3c-45df-9419-a9dfec996ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527248610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2527248610
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.778746534
Short name T509
Test name
Test status
Simulation time 65358456 ps
CPU time 1.38 seconds
Started Jul 26 05:44:34 PM PDT 24
Finished Jul 26 05:44:36 PM PDT 24
Peak memory 217100 kb
Host smart-48355343-6b27-4d25-a37c-3a88d1b432cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778746534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.778746534
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1448623260
Short name T251
Test name
Test status
Simulation time 58230059 ps
CPU time 1.33 seconds
Started Jul 26 05:44:19 PM PDT 24
Finished Jul 26 05:44:20 PM PDT 24
Peak memory 219888 kb
Host smart-bd5612d5-e282-4e0a-ab32-baf5a94c887e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448623260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1448623260
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.1794100264
Short name T441
Test name
Test status
Simulation time 40015336 ps
CPU time 1.52 seconds
Started Jul 26 05:44:17 PM PDT 24
Finished Jul 26 05:44:19 PM PDT 24
Peak memory 218328 kb
Host smart-e38536ec-6aa2-408a-857d-0cc5816415b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794100264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1794100264
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3963525668
Short name T901
Test name
Test status
Simulation time 49039709 ps
CPU time 1.19 seconds
Started Jul 26 05:44:36 PM PDT 24
Finished Jul 26 05:44:38 PM PDT 24
Peak memory 219456 kb
Host smart-a6a5c3c9-105c-482d-b969-1462b91fa178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963525668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3963525668
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.2223016824
Short name T784
Test name
Test status
Simulation time 25492169 ps
CPU time 1.21 seconds
Started Jul 26 05:44:36 PM PDT 24
Finished Jul 26 05:44:37 PM PDT 24
Peak memory 215128 kb
Host smart-d7ad8021-2297-4236-b123-4d72d11da5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223016824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2223016824
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.3439481784
Short name T833
Test name
Test status
Simulation time 36092330 ps
CPU time 1.06 seconds
Started Jul 26 05:44:28 PM PDT 24
Finished Jul 26 05:44:29 PM PDT 24
Peak memory 219700 kb
Host smart-08bfeb2a-72d1-4123-b9a1-68fc6cb22620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439481784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3439481784
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.4250652942
Short name T818
Test name
Test status
Simulation time 133731533 ps
CPU time 1.19 seconds
Started Jul 26 05:44:23 PM PDT 24
Finished Jul 26 05:44:25 PM PDT 24
Peak memory 217292 kb
Host smart-bda767f9-9ebe-46e0-b9a4-612229b31ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250652942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.4250652942
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3359459415
Short name T345
Test name
Test status
Simulation time 29970754 ps
CPU time 1.23 seconds
Started Jul 26 05:44:22 PM PDT 24
Finished Jul 26 05:44:24 PM PDT 24
Peak memory 218288 kb
Host smart-cb6bf112-a851-4dad-89f9-e60182037345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359459415 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3359459415
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.3982145449
Short name T938
Test name
Test status
Simulation time 33931083 ps
CPU time 1.4 seconds
Started Jul 26 05:44:37 PM PDT 24
Finished Jul 26 05:44:38 PM PDT 24
Peak memory 218420 kb
Host smart-4310035d-49e6-486f-9949-542657f65e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982145449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3982145449
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2973825768
Short name T911
Test name
Test status
Simulation time 34214001 ps
CPU time 1.19 seconds
Started Jul 26 05:44:29 PM PDT 24
Finished Jul 26 05:44:30 PM PDT 24
Peak memory 218396 kb
Host smart-68e5a0b6-ad81-4171-bcd7-8bc5aedd61f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973825768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2973825768
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/177.edn_alert.184352123
Short name T990
Test name
Test status
Simulation time 51751547 ps
CPU time 1.26 seconds
Started Jul 26 05:44:15 PM PDT 24
Finished Jul 26 05:44:16 PM PDT 24
Peak memory 220812 kb
Host smart-ba69768b-4295-42f1-b0ff-a5bfdfb47bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184352123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.184352123
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/178.edn_alert.1266531590
Short name T139
Test name
Test status
Simulation time 22158243 ps
CPU time 1.22 seconds
Started Jul 26 05:44:21 PM PDT 24
Finished Jul 26 05:44:22 PM PDT 24
Peak memory 218516 kb
Host smart-ecaaffd0-c6fc-4313-896b-674a127df4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266531590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.1266531590
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.756414682
Short name T584
Test name
Test status
Simulation time 59912172 ps
CPU time 1.31 seconds
Started Jul 26 05:44:21 PM PDT 24
Finished Jul 26 05:44:22 PM PDT 24
Peak memory 218280 kb
Host smart-e3517b04-8b92-4ce5-9c1a-da542c5423be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756414682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.756414682
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3836721273
Short name T570
Test name
Test status
Simulation time 48593739 ps
CPU time 1.18 seconds
Started Jul 26 05:44:16 PM PDT 24
Finished Jul 26 05:44:18 PM PDT 24
Peak memory 219428 kb
Host smart-9f882149-6d17-47af-b0a5-e0ef92d9053b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836721273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3836721273
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2470536879
Short name T559
Test name
Test status
Simulation time 122361006 ps
CPU time 1.08 seconds
Started Jul 26 05:44:30 PM PDT 24
Finished Jul 26 05:44:31 PM PDT 24
Peak memory 217292 kb
Host smart-cdaa741f-ecc6-46b1-b2f0-497e470f2a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470536879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2470536879
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1039561113
Short name T368
Test name
Test status
Simulation time 50547002 ps
CPU time 1.16 seconds
Started Jul 26 05:42:54 PM PDT 24
Finished Jul 26 05:42:55 PM PDT 24
Peak memory 219160 kb
Host smart-601a8390-e0bf-48a3-82d4-a664d0b13997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039561113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1039561113
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2123191231
Short name T720
Test name
Test status
Simulation time 14152364 ps
CPU time 0.93 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:01 PM PDT 24
Peak memory 207128 kb
Host smart-193aa453-ec65-47a2-b538-782024b6fd16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123191231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2123191231
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1176765464
Short name T220
Test name
Test status
Simulation time 21697540 ps
CPU time 0.86 seconds
Started Jul 26 05:42:57 PM PDT 24
Finished Jul 26 05:42:58 PM PDT 24
Peak memory 216172 kb
Host smart-6ef44006-83af-44b5-8039-7ccd549e0107
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176765464 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1176765464
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1337450584
Short name T124
Test name
Test status
Simulation time 67438542 ps
CPU time 1.37 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 216536 kb
Host smart-4f2011e1-8f33-4e19-bcdd-834811b1711d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337450584 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1337450584
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_genbits.182623864
Short name T680
Test name
Test status
Simulation time 60128360 ps
CPU time 2.33 seconds
Started Jul 26 05:42:57 PM PDT 24
Finished Jul 26 05:42:59 PM PDT 24
Peak memory 219728 kb
Host smart-1b3b136f-1db5-4548-af7e-9e710ba862b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182623864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.182623864
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1898444470
Short name T82
Test name
Test status
Simulation time 32686835 ps
CPU time 1.11 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:42:59 PM PDT 24
Peak memory 216612 kb
Host smart-c31190b8-9dda-40ba-8ea1-33f9004fc4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898444470 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1898444470
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2747141856
Short name T484
Test name
Test status
Simulation time 24220758 ps
CPU time 0.92 seconds
Started Jul 26 05:42:54 PM PDT 24
Finished Jul 26 05:42:55 PM PDT 24
Peak memory 215100 kb
Host smart-cf5a4120-fbf4-443c-82cc-0db21366a879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747141856 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2747141856
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.780924985
Short name T699
Test name
Test status
Simulation time 361749936 ps
CPU time 4.02 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 215020 kb
Host smart-7f2a0c3a-d9dd-4559-b0af-871597acd29c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780924985 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.780924985
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1734011513
Short name T230
Test name
Test status
Simulation time 88252504314 ps
CPU time 1082.7 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 06:01:04 PM PDT 24
Peak memory 223824 kb
Host smart-bd9bfd1c-2e69-455d-8158-0bd20e81574d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734011513 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1734011513
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1151936033
Short name T613
Test name
Test status
Simulation time 68698668 ps
CPU time 1.08 seconds
Started Jul 26 05:44:44 PM PDT 24
Finished Jul 26 05:44:45 PM PDT 24
Peak memory 219740 kb
Host smart-5337ecaf-e3b3-4dd5-bbf8-aa2be443fc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151936033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1151936033
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/181.edn_alert.2185686253
Short name T817
Test name
Test status
Simulation time 28241319 ps
CPU time 1.29 seconds
Started Jul 26 05:44:38 PM PDT 24
Finished Jul 26 05:44:40 PM PDT 24
Peak memory 218524 kb
Host smart-fa725d42-e37f-44a7-9659-199e94244bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185686253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2185686253
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.2529818708
Short name T603
Test name
Test status
Simulation time 99060543 ps
CPU time 3.05 seconds
Started Jul 26 05:44:30 PM PDT 24
Finished Jul 26 05:44:34 PM PDT 24
Peak memory 215156 kb
Host smart-ff527651-8e99-4bad-9d5f-bae3ee673208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529818708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2529818708
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.60078505
Short name T159
Test name
Test status
Simulation time 29159452 ps
CPU time 1.31 seconds
Started Jul 26 05:44:26 PM PDT 24
Finished Jul 26 05:44:28 PM PDT 24
Peak memory 219744 kb
Host smart-57715d4a-9a29-479f-9d76-50446bd4133b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60078505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.60078505
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.2538412851
Short name T393
Test name
Test status
Simulation time 88054458 ps
CPU time 1.11 seconds
Started Jul 26 05:44:21 PM PDT 24
Finished Jul 26 05:44:22 PM PDT 24
Peak memory 217108 kb
Host smart-bf671e75-1e3c-48bd-b8f1-c46a0f2934c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538412851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2538412851
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.595307717
Short name T38
Test name
Test status
Simulation time 80946420 ps
CPU time 1.02 seconds
Started Jul 26 05:44:34 PM PDT 24
Finished Jul 26 05:44:35 PM PDT 24
Peak memory 217056 kb
Host smart-b0c58248-4285-4941-9bcf-6212db852d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595307717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.595307717
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.2559728291
Short name T780
Test name
Test status
Simulation time 28426674 ps
CPU time 1.25 seconds
Started Jul 26 05:44:26 PM PDT 24
Finished Jul 26 05:44:28 PM PDT 24
Peak memory 219936 kb
Host smart-ff17bede-d982-4cd5-a433-068c2761005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559728291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2559728291
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.1804689667
Short name T989
Test name
Test status
Simulation time 115601034 ps
CPU time 1.53 seconds
Started Jul 26 05:44:49 PM PDT 24
Finished Jul 26 05:44:50 PM PDT 24
Peak memory 220228 kb
Host smart-9fbe0018-29ea-4a78-906a-3f30b0436eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804689667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1804689667
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.4258784956
Short name T223
Test name
Test status
Simulation time 84622394 ps
CPU time 1.24 seconds
Started Jul 26 05:44:26 PM PDT 24
Finished Jul 26 05:44:28 PM PDT 24
Peak memory 218612 kb
Host smart-5556af60-426b-4d2c-96fc-531625e9882b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258784956 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.4258784956
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.1673029216
Short name T482
Test name
Test status
Simulation time 21020062 ps
CPU time 1.14 seconds
Started Jul 26 05:44:36 PM PDT 24
Finished Jul 26 05:44:37 PM PDT 24
Peak memory 217384 kb
Host smart-f4588642-209b-4e15-855e-9be665e8e9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673029216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1673029216
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.62104435
Short name T168
Test name
Test status
Simulation time 85004302 ps
CPU time 1.13 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:44:54 PM PDT 24
Peak memory 219680 kb
Host smart-4200e6e7-d9e6-4736-a56e-46cc62e29b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62104435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.62104435
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.1915949260
Short name T19
Test name
Test status
Simulation time 38857923 ps
CPU time 1.28 seconds
Started Jul 26 05:44:34 PM PDT 24
Finished Jul 26 05:44:35 PM PDT 24
Peak memory 218344 kb
Host smart-c3d5b33f-e40b-4845-a99b-8235f5bb87de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915949260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1915949260
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.4007904779
Short name T411
Test name
Test status
Simulation time 25492244 ps
CPU time 1.17 seconds
Started Jul 26 05:44:28 PM PDT 24
Finished Jul 26 05:44:29 PM PDT 24
Peak memory 218608 kb
Host smart-f7a4adb1-b271-4b90-a88a-1e2ecb140a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007904779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.4007904779
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.1291860978
Short name T888
Test name
Test status
Simulation time 111921112 ps
CPU time 1.92 seconds
Started Jul 26 05:44:26 PM PDT 24
Finished Jul 26 05:44:29 PM PDT 24
Peak memory 217484 kb
Host smart-a819016b-8293-4b97-8120-115551023093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291860978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1291860978
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2994075560
Short name T706
Test name
Test status
Simulation time 39965401 ps
CPU time 1.16 seconds
Started Jul 26 05:44:40 PM PDT 24
Finished Jul 26 05:44:41 PM PDT 24
Peak memory 218568 kb
Host smart-3bd04ede-ba09-4b9c-a0ab-f94ace2fe2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994075560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2994075560
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3422472967
Short name T671
Test name
Test status
Simulation time 41387122 ps
CPU time 1.48 seconds
Started Jul 26 05:44:38 PM PDT 24
Finished Jul 26 05:44:40 PM PDT 24
Peak memory 218604 kb
Host smart-ac7efdd2-0827-4aff-ba48-dbc1902fc70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422472967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3422472967
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3687337243
Short name T475
Test name
Test status
Simulation time 41865921 ps
CPU time 1.14 seconds
Started Jul 26 05:44:27 PM PDT 24
Finished Jul 26 05:44:28 PM PDT 24
Peak memory 219336 kb
Host smart-b4864f44-1417-49a5-9515-6e3190c3d1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687337243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3687337243
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.4055142378
Short name T874
Test name
Test status
Simulation time 52716136 ps
CPU time 1.29 seconds
Started Jul 26 05:44:37 PM PDT 24
Finished Jul 26 05:44:39 PM PDT 24
Peak memory 218308 kb
Host smart-e614bde2-d13d-4d0e-b0bf-98d4f16735ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055142378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.4055142378
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.385999164
Short name T611
Test name
Test status
Simulation time 40351403 ps
CPU time 1.12 seconds
Started Jul 26 05:42:56 PM PDT 24
Finished Jul 26 05:42:57 PM PDT 24
Peak memory 219636 kb
Host smart-2d08a44c-82ec-454c-a43a-33245e2c51ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385999164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.385999164
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2719744058
Short name T664
Test name
Test status
Simulation time 17814486 ps
CPU time 1.05 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:42:59 PM PDT 24
Peak memory 215092 kb
Host smart-6606c3fa-d739-4877-a352-76224faa936d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719744058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2719744058
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.605218088
Short name T527
Test name
Test status
Simulation time 13729675 ps
CPU time 0.94 seconds
Started Jul 26 05:42:56 PM PDT 24
Finished Jul 26 05:42:57 PM PDT 24
Peak memory 216280 kb
Host smart-10b716d3-0518-432c-a5c5-1af2c6784343
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605218088 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.605218088
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2046985320
Short name T836
Test name
Test status
Simulation time 281015970 ps
CPU time 1.16 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:42:59 PM PDT 24
Peak memory 216608 kb
Host smart-36873b04-d53f-443e-bdb2-cdac76e183a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046985320 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2046985320
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.4005664395
Short name T149
Test name
Test status
Simulation time 37944167 ps
CPU time 1.03 seconds
Started Jul 26 05:42:57 PM PDT 24
Finished Jul 26 05:42:58 PM PDT 24
Peak memory 229404 kb
Host smart-54b34fd5-44e3-4fa3-8798-69789cd27645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005664395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.4005664395
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1058611280
Short name T337
Test name
Test status
Simulation time 225134854 ps
CPU time 3.1 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:02 PM PDT 24
Peak memory 220200 kb
Host smart-89cde7f9-da7b-4f69-9105-710ee324b748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058611280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1058611280
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1011779162
Short name T470
Test name
Test status
Simulation time 26944001 ps
CPU time 0.97 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:02 PM PDT 24
Peak memory 215376 kb
Host smart-b6628c3b-f84b-4549-816d-5eac98029d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011779162 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1011779162
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1394689814
Short name T452
Test name
Test status
Simulation time 26020764 ps
CPU time 0.96 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 215164 kb
Host smart-c3ef587f-427e-476f-add7-cc1991c33470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394689814 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1394689814
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3115841878
Short name T41
Test name
Test status
Simulation time 123712121 ps
CPU time 2.89 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 215176 kb
Host smart-5e70ea22-1258-4d97-b974-1a7b4e322cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115841878 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3115841878
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.36766977
Short name T866
Test name
Test status
Simulation time 16675452626 ps
CPU time 431.93 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:50:13 PM PDT 24
Peak memory 217836 kb
Host smart-65cff0e1-08d4-438e-977b-86cb3169a5c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36766977 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.36766977
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.4078926717
Short name T206
Test name
Test status
Simulation time 30349012 ps
CPU time 1.25 seconds
Started Jul 26 05:45:01 PM PDT 24
Finished Jul 26 05:45:02 PM PDT 24
Peak memory 215516 kb
Host smart-0bf93fa5-9b17-4ffa-a909-6ef2bfd23d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078926717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.4078926717
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/191.edn_alert.2779801503
Short name T620
Test name
Test status
Simulation time 60991730 ps
CPU time 1.14 seconds
Started Jul 26 05:44:29 PM PDT 24
Finished Jul 26 05:44:31 PM PDT 24
Peak memory 219380 kb
Host smart-76aeb05e-473e-44c0-bef0-078a5ad2db3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779801503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.2779801503
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/192.edn_alert.3219996422
Short name T702
Test name
Test status
Simulation time 153182632 ps
CPU time 1.23 seconds
Started Jul 26 05:44:34 PM PDT 24
Finished Jul 26 05:44:36 PM PDT 24
Peak memory 218948 kb
Host smart-185d7183-1b3e-4dfc-ae46-d90a9fc4117d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219996422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3219996422
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.321888552
Short name T791
Test name
Test status
Simulation time 39670646 ps
CPU time 1.45 seconds
Started Jul 26 05:44:29 PM PDT 24
Finished Jul 26 05:44:31 PM PDT 24
Peak memory 218340 kb
Host smart-d282ff9b-88af-44a4-aa94-98b95113d137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321888552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.321888552
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.1418516659
Short name T160
Test name
Test status
Simulation time 74372408 ps
CPU time 1.26 seconds
Started Jul 26 05:44:40 PM PDT 24
Finished Jul 26 05:44:41 PM PDT 24
Peak memory 218176 kb
Host smart-18cdb3f5-1662-48af-bac2-a743291f65c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418516659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.1418516659
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.3881414197
Short name T652
Test name
Test status
Simulation time 94408749 ps
CPU time 1.14 seconds
Started Jul 26 05:44:29 PM PDT 24
Finished Jul 26 05:44:31 PM PDT 24
Peak memory 218572 kb
Host smart-536148c9-ff8c-409d-b1f8-f7167cb83768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881414197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3881414197
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3868678809
Short name T982
Test name
Test status
Simulation time 82648005 ps
CPU time 1.14 seconds
Started Jul 26 05:44:38 PM PDT 24
Finished Jul 26 05:44:40 PM PDT 24
Peak memory 219836 kb
Host smart-9f593129-7694-4210-9804-c4c7f51b0697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868678809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3868678809
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.4221058878
Short name T942
Test name
Test status
Simulation time 92872135 ps
CPU time 1.15 seconds
Started Jul 26 05:44:42 PM PDT 24
Finished Jul 26 05:44:44 PM PDT 24
Peak memory 218496 kb
Host smart-34d9d569-bd5d-44bf-9d9b-8929658be03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221058878 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.4221058878
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3609843073
Short name T799
Test name
Test status
Simulation time 123954634 ps
CPU time 1.73 seconds
Started Jul 26 05:44:37 PM PDT 24
Finished Jul 26 05:44:39 PM PDT 24
Peak memory 220120 kb
Host smart-17becdb9-4808-4d31-9cdb-aee9e1657d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609843073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3609843073
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.1414844522
Short name T150
Test name
Test status
Simulation time 47809265 ps
CPU time 1.2 seconds
Started Jul 26 05:44:26 PM PDT 24
Finished Jul 26 05:44:27 PM PDT 24
Peak memory 218384 kb
Host smart-ee246655-b8b8-4274-83c7-901a26ee3f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414844522 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1414844522
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3280857338
Short name T372
Test name
Test status
Simulation time 38706436 ps
CPU time 1.63 seconds
Started Jul 26 05:44:27 PM PDT 24
Finished Jul 26 05:44:29 PM PDT 24
Peak memory 218384 kb
Host smart-66d7cf0c-3b0f-45b3-8ff9-3915f7c2edc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280857338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3280857338
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.1419431435
Short name T181
Test name
Test status
Simulation time 46059497 ps
CPU time 1.19 seconds
Started Jul 26 05:44:26 PM PDT 24
Finished Jul 26 05:44:28 PM PDT 24
Peak memory 218932 kb
Host smart-a5e260d4-9c35-4399-8e81-0e2a7f33c5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419431435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.1419431435
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.2059723678
Short name T789
Test name
Test status
Simulation time 57626386 ps
CPU time 1.17 seconds
Started Jul 26 05:44:27 PM PDT 24
Finished Jul 26 05:44:28 PM PDT 24
Peak memory 217004 kb
Host smart-cbff2348-1fa1-4621-bb00-57432de97385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059723678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2059723678
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.1556029858
Short name T602
Test name
Test status
Simulation time 40239763 ps
CPU time 1.16 seconds
Started Jul 26 05:44:26 PM PDT 24
Finished Jul 26 05:44:27 PM PDT 24
Peak memory 218600 kb
Host smart-897a59c8-3e8b-4b99-b11d-d487bd4db32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556029858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.1556029858
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.680860131
Short name T84
Test name
Test status
Simulation time 43318904 ps
CPU time 1.57 seconds
Started Jul 26 05:44:25 PM PDT 24
Finished Jul 26 05:44:27 PM PDT 24
Peak memory 219768 kb
Host smart-fcab0c6a-5d30-41e0-b429-a9e4f7e277e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680860131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.680860131
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.486697352
Short name T594
Test name
Test status
Simulation time 28790726 ps
CPU time 1.25 seconds
Started Jul 26 05:44:40 PM PDT 24
Finished Jul 26 05:44:42 PM PDT 24
Peak memory 219684 kb
Host smart-74f1e76b-94b3-4b41-a2f4-bf91a54861fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486697352 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.486697352
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.964469830
Short name T508
Test name
Test status
Simulation time 68457524 ps
CPU time 1.4 seconds
Started Jul 26 05:44:40 PM PDT 24
Finished Jul 26 05:44:42 PM PDT 24
Peak memory 218300 kb
Host smart-b451c8bd-304d-4f09-9774-c0a0366d35b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964469830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.964469830
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.678435672
Short name T965
Test name
Test status
Simulation time 24154246 ps
CPU time 1.15 seconds
Started Jul 26 05:42:24 PM PDT 24
Finished Jul 26 05:42:25 PM PDT 24
Peak memory 219732 kb
Host smart-0453578f-9831-4a99-8bb4-e28666e7618e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678435672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.678435672
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2782284937
Short name T547
Test name
Test status
Simulation time 20759619 ps
CPU time 0.87 seconds
Started Jul 26 05:42:23 PM PDT 24
Finished Jul 26 05:42:24 PM PDT 24
Peak memory 206576 kb
Host smart-30a3ce01-e938-4f48-96a1-4bb93cd21068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782284937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2782284937
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1213235441
Short name T373
Test name
Test status
Simulation time 19571950 ps
CPU time 0.84 seconds
Started Jul 26 05:42:20 PM PDT 24
Finished Jul 26 05:42:21 PM PDT 24
Peak memory 216196 kb
Host smart-098909d3-6be6-40e8-b519-8bf3b297d5a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213235441 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1213235441
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3513143871
Short name T915
Test name
Test status
Simulation time 30325638 ps
CPU time 1.16 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:23 PM PDT 24
Peak memory 216948 kb
Host smart-ebc34e52-88bf-461e-8cdd-53d73b83d552
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513143871 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3513143871
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1149388144
Short name T120
Test name
Test status
Simulation time 37307515 ps
CPU time 1.36 seconds
Started Jul 26 05:42:15 PM PDT 24
Finished Jul 26 05:42:17 PM PDT 24
Peak memory 225404 kb
Host smart-66161e74-7a74-4424-bf49-b31daa30b8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149388144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1149388144
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.411675380
Short name T561
Test name
Test status
Simulation time 43702268 ps
CPU time 1.14 seconds
Started Jul 26 05:42:09 PM PDT 24
Finished Jul 26 05:42:11 PM PDT 24
Peak memory 217132 kb
Host smart-5fe86d64-4730-4169-a9f0-38aa89a9acf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411675380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.411675380
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3609176235
Short name T79
Test name
Test status
Simulation time 22313891 ps
CPU time 0.93 seconds
Started Jul 26 05:42:23 PM PDT 24
Finished Jul 26 05:42:24 PM PDT 24
Peak memory 215864 kb
Host smart-601aa22c-a629-4704-b5e8-a171afb6a4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609176235 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3609176235
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3674185917
Short name T957
Test name
Test status
Simulation time 21074227 ps
CPU time 1 seconds
Started Jul 26 05:42:20 PM PDT 24
Finished Jul 26 05:42:21 PM PDT 24
Peak memory 206920 kb
Host smart-b426963a-10df-4fa0-9f5e-5d52161f5042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674185917 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3674185917
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.304221907
Short name T970
Test name
Test status
Simulation time 23316344 ps
CPU time 0.95 seconds
Started Jul 26 05:42:25 PM PDT 24
Finished Jul 26 05:42:26 PM PDT 24
Peak memory 215168 kb
Host smart-8957329c-aa41-478e-b114-bee3da0a59e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304221907 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.304221907
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2840872108
Short name T327
Test name
Test status
Simulation time 1183144414 ps
CPU time 4.46 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:27 PM PDT 24
Peak memory 215236 kb
Host smart-be81c0a0-6dc6-41c2-928f-87b2132155f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840872108 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2840872108
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1701512429
Short name T725
Test name
Test status
Simulation time 93841659336 ps
CPU time 1154.4 seconds
Started Jul 26 05:42:20 PM PDT 24
Finished Jul 26 06:01:35 PM PDT 24
Peak memory 224704 kb
Host smart-c1fa0f75-e9c1-47f8-86ff-74e788ffbe44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701512429 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1701512429
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3017422566
Short name T280
Test name
Test status
Simulation time 50204905 ps
CPU time 1.28 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:42:59 PM PDT 24
Peak memory 218452 kb
Host smart-cadc14e1-247b-40c7-94ff-386167324390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017422566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3017422566
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.902904493
Short name T245
Test name
Test status
Simulation time 158002309 ps
CPU time 1.02 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:42:59 PM PDT 24
Peak memory 206684 kb
Host smart-6d8af59f-d9e4-41ec-9247-9a9913a2d5e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902904493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.902904493
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3669588547
Short name T291
Test name
Test status
Simulation time 54246238 ps
CPU time 1.12 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:02 PM PDT 24
Peak memory 218312 kb
Host smart-b084a44b-4f26-4f0d-b694-fecbed7e8a2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669588547 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3669588547
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1580163580
Short name T2
Test name
Test status
Simulation time 20491204 ps
CPU time 1.09 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 218308 kb
Host smart-22f8d5e4-76b7-45e9-a8e5-91d29eec9221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580163580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1580163580
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2193942208
Short name T431
Test name
Test status
Simulation time 38725953 ps
CPU time 1.44 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:01 PM PDT 24
Peak memory 218408 kb
Host smart-218eba95-fcf9-4ece-8eab-39bb98a97002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193942208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2193942208
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2646520253
Short name T90
Test name
Test status
Simulation time 19783535 ps
CPU time 1.11 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:02 PM PDT 24
Peak memory 215744 kb
Host smart-5aa14f46-d59f-4841-b02e-68cb8127d625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646520253 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2646520253
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.740918797
Short name T375
Test name
Test status
Simulation time 19401068 ps
CPU time 1.04 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:02 PM PDT 24
Peak memory 215160 kb
Host smart-a5d8c025-8f98-4cf6-91f2-98d68f173400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740918797 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.740918797
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3360721430
Short name T385
Test name
Test status
Simulation time 182025215 ps
CPU time 3.18 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 219948 kb
Host smart-b21c4c87-65a3-40e7-94d1-b9e53fcd8966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360721430 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3360721430
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2381427413
Short name T730
Test name
Test status
Simulation time 145060059441 ps
CPU time 816.29 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:56:34 PM PDT 24
Peak memory 220340 kb
Host smart-df250ad8-29f6-485a-941e-bf95f559a659
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381427413 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2381427413
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3033095959
Short name T954
Test name
Test status
Simulation time 67836631 ps
CPU time 1.06 seconds
Started Jul 26 05:44:26 PM PDT 24
Finished Jul 26 05:44:28 PM PDT 24
Peak memory 217236 kb
Host smart-5e8ed20c-7d57-41ad-9d09-077b47ff0212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033095959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3033095959
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.966004879
Short name T856
Test name
Test status
Simulation time 34492293 ps
CPU time 1.5 seconds
Started Jul 26 05:44:26 PM PDT 24
Finished Jul 26 05:44:28 PM PDT 24
Peak memory 218676 kb
Host smart-9b9c739e-5253-456a-a04e-48a7ad7dcec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966004879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.966004879
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1347190247
Short name T433
Test name
Test status
Simulation time 103002711 ps
CPU time 1.22 seconds
Started Jul 26 05:44:28 PM PDT 24
Finished Jul 26 05:44:30 PM PDT 24
Peak memory 219712 kb
Host smart-a9e15726-feb1-42cf-82e2-915706095e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347190247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1347190247
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2003108848
Short name T432
Test name
Test status
Simulation time 57103235 ps
CPU time 1.77 seconds
Started Jul 26 05:44:45 PM PDT 24
Finished Jul 26 05:44:48 PM PDT 24
Peak memory 218348 kb
Host smart-e53384fa-54ff-4ad0-942b-f0bb948a6640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003108848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2003108848
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.748860447
Short name T435
Test name
Test status
Simulation time 72283017 ps
CPU time 1.84 seconds
Started Jul 26 05:44:56 PM PDT 24
Finished Jul 26 05:44:58 PM PDT 24
Peak memory 217324 kb
Host smart-59da5f73-24dc-4c7b-8cc9-04dc5ce830be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748860447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.748860447
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1076070937
Short name T318
Test name
Test status
Simulation time 112399537 ps
CPU time 2.74 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:44:56 PM PDT 24
Peak memory 217528 kb
Host smart-307a9a61-5485-4891-9a3c-50e2b750a0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076070937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1076070937
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2666328885
Short name T912
Test name
Test status
Simulation time 41158710 ps
CPU time 1.41 seconds
Started Jul 26 05:44:51 PM PDT 24
Finished Jul 26 05:44:57 PM PDT 24
Peak memory 219524 kb
Host smart-35baec24-3af3-4c95-a04b-cb29ee254544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666328885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2666328885
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1561129728
Short name T754
Test name
Test status
Simulation time 42771453 ps
CPU time 1.72 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:44:55 PM PDT 24
Peak memory 217356 kb
Host smart-39dd642c-b82b-471b-af97-dceb6a7fa0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561129728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1561129728
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2913327948
Short name T690
Test name
Test status
Simulation time 44458902 ps
CPU time 1.25 seconds
Started Jul 26 05:44:50 PM PDT 24
Finished Jul 26 05:44:52 PM PDT 24
Peak memory 218940 kb
Host smart-566c319e-e5e6-4e66-9dd8-7af7b9764e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913327948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2913327948
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.4285427595
Short name T491
Test name
Test status
Simulation time 34916308 ps
CPU time 1.37 seconds
Started Jul 26 05:44:41 PM PDT 24
Finished Jul 26 05:44:43 PM PDT 24
Peak memory 217480 kb
Host smart-51aa90ff-147d-40a3-ba58-9a448f2ecaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285427595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.4285427595
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3042614841
Short name T174
Test name
Test status
Simulation time 51663242 ps
CPU time 1.12 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 219528 kb
Host smart-a98177a1-6199-47ab-bab5-197a819066d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042614841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3042614841
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.750942780
Short name T714
Test name
Test status
Simulation time 51366704 ps
CPU time 0.91 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:01 PM PDT 24
Peak memory 206568 kb
Host smart-fe5148d1-577a-488c-99df-f952e7f37e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750942780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.750942780
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2272035154
Short name T423
Test name
Test status
Simulation time 66316974 ps
CPU time 1.25 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:01 PM PDT 24
Peak memory 216684 kb
Host smart-8bcced70-1ccf-4488-979e-de76bc29c8dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272035154 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2272035154
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3384678000
Short name T810
Test name
Test status
Simulation time 44576143 ps
CPU time 0.86 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:01 PM PDT 24
Peak memory 218152 kb
Host smart-32771de1-0f1c-4ad5-9532-f1fada0beb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384678000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3384678000
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.943110838
Short name T637
Test name
Test status
Simulation time 100073053 ps
CPU time 1.54 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 217188 kb
Host smart-1392006e-d4aa-4382-96cb-c75afdef5f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943110838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.943110838
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3421329381
Short name T657
Test name
Test status
Simulation time 20656385 ps
CPU time 1.22 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:01 PM PDT 24
Peak memory 223892 kb
Host smart-bfdced32-d2c8-445a-b62c-2d4592f92036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421329381 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3421329381
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2542862490
Short name T679
Test name
Test status
Simulation time 139153335 ps
CPU time 0.91 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:42:59 PM PDT 24
Peak memory 214980 kb
Host smart-024eb3a4-af85-4e4b-b52a-cf1cdd5f079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542862490 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2542862490
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2463059027
Short name T565
Test name
Test status
Simulation time 1213963762 ps
CPU time 4.75 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 217164 kb
Host smart-14e79a1e-ace9-493d-994e-8aaa1c389437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463059027 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2463059027
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2144461358
Short name T22
Test name
Test status
Simulation time 215539619944 ps
CPU time 1209.7 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 06:03:09 PM PDT 24
Peak memory 231924 kb
Host smart-8cf9ff4c-e9f2-4824-ab09-c299e16741d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144461358 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2144461358
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.99875262
Short name T428
Test name
Test status
Simulation time 142314376 ps
CPU time 1.67 seconds
Started Jul 26 05:44:46 PM PDT 24
Finished Jul 26 05:44:48 PM PDT 24
Peak memory 220140 kb
Host smart-f466e288-a35c-45d8-88bf-3d7398220dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99875262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.99875262
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2401389364
Short name T456
Test name
Test status
Simulation time 35936377 ps
CPU time 1.47 seconds
Started Jul 26 05:44:51 PM PDT 24
Finished Jul 26 05:44:53 PM PDT 24
Peak memory 218392 kb
Host smart-4d6f5ed2-c665-4b82-b12b-ec4f5ba491be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401389364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2401389364
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3505754647
Short name T621
Test name
Test status
Simulation time 36150330 ps
CPU time 1.44 seconds
Started Jul 26 05:44:39 PM PDT 24
Finished Jul 26 05:44:41 PM PDT 24
Peak memory 217252 kb
Host smart-68b94721-c32f-4850-9414-efe15dfe4ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505754647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3505754647
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2125501323
Short name T418
Test name
Test status
Simulation time 39303692 ps
CPU time 1.72 seconds
Started Jul 26 05:44:39 PM PDT 24
Finished Jul 26 05:44:41 PM PDT 24
Peak memory 218472 kb
Host smart-8cdabe16-684b-4e8b-8dd5-cc8643e5c51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125501323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2125501323
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3155041146
Short name T853
Test name
Test status
Simulation time 48351142 ps
CPU time 1.7 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:44:55 PM PDT 24
Peak memory 217552 kb
Host smart-36bbcefe-6855-450e-984b-20bf7f083e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155041146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3155041146
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1522933969
Short name T310
Test name
Test status
Simulation time 4437670031 ps
CPU time 73.91 seconds
Started Jul 26 05:44:39 PM PDT 24
Finished Jul 26 05:45:54 PM PDT 24
Peak memory 215264 kb
Host smart-623ab91d-3d13-4189-bd9d-d42b0564c556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522933969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1522933969
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.788724478
Short name T519
Test name
Test status
Simulation time 35258278 ps
CPU time 1.3 seconds
Started Jul 26 05:44:42 PM PDT 24
Finished Jul 26 05:44:44 PM PDT 24
Peak memory 218244 kb
Host smart-09d28488-ffb5-448b-aa90-3faf3047c6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788724478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.788724478
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1624294632
Short name T763
Test name
Test status
Simulation time 173868878 ps
CPU time 2.48 seconds
Started Jul 26 05:44:43 PM PDT 24
Finished Jul 26 05:44:46 PM PDT 24
Peak memory 217360 kb
Host smart-4886888d-3850-4382-bc78-68083f3e08e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624294632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1624294632
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2510699279
Short name T249
Test name
Test status
Simulation time 27000556 ps
CPU time 1.22 seconds
Started Jul 26 05:44:46 PM PDT 24
Finished Jul 26 05:44:47 PM PDT 24
Peak memory 218456 kb
Host smart-f43f6f06-455a-4f59-892f-3969c82e0e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510699279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2510699279
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1915203757
Short name T381
Test name
Test status
Simulation time 45989190 ps
CPU time 1.11 seconds
Started Jul 26 05:44:44 PM PDT 24
Finished Jul 26 05:44:46 PM PDT 24
Peak memory 217156 kb
Host smart-c4cd4835-a529-4401-8889-3b34682fe99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915203757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1915203757
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.2069455161
Short name T656
Test name
Test status
Simulation time 30925613 ps
CPU time 0.95 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 214660 kb
Host smart-10971fc5-ae51-40c8-9c7b-980899a6595f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069455161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2069455161
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3496927307
Short name T902
Test name
Test status
Simulation time 24313843 ps
CPU time 0.88 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 216052 kb
Host smart-73186f5e-e757-4fb4-b78a-b8df2a0241fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496927307 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3496927307
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.3784381462
Short name T110
Test name
Test status
Simulation time 31309973 ps
CPU time 1.26 seconds
Started Jul 26 05:43:05 PM PDT 24
Finished Jul 26 05:43:07 PM PDT 24
Peak memory 217032 kb
Host smart-53685ca2-aa38-444a-944c-0a3825733f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784381462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3784381462
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3765416110
Short name T897
Test name
Test status
Simulation time 67310456 ps
CPU time 2.38 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 218772 kb
Host smart-a987369e-af4c-41cd-a4c5-dd5f85de741e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765416110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3765416110
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1830356621
Short name T746
Test name
Test status
Simulation time 28557022 ps
CPU time 0.9 seconds
Started Jul 26 05:42:58 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 215436 kb
Host smart-c70fdbeb-c9f0-4836-8bfa-90527e7c439a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830356621 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1830356621
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1104361642
Short name T908
Test name
Test status
Simulation time 25202871 ps
CPU time 0.97 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 215088 kb
Host smart-1a9c67d1-291e-4db7-a019-4c4796708cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104361642 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1104361642
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2532038929
Short name T374
Test name
Test status
Simulation time 349009297 ps
CPU time 5.78 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:06 PM PDT 24
Peak memory 219700 kb
Host smart-9bc98772-fee4-4b26-a5e0-9319fd3c14e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532038929 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2532038929
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1011461175
Short name T522
Test name
Test status
Simulation time 195995130872 ps
CPU time 871.81 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:57:33 PM PDT 24
Peak memory 223656 kb
Host smart-3ffc9204-3566-43cf-aeef-4382015dc926
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011461175 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1011461175
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3013362815
Short name T392
Test name
Test status
Simulation time 54629014 ps
CPU time 1.38 seconds
Started Jul 26 05:44:46 PM PDT 24
Finished Jul 26 05:44:48 PM PDT 24
Peak memory 218476 kb
Host smart-3e06bc16-446e-4395-a921-d4538a118a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013362815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3013362815
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1785929405
Short name T641
Test name
Test status
Simulation time 81193751 ps
CPU time 1.52 seconds
Started Jul 26 05:44:49 PM PDT 24
Finished Jul 26 05:44:51 PM PDT 24
Peak memory 218596 kb
Host smart-8ad67bc8-c5bd-4d22-b583-ec3b985055bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785929405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1785929405
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3474711404
Short name T533
Test name
Test status
Simulation time 30159764 ps
CPU time 1.06 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:44:48 PM PDT 24
Peak memory 219680 kb
Host smart-332de9d5-6d0d-4a93-9bd9-19a7b4799bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474711404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3474711404
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1169049244
Short name T476
Test name
Test status
Simulation time 41330758 ps
CPU time 1.25 seconds
Started Jul 26 05:44:54 PM PDT 24
Finished Jul 26 05:44:55 PM PDT 24
Peak memory 217444 kb
Host smart-a5e8d212-cc36-4a4d-91ed-f34aebad0cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169049244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1169049244
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1880688557
Short name T328
Test name
Test status
Simulation time 45789312 ps
CPU time 1.66 seconds
Started Jul 26 05:44:40 PM PDT 24
Finished Jul 26 05:44:42 PM PDT 24
Peak memory 218300 kb
Host smart-01223f12-f3e8-4551-ac91-b2c19866fb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880688557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1880688557
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.4240490581
Short name T760
Test name
Test status
Simulation time 49679297 ps
CPU time 1.35 seconds
Started Jul 26 05:44:45 PM PDT 24
Finished Jul 26 05:44:47 PM PDT 24
Peak memory 218476 kb
Host smart-9e376622-9977-498f-ab33-681add84d560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240490581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.4240490581
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2701199924
Short name T292
Test name
Test status
Simulation time 39928845 ps
CPU time 1.63 seconds
Started Jul 26 05:44:37 PM PDT 24
Finished Jul 26 05:44:39 PM PDT 24
Peak memory 218504 kb
Host smart-8cd5beef-98ec-4a87-8ece-6aba3b9704bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701199924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2701199924
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2544883832
Short name T320
Test name
Test status
Simulation time 73623355 ps
CPU time 1.47 seconds
Started Jul 26 05:44:46 PM PDT 24
Finished Jul 26 05:44:48 PM PDT 24
Peak memory 218548 kb
Host smart-f3fd87ff-555e-4a1e-9e3c-f4b760fb8589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544883832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2544883832
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3316405947
Short name T545
Test name
Test status
Simulation time 103367736 ps
CPU time 1.29 seconds
Started Jul 26 05:44:44 PM PDT 24
Finished Jul 26 05:44:46 PM PDT 24
Peak memory 218612 kb
Host smart-05bbaff3-c9f6-4bf9-b40a-54089e7a95e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316405947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3316405947
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2785218614
Short name T477
Test name
Test status
Simulation time 25439027 ps
CPU time 1.24 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 218356 kb
Host smart-d7ce9099-40d4-4090-b782-b6679fd77410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785218614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2785218614
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.975178763
Short name T443
Test name
Test status
Simulation time 83711116 ps
CPU time 0.9 seconds
Started Jul 26 05:42:48 PM PDT 24
Finished Jul 26 05:42:49 PM PDT 24
Peak memory 214804 kb
Host smart-c654a287-4b52-44b3-90c6-7b618e09d42f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975178763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.975178763
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2820240432
Short name T104
Test name
Test status
Simulation time 41521932 ps
CPU time 0.88 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 216200 kb
Host smart-6391be8d-0b73-4bc5-a7fe-5288162c5935
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820240432 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2820240432
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3518797690
Short name T552
Test name
Test status
Simulation time 111774068 ps
CPU time 1.29 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:01 PM PDT 24
Peak memory 219732 kb
Host smart-b713f6d4-c464-47ec-88e3-538a03a0b161
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518797690 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3518797690
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.600991116
Short name T752
Test name
Test status
Simulation time 34446824 ps
CPU time 0.96 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 219972 kb
Host smart-87782601-c83d-4040-b3d7-0bdb367eb60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600991116 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.600991116
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2033457722
Short name T505
Test name
Test status
Simulation time 125169336 ps
CPU time 1.15 seconds
Started Jul 26 05:43:05 PM PDT 24
Finished Jul 26 05:43:07 PM PDT 24
Peak memory 219780 kb
Host smart-3f063b6d-ed21-4799-b9ae-06fda65e066d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033457722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2033457722
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3615051225
Short name T862
Test name
Test status
Simulation time 34330420 ps
CPU time 0.92 seconds
Started Jul 26 05:43:05 PM PDT 24
Finished Jul 26 05:43:07 PM PDT 24
Peak memory 215564 kb
Host smart-54315629-71d9-4260-9bf4-a22f04be7c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615051225 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3615051225
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3533931538
Short name T859
Test name
Test status
Simulation time 14725107 ps
CPU time 0.94 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:02 PM PDT 24
Peak memory 215192 kb
Host smart-5f513c9f-8538-4323-9216-300fb9baf4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533931538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3533931538
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2212487369
Short name T322
Test name
Test status
Simulation time 249022799 ps
CPU time 4.79 seconds
Started Jul 26 05:43:05 PM PDT 24
Finished Jul 26 05:43:10 PM PDT 24
Peak memory 215132 kb
Host smart-22e4463e-dde6-4bdd-8913-8a1c192c5451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212487369 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2212487369
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3090357112
Short name T236
Test name
Test status
Simulation time 110524191548 ps
CPU time 1275.58 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 06:04:18 PM PDT 24
Peak memory 223468 kb
Host smart-e8ea793f-273e-403e-b17c-01f05de086a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090357112 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3090357112
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.3699448942
Short name T753
Test name
Test status
Simulation time 77285435 ps
CPU time 1.22 seconds
Started Jul 26 05:44:42 PM PDT 24
Finished Jul 26 05:44:43 PM PDT 24
Peak memory 218356 kb
Host smart-62444bd8-e736-45d8-a0a5-e7b6387b77b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699448942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3699448942
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3120875327
Short name T813
Test name
Test status
Simulation time 61243905 ps
CPU time 1.61 seconds
Started Jul 26 05:44:54 PM PDT 24
Finished Jul 26 05:44:55 PM PDT 24
Peak memory 217356 kb
Host smart-44cd534d-6a39-44c9-a8d0-ffe8d4230ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120875327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3120875327
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3441398388
Short name T918
Test name
Test status
Simulation time 104397551 ps
CPU time 1.33 seconds
Started Jul 26 05:44:37 PM PDT 24
Finished Jul 26 05:44:38 PM PDT 24
Peak memory 219592 kb
Host smart-c56af7af-545a-477c-833e-b774a5d0db96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441398388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3441398388
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.658520419
Short name T944
Test name
Test status
Simulation time 46865708 ps
CPU time 1.66 seconds
Started Jul 26 05:44:46 PM PDT 24
Finished Jul 26 05:44:48 PM PDT 24
Peak memory 217360 kb
Host smart-2d221454-31b0-4a09-9f30-75327da172df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658520419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.658520419
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1675316295
Short name T988
Test name
Test status
Simulation time 35520964 ps
CPU time 1.41 seconds
Started Jul 26 05:44:45 PM PDT 24
Finished Jul 26 05:44:47 PM PDT 24
Peak memory 218416 kb
Host smart-3ffdc0e3-d98b-49a2-8b86-b552f3cbdb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675316295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1675316295
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2114431993
Short name T425
Test name
Test status
Simulation time 39406650 ps
CPU time 1.27 seconds
Started Jul 26 05:44:49 PM PDT 24
Finished Jul 26 05:44:51 PM PDT 24
Peak memory 219708 kb
Host smart-f4cb1f4e-0697-4845-a064-f14bffa0a0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114431993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2114431993
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.180186630
Short name T995
Test name
Test status
Simulation time 54345040 ps
CPU time 1.13 seconds
Started Jul 26 05:44:37 PM PDT 24
Finished Jul 26 05:44:39 PM PDT 24
Peak memory 217364 kb
Host smart-ca7b0255-3390-4883-8e51-6f2f7ddf0798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180186630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.180186630
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.8172806
Short name T683
Test name
Test status
Simulation time 66600498 ps
CPU time 1.33 seconds
Started Jul 26 05:44:55 PM PDT 24
Finished Jul 26 05:44:56 PM PDT 24
Peak memory 218596 kb
Host smart-19fe65e6-b3c0-4f4d-ac60-d97577e86edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8172806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.8172806
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2883071108
Short name T824
Test name
Test status
Simulation time 49456152 ps
CPU time 1.2 seconds
Started Jul 26 05:44:45 PM PDT 24
Finished Jul 26 05:44:46 PM PDT 24
Peak memory 217280 kb
Host smart-c855af46-9712-498c-a2c8-53d318dd7218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883071108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2883071108
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2343890934
Short name T502
Test name
Test status
Simulation time 38181045 ps
CPU time 1.39 seconds
Started Jul 26 05:44:50 PM PDT 24
Finished Jul 26 05:44:51 PM PDT 24
Peak memory 218432 kb
Host smart-bc3eb97d-f9ec-4ab9-abdd-10fce0e25c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343890934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2343890934
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2741984988
Short name T486
Test name
Test status
Simulation time 62666208 ps
CPU time 1.06 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 219704 kb
Host smart-826a54a4-5ed6-4766-ae16-de4b82e7e878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741984988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2741984988
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.909411807
Short name T878
Test name
Test status
Simulation time 59982959 ps
CPU time 0.95 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 206608 kb
Host smart-1ae6d5e5-daf8-4c7b-aacc-2fcbbe460cb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909411807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.909411807
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1517360517
Short name T112
Test name
Test status
Simulation time 34373086 ps
CPU time 0.86 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 216036 kb
Host smart-4a9fdf98-7388-4ce5-a366-d607fafc19cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517360517 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1517360517
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3009462172
Short name T525
Test name
Test status
Simulation time 64110702 ps
CPU time 1.35 seconds
Started Jul 26 05:43:04 PM PDT 24
Finished Jul 26 05:43:06 PM PDT 24
Peak memory 216828 kb
Host smart-855d018c-e8ae-4ef1-83fa-c2ff9b7451ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009462172 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3009462172
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1237049496
Short name T548
Test name
Test status
Simulation time 34898949 ps
CPU time 0.9 seconds
Started Jul 26 05:43:04 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 218208 kb
Host smart-208e67c9-83aa-4153-9370-f6b501fb029a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237049496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1237049496
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1745797123
Short name T700
Test name
Test status
Simulation time 53679132 ps
CPU time 1.4 seconds
Started Jul 26 05:42:56 PM PDT 24
Finished Jul 26 05:42:57 PM PDT 24
Peak memory 219964 kb
Host smart-b1b853cf-2815-494a-9992-4fbb112fa1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745797123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1745797123
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3625471376
Short name T834
Test name
Test status
Simulation time 22072567 ps
CPU time 1.16 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 215288 kb
Host smart-3cc9fc59-3ce0-4d54-9d82-1f1b1875ef08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625471376 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3625471376
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3107148105
Short name T806
Test name
Test status
Simulation time 19777988 ps
CPU time 0.9 seconds
Started Jul 26 05:42:56 PM PDT 24
Finished Jul 26 05:42:57 PM PDT 24
Peak memory 215100 kb
Host smart-110babe5-1e33-4be5-8c85-fb689cf3f0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107148105 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3107148105
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1242557837
Short name T941
Test name
Test status
Simulation time 131017398 ps
CPU time 2.89 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 215160 kb
Host smart-bff9d8e3-c5c1-432b-8493-7e510cb3d67b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242557837 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1242557837
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1839563861
Short name T237
Test name
Test status
Simulation time 48985560793 ps
CPU time 623.08 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:53:24 PM PDT 24
Peak memory 220924 kb
Host smart-3c08b2e2-f064-4aeb-9c2c-f0d2a7cc15e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839563861 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1839563861
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2561907960
Short name T351
Test name
Test status
Simulation time 66943126 ps
CPU time 1.07 seconds
Started Jul 26 05:44:38 PM PDT 24
Finished Jul 26 05:44:39 PM PDT 24
Peak memory 217092 kb
Host smart-e1d62204-c80c-4acc-b83d-b1e5f7c578de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561907960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2561907960
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.513509214
Short name T854
Test name
Test status
Simulation time 77708037 ps
CPU time 2.69 seconds
Started Jul 26 05:44:42 PM PDT 24
Finished Jul 26 05:44:45 PM PDT 24
Peak memory 220016 kb
Host smart-370e1a6b-911e-406b-bc84-cf482aa83f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513509214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.513509214
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3213517288
Short name T317
Test name
Test status
Simulation time 136037179 ps
CPU time 2.73 seconds
Started Jul 26 05:44:54 PM PDT 24
Finished Jul 26 05:44:57 PM PDT 24
Peak memory 220156 kb
Host smart-4fc97381-7f99-42c7-8f1b-3020defba026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213517288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3213517288
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.889154900
Short name T685
Test name
Test status
Simulation time 100453905 ps
CPU time 1.53 seconds
Started Jul 26 05:44:44 PM PDT 24
Finished Jul 26 05:44:46 PM PDT 24
Peak memory 217116 kb
Host smart-257b151a-8501-424d-ba29-6ea688c00635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889154900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.889154900
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3280925369
Short name T71
Test name
Test status
Simulation time 39584346 ps
CPU time 1.39 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:44:54 PM PDT 24
Peak memory 217252 kb
Host smart-a7f3d2a5-29e9-4339-866c-955b54e99710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280925369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3280925369
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1943837906
Short name T446
Test name
Test status
Simulation time 390904155 ps
CPU time 3.45 seconds
Started Jul 26 05:44:46 PM PDT 24
Finished Jul 26 05:44:49 PM PDT 24
Peak memory 217664 kb
Host smart-3458141e-cdb8-495f-a84c-93f7417033a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943837906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1943837906
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2145943734
Short name T382
Test name
Test status
Simulation time 37244876 ps
CPU time 1.41 seconds
Started Jul 26 05:44:37 PM PDT 24
Finished Jul 26 05:44:38 PM PDT 24
Peak memory 218300 kb
Host smart-f67ccc3e-88b5-466c-8e5e-81193a90a177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145943734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2145943734
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.4022089864
Short name T321
Test name
Test status
Simulation time 39643511 ps
CPU time 1.59 seconds
Started Jul 26 05:44:46 PM PDT 24
Finished Jul 26 05:44:48 PM PDT 24
Peak memory 218348 kb
Host smart-7ac753a7-415a-468c-b608-5bea7595479f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022089864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.4022089864
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.396291420
Short name T531
Test name
Test status
Simulation time 89543777 ps
CPU time 1.41 seconds
Started Jul 26 05:44:52 PM PDT 24
Finished Jul 26 05:44:54 PM PDT 24
Peak memory 218492 kb
Host smart-0c4a99d5-4ac7-4e07-9090-d9f888c3ac53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396291420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.396291420
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.399701029
Short name T976
Test name
Test status
Simulation time 44806083 ps
CPU time 0.9 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 206624 kb
Host smart-136e0b19-78a8-411d-a09b-a9c673121442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399701029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.399701029
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1567556541
Short name T537
Test name
Test status
Simulation time 21594730 ps
CPU time 0.89 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 207076 kb
Host smart-387de9fd-1153-46b6-8146-406a44ccc2ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567556541 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1567556541
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.4277042933
Short name T493
Test name
Test status
Simulation time 103748796 ps
CPU time 1.37 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 216628 kb
Host smart-c90b8345-d979-43e9-80e2-003a905449d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277042933 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.4277042933
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3607857236
Short name T597
Test name
Test status
Simulation time 29926253 ps
CPU time 1.26 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 219500 kb
Host smart-dbc10d93-1658-4347-96f9-62f6e4e3323a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607857236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3607857236
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.736883413
Short name T846
Test name
Test status
Simulation time 139292273 ps
CPU time 1.21 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 217052 kb
Host smart-ff37cb93-214e-45cf-925b-21d51ec4c31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736883413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.736883413
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_smoke.3524667298
Short name T132
Test name
Test status
Simulation time 51153260 ps
CPU time 0.98 seconds
Started Jul 26 05:43:04 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 215124 kb
Host smart-18b7b89b-e5e0-431f-a668-eb69378bce63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524667298 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3524667298
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1796421150
Short name T308
Test name
Test status
Simulation time 313076427 ps
CPU time 6.13 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:10 PM PDT 24
Peak memory 216764 kb
Host smart-d82896a1-5ec9-4fa1-8cda-f45c024c1f45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796421150 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1796421150
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1018405174
Short name T907
Test name
Test status
Simulation time 70914924790 ps
CPU time 1161.3 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 06:02:25 PM PDT 24
Peak memory 221932 kb
Host smart-2a136e1d-e275-48c6-bbe0-049b97eceeee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018405174 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1018405174
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.54508997
Short name T398
Test name
Test status
Simulation time 49870891 ps
CPU time 1.81 seconds
Started Jul 26 05:44:51 PM PDT 24
Finished Jul 26 05:44:53 PM PDT 24
Peak memory 218536 kb
Host smart-2c7469f6-a1af-47f3-a537-61c566568ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54508997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.54508997
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.875254073
Short name T879
Test name
Test status
Simulation time 110492508 ps
CPU time 1.51 seconds
Started Jul 26 05:44:38 PM PDT 24
Finished Jul 26 05:44:40 PM PDT 24
Peak memory 218708 kb
Host smart-22bd0cc5-6e2b-45f4-8c58-a8938504b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875254073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.875254073
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1307926244
Short name T539
Test name
Test status
Simulation time 41185682 ps
CPU time 1.12 seconds
Started Jul 26 05:44:45 PM PDT 24
Finished Jul 26 05:44:46 PM PDT 24
Peak memory 217244 kb
Host smart-7b828ec6-35bc-4b94-8f91-4ee77848697a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307926244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1307926244
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.548673519
Short name T904
Test name
Test status
Simulation time 60226833 ps
CPU time 1.07 seconds
Started Jul 26 05:44:52 PM PDT 24
Finished Jul 26 05:44:54 PM PDT 24
Peak memory 219800 kb
Host smart-85b1b48d-f2d3-4a00-bc78-6aba806a3ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548673519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.548673519
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.636413264
Short name T518
Test name
Test status
Simulation time 89603512 ps
CPU time 1.17 seconds
Started Jul 26 05:44:55 PM PDT 24
Finished Jul 26 05:44:56 PM PDT 24
Peak memory 218520 kb
Host smart-e905b7f0-3a46-487b-b009-7a0179a72402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636413264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.636413264
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3461411832
Short name T511
Test name
Test status
Simulation time 330246361 ps
CPU time 1.33 seconds
Started Jul 26 05:44:40 PM PDT 24
Finished Jul 26 05:44:42 PM PDT 24
Peak memory 218384 kb
Host smart-19730abd-81ac-4704-890e-a15ee715ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461411832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3461411832
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.804982997
Short name T348
Test name
Test status
Simulation time 47213829 ps
CPU time 1.17 seconds
Started Jul 26 05:44:46 PM PDT 24
Finished Jul 26 05:44:47 PM PDT 24
Peak memory 219780 kb
Host smart-2bd9194f-6935-4f76-80bf-3aa133553e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804982997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.804982997
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2836776932
Short name T312
Test name
Test status
Simulation time 51771140 ps
CPU time 1.64 seconds
Started Jul 26 05:44:38 PM PDT 24
Finished Jul 26 05:44:40 PM PDT 24
Peak memory 218516 kb
Host smart-5bff8789-eed5-4bee-9ec7-0eef50a60e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836776932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2836776932
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2396046461
Short name T930
Test name
Test status
Simulation time 95693811 ps
CPU time 1.71 seconds
Started Jul 26 05:44:40 PM PDT 24
Finished Jul 26 05:44:42 PM PDT 24
Peak memory 215120 kb
Host smart-e87bad81-0d25-4e48-b9e9-94cc482196cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396046461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2396046461
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2298995448
Short name T376
Test name
Test status
Simulation time 89575597 ps
CPU time 1.2 seconds
Started Jul 26 05:44:42 PM PDT 24
Finished Jul 26 05:44:44 PM PDT 24
Peak memory 218812 kb
Host smart-1747275f-ee24-4020-b560-c14df83ac0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298995448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2298995448
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1087533234
Short name T556
Test name
Test status
Simulation time 115034661 ps
CPU time 1.18 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 220112 kb
Host smart-48521c5f-671c-4a9d-ae54-eb29ca5ca8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087533234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1087533234
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.107840965
Short name T383
Test name
Test status
Simulation time 22700372 ps
CPU time 0.86 seconds
Started Jul 26 05:43:05 PM PDT 24
Finished Jul 26 05:43:06 PM PDT 24
Peak memory 206864 kb
Host smart-65ea5c3c-bde0-405a-a0eb-8bacd616dd4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107840965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.107840965
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2150847859
Short name T100
Test name
Test status
Simulation time 50563140 ps
CPU time 1.52 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:01 PM PDT 24
Peak memory 216652 kb
Host smart-5099ba43-c5db-4650-9abf-d50a2b22a055
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150847859 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2150847859
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3414961644
Short name T550
Test name
Test status
Simulation time 18167632 ps
CPU time 1.17 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:02 PM PDT 24
Peak memory 223940 kb
Host smart-07003fda-0597-48e4-ad1d-4564261e568e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414961644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3414961644
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3244497051
Short name T394
Test name
Test status
Simulation time 86293765 ps
CPU time 1.14 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 217236 kb
Host smart-6e7bda1b-1101-4e0e-a5b4-606d52da7719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244497051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3244497051
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.9198765
Short name T542
Test name
Test status
Simulation time 22743229 ps
CPU time 1.12 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 223864 kb
Host smart-9d4ecd85-ab04-4a0a-b966-b7f1c7730fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9198765 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.9198765
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.4077919700
Short name T925
Test name
Test status
Simulation time 26912459 ps
CPU time 0.89 seconds
Started Jul 26 05:43:09 PM PDT 24
Finished Jul 26 05:43:10 PM PDT 24
Peak memory 215176 kb
Host smart-3b7ae370-929a-4eec-9346-f79d975d9c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077919700 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.4077919700
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1805180321
Short name T618
Test name
Test status
Simulation time 421002775 ps
CPU time 4.7 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 217044 kb
Host smart-1d3cfed4-18a0-42c8-954b-3a98cef72ac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805180321 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1805180321
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.897084709
Short name T694
Test name
Test status
Simulation time 112164209934 ps
CPU time 681.6 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:54:25 PM PDT 24
Peak memory 220720 kb
Host smart-56b8e529-fe3f-4223-b8b7-e5d836a3572b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897084709 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.897084709
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.4078969206
Short name T516
Test name
Test status
Simulation time 71824838 ps
CPU time 1.8 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:44:55 PM PDT 24
Peak memory 218360 kb
Host smart-aa570fc2-9a37-417d-8ef8-3ccad5253d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078969206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.4078969206
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3460842691
Short name T711
Test name
Test status
Simulation time 33387058 ps
CPU time 1.34 seconds
Started Jul 26 05:44:44 PM PDT 24
Finished Jul 26 05:44:45 PM PDT 24
Peak memory 217172 kb
Host smart-46be80a2-a2eb-4518-8459-b9e7557a0c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460842691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3460842691
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3088002787
Short name T536
Test name
Test status
Simulation time 189171221 ps
CPU time 1.24 seconds
Started Jul 26 05:44:44 PM PDT 24
Finished Jul 26 05:44:45 PM PDT 24
Peak memory 217300 kb
Host smart-03c76434-d7f6-4ab0-bc53-651705951ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088002787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3088002787
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2103391910
Short name T474
Test name
Test status
Simulation time 71150221 ps
CPU time 1.41 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:44:48 PM PDT 24
Peak memory 218544 kb
Host smart-698e981d-307c-4814-8b30-b03aeb27ecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103391910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2103391910
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2640173580
Short name T504
Test name
Test status
Simulation time 34080957 ps
CPU time 1.49 seconds
Started Jul 26 05:44:45 PM PDT 24
Finished Jul 26 05:44:46 PM PDT 24
Peak memory 218496 kb
Host smart-13fb7af3-4ab0-4753-b2a1-00677e572057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640173580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2640173580
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.456126756
Short name T722
Test name
Test status
Simulation time 160270050 ps
CPU time 1.01 seconds
Started Jul 26 05:44:49 PM PDT 24
Finished Jul 26 05:44:50 PM PDT 24
Peak memory 217360 kb
Host smart-322e11a8-7876-4329-a420-c9ffcab2547b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456126756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.456126756
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.658591928
Short name T485
Test name
Test status
Simulation time 189418840 ps
CPU time 1.74 seconds
Started Jul 26 05:44:54 PM PDT 24
Finished Jul 26 05:44:56 PM PDT 24
Peak memory 218920 kb
Host smart-ba24fe74-5487-4ca3-8139-b6322320bb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658591928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.658591928
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2477228680
Short name T517
Test name
Test status
Simulation time 46550348 ps
CPU time 1.39 seconds
Started Jul 26 05:44:46 PM PDT 24
Finished Jul 26 05:44:48 PM PDT 24
Peak memory 219912 kb
Host smart-ab45c879-cfad-404f-8cd1-30c3e4dddf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477228680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2477228680
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.552027967
Short name T807
Test name
Test status
Simulation time 96573138 ps
CPU time 1.48 seconds
Started Jul 26 05:44:45 PM PDT 24
Finished Jul 26 05:44:47 PM PDT 24
Peak memory 220200 kb
Host smart-ad5af4ce-46ec-4d9a-8199-096dd1321905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552027967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.552027967
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1440174331
Short name T501
Test name
Test status
Simulation time 55745047 ps
CPU time 2.03 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:44:49 PM PDT 24
Peak memory 219924 kb
Host smart-1626c0e0-a82a-4d2f-a713-fed76377f99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440174331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1440174331
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.4086769242
Short name T923
Test name
Test status
Simulation time 70494388 ps
CPU time 1.3 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:02 PM PDT 24
Peak memory 218552 kb
Host smart-c59eb4f8-2558-4969-ab08-5ffb539ac614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086769242 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.4086769242
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1204455486
Short name T51
Test name
Test status
Simulation time 20439214 ps
CPU time 1.06 seconds
Started Jul 26 05:43:10 PM PDT 24
Finished Jul 26 05:43:11 PM PDT 24
Peak memory 215088 kb
Host smart-ebf52fe7-bc32-4ade-a80d-73527aad7d0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204455486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1204455486
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.685197167
Short name T33
Test name
Test status
Simulation time 20878919 ps
CPU time 0.88 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 215236 kb
Host smart-05d47deb-e3c1-497c-832b-f00482430291
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685197167 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.685197167
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.917212554
Short name T670
Test name
Test status
Simulation time 35149856 ps
CPU time 1.28 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 216604 kb
Host smart-f0bf0a3a-adce-46b7-89e2-009952604544
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917212554 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.917212554
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.590336861
Short name T710
Test name
Test status
Simulation time 26313375 ps
CPU time 1 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 219464 kb
Host smart-d9e63bfb-5e9b-4189-b3fb-933ddc2179b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590336861 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.590336861
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2610691861
Short name T314
Test name
Test status
Simulation time 51116306 ps
CPU time 1.73 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 220096 kb
Host smart-b01513bf-cd00-4a57-bf19-a81ccff6a244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610691861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2610691861
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_smoke.570859533
Short name T599
Test name
Test status
Simulation time 43685191 ps
CPU time 0.95 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 215156 kb
Host smart-fd02a1c2-1416-4229-a5ef-a595ac85789a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570859533 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.570859533
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.316854845
Short name T723
Test name
Test status
Simulation time 128389502 ps
CPU time 3.03 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 217160 kb
Host smart-7c2ac385-c52b-4522-90ab-20b9cef90da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316854845 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.316854845
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1691078572
Short name T776
Test name
Test status
Simulation time 208451329899 ps
CPU time 830.68 seconds
Started Jul 26 05:43:06 PM PDT 24
Finished Jul 26 05:56:57 PM PDT 24
Peak memory 220492 kb
Host smart-e4562e00-e99a-4a4f-92ed-1ae7f252d690
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691078572 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1691078572
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2469969304
Short name T887
Test name
Test status
Simulation time 92303477 ps
CPU time 1.75 seconds
Started Jul 26 05:44:46 PM PDT 24
Finished Jul 26 05:44:48 PM PDT 24
Peak memory 219824 kb
Host smart-9318964e-61cd-440b-a0cb-5417ed8ad0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469969304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2469969304
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2034444029
Short name T934
Test name
Test status
Simulation time 49201056 ps
CPU time 1.25 seconds
Started Jul 26 05:44:48 PM PDT 24
Finished Jul 26 05:44:49 PM PDT 24
Peak memory 219588 kb
Host smart-ba1b914c-7e20-4bfd-b10c-a402d1bd7671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034444029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2034444029
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3035613885
Short name T627
Test name
Test status
Simulation time 42740685 ps
CPU time 1.46 seconds
Started Jul 26 05:44:41 PM PDT 24
Finished Jul 26 05:44:43 PM PDT 24
Peak memory 218216 kb
Host smart-e0ea13a1-6448-4cf1-b67f-5eb7b058f6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035613885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3035613885
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3727335197
Short name T794
Test name
Test status
Simulation time 59020083 ps
CPU time 1.64 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:44:49 PM PDT 24
Peak memory 218696 kb
Host smart-1cf7cc61-c22b-4d08-9ad9-59cbc3bffcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727335197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3727335197
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.4125301881
Short name T927
Test name
Test status
Simulation time 34886696 ps
CPU time 1.54 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:44:49 PM PDT 24
Peak memory 217212 kb
Host smart-f7d8ef22-fdce-4d10-8048-9ef9a89da5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125301881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.4125301881
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3744027431
Short name T768
Test name
Test status
Simulation time 84213795 ps
CPU time 2.74 seconds
Started Jul 26 05:44:44 PM PDT 24
Finished Jul 26 05:44:47 PM PDT 24
Peak memory 219408 kb
Host smart-fa21a8bc-1906-4d5b-8eb0-7c11da706efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744027431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3744027431
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.4025253756
Short name T434
Test name
Test status
Simulation time 51913026 ps
CPU time 1.94 seconds
Started Jul 26 05:44:51 PM PDT 24
Finished Jul 26 05:44:53 PM PDT 24
Peak memory 219928 kb
Host smart-1d69e171-30c1-4a7f-b7bb-4439f8f127c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025253756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.4025253756
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3997174021
Short name T30
Test name
Test status
Simulation time 74661883 ps
CPU time 1.71 seconds
Started Jul 26 05:44:45 PM PDT 24
Finished Jul 26 05:44:46 PM PDT 24
Peak memory 218600 kb
Host smart-9392c52a-346f-4db8-afd8-282e8bd05048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997174021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3997174021
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.576635124
Short name T311
Test name
Test status
Simulation time 30911984 ps
CPU time 1.09 seconds
Started Jul 26 05:44:54 PM PDT 24
Finished Jul 26 05:44:55 PM PDT 24
Peak memory 219496 kb
Host smart-c177e99c-e843-48cf-8f62-a072f4cc3e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576635124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.576635124
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2509024228
Short name T507
Test name
Test status
Simulation time 48515682 ps
CPU time 1.19 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:44:48 PM PDT 24
Peak memory 219708 kb
Host smart-f681d4a8-b443-4408-b836-f7dbec0fd049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509024228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2509024228
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.244483567
Short name T568
Test name
Test status
Simulation time 76493718 ps
CPU time 1.21 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 219436 kb
Host smart-1bcc0331-dd19-4407-b53f-f1bc8751a1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244483567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.244483567
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.963740953
Short name T642
Test name
Test status
Simulation time 38583357 ps
CPU time 0.83 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:01 PM PDT 24
Peak memory 206388 kb
Host smart-0e4b2b98-62de-4795-aaea-db7591dfcce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963740953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.963740953
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.148090011
Short name T535
Test name
Test status
Simulation time 36903674 ps
CPU time 0.85 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:01 PM PDT 24
Peak memory 215776 kb
Host smart-f9ee03a4-92e8-490d-b2cf-ae239d9d6031
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148090011 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.148090011
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_genbits.1891086092
Short name T489
Test name
Test status
Simulation time 146430619 ps
CPU time 1.14 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 217120 kb
Host smart-310f8ba8-600a-4554-aeb2-f0ff23bfb1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891086092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1891086092
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.71163394
Short name T78
Test name
Test status
Simulation time 31249380 ps
CPU time 0.9 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 215944 kb
Host smart-0cd691c3-4de3-44ad-a4e6-b2dce0c91643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71163394 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.71163394
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2505137970
Short name T681
Test name
Test status
Simulation time 16661995 ps
CPU time 0.96 seconds
Started Jul 26 05:43:06 PM PDT 24
Finished Jul 26 05:43:07 PM PDT 24
Peak memory 215108 kb
Host smart-f3d78253-1054-41ec-820b-463412e69dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505137970 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2505137970
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3687318621
Short name T560
Test name
Test status
Simulation time 415353653 ps
CPU time 6.19 seconds
Started Jul 26 05:43:09 PM PDT 24
Finished Jul 26 05:43:16 PM PDT 24
Peak memory 216964 kb
Host smart-7ee40d96-3fa5-4d83-9086-06d8b8e63983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687318621 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3687318621
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/280.edn_genbits.228397517
Short name T801
Test name
Test status
Simulation time 77503082 ps
CPU time 1.47 seconds
Started Jul 26 05:44:49 PM PDT 24
Finished Jul 26 05:44:51 PM PDT 24
Peak memory 218404 kb
Host smart-626b2427-e321-4465-abc0-a396ff4cfbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228397517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.228397517
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.4214936962
Short name T386
Test name
Test status
Simulation time 74347165 ps
CPU time 1.23 seconds
Started Jul 26 05:44:34 PM PDT 24
Finished Jul 26 05:44:35 PM PDT 24
Peak memory 218588 kb
Host smart-35285e0f-d08c-4b27-a1bc-9e199e7f61cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214936962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.4214936962
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3262121604
Short name T439
Test name
Test status
Simulation time 43157596 ps
CPU time 1.5 seconds
Started Jul 26 05:44:51 PM PDT 24
Finished Jul 26 05:44:52 PM PDT 24
Peak memory 218480 kb
Host smart-74bf0af3-dccb-49cd-8bd2-8418ec1896e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262121604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3262121604
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1307773000
Short name T412
Test name
Test status
Simulation time 36560869 ps
CPU time 1.43 seconds
Started Jul 26 05:44:45 PM PDT 24
Finished Jul 26 05:44:47 PM PDT 24
Peak memory 218320 kb
Host smart-bdb5e622-febe-449a-9c56-101277847885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307773000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1307773000
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3606403581
Short name T707
Test name
Test status
Simulation time 39564041 ps
CPU time 1.37 seconds
Started Jul 26 05:44:51 PM PDT 24
Finished Jul 26 05:44:52 PM PDT 24
Peak memory 218528 kb
Host smart-44e5152f-d366-44e5-91eb-11f700a22685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606403581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3606403581
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1081558214
Short name T534
Test name
Test status
Simulation time 91839962 ps
CPU time 1.43 seconds
Started Jul 26 05:44:49 PM PDT 24
Finished Jul 26 05:44:51 PM PDT 24
Peak memory 218576 kb
Host smart-8ee7c302-7086-4576-8bfa-ec5330538f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081558214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1081558214
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2827200474
Short name T12
Test name
Test status
Simulation time 255972640 ps
CPU time 3.77 seconds
Started Jul 26 05:44:51 PM PDT 24
Finished Jul 26 05:44:55 PM PDT 24
Peak memory 217328 kb
Host smart-4618eb5f-8b80-48c5-9458-5ae75af99ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827200474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2827200474
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.880244357
Short name T845
Test name
Test status
Simulation time 25225040 ps
CPU time 1.15 seconds
Started Jul 26 05:44:49 PM PDT 24
Finished Jul 26 05:44:50 PM PDT 24
Peak memory 219336 kb
Host smart-ab096d57-260d-4590-a4e1-bb0db34815fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880244357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.880244357
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.4033116534
Short name T973
Test name
Test status
Simulation time 49586961 ps
CPU time 1.22 seconds
Started Jul 26 05:44:51 PM PDT 24
Finished Jul 26 05:44:52 PM PDT 24
Peak memory 218700 kb
Host smart-d2ac948f-2584-49e4-9c9f-deb8ff5f0513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033116534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.4033116534
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2902195612
Short name T11
Test name
Test status
Simulation time 43629485 ps
CPU time 1.26 seconds
Started Jul 26 05:44:43 PM PDT 24
Finished Jul 26 05:44:50 PM PDT 24
Peak memory 219624 kb
Host smart-40ab42af-9493-4dac-9086-aa020464817d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902195612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2902195612
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2222147439
Short name T841
Test name
Test status
Simulation time 24238133 ps
CPU time 1.17 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 218740 kb
Host smart-aa56be09-ceeb-4c4d-bd2f-ce40297610c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222147439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2222147439
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.878304016
Short name T458
Test name
Test status
Simulation time 23404890 ps
CPU time 0.81 seconds
Started Jul 26 05:43:09 PM PDT 24
Finished Jul 26 05:43:11 PM PDT 24
Peak memory 206448 kb
Host smart-c827df6f-a8ad-4bcf-bd10-ad396b0758a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878304016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.878304016
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2303886873
Short name T440
Test name
Test status
Simulation time 80760560 ps
CPU time 0.9 seconds
Started Jul 26 05:43:07 PM PDT 24
Finished Jul 26 05:43:08 PM PDT 24
Peak memory 215728 kb
Host smart-718b1f7c-abfa-41d4-a6b5-604c399ab330
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303886873 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2303886873
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3439520838
Short name T177
Test name
Test status
Simulation time 97251575 ps
CPU time 1.09 seconds
Started Jul 26 05:43:06 PM PDT 24
Finished Jul 26 05:43:07 PM PDT 24
Peak memory 216584 kb
Host smart-24a89bde-0558-430c-b19f-d224470416c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439520838 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3439520838
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.921689404
Short name T612
Test name
Test status
Simulation time 32306939 ps
CPU time 1.04 seconds
Started Jul 26 05:43:08 PM PDT 24
Finished Jul 26 05:43:10 PM PDT 24
Peak memory 218564 kb
Host smart-b03c4ef6-b2b7-4619-9b2b-aba9ef23e07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921689404 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.921689404
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.969772770
Short name T455
Test name
Test status
Simulation time 111648250 ps
CPU time 1.09 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:02 PM PDT 24
Peak memory 217348 kb
Host smart-071c8fca-35bf-487d-9765-7b6bd1ef3354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969772770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.969772770
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2537361125
Short name T872
Test name
Test status
Simulation time 23886282 ps
CPU time 1.12 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:02 PM PDT 24
Peak memory 215600 kb
Host smart-4db45dcd-32af-4533-840e-21e474b54282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537361125 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2537361125
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.4016027821
Short name T769
Test name
Test status
Simulation time 51060787 ps
CPU time 0.93 seconds
Started Jul 26 05:43:05 PM PDT 24
Finished Jul 26 05:43:07 PM PDT 24
Peak memory 215148 kb
Host smart-513a66ff-8bf5-4a5c-9a74-85a239f873b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016027821 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.4016027821
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.617607875
Short name T623
Test name
Test status
Simulation time 360488325 ps
CPU time 4.07 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:08 PM PDT 24
Peak memory 217048 kb
Host smart-a834b2ff-c80e-405e-8b6f-9d50957c8b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617607875 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.617607875
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.320856655
Short name T692
Test name
Test status
Simulation time 240326275814 ps
CPU time 1013.8 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:59:58 PM PDT 24
Peak memory 222388 kb
Host smart-0552ba7c-03c9-4c04-8a46-a6d2bef2724d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320856655 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.320856655
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2446305271
Short name T756
Test name
Test status
Simulation time 106713394 ps
CPU time 1.45 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:44:49 PM PDT 24
Peak memory 217316 kb
Host smart-b9f04253-b6d3-4ba5-be3d-28a7b6a5e06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446305271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2446305271
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.218045745
Short name T483
Test name
Test status
Simulation time 592535071 ps
CPU time 4.86 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:44:53 PM PDT 24
Peak memory 219836 kb
Host smart-fd00ad2a-5eca-4c0d-81fd-1c39f4e41e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218045745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.218045745
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.4234751011
Short name T444
Test name
Test status
Simulation time 50046201 ps
CPU time 1.48 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:44:49 PM PDT 24
Peak memory 219708 kb
Host smart-d858b951-501b-4f04-b568-2e5d90dc2d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234751011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.4234751011
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2926170067
Short name T798
Test name
Test status
Simulation time 156494917 ps
CPU time 1.37 seconds
Started Jul 26 05:44:50 PM PDT 24
Finished Jul 26 05:44:52 PM PDT 24
Peak memory 219980 kb
Host smart-c0c6c995-3180-43a7-ab8c-9f3f4d051b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926170067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2926170067
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.771372524
Short name T961
Test name
Test status
Simulation time 36472218 ps
CPU time 1.31 seconds
Started Jul 26 05:44:46 PM PDT 24
Finished Jul 26 05:44:48 PM PDT 24
Peak memory 217136 kb
Host smart-f7fc0fb0-c26c-486b-a378-57ab598239db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771372524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.771372524
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3221357376
Short name T822
Test name
Test status
Simulation time 163410578 ps
CPU time 2.33 seconds
Started Jul 26 05:44:46 PM PDT 24
Finished Jul 26 05:44:49 PM PDT 24
Peak memory 218448 kb
Host smart-df685055-e4d2-4e78-b77e-233a72e90409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221357376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3221357376
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.297595155
Short name T787
Test name
Test status
Simulation time 84107201 ps
CPU time 2.83 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:44:50 PM PDT 24
Peak memory 220004 kb
Host smart-41626959-7889-4847-92ae-4f83a6e85816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297595155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.297595155
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1002126922
Short name T402
Test name
Test status
Simulation time 37186183 ps
CPU time 1.28 seconds
Started Jul 26 05:44:45 PM PDT 24
Finished Jul 26 05:44:46 PM PDT 24
Peak memory 217112 kb
Host smart-5c747d61-27c2-47e1-99ad-f51c45dc16bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002126922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1002126922
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3764272518
Short name T564
Test name
Test status
Simulation time 67073980 ps
CPU time 1.48 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:44:49 PM PDT 24
Peak memory 218392 kb
Host smart-c58b3fa9-4bc0-48bf-99fe-2ffc696f70d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764272518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3764272518
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3851548139
Short name T144
Test name
Test status
Simulation time 248553432 ps
CPU time 1.14 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:23 PM PDT 24
Peak memory 218180 kb
Host smart-1424841c-f34e-403b-a207-24883e2c8939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851548139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3851548139
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.212639926
Short name T695
Test name
Test status
Simulation time 33804913 ps
CPU time 0.96 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:23 PM PDT 24
Peak memory 206664 kb
Host smart-cac43860-c049-4309-a3af-ebfcf09577d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212639926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.212639926
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.34655084
Short name T985
Test name
Test status
Simulation time 10992172 ps
CPU time 0.86 seconds
Started Jul 26 05:42:19 PM PDT 24
Finished Jul 26 05:42:20 PM PDT 24
Peak memory 215252 kb
Host smart-946f352f-8721-4016-9af2-4e08c3e8701b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34655084 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.34655084
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2430715508
Short name T155
Test name
Test status
Simulation time 32746770 ps
CPU time 1.22 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:23 PM PDT 24
Peak memory 216772 kb
Host smart-396f52ce-93f3-4046-a7ff-ec58990dc2c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430715508 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2430715508
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2096762030
Short name T876
Test name
Test status
Simulation time 71454441 ps
CPU time 1.09 seconds
Started Jul 26 05:42:36 PM PDT 24
Finished Jul 26 05:42:38 PM PDT 24
Peak memory 219428 kb
Host smart-75ebf4d4-30ed-4a6b-bee4-5d2c26bfb9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096762030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2096762030
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3967903778
Short name T939
Test name
Test status
Simulation time 40031328 ps
CPU time 1.5 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:24 PM PDT 24
Peak memory 215188 kb
Host smart-b9dfbb9f-26f6-44ff-bfb5-afdcec4ee08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967903778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3967903778
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1048605741
Short name T83
Test name
Test status
Simulation time 26937776 ps
CPU time 1.12 seconds
Started Jul 26 05:42:24 PM PDT 24
Finished Jul 26 05:42:26 PM PDT 24
Peak memory 216580 kb
Host smart-49642ae1-2578-4078-9a1b-1779eb7ebe46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048605741 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1048605741
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1683640471
Short name T496
Test name
Test status
Simulation time 42131849 ps
CPU time 0.9 seconds
Started Jul 26 05:42:25 PM PDT 24
Finished Jul 26 05:42:26 PM PDT 24
Peak memory 206908 kb
Host smart-fba6bfea-4f5b-4bc1-b8c9-72625128ab29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683640471 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1683640471
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.2691290061
Short name T920
Test name
Test status
Simulation time 14620440 ps
CPU time 0.97 seconds
Started Jul 26 05:42:21 PM PDT 24
Finished Jul 26 05:42:22 PM PDT 24
Peak memory 215088 kb
Host smart-19a6eda3-4b0e-4150-88f9-c616b725bba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691290061 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2691290061
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1829957396
Short name T243
Test name
Test status
Simulation time 124618681 ps
CPU time 3.1 seconds
Started Jul 26 05:42:23 PM PDT 24
Finished Jul 26 05:42:26 PM PDT 24
Peak memory 217176 kb
Host smart-dbb9d984-c71f-4ae8-a16c-ce0cf3a06434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829957396 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1829957396
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3837119194
Short name T724
Test name
Test status
Simulation time 35441802360 ps
CPU time 774.87 seconds
Started Jul 26 05:42:18 PM PDT 24
Finished Jul 26 05:55:13 PM PDT 24
Peak memory 218640 kb
Host smart-7925643c-d966-4649-b331-4958696bce3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837119194 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3837119194
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3067525872
Short name T188
Test name
Test status
Simulation time 26546133 ps
CPU time 1.16 seconds
Started Jul 26 05:43:06 PM PDT 24
Finished Jul 26 05:43:07 PM PDT 24
Peak memory 218392 kb
Host smart-246d7b76-e489-49e2-888d-f22567a3340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067525872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3067525872
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1924066202
Short name T654
Test name
Test status
Simulation time 14762252 ps
CPU time 0.93 seconds
Started Jul 26 05:43:09 PM PDT 24
Finished Jul 26 05:43:11 PM PDT 24
Peak memory 214776 kb
Host smart-e2cb2da5-e324-4d7e-8fde-551f34c6bd25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924066202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1924066202
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1259241323
Short name T114
Test name
Test status
Simulation time 49122776 ps
CPU time 0.87 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 216004 kb
Host smart-e905f7f6-293b-46dd-b3de-7de9b19b6822
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259241323 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1259241323
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1691718511
Short name T793
Test name
Test status
Simulation time 83000561 ps
CPU time 1.11 seconds
Started Jul 26 05:43:10 PM PDT 24
Finished Jul 26 05:43:11 PM PDT 24
Peak memory 216744 kb
Host smart-447ced10-cbd1-4775-b828-11d1bdcbaee7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691718511 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1691718511
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.899584869
Short name T213
Test name
Test status
Simulation time 22593306 ps
CPU time 1.1 seconds
Started Jul 26 05:43:00 PM PDT 24
Finished Jul 26 05:43:01 PM PDT 24
Peak memory 223876 kb
Host smart-f08591ac-5800-4254-946a-6dbf025a27ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899584869 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.899584869
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1385775736
Short name T332
Test name
Test status
Simulation time 40914835 ps
CPU time 1.5 seconds
Started Jul 26 05:43:09 PM PDT 24
Finished Jul 26 05:43:11 PM PDT 24
Peak memory 217156 kb
Host smart-0f6e5a46-11a6-49e8-9386-1bc8c7552749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385775736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1385775736
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3984016470
Short name T953
Test name
Test status
Simulation time 28913210 ps
CPU time 1.03 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:01 PM PDT 24
Peak memory 215240 kb
Host smart-26ff8140-d9d0-4c7f-a1a0-8b33843c9fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984016470 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3984016470
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2183753279
Short name T581
Test name
Test status
Simulation time 18940327 ps
CPU time 1.02 seconds
Started Jul 26 05:43:09 PM PDT 24
Finished Jul 26 05:43:10 PM PDT 24
Peak memory 215180 kb
Host smart-3f1d7e1b-ccea-4a0e-b9b9-1a3eba9de0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183753279 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2183753279
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2989405507
Short name T387
Test name
Test status
Simulation time 1451191944 ps
CPU time 3.71 seconds
Started Jul 26 05:43:07 PM PDT 24
Finished Jul 26 05:43:11 PM PDT 24
Peak memory 215176 kb
Host smart-77db5f54-a51d-47d4-931f-d4e2602fb412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989405507 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2989405507
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_alert.2240798328
Short name T909
Test name
Test status
Simulation time 80716806 ps
CPU time 1.14 seconds
Started Jul 26 05:43:09 PM PDT 24
Finished Jul 26 05:43:10 PM PDT 24
Peak memory 221504 kb
Host smart-84e91104-5976-4c38-9193-7a73b337f2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240798328 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2240798328
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2972754875
Short name T848
Test name
Test status
Simulation time 34018102 ps
CPU time 0.81 seconds
Started Jul 26 05:43:09 PM PDT 24
Finished Jul 26 05:43:11 PM PDT 24
Peak memory 206688 kb
Host smart-7d39ee5f-8127-4ee7-b7ba-65a801bd1c8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972754875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2972754875
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.737832642
Short name T607
Test name
Test status
Simulation time 17293347 ps
CPU time 0.82 seconds
Started Jul 26 05:43:07 PM PDT 24
Finished Jul 26 05:43:08 PM PDT 24
Peak memory 215268 kb
Host smart-399967d6-15ae-4ade-822e-b1f20e5192d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737832642 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.737832642
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.3057098624
Short name T614
Test name
Test status
Simulation time 27783520 ps
CPU time 1.26 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 223836 kb
Host smart-0e24413c-95d4-4349-b8ec-fd86ffe5859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057098624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3057098624
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.138546893
Short name T987
Test name
Test status
Simulation time 49025265 ps
CPU time 1.42 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 218468 kb
Host smart-61553769-2232-4878-a58a-0c887f63ee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138546893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.138546893
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2572671298
Short name T437
Test name
Test status
Simulation time 23477414 ps
CPU time 1.18 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 215296 kb
Host smart-337d2d43-6e48-4138-82f8-6e4340ee920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572671298 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2572671298
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.302002554
Short name T691
Test name
Test status
Simulation time 58322062 ps
CPU time 0.9 seconds
Started Jul 26 05:43:10 PM PDT 24
Finished Jul 26 05:43:11 PM PDT 24
Peak memory 215080 kb
Host smart-ab43903c-1f87-4d43-9868-f35f8f2574f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302002554 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.302002554
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1978289275
Short name T242
Test name
Test status
Simulation time 131167440 ps
CPU time 1.91 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 217220 kb
Host smart-88644f3b-c722-4cda-afda-7232b5f3ecef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978289275 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1978289275
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2561970370
Short name T229
Test name
Test status
Simulation time 113142299265 ps
CPU time 1276.02 seconds
Started Jul 26 05:43:07 PM PDT 24
Finished Jul 26 06:04:23 PM PDT 24
Peak memory 225744 kb
Host smart-bfd7b42d-150b-4432-801e-5628a10b599e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561970370 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2561970370
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1611112903
Short name T593
Test name
Test status
Simulation time 72156206 ps
CPU time 1.14 seconds
Started Jul 26 05:43:12 PM PDT 24
Finished Jul 26 05:43:14 PM PDT 24
Peak memory 220596 kb
Host smart-b1826d44-b958-40ff-a889-eb482c287c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611112903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1611112903
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2237866411
Short name T994
Test name
Test status
Simulation time 13940122 ps
CPU time 0.91 seconds
Started Jul 26 05:43:10 PM PDT 24
Finished Jul 26 05:43:11 PM PDT 24
Peak memory 215036 kb
Host smart-881041fa-c429-4ee2-a65f-2a3e9a431d22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237866411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2237866411
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3835003637
Short name T186
Test name
Test status
Simulation time 14291191 ps
CPU time 0.9 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 207196 kb
Host smart-6830b4c5-f1ec-48d5-a739-ff9b591aaa6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835003637 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3835003637
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1379073208
Short name T165
Test name
Test status
Simulation time 263097772 ps
CPU time 1.17 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 215412 kb
Host smart-985aa8e0-dd84-43dd-a9b1-4865d38760fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379073208 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1379073208
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1544718287
Short name T587
Test name
Test status
Simulation time 227571213 ps
CPU time 0.99 seconds
Started Jul 26 05:43:12 PM PDT 24
Finished Jul 26 05:43:13 PM PDT 24
Peak memory 219768 kb
Host smart-85d15ef2-f6f2-4274-9a50-d3b06d584558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544718287 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1544718287
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.56929767
Short name T70
Test name
Test status
Simulation time 701246297 ps
CPU time 4.79 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:09 PM PDT 24
Peak memory 220280 kb
Host smart-32e123ec-977d-43d4-b926-353fa4fd86bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56929767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.56929767
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2551377828
Short name T638
Test name
Test status
Simulation time 29650881 ps
CPU time 0.88 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 215736 kb
Host smart-e218f059-344a-4f01-a1d4-cd946a027153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551377828 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2551377828
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3972714037
Short name T357
Test name
Test status
Simulation time 88932461 ps
CPU time 0.93 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 215176 kb
Host smart-2feb6b1a-3ba7-4221-92b3-6f58ff9ff54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972714037 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3972714037
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.311618453
Short name T288
Test name
Test status
Simulation time 118534236 ps
CPU time 1.7 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 215216 kb
Host smart-3db2825d-0e5d-410e-a2b8-b7ce4b8ebc01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311618453 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.311618453
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2301374594
Short name T136
Test name
Test status
Simulation time 168456961952 ps
CPU time 980.27 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:59:24 PM PDT 24
Peak memory 221220 kb
Host smart-c7a958e2-b623-4c49-baf1-8d050fcc1ebf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301374594 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2301374594
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2798780305
Short name T198
Test name
Test status
Simulation time 46622866 ps
CPU time 1.16 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 219572 kb
Host smart-bba6e4f2-2ebf-46bc-8395-dd3380e694ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798780305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2798780305
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.4242973327
Short name T530
Test name
Test status
Simulation time 55035139 ps
CPU time 0.97 seconds
Started Jul 26 05:43:10 PM PDT 24
Finished Jul 26 05:43:11 PM PDT 24
Peak memory 206572 kb
Host smart-e786fd55-98a6-40c2-83c4-936e86e8ace6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242973327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.4242973327
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.4227913054
Short name T123
Test name
Test status
Simulation time 14867348 ps
CPU time 0.93 seconds
Started Jul 26 05:42:59 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 216300 kb
Host smart-5562504b-7eed-4315-b342-62a74dddb8dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227913054 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.4227913054
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.790136957
Short name T771
Test name
Test status
Simulation time 37981388 ps
CPU time 1.19 seconds
Started Jul 26 05:43:05 PM PDT 24
Finished Jul 26 05:43:07 PM PDT 24
Peak memory 215400 kb
Host smart-5fccce69-ad90-467e-95ae-290c199a93af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790136957 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.790136957
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2691509787
Short name T183
Test name
Test status
Simulation time 33186498 ps
CPU time 0.91 seconds
Started Jul 26 05:43:10 PM PDT 24
Finished Jul 26 05:43:11 PM PDT 24
Peak memory 218068 kb
Host smart-5f729441-3924-4bda-8502-29dba9c39a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691509787 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2691509787
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2459967708
Short name T781
Test name
Test status
Simulation time 107889334 ps
CPU time 1.23 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 05:43:03 PM PDT 24
Peak memory 219676 kb
Host smart-4654c454-4fdd-4204-81eb-d6e7d953702c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459967708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2459967708
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.4169134057
Short name T87
Test name
Test status
Simulation time 23251217 ps
CPU time 0.96 seconds
Started Jul 26 05:43:06 PM PDT 24
Finished Jul 26 05:43:07 PM PDT 24
Peak memory 215664 kb
Host smart-f1db3e0e-9a03-41b5-8601-48ae3c4a639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169134057 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.4169134057
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2436517064
Short name T609
Test name
Test status
Simulation time 42121801 ps
CPU time 0.88 seconds
Started Jul 26 05:43:08 PM PDT 24
Finished Jul 26 05:43:09 PM PDT 24
Peak memory 215104 kb
Host smart-b0bc848c-008e-421f-bae8-7147f689d96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436517064 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2436517064
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.4195509896
Short name T359
Test name
Test status
Simulation time 630275960 ps
CPU time 3.85 seconds
Started Jul 26 05:43:01 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 215204 kb
Host smart-a7fc14e2-57a1-4cf9-b81c-fd02d1df8220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195509896 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.4195509896
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1592872434
Short name T469
Test name
Test status
Simulation time 98567471512 ps
CPU time 585.88 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 05:52:48 PM PDT 24
Peak memory 223528 kb
Host smart-20e0f845-d9b9-47ee-a325-a4f1cb1bc0b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592872434 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1592872434
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1816351904
Short name T554
Test name
Test status
Simulation time 80858423 ps
CPU time 1.17 seconds
Started Jul 26 05:43:04 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 220084 kb
Host smart-f3d1eae9-674e-43b1-bf75-5ae3c652edca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816351904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1816351904
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1682552478
Short name T631
Test name
Test status
Simulation time 129381351 ps
CPU time 0.78 seconds
Started Jul 26 05:43:12 PM PDT 24
Finished Jul 26 05:43:13 PM PDT 24
Peak memory 205940 kb
Host smart-06b219a2-cd01-417b-a9ec-d004a92d3feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682552478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1682552478
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2915753606
Short name T366
Test name
Test status
Simulation time 13118559 ps
CPU time 0.89 seconds
Started Jul 26 05:43:06 PM PDT 24
Finished Jul 26 05:43:07 PM PDT 24
Peak memory 216032 kb
Host smart-209339fd-9d84-455f-aa18-0a7ea304e61d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915753606 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2915753606
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3553962142
Short name T179
Test name
Test status
Simulation time 60619392 ps
CPU time 1.19 seconds
Started Jul 26 05:43:04 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 216528 kb
Host smart-11efbaa8-0154-491a-bcca-71ff48f78d6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553962142 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3553962142
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3438701674
Short name T721
Test name
Test status
Simulation time 28806195 ps
CPU time 0.98 seconds
Started Jul 26 05:43:06 PM PDT 24
Finished Jul 26 05:43:07 PM PDT 24
Peak memory 219512 kb
Host smart-7c5c565c-a3f0-44e8-ab3b-ce5175484c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438701674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3438701674
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1508603203
Short name T632
Test name
Test status
Simulation time 65170640 ps
CPU time 1.15 seconds
Started Jul 26 05:43:03 PM PDT 24
Finished Jul 26 05:43:05 PM PDT 24
Peak memory 219896 kb
Host smart-f316575f-64ed-4c86-bbbd-5c420937750f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508603203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1508603203
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.663265686
Short name T131
Test name
Test status
Simulation time 38752856 ps
CPU time 0.86 seconds
Started Jul 26 05:43:06 PM PDT 24
Finished Jul 26 05:43:07 PM PDT 24
Peak memory 215608 kb
Host smart-143f4ecb-4e4e-4ffd-a3d2-d806b67e92b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663265686 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.663265686
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2051832798
Short name T569
Test name
Test status
Simulation time 19783580 ps
CPU time 1.02 seconds
Started Jul 26 05:43:10 PM PDT 24
Finished Jul 26 05:43:11 PM PDT 24
Peak memory 215096 kb
Host smart-8a6cee27-71ab-4fcf-88a8-aa6004b66306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051832798 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2051832798
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.4092790947
Short name T241
Test name
Test status
Simulation time 401099152 ps
CPU time 4.23 seconds
Started Jul 26 05:43:10 PM PDT 24
Finished Jul 26 05:43:15 PM PDT 24
Peak memory 215244 kb
Host smart-73761afd-6a40-4a25-9fdd-befb753e8286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092790947 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.4092790947
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.32058735
Short name T460
Test name
Test status
Simulation time 334565936024 ps
CPU time 2099.3 seconds
Started Jul 26 05:43:02 PM PDT 24
Finished Jul 26 06:18:02 PM PDT 24
Peak memory 229552 kb
Host smart-4dd60c7a-8937-4c83-bf00-f10b0c4fd069
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32058735 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.32058735
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2458503225
Short name T203
Test name
Test status
Simulation time 25890371 ps
CPU time 1.2 seconds
Started Jul 26 05:43:14 PM PDT 24
Finished Jul 26 05:43:15 PM PDT 24
Peak memory 219480 kb
Host smart-239442c7-166b-4155-93ca-89df8a5db274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458503225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2458503225
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1141223342
Short name T436
Test name
Test status
Simulation time 27360366 ps
CPU time 1.11 seconds
Started Jul 26 05:43:11 PM PDT 24
Finished Jul 26 05:43:12 PM PDT 24
Peak memory 214796 kb
Host smart-0e2cbba8-7897-4dd2-9469-fdbc552eccfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141223342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1141223342
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2772244901
Short name T805
Test name
Test status
Simulation time 34025349 ps
CPU time 0.84 seconds
Started Jul 26 05:43:15 PM PDT 24
Finished Jul 26 05:43:16 PM PDT 24
Peak memory 216176 kb
Host smart-df758f63-aec9-4eeb-bb43-9748cdf298a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772244901 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2772244901
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1871543914
Short name T571
Test name
Test status
Simulation time 252881437 ps
CPU time 1.06 seconds
Started Jul 26 05:43:17 PM PDT 24
Finished Jul 26 05:43:18 PM PDT 24
Peak memory 216668 kb
Host smart-22559190-e050-4162-a6de-62936df900db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871543914 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1871543914
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3703731692
Short name T102
Test name
Test status
Simulation time 29629173 ps
CPU time 1.31 seconds
Started Jul 26 05:43:23 PM PDT 24
Finished Jul 26 05:43:24 PM PDT 24
Peak memory 219612 kb
Host smart-1e888f59-0aca-479b-9e34-a191b3dbf097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703731692 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3703731692
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.316130850
Short name T453
Test name
Test status
Simulation time 47759942 ps
CPU time 1.27 seconds
Started Jul 26 05:43:06 PM PDT 24
Finished Jul 26 05:43:07 PM PDT 24
Peak memory 218424 kb
Host smart-da8f2e8a-4586-4635-a37f-90fac2bb5f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316130850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.316130850
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.4039306019
Short name T775
Test name
Test status
Simulation time 28841524 ps
CPU time 1.09 seconds
Started Jul 26 05:43:38 PM PDT 24
Finished Jul 26 05:43:39 PM PDT 24
Peak memory 223900 kb
Host smart-565a415e-8770-41a2-b4fd-2c626c018471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039306019 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.4039306019
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.521070390
Short name T414
Test name
Test status
Simulation time 16840609 ps
CPU time 0.97 seconds
Started Jul 26 05:43:06 PM PDT 24
Finished Jul 26 05:43:07 PM PDT 24
Peak memory 215104 kb
Host smart-419b1ca7-3ce1-4752-9d02-135aa24a0cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521070390 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.521070390
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1016186060
Short name T407
Test name
Test status
Simulation time 405779780 ps
CPU time 7.74 seconds
Started Jul 26 05:43:28 PM PDT 24
Finished Jul 26 05:43:36 PM PDT 24
Peak memory 215140 kb
Host smart-23d18152-5590-4253-a2e5-9051802e3641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016186060 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1016186060
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.299768628
Short name T643
Test name
Test status
Simulation time 208517371308 ps
CPU time 2329.79 seconds
Started Jul 26 05:43:13 PM PDT 24
Finished Jul 26 06:22:03 PM PDT 24
Peak memory 228756 kb
Host smart-44589790-9011-4ae3-bf74-2409e85fda0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299768628 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.299768628
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2965394563
Short name T984
Test name
Test status
Simulation time 52079865 ps
CPU time 1.19 seconds
Started Jul 26 05:43:30 PM PDT 24
Finished Jul 26 05:43:32 PM PDT 24
Peak memory 219972 kb
Host smart-29f7d1cc-c318-4f68-b1f9-dc577faf1783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965394563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2965394563
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3277147278
Short name T380
Test name
Test status
Simulation time 95603934 ps
CPU time 0.96 seconds
Started Jul 26 05:43:12 PM PDT 24
Finished Jul 26 05:43:14 PM PDT 24
Peak memory 206628 kb
Host smart-558b9074-92db-4ff2-92b9-f439fae65ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277147278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3277147278
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.927796514
Short name T977
Test name
Test status
Simulation time 12917992 ps
CPU time 0.9 seconds
Started Jul 26 05:43:11 PM PDT 24
Finished Jul 26 05:43:12 PM PDT 24
Peak memory 216012 kb
Host smart-b073faec-7aaa-424d-bed8-ed3f3a197f4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927796514 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.927796514
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.4202713630
Short name T774
Test name
Test status
Simulation time 101358461 ps
CPU time 1.15 seconds
Started Jul 26 05:43:11 PM PDT 24
Finished Jul 26 05:43:12 PM PDT 24
Peak memory 216792 kb
Host smart-5379f0bf-8c0f-48e7-b431-8ed19b048874
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202713630 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.4202713630
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_genbits.3929967862
Short name T761
Test name
Test status
Simulation time 36415235 ps
CPU time 1.17 seconds
Started Jul 26 05:43:31 PM PDT 24
Finished Jul 26 05:43:32 PM PDT 24
Peak memory 218244 kb
Host smart-f26a58ff-7b27-4d55-8d2f-4ca4caaa4e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929967862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3929967862
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3007247646
Short name T634
Test name
Test status
Simulation time 24288936 ps
CPU time 0.91 seconds
Started Jul 26 05:43:18 PM PDT 24
Finished Jul 26 05:43:19 PM PDT 24
Peak memory 215292 kb
Host smart-313b4a10-7302-4042-9b2d-3e62bf7c2cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007247646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3007247646
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2307114450
Short name T457
Test name
Test status
Simulation time 53663175 ps
CPU time 0.92 seconds
Started Jul 26 05:43:31 PM PDT 24
Finished Jul 26 05:43:32 PM PDT 24
Peak memory 215152 kb
Host smart-c3236699-a1e3-46ac-8a26-3f831bfe734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307114450 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2307114450
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2227128818
Short name T914
Test name
Test status
Simulation time 313223938 ps
CPU time 6.26 seconds
Started Jul 26 05:43:22 PM PDT 24
Finished Jul 26 05:43:28 PM PDT 24
Peak memory 216924 kb
Host smart-9f141dff-8f18-4876-a2af-bcde56008933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227128818 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2227128818
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.471374462
Short name T463
Test name
Test status
Simulation time 103477395047 ps
CPU time 592.1 seconds
Started Jul 26 05:43:30 PM PDT 24
Finished Jul 26 05:53:23 PM PDT 24
Peak memory 219456 kb
Host smart-b1d8c482-bb5e-4005-8a5e-41d90d87f0ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471374462 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.471374462
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.80482253
Short name T735
Test name
Test status
Simulation time 59023170 ps
CPU time 1.31 seconds
Started Jul 26 05:43:31 PM PDT 24
Finished Jul 26 05:43:33 PM PDT 24
Peak memory 215524 kb
Host smart-c1318462-79dc-4216-aea2-fb746796da34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80482253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.80482253
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.27839953
Short name T279
Test name
Test status
Simulation time 50403769 ps
CPU time 0.94 seconds
Started Jul 26 05:43:24 PM PDT 24
Finished Jul 26 05:43:25 PM PDT 24
Peak memory 206720 kb
Host smart-9999d8b7-ad71-47c6-881a-6d154d8e1f70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27839953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.27839953
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3334445535
Short name T978
Test name
Test status
Simulation time 12059657 ps
CPU time 0.9 seconds
Started Jul 26 05:43:32 PM PDT 24
Finished Jul 26 05:43:33 PM PDT 24
Peak memory 216272 kb
Host smart-33783e09-d3a5-4322-b8b6-f5c98ba74e3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334445535 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3334445535
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1592086213
Short name T442
Test name
Test status
Simulation time 31634880 ps
CPU time 1.1 seconds
Started Jul 26 05:43:14 PM PDT 24
Finished Jul 26 05:43:15 PM PDT 24
Peak memory 218040 kb
Host smart-8b481ab2-a856-4a2b-9cdd-f276c27c981e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592086213 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1592086213
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1196634517
Short name T647
Test name
Test status
Simulation time 22638889 ps
CPU time 1.2 seconds
Started Jul 26 05:43:31 PM PDT 24
Finished Jul 26 05:43:32 PM PDT 24
Peak memory 218636 kb
Host smart-8edc99a7-7c88-4bc1-835c-67151ecac6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196634517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1196634517
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1581472944
Short name T864
Test name
Test status
Simulation time 58907094 ps
CPU time 1.12 seconds
Started Jul 26 05:43:17 PM PDT 24
Finished Jul 26 05:43:19 PM PDT 24
Peak memory 219240 kb
Host smart-0956a9b8-029f-42e3-89a0-5374df833414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581472944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1581472944
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3991963678
Short name T622
Test name
Test status
Simulation time 24374868 ps
CPU time 0.93 seconds
Started Jul 26 05:43:13 PM PDT 24
Finished Jul 26 05:43:14 PM PDT 24
Peak memory 215736 kb
Host smart-e18c2284-d415-4f31-a55f-096050dbdf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991963678 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3991963678
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3379330381
Short name T390
Test name
Test status
Simulation time 18238635 ps
CPU time 1.06 seconds
Started Jul 26 05:43:11 PM PDT 24
Finished Jul 26 05:43:12 PM PDT 24
Peak memory 215128 kb
Host smart-20ccfbad-e140-434e-ac9c-aa860adf715b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379330381 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3379330381
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.4243320826
Short name T95
Test name
Test status
Simulation time 79125128 ps
CPU time 1.93 seconds
Started Jul 26 05:43:14 PM PDT 24
Finished Jul 26 05:43:16 PM PDT 24
Peak memory 218352 kb
Host smart-011a85f4-ce9c-4211-a079-92732e5d50e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243320826 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.4243320826
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1162583794
Short name T549
Test name
Test status
Simulation time 676701219342 ps
CPU time 2823.05 seconds
Started Jul 26 05:43:30 PM PDT 24
Finished Jul 26 06:30:34 PM PDT 24
Peak memory 229156 kb
Host smart-ee1ee235-1da1-4cde-8b48-02fe5c6338d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162583794 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1162583794
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1701689027
Short name T757
Test name
Test status
Simulation time 128799629 ps
CPU time 1.15 seconds
Started Jul 26 05:43:20 PM PDT 24
Finished Jul 26 05:43:21 PM PDT 24
Peak memory 218504 kb
Host smart-278d407c-4133-4789-aa5b-99d00293bbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701689027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1701689027
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3535535913
Short name T521
Test name
Test status
Simulation time 13705124 ps
CPU time 0.89 seconds
Started Jul 26 05:43:18 PM PDT 24
Finished Jul 26 05:43:19 PM PDT 24
Peak memory 206628 kb
Host smart-5ce47a55-6d1c-4a97-a8a7-70c4c22c5c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535535913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3535535913
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2810644035
Short name T640
Test name
Test status
Simulation time 70354818 ps
CPU time 0.94 seconds
Started Jul 26 05:43:14 PM PDT 24
Finished Jul 26 05:43:15 PM PDT 24
Peak memory 216080 kb
Host smart-e47d36b0-f5f9-430c-9e7b-5af98176a000
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810644035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2810644035
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2274844552
Short name T16
Test name
Test status
Simulation time 39881127 ps
CPU time 1.19 seconds
Started Jul 26 05:43:24 PM PDT 24
Finished Jul 26 05:43:25 PM PDT 24
Peak memory 216616 kb
Host smart-21ba2aaf-a1f4-42a1-9cce-83604e8c1ff3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274844552 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2274844552
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2502501353
Short name T97
Test name
Test status
Simulation time 22053438 ps
CPU time 1.02 seconds
Started Jul 26 05:43:12 PM PDT 24
Finished Jul 26 05:43:13 PM PDT 24
Peak memory 223868 kb
Host smart-7e25f885-f7cc-4858-9a12-09e67ab57a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502501353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2502501353
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.698617796
Short name T713
Test name
Test status
Simulation time 90291373 ps
CPU time 1.11 seconds
Started Jul 26 05:43:23 PM PDT 24
Finished Jul 26 05:43:24 PM PDT 24
Peak memory 217264 kb
Host smart-6465e459-0d43-471b-9281-32a9e96f72bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698617796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.698617796
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1900801951
Short name T969
Test name
Test status
Simulation time 23939968 ps
CPU time 1 seconds
Started Jul 26 05:43:11 PM PDT 24
Finished Jul 26 05:43:13 PM PDT 24
Peak memory 215412 kb
Host smart-80f00f31-1e3c-4048-a00b-b31b2cd5fff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900801951 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1900801951
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1535908351
Short name T424
Test name
Test status
Simulation time 20667406 ps
CPU time 1 seconds
Started Jul 26 05:43:24 PM PDT 24
Finished Jul 26 05:43:25 PM PDT 24
Peak memory 206976 kb
Host smart-e5eafb4e-8b49-40bb-986d-f5439b70c2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535908351 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1535908351
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2001144777
Short name T956
Test name
Test status
Simulation time 1282993877 ps
CPU time 3.39 seconds
Started Jul 26 05:43:48 PM PDT 24
Finished Jul 26 05:43:51 PM PDT 24
Peak memory 217048 kb
Host smart-3815f207-2b5e-42ae-a179-fd4a02637060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001144777 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2001144777
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3414786110
Short name T228
Test name
Test status
Simulation time 153296575559 ps
CPU time 888.24 seconds
Started Jul 26 05:43:24 PM PDT 24
Finished Jul 26 05:58:13 PM PDT 24
Peak memory 223520 kb
Host smart-c45c216c-716f-4bc1-8cc3-a798e267cf08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414786110 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3414786110
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert_test.2644805606
Short name T772
Test name
Test status
Simulation time 20260287 ps
CPU time 0.95 seconds
Started Jul 26 05:43:11 PM PDT 24
Finished Jul 26 05:43:13 PM PDT 24
Peak memory 206732 kb
Host smart-78c9c947-6c03-4dd4-96c4-504fb9f8cf56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644805606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2644805606
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3696716308
Short name T462
Test name
Test status
Simulation time 53129169 ps
CPU time 0.92 seconds
Started Jul 26 05:43:17 PM PDT 24
Finished Jul 26 05:43:19 PM PDT 24
Peak memory 218300 kb
Host smart-b2ad99ef-6cfb-4606-a42a-db9157596e9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696716308 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3696716308
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1262420127
Short name T653
Test name
Test status
Simulation time 17922459 ps
CPU time 1.02 seconds
Started Jul 26 05:43:21 PM PDT 24
Finished Jul 26 05:43:23 PM PDT 24
Peak memory 218408 kb
Host smart-0aa0b490-f094-4933-b0e6-f3d479680bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262420127 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1262420127
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1089624273
Short name T899
Test name
Test status
Simulation time 59991372 ps
CPU time 1.6 seconds
Started Jul 26 05:43:17 PM PDT 24
Finished Jul 26 05:43:18 PM PDT 24
Peak memory 218480 kb
Host smart-82d5750a-6f5f-492a-b33f-9416dfa91f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089624273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1089624273
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3348555324
Short name T886
Test name
Test status
Simulation time 32204613 ps
CPU time 0.89 seconds
Started Jul 26 05:43:24 PM PDT 24
Finished Jul 26 05:43:25 PM PDT 24
Peak memory 215300 kb
Host smart-155ca925-dddd-4116-bb78-4720b0242b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348555324 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3348555324
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.579792249
Short name T541
Test name
Test status
Simulation time 56880855 ps
CPU time 0.88 seconds
Started Jul 26 05:43:39 PM PDT 24
Finished Jul 26 05:43:40 PM PDT 24
Peak memory 215148 kb
Host smart-260301f6-86ea-490d-b397-04cc9a9c0bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579792249 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.579792249
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1372259660
Short name T625
Test name
Test status
Simulation time 322995874 ps
CPU time 6.38 seconds
Started Jul 26 05:43:31 PM PDT 24
Finished Jul 26 05:43:38 PM PDT 24
Peak memory 217212 kb
Host smart-ba944b2f-05c7-4070-bc8e-4d5be283143c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372259660 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1372259660
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.783073663
Short name T23
Test name
Test status
Simulation time 233990928888 ps
CPU time 1455.34 seconds
Started Jul 26 05:43:13 PM PDT 24
Finished Jul 26 06:07:28 PM PDT 24
Peak memory 223496 kb
Host smart-d65bf135-e369-44de-826a-b8503022b29e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783073663 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.783073663
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2569819695
Short name T219
Test name
Test status
Simulation time 81263001 ps
CPU time 1.09 seconds
Started Jul 26 05:42:19 PM PDT 24
Finished Jul 26 05:42:21 PM PDT 24
Peak memory 219740 kb
Host smart-5785b530-03d3-4199-9164-2d2c2f61a345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569819695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2569819695
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1450024042
Short name T589
Test name
Test status
Simulation time 21342473 ps
CPU time 0.84 seconds
Started Jul 26 05:42:20 PM PDT 24
Finished Jul 26 05:42:21 PM PDT 24
Peak memory 206416 kb
Host smart-a74c0c2c-30c4-4291-82f0-1a46efa86ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450024042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1450024042
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1066122595
Short name T572
Test name
Test status
Simulation time 12393100 ps
CPU time 0.88 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:23 PM PDT 24
Peak memory 216264 kb
Host smart-9abead17-4ff4-4159-9677-c35050e3d22d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066122595 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1066122595
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1454986213
Short name T869
Test name
Test status
Simulation time 61077573 ps
CPU time 1.02 seconds
Started Jul 26 05:42:21 PM PDT 24
Finished Jul 26 05:42:22 PM PDT 24
Peak memory 218328 kb
Host smart-da32ccf8-7dcf-44e9-8f8f-d0df4f0f3aa4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454986213 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1454986213
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3432442565
Short name T212
Test name
Test status
Simulation time 18785261 ps
CPU time 1.05 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:23 PM PDT 24
Peak memory 218276 kb
Host smart-22026c56-dc41-4c89-b6f8-1df08a0b9e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432442565 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3432442565
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1184824370
Short name T963
Test name
Test status
Simulation time 109272053 ps
CPU time 1.41 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:23 PM PDT 24
Peak memory 218880 kb
Host smart-9a777e07-de34-426f-baae-95337969187c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184824370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1184824370
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.969824153
Short name T76
Test name
Test status
Simulation time 20108702 ps
CPU time 1.07 seconds
Started Jul 26 05:42:19 PM PDT 24
Finished Jul 26 05:42:20 PM PDT 24
Peak memory 215848 kb
Host smart-23dcfcc7-da99-429b-b0bf-c95727af7d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969824153 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.969824153
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_smoke.4289103968
Short name T865
Test name
Test status
Simulation time 16258693 ps
CPU time 0.99 seconds
Started Jul 26 05:42:21 PM PDT 24
Finished Jul 26 05:42:23 PM PDT 24
Peak memory 215200 kb
Host smart-ff4523c2-e840-44b1-b79c-09f9417b896f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289103968 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.4289103968
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.757554926
Short name T779
Test name
Test status
Simulation time 225707234 ps
CPU time 4.91 seconds
Started Jul 26 05:42:23 PM PDT 24
Finished Jul 26 05:42:28 PM PDT 24
Peak memory 217060 kb
Host smart-03e100ff-648a-464b-aba7-7e158111de7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757554926 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.757554926
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3826793531
Short name T558
Test name
Test status
Simulation time 53198894395 ps
CPU time 298.17 seconds
Started Jul 26 05:42:24 PM PDT 24
Finished Jul 26 05:47:22 PM PDT 24
Peak memory 219912 kb
Host smart-7eab5670-153b-490e-931e-106b724dc26c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826793531 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3826793531
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2075432834
Short name T207
Test name
Test status
Simulation time 21118963 ps
CPU time 1.13 seconds
Started Jul 26 05:43:17 PM PDT 24
Finished Jul 26 05:43:19 PM PDT 24
Peak memory 219752 kb
Host smart-a772e27f-dd75-4998-95fd-fc491a481860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075432834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2075432834
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.568627433
Short name T361
Test name
Test status
Simulation time 181562379 ps
CPU time 0.93 seconds
Started Jul 26 05:43:30 PM PDT 24
Finished Jul 26 05:43:32 PM PDT 24
Peak memory 206744 kb
Host smart-5e3a4029-7557-4496-915f-bca4fc04d197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568627433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.568627433
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2826846890
Short name T108
Test name
Test status
Simulation time 13850174 ps
CPU time 0.92 seconds
Started Jul 26 05:43:22 PM PDT 24
Finished Jul 26 05:43:23 PM PDT 24
Peak memory 216276 kb
Host smart-b0379cee-8701-42cf-946f-c460505dca0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826846890 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2826846890
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3329997149
Short name T68
Test name
Test status
Simulation time 285874322 ps
CPU time 1.18 seconds
Started Jul 26 05:43:32 PM PDT 24
Finished Jul 26 05:43:34 PM PDT 24
Peak memory 215564 kb
Host smart-e355e619-9034-404f-b94a-cf3f64b71ce1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329997149 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3329997149
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1540551555
Short name T750
Test name
Test status
Simulation time 21496355 ps
CPU time 0.93 seconds
Started Jul 26 05:43:42 PM PDT 24
Finished Jul 26 05:43:43 PM PDT 24
Peak memory 218504 kb
Host smart-799daf0f-6d65-4dd5-8751-af83a2f48412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540551555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1540551555
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3365400900
Short name T388
Test name
Test status
Simulation time 91255814 ps
CPU time 1.11 seconds
Started Jul 26 05:43:17 PM PDT 24
Finished Jul 26 05:43:18 PM PDT 24
Peak memory 217196 kb
Host smart-da946c29-7759-44c8-994b-e85311a406f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365400900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3365400900
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3724659147
Short name T882
Test name
Test status
Simulation time 26688908 ps
CPU time 0.93 seconds
Started Jul 26 05:43:11 PM PDT 24
Finished Jul 26 05:43:12 PM PDT 24
Peak memory 215724 kb
Host smart-a55b3c4e-a2b5-4642-84c6-e97dea2c7898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724659147 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3724659147
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.965505701
Short name T540
Test name
Test status
Simulation time 21536945 ps
CPU time 1.01 seconds
Started Jul 26 05:43:12 PM PDT 24
Finished Jul 26 05:43:13 PM PDT 24
Peak memory 215148 kb
Host smart-5fb4ea3a-def7-44cf-ad2b-d9d8ba1ca99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965505701 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.965505701
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.699228003
Short name T778
Test name
Test status
Simulation time 139950257 ps
CPU time 1.91 seconds
Started Jul 26 05:43:30 PM PDT 24
Finished Jul 26 05:43:32 PM PDT 24
Peak memory 214592 kb
Host smart-da293367-5c24-49f5-a19b-3f7b9de95724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699228003 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.699228003
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.321953108
Short name T744
Test name
Test status
Simulation time 94076740630 ps
CPU time 1312.68 seconds
Started Jul 26 05:43:15 PM PDT 24
Finished Jul 26 06:05:07 PM PDT 24
Peak memory 222464 kb
Host smart-a6057dfa-5ace-43da-8a32-9b44b8905d89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321953108 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.321953108
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2027945333
Short name T40
Test name
Test status
Simulation time 40797961 ps
CPU time 1.19 seconds
Started Jul 26 05:43:12 PM PDT 24
Finished Jul 26 05:43:14 PM PDT 24
Peak memory 218576 kb
Host smart-969d5c9d-6030-4160-a3c7-094ab0748a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027945333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2027945333
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3407081251
Short name T606
Test name
Test status
Simulation time 24759716 ps
CPU time 0.91 seconds
Started Jul 26 05:43:30 PM PDT 24
Finished Jul 26 05:43:31 PM PDT 24
Peak memory 214784 kb
Host smart-2937ff3e-eb34-4c47-8ee7-09a056088f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407081251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3407081251
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3504246022
Short name T66
Test name
Test status
Simulation time 11088867 ps
CPU time 0.87 seconds
Started Jul 26 05:43:37 PM PDT 24
Finished Jul 26 05:43:38 PM PDT 24
Peak memory 215988 kb
Host smart-30c880fc-5d69-4b18-9744-1ee315694a3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504246022 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3504246022
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3389998250
Short name T658
Test name
Test status
Simulation time 80171015 ps
CPU time 0.96 seconds
Started Jul 26 05:53:33 PM PDT 24
Finished Jul 26 05:53:34 PM PDT 24
Peak memory 216664 kb
Host smart-f7d7f700-ff82-49a7-9ba1-4089694b681e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389998250 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3389998250
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3529585244
Short name T153
Test name
Test status
Simulation time 21119446 ps
CPU time 1.08 seconds
Started Jul 26 05:43:32 PM PDT 24
Finished Jul 26 05:43:33 PM PDT 24
Peak memory 219376 kb
Host smart-974b4d26-90d4-4b1a-9c26-568f2e4540ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529585244 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3529585244
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3558155056
Short name T510
Test name
Test status
Simulation time 54748827 ps
CPU time 1.01 seconds
Started Jul 26 05:43:31 PM PDT 24
Finished Jul 26 05:43:32 PM PDT 24
Peak memory 217300 kb
Host smart-4e0b8a41-d23e-446e-82da-41c2da09c7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558155056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3558155056
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1108866711
Short name T624
Test name
Test status
Simulation time 21668782 ps
CPU time 1.04 seconds
Started Jul 26 05:43:20 PM PDT 24
Finished Jul 26 05:43:21 PM PDT 24
Peak memory 215676 kb
Host smart-a44de884-bbeb-421c-8ae6-fc473061a4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108866711 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1108866711
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2276588332
Short name T512
Test name
Test status
Simulation time 53858555 ps
CPU time 0.93 seconds
Started Jul 26 05:43:30 PM PDT 24
Finished Jul 26 05:43:31 PM PDT 24
Peak memory 215128 kb
Host smart-37685ee9-e874-42e9-a6eb-3f893d93bd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276588332 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2276588332
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1831696588
Short name T832
Test name
Test status
Simulation time 537625549 ps
CPU time 4.49 seconds
Started Jul 26 05:43:37 PM PDT 24
Finished Jul 26 05:43:42 PM PDT 24
Peak memory 218340 kb
Host smart-857d67e2-47b0-40ac-b978-625377ea9207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831696588 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1831696588
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3730426196
Short name T935
Test name
Test status
Simulation time 85223130907 ps
CPU time 1897.52 seconds
Started Jul 26 05:43:32 PM PDT 24
Finished Jul 26 06:15:10 PM PDT 24
Peak memory 225772 kb
Host smart-93d8b9ca-68fe-4a42-809d-731d2cafb24c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730426196 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3730426196
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.786786026
Short name T142
Test name
Test status
Simulation time 59039866 ps
CPU time 1.08 seconds
Started Jul 26 05:43:18 PM PDT 24
Finished Jul 26 05:43:20 PM PDT 24
Peak memory 219612 kb
Host smart-45ea0b77-57e1-493c-bb14-167929f18154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786786026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.786786026
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1361154698
Short name T54
Test name
Test status
Simulation time 23853218 ps
CPU time 1 seconds
Started Jul 26 05:43:33 PM PDT 24
Finished Jul 26 05:43:34 PM PDT 24
Peak memory 214944 kb
Host smart-da01b781-3daa-4dd4-a5ef-e5092d24d7a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361154698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1361154698
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3388806438
Short name T99
Test name
Test status
Simulation time 31722993 ps
CPU time 1.22 seconds
Started Jul 26 05:43:29 PM PDT 24
Finished Jul 26 05:43:31 PM PDT 24
Peak memory 219476 kb
Host smart-91a2e830-125d-4a8a-bff7-29648c17ac47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388806438 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3388806438
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3926000046
Short name T673
Test name
Test status
Simulation time 83597602 ps
CPU time 0.88 seconds
Started Jul 26 05:43:32 PM PDT 24
Finished Jul 26 05:43:33 PM PDT 24
Peak memory 218148 kb
Host smart-f4856155-8654-4929-9678-8c8150a07eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926000046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3926000046
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3021813124
Short name T335
Test name
Test status
Simulation time 83067243 ps
CPU time 1.24 seconds
Started Jul 26 05:43:13 PM PDT 24
Finished Jul 26 05:43:14 PM PDT 24
Peak memory 219516 kb
Host smart-add4135d-5582-4aa6-adcf-4390aa11bded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021813124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3021813124
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.4017937226
Short name T777
Test name
Test status
Simulation time 22707298 ps
CPU time 1.04 seconds
Started Jul 26 05:43:21 PM PDT 24
Finished Jul 26 05:43:22 PM PDT 24
Peak memory 215444 kb
Host smart-653f25fd-7c09-495d-9afd-18ee12273775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017937226 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.4017937226
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1433559396
Short name T487
Test name
Test status
Simulation time 180178185 ps
CPU time 0.87 seconds
Started Jul 26 05:43:24 PM PDT 24
Finished Jul 26 05:43:25 PM PDT 24
Peak memory 215128 kb
Host smart-35215c09-eca9-4947-bd41-cbef7ada3441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433559396 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1433559396
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2888223308
Short name T860
Test name
Test status
Simulation time 50719716 ps
CPU time 1.54 seconds
Started Jul 26 05:59:30 PM PDT 24
Finished Jul 26 05:59:32 PM PDT 24
Peak memory 215160 kb
Host smart-a83b19ba-8d1f-4e1a-bb21-fd6e99ac3f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888223308 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2888223308
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2652858682
Short name T232
Test name
Test status
Simulation time 38355583987 ps
CPU time 858.24 seconds
Started Jul 26 05:43:28 PM PDT 24
Finished Jul 26 05:57:47 PM PDT 24
Peak memory 223564 kb
Host smart-385ca2af-58d7-4604-9bde-5f22da09655a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652858682 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2652858682
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2447888240
Short name T500
Test name
Test status
Simulation time 76909037 ps
CPU time 1.15 seconds
Started Jul 26 05:43:15 PM PDT 24
Finished Jul 26 05:43:17 PM PDT 24
Peak memory 218280 kb
Host smart-4c8d4401-b080-4699-b9b0-a654db0d4953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447888240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2447888240
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2582948594
Short name T617
Test name
Test status
Simulation time 31909539 ps
CPU time 0.87 seconds
Started Jul 26 05:43:29 PM PDT 24
Finished Jul 26 05:43:30 PM PDT 24
Peak memory 206424 kb
Host smart-11bc01c9-11b6-4b15-a7a9-7e0bf21ed7bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582948594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2582948594
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1384673258
Short name T185
Test name
Test status
Simulation time 20164122 ps
CPU time 0.85 seconds
Started Jul 26 05:43:15 PM PDT 24
Finished Jul 26 05:43:16 PM PDT 24
Peak memory 215264 kb
Host smart-4d38607b-dfbd-4535-858b-8196a33ead04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384673258 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1384673258
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2726716483
Short name T156
Test name
Test status
Simulation time 49017717 ps
CPU time 1.04 seconds
Started Jul 26 05:43:15 PM PDT 24
Finished Jul 26 05:43:16 PM PDT 24
Peak memory 216668 kb
Host smart-26b4dec4-8a92-4668-b441-8c95642d5d57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726716483 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2726716483
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2475802698
Short name T101
Test name
Test status
Simulation time 31853171 ps
CPU time 1.16 seconds
Started Jul 26 05:43:23 PM PDT 24
Finished Jul 26 05:43:24 PM PDT 24
Peak memory 219432 kb
Host smart-c9fd233e-5181-4c74-9dc4-07abeeb3661b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475802698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2475802698
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.630505623
Short name T816
Test name
Test status
Simulation time 4385407643 ps
CPU time 86.44 seconds
Started Jul 26 05:43:20 PM PDT 24
Finished Jul 26 05:44:47 PM PDT 24
Peak memory 220464 kb
Host smart-165e279c-911f-483f-b155-84c470680808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630505623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.630505623
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3366277886
Short name T81
Test name
Test status
Simulation time 23346502 ps
CPU time 0.98 seconds
Started Jul 26 05:43:19 PM PDT 24
Finished Jul 26 05:43:20 PM PDT 24
Peak memory 215596 kb
Host smart-0e195b7f-50ff-490d-99f6-f0d7e6d06ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366277886 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3366277886
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1994877852
Short name T353
Test name
Test status
Simulation time 28750624 ps
CPU time 0.94 seconds
Started Jul 26 05:43:14 PM PDT 24
Finished Jul 26 05:43:20 PM PDT 24
Peak memory 215164 kb
Host smart-a4157106-6a4b-48bd-9392-11c7a1dc0bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994877852 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1994877852
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3739785400
Short name T466
Test name
Test status
Simulation time 815605842 ps
CPU time 4.73 seconds
Started Jul 26 05:43:36 PM PDT 24
Finished Jul 26 05:43:41 PM PDT 24
Peak memory 217096 kb
Host smart-d97e5cd4-e917-4917-a7a4-14f56a79737e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739785400 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3739785400
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_alert.3627477848
Short name T950
Test name
Test status
Simulation time 29832581 ps
CPU time 1.21 seconds
Started Jul 26 05:43:34 PM PDT 24
Finished Jul 26 05:43:35 PM PDT 24
Peak memory 219740 kb
Host smart-a53fd0ab-6a5a-4a09-84b0-ed1ad4a59c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627477848 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3627477848
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.174978559
Short name T400
Test name
Test status
Simulation time 12682912 ps
CPU time 0.85 seconds
Started Jul 26 05:43:40 PM PDT 24
Finished Jul 26 05:43:41 PM PDT 24
Peak memory 206912 kb
Host smart-7ca81b44-03f4-4ced-a4c1-3fc5bd141cd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174978559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.174978559
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2147893292
Short name T802
Test name
Test status
Simulation time 81193142 ps
CPU time 0.85 seconds
Started Jul 26 05:43:37 PM PDT 24
Finished Jul 26 05:43:38 PM PDT 24
Peak memory 215268 kb
Host smart-fae1ceb6-0918-4c4e-9eaf-8f8bc958f16d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147893292 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2147893292
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3936580707
Short name T573
Test name
Test status
Simulation time 43878384 ps
CPU time 1.02 seconds
Started Jul 26 05:43:43 PM PDT 24
Finished Jul 26 05:43:45 PM PDT 24
Peak memory 218476 kb
Host smart-8e0694ba-4b24-49ca-b62d-51c6476bde4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936580707 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3936580707
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1656107379
Short name T121
Test name
Test status
Simulation time 25292394 ps
CPU time 1.09 seconds
Started Jul 26 05:43:31 PM PDT 24
Finished Jul 26 05:43:32 PM PDT 24
Peak memory 223844 kb
Host smart-86061562-d405-49c9-aa1c-0cb58e1b86f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656107379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1656107379
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2740576104
Short name T903
Test name
Test status
Simulation time 70132014 ps
CPU time 1.29 seconds
Started Jul 26 05:43:43 PM PDT 24
Finished Jul 26 05:43:44 PM PDT 24
Peak memory 218732 kb
Host smart-f2088033-d91b-4fb8-9b80-2036b9f2eb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740576104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2740576104
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.393611544
Short name T356
Test name
Test status
Simulation time 28356467 ps
CPU time 0.93 seconds
Started Jul 26 05:43:28 PM PDT 24
Finished Jul 26 05:43:29 PM PDT 24
Peak memory 215236 kb
Host smart-102ec882-0cac-41d9-b377-89fdb39b3f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393611544 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.393611544
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.253345096
Short name T932
Test name
Test status
Simulation time 16783751 ps
CPU time 1.05 seconds
Started Jul 26 05:43:49 PM PDT 24
Finished Jul 26 05:43:50 PM PDT 24
Peak memory 215100 kb
Host smart-3c27bc01-dc00-4ce6-ac5f-83fc493cd9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253345096 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.253345096
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2504118906
Short name T250
Test name
Test status
Simulation time 756331143 ps
CPU time 4.92 seconds
Started Jul 26 05:43:29 PM PDT 24
Finished Jul 26 05:43:34 PM PDT 24
Peak memory 219832 kb
Host smart-c0891ba2-fdf9-4b19-8aa6-05d0861d75d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504118906 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2504118906
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.634696469
Short name T626
Test name
Test status
Simulation time 25866469789 ps
CPU time 605.28 seconds
Started Jul 26 05:43:42 PM PDT 24
Finished Jul 26 05:53:47 PM PDT 24
Peak memory 217636 kb
Host smart-165167fe-c601-4980-be04-82b2797303e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634696469 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.634696469
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1446439232
Short name T820
Test name
Test status
Simulation time 25336790 ps
CPU time 1.18 seconds
Started Jul 26 05:43:41 PM PDT 24
Finished Jul 26 05:43:42 PM PDT 24
Peak memory 220548 kb
Host smart-3a7a0219-d659-4635-aeb4-1cb676d1d2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446439232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1446439232
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.264781697
Short name T56
Test name
Test status
Simulation time 52005731 ps
CPU time 0.95 seconds
Started Jul 26 05:43:35 PM PDT 24
Finished Jul 26 05:43:36 PM PDT 24
Peak memory 206708 kb
Host smart-b35d1e73-9d8d-4ab1-a9a8-5b4612fb80a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264781697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.264781697
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1163063684
Short name T128
Test name
Test status
Simulation time 169875413 ps
CPU time 1.05 seconds
Started Jul 26 05:43:34 PM PDT 24
Finished Jul 26 05:43:35 PM PDT 24
Peak memory 216804 kb
Host smart-ebb8b7dc-c098-4185-909c-f0f8330c6ed3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163063684 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1163063684
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3573088251
Short name T838
Test name
Test status
Simulation time 29234116 ps
CPU time 0.89 seconds
Started Jul 26 05:43:46 PM PDT 24
Finished Jul 26 05:43:47 PM PDT 24
Peak memory 218044 kb
Host smart-9540505e-78c1-4066-8529-edb9eeea591f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573088251 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3573088251
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.366698669
Short name T800
Test name
Test status
Simulation time 28813453 ps
CPU time 1.26 seconds
Started Jul 26 05:43:34 PM PDT 24
Finished Jul 26 05:43:36 PM PDT 24
Peak memory 217304 kb
Host smart-b86dfecd-ca51-4d34-8eb0-315b063a1dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366698669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.366698669
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1137346617
Short name T785
Test name
Test status
Simulation time 22533410 ps
CPU time 1.16 seconds
Started Jul 26 05:43:44 PM PDT 24
Finished Jul 26 05:43:46 PM PDT 24
Peak memory 215416 kb
Host smart-68a5cd24-979f-447e-8ec8-6f6da2c3aef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137346617 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1137346617
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.4194098052
Short name T580
Test name
Test status
Simulation time 76790559 ps
CPU time 0.93 seconds
Started Jul 26 05:43:35 PM PDT 24
Finished Jul 26 05:43:36 PM PDT 24
Peak memory 215040 kb
Host smart-2b24a3d1-0826-4288-b8b3-928d7b9c2f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194098052 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.4194098052
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1016015938
Short name T349
Test name
Test status
Simulation time 171374855 ps
CPU time 2.09 seconds
Started Jul 26 05:43:49 PM PDT 24
Finished Jul 26 05:43:51 PM PDT 24
Peak memory 215092 kb
Host smart-a061f538-228e-4ec2-bdc8-df3b5f21b91c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016015938 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1016015938
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3816595659
Short name T231
Test name
Test status
Simulation time 377879313504 ps
CPU time 1093.71 seconds
Started Jul 26 05:43:25 PM PDT 24
Finished Jul 26 06:01:39 PM PDT 24
Peak memory 221392 kb
Host smart-54eaa146-4d85-4227-aa35-d30c7cd098b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816595659 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3816595659
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.375478625
Short name T303
Test name
Test status
Simulation time 205297853 ps
CPU time 1.23 seconds
Started Jul 26 05:43:34 PM PDT 24
Finished Jul 26 05:43:35 PM PDT 24
Peak memory 219460 kb
Host smart-3be8f757-b8aa-440a-9eed-08447cb7fcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375478625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.375478625
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2657230869
Short name T704
Test name
Test status
Simulation time 57897324 ps
CPU time 1.18 seconds
Started Jul 26 05:43:30 PM PDT 24
Finished Jul 26 05:43:32 PM PDT 24
Peak memory 214824 kb
Host smart-f1b0f83c-a281-4c4c-8784-56227679e1e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657230869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2657230869
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.641468468
Short name T419
Test name
Test status
Simulation time 17560106 ps
CPU time 0.87 seconds
Started Jul 26 05:43:46 PM PDT 24
Finished Jul 26 05:43:47 PM PDT 24
Peak memory 215700 kb
Host smart-01308c8e-4490-453d-bdf6-f781faa17961
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641468468 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.641468468
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3349737235
Short name T85
Test name
Test status
Simulation time 25983756 ps
CPU time 1.07 seconds
Started Jul 26 05:43:44 PM PDT 24
Finished Jul 26 05:43:45 PM PDT 24
Peak memory 216788 kb
Host smart-25cf5399-ef3d-4ec2-be61-4d9e73e6df20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349737235 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3349737235
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2582714556
Short name T409
Test name
Test status
Simulation time 28751614 ps
CPU time 1.02 seconds
Started Jul 26 05:43:26 PM PDT 24
Finished Jul 26 05:43:27 PM PDT 24
Peak memory 223688 kb
Host smart-3c05c416-594e-4b9f-a8f4-b6ab5ee27efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582714556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2582714556
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.586488305
Short name T717
Test name
Test status
Simulation time 98089220 ps
CPU time 1.46 seconds
Started Jul 26 05:43:29 PM PDT 24
Finished Jul 26 05:43:31 PM PDT 24
Peak memory 220000 kb
Host smart-dac565d1-da83-44b6-a66f-9be2b240ffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586488305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.586488305
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1805592629
Short name T851
Test name
Test status
Simulation time 21440605 ps
CPU time 1.07 seconds
Started Jul 26 05:43:43 PM PDT 24
Finished Jul 26 05:43:45 PM PDT 24
Peak memory 215780 kb
Host smart-1b0fbb29-84d7-46c0-adfd-15e1f68ae2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805592629 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1805592629
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.586066740
Short name T870
Test name
Test status
Simulation time 22707765 ps
CPU time 0.9 seconds
Started Jul 26 05:43:42 PM PDT 24
Finished Jul 26 05:43:43 PM PDT 24
Peak memory 215164 kb
Host smart-f9cff885-3e44-4d82-8481-157af1b90448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586066740 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.586066740
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.977121528
Short name T52
Test name
Test status
Simulation time 229478620 ps
CPU time 2.75 seconds
Started Jul 26 05:43:38 PM PDT 24
Finished Jul 26 05:43:41 PM PDT 24
Peak memory 217200 kb
Host smart-cd8efd86-428e-4d26-895b-1234ea3317ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977121528 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.977121528
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1030978078
Short name T233
Test name
Test status
Simulation time 29906194217 ps
CPU time 670.92 seconds
Started Jul 26 05:43:35 PM PDT 24
Finished Jul 26 05:54:46 PM PDT 24
Peak memory 217884 kb
Host smart-803a51aa-96a5-4ccc-8ba7-e63eeb0a7e01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030978078 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1030978078
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.579900024
Short name T464
Test name
Test status
Simulation time 26837804 ps
CPU time 1.19 seconds
Started Jul 26 05:43:47 PM PDT 24
Finished Jul 26 05:43:48 PM PDT 24
Peak memory 218412 kb
Host smart-a5bcd21f-8f5e-4bb9-9aa1-cf01547bf625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579900024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.579900024
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3456380641
Short name T20
Test name
Test status
Simulation time 72616461 ps
CPU time 0.91 seconds
Started Jul 26 05:43:31 PM PDT 24
Finished Jul 26 05:43:37 PM PDT 24
Peak memory 206712 kb
Host smart-c62f8288-a334-427e-80c6-5d34d673cfd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456380641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3456380641
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3432118555
Short name T200
Test name
Test status
Simulation time 12623218 ps
CPU time 0.89 seconds
Started Jul 26 05:43:27 PM PDT 24
Finished Jul 26 05:43:28 PM PDT 24
Peak memory 216312 kb
Host smart-b1ebc1db-58d1-4d8d-9274-be71e62224bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432118555 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3432118555
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1378620374
Short name T93
Test name
Test status
Simulation time 28156241 ps
CPU time 1.08 seconds
Started Jul 26 05:43:45 PM PDT 24
Finished Jul 26 05:43:46 PM PDT 24
Peak memory 216644 kb
Host smart-0a2da417-cb6b-4365-89cf-9303ddaa543e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378620374 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1378620374
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2090189798
Short name T176
Test name
Test status
Simulation time 24900472 ps
CPU time 0.99 seconds
Started Jul 26 05:43:41 PM PDT 24
Finished Jul 26 05:43:42 PM PDT 24
Peak memory 219528 kb
Host smart-eac89f95-c016-4841-a9c3-586800d0ec0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090189798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2090189798
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3404086940
Short name T371
Test name
Test status
Simulation time 45841358 ps
CPU time 1.18 seconds
Started Jul 26 05:43:45 PM PDT 24
Finished Jul 26 05:43:46 PM PDT 24
Peak memory 216988 kb
Host smart-d7dba554-fa3a-4724-829d-6dfca78518e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404086940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3404086940
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3278291288
Short name T130
Test name
Test status
Simulation time 36279582 ps
CPU time 0.86 seconds
Started Jul 26 05:43:30 PM PDT 24
Finished Jul 26 05:43:31 PM PDT 24
Peak memory 215488 kb
Host smart-2fb90a14-e150-4a00-becc-8cbc52772d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278291288 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3278291288
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2539141609
Short name T666
Test name
Test status
Simulation time 52385434 ps
CPU time 0.88 seconds
Started Jul 26 05:43:38 PM PDT 24
Finished Jul 26 05:43:39 PM PDT 24
Peak memory 206964 kb
Host smart-ae527b79-958c-48f5-8a97-970dc62864ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539141609 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2539141609
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2262299468
Short name T986
Test name
Test status
Simulation time 581743469 ps
CPU time 3.53 seconds
Started Jul 26 05:43:28 PM PDT 24
Finished Jul 26 05:43:32 PM PDT 24
Peak memory 217268 kb
Host smart-724efad5-9263-44af-98bb-8d13659403e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262299468 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2262299468
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2414005158
Short name T235
Test name
Test status
Simulation time 75360944361 ps
CPU time 687.08 seconds
Started Jul 26 05:43:33 PM PDT 24
Finished Jul 26 05:55:01 PM PDT 24
Peak memory 223300 kb
Host smart-88c9dd77-74b8-4c72-9d46-3e52df8520db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414005158 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2414005158
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3817424790
Short name T244
Test name
Test status
Simulation time 85166594 ps
CPU time 1.14 seconds
Started Jul 26 05:43:26 PM PDT 24
Finished Jul 26 05:43:27 PM PDT 24
Peak memory 218620 kb
Host smart-daed76dd-7928-4c2e-87c1-1d73b8703376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817424790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3817424790
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2740448355
Short name T50
Test name
Test status
Simulation time 42616038 ps
CPU time 1.05 seconds
Started Jul 26 05:43:48 PM PDT 24
Finished Jul 26 05:43:49 PM PDT 24
Peak memory 206772 kb
Host smart-2db1505f-9997-4485-8dd9-624598903c7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740448355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2740448355
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.552741584
Short name T118
Test name
Test status
Simulation time 17520210 ps
CPU time 0.88 seconds
Started Jul 26 05:43:48 PM PDT 24
Finished Jul 26 05:43:49 PM PDT 24
Peak memory 216076 kb
Host smart-e10e8157-70c3-4cda-93e4-99f720c94c37
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552741584 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.552741584
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.739046833
Short name T55
Test name
Test status
Simulation time 92154502 ps
CPU time 1.03 seconds
Started Jul 26 05:43:37 PM PDT 24
Finished Jul 26 05:43:39 PM PDT 24
Peak memory 216788 kb
Host smart-6ea86362-8c7f-4d58-aae7-88dcba39fcf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739046833 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.739046833
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2180573462
Short name T5
Test name
Test status
Simulation time 76292495 ps
CPU time 1.05 seconds
Started Jul 26 05:43:43 PM PDT 24
Finished Jul 26 05:43:44 PM PDT 24
Peak memory 219564 kb
Host smart-acd2095f-d0e1-4c78-8423-8bb60dd4ee07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180573462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2180573462
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2469690246
Short name T688
Test name
Test status
Simulation time 46221722 ps
CPU time 1.55 seconds
Started Jul 26 05:43:28 PM PDT 24
Finished Jul 26 05:43:30 PM PDT 24
Peak memory 217400 kb
Host smart-486f6289-7f6f-42ec-abb8-b63af2d75f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469690246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2469690246
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.483122178
Short name T45
Test name
Test status
Simulation time 22701469 ps
CPU time 1.19 seconds
Started Jul 26 05:43:38 PM PDT 24
Finished Jul 26 05:43:40 PM PDT 24
Peak memory 223976 kb
Host smart-fea29151-3c09-4839-a92b-04405c0d514f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483122178 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.483122178
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.4257281083
Short name T379
Test name
Test status
Simulation time 42818455 ps
CPU time 0.91 seconds
Started Jul 26 05:43:33 PM PDT 24
Finished Jul 26 05:43:34 PM PDT 24
Peak memory 215132 kb
Host smart-dad62ea6-5d07-4937-adc1-0832bee82b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257281083 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.4257281083
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2505407244
Short name T739
Test name
Test status
Simulation time 244386006 ps
CPU time 2.95 seconds
Started Jul 26 05:43:31 PM PDT 24
Finished Jul 26 05:43:34 PM PDT 24
Peak memory 220180 kb
Host smart-ecc0098d-1cc9-4ed8-93e7-9d6b8c93a778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505407244 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2505407244
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3984928069
Short name T395
Test name
Test status
Simulation time 51283768905 ps
CPU time 626.18 seconds
Started Jul 26 05:43:35 PM PDT 24
Finished Jul 26 05:54:02 PM PDT 24
Peak memory 218240 kb
Host smart-b59095e1-ff3a-45dc-80dd-98304aed1191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984928069 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3984928069
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.61186617
Short name T134
Test name
Test status
Simulation time 71598841 ps
CPU time 1.24 seconds
Started Jul 26 05:43:47 PM PDT 24
Finished Jul 26 05:43:48 PM PDT 24
Peak memory 220768 kb
Host smart-bb97cbc8-6158-4d00-b9db-66a712c34029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61186617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.61186617
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.422734995
Short name T53
Test name
Test status
Simulation time 46685955 ps
CPU time 0.9 seconds
Started Jul 26 05:43:56 PM PDT 24
Finished Jul 26 05:43:57 PM PDT 24
Peak memory 214736 kb
Host smart-059d74bb-f602-4e49-be36-ee92b18b94dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422734995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.422734995
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.4170253677
Short name T629
Test name
Test status
Simulation time 36710646 ps
CPU time 0.83 seconds
Started Jul 26 05:43:34 PM PDT 24
Finished Jul 26 05:43:35 PM PDT 24
Peak memory 216040 kb
Host smart-9da0fafe-1c35-4bfb-aa51-d7512cfb17a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170253677 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.4170253677
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2327974737
Short name T107
Test name
Test status
Simulation time 53672399 ps
CPU time 1.28 seconds
Started Jul 26 05:43:45 PM PDT 24
Finished Jul 26 05:43:47 PM PDT 24
Peak memory 216652 kb
Host smart-0c6dbafa-f575-44e2-a979-e6dccd54b3f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327974737 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2327974737
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3936012812
Short name T48
Test name
Test status
Simulation time 19689697 ps
CPU time 1.14 seconds
Started Jul 26 05:43:50 PM PDT 24
Finished Jul 26 05:43:52 PM PDT 24
Peak memory 223812 kb
Host smart-702babf7-940e-4efb-b4a7-958673f1dd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936012812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3936012812
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1402416185
Short name T600
Test name
Test status
Simulation time 38733649 ps
CPU time 1.13 seconds
Started Jul 26 05:43:43 PM PDT 24
Finished Jul 26 05:43:45 PM PDT 24
Peak memory 217392 kb
Host smart-c4ed6d7a-71c9-4bf4-9058-c41bd3bbd4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402416185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1402416185
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1212623338
Short name T877
Test name
Test status
Simulation time 35848797 ps
CPU time 0.84 seconds
Started Jul 26 05:43:38 PM PDT 24
Finished Jul 26 05:43:39 PM PDT 24
Peak memory 215596 kb
Host smart-e6d1f7b7-f4f2-4807-b6f2-a0f1c256fe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212623338 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1212623338
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1299792571
Short name T410
Test name
Test status
Simulation time 24984246 ps
CPU time 0.91 seconds
Started Jul 26 05:43:45 PM PDT 24
Finished Jul 26 05:43:46 PM PDT 24
Peak memory 215280 kb
Host smart-947ecd1c-e2c5-4820-b42a-1adf0d07cd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299792571 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1299792571
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2210610704
Short name T943
Test name
Test status
Simulation time 104839302 ps
CPU time 2.45 seconds
Started Jul 26 05:43:42 PM PDT 24
Finished Jul 26 05:43:44 PM PDT 24
Peak memory 217112 kb
Host smart-32b25329-c722-4878-a232-e112bd86204c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210610704 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2210610704
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1783118069
Short name T644
Test name
Test status
Simulation time 122906719054 ps
CPU time 764.68 seconds
Started Jul 26 05:43:44 PM PDT 24
Finished Jul 26 05:56:28 PM PDT 24
Peak memory 220872 kb
Host smart-3fd9b71b-a48f-465e-a2bb-3d0273b0a9e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783118069 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1783118069
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3356919084
Short name T566
Test name
Test status
Simulation time 153878334 ps
CPU time 1.2 seconds
Started Jul 26 05:42:20 PM PDT 24
Finished Jul 26 05:42:21 PM PDT 24
Peak memory 218796 kb
Host smart-6ebcebc6-7952-4537-be42-3da752f1a344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356919084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3356919084
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1099220003
Short name T815
Test name
Test status
Simulation time 24834567 ps
CPU time 0.9 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:23 PM PDT 24
Peak memory 215124 kb
Host smart-9c84385e-58ce-45a0-b6dd-4cdcde27537e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099220003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1099220003
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2283197790
Short name T610
Test name
Test status
Simulation time 20595666 ps
CPU time 0.84 seconds
Started Jul 26 05:42:25 PM PDT 24
Finished Jul 26 05:42:26 PM PDT 24
Peak memory 215748 kb
Host smart-b7949d0c-0c83-40fc-8eb2-e06fb761ba37
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283197790 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2283197790
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.1538597537
Short name T712
Test name
Test status
Simulation time 19288408 ps
CPU time 1.14 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:23 PM PDT 24
Peak memory 223872 kb
Host smart-9227abba-78bc-4727-aec3-111c773e8e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538597537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1538597537
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.909192173
Short name T480
Test name
Test status
Simulation time 66280233 ps
CPU time 1.15 seconds
Started Jul 26 05:42:36 PM PDT 24
Finished Jul 26 05:42:38 PM PDT 24
Peak memory 217128 kb
Host smart-b5adcfbf-ce98-487f-874d-3f92c5e10813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909192173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.909192173
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3161248203
Short name T819
Test name
Test status
Simulation time 124657380 ps
CPU time 0.93 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:23 PM PDT 24
Peak memory 223664 kb
Host smart-313a9049-b8ad-4e35-a1e5-9b005b4d501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161248203 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3161248203
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3671599768
Short name T881
Test name
Test status
Simulation time 16466087 ps
CPU time 0.97 seconds
Started Jul 26 05:42:23 PM PDT 24
Finished Jul 26 05:42:24 PM PDT 24
Peak memory 206952 kb
Host smart-d04135d4-12e0-4cb8-8d37-3884fc633f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671599768 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3671599768
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1985157977
Short name T840
Test name
Test status
Simulation time 15757999 ps
CPU time 0.97 seconds
Started Jul 26 05:42:24 PM PDT 24
Finished Jul 26 05:42:25 PM PDT 24
Peak memory 215148 kb
Host smart-919f13c9-bbae-46b2-b7b9-da35d3328303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985157977 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1985157977
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2656240690
Short name T669
Test name
Test status
Simulation time 91288480 ps
CPU time 2.21 seconds
Started Jul 26 05:42:25 PM PDT 24
Finished Jul 26 05:42:28 PM PDT 24
Peak memory 218276 kb
Host smart-a5b7413b-d980-49d3-adec-0c6bc8efd3c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656240690 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2656240690
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.601367958
Short name T837
Test name
Test status
Simulation time 44902164323 ps
CPU time 578.77 seconds
Started Jul 26 05:42:35 PM PDT 24
Finished Jul 26 05:52:14 PM PDT 24
Peak memory 223576 kb
Host smart-73d4e27c-d425-4449-a5e2-a2da260140d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601367958 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.601367958
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.3718406468
Short name T170
Test name
Test status
Simulation time 28368760 ps
CPU time 1.22 seconds
Started Jul 26 05:43:55 PM PDT 24
Finished Jul 26 05:43:57 PM PDT 24
Peak memory 219680 kb
Host smart-03624d2a-6eaf-4e06-8f63-60fd0177fddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718406468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.3718406468
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1161736697
Short name T490
Test name
Test status
Simulation time 47380486 ps
CPU time 0.98 seconds
Started Jul 26 05:43:53 PM PDT 24
Finished Jul 26 05:43:54 PM PDT 24
Peak memory 219676 kb
Host smart-8a952e9b-9466-4531-88a4-7afce758d5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161736697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1161736697
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3877492003
Short name T843
Test name
Test status
Simulation time 52553333 ps
CPU time 1.1 seconds
Started Jul 26 05:43:43 PM PDT 24
Finished Jul 26 05:43:44 PM PDT 24
Peak memory 217276 kb
Host smart-ad8cafb7-29f1-4d94-af77-7104fc1c5202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877492003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3877492003
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3313936911
Short name T747
Test name
Test status
Simulation time 49213083 ps
CPU time 1.2 seconds
Started Jul 26 05:43:46 PM PDT 24
Finished Jul 26 05:43:47 PM PDT 24
Peak memory 219916 kb
Host smart-b3870e19-8693-47ec-86ab-d97a1b21ee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313936911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3313936911
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.2232784601
Short name T790
Test name
Test status
Simulation time 22262550 ps
CPU time 0.89 seconds
Started Jul 26 05:43:47 PM PDT 24
Finished Jul 26 05:43:48 PM PDT 24
Peak memory 218536 kb
Host smart-7166495f-96a9-4711-b9c8-c65a7313175d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232784601 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2232784601
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.407246896
Short name T850
Test name
Test status
Simulation time 62252299 ps
CPU time 1.38 seconds
Started Jul 26 05:43:47 PM PDT 24
Finished Jul 26 05:43:48 PM PDT 24
Peak memory 219828 kb
Host smart-f797eeaa-3cf0-4bbf-89c3-c1379d060651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407246896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.407246896
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.2284299073
Short name T922
Test name
Test status
Simulation time 103896970 ps
CPU time 1.18 seconds
Started Jul 26 05:43:57 PM PDT 24
Finished Jul 26 05:43:59 PM PDT 24
Peak memory 218296 kb
Host smart-476ca75a-90e9-45d1-bcfc-a7f03890981f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284299073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.2284299073
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.1462406840
Short name T47
Test name
Test status
Simulation time 116251291 ps
CPU time 1.03 seconds
Started Jul 26 05:43:41 PM PDT 24
Finished Jul 26 05:43:43 PM PDT 24
Peak memory 229236 kb
Host smart-89f64e72-546b-45fc-9ddc-64ec1a7dd396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462406840 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1462406840
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2952824671
Short name T929
Test name
Test status
Simulation time 32763763 ps
CPU time 1.06 seconds
Started Jul 26 05:43:42 PM PDT 24
Finished Jul 26 05:43:43 PM PDT 24
Peak memory 217480 kb
Host smart-1a6a5c60-4d72-46a9-9ead-5788c2a9d930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952824671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2952824671
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.1138914406
Short name T151
Test name
Test status
Simulation time 35711770 ps
CPU time 1.12 seconds
Started Jul 26 05:43:46 PM PDT 24
Finished Jul 26 05:43:47 PM PDT 24
Peak memory 219656 kb
Host smart-adb966ab-8325-46f7-9ee7-4b169ad5f75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138914406 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.1138914406
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.51551300
Short name T60
Test name
Test status
Simulation time 39467905 ps
CPU time 0.88 seconds
Started Jul 26 05:43:48 PM PDT 24
Finished Jul 26 05:43:49 PM PDT 24
Peak memory 218060 kb
Host smart-94d8f133-9a71-4864-9d23-cb61c98e520c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51551300 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.51551300
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1238848325
Short name T971
Test name
Test status
Simulation time 148469594 ps
CPU time 1.24 seconds
Started Jul 26 05:43:46 PM PDT 24
Finished Jul 26 05:43:48 PM PDT 24
Peak memory 217260 kb
Host smart-6a4fe845-d49f-4b25-baa4-81cda33ad316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238848325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1238848325
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3639224465
Short name T737
Test name
Test status
Simulation time 39406885 ps
CPU time 1.09 seconds
Started Jul 26 05:43:53 PM PDT 24
Finished Jul 26 05:43:54 PM PDT 24
Peak memory 219700 kb
Host smart-58fea465-bf8e-414c-825a-eb2e597d5ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639224465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3639224465
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.476127418
Short name T239
Test name
Test status
Simulation time 33815978 ps
CPU time 0.86 seconds
Started Jul 26 05:43:53 PM PDT 24
Finished Jul 26 05:43:54 PM PDT 24
Peak memory 218076 kb
Host smart-ba4ed7b4-6cd7-415e-aede-9528bc62fbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476127418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.476127418
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3640433873
Short name T921
Test name
Test status
Simulation time 113946065 ps
CPU time 2.23 seconds
Started Jul 26 05:43:56 PM PDT 24
Finished Jul 26 05:43:58 PM PDT 24
Peak memory 219756 kb
Host smart-c3776433-77ae-49e5-b577-99d3de1ffdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640433873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3640433873
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1836237140
Short name T940
Test name
Test status
Simulation time 102033018 ps
CPU time 1.24 seconds
Started Jul 26 05:43:50 PM PDT 24
Finished Jul 26 05:43:51 PM PDT 24
Peak memory 219484 kb
Host smart-1cfbbe02-d5c6-4bfa-8841-ae35244ca0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836237140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1836237140
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2856435406
Short name T145
Test name
Test status
Simulation time 32803516 ps
CPU time 1.18 seconds
Started Jul 26 05:43:41 PM PDT 24
Finished Jul 26 05:43:43 PM PDT 24
Peak memory 229432 kb
Host smart-31bde0b0-2588-43ad-9382-2fc69bb28a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856435406 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2856435406
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3928051872
Short name T948
Test name
Test status
Simulation time 49659369 ps
CPU time 1.24 seconds
Started Jul 26 05:43:35 PM PDT 24
Finished Jul 26 05:43:36 PM PDT 24
Peak memory 218572 kb
Host smart-2235a5ac-2eda-4ed3-a032-5ea8e9d2de8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928051872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3928051872
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2175582638
Short name T889
Test name
Test status
Simulation time 29194799 ps
CPU time 1.35 seconds
Started Jul 26 05:43:49 PM PDT 24
Finished Jul 26 05:43:50 PM PDT 24
Peak memory 219216 kb
Host smart-a571faec-4a8a-4772-87ca-0bef17978576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175582638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2175582638
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.658813056
Short name T7
Test name
Test status
Simulation time 23291400 ps
CPU time 1.17 seconds
Started Jul 26 05:43:56 PM PDT 24
Finished Jul 26 05:43:57 PM PDT 24
Peak memory 219436 kb
Host smart-6e6fa6c0-35aa-4730-a6c3-df7e03023d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658813056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.658813056
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.109449153
Short name T544
Test name
Test status
Simulation time 24775188 ps
CPU time 1.15 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 217272 kb
Host smart-8dac34f7-778e-4406-929c-b4ffdeba5540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109449153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.109449153
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.262436240
Short name T367
Test name
Test status
Simulation time 30484836 ps
CPU time 1.33 seconds
Started Jul 26 05:43:48 PM PDT 24
Finished Jul 26 05:43:50 PM PDT 24
Peak memory 219480 kb
Host smart-cf800070-4536-4687-96aa-e81eede2417f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262436240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.262436240
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.968192114
Short name T105
Test name
Test status
Simulation time 25129514 ps
CPU time 0.96 seconds
Started Jul 26 05:43:48 PM PDT 24
Finished Jul 26 05:43:50 PM PDT 24
Peak memory 218624 kb
Host smart-83d6f75b-5426-4acf-a785-6093238f4165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968192114 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.968192114
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.925572007
Short name T648
Test name
Test status
Simulation time 53865192 ps
CPU time 1.35 seconds
Started Jul 26 05:43:57 PM PDT 24
Finished Jul 26 05:43:58 PM PDT 24
Peak memory 217116 kb
Host smart-4da2a58a-59f1-44b7-ab05-623051199368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925572007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.925572007
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3496031428
Short name T663
Test name
Test status
Simulation time 27613557 ps
CPU time 1.25 seconds
Started Jul 26 05:43:47 PM PDT 24
Finished Jul 26 05:43:48 PM PDT 24
Peak memory 215536 kb
Host smart-b68aeeeb-cd81-4497-8056-6f6c18494d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496031428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3496031428
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2655968538
Short name T551
Test name
Test status
Simulation time 20397172 ps
CPU time 1.06 seconds
Started Jul 26 05:43:50 PM PDT 24
Finished Jul 26 05:43:51 PM PDT 24
Peak memory 218300 kb
Host smart-831f0d3a-e618-4622-898f-a2d5b30c5ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655968538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2655968538
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2003106983
Short name T406
Test name
Test status
Simulation time 59224033 ps
CPU time 1.99 seconds
Started Jul 26 05:43:48 PM PDT 24
Finished Jul 26 05:43:50 PM PDT 24
Peak memory 218444 kb
Host smart-d4bdde29-1c4e-4af5-9549-4363e390db1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003106983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2003106983
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3880524980
Short name T576
Test name
Test status
Simulation time 29926305 ps
CPU time 1.27 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:53 PM PDT 24
Peak memory 220716 kb
Host smart-2777f738-91bc-420a-9de9-ba3b6e8d328d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880524980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3880524980
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2374593930
Short name T193
Test name
Test status
Simulation time 19869953 ps
CPU time 1.07 seconds
Started Jul 26 05:43:44 PM PDT 24
Finished Jul 26 05:43:45 PM PDT 24
Peak memory 218216 kb
Host smart-076f51db-cfc6-4a28-8782-ed046356250f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374593930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2374593930
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.4163710622
Short name T728
Test name
Test status
Simulation time 51508760 ps
CPU time 1.88 seconds
Started Jul 26 05:43:44 PM PDT 24
Finished Jul 26 05:43:46 PM PDT 24
Peak memory 218280 kb
Host smart-bc94e8ab-bf2f-464a-a8d2-43e65aa001dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163710622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.4163710622
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1083919002
Short name T898
Test name
Test status
Simulation time 55260206 ps
CPU time 1.09 seconds
Started Jul 26 05:42:26 PM PDT 24
Finished Jul 26 05:42:28 PM PDT 24
Peak memory 219660 kb
Host smart-3ef8bf2f-09dc-4cd7-9bdf-67509c8c466d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083919002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1083919002
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3757849455
Short name T575
Test name
Test status
Simulation time 40609208 ps
CPU time 0.82 seconds
Started Jul 26 05:42:21 PM PDT 24
Finished Jul 26 05:42:22 PM PDT 24
Peak memory 206352 kb
Host smart-81b5101e-4047-4db0-ae8a-8ce9d2bab6b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757849455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3757849455
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2022443832
Short name T201
Test name
Test status
Simulation time 14057642 ps
CPU time 0.93 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:24 PM PDT 24
Peak memory 216392 kb
Host smart-edb18ba2-37fc-484a-a3a1-7a73bbc03b95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022443832 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2022443832
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3234347476
Short name T773
Test name
Test status
Simulation time 33132952 ps
CPU time 1.14 seconds
Started Jul 26 05:42:42 PM PDT 24
Finished Jul 26 05:42:44 PM PDT 24
Peak memory 216580 kb
Host smart-df8120a4-5f16-4c71-9a7e-ed2609b6bf68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234347476 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3234347476
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2291502991
Short name T208
Test name
Test status
Simulation time 23585916 ps
CPU time 1.02 seconds
Started Jul 26 05:42:24 PM PDT 24
Finished Jul 26 05:42:26 PM PDT 24
Peak memory 223872 kb
Host smart-d2fc1881-579a-4156-9421-6b24fe9183c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291502991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2291502991
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2152409071
Short name T578
Test name
Test status
Simulation time 54867059 ps
CPU time 1.26 seconds
Started Jul 26 05:42:20 PM PDT 24
Finished Jul 26 05:42:21 PM PDT 24
Peak memory 215120 kb
Host smart-4d707185-a3e2-49dc-a246-5b7e83fbb221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152409071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2152409071
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2826887639
Short name T952
Test name
Test status
Simulation time 28346645 ps
CPU time 0.89 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:23 PM PDT 24
Peak memory 215752 kb
Host smart-2fa996df-ccb7-4a9e-87bc-26075191ca27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826887639 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2826887639
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.470101669
Short name T74
Test name
Test status
Simulation time 39429704 ps
CPU time 0.88 seconds
Started Jul 26 05:42:30 PM PDT 24
Finished Jul 26 05:42:31 PM PDT 24
Peak memory 206948 kb
Host smart-923371e4-fac4-40fd-8fe7-3c5a944940c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470101669 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.470101669
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.478272953
Short name T803
Test name
Test status
Simulation time 26839048 ps
CPU time 0.99 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:23 PM PDT 24
Peak memory 215160 kb
Host smart-8a537922-1bca-49a7-84a4-5a44f103caef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478272953 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.478272953
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1612773549
Short name T18
Test name
Test status
Simulation time 64291786 ps
CPU time 1.81 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:24 PM PDT 24
Peak memory 217180 kb
Host smart-646aea37-887e-401e-9153-340e6a0a5d33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612773549 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1612773549
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1359643674
Short name T543
Test name
Test status
Simulation time 36807744531 ps
CPU time 450.37 seconds
Started Jul 26 05:42:20 PM PDT 24
Finished Jul 26 05:49:50 PM PDT 24
Peak memory 223556 kb
Host smart-bd2354e3-a82d-449a-a383-8d9603c555e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359643674 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1359643674
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.4291639810
Short name T248
Test name
Test status
Simulation time 49059647 ps
CPU time 1.24 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:52 PM PDT 24
Peak memory 219964 kb
Host smart-ff29a97a-b6b9-487e-a2d4-1eecf81f18f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291639810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.4291639810
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1114756050
Short name T726
Test name
Test status
Simulation time 29799637 ps
CPU time 0.97 seconds
Started Jul 26 05:43:47 PM PDT 24
Finished Jul 26 05:43:48 PM PDT 24
Peak memory 218312 kb
Host smart-d3d6051e-1b90-45f8-ab42-5a5b29450518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114756050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1114756050
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2563754376
Short name T65
Test name
Test status
Simulation time 61729493 ps
CPU time 1.21 seconds
Started Jul 26 05:43:53 PM PDT 24
Finished Jul 26 05:43:55 PM PDT 24
Peak memory 218568 kb
Host smart-31f8f52f-0b90-47de-a9ab-e9e122b6652d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563754376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2563754376
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1382357084
Short name T964
Test name
Test status
Simulation time 259399681 ps
CPU time 1.33 seconds
Started Jul 26 05:43:45 PM PDT 24
Finished Jul 26 05:43:46 PM PDT 24
Peak memory 219876 kb
Host smart-70d3e082-2ab7-483e-8664-ebdd49c94927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382357084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1382357084
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.2423140083
Short name T171
Test name
Test status
Simulation time 29679424 ps
CPU time 1.24 seconds
Started Jul 26 05:43:56 PM PDT 24
Finished Jul 26 05:43:57 PM PDT 24
Peak memory 229452 kb
Host smart-fdf9d3e6-bc44-4498-a99c-e7e86eb55bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423140083 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2423140083
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2328748333
Short name T9
Test name
Test status
Simulation time 29933890 ps
CPU time 1.32 seconds
Started Jul 26 05:43:49 PM PDT 24
Finished Jul 26 05:43:50 PM PDT 24
Peak memory 219824 kb
Host smart-79d70f41-4257-4f87-aa62-3303ff572d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328748333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2328748333
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.1498525840
Short name T246
Test name
Test status
Simulation time 28111288 ps
CPU time 1.25 seconds
Started Jul 26 05:43:53 PM PDT 24
Finished Jul 26 05:43:55 PM PDT 24
Peak memory 218452 kb
Host smart-cfb9cbc9-2b41-4058-908c-290fbb64db9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498525840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1498525840
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2663083897
Short name T567
Test name
Test status
Simulation time 89612866 ps
CPU time 1.07 seconds
Started Jul 26 05:43:53 PM PDT 24
Finished Jul 26 05:44:00 PM PDT 24
Peak memory 219572 kb
Host smart-8b0a68ef-94a8-4ccb-a97a-7e012f0ac7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663083897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2663083897
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1097229990
Short name T646
Test name
Test status
Simulation time 48801730 ps
CPU time 1.58 seconds
Started Jul 26 05:43:59 PM PDT 24
Finished Jul 26 05:44:01 PM PDT 24
Peak memory 218316 kb
Host smart-e3d44274-5c08-4576-a54c-ebdb3e0e90dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097229990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1097229990
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2109554049
Short name T252
Test name
Test status
Simulation time 92387022 ps
CPU time 1.21 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:53 PM PDT 24
Peak memory 218512 kb
Host smart-c570b590-6e23-4a37-b2e4-d24f2d76540d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109554049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2109554049
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.2095593802
Short name T240
Test name
Test status
Simulation time 19101791 ps
CPU time 1.1 seconds
Started Jul 26 05:43:49 PM PDT 24
Finished Jul 26 05:43:50 PM PDT 24
Peak memory 215332 kb
Host smart-87298535-960c-4d2a-bddf-c5197d03bc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095593802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2095593802
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2469934382
Short name T28
Test name
Test status
Simulation time 62359174 ps
CPU time 1.16 seconds
Started Jul 26 05:43:54 PM PDT 24
Finished Jul 26 05:43:55 PM PDT 24
Peak memory 218228 kb
Host smart-d1c285ef-4587-4788-aa01-266e2f09b1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469934382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2469934382
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.3502016367
Short name T216
Test name
Test status
Simulation time 71698612 ps
CPU time 1.23 seconds
Started Jul 26 05:43:58 PM PDT 24
Finished Jul 26 05:43:59 PM PDT 24
Peak memory 218352 kb
Host smart-c3b78268-4163-4924-bddf-e211554df160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502016367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.3502016367
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.3966053568
Short name T215
Test name
Test status
Simulation time 59591229 ps
CPU time 0.84 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:52 PM PDT 24
Peak memory 219212 kb
Host smart-667c9d3a-3fda-480a-9e06-8f13121f487b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966053568 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3966053568
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3024757255
Short name T468
Test name
Test status
Simulation time 220165691 ps
CPU time 1.15 seconds
Started Jul 26 05:43:48 PM PDT 24
Finished Jul 26 05:43:49 PM PDT 24
Peak memory 217204 kb
Host smart-bcf80dce-02f0-4658-93b0-bcab01856482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024757255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3024757255
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.466130521
Short name T202
Test name
Test status
Simulation time 25243948 ps
CPU time 1.14 seconds
Started Jul 26 05:44:00 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 219564 kb
Host smart-b24a5271-5e41-4418-866d-b6f65fe54d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466130521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.466130521
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.4002748070
Short name T529
Test name
Test status
Simulation time 86685068 ps
CPU time 1.17 seconds
Started Jul 26 05:43:58 PM PDT 24
Finished Jul 26 05:43:59 PM PDT 24
Peak memory 219632 kb
Host smart-adfbdb8d-fbb7-4f75-99b4-a621b038ce9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002748070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4002748070
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2228588125
Short name T465
Test name
Test status
Simulation time 66400371 ps
CPU time 1.69 seconds
Started Jul 26 05:43:54 PM PDT 24
Finished Jul 26 05:43:56 PM PDT 24
Peak memory 218540 kb
Host smart-7ed0a2ef-0b5e-495d-887e-aba856261062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228588125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2228588125
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_genbits.2102054689
Short name T615
Test name
Test status
Simulation time 403571110 ps
CPU time 4.5 seconds
Started Jul 26 05:43:58 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 218516 kb
Host smart-bedb2dd9-a50c-4383-b6bd-694d39695748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102054689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2102054689
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.3691565091
Short name T931
Test name
Test status
Simulation time 83327118 ps
CPU time 1.13 seconds
Started Jul 26 05:43:52 PM PDT 24
Finished Jul 26 05:43:54 PM PDT 24
Peak memory 219776 kb
Host smart-d2062c82-9c98-44cd-9a5a-6974c93b7c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691565091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.3691565091
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.3297839488
Short name T403
Test name
Test status
Simulation time 20587528 ps
CPU time 1 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:52 PM PDT 24
Peak memory 223924 kb
Host smart-3377aea5-ede5-4d9d-9c65-2bc4d1e1c13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297839488 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3297839488
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.721433863
Short name T896
Test name
Test status
Simulation time 49594992 ps
CPU time 1.25 seconds
Started Jul 26 05:43:56 PM PDT 24
Finished Jul 26 05:43:57 PM PDT 24
Peak memory 218752 kb
Host smart-c04d33ea-176e-4f84-a7d2-56cb6a386f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721433863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.721433863
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.4170585639
Short name T849
Test name
Test status
Simulation time 43611660 ps
CPU time 1.24 seconds
Started Jul 26 05:43:47 PM PDT 24
Finished Jul 26 05:43:48 PM PDT 24
Peak memory 220164 kb
Host smart-3b5cbf60-5959-4b52-8981-b8e8348770cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170585639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.4170585639
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.1322034993
Short name T951
Test name
Test status
Simulation time 30479952 ps
CPU time 0.9 seconds
Started Jul 26 05:43:58 PM PDT 24
Finished Jul 26 05:43:59 PM PDT 24
Peak memory 218480 kb
Host smart-ecdcee22-ae1c-439d-8295-d53fffca1bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322034993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1322034993
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.597161567
Short name T324
Test name
Test status
Simulation time 55783241 ps
CPU time 1.06 seconds
Started Jul 26 05:43:53 PM PDT 24
Finished Jul 26 05:43:54 PM PDT 24
Peak memory 218976 kb
Host smart-b4e0c207-15af-44aa-af85-c85d1c39da81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597161567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.597161567
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.4017544061
Short name T211
Test name
Test status
Simulation time 75732500 ps
CPU time 1.17 seconds
Started Jul 26 05:43:54 PM PDT 24
Finished Jul 26 05:43:56 PM PDT 24
Peak memory 220284 kb
Host smart-66b1b284-9318-4391-b595-7857c64ec909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017544061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.4017544061
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2059845885
Short name T191
Test name
Test status
Simulation time 23638976 ps
CPU time 0.9 seconds
Started Jul 26 05:43:55 PM PDT 24
Finished Jul 26 05:43:56 PM PDT 24
Peak memory 218208 kb
Host smart-f2c4b1bf-7946-4c9b-98e8-ec8fb54448a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059845885 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2059845885
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.335299316
Short name T825
Test name
Test status
Simulation time 39509542 ps
CPU time 1.43 seconds
Started Jul 26 05:43:52 PM PDT 24
Finished Jul 26 05:43:54 PM PDT 24
Peak memory 218396 kb
Host smart-43aef471-71af-438e-9b94-ba3331b26cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335299316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.335299316
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2118541879
Short name T194
Test name
Test status
Simulation time 144677035 ps
CPU time 1.07 seconds
Started Jul 26 05:42:25 PM PDT 24
Finished Jul 26 05:42:26 PM PDT 24
Peak memory 218276 kb
Host smart-44d4b70f-c969-494b-a684-19d1fdfcbf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118541879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2118541879
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2977174882
Short name T365
Test name
Test status
Simulation time 39042833 ps
CPU time 0.86 seconds
Started Jul 26 05:42:23 PM PDT 24
Finished Jul 26 05:42:24 PM PDT 24
Peak memory 206676 kb
Host smart-5842acde-1bce-4627-ac94-2461f342713b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977174882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2977174882
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.4053162922
Short name T786
Test name
Test status
Simulation time 29759238 ps
CPU time 0.86 seconds
Started Jul 26 05:42:24 PM PDT 24
Finished Jul 26 05:42:25 PM PDT 24
Peak memory 216132 kb
Host smart-cf907123-bd85-4507-884c-bf0490fbdb27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053162922 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.4053162922
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3091484075
Short name T842
Test name
Test status
Simulation time 31299066 ps
CPU time 1.02 seconds
Started Jul 26 05:42:31 PM PDT 24
Finished Jul 26 05:42:33 PM PDT 24
Peak memory 216752 kb
Host smart-f078f012-eb22-4209-8d56-fcea7a0aa18a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091484075 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3091484075
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.576630327
Short name T4
Test name
Test status
Simulation time 41887212 ps
CPU time 1.41 seconds
Started Jul 26 05:42:24 PM PDT 24
Finished Jul 26 05:42:25 PM PDT 24
Peak memory 225604 kb
Host smart-bc2e0dcb-a87d-4653-a63f-58f0cbbffe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576630327 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.576630327
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1772539143
Short name T67
Test name
Test status
Simulation time 28856704 ps
CPU time 1.22 seconds
Started Jul 26 05:42:18 PM PDT 24
Finished Jul 26 05:42:19 PM PDT 24
Peak memory 216968 kb
Host smart-4b96ca68-8429-4603-979b-1b6015b8b338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772539143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1772539143
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2380956185
Short name T459
Test name
Test status
Simulation time 25702478 ps
CPU time 0.92 seconds
Started Jul 26 05:42:36 PM PDT 24
Finished Jul 26 05:42:37 PM PDT 24
Peak memory 215432 kb
Host smart-00c5097f-7c69-4a41-b9e9-a3aa0685a211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380956185 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2380956185
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3395773491
Short name T75
Test name
Test status
Simulation time 15969550 ps
CPU time 0.99 seconds
Started Jul 26 05:42:21 PM PDT 24
Finished Jul 26 05:42:22 PM PDT 24
Peak memory 207060 kb
Host smart-c5df44e1-2160-4dff-acc0-0b14302ecbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395773491 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3395773491
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2586696120
Short name T553
Test name
Test status
Simulation time 19839227 ps
CPU time 1.03 seconds
Started Jul 26 05:42:22 PM PDT 24
Finished Jul 26 05:42:23 PM PDT 24
Peak memory 215336 kb
Host smart-87989186-d58f-4b1d-93f5-8d6d07c29e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586696120 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2586696120
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.640630708
Short name T767
Test name
Test status
Simulation time 503484980 ps
CPU time 5.17 seconds
Started Jul 26 05:42:43 PM PDT 24
Finished Jul 26 05:42:48 PM PDT 24
Peak memory 215080 kb
Host smart-e3537845-6f8d-4037-bea5-3d2d4012a343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640630708 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.640630708
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1829011353
Short name T133
Test name
Test status
Simulation time 22571126886 ps
CPU time 551.39 seconds
Started Jul 26 05:42:23 PM PDT 24
Finished Jul 26 05:51:35 PM PDT 24
Peak memory 217916 kb
Host smart-3e40665f-9cac-4e23-aa5b-35939012dd77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829011353 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1829011353
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.4145843576
Short name T696
Test name
Test status
Simulation time 23405579 ps
CPU time 1.19 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:53 PM PDT 24
Peak memory 219656 kb
Host smart-2ac5eb32-57c1-4ad7-80cc-f42297353c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145843576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.4145843576
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2176677752
Short name T660
Test name
Test status
Simulation time 82682293 ps
CPU time 1.03 seconds
Started Jul 26 05:43:46 PM PDT 24
Finished Jul 26 05:43:47 PM PDT 24
Peak memory 220700 kb
Host smart-f437d96d-fb35-4b24-a85e-aec3cfd6c077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176677752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2176677752
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.798465568
Short name T895
Test name
Test status
Simulation time 218055719 ps
CPU time 1.1 seconds
Started Jul 26 05:43:56 PM PDT 24
Finished Jul 26 05:43:57 PM PDT 24
Peak memory 215284 kb
Host smart-85198f7b-cd13-456e-9872-d8a1f5eac4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798465568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.798465568
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2869697132
Short name T57
Test name
Test status
Simulation time 77166714 ps
CPU time 1.1 seconds
Started Jul 26 05:44:00 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 220604 kb
Host smart-d75e9080-7473-475b-8969-dbc110b2e518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869697132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2869697132
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.431506500
Short name T979
Test name
Test status
Simulation time 28312489 ps
CPU time 1.19 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 219464 kb
Host smart-3a14151e-e21b-49fb-af28-e1fd3435fd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431506500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.431506500
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.312832528
Short name T421
Test name
Test status
Simulation time 91632603 ps
CPU time 1.35 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:53 PM PDT 24
Peak memory 218884 kb
Host smart-bf05d1f6-d43d-4c1f-aee0-b16a0571a97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312832528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.312832528
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.3092098396
Short name T46
Test name
Test status
Simulation time 39316412 ps
CPU time 1.05 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:52 PM PDT 24
Peak memory 223676 kb
Host smart-efeae629-4abb-4874-9d72-8a78cc5a7ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092098396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3092098396
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3571748389
Short name T14
Test name
Test status
Simulation time 31089201 ps
CPU time 1.29 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:03 PM PDT 24
Peak memory 219784 kb
Host smart-315c2cae-03d6-4297-ad54-fea911a2c321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571748389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3571748389
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3422891043
Short name T415
Test name
Test status
Simulation time 126039225 ps
CPU time 1.2 seconds
Started Jul 26 05:43:50 PM PDT 24
Finished Jul 26 05:43:52 PM PDT 24
Peak memory 218488 kb
Host smart-ffac3e30-e5fc-4b62-984d-ca1baaf265bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422891043 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3422891043
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3868612924
Short name T655
Test name
Test status
Simulation time 32629622 ps
CPU time 0.92 seconds
Started Jul 26 05:43:49 PM PDT 24
Finished Jul 26 05:43:50 PM PDT 24
Peak memory 219520 kb
Host smart-29888667-811c-4916-9b88-fe0365c03841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868612924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3868612924
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.4036947760
Short name T293
Test name
Test status
Simulation time 41692063 ps
CPU time 1.71 seconds
Started Jul 26 05:44:03 PM PDT 24
Finished Jul 26 05:44:05 PM PDT 24
Peak memory 218464 kb
Host smart-6d3919d9-b70b-4d9e-830d-8784740735c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036947760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.4036947760
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.813892484
Short name T796
Test name
Test status
Simulation time 21217793 ps
CPU time 1.12 seconds
Started Jul 26 05:43:40 PM PDT 24
Finished Jul 26 05:43:41 PM PDT 24
Peak memory 218500 kb
Host smart-2508e113-bd90-4919-b022-f8fd25dc60ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813892484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.813892484
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2277387942
Short name T427
Test name
Test status
Simulation time 34960998 ps
CPU time 0.88 seconds
Started Jul 26 05:43:55 PM PDT 24
Finished Jul 26 05:43:56 PM PDT 24
Peak memory 219744 kb
Host smart-ff564907-5775-41bc-8f00-63d6dd9814d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277387942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2277387942
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.333706994
Short name T362
Test name
Test status
Simulation time 63383959 ps
CPU time 1.54 seconds
Started Jul 26 05:43:46 PM PDT 24
Finished Jul 26 05:43:48 PM PDT 24
Peak memory 218392 kb
Host smart-05f1f82b-430c-4753-83bf-df513796ab13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333706994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.333706994
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.2124707745
Short name T137
Test name
Test status
Simulation time 23755663 ps
CPU time 0.93 seconds
Started Jul 26 05:43:54 PM PDT 24
Finished Jul 26 05:43:55 PM PDT 24
Peak memory 218436 kb
Host smart-7cb10834-11e3-4538-b1c0-4590e212a687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124707745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2124707745
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.424322889
Short name T422
Test name
Test status
Simulation time 35105346 ps
CPU time 1.34 seconds
Started Jul 26 05:43:50 PM PDT 24
Finished Jul 26 05:43:51 PM PDT 24
Peak memory 217444 kb
Host smart-7fa1490f-9210-4c29-b2fb-31cf6a38396d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424322889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.424322889
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.1144367206
Short name T524
Test name
Test status
Simulation time 216127371 ps
CPU time 1.3 seconds
Started Jul 26 05:43:50 PM PDT 24
Finished Jul 26 05:43:51 PM PDT 24
Peak memory 215560 kb
Host smart-729fe8a4-1cf7-4dcf-902b-98b65cec6f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144367206 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1144367206
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.3330442333
Short name T636
Test name
Test status
Simulation time 23043922 ps
CPU time 1.26 seconds
Started Jul 26 05:44:08 PM PDT 24
Finished Jul 26 05:44:10 PM PDT 24
Peak memory 223924 kb
Host smart-d0f68560-1152-48ea-89dc-3729e51370ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330442333 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3330442333
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1557267491
Short name T417
Test name
Test status
Simulation time 34750075 ps
CPU time 1.28 seconds
Started Jul 26 05:43:49 PM PDT 24
Finished Jul 26 05:43:50 PM PDT 24
Peak memory 219464 kb
Host smart-6b4e22ad-0a39-4625-9181-31e5df9a23b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557267491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1557267491
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.3178266121
Short name T719
Test name
Test status
Simulation time 34268602 ps
CPU time 1.24 seconds
Started Jul 26 05:43:56 PM PDT 24
Finished Jul 26 05:43:58 PM PDT 24
Peak memory 220788 kb
Host smart-2559cbff-9ebc-4f93-b96c-e7e6f8923b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178266121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.3178266121
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3491020896
Short name T364
Test name
Test status
Simulation time 21751293 ps
CPU time 0.94 seconds
Started Jul 26 05:43:46 PM PDT 24
Finished Jul 26 05:43:47 PM PDT 24
Peak memory 218496 kb
Host smart-8c1e76df-fcef-4050-a002-b41b013d49d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491020896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3491020896
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1131175746
Short name T36
Test name
Test status
Simulation time 73068410 ps
CPU time 1.53 seconds
Started Jul 26 05:43:48 PM PDT 24
Finished Jul 26 05:43:50 PM PDT 24
Peak memory 218512 kb
Host smart-5698cdde-e21f-4fd7-8ed8-32fdfc2745f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131175746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1131175746
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.249101071
Short name T592
Test name
Test status
Simulation time 40952464 ps
CPU time 1.27 seconds
Started Jul 26 05:43:53 PM PDT 24
Finished Jul 26 05:43:54 PM PDT 24
Peak memory 219580 kb
Host smart-6546366d-78cc-476a-8bd3-053d363deae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249101071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.249101071
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.3001675160
Short name T197
Test name
Test status
Simulation time 23793378 ps
CPU time 1.13 seconds
Started Jul 26 05:43:53 PM PDT 24
Finished Jul 26 05:43:54 PM PDT 24
Peak memory 223880 kb
Host smart-8e60687b-91f7-4ca6-988c-4ce237a0bdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001675160 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3001675160
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2639598445
Short name T955
Test name
Test status
Simulation time 71639037 ps
CPU time 0.99 seconds
Started Jul 26 05:43:52 PM PDT 24
Finished Jul 26 05:43:53 PM PDT 24
Peak memory 217056 kb
Host smart-1204776c-bc1c-41c0-9235-44e2922e3a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639598445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2639598445
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1049138647
Short name T628
Test name
Test status
Simulation time 73166622 ps
CPU time 1.14 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:53 PM PDT 24
Peak memory 219728 kb
Host smart-9d7aba7f-fc11-41cf-800e-64e84be58130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049138647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1049138647
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.667872999
Short name T916
Test name
Test status
Simulation time 20618006 ps
CPU time 1.1 seconds
Started Jul 26 05:43:48 PM PDT 24
Finished Jul 26 05:43:49 PM PDT 24
Peak memory 219852 kb
Host smart-cb53d874-3516-42fe-abbc-3b7c152ce07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667872999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.667872999
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert.505206321
Short name T858
Test name
Test status
Simulation time 94251581 ps
CPU time 1.28 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 05:42:42 PM PDT 24
Peak memory 218596 kb
Host smart-755eba1d-6bf0-4962-aa81-432ec322a519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505206321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.505206321
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1994660866
Short name T429
Test name
Test status
Simulation time 21928537 ps
CPU time 1.02 seconds
Started Jul 26 05:42:38 PM PDT 24
Finished Jul 26 05:42:40 PM PDT 24
Peak memory 206608 kb
Host smart-55753414-547f-462e-bd3b-56e14b408a8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994660866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1994660866
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2922968121
Short name T716
Test name
Test status
Simulation time 30197412 ps
CPU time 0.84 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 05:42:43 PM PDT 24
Peak memory 215764 kb
Host smart-68915042-92c9-48be-8fe5-bdbcde810c01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922968121 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2922968121
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2587461763
Short name T762
Test name
Test status
Simulation time 26720977 ps
CPU time 1.07 seconds
Started Jul 26 05:42:43 PM PDT 24
Finished Jul 26 05:42:44 PM PDT 24
Peak memory 218496 kb
Host smart-b09ba82f-5e1c-48e6-a6e0-1d424d501e1c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587461763 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2587461763
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3142329732
Short name T196
Test name
Test status
Simulation time 19494181 ps
CPU time 1.1 seconds
Started Jul 26 05:42:43 PM PDT 24
Finished Jul 26 05:42:45 PM PDT 24
Peak memory 218288 kb
Host smart-d039e829-ea2b-4baa-907b-140e084e4a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142329732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3142329732
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1202044410
Short name T705
Test name
Test status
Simulation time 63621472 ps
CPU time 1.56 seconds
Started Jul 26 05:42:23 PM PDT 24
Finished Jul 26 05:42:25 PM PDT 24
Peak memory 218424 kb
Host smart-0ef8b174-e948-4705-bc66-8cbbccc70a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202044410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1202044410
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3725608658
Short name T924
Test name
Test status
Simulation time 21783004 ps
CPU time 0.96 seconds
Started Jul 26 05:42:37 PM PDT 24
Finished Jul 26 05:42:38 PM PDT 24
Peak memory 215380 kb
Host smart-69d51bc6-87fe-4079-8b56-ab5b2c7d818f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725608658 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3725608658
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3230271699
Short name T598
Test name
Test status
Simulation time 45143267 ps
CPU time 0.91 seconds
Started Jul 26 05:42:30 PM PDT 24
Finished Jul 26 05:42:31 PM PDT 24
Peak memory 206948 kb
Host smart-b871b471-455c-468a-8629-70b8e6d9c291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230271699 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3230271699
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2974654043
Short name T370
Test name
Test status
Simulation time 23894788 ps
CPU time 0.92 seconds
Started Jul 26 05:42:24 PM PDT 24
Finished Jul 26 05:42:25 PM PDT 24
Peak memory 215108 kb
Host smart-550733c2-b286-4359-9cfc-02015433c13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974654043 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2974654043
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1834833243
Short name T96
Test name
Test status
Simulation time 205106527 ps
CPU time 4.08 seconds
Started Jul 26 05:42:23 PM PDT 24
Finished Jul 26 05:42:28 PM PDT 24
Peak memory 219848 kb
Host smart-847e935e-bd1a-403c-91ac-2776d03638b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834833243 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1834833243
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2314799510
Short name T795
Test name
Test status
Simulation time 422671676462 ps
CPU time 1873.36 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 06:13:55 PM PDT 24
Peak memory 227284 kb
Host smart-7a153049-43f9-4bc7-8e91-2e149edd6b68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314799510 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2314799510
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3830242920
Short name T526
Test name
Test status
Simulation time 30506976 ps
CPU time 0.97 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 223760 kb
Host smart-8db3116c-7812-4c73-ba76-11e191ba2045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830242920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3830242920
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.540204402
Short name T701
Test name
Test status
Simulation time 78165165 ps
CPU time 1.13 seconds
Started Jul 26 05:43:59 PM PDT 24
Finished Jul 26 05:44:00 PM PDT 24
Peak memory 217056 kb
Host smart-93faa9f1-6ff3-4570-8fbe-6be83b2da3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540204402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.540204402
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2454493055
Short name T344
Test name
Test status
Simulation time 87211747 ps
CPU time 1.2 seconds
Started Jul 26 05:44:00 PM PDT 24
Finished Jul 26 05:44:01 PM PDT 24
Peak memory 215536 kb
Host smart-e2b91ed7-e883-4e1e-8e6e-ce3b8db7d411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454493055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2454493055
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.614113155
Short name T122
Test name
Test status
Simulation time 30767144 ps
CPU time 1.24 seconds
Started Jul 26 05:43:58 PM PDT 24
Finished Jul 26 05:44:00 PM PDT 24
Peak memory 219456 kb
Host smart-a8d4bc58-9e7d-4874-b2b8-af940005c199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614113155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.614113155
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3022297584
Short name T37
Test name
Test status
Simulation time 80482726 ps
CPU time 1.76 seconds
Started Jul 26 05:43:48 PM PDT 24
Finished Jul 26 05:43:50 PM PDT 24
Peak memory 218532 kb
Host smart-1480a87c-9dd2-40ab-b494-7629cf0a4dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022297584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3022297584
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.585274765
Short name T173
Test name
Test status
Simulation time 44916072 ps
CPU time 1.25 seconds
Started Jul 26 05:43:55 PM PDT 24
Finished Jul 26 05:43:56 PM PDT 24
Peak memory 219392 kb
Host smart-0a46b73b-fc66-424a-87bd-28a70892e4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585274765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.585274765
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.549356783
Short name T146
Test name
Test status
Simulation time 50595898 ps
CPU time 1.16 seconds
Started Jul 26 05:43:50 PM PDT 24
Finished Jul 26 05:43:51 PM PDT 24
Peak memory 229496 kb
Host smart-3a8954ae-ad48-4952-bb0f-a76b8cc63214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549356783 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.549356783
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3366057040
Short name T797
Test name
Test status
Simulation time 36487263 ps
CPU time 1.32 seconds
Started Jul 26 05:43:49 PM PDT 24
Finished Jul 26 05:43:50 PM PDT 24
Peak memory 218104 kb
Host smart-10fa4ac2-289e-4b6c-9819-c54e061012d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366057040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3366057040
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.3975924435
Short name T140
Test name
Test status
Simulation time 247356408 ps
CPU time 1.24 seconds
Started Jul 26 05:44:00 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 219096 kb
Host smart-f5f2da01-5526-4482-a57f-5bd59245a55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975924435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.3975924435
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.2027553622
Short name T44
Test name
Test status
Simulation time 31931503 ps
CPU time 1.42 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:52 PM PDT 24
Peak memory 225484 kb
Host smart-db706c57-b818-4697-b8a9-12db92a2b927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027553622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2027553622
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3736573973
Short name T138
Test name
Test status
Simulation time 190328939 ps
CPU time 1.11 seconds
Started Jul 26 05:43:52 PM PDT 24
Finished Jul 26 05:43:53 PM PDT 24
Peak memory 217372 kb
Host smart-ef5d85c1-e831-454d-b3ea-d81ead885089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736573973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3736573973
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.448384715
Short name T286
Test name
Test status
Simulation time 30723001 ps
CPU time 1.35 seconds
Started Jul 26 05:43:53 PM PDT 24
Finished Jul 26 05:43:54 PM PDT 24
Peak memory 219256 kb
Host smart-28886185-ebb7-44a1-b4c9-295f54042713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448384715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.448384715
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3579256871
Short name T574
Test name
Test status
Simulation time 20042852 ps
CPU time 1.08 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 223884 kb
Host smart-fca63e02-1b9d-40b8-ab76-e22f2b24db22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579256871 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3579256871
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1412308324
Short name T684
Test name
Test status
Simulation time 72668178 ps
CPU time 1.85 seconds
Started Jul 26 05:43:45 PM PDT 24
Finished Jul 26 05:43:47 PM PDT 24
Peak memory 219528 kb
Host smart-c0a59905-05c7-409a-93bd-32908ce552b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412308324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1412308324
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.4023255592
Short name T893
Test name
Test status
Simulation time 83366900 ps
CPU time 1.14 seconds
Started Jul 26 05:43:56 PM PDT 24
Finished Jul 26 05:43:58 PM PDT 24
Peak memory 220340 kb
Host smart-ba32f036-5215-4aee-948b-afcdd7569cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023255592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.4023255592
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3901197028
Short name T503
Test name
Test status
Simulation time 18937925 ps
CPU time 1.06 seconds
Started Jul 26 05:43:58 PM PDT 24
Finished Jul 26 05:43:59 PM PDT 24
Peak memory 218504 kb
Host smart-ada4c529-9050-4ab3-b8dc-5bb010fe47f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901197028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3901197028
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3391678058
Short name T330
Test name
Test status
Simulation time 50887429 ps
CPU time 1.77 seconds
Started Jul 26 05:43:57 PM PDT 24
Finished Jul 26 05:43:58 PM PDT 24
Peak memory 218388 kb
Host smart-f526d145-a77e-42dc-97b2-003e15878a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391678058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3391678058
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1819898770
Short name T743
Test name
Test status
Simulation time 50549783 ps
CPU time 1.21 seconds
Started Jul 26 05:43:48 PM PDT 24
Finished Jul 26 05:43:49 PM PDT 24
Peak memory 218496 kb
Host smart-34b5a6ea-5b41-46ca-ac26-de6dbdd3e368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819898770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1819898770
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.1287704717
Short name T401
Test name
Test status
Simulation time 19799017 ps
CPU time 1.04 seconds
Started Jul 26 05:43:52 PM PDT 24
Finished Jul 26 05:43:53 PM PDT 24
Peak memory 218508 kb
Host smart-0a7ad9d7-1ff7-46d4-acae-e2fd929c4c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287704717 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1287704717
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3434295198
Short name T665
Test name
Test status
Simulation time 73852633 ps
CPU time 1.08 seconds
Started Jul 26 05:43:47 PM PDT 24
Finished Jul 26 05:43:48 PM PDT 24
Peak memory 217252 kb
Host smart-436db135-b66b-4aae-9580-2557b45bb142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434295198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3434295198
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.1812132132
Short name T449
Test name
Test status
Simulation time 30021724 ps
CPU time 1.3 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:03 PM PDT 24
Peak memory 215476 kb
Host smart-dcca2681-2255-490e-ad2b-e34baa47d79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812132132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.1812132132
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.3984975099
Short name T172
Test name
Test status
Simulation time 26162156 ps
CPU time 1.18 seconds
Started Jul 26 05:43:54 PM PDT 24
Finished Jul 26 05:43:55 PM PDT 24
Peak memory 220348 kb
Host smart-1631210a-96a9-4e92-bd65-dfa73196ac02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984975099 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3984975099
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2310864291
Short name T708
Test name
Test status
Simulation time 70792653 ps
CPU time 1.12 seconds
Started Jul 26 05:43:54 PM PDT 24
Finished Jul 26 05:43:55 PM PDT 24
Peak memory 219768 kb
Host smart-6d887178-4fde-4d21-9762-701a2558ff78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310864291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2310864291
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.4251520073
Short name T933
Test name
Test status
Simulation time 53264615 ps
CPU time 1.22 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 215552 kb
Host smart-e2d12040-e23e-4dac-b40e-48e24545cbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251520073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.4251520073
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.1505299223
Short name T111
Test name
Test status
Simulation time 19103006 ps
CPU time 1.05 seconds
Started Jul 26 05:43:55 PM PDT 24
Finished Jul 26 05:43:56 PM PDT 24
Peak memory 218620 kb
Host smart-54f45cd9-4bc1-4488-b5ea-15dd39cca5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505299223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1505299223
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2637607409
Short name T596
Test name
Test status
Simulation time 41364656 ps
CPU time 1.32 seconds
Started Jul 26 05:44:03 PM PDT 24
Finished Jul 26 05:44:05 PM PDT 24
Peak memory 217072 kb
Host smart-7051e14b-185f-4200-be2c-09fbe167ea2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637607409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2637607409
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2695921137
Short name T770
Test name
Test status
Simulation time 142576313 ps
CPU time 1.16 seconds
Started Jul 26 05:44:04 PM PDT 24
Finished Jul 26 05:44:05 PM PDT 24
Peak memory 219592 kb
Host smart-de3ca18f-0227-4df7-ad31-14ec48c5fea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695921137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2695921137
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2373616688
Short name T116
Test name
Test status
Simulation time 45614373 ps
CPU time 1.16 seconds
Started Jul 26 05:43:56 PM PDT 24
Finished Jul 26 05:43:58 PM PDT 24
Peak memory 229592 kb
Host smart-528c82d3-653f-4e26-8f60-08e6bc3ed9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373616688 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2373616688
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2953141736
Short name T972
Test name
Test status
Simulation time 77511938 ps
CPU time 1.13 seconds
Started Jul 26 05:44:05 PM PDT 24
Finished Jul 26 05:44:06 PM PDT 24
Peak memory 217084 kb
Host smart-5176982e-9901-493e-8d43-3207a84f6b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953141736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2953141736
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3716092516
Short name T450
Test name
Test status
Simulation time 71206521 ps
CPU time 1.15 seconds
Started Jul 26 05:42:42 PM PDT 24
Finished Jul 26 05:42:43 PM PDT 24
Peak memory 219700 kb
Host smart-0f3b3225-ad5a-45a4-b3e5-906731974b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716092516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3716092516
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.4075589806
Short name T741
Test name
Test status
Simulation time 25850228 ps
CPU time 0.88 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 05:42:42 PM PDT 24
Peak memory 206664 kb
Host smart-cea631fe-07b3-4aa7-8389-622b20fa778e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075589806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.4075589806
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3270334194
Short name T218
Test name
Test status
Simulation time 12864152 ps
CPU time 0.94 seconds
Started Jul 26 05:42:42 PM PDT 24
Finished Jul 26 05:42:43 PM PDT 24
Peak memory 215436 kb
Host smart-f18ad6cc-7777-4563-814d-d8527071cabc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270334194 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3270334194
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1370440834
Short name T164
Test name
Test status
Simulation time 69360728 ps
CPU time 1.33 seconds
Started Jul 26 05:42:40 PM PDT 24
Finished Jul 26 05:42:42 PM PDT 24
Peak memory 219516 kb
Host smart-ccbd58ee-b6db-4890-ab2c-baa5c5f8201b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370440834 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1370440834
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3707691684
Short name T127
Test name
Test status
Simulation time 33971895 ps
CPU time 1.49 seconds
Started Jul 26 05:42:38 PM PDT 24
Finished Jul 26 05:42:40 PM PDT 24
Peak memory 225396 kb
Host smart-22b07649-216e-4f14-b5ee-b48b71d5f789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707691684 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3707691684
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1152340885
Short name T892
Test name
Test status
Simulation time 44553032 ps
CPU time 1.5 seconds
Started Jul 26 05:42:34 PM PDT 24
Finished Jul 26 05:42:35 PM PDT 24
Peak memory 215312 kb
Host smart-60072d78-be57-477d-90fa-870f9aa215c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152340885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1152340885
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2193267483
Short name T58
Test name
Test status
Simulation time 27028487 ps
CPU time 0.97 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 05:42:42 PM PDT 24
Peak memory 215288 kb
Host smart-71a64069-887a-460b-8c33-d58f51b2ebb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193267483 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2193267483
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1405297367
Short name T73
Test name
Test status
Simulation time 51341840 ps
CPU time 0.92 seconds
Started Jul 26 05:42:35 PM PDT 24
Finished Jul 26 05:42:36 PM PDT 24
Peak memory 206936 kb
Host smart-cc6fc7b9-d7d0-4b7d-9bdc-59ae8f50e8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405297367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1405297367
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1023449834
Short name T868
Test name
Test status
Simulation time 17393337 ps
CPU time 1.06 seconds
Started Jul 26 05:42:41 PM PDT 24
Finished Jul 26 05:42:42 PM PDT 24
Peak memory 215108 kb
Host smart-907ad2fd-15b7-4af6-9b67-ffd3ff35c54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023449834 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1023449834
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2834679585
Short name T649
Test name
Test status
Simulation time 411509477 ps
CPU time 4.63 seconds
Started Jul 26 05:42:33 PM PDT 24
Finished Jul 26 05:42:38 PM PDT 24
Peak memory 217272 kb
Host smart-558ef60e-63c3-40eb-b0e7-cc424d75af4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834679585 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2834679585
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.497931342
Short name T323
Test name
Test status
Simulation time 48182567501 ps
CPU time 516.44 seconds
Started Jul 26 05:42:38 PM PDT 24
Finished Jul 26 05:51:15 PM PDT 24
Peak memory 217956 kb
Host smart-40c3e5df-814c-4131-8868-90c49f0e268e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497931342 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.497931342
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.4069367621
Short name T783
Test name
Test status
Simulation time 20356941 ps
CPU time 0.98 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:53 PM PDT 24
Peak memory 218264 kb
Host smart-a6c649b3-1e3b-4e68-9ba9-90718d194a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069367621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.4069367621
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2764332735
Short name T847
Test name
Test status
Simulation time 195091982 ps
CPU time 1.61 seconds
Started Jul 26 05:43:52 PM PDT 24
Finished Jul 26 05:43:54 PM PDT 24
Peak memory 217496 kb
Host smart-d2557d24-50c4-45c8-a9e9-f7a19ce46766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764332735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2764332735
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1531845735
Short name T157
Test name
Test status
Simulation time 39805377 ps
CPU time 1.14 seconds
Started Jul 26 05:44:14 PM PDT 24
Finished Jul 26 05:44:15 PM PDT 24
Peak memory 218464 kb
Host smart-8f93bd7d-89e7-47e9-a052-eeea6d437c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531845735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1531845735
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.1437646670
Short name T420
Test name
Test status
Simulation time 36188241 ps
CPU time 0.95 seconds
Started Jul 26 05:43:59 PM PDT 24
Finished Jul 26 05:44:01 PM PDT 24
Peak memory 223704 kb
Host smart-65f8aa64-008f-4f9c-a496-7e7050fcd4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437646670 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1437646670
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2455732231
Short name T659
Test name
Test status
Simulation time 34743670 ps
CPU time 1.15 seconds
Started Jul 26 05:43:51 PM PDT 24
Finished Jul 26 05:43:53 PM PDT 24
Peak memory 217272 kb
Host smart-aac460d4-6e11-42a6-a6e0-e864364d6f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455732231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2455732231
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.3113050075
Short name T917
Test name
Test status
Simulation time 37379872 ps
CPU time 1.13 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:03 PM PDT 24
Peak memory 218624 kb
Host smart-c7abf710-0a7c-40d6-9aa6-25322ca70aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113050075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.3113050075
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.554097602
Short name T43
Test name
Test status
Simulation time 18964461 ps
CPU time 1.16 seconds
Started Jul 26 05:43:50 PM PDT 24
Finished Jul 26 05:43:51 PM PDT 24
Peak memory 224108 kb
Host smart-9a73eb99-6663-420b-94ae-a95e5ec6cd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554097602 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.554097602
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2644978799
Short name T844
Test name
Test status
Simulation time 83185593 ps
CPU time 1.24 seconds
Started Jul 26 05:44:04 PM PDT 24
Finished Jul 26 05:44:05 PM PDT 24
Peak memory 217208 kb
Host smart-ea0890cc-5f17-4888-bf95-3f010507f2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644978799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2644978799
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2290842205
Short name T189
Test name
Test status
Simulation time 31568573 ps
CPU time 1.3 seconds
Started Jul 26 05:44:04 PM PDT 24
Finished Jul 26 05:44:06 PM PDT 24
Peak memory 215412 kb
Host smart-cfdc389b-0fb5-4620-afb7-2c04db0332c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290842205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2290842205
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3683764281
Short name T59
Test name
Test status
Simulation time 24790361 ps
CPU time 0.96 seconds
Started Jul 26 05:44:02 PM PDT 24
Finished Jul 26 05:44:04 PM PDT 24
Peak memory 219332 kb
Host smart-56deb510-9857-4d71-abc6-ed138c76f738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683764281 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3683764281
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3692498495
Short name T331
Test name
Test status
Simulation time 61405585 ps
CPU time 2.06 seconds
Started Jul 26 05:43:58 PM PDT 24
Finished Jul 26 05:44:00 PM PDT 24
Peak memory 219868 kb
Host smart-8eb9bf5e-b226-4608-b0bc-3d7e4773acbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692498495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3692498495
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.365243695
Short name T809
Test name
Test status
Simulation time 42209458 ps
CPU time 1.11 seconds
Started Jul 26 05:44:03 PM PDT 24
Finished Jul 26 05:44:04 PM PDT 24
Peak memory 219928 kb
Host smart-aac9a7ce-93e9-4d53-8d7c-f276ffa8fefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365243695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.365243695
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.335917304
Short name T147
Test name
Test status
Simulation time 37414293 ps
CPU time 1.16 seconds
Started Jul 26 05:44:02 PM PDT 24
Finished Jul 26 05:44:03 PM PDT 24
Peak memory 229600 kb
Host smart-d3299b88-28b9-4458-91ac-8af05588c095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335917304 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.335917304
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.288990593
Short name T808
Test name
Test status
Simulation time 66814950 ps
CPU time 1.39 seconds
Started Jul 26 05:44:01 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 217128 kb
Host smart-c928d330-7a0f-4dda-8878-9b52203754a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288990593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.288990593
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.458010957
Short name T792
Test name
Test status
Simulation time 28462172 ps
CPU time 1.24 seconds
Started Jul 26 05:43:55 PM PDT 24
Finished Jul 26 05:43:57 PM PDT 24
Peak memory 218384 kb
Host smart-c6eb184f-866f-496f-b926-59288e372b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458010957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.458010957
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.160373315
Short name T6
Test name
Test status
Simulation time 169839128 ps
CPU time 1.08 seconds
Started Jul 26 05:43:52 PM PDT 24
Finished Jul 26 05:43:53 PM PDT 24
Peak memory 223972 kb
Host smart-8d24b096-6af3-47e9-b662-f1166d1fffbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160373315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.160373315
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3139515587
Short name T557
Test name
Test status
Simulation time 54932859 ps
CPU time 1.71 seconds
Started Jul 26 05:43:59 PM PDT 24
Finished Jul 26 05:44:00 PM PDT 24
Peak memory 217480 kb
Host smart-53dc0a4e-2853-4714-b4da-d903c0abf170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139515587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3139515587
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1709495951
Short name T826
Test name
Test status
Simulation time 23984204 ps
CPU time 1.14 seconds
Started Jul 26 05:43:56 PM PDT 24
Finished Jul 26 05:43:57 PM PDT 24
Peak memory 218444 kb
Host smart-06b439fe-af73-45a4-8ad2-4da8c3b41590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709495951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1709495951
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3674085105
Short name T426
Test name
Test status
Simulation time 21681601 ps
CPU time 1.06 seconds
Started Jul 26 05:43:57 PM PDT 24
Finished Jul 26 05:43:58 PM PDT 24
Peak memory 223900 kb
Host smart-322ceca2-028e-49ed-a5bd-160fd1a9ac12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674085105 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3674085105
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2440432587
Short name T736
Test name
Test status
Simulation time 54450116 ps
CPU time 1.65 seconds
Started Jul 26 05:43:49 PM PDT 24
Finished Jul 26 05:43:51 PM PDT 24
Peak memory 218568 kb
Host smart-ebe3532f-0004-4f56-b71f-26b5cb28d1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440432587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2440432587
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2042567292
Short name T169
Test name
Test status
Simulation time 23781117 ps
CPU time 1.11 seconds
Started Jul 26 05:43:53 PM PDT 24
Finished Jul 26 05:43:54 PM PDT 24
Peak memory 220456 kb
Host smart-c4b89426-f78b-4e49-a8ec-06a25948f5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042567292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2042567292
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.2834034488
Short name T109
Test name
Test status
Simulation time 44663342 ps
CPU time 1.27 seconds
Started Jul 26 05:44:05 PM PDT 24
Finished Jul 26 05:44:06 PM PDT 24
Peak memory 219504 kb
Host smart-964c72e7-2e4f-4a3a-91cf-26be3081b2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834034488 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2834034488
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/98.edn_alert.4117028238
Short name T347
Test name
Test status
Simulation time 83564438 ps
CPU time 1.08 seconds
Started Jul 26 05:43:52 PM PDT 24
Finished Jul 26 05:43:53 PM PDT 24
Peak memory 218772 kb
Host smart-f30829a8-91e5-4731-baa8-933a3a154372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117028238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.4117028238
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1308583971
Short name T408
Test name
Test status
Simulation time 24293822 ps
CPU time 1.26 seconds
Started Jul 26 05:44:03 PM PDT 24
Finished Jul 26 05:44:05 PM PDT 24
Peak memory 223920 kb
Host smart-bb050b19-a5ae-4fda-b79d-58592dd20036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308583971 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1308583971
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.222628550
Short name T35
Test name
Test status
Simulation time 87773088 ps
CPU time 1.28 seconds
Started Jul 26 05:44:08 PM PDT 24
Finished Jul 26 05:44:10 PM PDT 24
Peak memory 217356 kb
Host smart-0725545e-163b-4079-b42e-2c79ef1095cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222628550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.222628550
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.1614884025
Short name T693
Test name
Test status
Simulation time 85686179 ps
CPU time 1.2 seconds
Started Jul 26 05:44:00 PM PDT 24
Finished Jul 26 05:44:02 PM PDT 24
Peak memory 220532 kb
Host smart-0b2609e8-3ef2-4662-abe1-3abc74a376a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614884025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1614884025
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.1904227526
Short name T479
Test name
Test status
Simulation time 89827483 ps
CPU time 1.27 seconds
Started Jul 26 05:43:58 PM PDT 24
Finished Jul 26 05:43:59 PM PDT 24
Peak memory 225412 kb
Host smart-6f32541a-8084-4002-9245-3cdd94fc5a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904227526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1904227526
Directory /workspace/99.edn_err/latest
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