Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

8039

1

T4

30

T5

170

T42

45

all_values[1]

8039

1

T4

30

T5

170

T42

45

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8232

1

T4

35

T5

170

T42

48

auto[1]

7846

1

T4

25

T5

170

T42

42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6327

1

T4

26

T5

128

T42

35

auto[1]

9751

1

T4

34

T5

212

T42

55

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9527

1

T4

38

T5

191

T42

54

auto[1]

6551

1

T4

22

T5

149

T42

36

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	0	12	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

1601

1

T4

11

T5

34

T42

9

all_values[0]

auto[0]

auto[0]

auto[1]

788

1

T4

3

T5

16

T42

5

all_values[0]

auto[0]

auto[1]

auto[0]

1551

1

T4

7

T5

32

T42

10

all_values[0]

auto[0]

auto[1]

auto[1]

801

1

T4

2

T5

16

T42

4

all_values[0]

auto[1]

auto[0]

auto[1]

1685

1

T4

2

T5

42

T42

11

all_values[0]

auto[1]

auto[1]

auto[1]

1613

1

T4

5

T5

30

T42

6

all_values[1]

auto[0]

auto[0]

auto[0]

1666

1

T4

5

T5

27

T42

11

all_values[1]

auto[0]

auto[0]

auto[1]

799

1

T4

4

T5

9

T42

3

all_values[1]

auto[0]

auto[1]

auto[0]

1509

1

T4

3

T5

35

T42

5

all_values[1]

auto[0]

auto[1]

auto[1]

812

1

T4

3

T5

22

T42

7

all_values[1]

auto[1]

auto[0]

auto[1]

1693

1

T4

10

T5

42

T42

9

all_values[1]

auto[1]

auto[1]

auto[1]

1560

1

T4

5

T5

35

T42

10

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal