Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.41 98.25 93.31 90.85 87.79 95.50 96.83 91.31


Total test records in report: 1125
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1019 /workspace/coverage/cover_reg_top/7.edn_intr_test.1515138845 Jul 27 05:36:53 PM PDT 24 Jul 27 05:36:54 PM PDT 24 13119069 ps
T1020 /workspace/coverage/cover_reg_top/4.edn_tl_errors.101151374 Jul 27 05:36:53 PM PDT 24 Jul 27 05:36:56 PM PDT 24 80977483 ps
T283 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1101843771 Jul 27 05:36:50 PM PDT 24 Jul 27 05:36:51 PM PDT 24 53194381 ps
T284 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1441679429 Jul 27 05:37:18 PM PDT 24 Jul 27 05:37:19 PM PDT 24 30307131 ps
T303 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3895178565 Jul 27 05:37:12 PM PDT 24 Jul 27 05:37:14 PM PDT 24 257152902 ps
T285 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1455260864 Jul 27 05:37:09 PM PDT 24 Jul 27 05:37:11 PM PDT 24 13503074 ps
T1021 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4129221326 Jul 27 05:36:53 PM PDT 24 Jul 27 05:36:56 PM PDT 24 166375554 ps
T1022 /workspace/coverage/cover_reg_top/8.edn_intr_test.4222979126 Jul 27 05:37:02 PM PDT 24 Jul 27 05:37:04 PM PDT 24 189305940 ps
T264 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3006637142 Jul 27 05:36:53 PM PDT 24 Jul 27 05:36:54 PM PDT 24 50521229 ps
T1023 /workspace/coverage/cover_reg_top/15.edn_intr_test.4245139491 Jul 27 05:37:12 PM PDT 24 Jul 27 05:37:13 PM PDT 24 61072198 ps
T1024 /workspace/coverage/cover_reg_top/18.edn_tl_errors.850372033 Jul 27 05:37:10 PM PDT 24 Jul 27 05:37:14 PM PDT 24 433815069 ps
T1025 /workspace/coverage/cover_reg_top/19.edn_tl_errors.445976172 Jul 27 05:37:11 PM PDT 24 Jul 27 05:37:15 PM PDT 24 197504885 ps
T265 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3596566116 Jul 27 05:37:08 PM PDT 24 Jul 27 05:37:09 PM PDT 24 41522853 ps
T1026 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1722965077 Jul 27 05:36:52 PM PDT 24 Jul 27 05:36:53 PM PDT 24 59998223 ps
T1027 /workspace/coverage/cover_reg_top/49.edn_intr_test.3075426803 Jul 27 05:37:21 PM PDT 24 Jul 27 05:37:22 PM PDT 24 140447418 ps
T1028 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.179770517 Jul 27 05:36:52 PM PDT 24 Jul 27 05:36:53 PM PDT 24 104151358 ps
T266 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2442876887 Jul 27 05:36:53 PM PDT 24 Jul 27 05:36:55 PM PDT 24 29523836 ps
T1029 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.629710637 Jul 27 05:36:51 PM PDT 24 Jul 27 05:36:54 PM PDT 24 94280390 ps
T1030 /workspace/coverage/cover_reg_top/40.edn_intr_test.324293196 Jul 27 05:37:19 PM PDT 24 Jul 27 05:37:20 PM PDT 24 17040727 ps
T267 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.766676593 Jul 27 05:36:43 PM PDT 24 Jul 27 05:36:44 PM PDT 24 30653126 ps
T1031 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3410138894 Jul 27 05:37:00 PM PDT 24 Jul 27 05:37:01 PM PDT 24 26581787 ps
T1032 /workspace/coverage/cover_reg_top/19.edn_intr_test.2337111924 Jul 27 05:37:12 PM PDT 24 Jul 27 05:37:13 PM PDT 24 28410800 ps
T1033 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.325069366 Jul 27 05:37:17 PM PDT 24 Jul 27 05:37:19 PM PDT 24 76738405 ps
T268 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3969715503 Jul 27 05:37:00 PM PDT 24 Jul 27 05:37:01 PM PDT 24 23836053 ps
T1034 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.169352928 Jul 27 05:37:10 PM PDT 24 Jul 27 05:37:11 PM PDT 24 31956899 ps
T1035 /workspace/coverage/cover_reg_top/8.edn_tl_errors.979111413 Jul 27 05:36:51 PM PDT 24 Jul 27 05:36:53 PM PDT 24 58058771 ps
T1036 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3163213634 Jul 27 05:36:51 PM PDT 24 Jul 27 05:36:58 PM PDT 24 255544066 ps
T1037 /workspace/coverage/cover_reg_top/10.edn_csr_rw.809682246 Jul 27 05:36:59 PM PDT 24 Jul 27 05:37:00 PM PDT 24 45710932 ps
T1038 /workspace/coverage/cover_reg_top/18.edn_csr_rw.434824924 Jul 27 05:37:18 PM PDT 24 Jul 27 05:37:19 PM PDT 24 96930226 ps
T1039 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2130555586 Jul 27 05:37:02 PM PDT 24 Jul 27 05:37:04 PM PDT 24 314187193 ps
T1040 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2483569978 Jul 27 05:37:00 PM PDT 24 Jul 27 05:37:02 PM PDT 24 277773832 ps
T1041 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3922855270 Jul 27 05:36:51 PM PDT 24 Jul 27 05:36:52 PM PDT 24 130695014 ps
T1042 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3970879546 Jul 27 05:36:52 PM PDT 24 Jul 27 05:36:53 PM PDT 24 19081452 ps
T1043 /workspace/coverage/cover_reg_top/22.edn_intr_test.637609248 Jul 27 05:37:15 PM PDT 24 Jul 27 05:37:16 PM PDT 24 13134589 ps
T1044 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2250217515 Jul 27 05:37:13 PM PDT 24 Jul 27 05:37:15 PM PDT 24 98707859 ps
T1045 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.4024222264 Jul 27 05:37:02 PM PDT 24 Jul 27 05:37:04 PM PDT 24 36023804 ps
T1046 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.98718199 Jul 27 05:37:03 PM PDT 24 Jul 27 05:37:05 PM PDT 24 60020481 ps
T269 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2568886787 Jul 27 05:37:14 PM PDT 24 Jul 27 05:37:16 PM PDT 24 37930752 ps
T270 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3696610016 Jul 27 05:37:01 PM PDT 24 Jul 27 05:37:02 PM PDT 24 22900487 ps
T1047 /workspace/coverage/cover_reg_top/34.edn_intr_test.3086779925 Jul 27 05:37:17 PM PDT 24 Jul 27 05:37:18 PM PDT 24 19846992 ps
T1048 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.742375338 Jul 27 05:37:15 PM PDT 24 Jul 27 05:37:17 PM PDT 24 42798028 ps
T1049 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2215585079 Jul 27 05:37:09 PM PDT 24 Jul 27 05:37:13 PM PDT 24 192560618 ps
T1050 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3869363235 Jul 27 05:36:52 PM PDT 24 Jul 27 05:36:55 PM PDT 24 229628487 ps
T1051 /workspace/coverage/cover_reg_top/41.edn_intr_test.28762892 Jul 27 05:37:21 PM PDT 24 Jul 27 05:37:22 PM PDT 24 16605606 ps
T1052 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1385300974 Jul 27 05:36:51 PM PDT 24 Jul 27 05:36:53 PM PDT 24 70549065 ps
T1053 /workspace/coverage/cover_reg_top/32.edn_intr_test.4233829811 Jul 27 05:37:18 PM PDT 24 Jul 27 05:37:19 PM PDT 24 51292261 ps
T1054 /workspace/coverage/cover_reg_top/6.edn_intr_test.118308178 Jul 27 05:36:55 PM PDT 24 Jul 27 05:36:56 PM PDT 24 11621315 ps
T1055 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3853531194 Jul 27 05:37:10 PM PDT 24 Jul 27 05:37:11 PM PDT 24 55066759 ps
T1056 /workspace/coverage/cover_reg_top/18.edn_intr_test.2543125383 Jul 27 05:37:17 PM PDT 24 Jul 27 05:37:18 PM PDT 24 44513546 ps
T1057 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2875069195 Jul 27 05:37:15 PM PDT 24 Jul 27 05:37:17 PM PDT 24 50100130 ps
T1058 /workspace/coverage/cover_reg_top/24.edn_intr_test.4049702422 Jul 27 05:37:13 PM PDT 24 Jul 27 05:37:14 PM PDT 24 37836307 ps
T1059 /workspace/coverage/cover_reg_top/21.edn_intr_test.2105496817 Jul 27 05:37:12 PM PDT 24 Jul 27 05:37:13 PM PDT 24 82311962 ps
T1060 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2921339871 Jul 27 05:36:55 PM PDT 24 Jul 27 05:36:56 PM PDT 24 18074453 ps
T1061 /workspace/coverage/cover_reg_top/46.edn_intr_test.150690440 Jul 27 05:37:18 PM PDT 24 Jul 27 05:37:19 PM PDT 24 26252934 ps
T1062 /workspace/coverage/cover_reg_top/4.edn_intr_test.376540392 Jul 27 05:36:53 PM PDT 24 Jul 27 05:36:54 PM PDT 24 33356839 ps
T1063 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2627751226 Jul 27 05:37:01 PM PDT 24 Jul 27 05:37:04 PM PDT 24 334666777 ps
T1064 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1331143141 Jul 27 05:37:08 PM PDT 24 Jul 27 05:37:10 PM PDT 24 16292288 ps
T1065 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4115381516 Jul 27 05:36:53 PM PDT 24 Jul 27 05:36:57 PM PDT 24 385174589 ps
T1066 /workspace/coverage/cover_reg_top/38.edn_intr_test.2480432580 Jul 27 05:37:18 PM PDT 24 Jul 27 05:37:19 PM PDT 24 12305426 ps
T1067 /workspace/coverage/cover_reg_top/25.edn_intr_test.1943750089 Jul 27 05:37:18 PM PDT 24 Jul 27 05:37:19 PM PDT 24 30286111 ps
T1068 /workspace/coverage/cover_reg_top/5.edn_intr_test.4271234420 Jul 27 05:36:53 PM PDT 24 Jul 27 05:36:54 PM PDT 24 17585577 ps
T1069 /workspace/coverage/cover_reg_top/33.edn_intr_test.3393167140 Jul 27 05:37:18 PM PDT 24 Jul 27 05:37:20 PM PDT 24 39868805 ps
T1070 /workspace/coverage/cover_reg_top/44.edn_intr_test.417926049 Jul 27 05:37:20 PM PDT 24 Jul 27 05:37:21 PM PDT 24 23339731 ps
T1071 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2645702479 Jul 27 05:36:59 PM PDT 24 Jul 27 05:37:01 PM PDT 24 49409462 ps
T1072 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3497338289 Jul 27 05:36:51 PM PDT 24 Jul 27 05:36:52 PM PDT 24 74633052 ps
T1073 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3977925185 Jul 27 05:37:16 PM PDT 24 Jul 27 05:37:19 PM PDT 24 97026475 ps
T1074 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3675650566 Jul 27 05:36:55 PM PDT 24 Jul 27 05:36:56 PM PDT 24 65415323 ps
T1075 /workspace/coverage/cover_reg_top/36.edn_intr_test.3540828517 Jul 27 05:37:21 PM PDT 24 Jul 27 05:37:22 PM PDT 24 21694849 ps
T1076 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2242799143 Jul 27 05:37:11 PM PDT 24 Jul 27 05:37:13 PM PDT 24 36103940 ps
T1077 /workspace/coverage/cover_reg_top/17.edn_intr_test.218935860 Jul 27 05:37:11 PM PDT 24 Jul 27 05:37:12 PM PDT 24 11526947 ps
T1078 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.457482327 Jul 27 05:37:13 PM PDT 24 Jul 27 05:37:15 PM PDT 24 22955247 ps
T1079 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1902858462 Jul 27 05:37:03 PM PDT 24 Jul 27 05:37:05 PM PDT 24 40907501 ps
T1080 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3496491757 Jul 27 05:37:02 PM PDT 24 Jul 27 05:37:05 PM PDT 24 114886896 ps
T1081 /workspace/coverage/cover_reg_top/5.edn_tl_errors.318072650 Jul 27 05:36:50 PM PDT 24 Jul 27 05:36:54 PM PDT 24 168838380 ps
T271 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3652005400 Jul 27 05:36:51 PM PDT 24 Jul 27 05:36:52 PM PDT 24 19038804 ps
T1082 /workspace/coverage/cover_reg_top/28.edn_intr_test.2846189525 Jul 27 05:37:20 PM PDT 24 Jul 27 05:37:21 PM PDT 24 52714441 ps
T1083 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3614621844 Jul 27 05:36:56 PM PDT 24 Jul 27 05:36:57 PM PDT 24 21762882 ps
T1084 /workspace/coverage/cover_reg_top/20.edn_intr_test.1917989941 Jul 27 05:37:11 PM PDT 24 Jul 27 05:37:12 PM PDT 24 15124598 ps
T273 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2822355641 Jul 27 05:37:03 PM PDT 24 Jul 27 05:37:05 PM PDT 24 11779708 ps
T1085 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1329760576 Jul 27 05:37:17 PM PDT 24 Jul 27 05:37:18 PM PDT 24 18742760 ps
T1086 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.91092260 Jul 27 05:37:02 PM PDT 24 Jul 27 05:37:04 PM PDT 24 62155641 ps
T1087 /workspace/coverage/cover_reg_top/26.edn_intr_test.779047662 Jul 27 05:37:12 PM PDT 24 Jul 27 05:37:13 PM PDT 24 11847649 ps
T1088 /workspace/coverage/cover_reg_top/14.edn_csr_rw.954938115 Jul 27 05:37:18 PM PDT 24 Jul 27 05:37:19 PM PDT 24 42883690 ps
T1089 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1166538888 Jul 27 05:36:51 PM PDT 24 Jul 27 05:36:52 PM PDT 24 27652605 ps
T1090 /workspace/coverage/cover_reg_top/15.edn_csr_rw.129627927 Jul 27 05:37:09 PM PDT 24 Jul 27 05:37:10 PM PDT 24 17855369 ps
T1091 /workspace/coverage/cover_reg_top/39.edn_intr_test.4097308151 Jul 27 05:37:25 PM PDT 24 Jul 27 05:37:26 PM PDT 24 19181554 ps
T1092 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1624850504 Jul 27 05:36:50 PM PDT 24 Jul 27 05:36:51 PM PDT 24 93443080 ps
T1093 /workspace/coverage/cover_reg_top/30.edn_intr_test.1523195676 Jul 27 05:37:19 PM PDT 24 Jul 27 05:37:20 PM PDT 24 95680974 ps
T1094 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1584952453 Jul 27 05:37:13 PM PDT 24 Jul 27 05:37:14 PM PDT 24 38117429 ps
T274 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4038147892 Jul 27 05:36:51 PM PDT 24 Jul 27 05:36:52 PM PDT 24 44197883 ps
T275 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1206250900 Jul 27 05:37:02 PM PDT 24 Jul 27 05:37:03 PM PDT 24 14785668 ps
T1095 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2197026178 Jul 27 05:37:04 PM PDT 24 Jul 27 05:37:06 PM PDT 24 54812197 ps
T1096 /workspace/coverage/cover_reg_top/23.edn_intr_test.1422290359 Jul 27 05:37:19 PM PDT 24 Jul 27 05:37:20 PM PDT 24 52607659 ps
T1097 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3693786913 Jul 27 05:37:08 PM PDT 24 Jul 27 05:37:11 PM PDT 24 105838948 ps
T1098 /workspace/coverage/cover_reg_top/14.edn_intr_test.4284934440 Jul 27 05:37:16 PM PDT 24 Jul 27 05:37:17 PM PDT 24 172674475 ps
T1099 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3021033811 Jul 27 05:37:08 PM PDT 24 Jul 27 05:37:09 PM PDT 24 32895551 ps
T1100 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.946661194 Jul 27 05:37:03 PM PDT 24 Jul 27 05:37:05 PM PDT 24 67320567 ps
T1101 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.4155170341 Jul 27 05:37:09 PM PDT 24 Jul 27 05:37:11 PM PDT 24 184314212 ps
T276 /workspace/coverage/cover_reg_top/16.edn_csr_rw.142103161 Jul 27 05:37:13 PM PDT 24 Jul 27 05:37:14 PM PDT 24 17778950 ps
T1102 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.453338708 Jul 27 05:37:10 PM PDT 24 Jul 27 05:37:12 PM PDT 24 45995119 ps
T1103 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1529355182 Jul 27 05:37:02 PM PDT 24 Jul 27 05:37:04 PM PDT 24 22959419 ps
T1104 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3671116695 Jul 27 05:37:08 PM PDT 24 Jul 27 05:37:10 PM PDT 24 122747110 ps
T1105 /workspace/coverage/cover_reg_top/0.edn_intr_test.3847352615 Jul 27 05:36:53 PM PDT 24 Jul 27 05:36:54 PM PDT 24 20558648 ps
T1106 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1197165177 Jul 27 05:37:08 PM PDT 24 Jul 27 05:37:10 PM PDT 24 45008139 ps
T1107 /workspace/coverage/cover_reg_top/37.edn_intr_test.2896795507 Jul 27 05:37:21 PM PDT 24 Jul 27 05:37:22 PM PDT 24 51304440 ps
T1108 /workspace/coverage/cover_reg_top/35.edn_intr_test.2103118244 Jul 27 05:37:18 PM PDT 24 Jul 27 05:37:20 PM PDT 24 77443914 ps
T1109 /workspace/coverage/cover_reg_top/10.edn_tl_errors.894234096 Jul 27 05:37:02 PM PDT 24 Jul 27 05:37:05 PM PDT 24 74927561 ps
T1110 /workspace/coverage/cover_reg_top/43.edn_intr_test.3098349924 Jul 27 05:37:22 PM PDT 24 Jul 27 05:37:23 PM PDT 24 15088856 ps
T1111 /workspace/coverage/cover_reg_top/45.edn_intr_test.2775484124 Jul 27 05:37:18 PM PDT 24 Jul 27 05:37:19 PM PDT 24 42931749 ps
T1112 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4147603051 Jul 27 05:37:14 PM PDT 24 Jul 27 05:37:16 PM PDT 24 70960130 ps
T1113 /workspace/coverage/cover_reg_top/9.edn_intr_test.4278565596 Jul 27 05:37:02 PM PDT 24 Jul 27 05:37:03 PM PDT 24 11153624 ps
T1114 /workspace/coverage/cover_reg_top/47.edn_intr_test.2047662226 Jul 27 05:37:24 PM PDT 24 Jul 27 05:37:25 PM PDT 24 17608300 ps
T1115 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1458901359 Jul 27 05:36:53 PM PDT 24 Jul 27 05:36:53 PM PDT 24 45381056 ps
T1116 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3048832796 Jul 27 05:37:12 PM PDT 24 Jul 27 05:37:15 PM PDT 24 68616510 ps
T1117 /workspace/coverage/cover_reg_top/42.edn_intr_test.1398674825 Jul 27 05:37:17 PM PDT 24 Jul 27 05:37:18 PM PDT 24 55151030 ps
T1118 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1034243286 Jul 27 05:36:52 PM PDT 24 Jul 27 05:36:53 PM PDT 24 23839737 ps
T1119 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1122899195 Jul 27 05:36:56 PM PDT 24 Jul 27 05:37:00 PM PDT 24 480279270 ps
T277 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1592911417 Jul 27 05:37:08 PM PDT 24 Jul 27 05:37:09 PM PDT 24 24879415 ps
T1120 /workspace/coverage/cover_reg_top/2.edn_intr_test.741047762 Jul 27 05:36:53 PM PDT 24 Jul 27 05:36:54 PM PDT 24 16959831 ps
T1121 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3355526786 Jul 27 05:37:02 PM PDT 24 Jul 27 05:37:03 PM PDT 24 51468686 ps
T1122 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1052426968 Jul 27 05:36:49 PM PDT 24 Jul 27 05:36:51 PM PDT 24 60066223 ps
T1123 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.571093958 Jul 27 05:36:53 PM PDT 24 Jul 27 05:36:54 PM PDT 24 14948586 ps
T1124 /workspace/coverage/cover_reg_top/13.edn_tl_errors.423120827 Jul 27 05:37:02 PM PDT 24 Jul 27 05:37:04 PM PDT 24 447527437 ps
T1125 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4226470786 Jul 27 05:36:53 PM PDT 24 Jul 27 05:36:55 PM PDT 24 59365011 ps
T300 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3606421884 Jul 27 05:37:12 PM PDT 24 Jul 27 05:37:14 PM PDT 24 184899120 ps

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2731718133
Short name T5
Test name
Test status
Simulation time 418129212837 ps
CPU time 2118.29 seconds
Started Jul 27 05:55:58 PM PDT 24
Finished Jul 27 06:31:17 PM PDT 24
Peak memory 229952 kb
Host smart-f84cddb6-bdc1-48df-b6de-f1961667eda3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731718133 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2731718133
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.edn_genbits.867548985
Short name T20
Test name
Test status
Simulation time 207685270 ps
CPU time 2.85 seconds
Started Jul 27 05:57:12 PM PDT 24
Finished Jul 27 05:57:15 PM PDT 24
Peak memory 218876 kb
Host smart-7db8f9ab-4b55-463d-95e0-9da9a5a4b615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867548985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.867548985
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.2014425321
Short name T26
Test name
Test status
Simulation time 30898306 ps
CPU time 1.33 seconds
Started Jul 27 05:57:47 PM PDT 24
Finished Jul 27 05:57:48 PM PDT 24
Peak memory 218432 kb
Host smart-e4bfe5f0-8f66-46ba-b0a3-47b020ff7583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014425321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.2014425321
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/12.edn_err.3953793172
Short name T6
Test name
Test status
Simulation time 24469876 ps
CPU time 0.93 seconds
Started Jul 27 05:55:59 PM PDT 24
Finished Jul 27 05:56:00 PM PDT 24
Peak memory 218336 kb
Host smart-6742e1e5-e461-48d6-b66a-e4caff164edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953793172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3953793172
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/144.edn_alert.3032762887
Short name T19
Test name
Test status
Simulation time 41762596 ps
CPU time 1.11 seconds
Started Jul 27 05:57:30 PM PDT 24
Finished Jul 27 05:57:31 PM PDT 24
Peak memory 219620 kb
Host smart-b76995fe-83b8-448e-873f-8aed7a8ab85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032762887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.3032762887
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/25.edn_err.2901026715
Short name T16
Test name
Test status
Simulation time 23751489 ps
CPU time 1.03 seconds
Started Jul 27 05:56:24 PM PDT 24
Finished Jul 27 05:56:25 PM PDT 24
Peak memory 223864 kb
Host smart-67f146c3-455e-4c34-bb68-5e88285a3fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901026715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2901026715
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/0.edn_disable.1104772063
Short name T50
Test name
Test status
Simulation time 13771039 ps
CPU time 0.93 seconds
Started Jul 27 05:55:33 PM PDT 24
Finished Jul 27 05:55:35 PM PDT 24
Peak memory 216260 kb
Host smart-e6dc56ac-c818-4e7d-89a6-d53d688a28ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104772063 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1104772063
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.4258990599
Short name T30
Test name
Test status
Simulation time 49101620628 ps
CPU time 537.06 seconds
Started Jul 27 05:56:15 PM PDT 24
Finished Jul 27 06:05:13 PM PDT 24
Peak memory 223720 kb
Host smart-afdfd99d-fa25-4990-a26e-19746a387055
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258990599 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.4258990599
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.edn_alert.2639961612
Short name T70
Test name
Test status
Simulation time 36605747 ps
CPU time 1.14 seconds
Started Jul 27 05:57:16 PM PDT 24
Finished Jul 27 05:57:17 PM PDT 24
Peak memory 219128 kb
Host smart-214e32fa-2d87-43d1-a265-e022a7301afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639961612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.2639961612
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.164303344
Short name T99
Test name
Test status
Simulation time 55939677 ps
CPU time 1.14 seconds
Started Jul 27 05:56:43 PM PDT 24
Finished Jul 27 05:56:44 PM PDT 24
Peak memory 216692 kb
Host smart-fc1b4797-9299-4b94-be83-c4ecc6bab3b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164303344 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di
sable_auto_req_mode.164303344
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_intr.2842955590
Short name T76
Test name
Test status
Simulation time 60464293 ps
CPU time 0.8 seconds
Started Jul 27 05:56:58 PM PDT 24
Finished Jul 27 05:56:59 PM PDT 24
Peak memory 215628 kb
Host smart-c5b758f4-7c63-424b-8036-b216f7b944e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842955590 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2842955590
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/191.edn_alert.986988652
Short name T37
Test name
Test status
Simulation time 80502130 ps
CPU time 1.13 seconds
Started Jul 27 05:57:45 PM PDT 24
Finished Jul 27 05:57:47 PM PDT 24
Peak memory 219728 kb
Host smart-a27c8a27-56f9-465b-810b-ab67b9fa3473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986988652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.986988652
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/2.edn_regwen.3547500303
Short name T74
Test name
Test status
Simulation time 33840193 ps
CPU time 0.87 seconds
Started Jul 27 05:55:37 PM PDT 24
Finished Jul 27 05:55:38 PM PDT 24
Peak memory 206968 kb
Host smart-29da30c7-cd74-4494-8027-bd79b898391e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547500303 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3547500303
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.828611254
Short name T301
Test name
Test status
Simulation time 161855290 ps
CPU time 2.44 seconds
Started Jul 27 05:36:54 PM PDT 24
Finished Jul 27 05:36:56 PM PDT 24
Peak memory 206656 kb
Host smart-6a915256-e4c8-451a-aed9-add0b0db7042
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828611254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.828611254
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.4151710465
Short name T10
Test name
Test status
Simulation time 92237340 ps
CPU time 1.11 seconds
Started Jul 27 05:55:58 PM PDT 24
Finished Jul 27 05:55:59 PM PDT 24
Peak memory 218452 kb
Host smart-9c2976f1-fa43-46ed-ac14-ac8dc77bc3c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151710465 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.4151710465
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/71.edn_err.3224598185
Short name T116
Test name
Test status
Simulation time 48246033 ps
CPU time 0.89 seconds
Started Jul 27 05:57:09 PM PDT 24
Finished Jul 27 05:57:10 PM PDT 24
Peak memory 218192 kb
Host smart-3e014206-417b-452b-97b9-86f5d781353d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224598185 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3224598185
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3738989843
Short name T263
Test name
Test status
Simulation time 16500738 ps
CPU time 0.98 seconds
Started Jul 27 05:36:57 PM PDT 24
Finished Jul 27 05:36:58 PM PDT 24
Peak memory 206404 kb
Host smart-bc5e3c1d-48f4-428a-b5de-cbaa3fd16b5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738989843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3738989843
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/default/43.edn_disable.852031872
Short name T64
Test name
Test status
Simulation time 23042791 ps
CPU time 0.92 seconds
Started Jul 27 05:56:57 PM PDT 24
Finished Jul 27 05:56:58 PM PDT 24
Peak memory 216076 kb
Host smart-e52bb31c-06c3-4012-bf05-1d24c9b05228
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852031872 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.852031872
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/99.edn_alert.1956294717
Short name T187
Test name
Test status
Simulation time 36103489 ps
CPU time 1.02 seconds
Started Jul 27 05:57:30 PM PDT 24
Finished Jul 27 05:57:31 PM PDT 24
Peak memory 218888 kb
Host smart-001e1fda-5851-4d54-a6c2-9d137a77e587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956294717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1956294717
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/75.edn_genbits.906196194
Short name T15
Test name
Test status
Simulation time 42416634 ps
CPU time 1.55 seconds
Started Jul 27 05:57:19 PM PDT 24
Finished Jul 27 05:57:20 PM PDT 24
Peak memory 219884 kb
Host smart-fe877fea-f962-4c6c-b7e2-15c6b0356f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906196194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.906196194
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3403951480
Short name T114
Test name
Test status
Simulation time 228332172 ps
CPU time 1.14 seconds
Started Jul 27 05:55:34 PM PDT 24
Finished Jul 27 05:55:36 PM PDT 24
Peak memory 216752 kb
Host smart-84547894-178a-4f6f-87e0-b148d91cc918
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403951480 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3403951480
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable.2312861308
Short name T123
Test name
Test status
Simulation time 34129483 ps
CPU time 0.88 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 216048 kb
Host smart-dbcae90e-60b4-4f74-9ad5-42d3c964ef60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312861308 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2312861308
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable.957745138
Short name T92
Test name
Test status
Simulation time 39513656 ps
CPU time 0.84 seconds
Started Jul 27 05:56:25 PM PDT 24
Finished Jul 27 05:56:26 PM PDT 24
Peak memory 216020 kb
Host smart-213957e9-a862-4c7c-b349-5d13b2da7acd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957745138 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.957745138
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable.4163934267
Short name T866
Test name
Test status
Simulation time 21996771 ps
CPU time 0.91 seconds
Started Jul 27 05:55:48 PM PDT 24
Finished Jul 27 05:55:48 PM PDT 24
Peak memory 215236 kb
Host smart-65168de3-ecd0-402d-8cfa-2e366f0a9e6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163934267 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.4163934267
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/40.edn_intr.2028285217
Short name T36
Test name
Test status
Simulation time 20545917 ps
CPU time 1.05 seconds
Started Jul 27 05:56:50 PM PDT 24
Finished Jul 27 05:56:51 PM PDT 24
Peak memory 215672 kb
Host smart-5f9e6a13-4048-4bb0-809f-241cf4334fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028285217 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2028285217
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/141.edn_alert.1528055667
Short name T148
Test name
Test status
Simulation time 127910952 ps
CPU time 1.34 seconds
Started Jul 27 05:57:33 PM PDT 24
Finished Jul 27 05:57:35 PM PDT 24
Peak memory 219040 kb
Host smart-c1cd4c52-b842-4345-bc69-6fb2b97352d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528055667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1528055667
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/68.edn_alert.3533127081
Short name T141
Test name
Test status
Simulation time 92754376 ps
CPU time 1.31 seconds
Started Jul 27 05:57:03 PM PDT 24
Finished Jul 27 05:57:05 PM PDT 24
Peak memory 218620 kb
Host smart-53671a16-4d5b-4959-ac23-2a9ca6f6cb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533127081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.3533127081
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/98.edn_alert.2455875104
Short name T71
Test name
Test status
Simulation time 29070456 ps
CPU time 1.23 seconds
Started Jul 27 05:57:24 PM PDT 24
Finished Jul 27 05:57:26 PM PDT 24
Peak memory 215524 kb
Host smart-e6a0c35e-7436-47fd-9b68-10c98962aa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455875104 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2455875104
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/288.edn_genbits.1408046513
Short name T314
Test name
Test status
Simulation time 37176606 ps
CPU time 1.54 seconds
Started Jul 27 05:58:13 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 218332 kb
Host smart-15901c20-5d31-4d71-8341-3d3f9e1252d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408046513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1408046513
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_alert.3549802326
Short name T157
Test name
Test status
Simulation time 135273018 ps
CPU time 1.21 seconds
Started Jul 27 05:56:45 PM PDT 24
Finished Jul 27 05:56:47 PM PDT 24
Peak memory 218476 kb
Host smart-2e59b8eb-24a7-467d-b27c-55c2465f13cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549802326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3549802326
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/181.edn_alert.3457842854
Short name T40
Test name
Test status
Simulation time 27017624 ps
CPU time 1.23 seconds
Started Jul 27 05:57:48 PM PDT 24
Finished Jul 27 05:57:49 PM PDT 24
Peak memory 220648 kb
Host smart-5b53eb21-ec1a-46bd-8fc4-d09f881f8baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457842854 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.3457842854
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert.63312082
Short name T204
Test name
Test status
Simulation time 41652684 ps
CPU time 1.11 seconds
Started Jul 27 05:55:28 PM PDT 24
Finished Jul 27 05:55:29 PM PDT 24
Peak memory 219896 kb
Host smart-8579b9ab-bd56-45c2-85c9-228447662f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63312082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.63312082
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/104.edn_alert.3094225364
Short name T940
Test name
Test status
Simulation time 50929669 ps
CPU time 1.2 seconds
Started Jul 27 05:57:26 PM PDT 24
Finished Jul 27 05:57:27 PM PDT 24
Peak memory 218400 kb
Host smart-dcc3020d-d69a-42d8-8d11-95d513fa67f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094225364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.3094225364
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/109.edn_alert.380343892
Short name T195
Test name
Test status
Simulation time 71017599 ps
CPU time 1.09 seconds
Started Jul 27 05:57:31 PM PDT 24
Finished Jul 27 05:57:32 PM PDT 24
Peak memory 220980 kb
Host smart-5350ca0d-1dfd-4e9b-b2d5-f9ab1680f2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380343892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.380343892
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/147.edn_alert.902711599
Short name T201
Test name
Test status
Simulation time 30260252 ps
CPU time 1.26 seconds
Started Jul 27 05:57:36 PM PDT 24
Finished Jul 27 05:57:37 PM PDT 24
Peak memory 215564 kb
Host smart-ee02de64-cc03-4424-9f8a-b646f105109b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902711599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.902711599
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/188.edn_alert.3276813929
Short name T760
Test name
Test status
Simulation time 26444504 ps
CPU time 1.24 seconds
Started Jul 27 05:57:57 PM PDT 24
Finished Jul 27 05:57:59 PM PDT 24
Peak memory 219596 kb
Host smart-2d2fa7b5-1af3-48f5-a406-578736b802c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276813929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.3276813929
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.4144621400
Short name T120
Test name
Test status
Simulation time 40967378497 ps
CPU time 1088.34 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 06:14:19 PM PDT 24
Peak memory 221176 kb
Host smart-454ed53b-e09f-4052-8371-8f0bd6c5f898
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144621400 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.4144621400
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.edn_genbits.1624848999
Short name T330
Test name
Test status
Simulation time 49639203 ps
CPU time 1.48 seconds
Started Jul 27 05:56:29 PM PDT 24
Finished Jul 27 05:56:30 PM PDT 24
Peak memory 218684 kb
Host smart-49ca2519-a0d4-455d-9f40-294731b9ab22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624848999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1624848999
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3167558307
Short name T154
Test name
Test status
Simulation time 212009278 ps
CPU time 1.24 seconds
Started Jul 27 05:55:58 PM PDT 24
Finished Jul 27 05:55:59 PM PDT 24
Peak memory 216820 kb
Host smart-d3e382d5-4167-49b8-b844-ef0a60d13ae7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167558307 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3167558307
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2314202995
Short name T433
Test name
Test status
Simulation time 72838026 ps
CPU time 1.18 seconds
Started Jul 27 05:55:58 PM PDT 24
Finished Jul 27 05:56:00 PM PDT 24
Peak memory 225560 kb
Host smart-b2088aec-a4ff-4b6a-a5a1-a79cbf057b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314202995 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2314202995
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/106.edn_alert.2310561575
Short name T163
Test name
Test status
Simulation time 26491398 ps
CPU time 1.27 seconds
Started Jul 27 05:57:25 PM PDT 24
Finished Jul 27 05:57:27 PM PDT 24
Peak memory 219520 kb
Host smart-35602335-6b2f-43ed-8e1b-af403010f2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310561575 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2310561575
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/123.edn_alert.3901722592
Short name T172
Test name
Test status
Simulation time 23305083 ps
CPU time 1.23 seconds
Started Jul 27 05:57:31 PM PDT 24
Finished Jul 27 05:57:33 PM PDT 24
Peak memory 218592 kb
Host smart-0fa38067-25f3-451b-8894-faed25044e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901722592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.3901722592
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2218101085
Short name T179
Test name
Test status
Simulation time 65329614 ps
CPU time 1.26 seconds
Started Jul 27 05:56:04 PM PDT 24
Finished Jul 27 05:56:06 PM PDT 24
Peak memory 216632 kb
Host smart-fbf22b03-9b8b-436c-a2a8-09f1ece2547a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218101085 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2218101085
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2320371650
Short name T213
Test name
Test status
Simulation time 19384826 ps
CPU time 1.02 seconds
Started Jul 27 05:56:05 PM PDT 24
Finished Jul 27 05:56:06 PM PDT 24
Peak memory 218360 kb
Host smart-c7602478-850c-44c3-bc30-61f43a28dcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320371650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2320371650
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/2.edn_disable.45557528
Short name T93
Test name
Test status
Simulation time 12416958 ps
CPU time 0.92 seconds
Started Jul 27 05:55:38 PM PDT 24
Finished Jul 27 05:55:39 PM PDT 24
Peak memory 215296 kb
Host smart-f97866fd-f475-4b34-b1a3-a196d56ba196
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45557528 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.45557528
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable.838686154
Short name T898
Test name
Test status
Simulation time 106615499 ps
CPU time 0.81 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 216088 kb
Host smart-8bf834a6-75ce-4230-86cc-a7934841ad1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838686154 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.838686154
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.2922100581
Short name T216
Test name
Test status
Simulation time 39607991 ps
CPU time 0.88 seconds
Started Jul 27 05:56:28 PM PDT 24
Finished Jul 27 05:56:29 PM PDT 24
Peak memory 219232 kb
Host smart-3a09bc20-8ac8-4ba5-bb5a-a405b2605835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922100581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2922100581
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/111.edn_genbits.798380940
Short name T24
Test name
Test status
Simulation time 63422416 ps
CPU time 2.33 seconds
Started Jul 27 05:57:33 PM PDT 24
Finished Jul 27 05:57:35 PM PDT 24
Peak memory 220004 kb
Host smart-57426bbf-1f34-4489-b1b2-e57b99cd84a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798380940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.798380940
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.2256576915
Short name T384
Test name
Test status
Simulation time 89879540 ps
CPU time 0.9 seconds
Started Jul 27 05:56:04 PM PDT 24
Finished Jul 27 05:56:05 PM PDT 24
Peak memory 214792 kb
Host smart-8d52d6db-99f5-486f-8980-e0237cf6309c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256576915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2256576915
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/184.edn_genbits.3131579092
Short name T311
Test name
Test status
Simulation time 74025423 ps
CPU time 1.29 seconds
Started Jul 27 05:57:51 PM PDT 24
Finished Jul 27 05:57:52 PM PDT 24
Peak memory 220060 kb
Host smart-26a15a12-4221-45ee-9669-390607397e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131579092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3131579092
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1002515403
Short name T135
Test name
Test status
Simulation time 330044223298 ps
CPU time 1270.87 seconds
Started Jul 27 05:56:08 PM PDT 24
Finished Jul 27 06:17:19 PM PDT 24
Peak memory 224796 kb
Host smart-4fbdec40-d72e-4c26-9175-39c5387c1afc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002515403 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1002515403
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.1079486091
Short name T89
Test name
Test status
Simulation time 160121327 ps
CPU time 1.85 seconds
Started Jul 27 05:57:23 PM PDT 24
Finished Jul 27 05:57:25 PM PDT 24
Peak memory 218468 kb
Host smart-6b682e90-b562-4f78-a396-ebf692bfd939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079486091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1079486091
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.3858532337
Short name T331
Test name
Test status
Simulation time 91300545 ps
CPU time 1.51 seconds
Started Jul 27 05:57:27 PM PDT 24
Finished Jul 27 05:57:29 PM PDT 24
Peak memory 219968 kb
Host smart-b53392da-f186-47c8-9af0-78dbfc197293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858532337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3858532337
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.878132120
Short name T57
Test name
Test status
Simulation time 16187055 ps
CPU time 0.98 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:56 PM PDT 24
Peak memory 206984 kb
Host smart-952d979a-97b8-4ac5-97ce-fb73605c7673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878132120 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.878132120
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/37.edn_intr.3287735449
Short name T27
Test name
Test status
Simulation time 83891981 ps
CPU time 0.87 seconds
Started Jul 27 05:56:37 PM PDT 24
Finished Jul 27 05:56:38 PM PDT 24
Peak memory 215380 kb
Host smart-642fb18e-68e5-45c6-b415-2ca1873be236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287735449 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3287735449
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/18.edn_genbits.1455407329
Short name T406
Test name
Test status
Simulation time 65389095 ps
CPU time 1.08 seconds
Started Jul 27 05:56:08 PM PDT 24
Finished Jul 27 05:56:10 PM PDT 24
Peak memory 217484 kb
Host smart-ba9b3e56-9a8e-45eb-b7c6-e1242547b6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455407329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1455407329
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2118819868
Short name T307
Test name
Test status
Simulation time 35513019 ps
CPU time 1.45 seconds
Started Jul 27 05:57:49 PM PDT 24
Finished Jul 27 05:57:51 PM PDT 24
Peak memory 217204 kb
Host smart-2b864bad-704f-4721-9c8a-eed912d4e60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118819868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2118819868
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1513204171
Short name T226
Test name
Test status
Simulation time 142124884 ps
CPU time 1.47 seconds
Started Jul 27 05:37:03 PM PDT 24
Finished Jul 27 05:37:04 PM PDT 24
Peak memory 206584 kb
Host smart-7d23010f-f3ca-40a5-9c87-cd2bad1343a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513204171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1513204171
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.877094424
Short name T338
Test name
Test status
Simulation time 235852908904 ps
CPU time 1425.31 seconds
Started Jul 27 05:55:28 PM PDT 24
Finished Jul 27 06:19:14 PM PDT 24
Peak memory 224456 kb
Host smart-6fd3678c-bae1-4919-bf5a-ea09ba29cd02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877094424 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.877094424
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/124.edn_genbits.2415925145
Short name T335
Test name
Test status
Simulation time 25209831 ps
CPU time 1.21 seconds
Started Jul 27 05:57:32 PM PDT 24
Finished Jul 27 05:57:33 PM PDT 24
Peak memory 218444 kb
Host smart-52f2b0e5-909a-4e73-9e9c-d24995d158d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415925145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2415925145
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_stress_all.2754564369
Short name T839
Test name
Test status
Simulation time 252346315 ps
CPU time 2.32 seconds
Started Jul 27 05:56:03 PM PDT 24
Finished Jul 27 05:56:06 PM PDT 24
Peak memory 217224 kb
Host smart-d6c2dfab-58be-4a23-8a88-c8f6f9a947fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754564369 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2754564369
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/145.edn_genbits.436130072
Short name T337
Test name
Test status
Simulation time 69037373 ps
CPU time 1.89 seconds
Started Jul 27 05:57:33 PM PDT 24
Finished Jul 27 05:57:35 PM PDT 24
Peak memory 219296 kb
Host smart-360f2bcc-0972-4892-a470-c8ef932cbd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436130072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.436130072
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/180.edn_genbits.4102492356
Short name T319
Test name
Test status
Simulation time 142374110 ps
CPU time 2.86 seconds
Started Jul 27 05:58:03 PM PDT 24
Finished Jul 27 05:58:05 PM PDT 24
Peak memory 220088 kb
Host smart-27f8ab0b-f1b7-4049-a112-f3a2ac1ce98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102492356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.4102492356
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1225510431
Short name T308
Test name
Test status
Simulation time 101417254 ps
CPU time 1.7 seconds
Started Jul 27 05:58:06 PM PDT 24
Finished Jul 27 05:58:07 PM PDT 24
Peak memory 220160 kb
Host smart-7e3cdd22-0772-4323-a437-c180f9a74bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225510431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1225510431
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2895860935
Short name T324
Test name
Test status
Simulation time 53996072 ps
CPU time 1.14 seconds
Started Jul 27 05:58:07 PM PDT 24
Finished Jul 27 05:58:08 PM PDT 24
Peak memory 218244 kb
Host smart-734c9b12-5799-4b02-9a29-5b45485c9ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895860935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2895860935
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.792910125
Short name T81
Test name
Test status
Simulation time 20455307 ps
CPU time 1.12 seconds
Started Jul 27 05:55:49 PM PDT 24
Finished Jul 27 05:55:50 PM PDT 24
Peak memory 215832 kb
Host smart-fd103a66-add1-44a5-b77b-d0fa11f6d9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792910125 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.792910125
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/1.edn_alert.2756191221
Short name T847
Test name
Test status
Simulation time 28525012 ps
CPU time 1.32 seconds
Started Jul 27 05:55:38 PM PDT 24
Finished Jul 27 05:55:40 PM PDT 24
Peak memory 220664 kb
Host smart-36eca42d-04fa-4be1-a06a-80f27b31c585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756191221 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2756191221
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/121.edn_alert.3972436736
Short name T144
Test name
Test status
Simulation time 184904494 ps
CPU time 1.3 seconds
Started Jul 27 05:57:29 PM PDT 24
Finished Jul 27 05:57:31 PM PDT 24
Peak memory 219568 kb
Host smart-7d9c5ac5-a929-4b39-84e0-1b7a07a9adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972436736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3972436736
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.3269604088
Short name T766
Test name
Test status
Simulation time 29507904 ps
CPU time 0.84 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 216096 kb
Host smart-a43970a5-28ac-466c-aac6-c99fe8ade34f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269604088 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3269604088
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2442876887
Short name T266
Test name
Test status
Simulation time 29523836 ps
CPU time 1.14 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:36:55 PM PDT 24
Peak memory 206484 kb
Host smart-4f931900-6bd4-44a6-b013-2e132b5e3d98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442876887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2442876887
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.629710637
Short name T1029
Test name
Test status
Simulation time 94280390 ps
CPU time 3.07 seconds
Started Jul 27 05:36:51 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 206412 kb
Host smart-62f2a5c7-13b6-45ab-b55a-a4f243f18983
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629710637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.629710637
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.766676593
Short name T267
Test name
Test status
Simulation time 30653126 ps
CPU time 0.96 seconds
Started Jul 27 05:36:43 PM PDT 24
Finished Jul 27 05:36:44 PM PDT 24
Peak memory 206464 kb
Host smart-e4596f1f-98e2-4737-bc92-961a1e3392db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766676593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.766676593
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1197165177
Short name T1106
Test name
Test status
Simulation time 45008139 ps
CPU time 1.23 seconds
Started Jul 27 05:37:08 PM PDT 24
Finished Jul 27 05:37:10 PM PDT 24
Peak memory 214800 kb
Host smart-53289de1-9a35-45ab-8703-f3dadf5d4a84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197165177 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1197165177
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3078871592
Short name T279
Test name
Test status
Simulation time 47497436 ps
CPU time 0.88 seconds
Started Jul 27 05:36:43 PM PDT 24
Finished Jul 27 05:36:44 PM PDT 24
Peak memory 206428 kb
Host smart-d9d5509a-23e5-438f-8232-54a8200cc47b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078871592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3078871592
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3847352615
Short name T1105
Test name
Test status
Simulation time 20558648 ps
CPU time 0.81 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 206436 kb
Host smart-8163bb6f-2198-4b97-b638-9dbea19f9a35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847352615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3847352615
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3497338289
Short name T1072
Test name
Test status
Simulation time 74633052 ps
CPU time 1.08 seconds
Started Jul 27 05:36:51 PM PDT 24
Finished Jul 27 05:36:52 PM PDT 24
Peak memory 206572 kb
Host smart-d4ad3127-ad53-455b-87da-b73fa6bee12f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497338289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3497338289
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2737299430
Short name T1003
Test name
Test status
Simulation time 37417152 ps
CPU time 2.48 seconds
Started Jul 27 05:36:54 PM PDT 24
Finished Jul 27 05:36:56 PM PDT 24
Peak memory 214824 kb
Host smart-bf1c90e8-a47c-4d1a-bc7a-d6ab61575443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737299430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2737299430
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4129221326
Short name T1021
Test name
Test status
Simulation time 166375554 ps
CPU time 2.37 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:36:56 PM PDT 24
Peak memory 206640 kb
Host smart-52393c72-cba5-4368-a6ac-835a55fe0224
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129221326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4129221326
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1624850504
Short name T1092
Test name
Test status
Simulation time 93443080 ps
CPU time 1.46 seconds
Started Jul 27 05:36:50 PM PDT 24
Finished Jul 27 05:36:51 PM PDT 24
Peak memory 206396 kb
Host smart-3384cd63-d7c3-4192-8ae4-671eac38f1c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624850504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1624850504
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1200494605
Short name T272
Test name
Test status
Simulation time 175238061 ps
CPU time 3.73 seconds
Started Jul 27 05:36:50 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 206444 kb
Host smart-67abc7e7-ea17-478a-8e9b-1dfb6c94f7c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200494605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1200494605
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1722965077
Short name T1026
Test name
Test status
Simulation time 59998223 ps
CPU time 0.89 seconds
Started Jul 27 05:36:52 PM PDT 24
Finished Jul 27 05:36:53 PM PDT 24
Peak memory 206420 kb
Host smart-9e838330-37e3-4b76-a565-3e8b987a027f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722965077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1722965077
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.179770517
Short name T1028
Test name
Test status
Simulation time 104151358 ps
CPU time 1.16 seconds
Started Jul 27 05:36:52 PM PDT 24
Finished Jul 27 05:36:53 PM PDT 24
Peak memory 214752 kb
Host smart-f57e37fb-cee0-430f-ae8a-3a275c7b868d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179770517 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.179770517
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3531797105
Short name T262
Test name
Test status
Simulation time 19886681 ps
CPU time 0.92 seconds
Started Jul 27 05:36:52 PM PDT 24
Finished Jul 27 05:36:53 PM PDT 24
Peak memory 206456 kb
Host smart-41684cb7-8e0f-49d0-9b07-d5176e65e7d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531797105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3531797105
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.534306854
Short name T1018
Test name
Test status
Simulation time 36768679 ps
CPU time 0.85 seconds
Started Jul 27 05:37:09 PM PDT 24
Finished Jul 27 05:37:10 PM PDT 24
Peak memory 206224 kb
Host smart-37fd0e1c-653f-4b9d-bc12-984c052dd77b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534306854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.534306854
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2956211641
Short name T281
Test name
Test status
Simulation time 51497804 ps
CPU time 1.03 seconds
Started Jul 27 05:36:50 PM PDT 24
Finished Jul 27 05:36:51 PM PDT 24
Peak memory 206648 kb
Host smart-bfc48ed1-c2f8-40fc-9ad7-9d7650cb7c0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956211641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2956211641
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.768987549
Short name T995
Test name
Test status
Simulation time 255681163 ps
CPU time 2.92 seconds
Started Jul 27 05:36:50 PM PDT 24
Finished Jul 27 05:36:53 PM PDT 24
Peak memory 214860 kb
Host smart-feacd2ac-1a01-4dc0-85ad-9e6f3e249d78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768987549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.768987549
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1052426968
Short name T1122
Test name
Test status
Simulation time 60066223 ps
CPU time 1.66 seconds
Started Jul 27 05:36:49 PM PDT 24
Finished Jul 27 05:36:51 PM PDT 24
Peak memory 214792 kb
Host smart-fed90e17-8be7-4988-b754-404131c464ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052426968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1052426968
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.946661194
Short name T1100
Test name
Test status
Simulation time 67320567 ps
CPU time 1.45 seconds
Started Jul 27 05:37:03 PM PDT 24
Finished Jul 27 05:37:05 PM PDT 24
Peak memory 214820 kb
Host smart-4fc6d22b-e5b9-4d58-8973-ba8410556d0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946661194 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.946661194
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.809682246
Short name T1037
Test name
Test status
Simulation time 45710932 ps
CPU time 0.91 seconds
Started Jul 27 05:36:59 PM PDT 24
Finished Jul 27 05:37:00 PM PDT 24
Peak memory 206464 kb
Host smart-75975288-69a1-4541-90ab-7b900a8eb2f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809682246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.809682246
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3992937878
Short name T1009
Test name
Test status
Simulation time 21233667 ps
CPU time 0.84 seconds
Started Jul 27 05:37:02 PM PDT 24
Finished Jul 27 05:37:04 PM PDT 24
Peak memory 206352 kb
Host smart-2ac86b45-454b-46f6-bf3e-892411a206a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992937878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3992937878
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3355526786
Short name T1121
Test name
Test status
Simulation time 51468686 ps
CPU time 1.03 seconds
Started Jul 27 05:37:02 PM PDT 24
Finished Jul 27 05:37:03 PM PDT 24
Peak memory 206644 kb
Host smart-2694c830-58df-4099-bc25-99b13400aaf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355526786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3355526786
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.894234096
Short name T1109
Test name
Test status
Simulation time 74927561 ps
CPU time 2.22 seconds
Started Jul 27 05:37:02 PM PDT 24
Finished Jul 27 05:37:05 PM PDT 24
Peak memory 214768 kb
Host smart-ab18bc42-6eaf-4704-b58d-e1f52f6765b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894234096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.894234096
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.4155170341
Short name T1101
Test name
Test status
Simulation time 184314212 ps
CPU time 1.62 seconds
Started Jul 27 05:37:09 PM PDT 24
Finished Jul 27 05:37:11 PM PDT 24
Peak memory 214820 kb
Host smart-62b69467-f73b-44dd-9d14-6880f6608164
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155170341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.4155170341
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2656947363
Short name T997
Test name
Test status
Simulation time 32481564 ps
CPU time 1.45 seconds
Started Jul 27 05:37:00 PM PDT 24
Finished Jul 27 05:37:01 PM PDT 24
Peak memory 214904 kb
Host smart-139f8c91-c61d-4352-b731-ec6887af0d00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656947363 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2656947363
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.466800064
Short name T260
Test name
Test status
Simulation time 50799829 ps
CPU time 0.81 seconds
Started Jul 27 05:36:57 PM PDT 24
Finished Jul 27 05:36:58 PM PDT 24
Peak memory 206276 kb
Host smart-850f8042-3a32-411c-984e-b3a46487a841
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466800064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.466800064
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1025311196
Short name T1014
Test name
Test status
Simulation time 19925216 ps
CPU time 0.81 seconds
Started Jul 27 05:37:01 PM PDT 24
Finished Jul 27 05:37:02 PM PDT 24
Peak memory 206284 kb
Host smart-d19cb230-cc91-4a8e-aa3d-92065b803160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025311196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1025311196
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.4024222264
Short name T1045
Test name
Test status
Simulation time 36023804 ps
CPU time 1.23 seconds
Started Jul 27 05:37:02 PM PDT 24
Finished Jul 27 05:37:04 PM PDT 24
Peak memory 206660 kb
Host smart-83c37f8b-0c6a-4390-a8db-d3e01fe39889
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024222264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.4024222264
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3143378523
Short name T1002
Test name
Test status
Simulation time 68204288 ps
CPU time 2.27 seconds
Started Jul 27 05:37:02 PM PDT 24
Finished Jul 27 05:37:05 PM PDT 24
Peak memory 214936 kb
Host smart-a4435d9a-9e1a-4db3-9c1f-994d1b241f6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143378523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3143378523
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2627751226
Short name T1063
Test name
Test status
Simulation time 334666777 ps
CPU time 2.84 seconds
Started Jul 27 05:37:01 PM PDT 24
Finished Jul 27 05:37:04 PM PDT 24
Peak memory 214860 kb
Host smart-2c5cc9da-b93f-4faf-a169-40fa25606e65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627751226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2627751226
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3426154940
Short name T1007
Test name
Test status
Simulation time 63154126 ps
CPU time 1.07 seconds
Started Jul 27 05:37:02 PM PDT 24
Finished Jul 27 05:37:03 PM PDT 24
Peak memory 216312 kb
Host smart-bf16946f-5470-4f37-a65b-256a01502abd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426154940 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3426154940
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3969715503
Short name T268
Test name
Test status
Simulation time 23836053 ps
CPU time 0.87 seconds
Started Jul 27 05:37:00 PM PDT 24
Finished Jul 27 05:37:01 PM PDT 24
Peak memory 206688 kb
Host smart-ac0ea98e-88f2-4d12-ba25-62736fe587d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969715503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3969715503
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.490303872
Short name T1012
Test name
Test status
Simulation time 14276903 ps
CPU time 0.92 seconds
Started Jul 27 05:37:00 PM PDT 24
Finished Jul 27 05:37:01 PM PDT 24
Peak memory 206404 kb
Host smart-7e5d87e0-7b55-41ed-b0c0-a10ec0b58119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490303872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.490303872
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1902858462
Short name T1079
Test name
Test status
Simulation time 40907501 ps
CPU time 1.55 seconds
Started Jul 27 05:37:03 PM PDT 24
Finished Jul 27 05:37:05 PM PDT 24
Peak memory 206620 kb
Host smart-e7d06f6a-53d8-4dfd-b1d2-5c6347fa8d12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902858462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1902858462
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2906332208
Short name T1008
Test name
Test status
Simulation time 95287133 ps
CPU time 3.8 seconds
Started Jul 27 05:37:00 PM PDT 24
Finished Jul 27 05:37:04 PM PDT 24
Peak memory 214892 kb
Host smart-23363681-2498-4d8d-b898-2fc443d38ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906332208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2906332208
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.98718199
Short name T1046
Test name
Test status
Simulation time 60020481 ps
CPU time 1.48 seconds
Started Jul 27 05:37:03 PM PDT 24
Finished Jul 27 05:37:05 PM PDT 24
Peak memory 223008 kb
Host smart-6221022c-c3d3-4703-9e0d-f8534248ca5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98718199 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.98718199
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3696610016
Short name T270
Test name
Test status
Simulation time 22900487 ps
CPU time 0.89 seconds
Started Jul 27 05:37:01 PM PDT 24
Finished Jul 27 05:37:02 PM PDT 24
Peak memory 206464 kb
Host smart-448c5af2-43b1-4982-9149-caa3b6b3d4b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696610016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3696610016
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1089411631
Short name T1015
Test name
Test status
Simulation time 16418857 ps
CPU time 0.88 seconds
Started Jul 27 05:37:04 PM PDT 24
Finished Jul 27 05:37:05 PM PDT 24
Peak memory 206464 kb
Host smart-c7ab93a9-a83e-4e3f-bd09-2b6865ebd2be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089411631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1089411631
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1754178375
Short name T280
Test name
Test status
Simulation time 57177274 ps
CPU time 1.09 seconds
Started Jul 27 05:37:00 PM PDT 24
Finished Jul 27 05:37:02 PM PDT 24
Peak memory 206628 kb
Host smart-294d6370-c30e-45e6-89a9-2ed086567901
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754178375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1754178375
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.423120827
Short name T1124
Test name
Test status
Simulation time 447527437 ps
CPU time 2.54 seconds
Started Jul 27 05:37:02 PM PDT 24
Finished Jul 27 05:37:04 PM PDT 24
Peak memory 214808 kb
Host smart-404b8d98-9e96-48ad-9bc4-5cb3f02308d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423120827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.423120827
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.91092260
Short name T1086
Test name
Test status
Simulation time 62155641 ps
CPU time 1.68 seconds
Started Jul 27 05:37:02 PM PDT 24
Finished Jul 27 05:37:04 PM PDT 24
Peak memory 206656 kb
Host smart-31412b2d-0d5c-47dc-9838-ed817474791a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91092260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.91092260
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1329760576
Short name T1085
Test name
Test status
Simulation time 18742760 ps
CPU time 1.16 seconds
Started Jul 27 05:37:17 PM PDT 24
Finished Jul 27 05:37:18 PM PDT 24
Peak memory 214884 kb
Host smart-bba85514-3e3b-4b70-991a-c196bfcfc448
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329760576 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1329760576
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.954938115
Short name T1088
Test name
Test status
Simulation time 42883690 ps
CPU time 0.82 seconds
Started Jul 27 05:37:18 PM PDT 24
Finished Jul 27 05:37:19 PM PDT 24
Peak memory 206132 kb
Host smart-c6befa44-0251-4952-ae04-60876af92244
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954938115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.954938115
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.4284934440
Short name T1098
Test name
Test status
Simulation time 172674475 ps
CPU time 0.81 seconds
Started Jul 27 05:37:16 PM PDT 24
Finished Jul 27 05:37:17 PM PDT 24
Peak memory 206452 kb
Host smart-a7f1ebda-1f39-4bc1-856c-da2bc9b835a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284934440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.4284934440
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.742375338
Short name T1048
Test name
Test status
Simulation time 42798028 ps
CPU time 1.08 seconds
Started Jul 27 05:37:15 PM PDT 24
Finished Jul 27 05:37:17 PM PDT 24
Peak memory 206516 kb
Host smart-5f0e609c-e15d-4747-9d18-44c04cbf332c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742375338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.742375338
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3048832796
Short name T1116
Test name
Test status
Simulation time 68616510 ps
CPU time 2.54 seconds
Started Jul 27 05:37:12 PM PDT 24
Finished Jul 27 05:37:15 PM PDT 24
Peak memory 222992 kb
Host smart-423510c6-0ca9-4583-9016-ad49cff5788a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048832796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3048832796
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.325069366
Short name T1033
Test name
Test status
Simulation time 76738405 ps
CPU time 1.54 seconds
Started Jul 27 05:37:17 PM PDT 24
Finished Jul 27 05:37:19 PM PDT 24
Peak memory 206568 kb
Host smart-fe6b732d-943b-47de-8fe0-e3b1332bce6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325069366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.325069366
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.457482327
Short name T1078
Test name
Test status
Simulation time 22955247 ps
CPU time 1.19 seconds
Started Jul 27 05:37:13 PM PDT 24
Finished Jul 27 05:37:15 PM PDT 24
Peak memory 214812 kb
Host smart-0680f13f-500d-41ab-8401-49129388d58c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457482327 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.457482327
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.129627927
Short name T1090
Test name
Test status
Simulation time 17855369 ps
CPU time 0.84 seconds
Started Jul 27 05:37:09 PM PDT 24
Finished Jul 27 05:37:10 PM PDT 24
Peak memory 206428 kb
Host smart-0b8590d5-6e33-4c0a-ac63-b9ba9e17e0bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129627927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.129627927
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.4245139491
Short name T1023
Test name
Test status
Simulation time 61072198 ps
CPU time 0.81 seconds
Started Jul 27 05:37:12 PM PDT 24
Finished Jul 27 05:37:13 PM PDT 24
Peak memory 206260 kb
Host smart-4c85e06e-7423-48af-b56b-8ced855d30bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245139491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.4245139491
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2875069195
Short name T1057
Test name
Test status
Simulation time 50100130 ps
CPU time 1.23 seconds
Started Jul 27 05:37:15 PM PDT 24
Finished Jul 27 05:37:17 PM PDT 24
Peak memory 206584 kb
Host smart-243c2e60-feb5-48b0-9439-9bab5ed00a1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875069195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2875069195
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.262040935
Short name T1004
Test name
Test status
Simulation time 40430874 ps
CPU time 1.63 seconds
Started Jul 27 05:37:10 PM PDT 24
Finished Jul 27 05:37:11 PM PDT 24
Peak memory 214880 kb
Host smart-8c070c71-d69a-4563-8470-7cb9021ebb69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262040935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.262040935
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3895178565
Short name T303
Test name
Test status
Simulation time 257152902 ps
CPU time 1.7 seconds
Started Jul 27 05:37:12 PM PDT 24
Finished Jul 27 05:37:14 PM PDT 24
Peak memory 206732 kb
Host smart-bb154156-be87-4510-b65d-2af0b8c89718
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895178565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3895178565
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1584952453
Short name T1094
Test name
Test status
Simulation time 38117429 ps
CPU time 1.34 seconds
Started Jul 27 05:37:13 PM PDT 24
Finished Jul 27 05:37:14 PM PDT 24
Peak memory 222984 kb
Host smart-fc6b395a-d4e4-4e00-9fe5-06939833e75b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584952453 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1584952453
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.142103161
Short name T276
Test name
Test status
Simulation time 17778950 ps
CPU time 0.84 seconds
Started Jul 27 05:37:13 PM PDT 24
Finished Jul 27 05:37:14 PM PDT 24
Peak memory 206268 kb
Host smart-51fca24d-0b53-4b4a-ab25-b300c82ee38a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142103161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.142103161
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1864219422
Short name T999
Test name
Test status
Simulation time 17877891 ps
CPU time 0.94 seconds
Started Jul 27 05:37:12 PM PDT 24
Finished Jul 27 05:37:13 PM PDT 24
Peak memory 206420 kb
Host smart-133a5f7a-8e44-4b14-be99-ad8278275a90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864219422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1864219422
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4147603051
Short name T1112
Test name
Test status
Simulation time 70960130 ps
CPU time 1.51 seconds
Started Jul 27 05:37:14 PM PDT 24
Finished Jul 27 05:37:16 PM PDT 24
Peak memory 206652 kb
Host smart-9924ad14-f2a2-4e11-bfd8-8172eb8819dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147603051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.4147603051
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1462081888
Short name T1006
Test name
Test status
Simulation time 314683446 ps
CPU time 3.36 seconds
Started Jul 27 05:37:10 PM PDT 24
Finished Jul 27 05:37:14 PM PDT 24
Peak memory 214848 kb
Host smart-c5ab4b06-3f55-491d-9015-a94ca6535adf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462081888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1462081888
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.979357574
Short name T1011
Test name
Test status
Simulation time 139861556 ps
CPU time 1.55 seconds
Started Jul 27 05:37:13 PM PDT 24
Finished Jul 27 05:37:15 PM PDT 24
Peak memory 214752 kb
Host smart-a1acf9c7-88e4-4d42-81a8-c12b07517301
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979357574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.979357574
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3671116695
Short name T1104
Test name
Test status
Simulation time 122747110 ps
CPU time 1.52 seconds
Started Jul 27 05:37:08 PM PDT 24
Finished Jul 27 05:37:10 PM PDT 24
Peak memory 214844 kb
Host smart-8a5f388d-84ba-44ed-ae46-11d538ea8008
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671116695 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3671116695
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.623736425
Short name T295
Test name
Test status
Simulation time 125430012 ps
CPU time 0.92 seconds
Started Jul 27 05:37:09 PM PDT 24
Finished Jul 27 05:37:10 PM PDT 24
Peak memory 206444 kb
Host smart-1e5819bf-3c76-4212-80d4-f9b2ac0f166b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623736425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.623736425
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.218935860
Short name T1077
Test name
Test status
Simulation time 11526947 ps
CPU time 0.88 seconds
Started Jul 27 05:37:11 PM PDT 24
Finished Jul 27 05:37:12 PM PDT 24
Peak memory 206340 kb
Host smart-0d35afb9-4383-4c6e-b17c-f96e0ebfd343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218935860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.218935860
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2242799143
Short name T1076
Test name
Test status
Simulation time 36103940 ps
CPU time 1.15 seconds
Started Jul 27 05:37:11 PM PDT 24
Finished Jul 27 05:37:13 PM PDT 24
Peak memory 206532 kb
Host smart-42abb11b-8ff8-4f11-a48d-77a2f4f5fea4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242799143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2242799143
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2250217515
Short name T1044
Test name
Test status
Simulation time 98707859 ps
CPU time 2.62 seconds
Started Jul 27 05:37:13 PM PDT 24
Finished Jul 27 05:37:15 PM PDT 24
Peak memory 214848 kb
Host smart-99612a18-caa1-4389-b9b8-8cc6bb60c1c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250217515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2250217515
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3977925185
Short name T1073
Test name
Test status
Simulation time 97026475 ps
CPU time 2.58 seconds
Started Jul 27 05:37:16 PM PDT 24
Finished Jul 27 05:37:19 PM PDT 24
Peak memory 206552 kb
Host smart-7e3f292e-c8f6-46a8-aeda-f352d7b42539
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977925185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3977925185
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.169352928
Short name T1034
Test name
Test status
Simulation time 31956899 ps
CPU time 1.52 seconds
Started Jul 27 05:37:10 PM PDT 24
Finished Jul 27 05:37:11 PM PDT 24
Peak memory 215084 kb
Host smart-14b7cb19-dbcb-413a-9def-6d46436f3eb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169352928 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.169352928
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.434824924
Short name T1038
Test name
Test status
Simulation time 96930226 ps
CPU time 0.81 seconds
Started Jul 27 05:37:18 PM PDT 24
Finished Jul 27 05:37:19 PM PDT 24
Peak memory 206132 kb
Host smart-893c3d35-e02f-4a42-b715-3e629ae249e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434824924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.434824924
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2543125383
Short name T1056
Test name
Test status
Simulation time 44513546 ps
CPU time 0.89 seconds
Started Jul 27 05:37:17 PM PDT 24
Finished Jul 27 05:37:18 PM PDT 24
Peak memory 206444 kb
Host smart-b0211585-ff24-449a-a344-685a0d655e56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543125383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2543125383
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.453338708
Short name T1102
Test name
Test status
Simulation time 45995119 ps
CPU time 1.37 seconds
Started Jul 27 05:37:10 PM PDT 24
Finished Jul 27 05:37:12 PM PDT 24
Peak memory 206632 kb
Host smart-bd98d3d6-5fe5-42bf-a59d-d457248af435
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453338708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.453338708
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.850372033
Short name T1024
Test name
Test status
Simulation time 433815069 ps
CPU time 3.47 seconds
Started Jul 27 05:37:10 PM PDT 24
Finished Jul 27 05:37:14 PM PDT 24
Peak memory 214892 kb
Host smart-3133b1f5-8500-4ad5-ad7b-57930b85ab31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850372033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.850372033
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4165128637
Short name T1016
Test name
Test status
Simulation time 82662128 ps
CPU time 2.39 seconds
Started Jul 27 05:37:11 PM PDT 24
Finished Jul 27 05:37:14 PM PDT 24
Peak memory 206544 kb
Host smart-4edc9a80-44ce-41b3-9a3e-166cadb2bc29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165128637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4165128637
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3853531194
Short name T1055
Test name
Test status
Simulation time 55066759 ps
CPU time 1.07 seconds
Started Jul 27 05:37:10 PM PDT 24
Finished Jul 27 05:37:11 PM PDT 24
Peak memory 206640 kb
Host smart-007c94c0-4eed-4446-9545-fe4babd453d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853531194 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3853531194
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2568886787
Short name T269
Test name
Test status
Simulation time 37930752 ps
CPU time 0.81 seconds
Started Jul 27 05:37:14 PM PDT 24
Finished Jul 27 05:37:16 PM PDT 24
Peak memory 206264 kb
Host smart-58c96ae9-73db-46e9-8338-80bdc5ebb753
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568886787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2568886787
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2337111924
Short name T1032
Test name
Test status
Simulation time 28410800 ps
CPU time 0.99 seconds
Started Jul 27 05:37:12 PM PDT 24
Finished Jul 27 05:37:13 PM PDT 24
Peak memory 206472 kb
Host smart-3babfa8a-8e9f-4303-8373-28b534417c44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337111924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2337111924
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1441679429
Short name T284
Test name
Test status
Simulation time 30307131 ps
CPU time 1.12 seconds
Started Jul 27 05:37:18 PM PDT 24
Finished Jul 27 05:37:19 PM PDT 24
Peak memory 206436 kb
Host smart-6aa93fce-ca08-4754-b5c4-a5ced7225e41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441679429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1441679429
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.445976172
Short name T1025
Test name
Test status
Simulation time 197504885 ps
CPU time 3.71 seconds
Started Jul 27 05:37:11 PM PDT 24
Finished Jul 27 05:37:15 PM PDT 24
Peak memory 214928 kb
Host smart-9e1e6327-1be3-4859-aa16-d68ea6e13b59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445976172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.445976172
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3606421884
Short name T300
Test name
Test status
Simulation time 184899120 ps
CPU time 2.47 seconds
Started Jul 27 05:37:12 PM PDT 24
Finished Jul 27 05:37:14 PM PDT 24
Peak memory 206920 kb
Host smart-9eef887a-61ae-4489-b423-e8853030d679
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606421884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3606421884
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4038147892
Short name T274
Test name
Test status
Simulation time 44197883 ps
CPU time 1.22 seconds
Started Jul 27 05:36:51 PM PDT 24
Finished Jul 27 05:36:52 PM PDT 24
Peak memory 206468 kb
Host smart-2394ce65-e43a-42f9-b5b8-52fcf687adfa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038147892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4038147892
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4115381516
Short name T1065
Test name
Test status
Simulation time 385174589 ps
CPU time 3.72 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:36:57 PM PDT 24
Peak memory 206480 kb
Host smart-b34efdd4-22c9-4368-96af-e1d2eec56bce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115381516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.4115381516
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3596566116
Short name T265
Test name
Test status
Simulation time 41522853 ps
CPU time 0.84 seconds
Started Jul 27 05:37:08 PM PDT 24
Finished Jul 27 05:37:09 PM PDT 24
Peak memory 206228 kb
Host smart-e7ff472a-05e5-4679-99bf-871cc80d188e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596566116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3596566116
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1166538888
Short name T1089
Test name
Test status
Simulation time 27652605 ps
CPU time 1.66 seconds
Started Jul 27 05:36:51 PM PDT 24
Finished Jul 27 05:36:52 PM PDT 24
Peak memory 214972 kb
Host smart-375ccc84-b82b-4896-88c8-eb9c0cb7d31e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166538888 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1166538888
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1592911417
Short name T277
Test name
Test status
Simulation time 24879415 ps
CPU time 0.9 seconds
Started Jul 27 05:37:08 PM PDT 24
Finished Jul 27 05:37:09 PM PDT 24
Peak memory 206412 kb
Host smart-b069733f-4573-4af5-b1fa-703eee655a23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592911417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1592911417
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.741047762
Short name T1120
Test name
Test status
Simulation time 16959831 ps
CPU time 0.78 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 206248 kb
Host smart-a485a9bd-5b24-4124-b9f5-2ade6d50ecd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741047762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.741047762
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1034243286
Short name T1118
Test name
Test status
Simulation time 23839737 ps
CPU time 1.14 seconds
Started Jul 27 05:36:52 PM PDT 24
Finished Jul 27 05:36:53 PM PDT 24
Peak memory 206560 kb
Host smart-c6d564e1-06bf-4486-a23a-90a4db1f7bc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034243286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1034243286
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3869363235
Short name T1050
Test name
Test status
Simulation time 229628487 ps
CPU time 2.97 seconds
Started Jul 27 05:36:52 PM PDT 24
Finished Jul 27 05:36:55 PM PDT 24
Peak memory 214932 kb
Host smart-085618d4-b384-428f-ba35-06d8cbb2a48a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869363235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3869363235
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2483569978
Short name T1040
Test name
Test status
Simulation time 277773832 ps
CPU time 2.22 seconds
Started Jul 27 05:37:00 PM PDT 24
Finished Jul 27 05:37:02 PM PDT 24
Peak memory 206812 kb
Host smart-bf1f7364-47a0-4b89-a4a5-e964f1db68bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483569978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2483569978
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1917989941
Short name T1084
Test name
Test status
Simulation time 15124598 ps
CPU time 0.89 seconds
Started Jul 27 05:37:11 PM PDT 24
Finished Jul 27 05:37:12 PM PDT 24
Peak memory 206468 kb
Host smart-9de6a4c1-2a84-4f35-b1cb-c0d8326d3aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917989941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1917989941
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2105496817
Short name T1059
Test name
Test status
Simulation time 82311962 ps
CPU time 0.85 seconds
Started Jul 27 05:37:12 PM PDT 24
Finished Jul 27 05:37:13 PM PDT 24
Peak memory 206420 kb
Host smart-2c2f3884-42bf-4c36-b762-ca553b810dfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105496817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2105496817
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.637609248
Short name T1043
Test name
Test status
Simulation time 13134589 ps
CPU time 0.88 seconds
Started Jul 27 05:37:15 PM PDT 24
Finished Jul 27 05:37:16 PM PDT 24
Peak memory 206448 kb
Host smart-31041526-b3d0-4193-97d1-8b49f40fa353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637609248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.637609248
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1422290359
Short name T1096
Test name
Test status
Simulation time 52607659 ps
CPU time 0.91 seconds
Started Jul 27 05:37:19 PM PDT 24
Finished Jul 27 05:37:20 PM PDT 24
Peak memory 206324 kb
Host smart-e84fd72d-1188-4c4d-8a3c-f4d62724c9da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422290359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1422290359
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.4049702422
Short name T1058
Test name
Test status
Simulation time 37836307 ps
CPU time 0.81 seconds
Started Jul 27 05:37:13 PM PDT 24
Finished Jul 27 05:37:14 PM PDT 24
Peak memory 206248 kb
Host smart-513cee30-0d8b-4cc2-9c6e-16e3cea6c556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049702422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.4049702422
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1943750089
Short name T1067
Test name
Test status
Simulation time 30286111 ps
CPU time 0.78 seconds
Started Jul 27 05:37:18 PM PDT 24
Finished Jul 27 05:37:19 PM PDT 24
Peak memory 206140 kb
Host smart-a168c356-ada6-49cf-b254-6b6cc43a2206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943750089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1943750089
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.779047662
Short name T1087
Test name
Test status
Simulation time 11847649 ps
CPU time 0.84 seconds
Started Jul 27 05:37:12 PM PDT 24
Finished Jul 27 05:37:13 PM PDT 24
Peak memory 206460 kb
Host smart-905442e5-0fcd-4657-bbc2-3c422a935dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779047662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.779047662
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1396074326
Short name T998
Test name
Test status
Simulation time 19300275 ps
CPU time 0.92 seconds
Started Jul 27 05:37:10 PM PDT 24
Finished Jul 27 05:37:11 PM PDT 24
Peak memory 206532 kb
Host smart-1ae31ed1-add0-4ce7-a0b2-1d921d9a3464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396074326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1396074326
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2846189525
Short name T1082
Test name
Test status
Simulation time 52714441 ps
CPU time 0.83 seconds
Started Jul 27 05:37:20 PM PDT 24
Finished Jul 27 05:37:21 PM PDT 24
Peak memory 206276 kb
Host smart-e8f7bebf-4421-4d4e-a184-a2ebbec41d63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846189525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2846189525
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3973563201
Short name T1013
Test name
Test status
Simulation time 76323694 ps
CPU time 0.92 seconds
Started Jul 27 05:37:21 PM PDT 24
Finished Jul 27 05:37:22 PM PDT 24
Peak memory 206396 kb
Host smart-6348b0d2-27e5-4062-8fae-8342c5579404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973563201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3973563201
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2103466546
Short name T261
Test name
Test status
Simulation time 37813103 ps
CPU time 1.54 seconds
Started Jul 27 05:36:49 PM PDT 24
Finished Jul 27 05:36:51 PM PDT 24
Peak memory 206464 kb
Host smart-3dba2773-4f50-4929-9bb8-b0c23a4c4fb2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103466546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2103466546
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3163213634
Short name T1036
Test name
Test status
Simulation time 255544066 ps
CPU time 6.39 seconds
Started Jul 27 05:36:51 PM PDT 24
Finished Jul 27 05:36:58 PM PDT 24
Peak memory 206600 kb
Host smart-d28beb4d-d501-4558-a57c-1128264a19f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163213634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3163213634
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3006637142
Short name T264
Test name
Test status
Simulation time 50521229 ps
CPU time 0.89 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 206216 kb
Host smart-7e518a6e-fda5-4e17-a1f4-7ed05d660b9b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006637142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3006637142
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3922855270
Short name T1041
Test name
Test status
Simulation time 130695014 ps
CPU time 1.46 seconds
Started Jul 27 05:36:51 PM PDT 24
Finished Jul 27 05:36:52 PM PDT 24
Peak memory 218000 kb
Host smart-4620d1b5-ae21-4ac2-b314-5d293da2abd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922855270 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3922855270
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2984036790
Short name T996
Test name
Test status
Simulation time 53677607 ps
CPU time 0.89 seconds
Started Jul 27 05:37:08 PM PDT 24
Finished Jul 27 05:37:09 PM PDT 24
Peak memory 206420 kb
Host smart-60b84494-a23e-4bf1-b715-281740976d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984036790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2984036790
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3305715128
Short name T282
Test name
Test status
Simulation time 150659520 ps
CPU time 1.34 seconds
Started Jul 27 05:36:54 PM PDT 24
Finished Jul 27 05:36:55 PM PDT 24
Peak memory 206644 kb
Host smart-b89dc3da-4a26-473a-9f8a-117639115583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305715128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3305715128
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1122899195
Short name T1119
Test name
Test status
Simulation time 480279270 ps
CPU time 4.6 seconds
Started Jul 27 05:36:56 PM PDT 24
Finished Jul 27 05:37:00 PM PDT 24
Peak memory 214792 kb
Host smart-6cdaddbe-b387-47d6-a816-fcb6f5f9c260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122899195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1122899195
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.453901223
Short name T227
Test name
Test status
Simulation time 131726017 ps
CPU time 3.23 seconds
Started Jul 27 05:36:51 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 206596 kb
Host smart-798e62ae-8662-482f-9892-63f3321bd7cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453901223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.453901223
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1523195676
Short name T1093
Test name
Test status
Simulation time 95680974 ps
CPU time 0.86 seconds
Started Jul 27 05:37:19 PM PDT 24
Finished Jul 27 05:37:20 PM PDT 24
Peak memory 206280 kb
Host smart-6b8ed4f1-1b5d-4179-8999-4fc4d06532c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523195676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1523195676
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1430734558
Short name T1001
Test name
Test status
Simulation time 14468279 ps
CPU time 0.91 seconds
Started Jul 27 05:37:16 PM PDT 24
Finished Jul 27 05:37:18 PM PDT 24
Peak memory 206428 kb
Host smart-ac8c0516-7e04-4c5c-94b9-51bde22417a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430734558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1430734558
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.4233829811
Short name T1053
Test name
Test status
Simulation time 51292261 ps
CPU time 0.91 seconds
Started Jul 27 05:37:18 PM PDT 24
Finished Jul 27 05:37:19 PM PDT 24
Peak memory 206416 kb
Host smart-5d8528ba-29b1-4e1e-a313-38b34c0cde89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233829811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.4233829811
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3393167140
Short name T1069
Test name
Test status
Simulation time 39868805 ps
CPU time 0.8 seconds
Started Jul 27 05:37:18 PM PDT 24
Finished Jul 27 05:37:20 PM PDT 24
Peak memory 206300 kb
Host smart-be59318e-83a1-4483-8c73-f2bfd59cc32d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393167140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3393167140
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3086779925
Short name T1047
Test name
Test status
Simulation time 19846992 ps
CPU time 0.96 seconds
Started Jul 27 05:37:17 PM PDT 24
Finished Jul 27 05:37:18 PM PDT 24
Peak memory 206468 kb
Host smart-fc632fd9-c12d-4260-991b-7af21d609ecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086779925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3086779925
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2103118244
Short name T1108
Test name
Test status
Simulation time 77443914 ps
CPU time 0.85 seconds
Started Jul 27 05:37:18 PM PDT 24
Finished Jul 27 05:37:20 PM PDT 24
Peak memory 206432 kb
Host smart-b1a02694-6105-49c6-a0d6-6f8a61018fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103118244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2103118244
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3540828517
Short name T1075
Test name
Test status
Simulation time 21694849 ps
CPU time 0.79 seconds
Started Jul 27 05:37:21 PM PDT 24
Finished Jul 27 05:37:22 PM PDT 24
Peak memory 206228 kb
Host smart-afe1d9a3-34c9-4326-8a81-1374d0f44c17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540828517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3540828517
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2896795507
Short name T1107
Test name
Test status
Simulation time 51304440 ps
CPU time 0.84 seconds
Started Jul 27 05:37:21 PM PDT 24
Finished Jul 27 05:37:22 PM PDT 24
Peak memory 206536 kb
Host smart-dd2e9086-0096-4bfa-91e7-d27e98c75623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896795507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2896795507
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2480432580
Short name T1066
Test name
Test status
Simulation time 12305426 ps
CPU time 0.91 seconds
Started Jul 27 05:37:18 PM PDT 24
Finished Jul 27 05:37:19 PM PDT 24
Peak memory 206444 kb
Host smart-04643b80-a119-406e-8bbb-94ec17febf9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480432580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2480432580
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.4097308151
Short name T1091
Test name
Test status
Simulation time 19181554 ps
CPU time 0.86 seconds
Started Jul 27 05:37:25 PM PDT 24
Finished Jul 27 05:37:26 PM PDT 24
Peak memory 206456 kb
Host smart-6e93860d-9349-4238-8f86-35d557b3e989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097308151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.4097308151
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3021033811
Short name T1099
Test name
Test status
Simulation time 32895551 ps
CPU time 1.45 seconds
Started Jul 27 05:37:08 PM PDT 24
Finished Jul 27 05:37:09 PM PDT 24
Peak memory 206420 kb
Host smart-5c131bd4-ec8d-4d36-8f5b-567c34b73276
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021033811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3021033811
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2565904258
Short name T1017
Test name
Test status
Simulation time 59549753 ps
CPU time 3.33 seconds
Started Jul 27 05:36:51 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 206484 kb
Host smart-867fcf65-9e86-4407-814f-d26522f17460
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565904258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2565904258
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3652005400
Short name T271
Test name
Test status
Simulation time 19038804 ps
CPU time 0.99 seconds
Started Jul 27 05:36:51 PM PDT 24
Finished Jul 27 05:36:52 PM PDT 24
Peak memory 206464 kb
Host smart-3fca3a7b-47f5-4c91-8113-18c06bc4e5ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652005400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3652005400
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4226470786
Short name T1125
Test name
Test status
Simulation time 59365011 ps
CPU time 1.41 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:36:55 PM PDT 24
Peak memory 214840 kb
Host smart-048f2b98-ed5f-4423-abdf-2e35a18fe946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226470786 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.4226470786
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1458901359
Short name T1115
Test name
Test status
Simulation time 45381056 ps
CPU time 0.9 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:36:53 PM PDT 24
Peak memory 206472 kb
Host smart-991aae02-e46c-4e20-a23a-cc935dfd7cbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458901359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1458901359
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.376540392
Short name T1062
Test name
Test status
Simulation time 33356839 ps
CPU time 0.82 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 206232 kb
Host smart-7611680e-607f-45b1-b5f2-bd6c02cd208a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376540392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.376540392
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1101843771
Short name T283
Test name
Test status
Simulation time 53194381 ps
CPU time 0.95 seconds
Started Jul 27 05:36:50 PM PDT 24
Finished Jul 27 05:36:51 PM PDT 24
Peak memory 206668 kb
Host smart-848d969e-d663-4a00-a6bb-d33e3cb8897e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101843771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1101843771
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.101151374
Short name T1020
Test name
Test status
Simulation time 80977483 ps
CPU time 2.79 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:36:56 PM PDT 24
Peak memory 214916 kb
Host smart-dcd7b903-c5e9-4e7b-8253-c3b7211f72a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101151374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.101151374
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3675650566
Short name T1074
Test name
Test status
Simulation time 65415323 ps
CPU time 1.38 seconds
Started Jul 27 05:36:55 PM PDT 24
Finished Jul 27 05:36:56 PM PDT 24
Peak memory 206620 kb
Host smart-bd98b8bb-aa1a-4522-b5bd-cb3fa6d8be97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675650566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3675650566
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.324293196
Short name T1030
Test name
Test status
Simulation time 17040727 ps
CPU time 0.91 seconds
Started Jul 27 05:37:19 PM PDT 24
Finished Jul 27 05:37:20 PM PDT 24
Peak memory 206460 kb
Host smart-e5671378-d9f9-4183-a790-afed4059ab20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324293196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.324293196
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.28762892
Short name T1051
Test name
Test status
Simulation time 16605606 ps
CPU time 0.9 seconds
Started Jul 27 05:37:21 PM PDT 24
Finished Jul 27 05:37:22 PM PDT 24
Peak memory 206532 kb
Host smart-3a850bd4-e164-45ed-813b-f15ccc81818a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28762892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.28762892
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1398674825
Short name T1117
Test name
Test status
Simulation time 55151030 ps
CPU time 0.86 seconds
Started Jul 27 05:37:17 PM PDT 24
Finished Jul 27 05:37:18 PM PDT 24
Peak memory 206456 kb
Host smart-e6e47e06-785c-4eae-b83a-ad6715fef7d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398674825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1398674825
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3098349924
Short name T1110
Test name
Test status
Simulation time 15088856 ps
CPU time 0.93 seconds
Started Jul 27 05:37:22 PM PDT 24
Finished Jul 27 05:37:23 PM PDT 24
Peak memory 206460 kb
Host smart-e69e4c2e-ced9-426c-a52e-e1ed6c737c95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098349924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3098349924
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.417926049
Short name T1070
Test name
Test status
Simulation time 23339731 ps
CPU time 0.85 seconds
Started Jul 27 05:37:20 PM PDT 24
Finished Jul 27 05:37:21 PM PDT 24
Peak memory 206460 kb
Host smart-db6d6edd-0938-4d39-a30c-f8f5d9472e2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417926049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.417926049
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2775484124
Short name T1111
Test name
Test status
Simulation time 42931749 ps
CPU time 0.87 seconds
Started Jul 27 05:37:18 PM PDT 24
Finished Jul 27 05:37:19 PM PDT 24
Peak memory 206452 kb
Host smart-41191f3f-f55c-43bd-9de7-f1e1e6e2625a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775484124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2775484124
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.150690440
Short name T1061
Test name
Test status
Simulation time 26252934 ps
CPU time 0.83 seconds
Started Jul 27 05:37:18 PM PDT 24
Finished Jul 27 05:37:19 PM PDT 24
Peak memory 206372 kb
Host smart-5ce46757-0cb3-4892-9a03-56fe400e3cdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150690440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.150690440
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2047662226
Short name T1114
Test name
Test status
Simulation time 17608300 ps
CPU time 0.92 seconds
Started Jul 27 05:37:24 PM PDT 24
Finished Jul 27 05:37:25 PM PDT 24
Peak memory 206324 kb
Host smart-3e64233c-c396-4e7b-9ca1-0c2b69da9af6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047662226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2047662226
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.701405701
Short name T1010
Test name
Test status
Simulation time 109909686 ps
CPU time 0.77 seconds
Started Jul 27 05:37:21 PM PDT 24
Finished Jul 27 05:37:22 PM PDT 24
Peak memory 206272 kb
Host smart-172a92f2-366c-420a-b1c9-d0588bc387b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701405701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.701405701
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3075426803
Short name T1027
Test name
Test status
Simulation time 140447418 ps
CPU time 0.89 seconds
Started Jul 27 05:37:21 PM PDT 24
Finished Jul 27 05:37:22 PM PDT 24
Peak memory 206452 kb
Host smart-bef18d94-3761-45a0-99a8-528a5ff47d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075426803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3075426803
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3614621844
Short name T1083
Test name
Test status
Simulation time 21762882 ps
CPU time 1.32 seconds
Started Jul 27 05:36:56 PM PDT 24
Finished Jul 27 05:36:57 PM PDT 24
Peak memory 214796 kb
Host smart-a5320c56-e3f2-4305-a17c-ad60290c3b50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614621844 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3614621844
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3970879546
Short name T1042
Test name
Test status
Simulation time 19081452 ps
CPU time 0.88 seconds
Started Jul 27 05:36:52 PM PDT 24
Finished Jul 27 05:36:53 PM PDT 24
Peak memory 206460 kb
Host smart-883c4393-1597-4c71-a1f9-f208650f9195
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970879546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3970879546
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.4271234420
Short name T1068
Test name
Test status
Simulation time 17585577 ps
CPU time 0.82 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 206464 kb
Host smart-3405ec40-e319-4032-9e68-e968a3041a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271234420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.4271234420
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2921339871
Short name T1060
Test name
Test status
Simulation time 18074453 ps
CPU time 1.16 seconds
Started Jul 27 05:36:55 PM PDT 24
Finished Jul 27 05:36:56 PM PDT 24
Peak memory 206536 kb
Host smart-39d3d367-261d-4063-b541-3db8407bf6d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921339871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2921339871
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.318072650
Short name T1081
Test name
Test status
Simulation time 168838380 ps
CPU time 4.1 seconds
Started Jul 27 05:36:50 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 214748 kb
Host smart-9cbf73ef-4fcb-463f-8109-3c2beae83883
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318072650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.318072650
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1385300974
Short name T1052
Test name
Test status
Simulation time 70549065 ps
CPU time 2.2 seconds
Started Jul 27 05:36:51 PM PDT 24
Finished Jul 27 05:36:53 PM PDT 24
Peak memory 206532 kb
Host smart-281785ea-d51a-4896-b8dd-f419af78b621
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385300974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1385300974
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3081697679
Short name T1005
Test name
Test status
Simulation time 47517402 ps
CPU time 1.45 seconds
Started Jul 27 05:36:54 PM PDT 24
Finished Jul 27 05:36:56 PM PDT 24
Peak memory 214980 kb
Host smart-8725a8c5-2773-4a39-9f33-1e138c2280b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081697679 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3081697679
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1455260864
Short name T285
Test name
Test status
Simulation time 13503074 ps
CPU time 0.9 seconds
Started Jul 27 05:37:09 PM PDT 24
Finished Jul 27 05:37:11 PM PDT 24
Peak memory 206412 kb
Host smart-67c7616a-1319-48b0-a5f9-5ffd26ff8e71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455260864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1455260864
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.118308178
Short name T1054
Test name
Test status
Simulation time 11621315 ps
CPU time 0.84 seconds
Started Jul 27 05:36:55 PM PDT 24
Finished Jul 27 05:36:56 PM PDT 24
Peak memory 206464 kb
Host smart-4661bcf7-e8da-47db-8720-01dde6bffd5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118308178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.118308178
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2225824371
Short name T278
Test name
Test status
Simulation time 39227691 ps
CPU time 1.49 seconds
Started Jul 27 05:36:56 PM PDT 24
Finished Jul 27 05:36:57 PM PDT 24
Peak memory 206644 kb
Host smart-67579e6a-34eb-4b6f-b66c-1f022135fb71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225824371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2225824371
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2215585079
Short name T1049
Test name
Test status
Simulation time 192560618 ps
CPU time 3.46 seconds
Started Jul 27 05:37:09 PM PDT 24
Finished Jul 27 05:37:13 PM PDT 24
Peak memory 214792 kb
Host smart-974063fb-65bd-4506-b35c-a5c276698bea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215585079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2215585079
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1768147823
Short name T1000
Test name
Test status
Simulation time 50976038 ps
CPU time 1.26 seconds
Started Jul 27 05:36:52 PM PDT 24
Finished Jul 27 05:36:53 PM PDT 24
Peak memory 222988 kb
Host smart-6753a926-65ca-48c9-b473-2adab86b3c2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768147823 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1768147823
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1331143141
Short name T1064
Test name
Test status
Simulation time 16292288 ps
CPU time 0.96 seconds
Started Jul 27 05:37:08 PM PDT 24
Finished Jul 27 05:37:10 PM PDT 24
Peak memory 206412 kb
Host smart-d680294b-f435-4680-986a-e66505daf058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331143141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1331143141
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1515138845
Short name T1019
Test name
Test status
Simulation time 13119069 ps
CPU time 0.89 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 206460 kb
Host smart-475cf1f8-09c5-438d-9f1c-d423962e515b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515138845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1515138845
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.571093958
Short name T1123
Test name
Test status
Simulation time 14948586 ps
CPU time 1.02 seconds
Started Jul 27 05:36:53 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 206576 kb
Host smart-27477070-7ac8-40cc-8189-c9738e32a5a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571093958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.571093958
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3693786913
Short name T1097
Test name
Test status
Simulation time 105838948 ps
CPU time 2.56 seconds
Started Jul 27 05:37:08 PM PDT 24
Finished Jul 27 05:37:11 PM PDT 24
Peak memory 214868 kb
Host smart-4da5fec2-21d6-4bc9-86d8-0896c3338793
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693786913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3693786913
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2282606991
Short name T225
Test name
Test status
Simulation time 690095084 ps
CPU time 2.34 seconds
Started Jul 27 05:36:54 PM PDT 24
Finished Jul 27 05:36:57 PM PDT 24
Peak memory 206584 kb
Host smart-40330838-b43f-4e1d-877c-a0386f333da8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282606991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2282606991
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1529355182
Short name T1103
Test name
Test status
Simulation time 22959419 ps
CPU time 1.44 seconds
Started Jul 27 05:37:02 PM PDT 24
Finished Jul 27 05:37:04 PM PDT 24
Peak memory 214884 kb
Host smart-765536a9-3f20-4002-8c9a-8d8f48e2fb34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529355182 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1529355182
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1206250900
Short name T275
Test name
Test status
Simulation time 14785668 ps
CPU time 0.94 seconds
Started Jul 27 05:37:02 PM PDT 24
Finished Jul 27 05:37:03 PM PDT 24
Peak memory 206440 kb
Host smart-664e78df-1d29-4383-8d4e-162cad214d7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206250900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1206250900
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.4222979126
Short name T1022
Test name
Test status
Simulation time 189305940 ps
CPU time 0.98 seconds
Started Jul 27 05:37:02 PM PDT 24
Finished Jul 27 05:37:04 PM PDT 24
Peak memory 206444 kb
Host smart-be089357-d993-4451-a2c6-c89ff258ee19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222979126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.4222979126
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2197026178
Short name T1095
Test name
Test status
Simulation time 54812197 ps
CPU time 1.37 seconds
Started Jul 27 05:37:04 PM PDT 24
Finished Jul 27 05:37:06 PM PDT 24
Peak memory 206660 kb
Host smart-bee91ffd-6afc-4dff-8227-fe0fb264bc00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197026178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2197026178
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.979111413
Short name T1035
Test name
Test status
Simulation time 58058771 ps
CPU time 2.22 seconds
Started Jul 27 05:36:51 PM PDT 24
Finished Jul 27 05:36:53 PM PDT 24
Peak memory 214900 kb
Host smart-8bc284ba-c645-4c23-8a24-f6ebad00e3ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979111413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.979111413
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2259000416
Short name T302
Test name
Test status
Simulation time 281960736 ps
CPU time 2.38 seconds
Started Jul 27 05:36:51 PM PDT 24
Finished Jul 27 05:36:54 PM PDT 24
Peak memory 206588 kb
Host smart-3b000894-5a26-4a85-8b42-4f7f85012ff0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259000416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2259000416
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2645702479
Short name T1071
Test name
Test status
Simulation time 49409462 ps
CPU time 1.87 seconds
Started Jul 27 05:36:59 PM PDT 24
Finished Jul 27 05:37:01 PM PDT 24
Peak memory 214824 kb
Host smart-3176df75-ab52-4e9c-af36-0ecc7f90f175
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645702479 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2645702479
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2822355641
Short name T273
Test name
Test status
Simulation time 11779708 ps
CPU time 0.9 seconds
Started Jul 27 05:37:03 PM PDT 24
Finished Jul 27 05:37:05 PM PDT 24
Peak memory 206372 kb
Host smart-789caa85-16dd-4d0a-ae23-c7c5a18ff102
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822355641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2822355641
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.4278565596
Short name T1113
Test name
Test status
Simulation time 11153624 ps
CPU time 0.84 seconds
Started Jul 27 05:37:02 PM PDT 24
Finished Jul 27 05:37:03 PM PDT 24
Peak memory 206376 kb
Host smart-688372ea-0ff9-4180-b8a8-2fef8b802277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278565596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4278565596
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3410138894
Short name T1031
Test name
Test status
Simulation time 26581787 ps
CPU time 1.2 seconds
Started Jul 27 05:37:00 PM PDT 24
Finished Jul 27 05:37:01 PM PDT 24
Peak memory 206472 kb
Host smart-784532d4-95a7-4699-a281-c55e52135e4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410138894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3410138894
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2130555586
Short name T1039
Test name
Test status
Simulation time 314187193 ps
CPU time 2.42 seconds
Started Jul 27 05:37:02 PM PDT 24
Finished Jul 27 05:37:04 PM PDT 24
Peak memory 214852 kb
Host smart-446327e5-da35-4bf5-b95a-a22052860a87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130555586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2130555586
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3496491757
Short name T1080
Test name
Test status
Simulation time 114886896 ps
CPU time 2.66 seconds
Started Jul 27 05:37:02 PM PDT 24
Finished Jul 27 05:37:05 PM PDT 24
Peak memory 206456 kb
Host smart-76ebffdf-2470-4919-a3c0-dbdfa35c6738
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496491757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3496491757
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.2460664277
Short name T658
Test name
Test status
Simulation time 17443630 ps
CPU time 0.85 seconds
Started Jul 27 05:55:38 PM PDT 24
Finished Jul 27 05:55:39 PM PDT 24
Peak memory 206632 kb
Host smart-ae7b45bb-ff00-4bb6-95e8-c1c13730eda8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460664277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2460664277
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.13447500
Short name T124
Test name
Test status
Simulation time 60006858 ps
CPU time 1.06 seconds
Started Jul 27 05:55:37 PM PDT 24
Finished Jul 27 05:55:38 PM PDT 24
Peak memory 216860 kb
Host smart-0632e21a-140a-4ca9-91f8-6b7a6db8c8eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13447500 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disa
ble_auto_req_mode.13447500
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2469329927
Short name T194
Test name
Test status
Simulation time 19684294 ps
CPU time 1.12 seconds
Started Jul 27 05:55:42 PM PDT 24
Finished Jul 27 05:55:44 PM PDT 24
Peak memory 223924 kb
Host smart-66b58c62-5893-4e9c-aa9d-6735c5a62765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469329927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2469329927
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.312217794
Short name T859
Test name
Test status
Simulation time 82888335 ps
CPU time 2.89 seconds
Started Jul 27 05:55:27 PM PDT 24
Finished Jul 27 05:55:30 PM PDT 24
Peak memory 219184 kb
Host smart-03fe18be-2ab8-46d5-b872-7defa5b68c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312217794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.312217794
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.41720935
Short name T454
Test name
Test status
Simulation time 28501202 ps
CPU time 0.94 seconds
Started Jul 27 05:55:26 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 215256 kb
Host smart-a2a0f22b-879e-4c07-ae0b-f613072292c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41720935 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.41720935
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3246161408
Short name T611
Test name
Test status
Simulation time 49085190 ps
CPU time 0.99 seconds
Started Jul 27 05:55:28 PM PDT 24
Finished Jul 27 05:55:29 PM PDT 24
Peak memory 206928 kb
Host smart-1350c9e1-8350-4645-8ac9-6578e608f882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246161408 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3246161408
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.1789650050
Short name T253
Test name
Test status
Simulation time 91531476 ps
CPU time 0.84 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 215120 kb
Host smart-7aa61e18-78eb-46e3-86cd-0b193d0163cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789650050 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1789650050
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3567405314
Short name T372
Test name
Test status
Simulation time 59317508 ps
CPU time 1.21 seconds
Started Jul 27 05:55:28 PM PDT 24
Finished Jul 27 05:55:29 PM PDT 24
Peak memory 217232 kb
Host smart-ed953c6b-01a5-4d42-af8b-8b24ec7d7d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567405314 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3567405314
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert_test.1030373225
Short name T906
Test name
Test status
Simulation time 43753135 ps
CPU time 1.39 seconds
Started Jul 27 05:55:42 PM PDT 24
Finished Jul 27 05:55:43 PM PDT 24
Peak memory 206828 kb
Host smart-a08be8b0-06da-4937-a342-d7138b840be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030373225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1030373225
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1386383559
Short name T370
Test name
Test status
Simulation time 31626479 ps
CPU time 0.85 seconds
Started Jul 27 05:55:36 PM PDT 24
Finished Jul 27 05:55:37 PM PDT 24
Peak memory 215800 kb
Host smart-7015b5a0-974c-4e7a-9c01-5f8f4f98782d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386383559 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1386383559
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.4207803037
Short name T192
Test name
Test status
Simulation time 18448467 ps
CPU time 1.17 seconds
Started Jul 27 05:55:33 PM PDT 24
Finished Jul 27 05:55:34 PM PDT 24
Peak memory 223888 kb
Host smart-8ca94871-56a5-4a70-b0f2-49a11cb82b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207803037 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.4207803037
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.1840841779
Short name T478
Test name
Test status
Simulation time 41931239 ps
CPU time 1.64 seconds
Started Jul 27 05:55:38 PM PDT 24
Finished Jul 27 05:55:40 PM PDT 24
Peak memory 217160 kb
Host smart-072debd9-cb71-40be-aabf-2c8cd6dfc8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840841779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1840841779
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2749351758
Short name T546
Test name
Test status
Simulation time 21405819 ps
CPU time 1.09 seconds
Started Jul 27 05:55:38 PM PDT 24
Finished Jul 27 05:55:39 PM PDT 24
Peak memory 215156 kb
Host smart-b1ff949f-b67c-4d97-8029-f5dee4341756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749351758 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2749351758
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3528210321
Short name T674
Test name
Test status
Simulation time 37303320 ps
CPU time 0.89 seconds
Started Jul 27 05:55:39 PM PDT 24
Finished Jul 27 05:55:40 PM PDT 24
Peak memory 206696 kb
Host smart-fb6fbf94-7900-4302-8826-ccb049ef972e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528210321 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3528210321
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.1295139752
Short name T814
Test name
Test status
Simulation time 22641885 ps
CPU time 0.92 seconds
Started Jul 27 05:55:33 PM PDT 24
Finished Jul 27 05:55:35 PM PDT 24
Peak memory 215144 kb
Host smart-138ee1ab-f4d5-47ec-a6b2-16757f404c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295139752 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1295139752
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2302543285
Short name T509
Test name
Test status
Simulation time 976075462 ps
CPU time 3.48 seconds
Started Jul 27 05:55:37 PM PDT 24
Finished Jul 27 05:55:41 PM PDT 24
Peak memory 217160 kb
Host smart-74d95a4b-1723-4dc4-ad30-ccd87d43cca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302543285 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2302543285
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.667455285
Short name T896
Test name
Test status
Simulation time 337377954335 ps
CPU time 898.3 seconds
Started Jul 27 05:55:42 PM PDT 24
Finished Jul 27 06:10:41 PM PDT 24
Peak memory 221372 kb
Host smart-98c3d462-ac68-44f1-a627-586911e7ddef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667455285 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.667455285
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.978081310
Short name T646
Test name
Test status
Simulation time 31543315 ps
CPU time 1.1 seconds
Started Jul 27 05:56:01 PM PDT 24
Finished Jul 27 05:56:03 PM PDT 24
Peak memory 218712 kb
Host smart-a6c354c1-7171-43b1-8aa5-92faa897ebf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978081310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.978081310
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.815688745
Short name T975
Test name
Test status
Simulation time 13978209 ps
CPU time 0.89 seconds
Started Jul 27 05:56:02 PM PDT 24
Finished Jul 27 05:56:03 PM PDT 24
Peak memory 214732 kb
Host smart-b9f484f4-3649-4a40-a01e-37a0747cf72c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815688745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.815688745
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.444981713
Short name T860
Test name
Test status
Simulation time 41934427 ps
CPU time 0.94 seconds
Started Jul 27 05:55:56 PM PDT 24
Finished Jul 27 05:55:57 PM PDT 24
Peak memory 216052 kb
Host smart-c8b4509a-0190-4694-b648-c60a27f8c8b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444981713 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.444981713
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_genbits.3185902862
Short name T517
Test name
Test status
Simulation time 48989117 ps
CPU time 1.32 seconds
Started Jul 27 05:55:58 PM PDT 24
Finished Jul 27 05:55:59 PM PDT 24
Peak memory 218696 kb
Host smart-db89f7fc-532b-4299-8d4b-683615a8e897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185902862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3185902862
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3034471165
Short name T45
Test name
Test status
Simulation time 21240516 ps
CPU time 1.16 seconds
Started Jul 27 05:55:57 PM PDT 24
Finished Jul 27 05:55:58 PM PDT 24
Peak memory 223888 kb
Host smart-760a8a26-b45d-425b-ade0-f6720bba94c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034471165 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3034471165
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1776249483
Short name T548
Test name
Test status
Simulation time 52139451 ps
CPU time 0.94 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:56 PM PDT 24
Peak memory 215132 kb
Host smart-12768f67-6772-47b8-a105-dcf1e0b95f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776249483 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1776249483
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1421795244
Short name T4
Test name
Test status
Simulation time 349737421 ps
CPU time 3.83 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:59 PM PDT 24
Peak memory 218260 kb
Host smart-1487d54d-9db4-4042-931f-d30c6d5a0497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421795244 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1421795244
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1522431490
Short name T234
Test name
Test status
Simulation time 38999802265 ps
CPU time 477.18 seconds
Started Jul 27 05:55:58 PM PDT 24
Finished Jul 27 06:03:56 PM PDT 24
Peak memory 217828 kb
Host smart-094bcbaa-a0b2-4282-b8ac-feca72287267
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522431490 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1522431490
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.468901298
Short name T724
Test name
Test status
Simulation time 94280413 ps
CPU time 1.26 seconds
Started Jul 27 05:57:19 PM PDT 24
Finished Jul 27 05:57:20 PM PDT 24
Peak memory 219336 kb
Host smart-5d06e460-4647-415f-bad5-3f1acf5b8605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468901298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.468901298
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.1503956125
Short name T745
Test name
Test status
Simulation time 32925772 ps
CPU time 1.22 seconds
Started Jul 27 05:57:17 PM PDT 24
Finished Jul 27 05:57:18 PM PDT 24
Peak memory 218540 kb
Host smart-9fb8e60d-63e2-4f3c-9531-7fd67e1978a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503956125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1503956125
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.4159832935
Short name T983
Test name
Test status
Simulation time 31155468 ps
CPU time 1.26 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 215540 kb
Host smart-eaf3f41a-e8dd-4e62-ab3c-96e81d57215f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159832935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.4159832935
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.885913850
Short name T419
Test name
Test status
Simulation time 30878869 ps
CPU time 0.99 seconds
Started Jul 27 05:57:21 PM PDT 24
Finished Jul 27 05:57:22 PM PDT 24
Peak memory 217216 kb
Host smart-fde67163-9be8-4e7d-861d-c2cf0970d2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885913850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.885913850
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.448824389
Short name T294
Test name
Test status
Simulation time 84770875 ps
CPU time 1.17 seconds
Started Jul 27 05:57:25 PM PDT 24
Finished Jul 27 05:57:26 PM PDT 24
Peak memory 219024 kb
Host smart-2f11d62f-4c47-49f0-906b-1a2160a479b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448824389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.448824389
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.3602502715
Short name T309
Test name
Test status
Simulation time 65799058 ps
CPU time 1.04 seconds
Started Jul 27 05:57:28 PM PDT 24
Finished Jul 27 05:57:29 PM PDT 24
Peak memory 217220 kb
Host smart-5d38dbe0-ac9f-4231-81a6-dae6783eb1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602502715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3602502715
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.208343094
Short name T588
Test name
Test status
Simulation time 25002792 ps
CPU time 1.25 seconds
Started Jul 27 05:57:24 PM PDT 24
Finished Jul 27 05:57:25 PM PDT 24
Peak memory 218652 kb
Host smart-dc5049e9-5275-4e18-a629-3c413d9e3840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208343094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.208343094
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.2814536871
Short name T474
Test name
Test status
Simulation time 64749073 ps
CPU time 1.56 seconds
Started Jul 27 05:57:27 PM PDT 24
Finished Jul 27 05:57:28 PM PDT 24
Peak memory 218548 kb
Host smart-df7ca518-6bad-428e-ad00-7c75e5586064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814536871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2814536871
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.2023263946
Short name T519
Test name
Test status
Simulation time 79514837 ps
CPU time 1.36 seconds
Started Jul 27 05:57:24 PM PDT 24
Finished Jul 27 05:57:25 PM PDT 24
Peak memory 217492 kb
Host smart-62033ed1-c84b-4c87-b36c-35019f1524ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023263946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2023263946
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.3982497420
Short name T342
Test name
Test status
Simulation time 49892547 ps
CPU time 1.2 seconds
Started Jul 27 05:57:27 PM PDT 24
Finished Jul 27 05:57:29 PM PDT 24
Peak memory 215512 kb
Host smart-bd560700-4705-4240-8f71-96c260f84a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982497420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.3982497420
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.3467937307
Short name T801
Test name
Test status
Simulation time 115826902 ps
CPU time 1.41 seconds
Started Jul 27 05:57:30 PM PDT 24
Finished Jul 27 05:57:32 PM PDT 24
Peak memory 218968 kb
Host smart-5dd672eb-899c-4794-b6d0-ced5c330a01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467937307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3467937307
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.1292065340
Short name T682
Test name
Test status
Simulation time 90066823 ps
CPU time 1.18 seconds
Started Jul 27 05:57:27 PM PDT 24
Finished Jul 27 05:57:28 PM PDT 24
Peak memory 219520 kb
Host smart-485e8993-5ca8-4953-b1af-580631168189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292065340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.1292065340
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.3725318885
Short name T460
Test name
Test status
Simulation time 50262318 ps
CPU time 1.3 seconds
Started Jul 27 05:57:29 PM PDT 24
Finished Jul 27 05:57:31 PM PDT 24
Peak memory 219912 kb
Host smart-86a8adf0-c0b1-4528-8ab9-3a52d858478b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725318885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3725318885
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.1392158300
Short name T369
Test name
Test status
Simulation time 60210022 ps
CPU time 1.07 seconds
Started Jul 27 05:57:27 PM PDT 24
Finished Jul 27 05:57:28 PM PDT 24
Peak memory 218304 kb
Host smart-c9a3d543-d5a2-4e41-a13c-bfa8ebe0c748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392158300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1392158300
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.2139226351
Short name T826
Test name
Test status
Simulation time 44602666 ps
CPU time 1.64 seconds
Started Jul 27 05:57:27 PM PDT 24
Finished Jul 27 05:57:29 PM PDT 24
Peak memory 219908 kb
Host smart-909ae039-a96e-4429-a592-b52946a5195a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139226351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2139226351
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.333521007
Short name T722
Test name
Test status
Simulation time 83724512 ps
CPU time 1.38 seconds
Started Jul 27 05:57:28 PM PDT 24
Finished Jul 27 05:57:29 PM PDT 24
Peak memory 218816 kb
Host smart-c08521d0-5411-41e2-9dea-35a4bb9ac664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333521007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.333521007
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.4097378817
Short name T619
Test name
Test status
Simulation time 28623587 ps
CPU time 1.27 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:57 PM PDT 24
Peak memory 218396 kb
Host smart-71787cfa-ace4-4e20-9612-26dfaa6a2c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097378817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.4097378817
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.280762213
Short name T625
Test name
Test status
Simulation time 13091789 ps
CPU time 0.89 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:56 PM PDT 24
Peak memory 215032 kb
Host smart-6e25952b-56ff-4d21-b674-efea5f7b017e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280762213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.280762213
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3990148936
Short name T118
Test name
Test status
Simulation time 27369035 ps
CPU time 0.82 seconds
Started Jul 27 05:55:57 PM PDT 24
Finished Jul 27 05:55:58 PM PDT 24
Peak memory 216176 kb
Host smart-d8e4d079-4dde-4713-93bf-d39714074f96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990148936 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3990148936
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2283054949
Short name T712
Test name
Test status
Simulation time 109900253 ps
CPU time 1.03 seconds
Started Jul 27 05:56:01 PM PDT 24
Finished Jul 27 05:56:02 PM PDT 24
Peak memory 218208 kb
Host smart-586ad2a5-08b2-4af4-b0de-947a0b7a1829
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283054949 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2283054949
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.4064650867
Short name T656
Test name
Test status
Simulation time 55302221 ps
CPU time 1.04 seconds
Started Jul 27 05:55:58 PM PDT 24
Finished Jul 27 05:55:59 PM PDT 24
Peak memory 220780 kb
Host smart-d57a1490-8ca4-4cdc-b7b9-c4002c6ab8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064650867 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.4064650867
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2767020606
Short name T597
Test name
Test status
Simulation time 68511509 ps
CPU time 1.12 seconds
Started Jul 27 05:56:01 PM PDT 24
Finished Jul 27 05:56:02 PM PDT 24
Peak memory 217204 kb
Host smart-f40905fc-1b00-4b58-80f6-1d044fc22367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767020606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2767020606
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.4161849630
Short name T876
Test name
Test status
Simulation time 34229036 ps
CPU time 0.98 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:57 PM PDT 24
Peak memory 215680 kb
Host smart-83c7b205-d2c8-4f6d-a416-d0757f3f305e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161849630 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.4161849630
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.452085265
Short name T248
Test name
Test status
Simulation time 46301317 ps
CPU time 0.95 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:57 PM PDT 24
Peak memory 215184 kb
Host smart-3bb61cf6-31e4-49e8-8c5d-dfc2f059ee7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452085265 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.452085265
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.348385178
Short name T496
Test name
Test status
Simulation time 273784455 ps
CPU time 3.12 seconds
Started Jul 27 05:55:56 PM PDT 24
Finished Jul 27 05:55:59 PM PDT 24
Peak memory 215176 kb
Host smart-5cee6f70-26a3-45ed-acb5-90f62431537b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348385178 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.348385178
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2879769034
Short name T961
Test name
Test status
Simulation time 273187563085 ps
CPU time 815.58 seconds
Started Jul 27 05:55:59 PM PDT 24
Finished Jul 27 06:09:35 PM PDT 24
Peak memory 221612 kb
Host smart-217c1480-7ded-4782-bcc6-a30717e2b8b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879769034 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2879769034
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.2599157248
Short name T623
Test name
Test status
Simulation time 66915603 ps
CPU time 1.27 seconds
Started Jul 27 05:57:30 PM PDT 24
Finished Jul 27 05:57:31 PM PDT 24
Peak memory 215540 kb
Host smart-a281511e-71e7-4279-a55b-e12f31d85f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599157248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2599157248
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/111.edn_alert.1792678214
Short name T598
Test name
Test status
Simulation time 26024167 ps
CPU time 1.22 seconds
Started Jul 27 05:57:26 PM PDT 24
Finished Jul 27 05:57:28 PM PDT 24
Peak memory 220928 kb
Host smart-50f41ac8-b48e-4ed3-bd9d-bf70747a1973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792678214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.1792678214
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/112.edn_alert.176788601
Short name T568
Test name
Test status
Simulation time 49758167 ps
CPU time 1.2 seconds
Started Jul 27 05:57:24 PM PDT 24
Finished Jul 27 05:57:26 PM PDT 24
Peak memory 218376 kb
Host smart-2e71695d-25ac-406e-b41d-af5c1e14f531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176788601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.176788601
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3107103841
Short name T923
Test name
Test status
Simulation time 67875065 ps
CPU time 1.6 seconds
Started Jul 27 05:57:30 PM PDT 24
Finished Jul 27 05:57:32 PM PDT 24
Peak memory 220056 kb
Host smart-0daac139-ca63-4147-ab08-12f128a59eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107103841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3107103841
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2428133652
Short name T863
Test name
Test status
Simulation time 24855514 ps
CPU time 1.13 seconds
Started Jul 27 05:57:27 PM PDT 24
Finished Jul 27 05:57:28 PM PDT 24
Peak memory 220548 kb
Host smart-e695e2b2-9c8c-4236-84b7-cf5c8c38eeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428133652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2428133652
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.169013332
Short name T736
Test name
Test status
Simulation time 60882712 ps
CPU time 1.65 seconds
Started Jul 27 05:57:26 PM PDT 24
Finished Jul 27 05:57:28 PM PDT 24
Peak memory 218688 kb
Host smart-eae8a12b-11d5-4231-b781-3048b0e5c4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169013332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.169013332
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.3762856790
Short name T976
Test name
Test status
Simulation time 73262614 ps
CPU time 1.08 seconds
Started Jul 27 05:57:29 PM PDT 24
Finished Jul 27 05:57:31 PM PDT 24
Peak memory 218616 kb
Host smart-f97af895-15fd-49d4-88b0-3f91e86971d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762856790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3762856790
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.1031429322
Short name T832
Test name
Test status
Simulation time 39246658 ps
CPU time 1.48 seconds
Started Jul 27 05:57:27 PM PDT 24
Finished Jul 27 05:57:28 PM PDT 24
Peak memory 215192 kb
Host smart-54585726-ceb9-4726-ade5-d6a7d5e9a894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031429322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1031429322
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.526223296
Short name T415
Test name
Test status
Simulation time 43990208 ps
CPU time 1.19 seconds
Started Jul 27 05:57:26 PM PDT 24
Finished Jul 27 05:57:27 PM PDT 24
Peak memory 219196 kb
Host smart-d98d1e29-990b-4d7c-aed8-9310f88e291b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526223296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.526223296
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3638576190
Short name T315
Test name
Test status
Simulation time 81382073 ps
CPU time 1.16 seconds
Started Jul 27 05:57:28 PM PDT 24
Finished Jul 27 05:57:29 PM PDT 24
Peak memory 218928 kb
Host smart-4e9a0255-abf4-470a-b066-0f28aeeddaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638576190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3638576190
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.4168622785
Short name T891
Test name
Test status
Simulation time 87702562 ps
CPU time 1.13 seconds
Started Jul 27 05:57:27 PM PDT 24
Finished Jul 27 05:57:28 PM PDT 24
Peak memory 218336 kb
Host smart-c97fa2ab-49b9-4f46-a41a-7a7ad6fbc862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168622785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.4168622785
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.2126178832
Short name T366
Test name
Test status
Simulation time 39291543 ps
CPU time 1.44 seconds
Started Jul 27 05:57:27 PM PDT 24
Finished Jul 27 05:57:29 PM PDT 24
Peak memory 218468 kb
Host smart-96656e6c-cd59-4e7e-8118-4b068d3ff4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126178832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2126178832
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1336815786
Short name T259
Test name
Test status
Simulation time 87459319 ps
CPU time 1.21 seconds
Started Jul 27 05:57:33 PM PDT 24
Finished Jul 27 05:57:34 PM PDT 24
Peak memory 218172 kb
Host smart-ebe8375b-712b-43a1-9716-8e9f77508f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336815786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1336815786
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.12391809
Short name T747
Test name
Test status
Simulation time 125584490 ps
CPU time 2.51 seconds
Started Jul 27 05:57:22 PM PDT 24
Finished Jul 27 05:57:24 PM PDT 24
Peak memory 219852 kb
Host smart-e2302af7-e2e9-47c1-8295-eafa18d95088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12391809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.12391809
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.2629984898
Short name T613
Test name
Test status
Simulation time 36068330 ps
CPU time 1.23 seconds
Started Jul 27 05:57:43 PM PDT 24
Finished Jul 27 05:57:44 PM PDT 24
Peak memory 218376 kb
Host smart-c058104e-3145-40ff-918c-28722bd87aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629984898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.2629984898
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.2144766225
Short name T928
Test name
Test status
Simulation time 104533660 ps
CPU time 1.37 seconds
Started Jul 27 05:57:28 PM PDT 24
Finished Jul 27 05:57:30 PM PDT 24
Peak memory 219812 kb
Host smart-ee3821d5-7372-455b-913c-ebd416b9545f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144766225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2144766225
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1854549773
Short name T966
Test name
Test status
Simulation time 23729627 ps
CPU time 1.16 seconds
Started Jul 27 05:57:23 PM PDT 24
Finished Jul 27 05:57:25 PM PDT 24
Peak memory 218980 kb
Host smart-ad456ef9-0398-448a-ad05-fba2f1f8a350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854549773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1854549773
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.59658864
Short name T726
Test name
Test status
Simulation time 127466044 ps
CPU time 1.62 seconds
Started Jul 27 05:57:27 PM PDT 24
Finished Jul 27 05:57:29 PM PDT 24
Peak memory 219948 kb
Host smart-070461da-7ee7-442e-9154-17bb0c96ad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59658864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.59658864
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1215154695
Short name T291
Test name
Test status
Simulation time 120120298 ps
CPU time 1.04 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:56 PM PDT 24
Peak memory 220492 kb
Host smart-5392d48b-9f0e-43a3-91c4-6222163f0b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215154695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1215154695
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.391519820
Short name T494
Test name
Test status
Simulation time 66925651 ps
CPU time 0.89 seconds
Started Jul 27 05:56:05 PM PDT 24
Finished Jul 27 05:56:06 PM PDT 24
Peak memory 214820 kb
Host smart-9c89dfb4-acee-4961-ab4b-751b48e14982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391519820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.391519820
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2658623678
Short name T708
Test name
Test status
Simulation time 20565838 ps
CPU time 0.86 seconds
Started Jul 27 05:55:58 PM PDT 24
Finished Jul 27 05:55:59 PM PDT 24
Peak memory 216100 kb
Host smart-2bea4b34-a2e3-46d0-9cd8-030a926812d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658623678 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2658623678
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_genbits.2020912171
Short name T14
Test name
Test status
Simulation time 48311985 ps
CPU time 1.25 seconds
Started Jul 27 05:55:59 PM PDT 24
Finished Jul 27 05:56:01 PM PDT 24
Peak memory 218452 kb
Host smart-ca9cfc2c-7929-441f-af8b-499fbbff84d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020912171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2020912171
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1246083126
Short name T931
Test name
Test status
Simulation time 24615277 ps
CPU time 0.94 seconds
Started Jul 27 05:55:56 PM PDT 24
Finished Jul 27 05:55:57 PM PDT 24
Peak memory 215484 kb
Host smart-8d6d3e11-e76b-46c9-943e-da1b28e8fe8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246083126 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1246083126
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2703249093
Short name T586
Test name
Test status
Simulation time 25950456 ps
CPU time 0.97 seconds
Started Jul 27 05:55:57 PM PDT 24
Finished Jul 27 05:55:58 PM PDT 24
Peak memory 215176 kb
Host smart-e7e4350a-a130-42d3-b00b-3617f94e43cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703249093 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2703249093
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.792228765
Short name T770
Test name
Test status
Simulation time 224396283 ps
CPU time 4.95 seconds
Started Jul 27 05:55:57 PM PDT 24
Finished Jul 27 05:56:02 PM PDT 24
Peak memory 218472 kb
Host smart-76243c1a-0729-472b-a8b6-97b120415a89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792228765 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.792228765
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/120.edn_alert.2647105156
Short name T158
Test name
Test status
Simulation time 31252565 ps
CPU time 1.35 seconds
Started Jul 27 05:57:26 PM PDT 24
Finished Jul 27 05:57:28 PM PDT 24
Peak memory 220084 kb
Host smart-ecc3e458-a494-4037-8596-e5f6048ce826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647105156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.2647105156
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.2008174768
Short name T886
Test name
Test status
Simulation time 54415899 ps
CPU time 1.09 seconds
Started Jul 27 05:57:46 PM PDT 24
Finished Jul 27 05:57:47 PM PDT 24
Peak memory 219696 kb
Host smart-6dc45794-2dba-48ac-babd-5d56ce279efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008174768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2008174768
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.4170041580
Short name T551
Test name
Test status
Simulation time 59323978 ps
CPU time 1.63 seconds
Started Jul 27 05:57:34 PM PDT 24
Finished Jul 27 05:57:36 PM PDT 24
Peak memory 218796 kb
Host smart-c8593daa-e0c1-41ad-81ea-f8d34c96f0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170041580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.4170041580
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.1824377132
Short name T767
Test name
Test status
Simulation time 46173740 ps
CPU time 1.2 seconds
Started Jul 27 05:57:25 PM PDT 24
Finished Jul 27 05:57:26 PM PDT 24
Peak memory 219748 kb
Host smart-d83c1800-c388-4a4f-af86-217c154d16a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824377132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1824377132
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.660656563
Short name T367
Test name
Test status
Simulation time 65775769 ps
CPU time 1.06 seconds
Started Jul 27 05:57:30 PM PDT 24
Finished Jul 27 05:57:31 PM PDT 24
Peak memory 217236 kb
Host smart-b919a814-eee4-4940-8604-75a198d1b89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660656563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.660656563
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2601595361
Short name T696
Test name
Test status
Simulation time 45513114 ps
CPU time 1.16 seconds
Started Jul 27 05:57:30 PM PDT 24
Finished Jul 27 05:57:31 PM PDT 24
Peak memory 219268 kb
Host smart-9e7ad4e2-88ae-4bd4-a34c-7ee96fd3446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601595361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2601595361
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2835202576
Short name T717
Test name
Test status
Simulation time 32768055 ps
CPU time 1.08 seconds
Started Jul 27 05:57:42 PM PDT 24
Finished Jul 27 05:57:44 PM PDT 24
Peak memory 218808 kb
Host smart-f61a4074-9ab4-4585-b435-940aa637d8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835202576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2835202576
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/125.edn_alert.2387119729
Short name T756
Test name
Test status
Simulation time 44066988 ps
CPU time 1.21 seconds
Started Jul 27 05:57:43 PM PDT 24
Finished Jul 27 05:57:44 PM PDT 24
Peak memory 218556 kb
Host smart-08e0bfda-493b-44cc-a542-4c75e1d57f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387119729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2387119729
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.2698422479
Short name T873
Test name
Test status
Simulation time 39914495 ps
CPU time 1.25 seconds
Started Jul 27 05:57:53 PM PDT 24
Finished Jul 27 05:57:54 PM PDT 24
Peak memory 218592 kb
Host smart-bba807a7-396a-4f29-b328-3adf72b43c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698422479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2698422479
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.4058631406
Short name T641
Test name
Test status
Simulation time 25575052 ps
CPU time 1.21 seconds
Started Jul 27 05:57:35 PM PDT 24
Finished Jul 27 05:57:36 PM PDT 24
Peak memory 220780 kb
Host smart-161a3329-3dc8-49db-86dd-51ce51a0c5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058631406 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.4058631406
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.1224490593
Short name T778
Test name
Test status
Simulation time 69384453 ps
CPU time 1.04 seconds
Started Jul 27 05:57:45 PM PDT 24
Finished Jul 27 05:57:46 PM PDT 24
Peak memory 219056 kb
Host smart-3d482fac-ef85-490a-9ee4-8a4e34390af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224490593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1224490593
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.307445222
Short name T777
Test name
Test status
Simulation time 78025151 ps
CPU time 1.16 seconds
Started Jul 27 05:57:34 PM PDT 24
Finished Jul 27 05:57:35 PM PDT 24
Peak memory 219300 kb
Host smart-eb105ef2-8253-43ae-b0b8-1ebbf7f9cdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307445222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.307445222
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.2137267000
Short name T627
Test name
Test status
Simulation time 119333844 ps
CPU time 1.64 seconds
Started Jul 27 05:57:30 PM PDT 24
Finished Jul 27 05:57:32 PM PDT 24
Peak memory 218884 kb
Host smart-f3d4f463-dc12-477d-8147-759431ed0b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137267000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2137267000
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2486802786
Short name T224
Test name
Test status
Simulation time 25542081 ps
CPU time 1.22 seconds
Started Jul 27 05:57:29 PM PDT 24
Finished Jul 27 05:57:30 PM PDT 24
Peak memory 219704 kb
Host smart-59d29320-c97a-41f7-b8b6-bf7ffb68f832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486802786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2486802786
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.3385454888
Short name T917
Test name
Test status
Simulation time 57301172 ps
CPU time 0.98 seconds
Started Jul 27 05:57:36 PM PDT 24
Finished Jul 27 05:57:37 PM PDT 24
Peak memory 217236 kb
Host smart-526c9517-7f3f-4e33-a000-623945d12c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385454888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3385454888
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.3865164838
Short name T661
Test name
Test status
Simulation time 190245362 ps
CPU time 1.28 seconds
Started Jul 27 05:57:41 PM PDT 24
Finished Jul 27 05:57:42 PM PDT 24
Peak memory 218308 kb
Host smart-7725e7b9-0a24-4d9c-928c-7464128ff68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865164838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3865164838
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.1463745440
Short name T894
Test name
Test status
Simulation time 57804782 ps
CPU time 1.09 seconds
Started Jul 27 05:57:48 PM PDT 24
Finished Jul 27 05:57:49 PM PDT 24
Peak memory 217268 kb
Host smart-d73a45a0-76d4-4954-bcdd-5cb88b9d7661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463745440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1463745440
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.4184036310
Short name T69
Test name
Test status
Simulation time 46505171 ps
CPU time 1.25 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:12 PM PDT 24
Peak memory 220620 kb
Host smart-c83154f3-797e-4e01-80c0-c64bd6f620ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184036310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.4184036310
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2092807658
Short name T952
Test name
Test status
Simulation time 98957831 ps
CPU time 0.81 seconds
Started Jul 27 05:56:04 PM PDT 24
Finished Jul 27 05:56:05 PM PDT 24
Peak memory 206592 kb
Host smart-54f53556-2673-41e6-ada0-dbef82961da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092807658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2092807658
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_err.752635656
Short name T558
Test name
Test status
Simulation time 55103709 ps
CPU time 1.14 seconds
Started Jul 27 05:56:06 PM PDT 24
Finished Jul 27 05:56:07 PM PDT 24
Peak memory 219504 kb
Host smart-7e661812-7f9d-4ce9-8496-f70a3da00169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752635656 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.752635656
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2289872916
Short name T748
Test name
Test status
Simulation time 34240675 ps
CPU time 1.25 seconds
Started Jul 27 05:56:05 PM PDT 24
Finished Jul 27 05:56:06 PM PDT 24
Peak memory 217052 kb
Host smart-00b0712b-ab72-4b0a-b6fb-04409344cd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289872916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2289872916
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.4152990922
Short name T739
Test name
Test status
Simulation time 25970471 ps
CPU time 1 seconds
Started Jul 27 05:56:02 PM PDT 24
Finished Jul 27 05:56:03 PM PDT 24
Peak memory 223872 kb
Host smart-7666e4f0-fc51-4a3e-b933-3872d2823fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152990922 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.4152990922
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.630113100
Short name T591
Test name
Test status
Simulation time 15490052 ps
CPU time 0.99 seconds
Started Jul 27 05:56:05 PM PDT 24
Finished Jul 27 05:56:06 PM PDT 24
Peak memory 215100 kb
Host smart-63fa2691-67b6-40c5-a361-7f67cdbbe2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630113100 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.630113100
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2331990066
Short name T245
Test name
Test status
Simulation time 105600285 ps
CPU time 1.57 seconds
Started Jul 27 05:56:08 PM PDT 24
Finished Jul 27 05:56:09 PM PDT 24
Peak memory 215160 kb
Host smart-2b04a880-5438-4f83-a497-ff22d1e0244c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331990066 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2331990066
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1447805256
Short name T538
Test name
Test status
Simulation time 32879908431 ps
CPU time 885.15 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 06:10:55 PM PDT 24
Peak memory 219500 kb
Host smart-b366cd76-f517-4190-8879-1aa881c6cbf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447805256 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1447805256
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2241310580
Short name T451
Test name
Test status
Simulation time 26778785 ps
CPU time 1.18 seconds
Started Jul 27 05:57:33 PM PDT 24
Finished Jul 27 05:57:35 PM PDT 24
Peak memory 218604 kb
Host smart-85e83e3f-af09-4a6f-b984-2d1632c632f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241310580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2241310580
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.4135334113
Short name T1
Test name
Test status
Simulation time 46370433 ps
CPU time 1.47 seconds
Started Jul 27 05:57:29 PM PDT 24
Finished Jul 27 05:57:30 PM PDT 24
Peak memory 215176 kb
Host smart-d2d8e4f7-beaf-4362-b465-e0cb41f5c294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135334113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.4135334113
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.27396667
Short name T481
Test name
Test status
Simulation time 57416778 ps
CPU time 1.28 seconds
Started Jul 27 05:57:46 PM PDT 24
Finished Jul 27 05:57:47 PM PDT 24
Peak memory 215528 kb
Host smart-e37e76bd-ee76-4a4d-90ae-51ffcbc43e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27396667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.27396667
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.778825347
Short name T288
Test name
Test status
Simulation time 43313969 ps
CPU time 1.42 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 215228 kb
Host smart-14961b88-d60b-4e4f-bb56-30e122a052a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778825347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.778825347
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.1123121958
Short name T138
Test name
Test status
Simulation time 112063604 ps
CPU time 1.29 seconds
Started Jul 27 05:57:45 PM PDT 24
Finished Jul 27 05:57:46 PM PDT 24
Peak memory 215500 kb
Host smart-19b9c6e9-466a-436c-9713-990db2117d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123121958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1123121958
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.669314486
Short name T849
Test name
Test status
Simulation time 45399353 ps
CPU time 1.55 seconds
Started Jul 27 05:57:30 PM PDT 24
Finished Jul 27 05:57:32 PM PDT 24
Peak memory 218276 kb
Host smart-0142fc0f-1a76-4347-b057-d5e9d1228ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669314486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.669314486
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.2992825746
Short name T660
Test name
Test status
Simulation time 36269391 ps
CPU time 1.07 seconds
Started Jul 27 05:57:50 PM PDT 24
Finished Jul 27 05:57:51 PM PDT 24
Peak memory 219576 kb
Host smart-20b940ba-33d7-49e5-ac69-c70b71c5f118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992825746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2992825746
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.283987651
Short name T84
Test name
Test status
Simulation time 72015307 ps
CPU time 1.39 seconds
Started Jul 27 05:57:34 PM PDT 24
Finished Jul 27 05:57:35 PM PDT 24
Peak memory 219588 kb
Host smart-e8dd03e0-4ddb-49f9-9e1b-6a7d111dcb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283987651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.283987651
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.3979152510
Short name T583
Test name
Test status
Simulation time 23029561 ps
CPU time 1.21 seconds
Started Jul 27 05:57:32 PM PDT 24
Finished Jul 27 05:57:34 PM PDT 24
Peak memory 218448 kb
Host smart-9c9ed2bf-694c-4bac-b1e5-f696a7550124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979152510 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.3979152510
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.2356949297
Short name T785
Test name
Test status
Simulation time 28813420 ps
CPU time 1.29 seconds
Started Jul 27 05:57:33 PM PDT 24
Finished Jul 27 05:57:34 PM PDT 24
Peak memory 217228 kb
Host smart-3eb43730-d3f2-4c3f-a08f-580abc83435c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356949297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2356949297
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.528961797
Short name T533
Test name
Test status
Simulation time 49802832 ps
CPU time 1.24 seconds
Started Jul 27 05:57:33 PM PDT 24
Finished Jul 27 05:57:34 PM PDT 24
Peak memory 219496 kb
Host smart-6ae6a5c2-e2b8-496f-a6f0-fa0ede9a0ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528961797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.528961797
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.3697416326
Short name T495
Test name
Test status
Simulation time 52052873 ps
CPU time 1.12 seconds
Started Jul 27 05:57:37 PM PDT 24
Finished Jul 27 05:57:39 PM PDT 24
Peak memory 217224 kb
Host smart-4128cde2-9cfe-4adc-97d1-9e296aca2163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697416326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3697416326
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.4075290126
Short name T854
Test name
Test status
Simulation time 72748365 ps
CPU time 1.07 seconds
Started Jul 27 05:57:39 PM PDT 24
Finished Jul 27 05:57:40 PM PDT 24
Peak memory 219852 kb
Host smart-128755a4-7900-416c-a5c5-3e312f28e38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075290126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.4075290126
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.573411055
Short name T665
Test name
Test status
Simulation time 65247449 ps
CPU time 1.13 seconds
Started Jul 27 05:57:31 PM PDT 24
Finished Jul 27 05:57:33 PM PDT 24
Peak memory 219896 kb
Host smart-b1b49436-4f98-4acb-a3f2-d42ccaf37461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573411055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.573411055
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.1205922924
Short name T772
Test name
Test status
Simulation time 29738891 ps
CPU time 1.24 seconds
Started Jul 27 05:57:35 PM PDT 24
Finished Jul 27 05:57:36 PM PDT 24
Peak memory 219524 kb
Host smart-85a3564c-be64-40a1-9a97-acb1a9489389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205922924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1205922924
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.3001468195
Short name T953
Test name
Test status
Simulation time 34585482 ps
CPU time 1.39 seconds
Started Jul 27 05:57:48 PM PDT 24
Finished Jul 27 05:57:50 PM PDT 24
Peak memory 218408 kb
Host smart-00b947d8-3efc-4a01-bd79-99c1c2b728ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001468195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3001468195
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.3238152612
Short name T958
Test name
Test status
Simulation time 147198350 ps
CPU time 1.09 seconds
Started Jul 27 05:57:40 PM PDT 24
Finished Jul 27 05:57:41 PM PDT 24
Peak memory 218600 kb
Host smart-1cab2ba5-ceb1-45d8-8d13-366d64e61b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238152612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3238152612
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.3107498842
Short name T555
Test name
Test status
Simulation time 33018451 ps
CPU time 1.24 seconds
Started Jul 27 05:57:35 PM PDT 24
Finished Jul 27 05:57:36 PM PDT 24
Peak memory 219816 kb
Host smart-6f30e7c2-809a-4320-8702-56ace040f1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107498842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3107498842
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.1336488544
Short name T508
Test name
Test status
Simulation time 44605325 ps
CPU time 1.12 seconds
Started Jul 27 05:57:47 PM PDT 24
Finished Jul 27 05:57:48 PM PDT 24
Peak memory 218168 kb
Host smart-2162e453-c20c-4fc2-8185-0921ce3f2cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336488544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1336488544
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.1607365306
Short name T249
Test name
Test status
Simulation time 47484713 ps
CPU time 1.12 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 218440 kb
Host smart-407b94a6-6b3b-49b0-bb97-a2d1e5b1c36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607365306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1607365306
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.4185430370
Short name T410
Test name
Test status
Simulation time 21015356 ps
CPU time 1.17 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:12 PM PDT 24
Peak memory 219476 kb
Host smart-ce7eee2b-1c90-40e1-a7ca-c9a6d2aa7c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185430370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.4185430370
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.709524800
Short name T512
Test name
Test status
Simulation time 61775821 ps
CPU time 1.06 seconds
Started Jul 27 05:56:03 PM PDT 24
Finished Jul 27 05:56:04 PM PDT 24
Peak memory 206700 kb
Host smart-7e0057fa-0a7a-4cda-b3ff-96b25775ce5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709524800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.709524800
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3073414974
Short name T400
Test name
Test status
Simulation time 38592796 ps
CPU time 0.88 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 215764 kb
Host smart-49d37599-9387-4518-b363-e18a208040f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073414974 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3073414974
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2148631265
Short name T21
Test name
Test status
Simulation time 126217840 ps
CPU time 1.16 seconds
Started Jul 27 05:56:01 PM PDT 24
Finished Jul 27 05:56:03 PM PDT 24
Peak memory 215604 kb
Host smart-e289f6ca-aa5a-4e0a-b9a0-1e59580095be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148631265 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2148631265
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_genbits.2658292066
Short name T325
Test name
Test status
Simulation time 56651873 ps
CPU time 2 seconds
Started Jul 27 05:56:03 PM PDT 24
Finished Jul 27 05:56:05 PM PDT 24
Peak memory 220064 kb
Host smart-5ef70cda-0a3e-4ee9-8425-a3ad38f26c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658292066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2658292066
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3505112573
Short name T734
Test name
Test status
Simulation time 27608650 ps
CPU time 0.96 seconds
Started Jul 27 05:56:04 PM PDT 24
Finished Jul 27 05:56:05 PM PDT 24
Peak memory 215276 kb
Host smart-ca4052eb-6cce-453b-9406-6cc49035ba61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505112573 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3505112573
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1643233206
Short name T800
Test name
Test status
Simulation time 27231222 ps
CPU time 0.95 seconds
Started Jul 27 05:56:04 PM PDT 24
Finished Jul 27 05:56:05 PM PDT 24
Peak memory 215156 kb
Host smart-b55fb9e9-1a92-4c72-97ad-f45f68a8876e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643233206 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1643233206
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/140.edn_alert.49690363
Short name T848
Test name
Test status
Simulation time 101960280 ps
CPU time 1.12 seconds
Started Jul 27 05:57:40 PM PDT 24
Finished Jul 27 05:57:42 PM PDT 24
Peak memory 220284 kb
Host smart-1bee3189-07d6-4b02-aa16-0e949e91038a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49690363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.49690363
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3630912772
Short name T842
Test name
Test status
Simulation time 61325069 ps
CPU time 1.45 seconds
Started Jul 27 05:57:29 PM PDT 24
Finished Jul 27 05:57:36 PM PDT 24
Peak memory 218560 kb
Host smart-ebf9b404-383d-45b1-a6b3-c85d4ba4203c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630912772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3630912772
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.2179588017
Short name T561
Test name
Test status
Simulation time 109160965 ps
CPU time 1.24 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 218356 kb
Host smart-9928515c-116a-4095-899d-bad9e1c83c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179588017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2179588017
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.356244981
Short name T219
Test name
Test status
Simulation time 89096159 ps
CPU time 1.18 seconds
Started Jul 27 05:57:32 PM PDT 24
Finished Jul 27 05:57:34 PM PDT 24
Peak memory 221632 kb
Host smart-604c8ec1-cf53-47a5-bfd3-39d694b185f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356244981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.356244981
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.3440273010
Short name T890
Test name
Test status
Simulation time 48977815 ps
CPU time 1.37 seconds
Started Jul 27 05:57:38 PM PDT 24
Finished Jul 27 05:57:39 PM PDT 24
Peak memory 218368 kb
Host smart-273f1bb3-641b-4b2a-bf6c-861d38f2d68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440273010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3440273010
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.3996140851
Short name T582
Test name
Test status
Simulation time 24241743 ps
CPU time 1.17 seconds
Started Jul 27 05:57:52 PM PDT 24
Finished Jul 27 05:57:53 PM PDT 24
Peak memory 219644 kb
Host smart-22360834-92ee-448b-bf34-4931f5393b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996140851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.3996140851
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.3176780311
Short name T428
Test name
Test status
Simulation time 33021887 ps
CPU time 1.33 seconds
Started Jul 27 05:57:36 PM PDT 24
Finished Jul 27 05:57:38 PM PDT 24
Peak memory 218200 kb
Host smart-29bdb555-95e4-4c4c-a77b-4a243ab62fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176780311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3176780311
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3881133758
Short name T628
Test name
Test status
Simulation time 45156253 ps
CPU time 1.6 seconds
Started Jul 27 05:57:37 PM PDT 24
Finished Jul 27 05:57:39 PM PDT 24
Peak memory 219800 kb
Host smart-ad90ad96-ea29-41a1-946f-651ad5340f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881133758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3881133758
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.3602115273
Short name T587
Test name
Test status
Simulation time 84899127 ps
CPU time 1.12 seconds
Started Jul 27 05:57:38 PM PDT 24
Finished Jul 27 05:57:39 PM PDT 24
Peak memory 219648 kb
Host smart-6fe8f8a7-4a3a-44dd-af5d-96b608cb7cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602115273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3602115273
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/146.edn_alert.775491537
Short name T485
Test name
Test status
Simulation time 295506859 ps
CPU time 1.26 seconds
Started Jul 27 05:57:57 PM PDT 24
Finished Jul 27 05:57:58 PM PDT 24
Peak memory 218336 kb
Host smart-255a8257-1dfc-4a69-96b7-4dd29689aa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775491537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.775491537
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2719694522
Short name T468
Test name
Test status
Simulation time 88890096 ps
CPU time 1.28 seconds
Started Jul 27 05:57:39 PM PDT 24
Finished Jul 27 05:57:46 PM PDT 24
Peak memory 218772 kb
Host smart-c9c05612-2d96-47d1-973d-39999e625578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719694522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2719694522
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3897208256
Short name T90
Test name
Test status
Simulation time 220196187 ps
CPU time 3.03 seconds
Started Jul 27 05:57:56 PM PDT 24
Finished Jul 27 05:57:59 PM PDT 24
Peak memory 220032 kb
Host smart-c244f919-fdbd-4123-9edd-f52f8ec8c911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897208256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3897208256
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.1535923952
Short name T594
Test name
Test status
Simulation time 48611388 ps
CPU time 1.2 seconds
Started Jul 27 05:57:35 PM PDT 24
Finished Jul 27 05:57:36 PM PDT 24
Peak memory 220128 kb
Host smart-87d6748b-6686-4a2a-8024-0735b09d0a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535923952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1535923952
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.2409514813
Short name T63
Test name
Test status
Simulation time 142298467 ps
CPU time 2.53 seconds
Started Jul 27 05:57:36 PM PDT 24
Finished Jul 27 05:57:38 PM PDT 24
Peak memory 218528 kb
Host smart-7d5e00b8-d55a-4340-b211-030779b9099c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409514813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2409514813
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.1840680593
Short name T164
Test name
Test status
Simulation time 161732799 ps
CPU time 1.26 seconds
Started Jul 27 05:57:53 PM PDT 24
Finished Jul 27 05:57:54 PM PDT 24
Peak memory 218544 kb
Host smart-217a70e0-e3c4-4afe-a3e0-61fdeabff180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840680593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1840680593
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.2542853072
Short name T702
Test name
Test status
Simulation time 127307581 ps
CPU time 2.66 seconds
Started Jul 27 05:57:48 PM PDT 24
Finished Jul 27 05:57:51 PM PDT 24
Peak memory 218520 kb
Host smart-e31f7eba-ef2b-472f-b45b-8bf6966460e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542853072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2542853072
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.71519373
Short name T681
Test name
Test status
Simulation time 76121684 ps
CPU time 1.18 seconds
Started Jul 27 05:56:04 PM PDT 24
Finished Jul 27 05:56:06 PM PDT 24
Peak memory 219548 kb
Host smart-2c9c0270-9d4f-4853-be0a-d326b752b426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71519373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.71519373
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1194485150
Short name T535
Test name
Test status
Simulation time 26567879 ps
CPU time 0.91 seconds
Started Jul 27 05:56:08 PM PDT 24
Finished Jul 27 05:56:09 PM PDT 24
Peak memory 214672 kb
Host smart-873ce48d-0576-413c-85af-a4ef706fa07e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194485150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1194485150
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.202659950
Short name T186
Test name
Test status
Simulation time 11614594 ps
CPU time 0.94 seconds
Started Jul 27 05:56:03 PM PDT 24
Finished Jul 27 05:56:04 PM PDT 24
Peak memory 215284 kb
Host smart-908f36b2-9956-4285-a7e2-e4a82defb1e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202659950 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.202659950
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.4086621745
Short name T955
Test name
Test status
Simulation time 27697389 ps
CPU time 1.11 seconds
Started Jul 27 05:56:08 PM PDT 24
Finished Jul 27 05:56:09 PM PDT 24
Peak memory 218288 kb
Host smart-da20ea4c-e8c4-4c93-964a-595886775808
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086621745 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.4086621745
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1293245130
Short name T670
Test name
Test status
Simulation time 81553283 ps
CPU time 0.93 seconds
Started Jul 27 05:56:07 PM PDT 24
Finished Jul 27 05:56:08 PM PDT 24
Peak memory 219680 kb
Host smart-cb56d19b-d752-49f5-9e2b-6e465f090ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293245130 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1293245130
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1221737192
Short name T994
Test name
Test status
Simulation time 42425122 ps
CPU time 1.46 seconds
Started Jul 27 05:56:03 PM PDT 24
Finished Jul 27 05:56:05 PM PDT 24
Peak memory 219744 kb
Host smart-c35eda44-e4a8-46c1-b542-7f4bd208ebba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221737192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1221737192
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1346815190
Short name T895
Test name
Test status
Simulation time 20489992 ps
CPU time 1.09 seconds
Started Jul 27 05:56:08 PM PDT 24
Finished Jul 27 05:56:14 PM PDT 24
Peak memory 215408 kb
Host smart-a0a76f9d-d501-43ef-a941-0ab71f770875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346815190 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1346815190
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1308795349
Short name T654
Test name
Test status
Simulation time 16690324 ps
CPU time 0.9 seconds
Started Jul 27 05:56:08 PM PDT 24
Finished Jul 27 05:56:09 PM PDT 24
Peak memory 215084 kb
Host smart-43eed192-b935-4538-95eb-717db9ef9cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308795349 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1308795349
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.42960490
Short name T924
Test name
Test status
Simulation time 197778362 ps
CPU time 2.54 seconds
Started Jul 27 05:56:02 PM PDT 24
Finished Jul 27 05:56:05 PM PDT 24
Peak memory 217400 kb
Host smart-719dc79d-ae1f-4e95-87bc-dbe3d6734d5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42960490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.42960490
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3922135727
Short name T236
Test name
Test status
Simulation time 17718788346 ps
CPU time 413.92 seconds
Started Jul 27 05:56:06 PM PDT 24
Finished Jul 27 06:03:00 PM PDT 24
Peak memory 218296 kb
Host smart-349f1010-2031-4586-94e4-bd7165471814
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922135727 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3922135727
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2613355278
Short name T903
Test name
Test status
Simulation time 25194226 ps
CPU time 1.18 seconds
Started Jul 27 05:57:37 PM PDT 24
Finished Jul 27 05:57:39 PM PDT 24
Peak memory 215544 kb
Host smart-2a00733f-105e-4960-a5c4-7f67d0b9ad73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613355278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2613355278
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.2410302815
Short name T537
Test name
Test status
Simulation time 83953566 ps
CPU time 2.86 seconds
Started Jul 27 05:57:37 PM PDT 24
Finished Jul 27 05:57:40 PM PDT 24
Peak memory 219696 kb
Host smart-d6726f95-f649-455a-a7a6-77a0ad95edfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410302815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2410302815
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.1830684886
Short name T211
Test name
Test status
Simulation time 158923652 ps
CPU time 1.2 seconds
Started Jul 27 05:57:34 PM PDT 24
Finished Jul 27 05:57:36 PM PDT 24
Peak memory 218968 kb
Host smart-21361fde-c21c-4df9-891b-6cf782412c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830684886 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1830684886
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3678853729
Short name T313
Test name
Test status
Simulation time 64264979 ps
CPU time 1.05 seconds
Started Jul 27 05:57:33 PM PDT 24
Finished Jul 27 05:57:34 PM PDT 24
Peak memory 217168 kb
Host smart-a00a4bf4-ddfb-4b1c-925e-559a55518efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678853729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3678853729
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3813983046
Short name T210
Test name
Test status
Simulation time 60934860 ps
CPU time 1.15 seconds
Started Jul 27 05:57:33 PM PDT 24
Finished Jul 27 05:57:34 PM PDT 24
Peak memory 218592 kb
Host smart-d030a984-2cb1-42cd-92bd-1b13c7567292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813983046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3813983046
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.907065606
Short name T874
Test name
Test status
Simulation time 84958193 ps
CPU time 1.18 seconds
Started Jul 27 05:57:34 PM PDT 24
Finished Jul 27 05:57:35 PM PDT 24
Peak memory 217168 kb
Host smart-1a02197c-3876-4b71-bfc4-7a572b056eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907065606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.907065606
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.3917212555
Short name T171
Test name
Test status
Simulation time 53312552 ps
CPU time 1.22 seconds
Started Jul 27 05:57:40 PM PDT 24
Finished Jul 27 05:57:41 PM PDT 24
Peak memory 219584 kb
Host smart-6d80a73d-c8bf-44be-b77f-55dd041336a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917212555 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3917212555
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.570319019
Short name T486
Test name
Test status
Simulation time 134009010 ps
CPU time 1.75 seconds
Started Jul 27 05:57:40 PM PDT 24
Finished Jul 27 05:57:42 PM PDT 24
Peak memory 217384 kb
Host smart-69642bd3-5c41-4d59-a378-eedc675620f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570319019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.570319019
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.456533470
Short name T214
Test name
Test status
Simulation time 56289585 ps
CPU time 1.17 seconds
Started Jul 27 05:57:42 PM PDT 24
Finished Jul 27 05:57:43 PM PDT 24
Peak memory 220356 kb
Host smart-7f6d6899-5df1-4db2-8bd8-70ed20ae3cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456533470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.456533470
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.2779498040
Short name T51
Test name
Test status
Simulation time 51338639 ps
CPU time 1.2 seconds
Started Jul 27 05:57:36 PM PDT 24
Finished Jul 27 05:57:37 PM PDT 24
Peak memory 218388 kb
Host smart-18f1ed29-eec2-4384-9e6f-c6e42ea443a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779498040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2779498040
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3904958921
Short name T341
Test name
Test status
Simulation time 30210119 ps
CPU time 1.18 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:46 PM PDT 24
Peak memory 218400 kb
Host smart-7f9e1d50-3bd3-4ca2-9356-9a545ddd2e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904958921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3904958921
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.632648667
Short name T710
Test name
Test status
Simulation time 110179117 ps
CPU time 1.68 seconds
Started Jul 27 05:57:42 PM PDT 24
Finished Jul 27 05:57:44 PM PDT 24
Peak memory 218760 kb
Host smart-66d9355c-6dbc-4d1c-a295-b58ceb4cea2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632648667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.632648667
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.4205377821
Short name T222
Test name
Test status
Simulation time 26576176 ps
CPU time 1.26 seconds
Started Jul 27 05:57:41 PM PDT 24
Finished Jul 27 05:57:43 PM PDT 24
Peak memory 219676 kb
Host smart-353fd2e0-0fda-40bc-b703-04755c03ad19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205377821 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.4205377821
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3139682785
Short name T534
Test name
Test status
Simulation time 76443968 ps
CPU time 1.34 seconds
Started Jul 27 05:57:56 PM PDT 24
Finished Jul 27 05:57:57 PM PDT 24
Peak memory 218604 kb
Host smart-ac5b4305-8b16-4b60-9aee-75a57417b50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139682785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3139682785
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.884432644
Short name T913
Test name
Test status
Simulation time 92752480 ps
CPU time 1.24 seconds
Started Jul 27 05:57:49 PM PDT 24
Finished Jul 27 05:57:50 PM PDT 24
Peak memory 220532 kb
Host smart-f50231ad-e597-4789-bf12-d526bdce5444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884432644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.884432644
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.1112481015
Short name T942
Test name
Test status
Simulation time 43369373 ps
CPU time 1.71 seconds
Started Jul 27 05:57:46 PM PDT 24
Finished Jul 27 05:57:48 PM PDT 24
Peak memory 217304 kb
Host smart-7ab38b73-86f3-43b4-b70b-90e0b045290a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112481015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1112481015
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.1616671266
Short name T402
Test name
Test status
Simulation time 36051193 ps
CPU time 1.06 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 218264 kb
Host smart-ee983d82-2d42-4c5c-90fa-ad708708a07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616671266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1616671266
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.437940812
Short name T956
Test name
Test status
Simulation time 58264046 ps
CPU time 1.59 seconds
Started Jul 27 05:57:38 PM PDT 24
Finished Jul 27 05:57:40 PM PDT 24
Peak memory 218356 kb
Host smart-390b6882-11aa-43eb-9792-b7c8aa448e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437940812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.437940812
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.2328772190
Short name T626
Test name
Test status
Simulation time 70025139 ps
CPU time 1.24 seconds
Started Jul 27 05:57:42 PM PDT 24
Finished Jul 27 05:57:44 PM PDT 24
Peak memory 215560 kb
Host smart-606785bf-f9e5-4570-8b91-9dab6ce86d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328772190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2328772190
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.837122529
Short name T542
Test name
Test status
Simulation time 44728271 ps
CPU time 1.46 seconds
Started Jul 27 05:57:54 PM PDT 24
Finished Jul 27 05:57:55 PM PDT 24
Peak memory 218388 kb
Host smart-85ed1906-17a0-4941-8d08-5fdc60ae1345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837122529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.837122529
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.782155872
Short name T12
Test name
Test status
Simulation time 25982398 ps
CPU time 1.27 seconds
Started Jul 27 05:56:06 PM PDT 24
Finished Jul 27 05:56:13 PM PDT 24
Peak memory 219636 kb
Host smart-09ebac34-406a-4f0a-b48b-c78860c8d47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782155872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.782155872
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3377325946
Short name T549
Test name
Test status
Simulation time 35199058 ps
CPU time 0.82 seconds
Started Jul 27 05:56:05 PM PDT 24
Finished Jul 27 05:56:06 PM PDT 24
Peak memory 206716 kb
Host smart-67f333b3-7b8a-4215-8dfa-79ab6f2cb70e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377325946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3377325946
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.323826030
Short name T803
Test name
Test status
Simulation time 28733011 ps
CPU time 0.86 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 215940 kb
Host smart-6c347588-01fd-4e7c-a465-19fad0a76a74
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323826030 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.323826030
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2829023757
Short name T789
Test name
Test status
Simulation time 34904390 ps
CPU time 1.16 seconds
Started Jul 27 05:56:06 PM PDT 24
Finished Jul 27 05:56:07 PM PDT 24
Peak memory 215668 kb
Host smart-d4f44662-4ad6-42c6-a1e6-50110ddec4f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829023757 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2829023757
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.504285504
Short name T574
Test name
Test status
Simulation time 22912482 ps
CPU time 1.08 seconds
Started Jul 27 05:56:08 PM PDT 24
Finished Jul 27 05:56:09 PM PDT 24
Peak memory 223908 kb
Host smart-e8da4593-982a-49dc-915c-180d0992470d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504285504 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.504285504
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3552118378
Short name T359
Test name
Test status
Simulation time 42578029 ps
CPU time 1.49 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:12 PM PDT 24
Peak memory 219752 kb
Host smart-f974d215-edc0-45e6-a248-e4f4512342b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552118378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3552118378
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.4263394351
Short name T576
Test name
Test status
Simulation time 26786542 ps
CPU time 0.95 seconds
Started Jul 27 05:56:07 PM PDT 24
Finished Jul 27 05:56:08 PM PDT 24
Peak memory 215416 kb
Host smart-f2685790-8d28-45dc-81ce-f6f2f665368c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263394351 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.4263394351
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.4067147770
Short name T243
Test name
Test status
Simulation time 22309559 ps
CPU time 0.93 seconds
Started Jul 27 05:56:07 PM PDT 24
Finished Jul 27 05:56:08 PM PDT 24
Peak memory 215232 kb
Host smart-9919efb6-388c-40c6-ad86-720e8db85a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067147770 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.4067147770
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2661207043
Short name T131
Test name
Test status
Simulation time 309879367 ps
CPU time 4.28 seconds
Started Jul 27 05:56:03 PM PDT 24
Finished Jul 27 05:56:07 PM PDT 24
Peak memory 217116 kb
Host smart-112399de-1c70-401a-83fa-2716c668454d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661207043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2661207043
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3619581274
Short name T550
Test name
Test status
Simulation time 228028487206 ps
CPU time 2516.66 seconds
Started Jul 27 05:56:03 PM PDT 24
Finished Jul 27 06:38:00 PM PDT 24
Peak memory 229700 kb
Host smart-fc7d88c7-12a0-4b21-a8f6-552539d4f1a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619581274 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3619581274
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.1827577406
Short name T694
Test name
Test status
Simulation time 51839393 ps
CPU time 1.25 seconds
Started Jul 27 05:57:46 PM PDT 24
Finished Jul 27 05:57:47 PM PDT 24
Peak memory 218524 kb
Host smart-4436979a-2e93-431e-b875-926ff5e23f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827577406 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.1827577406
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1897828559
Short name T733
Test name
Test status
Simulation time 61172647 ps
CPU time 1.02 seconds
Started Jul 27 05:57:42 PM PDT 24
Finished Jul 27 05:57:43 PM PDT 24
Peak memory 217428 kb
Host smart-bb97e556-4937-4d94-976f-1c05353b133b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897828559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1897828559
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.1872809686
Short name T528
Test name
Test status
Simulation time 85969426 ps
CPU time 1.13 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 218256 kb
Host smart-c6be4c09-85d5-4d23-8a35-07311ec8604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872809686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.1872809686
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.2896224570
Short name T417
Test name
Test status
Simulation time 61711081 ps
CPU time 1.39 seconds
Started Jul 27 05:57:45 PM PDT 24
Finished Jul 27 05:57:46 PM PDT 24
Peak memory 218420 kb
Host smart-fb96ad77-fbe5-4b4d-8be8-a9d50533701a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896224570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2896224570
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.1904627090
Short name T825
Test name
Test status
Simulation time 37592630 ps
CPU time 1.13 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 219500 kb
Host smart-97f77dd8-aef8-4dda-a512-98bae1cc03df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904627090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1904627090
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.4065129644
Short name T984
Test name
Test status
Simulation time 36786762 ps
CPU time 1.11 seconds
Started Jul 27 05:57:52 PM PDT 24
Finished Jul 27 05:57:53 PM PDT 24
Peak memory 217320 kb
Host smart-614c9c3e-ed8b-42da-8ba8-1554f71e31a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065129644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.4065129644
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1273051247
Short name T188
Test name
Test status
Simulation time 31213841 ps
CPU time 1.18 seconds
Started Jul 27 05:57:49 PM PDT 24
Finished Jul 27 05:57:50 PM PDT 24
Peak memory 218424 kb
Host smart-715e3b59-4a98-4bae-8e5d-78375d4fa2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273051247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1273051247
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1280034179
Short name T730
Test name
Test status
Simulation time 139707295 ps
CPU time 1.56 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:46 PM PDT 24
Peak memory 218772 kb
Host smart-cc4fe20e-2c3b-43fa-91d3-e01229fde5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280034179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1280034179
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.1711358384
Short name T638
Test name
Test status
Simulation time 32815932 ps
CPU time 1.25 seconds
Started Jul 27 05:57:41 PM PDT 24
Finished Jul 27 05:57:43 PM PDT 24
Peak memory 219856 kb
Host smart-27dc4257-08a9-43e8-838f-ee0f4a02b6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711358384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.1711358384
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.395806700
Short name T524
Test name
Test status
Simulation time 40505008 ps
CPU time 1.65 seconds
Started Jul 27 05:57:45 PM PDT 24
Finished Jul 27 05:57:47 PM PDT 24
Peak memory 218600 kb
Host smart-b84d9c02-a0cb-4d98-876c-694be66f84fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395806700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.395806700
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2397156377
Short name T683
Test name
Test status
Simulation time 46289329 ps
CPU time 1.24 seconds
Started Jul 27 05:57:43 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 219228 kb
Host smart-c88bb3fe-72d8-422b-bac0-06de4228f1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397156377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2397156377
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.307047210
Short name T396
Test name
Test status
Simulation time 37842596 ps
CPU time 1.51 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:46 PM PDT 24
Peak memory 218352 kb
Host smart-d43a68e4-4e3d-4ed0-98bb-7c368914c680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307047210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.307047210
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.4080963133
Short name T622
Test name
Test status
Simulation time 46304375 ps
CPU time 1.28 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:46 PM PDT 24
Peak memory 219632 kb
Host smart-797f3eea-c793-43cc-b9a8-c8142dc808fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080963133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.4080963133
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.1249703571
Short name T616
Test name
Test status
Simulation time 46287940 ps
CPU time 1.71 seconds
Started Jul 27 05:57:43 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 215172 kb
Host smart-d3830a7d-f2e5-4666-b1e1-a29185c16159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249703571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1249703571
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2950992133
Short name T220
Test name
Test status
Simulation time 136491726 ps
CPU time 1.16 seconds
Started Jul 27 05:57:48 PM PDT 24
Finished Jul 27 05:57:50 PM PDT 24
Peak memory 218900 kb
Host smart-cc6eebbd-10af-471f-be49-7923f8c9e6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950992133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2950992133
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2786920553
Short name T909
Test name
Test status
Simulation time 134564757 ps
CPU time 1.44 seconds
Started Jul 27 05:57:45 PM PDT 24
Finished Jul 27 05:57:46 PM PDT 24
Peak memory 218728 kb
Host smart-7400b4fa-cc40-4b44-a568-6d3618080a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786920553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2786920553
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.723672446
Short name T203
Test name
Test status
Simulation time 28907775 ps
CPU time 1.22 seconds
Started Jul 27 05:57:43 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 219600 kb
Host smart-1b6a94ed-8413-43a5-9bdc-7177e098fb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723672446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.723672446
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1837563293
Short name T65
Test name
Test status
Simulation time 33908257 ps
CPU time 1.3 seconds
Started Jul 27 05:57:42 PM PDT 24
Finished Jul 27 05:57:44 PM PDT 24
Peak memory 218280 kb
Host smart-301ff325-8057-44a3-961f-ec3ad732d25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837563293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1837563293
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.3106211052
Short name T62
Test name
Test status
Simulation time 23357982 ps
CPU time 1.11 seconds
Started Jul 27 05:57:43 PM PDT 24
Finished Jul 27 05:57:44 PM PDT 24
Peak memory 219348 kb
Host smart-f5dfbf02-25a9-4df8-8a0d-eaa7d28b15fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106211052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.3106211052
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.702497522
Short name T989
Test name
Test status
Simulation time 35656199 ps
CPU time 1.46 seconds
Started Jul 27 05:57:41 PM PDT 24
Finished Jul 27 05:57:42 PM PDT 24
Peak memory 218380 kb
Host smart-94173280-f6d6-4194-a1be-a466ce323298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702497522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.702497522
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1671145577
Short name T461
Test name
Test status
Simulation time 86207796 ps
CPU time 1.26 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:12 PM PDT 24
Peak memory 215504 kb
Host smart-c7feb72b-ae7e-4409-825c-199c312238cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671145577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1671145577
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.427227490
Short name T855
Test name
Test status
Simulation time 23559102 ps
CPU time 0.89 seconds
Started Jul 27 05:56:02 PM PDT 24
Finished Jul 27 05:56:03 PM PDT 24
Peak memory 206676 kb
Host smart-8e49d58d-a5c2-4db1-bd12-4fab64327f05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427227490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.427227490
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2590029533
Short name T553
Test name
Test status
Simulation time 35107695 ps
CPU time 1.17 seconds
Started Jul 27 05:56:02 PM PDT 24
Finished Jul 27 05:56:03 PM PDT 24
Peak memory 216724 kb
Host smart-31ddf120-8e12-4ed1-ac36-11257855726f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590029533 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2590029533
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.3420786522
Short name T153
Test name
Test status
Simulation time 21290938 ps
CPU time 1.21 seconds
Started Jul 27 05:56:04 PM PDT 24
Finished Jul 27 05:56:06 PM PDT 24
Peak memory 229464 kb
Host smart-7d8ee768-bccf-4226-8aa8-7a5686765b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420786522 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3420786522
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2465349547
Short name T411
Test name
Test status
Simulation time 28875160 ps
CPU time 1.24 seconds
Started Jul 27 05:56:03 PM PDT 24
Finished Jul 27 05:56:04 PM PDT 24
Peak memory 218496 kb
Host smart-fe9a1155-2b1e-4d9d-8273-a920b25cff90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465349547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2465349547
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3161245701
Short name T43
Test name
Test status
Simulation time 23404203 ps
CPU time 1.27 seconds
Started Jul 27 05:56:05 PM PDT 24
Finished Jul 27 05:56:06 PM PDT 24
Peak memory 223832 kb
Host smart-5c4798b2-0ee6-4bf0-93c1-454a40a5a198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161245701 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3161245701
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3604614946
Short name T52
Test name
Test status
Simulation time 49816593 ps
CPU time 0.9 seconds
Started Jul 27 05:56:03 PM PDT 24
Finished Jul 27 05:56:04 PM PDT 24
Peak memory 215184 kb
Host smart-07bbd634-6aee-46b2-a072-96690979729a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604614946 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3604614946
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.805654331
Short name T754
Test name
Test status
Simulation time 376318224 ps
CPU time 2.4 seconds
Started Jul 27 05:56:07 PM PDT 24
Finished Jul 27 05:56:10 PM PDT 24
Peak memory 219952 kb
Host smart-183d6386-2264-410b-a4ad-0fb9175cf21f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805654331 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.805654331
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1001885818
Short name T506
Test name
Test status
Simulation time 338504705860 ps
CPU time 2368.18 seconds
Started Jul 27 05:56:07 PM PDT 24
Finished Jul 27 06:35:36 PM PDT 24
Peak memory 231356 kb
Host smart-884f605d-b036-4f95-b0ce-baefb58da98c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001885818 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1001885818
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.539910583
Short name T223
Test name
Test status
Simulation time 42408702 ps
CPU time 1.12 seconds
Started Jul 27 05:57:43 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 218696 kb
Host smart-f6bf1434-5b35-4760-b796-d69bbdf589c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539910583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.539910583
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.3445613921
Short name T864
Test name
Test status
Simulation time 52128593 ps
CPU time 1.23 seconds
Started Jul 27 05:57:41 PM PDT 24
Finished Jul 27 05:57:43 PM PDT 24
Peak memory 218352 kb
Host smart-a98e0ccb-d443-492e-9fa7-eeb3aeffc69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445613921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3445613921
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.3573787081
Short name T482
Test name
Test status
Simulation time 24886056 ps
CPU time 1.24 seconds
Started Jul 27 05:57:54 PM PDT 24
Finished Jul 27 05:57:55 PM PDT 24
Peak memory 218472 kb
Host smart-8be04384-ee3d-4e40-b4a4-a4f815ec6bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573787081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.3573787081
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.2903433783
Short name T544
Test name
Test status
Simulation time 122606365 ps
CPU time 1.36 seconds
Started Jul 27 05:57:46 PM PDT 24
Finished Jul 27 05:57:47 PM PDT 24
Peak memory 218716 kb
Host smart-61fac04d-58c5-47c9-a4f1-3cc0022aad4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903433783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2903433783
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1610160812
Short name T149
Test name
Test status
Simulation time 240121228 ps
CPU time 1.4 seconds
Started Jul 27 05:57:48 PM PDT 24
Finished Jul 27 05:57:50 PM PDT 24
Peak memory 218484 kb
Host smart-6a674f37-dded-4659-8162-0f0d78ff1e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610160812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1610160812
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.97379344
Short name T465
Test name
Test status
Simulation time 84982008 ps
CPU time 1.28 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 218528 kb
Host smart-83ae8f46-83d0-4b06-8e9d-e242437d2405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97379344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.97379344
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3797423587
Short name T344
Test name
Test status
Simulation time 25059631 ps
CPU time 1.15 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:46 PM PDT 24
Peak memory 218284 kb
Host smart-f271f6bf-a948-48a5-9be5-f06923d09f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797423587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3797423587
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.123335378
Short name T941
Test name
Test status
Simulation time 33120871 ps
CPU time 1.37 seconds
Started Jul 27 05:57:43 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 219936 kb
Host smart-bea3f064-cc3f-4642-a13c-08e94a7019ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123335378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.123335378
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.1164577953
Short name T856
Test name
Test status
Simulation time 37016971 ps
CPU time 1.48 seconds
Started Jul 27 05:57:43 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 218404 kb
Host smart-30b71e41-10ce-46fa-b2fb-e62b5075eb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164577953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1164577953
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.992957899
Short name T379
Test name
Test status
Simulation time 167191793 ps
CPU time 1.17 seconds
Started Jul 27 05:57:42 PM PDT 24
Finished Jul 27 05:57:43 PM PDT 24
Peak memory 218680 kb
Host smart-a252c7cd-82b5-4f6f-9358-c916444f55d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992957899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.992957899
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.2699264375
Short name T289
Test name
Test status
Simulation time 75463749 ps
CPU time 1.26 seconds
Started Jul 27 05:57:46 PM PDT 24
Finished Jul 27 05:57:47 PM PDT 24
Peak memory 218732 kb
Host smart-4dd93f0c-7814-4b17-aac5-7b0b3b9f20c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699264375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2699264375
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1424291084
Short name T180
Test name
Test status
Simulation time 101398255 ps
CPU time 1.3 seconds
Started Jul 27 05:57:42 PM PDT 24
Finished Jul 27 05:57:44 PM PDT 24
Peak memory 218372 kb
Host smart-70e1d7b7-5d7d-4df2-a26d-32131c8549e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424291084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1424291084
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.997410404
Short name T437
Test name
Test status
Simulation time 98537900 ps
CPU time 1.27 seconds
Started Jul 27 05:57:46 PM PDT 24
Finished Jul 27 05:57:47 PM PDT 24
Peak memory 218964 kb
Host smart-2ecfed0c-65b2-448b-bcda-ebcaad771433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997410404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.997410404
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.1661489776
Short name T563
Test name
Test status
Simulation time 49869775 ps
CPU time 1.2 seconds
Started Jul 27 05:57:55 PM PDT 24
Finished Jul 27 05:57:56 PM PDT 24
Peak memory 220684 kb
Host smart-e3ef65a2-983e-40ae-881d-fa422a1f5cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661489776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.1661489776
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.448956623
Short name T290
Test name
Test status
Simulation time 32306726 ps
CPU time 1.34 seconds
Started Jul 27 05:57:47 PM PDT 24
Finished Jul 27 05:57:49 PM PDT 24
Peak memory 218552 kb
Host smart-a3b615ec-46e5-4bc6-a53f-2a58a066a968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448956623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.448956623
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.3386584424
Short name T691
Test name
Test status
Simulation time 97085158 ps
CPU time 1.12 seconds
Started Jul 27 05:57:50 PM PDT 24
Finished Jul 27 05:57:51 PM PDT 24
Peak memory 219356 kb
Host smart-15d9c157-da7f-4116-8cc0-4995ed676efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386584424 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3386584424
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.4283904278
Short name T771
Test name
Test status
Simulation time 41292263 ps
CPU time 1.09 seconds
Started Jul 27 05:57:46 PM PDT 24
Finished Jul 27 05:57:47 PM PDT 24
Peak memory 218316 kb
Host smart-62f87ced-aee0-4eac-b61a-0c90613666a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283904278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.4283904278
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3997633352
Short name T916
Test name
Test status
Simulation time 23458951 ps
CPU time 1.15 seconds
Started Jul 27 05:57:47 PM PDT 24
Finished Jul 27 05:57:49 PM PDT 24
Peak memory 220560 kb
Host smart-9a2d9032-23f9-40a1-a4a3-b9ccf2efc8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997633352 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3997633352
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2960864231
Short name T364
Test name
Test status
Simulation time 94715466 ps
CPU time 1.41 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:46 PM PDT 24
Peak memory 217340 kb
Host smart-96e29063-c9b4-4d61-9c55-62b89938d5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960864231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2960864231
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.649260604
Short name T247
Test name
Test status
Simulation time 48341411 ps
CPU time 1.24 seconds
Started Jul 27 05:56:07 PM PDT 24
Finished Jul 27 05:56:08 PM PDT 24
Peak memory 218424 kb
Host smart-4d44a63a-9fd6-47fd-8e79-97c1becd8ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649260604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.649260604
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_disable.2248032692
Short name T199
Test name
Test status
Simulation time 15122395 ps
CPU time 0.9 seconds
Started Jul 27 05:56:08 PM PDT 24
Finished Jul 27 05:56:09 PM PDT 24
Peak memory 216216 kb
Host smart-99aa6ceb-3644-4b0b-9698-0db67257f86a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248032692 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2248032692
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.201385722
Short name T662
Test name
Test status
Simulation time 31514241 ps
CPU time 1.23 seconds
Started Jul 27 05:56:05 PM PDT 24
Finished Jul 27 05:56:07 PM PDT 24
Peak memory 216844 kb
Host smart-97461f53-2aba-4234-9c05-525f67c931e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201385722 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.201385722
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2753057268
Short name T18
Test name
Test status
Simulation time 19384310 ps
CPU time 1.2 seconds
Started Jul 27 05:56:11 PM PDT 24
Finished Jul 27 05:56:12 PM PDT 24
Peak memory 223852 kb
Host smart-e51a8a70-b2ab-4fc4-8c2b-77c3049d6245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753057268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2753057268
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_intr.2124082073
Short name T59
Test name
Test status
Simulation time 23300750 ps
CPU time 1.15 seconds
Started Jul 27 05:56:03 PM PDT 24
Finished Jul 27 05:56:04 PM PDT 24
Peak memory 215304 kb
Host smart-a3a238f2-e15e-47ec-a2d8-87d461bd5a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124082073 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2124082073
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3956134184
Short name T603
Test name
Test status
Simulation time 16844503 ps
CPU time 1.06 seconds
Started Jul 27 05:56:06 PM PDT 24
Finished Jul 27 05:56:07 PM PDT 24
Peak memory 215364 kb
Host smart-6a87b6f0-5052-43a2-a152-ccfce7f0b367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956134184 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3956134184
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1015991542
Short name T416
Test name
Test status
Simulation time 23639318 ps
CPU time 1.12 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 215104 kb
Host smart-aa6670e3-e214-4974-987c-f4a67eb66394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015991542 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1015991542
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3645244315
Short name T237
Test name
Test status
Simulation time 72752499320 ps
CPU time 419.94 seconds
Started Jul 27 05:56:08 PM PDT 24
Finished Jul 27 06:03:08 PM PDT 24
Peak memory 218532 kb
Host smart-0acd6381-e056-4054-8ed4-5398db2cdbb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645244315 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3645244315
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.54791874
Short name T781
Test name
Test status
Simulation time 25617381 ps
CPU time 1.23 seconds
Started Jul 27 05:57:57 PM PDT 24
Finished Jul 27 05:57:59 PM PDT 24
Peak memory 219440 kb
Host smart-cf8f57d5-77ae-4d64-a972-5614be4ef1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54791874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.54791874
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.1072706221
Short name T3
Test name
Test status
Simulation time 66457893 ps
CPU time 1.07 seconds
Started Jul 27 05:57:43 PM PDT 24
Finished Jul 27 05:57:44 PM PDT 24
Peak memory 217192 kb
Host smart-89103202-4d9d-4643-b616-db8f8098f94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072706221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1072706221
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2523787416
Short name T700
Test name
Test status
Simulation time 57046539 ps
CPU time 1.29 seconds
Started Jul 27 05:57:53 PM PDT 24
Finished Jul 27 05:57:54 PM PDT 24
Peak memory 215748 kb
Host smart-013c918f-c4d6-4af4-8168-c229e2e835f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523787416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2523787416
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.1439653405
Short name T815
Test name
Test status
Simulation time 73530545 ps
CPU time 1.39 seconds
Started Jul 27 05:58:00 PM PDT 24
Finished Jul 27 05:58:02 PM PDT 24
Peak memory 218668 kb
Host smart-48ce236e-5bb8-41ab-9b6a-fc2d59fbfb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439653405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1439653405
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.230756903
Short name T255
Test name
Test status
Simulation time 72410226 ps
CPU time 1.33 seconds
Started Jul 27 05:57:56 PM PDT 24
Finished Jul 27 05:57:58 PM PDT 24
Peak memory 218060 kb
Host smart-b3a9c059-61dc-4442-bcc6-6f7938ced40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230756903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.230756903
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.1789668171
Short name T764
Test name
Test status
Simulation time 93519448 ps
CPU time 1.19 seconds
Started Jul 27 05:57:51 PM PDT 24
Finished Jul 27 05:57:52 PM PDT 24
Peak memory 217008 kb
Host smart-6b5325e1-9684-49a6-8f34-12a581a34486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789668171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1789668171
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.3517947061
Short name T339
Test name
Test status
Simulation time 65572770 ps
CPU time 1.2 seconds
Started Jul 27 05:57:43 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 220340 kb
Host smart-6d7c5f81-085f-4bd5-9dae-5cf05ed48f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517947061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3517947061
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/185.edn_alert.1679054530
Short name T910
Test name
Test status
Simulation time 21985339 ps
CPU time 1.14 seconds
Started Jul 27 05:57:55 PM PDT 24
Finished Jul 27 05:57:56 PM PDT 24
Peak memory 218288 kb
Host smart-ef4fe4e6-bc7c-4130-8a62-d40db0004c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679054530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.1679054530
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.791772281
Short name T884
Test name
Test status
Simulation time 78833459 ps
CPU time 1.1 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:46 PM PDT 24
Peak memory 217368 kb
Host smart-1344f913-4bb0-43c5-b92a-228f20d73fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791772281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.791772281
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.3941495092
Short name T773
Test name
Test status
Simulation time 28371277 ps
CPU time 1.36 seconds
Started Jul 27 05:58:01 PM PDT 24
Finished Jul 27 05:58:03 PM PDT 24
Peak memory 215548 kb
Host smart-3f06cee0-c3f4-40d7-a581-1acfbfe11c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941495092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3941495092
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.4156759844
Short name T720
Test name
Test status
Simulation time 152729811 ps
CPU time 3.55 seconds
Started Jul 27 05:57:57 PM PDT 24
Finished Jul 27 05:58:01 PM PDT 24
Peak memory 220032 kb
Host smart-f1d31582-0b57-42da-ac7a-a63f72c2a0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156759844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4156759844
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.3740025218
Short name T287
Test name
Test status
Simulation time 96725090 ps
CPU time 1.17 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 220144 kb
Host smart-4df65799-1a2d-4206-9558-a3f4b3f9606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740025218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3740025218
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.785179775
Short name T348
Test name
Test status
Simulation time 68452104 ps
CPU time 1.03 seconds
Started Jul 27 05:57:57 PM PDT 24
Finished Jul 27 05:57:58 PM PDT 24
Peak memory 217364 kb
Host smart-ca0b6838-94f0-45de-8dce-09fcc39280aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785179775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.785179775
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1121489381
Short name T578
Test name
Test status
Simulation time 19420075 ps
CPU time 1.16 seconds
Started Jul 27 05:57:56 PM PDT 24
Finished Jul 27 05:57:57 PM PDT 24
Peak memory 219704 kb
Host smart-5d55f9d6-bac6-4c16-9eda-8c93c1c0936a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121489381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1121489381
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2812407794
Short name T173
Test name
Test status
Simulation time 302106446 ps
CPU time 1.17 seconds
Started Jul 27 05:57:51 PM PDT 24
Finished Jul 27 05:57:52 PM PDT 24
Peak memory 218316 kb
Host smart-e4af114e-3a24-444c-8404-8346c2ed64bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812407794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2812407794
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2064517888
Short name T540
Test name
Test status
Simulation time 2203693940 ps
CPU time 65.12 seconds
Started Jul 27 05:57:54 PM PDT 24
Finished Jul 27 05:58:59 PM PDT 24
Peak memory 220076 kb
Host smart-8fe67735-7732-4767-a27e-b631dbc2bc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064517888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2064517888
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.983038881
Short name T166
Test name
Test status
Simulation time 138908694 ps
CPU time 1.19 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 220456 kb
Host smart-465e0434-1e71-4970-9740-e137fca58627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983038881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.983038881
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.23786731
Short name T556
Test name
Test status
Simulation time 26719298 ps
CPU time 0.92 seconds
Started Jul 27 05:56:06 PM PDT 24
Finished Jul 27 05:56:07 PM PDT 24
Peak memory 206816 kb
Host smart-cbb3c5eb-0b73-4a68-a2a1-03a3e9030998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23786731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.23786731
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.4047173340
Short name T113
Test name
Test status
Simulation time 23087018 ps
CPU time 0.85 seconds
Started Jul 27 05:56:26 PM PDT 24
Finished Jul 27 05:56:27 PM PDT 24
Peak memory 216184 kb
Host smart-d35781e9-c258-4775-95b1-c32167ecf082
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047173340 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.4047173340
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2269498396
Short name T929
Test name
Test status
Simulation time 26868638 ps
CPU time 1.07 seconds
Started Jul 27 05:56:06 PM PDT 24
Finished Jul 27 05:56:08 PM PDT 24
Peak memory 216600 kb
Host smart-14902055-6d76-4205-a98d-47314ed556eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269498396 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2269498396
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.235793975
Short name T743
Test name
Test status
Simulation time 76286962 ps
CPU time 1.13 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:12 PM PDT 24
Peak memory 219548 kb
Host smart-0f996414-2695-41b1-a962-4d000663c552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235793975 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.235793975
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.118666942
Short name T242
Test name
Test status
Simulation time 84687020 ps
CPU time 1.08 seconds
Started Jul 27 05:56:15 PM PDT 24
Finished Jul 27 05:56:16 PM PDT 24
Peak memory 217060 kb
Host smart-a590018e-754d-4bfe-8dc9-8d0b33a75e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118666942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.118666942
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3883380660
Short name T82
Test name
Test status
Simulation time 45082378 ps
CPU time 0.81 seconds
Started Jul 27 05:56:09 PM PDT 24
Finished Jul 27 05:56:10 PM PDT 24
Peak memory 215484 kb
Host smart-e606e62e-ad9a-4acf-987c-f9a4a6c1ebe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883380660 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3883380660
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1603283501
Short name T464
Test name
Test status
Simulation time 18211896 ps
CPU time 1.06 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 215136 kb
Host smart-f9afceb9-a804-4160-865d-531ce4981e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603283501 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1603283501
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3074283678
Short name T636
Test name
Test status
Simulation time 72606098 ps
CPU time 2.06 seconds
Started Jul 27 05:56:05 PM PDT 24
Finished Jul 27 05:56:07 PM PDT 24
Peak memory 215180 kb
Host smart-5e6d2520-4e73-4f37-8c0e-528d3882cd63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074283678 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3074283678
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/190.edn_alert.867654138
Short name T510
Test name
Test status
Simulation time 51737314 ps
CPU time 1.35 seconds
Started Jul 27 05:57:55 PM PDT 24
Finished Jul 27 05:57:57 PM PDT 24
Peak memory 218576 kb
Host smart-3aef204b-905d-4a62-9d34-bef5ee5a7676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867654138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.867654138
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.1292730345
Short name T647
Test name
Test status
Simulation time 70946978 ps
CPU time 1.04 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 217200 kb
Host smart-86916838-656d-4168-9151-daff51e92bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292730345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1292730345
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.4259597080
Short name T466
Test name
Test status
Simulation time 29616269 ps
CPU time 1.49 seconds
Started Jul 27 05:57:58 PM PDT 24
Finished Jul 27 05:57:59 PM PDT 24
Peak memory 218548 kb
Host smart-b087ac4b-b982-4951-bd69-a5b519c0d98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259597080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.4259597080
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3085061037
Short name T167
Test name
Test status
Simulation time 50415623 ps
CPU time 1.18 seconds
Started Jul 27 05:57:54 PM PDT 24
Finished Jul 27 05:57:56 PM PDT 24
Peak memory 220488 kb
Host smart-bfff114a-e3a5-416c-a7a9-b0b9a120459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085061037 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3085061037
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.754254381
Short name T336
Test name
Test status
Simulation time 32559083 ps
CPU time 1.35 seconds
Started Jul 27 05:57:51 PM PDT 24
Finished Jul 27 05:57:53 PM PDT 24
Peak memory 219628 kb
Host smart-97d60058-7eea-4044-947d-af354ee9b334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754254381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.754254381
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.1527902786
Short name T545
Test name
Test status
Simulation time 67603941 ps
CPU time 1.3 seconds
Started Jul 27 05:57:56 PM PDT 24
Finished Jul 27 05:57:57 PM PDT 24
Peak memory 220528 kb
Host smart-ff05a280-a7fa-48fa-bb19-e057d3480607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527902786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.1527902786
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/194.edn_alert.3944508584
Short name T749
Test name
Test status
Simulation time 52630392 ps
CPU time 1.27 seconds
Started Jul 27 05:58:02 PM PDT 24
Finished Jul 27 05:58:03 PM PDT 24
Peak memory 215576 kb
Host smart-a37eb71f-c009-4d5c-8b2e-5831102ab100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944508584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.3944508584
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2968182036
Short name T361
Test name
Test status
Simulation time 139506114 ps
CPU time 3.24 seconds
Started Jul 27 05:58:10 PM PDT 24
Finished Jul 27 05:58:13 PM PDT 24
Peak memory 219940 kb
Host smart-3c23762d-f8fb-47f4-9c05-291a92fd8def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968182036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2968182036
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2843529064
Short name T343
Test name
Test status
Simulation time 36828890 ps
CPU time 1.08 seconds
Started Jul 27 05:57:52 PM PDT 24
Finished Jul 27 05:57:53 PM PDT 24
Peak memory 221280 kb
Host smart-f8ad229a-ec3f-4aa6-a440-08dbe579d624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843529064 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2843529064
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.1978729103
Short name T11
Test name
Test status
Simulation time 412673678 ps
CPU time 3.89 seconds
Started Jul 27 05:57:50 PM PDT 24
Finished Jul 27 05:57:54 PM PDT 24
Peak memory 219652 kb
Host smart-9a376dc5-18d0-4295-a0c6-55f8fb21129c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978729103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1978729103
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.3275854461
Short name T543
Test name
Test status
Simulation time 32275207 ps
CPU time 1.29 seconds
Started Jul 27 05:57:49 PM PDT 24
Finished Jul 27 05:57:50 PM PDT 24
Peak memory 215560 kb
Host smart-9cf20636-b750-433f-8d52-47afa9dad6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275854461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.3275854461
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.905619117
Short name T824
Test name
Test status
Simulation time 74002802 ps
CPU time 1.24 seconds
Started Jul 27 05:57:49 PM PDT 24
Finished Jul 27 05:57:50 PM PDT 24
Peak memory 217144 kb
Host smart-df106405-9274-496d-85d3-20337a996625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905619117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.905619117
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3318872257
Short name T631
Test name
Test status
Simulation time 23337120 ps
CPU time 1.15 seconds
Started Jul 27 05:57:54 PM PDT 24
Finished Jul 27 05:57:55 PM PDT 24
Peak memory 220768 kb
Host smart-77cb3d42-550f-47b4-b808-4750c1e6e5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318872257 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3318872257
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.1368555981
Short name T788
Test name
Test status
Simulation time 383596278 ps
CPU time 3.74 seconds
Started Jul 27 05:57:44 PM PDT 24
Finished Jul 27 05:57:48 PM PDT 24
Peak memory 220036 kb
Host smart-37a26bc8-da7f-46a0-9afe-5861b2334f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368555981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1368555981
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.3029714965
Short name T885
Test name
Test status
Simulation time 24601311 ps
CPU time 1.14 seconds
Started Jul 27 05:57:48 PM PDT 24
Finished Jul 27 05:57:50 PM PDT 24
Peak memory 218300 kb
Host smart-ded45233-1ba2-4a0b-a6d9-38a491d079ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029714965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.3029714965
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.2046039895
Short name T709
Test name
Test status
Simulation time 65034514 ps
CPU time 1.07 seconds
Started Jul 27 05:58:00 PM PDT 24
Finished Jul 27 05:58:01 PM PDT 24
Peak memory 217148 kb
Host smart-ef90e01a-cb10-4395-8b92-9132da88cf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046039895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2046039895
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1295980358
Short name T666
Test name
Test status
Simulation time 45525976 ps
CPU time 1.17 seconds
Started Jul 27 05:57:56 PM PDT 24
Finished Jul 27 05:57:58 PM PDT 24
Peak memory 219144 kb
Host smart-27f8a500-2c80-442f-907f-d20c215b084e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295980358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1295980358
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.164642654
Short name T469
Test name
Test status
Simulation time 48058084 ps
CPU time 1.18 seconds
Started Jul 27 05:58:12 PM PDT 24
Finished Jul 27 05:58:13 PM PDT 24
Peak memory 219732 kb
Host smart-5b9a2bdb-0895-4be1-b9a3-fbaa88636e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164642654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.164642654
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3228943122
Short name T169
Test name
Test status
Simulation time 52708852 ps
CPU time 1.11 seconds
Started Jul 27 05:55:37 PM PDT 24
Finished Jul 27 05:55:38 PM PDT 24
Peak memory 218184 kb
Host smart-c6d47ae0-be5c-46c8-b145-9d7db41e2614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228943122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3228943122
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.1301758367
Short name T703
Test name
Test status
Simulation time 41303432 ps
CPU time 0.94 seconds
Started Jul 27 05:55:33 PM PDT 24
Finished Jul 27 05:55:34 PM PDT 24
Peak memory 214820 kb
Host smart-41a370e5-a484-4d04-ad3e-caea7b46eccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301758367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1301758367
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.967166083
Short name T740
Test name
Test status
Simulation time 84782878 ps
CPU time 1.15 seconds
Started Jul 27 05:55:35 PM PDT 24
Finished Jul 27 05:55:36 PM PDT 24
Peak memory 216776 kb
Host smart-0744b51e-1501-4e1d-b6ae-b9ee5faeb7fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967166083 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.967166083
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2495954834
Short name T456
Test name
Test status
Simulation time 21156611 ps
CPU time 0.89 seconds
Started Jul 27 05:55:37 PM PDT 24
Finished Jul 27 05:55:38 PM PDT 24
Peak memory 218620 kb
Host smart-37711378-3a2d-4001-b417-9db35a5bdeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495954834 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2495954834
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2218047204
Short name T581
Test name
Test status
Simulation time 121261535 ps
CPU time 1.06 seconds
Started Jul 27 05:55:32 PM PDT 24
Finished Jul 27 05:55:33 PM PDT 24
Peak memory 217232 kb
Host smart-90f72503-ab65-4e45-8c2e-4ec404d39832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218047204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2218047204
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.752046210
Short name T759
Test name
Test status
Simulation time 22132366 ps
CPU time 1.09 seconds
Started Jul 27 05:55:43 PM PDT 24
Finished Jul 27 05:55:44 PM PDT 24
Peak memory 216656 kb
Host smart-68334ccb-db3f-4aea-b36d-a7c34eb21667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752046210 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.752046210
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_smoke.3316813937
Short name T378
Test name
Test status
Simulation time 78468936 ps
CPU time 0.98 seconds
Started Jul 27 05:55:38 PM PDT 24
Finished Jul 27 05:55:40 PM PDT 24
Peak memory 215064 kb
Host smart-621cb127-a41b-43ce-99d0-2eab6042c21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316813937 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3316813937
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.4037904158
Short name T653
Test name
Test status
Simulation time 116936750 ps
CPU time 1.2 seconds
Started Jul 27 05:55:32 PM PDT 24
Finished Jul 27 05:55:34 PM PDT 24
Peak memory 206952 kb
Host smart-bba71f0d-9ad6-4474-b752-1da7debafba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037904158 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.4037904158
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1486122799
Short name T233
Test name
Test status
Simulation time 52586999611 ps
CPU time 580.9 seconds
Started Jul 27 05:55:34 PM PDT 24
Finished Jul 27 06:05:15 PM PDT 24
Peak memory 217548 kb
Host smart-e505f059-7e3d-44f1-be9e-fd375206780d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486122799 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1486122799
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.4093351372
Short name T867
Test name
Test status
Simulation time 48424649 ps
CPU time 1.15 seconds
Started Jul 27 05:56:05 PM PDT 24
Finished Jul 27 05:56:06 PM PDT 24
Peak memory 218492 kb
Host smart-151c1c13-fc15-4492-88e5-76ce2bb43f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093351372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4093351372
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2401964410
Short name T41
Test name
Test status
Simulation time 13301527 ps
CPU time 0.9 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 206904 kb
Host smart-36bffb2b-3e2b-442a-a3a7-e35287ce6256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401964410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2401964410
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1933180260
Short name T418
Test name
Test status
Simulation time 94844199 ps
CPU time 1.05 seconds
Started Jul 27 05:56:18 PM PDT 24
Finished Jul 27 05:56:19 PM PDT 24
Peak memory 218204 kb
Host smart-573857f0-2cd5-4508-b391-4b6f16804736
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933180260 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1933180260
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.680564468
Short name T753
Test name
Test status
Simulation time 22503778 ps
CPU time 0.93 seconds
Started Jul 27 05:56:05 PM PDT 24
Finished Jul 27 05:56:06 PM PDT 24
Peak memory 218404 kb
Host smart-eff49ba1-2fe5-4eb5-afca-f47fb780242e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680564468 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.680564468
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1072552190
Short name T938
Test name
Test status
Simulation time 48410488 ps
CPU time 1.62 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 217292 kb
Host smart-3d2bae34-28de-40c3-af81-7291188b1491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072552190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1072552190
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3160047041
Short name T423
Test name
Test status
Simulation time 28205829 ps
CPU time 0.95 seconds
Started Jul 27 05:56:31 PM PDT 24
Finished Jul 27 05:56:32 PM PDT 24
Peak memory 215812 kb
Host smart-410c7a4e-b5ea-4e27-988e-32616ba9e294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160047041 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3160047041
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2112173372
Short name T870
Test name
Test status
Simulation time 51079263 ps
CPU time 0.92 seconds
Started Jul 27 05:56:29 PM PDT 24
Finished Jul 27 05:56:30 PM PDT 24
Peak memory 215104 kb
Host smart-a4c0e07c-060c-4667-8b47-c045604617c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112173372 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2112173372
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3445099494
Short name T296
Test name
Test status
Simulation time 1207092699 ps
CPU time 3.48 seconds
Started Jul 27 05:56:06 PM PDT 24
Finished Jul 27 05:56:09 PM PDT 24
Peak memory 215176 kb
Host smart-bfee814a-458b-4fe4-9548-3f9c97b0e00c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445099494 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3445099494
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.636386959
Short name T791
Test name
Test status
Simulation time 293277241186 ps
CPU time 3009.5 seconds
Started Jul 27 05:56:05 PM PDT 24
Finished Jul 27 06:46:15 PM PDT 24
Peak memory 232052 kb
Host smart-2b937701-0d69-4ff2-9e7d-309ca999a52c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636386959 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.636386959
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3550515432
Short name T489
Test name
Test status
Simulation time 49583829 ps
CPU time 1.54 seconds
Started Jul 27 05:57:43 PM PDT 24
Finished Jul 27 05:57:45 PM PDT 24
Peak memory 217088 kb
Host smart-2118c58d-9605-4976-991e-8562468f8fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550515432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3550515432
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2274816320
Short name T354
Test name
Test status
Simulation time 93465566 ps
CPU time 2.23 seconds
Started Jul 27 05:58:09 PM PDT 24
Finished Jul 27 05:58:12 PM PDT 24
Peak memory 219848 kb
Host smart-86fb620d-e239-4c5e-b536-979a42fc8c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274816320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2274816320
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2011937025
Short name T693
Test name
Test status
Simulation time 34992415 ps
CPU time 1.44 seconds
Started Jul 27 05:57:55 PM PDT 24
Finished Jul 27 05:57:57 PM PDT 24
Peak memory 217220 kb
Host smart-8986efc3-540e-4c70-a33a-d4bb9b9f604e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011937025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2011937025
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3853742046
Short name T607
Test name
Test status
Simulation time 80009329 ps
CPU time 1.1 seconds
Started Jul 27 05:58:10 PM PDT 24
Finished Jul 27 05:58:11 PM PDT 24
Peak memory 217088 kb
Host smart-71a63d7f-1569-4979-982d-8c930ee62d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853742046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3853742046
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.60289119
Short name T775
Test name
Test status
Simulation time 4471811657 ps
CPU time 89.43 seconds
Started Jul 27 05:58:10 PM PDT 24
Finished Jul 27 05:59:40 PM PDT 24
Peak memory 220720 kb
Host smart-e9a2157b-55bf-45b4-87cf-b9044d423c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60289119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.60289119
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1480991906
Short name T927
Test name
Test status
Simulation time 28790401 ps
CPU time 1.29 seconds
Started Jul 27 05:57:58 PM PDT 24
Finished Jul 27 05:57:59 PM PDT 24
Peak memory 218436 kb
Host smart-3eb30150-b668-4f01-80c3-a32bed645555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480991906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1480991906
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1696590924
Short name T414
Test name
Test status
Simulation time 50844225 ps
CPU time 1.17 seconds
Started Jul 27 05:57:59 PM PDT 24
Finished Jul 27 05:58:00 PM PDT 24
Peak memory 218396 kb
Host smart-4bd1a344-d299-4fbc-b380-756356e63b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696590924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1696590924
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1762189944
Short name T946
Test name
Test status
Simulation time 55413764 ps
CPU time 1.78 seconds
Started Jul 27 05:58:00 PM PDT 24
Finished Jul 27 05:58:02 PM PDT 24
Peak memory 218284 kb
Host smart-8e2ff18d-733f-4457-86cb-3055a25088dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762189944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1762189944
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3054945048
Short name T926
Test name
Test status
Simulation time 94598351 ps
CPU time 3.02 seconds
Started Jul 27 05:57:55 PM PDT 24
Finished Jul 27 05:57:58 PM PDT 24
Peak memory 218452 kb
Host smart-da51f090-8366-48f8-8b56-cad565b785da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054945048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3054945048
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3641221266
Short name T257
Test name
Test status
Simulation time 99156999 ps
CPU time 1.27 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:12 PM PDT 24
Peak memory 220140 kb
Host smart-59a12a9b-03ad-452c-9682-b1005877bdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641221266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3641221266
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3901889540
Short name T762
Test name
Test status
Simulation time 215157095 ps
CPU time 0.9 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 206596 kb
Host smart-ceb9de92-de1d-4047-8d93-c611a78e066b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901889540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3901889540
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2494118432
Short name T769
Test name
Test status
Simulation time 54792914 ps
CPU time 1.27 seconds
Started Jul 27 05:56:15 PM PDT 24
Finished Jul 27 05:56:17 PM PDT 24
Peak memory 216868 kb
Host smart-9365c9bb-007c-4219-8374-5a0e8330cdf8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494118432 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2494118432
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3080917192
Short name T175
Test name
Test status
Simulation time 27864959 ps
CPU time 1.44 seconds
Started Jul 27 05:56:15 PM PDT 24
Finished Jul 27 05:56:17 PM PDT 24
Peak memory 229592 kb
Host smart-faf7cd09-7409-45ae-be16-f9461f9b42b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080917192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3080917192
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2171354281
Short name T318
Test name
Test status
Simulation time 42973378 ps
CPU time 1.38 seconds
Started Jul 27 05:56:05 PM PDT 24
Finished Jul 27 05:56:07 PM PDT 24
Peak memory 217176 kb
Host smart-1ec13c2d-0034-4f8c-a091-d53fd11c3534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171354281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2171354281
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1174419230
Short name T122
Test name
Test status
Simulation time 27089891 ps
CPU time 0.98 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 215380 kb
Host smart-28fbecea-f42b-4871-83d0-f59fee6e8634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174419230 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1174419230
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3444217017
Short name T837
Test name
Test status
Simulation time 46308722 ps
CPU time 0.86 seconds
Started Jul 27 05:56:08 PM PDT 24
Finished Jul 27 05:56:09 PM PDT 24
Peak memory 215168 kb
Host smart-9e9dd896-26a5-4b1d-8b4a-603bfb426715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444217017 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3444217017
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.621646051
Short name T133
Test name
Test status
Simulation time 980930605 ps
CPU time 5.11 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:15 PM PDT 24
Peak memory 217048 kb
Host smart-7bfc80dc-c1eb-44b4-b5a9-6e7eca91d9a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621646051 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.621646051
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/210.edn_genbits.3231402149
Short name T346
Test name
Test status
Simulation time 306190282 ps
CPU time 2.78 seconds
Started Jul 27 05:57:57 PM PDT 24
Finished Jul 27 05:58:00 PM PDT 24
Peak memory 217600 kb
Host smart-da9ac01a-b89a-4d23-8744-f7d3a99426fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231402149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3231402149
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3447514131
Short name T390
Test name
Test status
Simulation time 48904725 ps
CPU time 1.34 seconds
Started Jul 27 05:57:54 PM PDT 24
Finished Jul 27 05:57:56 PM PDT 24
Peak memory 217236 kb
Host smart-edb7c1dc-e52b-4686-b1f8-b077fcefdb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447514131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3447514131
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2216199610
Short name T604
Test name
Test status
Simulation time 105410500 ps
CPU time 1.43 seconds
Started Jul 27 05:58:03 PM PDT 24
Finished Jul 27 05:58:05 PM PDT 24
Peak memory 219128 kb
Host smart-06974e49-5e57-4141-a812-e2b457e85aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216199610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2216199610
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2174428268
Short name T922
Test name
Test status
Simulation time 52019922 ps
CPU time 1.1 seconds
Started Jul 27 05:57:56 PM PDT 24
Finished Jul 27 05:57:58 PM PDT 24
Peak memory 217140 kb
Host smart-df059292-1c57-432a-bab6-33f5c0237216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174428268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2174428268
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2391236959
Short name T520
Test name
Test status
Simulation time 297987778 ps
CPU time 1.2 seconds
Started Jul 27 05:58:07 PM PDT 24
Finished Jul 27 05:58:08 PM PDT 24
Peak memory 215208 kb
Host smart-5f3616ab-3d00-4c64-bb90-91c10c30fd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391236959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2391236959
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.336762856
Short name T872
Test name
Test status
Simulation time 103061158 ps
CPU time 1.59 seconds
Started Jul 27 05:58:04 PM PDT 24
Finished Jul 27 05:58:05 PM PDT 24
Peak memory 218776 kb
Host smart-a7a7a126-a6d6-4b99-80d4-d83294ca660b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336762856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.336762856
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2573186104
Short name T431
Test name
Test status
Simulation time 71844522 ps
CPU time 1.41 seconds
Started Jul 27 05:58:11 PM PDT 24
Finished Jul 27 05:58:13 PM PDT 24
Peak memory 217316 kb
Host smart-aac16157-e110-4b0e-bde8-216623f93bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573186104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2573186104
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3213810606
Short name T716
Test name
Test status
Simulation time 60058746 ps
CPU time 1.06 seconds
Started Jul 27 05:58:02 PM PDT 24
Finished Jul 27 05:58:03 PM PDT 24
Peak memory 217200 kb
Host smart-022c2f7e-f127-485c-b55b-33feaaae5848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213810606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3213810606
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2964010520
Short name T358
Test name
Test status
Simulation time 53919935 ps
CPU time 1.38 seconds
Started Jul 27 05:57:57 PM PDT 24
Finished Jul 27 05:57:59 PM PDT 24
Peak memory 218488 kb
Host smart-7f43bb30-75fe-4e1d-b20a-7fc00d5fa7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964010520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2964010520
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1500863532
Short name T2
Test name
Test status
Simulation time 56788369 ps
CPU time 1.67 seconds
Started Jul 27 05:57:57 PM PDT 24
Finished Jul 27 05:57:59 PM PDT 24
Peak memory 218336 kb
Host smart-dc0ba7db-4722-4021-8ea4-958ca077d495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500863532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1500863532
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3647285991
Short name T620
Test name
Test status
Simulation time 74690741 ps
CPU time 1.22 seconds
Started Jul 27 05:56:46 PM PDT 24
Finished Jul 27 05:56:47 PM PDT 24
Peak memory 218600 kb
Host smart-af4833ce-0342-43fa-af11-de1595387070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647285991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3647285991
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3428180737
Short name T462
Test name
Test status
Simulation time 22734646 ps
CPU time 0.9 seconds
Started Jul 27 05:56:40 PM PDT 24
Finished Jul 27 05:56:41 PM PDT 24
Peak memory 206568 kb
Host smart-c53963e0-f04c-4d6f-9cdc-d8bae4abbf33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428180737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3428180737
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3690837197
Short name T33
Test name
Test status
Simulation time 12444074 ps
CPU time 0.88 seconds
Started Jul 27 05:56:20 PM PDT 24
Finished Jul 27 05:56:21 PM PDT 24
Peak memory 216436 kb
Host smart-04318974-5aa3-48d9-a5a0-437f65d67077
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690837197 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3690837197
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2841952350
Short name T349
Test name
Test status
Simulation time 44146737 ps
CPU time 1.06 seconds
Started Jul 27 05:56:13 PM PDT 24
Finished Jul 27 05:56:14 PM PDT 24
Peak memory 218484 kb
Host smart-bc20ff1f-05c0-479a-82ef-b08cf7e26192
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841952350 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2841952350
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3487247229
Short name T160
Test name
Test status
Simulation time 34440535 ps
CPU time 0.95 seconds
Started Jul 27 05:56:19 PM PDT 24
Finished Jul 27 05:56:20 PM PDT 24
Peak memory 219408 kb
Host smart-04ea1c93-3e5c-4274-b299-7b4f1c315d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487247229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3487247229
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.858810010
Short name T23
Test name
Test status
Simulation time 71116521 ps
CPU time 1.26 seconds
Started Jul 27 05:56:11 PM PDT 24
Finished Jul 27 05:56:12 PM PDT 24
Peak memory 219972 kb
Host smart-3e4f20a7-1fe6-40bd-b5c4-4829fc14c0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858810010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.858810010
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3120056102
Short name T570
Test name
Test status
Simulation time 23139467 ps
CPU time 1.19 seconds
Started Jul 27 05:56:11 PM PDT 24
Finished Jul 27 05:56:17 PM PDT 24
Peak memory 223984 kb
Host smart-eddd0387-309a-4453-95f0-dbbe5d06df9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120056102 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3120056102
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.231011580
Short name T981
Test name
Test status
Simulation time 27459477 ps
CPU time 0.96 seconds
Started Jul 27 05:56:11 PM PDT 24
Finished Jul 27 05:56:12 PM PDT 24
Peak memory 215080 kb
Host smart-e2030ec3-b6b9-4447-9e37-22a6958f50c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231011580 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.231011580
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1926950431
Short name T713
Test name
Test status
Simulation time 299117711 ps
CPU time 2.2 seconds
Started Jul 27 05:56:26 PM PDT 24
Finished Jul 27 05:56:28 PM PDT 24
Peak memory 220020 kb
Host smart-f541de49-f0a7-4de1-94d5-f0ac4e6b62f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926950431 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1926950431
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1565909599
Short name T861
Test name
Test status
Simulation time 23632337327 ps
CPU time 425.68 seconds
Started Jul 27 05:56:16 PM PDT 24
Finished Jul 27 06:03:21 PM PDT 24
Peak memory 223672 kb
Host smart-cf08570f-7e71-4d20-9f12-3fe2c4fa4702
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565909599 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1565909599
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3248959456
Short name T751
Test name
Test status
Simulation time 49228967 ps
CPU time 1.52 seconds
Started Jul 27 05:57:56 PM PDT 24
Finished Jul 27 05:57:58 PM PDT 24
Peak memory 218620 kb
Host smart-22559fce-8b94-4fb3-a9d1-bca69be8c765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248959456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3248959456
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3041370452
Short name T892
Test name
Test status
Simulation time 58835643 ps
CPU time 2.12 seconds
Started Jul 27 05:58:05 PM PDT 24
Finished Jul 27 05:58:08 PM PDT 24
Peak memory 218548 kb
Host smart-f973c6c1-3303-4556-9818-ebca7a4e8745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041370452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3041370452
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3392928460
Short name T782
Test name
Test status
Simulation time 54517613 ps
CPU time 1.04 seconds
Started Jul 27 05:58:03 PM PDT 24
Finished Jul 27 05:58:05 PM PDT 24
Peak memory 217204 kb
Host smart-91f41107-d0c4-4231-b203-754a0ade3ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392928460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3392928460
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.4276476034
Short name T13
Test name
Test status
Simulation time 42552990 ps
CPU time 1.53 seconds
Started Jul 27 05:58:02 PM PDT 24
Finished Jul 27 05:58:04 PM PDT 24
Peak memory 219776 kb
Host smart-ba6cea7c-364a-4c9e-b0a5-77d077377aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276476034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.4276476034
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2515473682
Short name T750
Test name
Test status
Simulation time 194856167 ps
CPU time 2.83 seconds
Started Jul 27 05:58:13 PM PDT 24
Finished Jul 27 05:58:16 PM PDT 24
Peak memory 219312 kb
Host smart-57337e5f-2a9e-4444-9de2-33a3c1d7d0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515473682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2515473682
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.450227463
Short name T38
Test name
Test status
Simulation time 83880012 ps
CPU time 1.15 seconds
Started Jul 27 05:57:55 PM PDT 24
Finished Jul 27 05:57:56 PM PDT 24
Peak memory 218236 kb
Host smart-9128fd24-d04c-4822-9f5d-f23c7ba0066d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450227463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.450227463
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3111578516
Short name T467
Test name
Test status
Simulation time 91564871 ps
CPU time 1.19 seconds
Started Jul 27 05:57:56 PM PDT 24
Finished Jul 27 05:57:57 PM PDT 24
Peak memory 217100 kb
Host smart-4ed9f30c-b03d-4f59-9f69-802fa443896b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111578516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3111578516
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3464648007
Short name T911
Test name
Test status
Simulation time 108051412 ps
CPU time 1.33 seconds
Started Jul 27 05:57:54 PM PDT 24
Finished Jul 27 05:57:55 PM PDT 24
Peak memory 217160 kb
Host smart-3d304a16-6d84-4afd-9fbb-679ace2d77a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464648007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3464648007
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2905665686
Short name T72
Test name
Test status
Simulation time 28539160 ps
CPU time 1.32 seconds
Started Jul 27 05:58:03 PM PDT 24
Finished Jul 27 05:58:05 PM PDT 24
Peak memory 217684 kb
Host smart-9fb4f756-de02-4830-86ed-8d203a9ebc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905665686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2905665686
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.851227260
Short name T746
Test name
Test status
Simulation time 83564393 ps
CPU time 1.21 seconds
Started Jul 27 05:58:10 PM PDT 24
Finished Jul 27 05:58:12 PM PDT 24
Peak memory 217216 kb
Host smart-b5ecd924-4b1b-4ea0-8739-2f6353492bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851227260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.851227260
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2191735129
Short name T516
Test name
Test status
Simulation time 145422377 ps
CPU time 1.07 seconds
Started Jul 27 05:56:09 PM PDT 24
Finished Jul 27 05:56:10 PM PDT 24
Peak memory 219372 kb
Host smart-a4e6c2bd-211e-4380-94e9-be66bde14aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191735129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2191735129
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.64800306
Short name T757
Test name
Test status
Simulation time 14211402 ps
CPU time 0.85 seconds
Started Jul 27 05:56:15 PM PDT 24
Finished Jul 27 05:56:16 PM PDT 24
Peak memory 206860 kb
Host smart-7e539418-0a5b-4ef4-8253-c6c79c1bba1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64800306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.64800306
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3217668543
Short name T109
Test name
Test status
Simulation time 12918396 ps
CPU time 0.91 seconds
Started Jul 27 05:56:11 PM PDT 24
Finished Jul 27 05:56:12 PM PDT 24
Peak memory 216304 kb
Host smart-c14a5c24-5b0b-4d0c-841f-354b7cf4cc56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217668543 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3217668543
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3192555682
Short name T177
Test name
Test status
Simulation time 62667464 ps
CPU time 1.04 seconds
Started Jul 27 05:56:22 PM PDT 24
Finished Jul 27 05:56:23 PM PDT 24
Peak memory 216640 kb
Host smart-a8c3b0ca-4ad2-42f3-9c12-ae104f470167
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192555682 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3192555682
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3467202729
Short name T9
Test name
Test status
Simulation time 41421297 ps
CPU time 1.18 seconds
Started Jul 27 05:56:11 PM PDT 24
Finished Jul 27 05:56:12 PM PDT 24
Peak memory 220472 kb
Host smart-b1f9c03d-f619-40d5-be92-5a099ead3040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467202729 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3467202729
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2983453909
Short name T317
Test name
Test status
Simulation time 316642439 ps
CPU time 4.05 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:14 PM PDT 24
Peak memory 218424 kb
Host smart-d6fe8133-9e7f-4d52-9edb-5ab8c9961b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983453909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2983453909
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.422755655
Short name T673
Test name
Test status
Simulation time 97496889 ps
CPU time 0.82 seconds
Started Jul 27 05:56:11 PM PDT 24
Finished Jul 27 05:56:12 PM PDT 24
Peak memory 215416 kb
Host smart-33e713fb-4ddc-4a6c-81e2-877e9910a3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422755655 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.422755655
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2107981511
Short name T398
Test name
Test status
Simulation time 28787364 ps
CPU time 0.91 seconds
Started Jul 27 05:56:09 PM PDT 24
Finished Jul 27 05:56:10 PM PDT 24
Peak memory 215176 kb
Host smart-128b5d5e-03c7-481c-b93e-7db25f313130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107981511 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2107981511
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3165050812
Short name T251
Test name
Test status
Simulation time 342016065 ps
CPU time 3.64 seconds
Started Jul 27 05:56:29 PM PDT 24
Finished Jul 27 05:56:33 PM PDT 24
Peak memory 218348 kb
Host smart-a9b8c994-ec52-4a31-8c55-3b215d6dc769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165050812 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3165050812
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2430943318
Short name T452
Test name
Test status
Simulation time 375383410927 ps
CPU time 1618.71 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 06:23:09 PM PDT 24
Peak memory 234356 kb
Host smart-cc6c526d-5a3d-4c22-b86c-3d05d98d0504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430943318 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2430943318
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1679217198
Short name T442
Test name
Test status
Simulation time 238068948 ps
CPU time 1.21 seconds
Started Jul 27 05:58:05 PM PDT 24
Finished Jul 27 05:58:06 PM PDT 24
Peak memory 219684 kb
Host smart-0e434018-ec82-485e-9df0-eab253fae6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679217198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1679217198
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.340366788
Short name T449
Test name
Test status
Simulation time 60811601 ps
CPU time 1.26 seconds
Started Jul 27 05:58:08 PM PDT 24
Finished Jul 27 05:58:09 PM PDT 24
Peak memory 218536 kb
Host smart-453df137-36fe-4ccd-91e7-484bb458980b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340366788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.340366788
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.810429406
Short name T844
Test name
Test status
Simulation time 40184496 ps
CPU time 1.39 seconds
Started Jul 27 05:57:53 PM PDT 24
Finished Jul 27 05:57:54 PM PDT 24
Peak memory 218288 kb
Host smart-91fb9f4c-db6b-4ac2-8844-cc30c3756e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810429406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.810429406
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2476749221
Short name T878
Test name
Test status
Simulation time 76628584 ps
CPU time 1.18 seconds
Started Jul 27 05:58:03 PM PDT 24
Finished Jul 27 05:58:04 PM PDT 24
Peak memory 218852 kb
Host smart-34cbdf0c-fd8f-4e0e-8332-2079c5792f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476749221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2476749221
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2686710620
Short name T893
Test name
Test status
Simulation time 125313950 ps
CPU time 1.09 seconds
Started Jul 27 05:57:59 PM PDT 24
Finished Jul 27 05:58:01 PM PDT 24
Peak memory 216736 kb
Host smart-fe3be153-3e8c-4511-b238-3a88e0c930c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686710620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2686710620
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3188840062
Short name T605
Test name
Test status
Simulation time 37171080 ps
CPU time 1.38 seconds
Started Jul 27 05:58:02 PM PDT 24
Finished Jul 27 05:58:04 PM PDT 24
Peak memory 218352 kb
Host smart-fb9b1ccc-bbdf-41cd-8fcd-a33306f5a1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188840062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3188840062
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3149956096
Short name T965
Test name
Test status
Simulation time 86469913 ps
CPU time 1.56 seconds
Started Jul 27 05:58:11 PM PDT 24
Finished Jul 27 05:58:13 PM PDT 24
Peak memory 218716 kb
Host smart-0a637a6d-0f3c-4076-9d28-4c85d0a128f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149956096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3149956096
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.4288717678
Short name T960
Test name
Test status
Simulation time 60356903 ps
CPU time 1.09 seconds
Started Jul 27 05:58:02 PM PDT 24
Finished Jul 27 05:58:03 PM PDT 24
Peak memory 219828 kb
Host smart-b8d4adca-cad4-4c84-b483-1cea2f7f42ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288717678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.4288717678
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.673731874
Short name T790
Test name
Test status
Simulation time 40697649 ps
CPU time 1.86 seconds
Started Jul 27 05:57:59 PM PDT 24
Finished Jul 27 05:58:01 PM PDT 24
Peak memory 218608 kb
Host smart-642a56e1-1c87-4b5b-b466-8aa21a35ad43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673731874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.673731874
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.938037341
Short name T632
Test name
Test status
Simulation time 27666460 ps
CPU time 1.26 seconds
Started Jul 27 05:58:09 PM PDT 24
Finished Jul 27 05:58:11 PM PDT 24
Peak memory 219888 kb
Host smart-28673e41-249a-4b3e-8649-666df708b7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938037341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.938037341
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.517291468
Short name T209
Test name
Test status
Simulation time 80708693 ps
CPU time 1.11 seconds
Started Jul 27 05:56:25 PM PDT 24
Finished Jul 27 05:56:26 PM PDT 24
Peak memory 219380 kb
Host smart-6837330f-70ae-4fcd-8d27-c954b15839f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517291468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.517291468
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3886456135
Short name T925
Test name
Test status
Simulation time 19512368 ps
CPU time 0.99 seconds
Started Jul 27 05:56:30 PM PDT 24
Finished Jul 27 05:56:31 PM PDT 24
Peak memory 206608 kb
Host smart-c26973cf-4c29-4ac0-9370-4a08f0894f8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886456135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3886456135
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1215020737
Short name T737
Test name
Test status
Simulation time 31814892 ps
CPU time 1.12 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 219420 kb
Host smart-9ef509e8-4a1a-418b-8f8c-3afff34c0d25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215020737 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1215020737
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.221819371
Short name T352
Test name
Test status
Simulation time 31997820 ps
CPU time 1.19 seconds
Started Jul 27 05:56:10 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 216856 kb
Host smart-211b70fc-fc58-4452-9b65-3e96662e1374
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221819371 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.221819371
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2125935165
Short name T792
Test name
Test status
Simulation time 25166593 ps
CPU time 0.96 seconds
Started Jul 27 05:56:13 PM PDT 24
Finished Jul 27 05:56:14 PM PDT 24
Peak memory 218704 kb
Host smart-65141331-c76e-4036-a10f-8b71b66f5e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125935165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2125935165
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2471586605
Short name T584
Test name
Test status
Simulation time 50819983 ps
CPU time 1.69 seconds
Started Jul 27 05:56:22 PM PDT 24
Finished Jul 27 05:56:23 PM PDT 24
Peak memory 218684 kb
Host smart-84539ea0-58e6-4eb4-a5ae-f0ed7e91de0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471586605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2471586605
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3858275013
Short name T439
Test name
Test status
Simulation time 32693349 ps
CPU time 0.89 seconds
Started Jul 27 05:56:09 PM PDT 24
Finished Jul 27 05:56:10 PM PDT 24
Peak memory 215536 kb
Host smart-245b6b53-0b54-4b7d-8ed6-3619abb92eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858275013 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3858275013
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1938712584
Short name T476
Test name
Test status
Simulation time 46166020 ps
CPU time 0.94 seconds
Started Jul 27 05:56:13 PM PDT 24
Finished Jul 27 05:56:14 PM PDT 24
Peak memory 215108 kb
Host smart-3467fff1-007d-4c6d-8a97-ebc13e171ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938712584 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1938712584
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1886808588
Short name T951
Test name
Test status
Simulation time 1262897265 ps
CPU time 4.93 seconds
Started Jul 27 05:56:12 PM PDT 24
Finished Jul 27 05:56:17 PM PDT 24
Peak memory 215112 kb
Host smart-03fda9b5-50e5-489a-8a58-82a411c9ff96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886808588 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1886808588
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1774390992
Short name T950
Test name
Test status
Simulation time 80150351442 ps
CPU time 1027.01 seconds
Started Jul 27 05:56:23 PM PDT 24
Finished Jul 27 06:13:30 PM PDT 24
Peak memory 223768 kb
Host smart-52c3364c-1940-4b4f-a092-40ff27671712
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774390992 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1774390992
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3293627454
Short name T360
Test name
Test status
Simulation time 120848068 ps
CPU time 1.24 seconds
Started Jul 27 05:57:59 PM PDT 24
Finished Jul 27 05:58:01 PM PDT 24
Peak memory 218496 kb
Host smart-4219c54a-9aec-4fd6-95d8-6b03f45f62d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293627454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3293627454
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2340050778
Short name T758
Test name
Test status
Simulation time 100954791 ps
CPU time 1.6 seconds
Started Jul 27 05:58:12 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 218620 kb
Host smart-b7bf204a-3cec-4909-b4e4-afa46d511ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340050778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2340050778
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1672927444
Short name T312
Test name
Test status
Simulation time 49923886 ps
CPU time 1.24 seconds
Started Jul 27 05:58:12 PM PDT 24
Finished Jul 27 05:58:13 PM PDT 24
Peak memory 217288 kb
Host smart-b4f4fa2b-3832-469a-84ca-a58a8fb8d1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672927444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1672927444
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1445152172
Short name T438
Test name
Test status
Simulation time 85808892 ps
CPU time 1.47 seconds
Started Jul 27 05:58:11 PM PDT 24
Finished Jul 27 05:58:13 PM PDT 24
Peak memory 218564 kb
Host smart-ffc41d9a-0869-41ab-9182-08e3b5bcb560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445152172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1445152172
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1643157965
Short name T615
Test name
Test status
Simulation time 113435281 ps
CPU time 1.25 seconds
Started Jul 27 05:57:51 PM PDT 24
Finished Jul 27 05:57:53 PM PDT 24
Peak memory 217124 kb
Host smart-fdce0433-ea82-41cb-aa9f-d3c3bb228021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643157965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1643157965
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.895417507
Short name T897
Test name
Test status
Simulation time 23587798 ps
CPU time 1.17 seconds
Started Jul 27 05:58:10 PM PDT 24
Finished Jul 27 05:58:12 PM PDT 24
Peak memory 219892 kb
Host smart-1b28d7d0-b6f3-4b4f-8716-5bbc6afdf816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895417507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.895417507
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.94990933
Short name T865
Test name
Test status
Simulation time 59607482 ps
CPU time 1.08 seconds
Started Jul 27 05:57:57 PM PDT 24
Finished Jul 27 05:57:58 PM PDT 24
Peak memory 217316 kb
Host smart-ddb10cfd-280f-4d12-bb82-60e9753f0d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94990933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.94990933
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.636053118
Short name T526
Test name
Test status
Simulation time 31295194 ps
CPU time 1.53 seconds
Started Jul 27 05:58:10 PM PDT 24
Finished Jul 27 05:58:12 PM PDT 24
Peak memory 217112 kb
Host smart-7a2c05a1-362c-4d03-81c0-a8649652abd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636053118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.636053118
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2863507822
Short name T554
Test name
Test status
Simulation time 34939494 ps
CPU time 1.39 seconds
Started Jul 27 05:58:03 PM PDT 24
Finished Jul 27 05:58:05 PM PDT 24
Peak memory 218504 kb
Host smart-2910376e-c79f-46d9-bb66-16394e9ea887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863507822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2863507822
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2192088300
Short name T455
Test name
Test status
Simulation time 45684189 ps
CPU time 1.23 seconds
Started Jul 27 05:56:12 PM PDT 24
Finished Jul 27 05:56:13 PM PDT 24
Peak memory 218336 kb
Host smart-850f3945-cd2d-41ec-b2eb-6965b13f9a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192088300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2192088300
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2348655351
Short name T945
Test name
Test status
Simulation time 20197601 ps
CPU time 0.95 seconds
Started Jul 27 05:56:31 PM PDT 24
Finished Jul 27 05:56:32 PM PDT 24
Peak memory 214796 kb
Host smart-63fa26d9-e9e7-46e5-a3c7-cda7e74e4823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348655351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2348655351
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.102297270
Short name T947
Test name
Test status
Simulation time 21058897 ps
CPU time 0.91 seconds
Started Jul 27 05:56:18 PM PDT 24
Finished Jul 27 05:56:19 PM PDT 24
Peak memory 215804 kb
Host smart-3acb856e-77ae-4986-a598-b22cfac183af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102297270 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.102297270
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3467364051
Short name T639
Test name
Test status
Simulation time 57533163 ps
CPU time 1.38 seconds
Started Jul 27 05:56:27 PM PDT 24
Finished Jul 27 05:56:34 PM PDT 24
Peak memory 216804 kb
Host smart-f99a4345-eebb-4a96-bacf-7d9e08aaca22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467364051 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3467364051
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_genbits.746882278
Short name T35
Test name
Test status
Simulation time 24318835 ps
CPU time 1.2 seconds
Started Jul 27 05:56:26 PM PDT 24
Finished Jul 27 05:56:32 PM PDT 24
Peak memory 216988 kb
Host smart-71f9e9a9-1b01-4b17-8984-c5fe82007da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746882278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.746882278
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3564098985
Short name T643
Test name
Test status
Simulation time 30719567 ps
CPU time 0.97 seconds
Started Jul 27 05:56:12 PM PDT 24
Finished Jul 27 05:56:13 PM PDT 24
Peak memory 215332 kb
Host smart-b1a6271e-3ebf-4520-97b9-93dbda256067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564098985 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3564098985
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1745349155
Short name T921
Test name
Test status
Simulation time 54176827 ps
CPU time 0.89 seconds
Started Jul 27 05:56:26 PM PDT 24
Finished Jul 27 05:56:27 PM PDT 24
Peak memory 214908 kb
Host smart-e6a5bf56-3deb-446a-95d3-9d38b36e2018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745349155 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1745349155
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1943864204
Short name T686
Test name
Test status
Simulation time 165232714 ps
CPU time 2.15 seconds
Started Jul 27 05:56:29 PM PDT 24
Finished Jul 27 05:56:31 PM PDT 24
Peak memory 217140 kb
Host smart-ee8da74b-6801-4dd0-9b18-076800a703d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943864204 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1943864204
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2368992647
Short name T424
Test name
Test status
Simulation time 72823336038 ps
CPU time 1739.06 seconds
Started Jul 27 05:56:26 PM PDT 24
Finished Jul 27 06:25:25 PM PDT 24
Peak memory 227420 kb
Host smart-4faf73d8-376c-4f09-8004-d3763efd0580
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368992647 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2368992647
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2405343861
Short name T804
Test name
Test status
Simulation time 36940415 ps
CPU time 1.64 seconds
Started Jul 27 05:58:12 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 218256 kb
Host smart-cc0b61ac-8054-46a8-b2df-cf94b2c18228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405343861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2405343861
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.221279424
Short name T499
Test name
Test status
Simulation time 43484136 ps
CPU time 1.41 seconds
Started Jul 27 05:58:11 PM PDT 24
Finished Jul 27 05:58:13 PM PDT 24
Peak memory 218484 kb
Host smart-a6ef005e-5529-4a7b-a4d3-07501f66581a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221279424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.221279424
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2391063144
Short name T823
Test name
Test status
Simulation time 205000688 ps
CPU time 2.9 seconds
Started Jul 27 05:58:11 PM PDT 24
Finished Jul 27 05:58:15 PM PDT 24
Peak memory 220168 kb
Host smart-ce8159e6-a0bb-4ef2-ada9-a050382c6154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391063144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2391063144
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.242887166
Short name T39
Test name
Test status
Simulation time 83936506 ps
CPU time 1.39 seconds
Started Jul 27 05:58:14 PM PDT 24
Finished Jul 27 05:58:16 PM PDT 24
Peak memory 217248 kb
Host smart-c9047892-7cd8-4f7f-be32-9b956baa6237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242887166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.242887166
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2316652775
Short name T934
Test name
Test status
Simulation time 81469346 ps
CPU time 1.17 seconds
Started Jul 27 05:58:12 PM PDT 24
Finished Jul 27 05:58:13 PM PDT 24
Peak memory 218256 kb
Host smart-51620f15-0b2e-4978-928c-7fdf6d2fe6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316652775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2316652775
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2457567036
Short name T397
Test name
Test status
Simulation time 67020961 ps
CPU time 1.36 seconds
Started Jul 27 05:58:06 PM PDT 24
Finished Jul 27 05:58:08 PM PDT 24
Peak memory 217352 kb
Host smart-ff1f9a7b-0ffa-4e02-b0f7-0e105593b8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457567036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2457567036
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1245154298
Short name T322
Test name
Test status
Simulation time 38160820 ps
CPU time 1.53 seconds
Started Jul 27 05:58:02 PM PDT 24
Finished Jul 27 05:58:03 PM PDT 24
Peak memory 218368 kb
Host smart-14ad7278-a3b3-4349-957c-f250d19910c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245154298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1245154298
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.137307955
Short name T718
Test name
Test status
Simulation time 41448275 ps
CPU time 1.28 seconds
Started Jul 27 05:58:05 PM PDT 24
Finished Jul 27 05:58:07 PM PDT 24
Peak memory 215156 kb
Host smart-1b916274-1916-4af9-96d8-885e458dbd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137307955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.137307955
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3145574276
Short name T648
Test name
Test status
Simulation time 65306649 ps
CPU time 1.09 seconds
Started Jul 27 05:58:04 PM PDT 24
Finished Jul 27 05:58:05 PM PDT 24
Peak memory 217232 kb
Host smart-c893af5c-acf5-4e23-97d0-f47965a8d659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145574276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3145574276
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.622931680
Short name T448
Test name
Test status
Simulation time 74215526 ps
CPU time 1.09 seconds
Started Jul 27 05:58:10 PM PDT 24
Finished Jul 27 05:58:11 PM PDT 24
Peak memory 217204 kb
Host smart-b9e25b34-69ce-4c05-ae31-f6edf01de811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622931680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.622931680
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.519345497
Short name T794
Test name
Test status
Simulation time 41027081 ps
CPU time 1.06 seconds
Started Jul 27 05:56:23 PM PDT 24
Finished Jul 27 05:56:24 PM PDT 24
Peak memory 219712 kb
Host smart-2b254228-0771-4097-9e17-a6338211875a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519345497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.519345497
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2722018116
Short name T54
Test name
Test status
Simulation time 21751308 ps
CPU time 1.07 seconds
Started Jul 27 05:56:18 PM PDT 24
Finished Jul 27 05:56:19 PM PDT 24
Peak memory 206940 kb
Host smart-8f4cb994-484c-46a7-83b9-e7cb56398403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722018116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2722018116
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.889692790
Short name T107
Test name
Test status
Simulation time 12707489 ps
CPU time 0.92 seconds
Started Jul 27 05:56:24 PM PDT 24
Finished Jul 27 05:56:25 PM PDT 24
Peak memory 216304 kb
Host smart-d1ad1924-0bec-4087-b6fd-916bb97c4ee7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889692790 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.889692790
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3745434111
Short name T129
Test name
Test status
Simulation time 54144449 ps
CPU time 1.33 seconds
Started Jul 27 05:56:37 PM PDT 24
Finished Jul 27 05:56:38 PM PDT 24
Peak memory 216912 kb
Host smart-a95b6642-3650-4287-be49-0bffcfe32b4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745434111 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3745434111
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1962603685
Short name T768
Test name
Test status
Simulation time 122449549 ps
CPU time 1.38 seconds
Started Jul 27 05:56:21 PM PDT 24
Finished Jul 27 05:56:23 PM PDT 24
Peak memory 225652 kb
Host smart-86dc35bd-1017-4e2e-a11c-48af4b221ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962603685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1962603685
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1595043412
Short name T457
Test name
Test status
Simulation time 28428881 ps
CPU time 1.24 seconds
Started Jul 27 05:56:26 PM PDT 24
Finished Jul 27 05:56:27 PM PDT 24
Peak memory 218196 kb
Host smart-506421fd-456b-4044-9292-01f15205ffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595043412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1595043412
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2754583009
Short name T882
Test name
Test status
Simulation time 23178176 ps
CPU time 1.17 seconds
Started Jul 27 05:56:24 PM PDT 24
Finished Jul 27 05:56:25 PM PDT 24
Peak memory 215428 kb
Host smart-ddc903ee-ba3f-4b23-ab65-5e5bc78a603d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754583009 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2754583009
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.4145047922
Short name T134
Test name
Test status
Simulation time 20519642 ps
CPU time 1.04 seconds
Started Jul 27 05:56:28 PM PDT 24
Finished Jul 27 05:56:29 PM PDT 24
Peak memory 215180 kb
Host smart-7aa053ca-5f02-4096-8d55-ea66c2182e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145047922 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.4145047922
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3935765769
Short name T246
Test name
Test status
Simulation time 154429523 ps
CPU time 3.28 seconds
Started Jul 27 05:56:26 PM PDT 24
Finished Jul 27 05:56:29 PM PDT 24
Peak memory 217104 kb
Host smart-71a13cfe-4529-4423-87a1-ea6e8e6037eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935765769 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3935765769
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1239138128
Short name T228
Test name
Test status
Simulation time 79633044846 ps
CPU time 1733.3 seconds
Started Jul 27 05:56:28 PM PDT 24
Finished Jul 27 06:25:21 PM PDT 24
Peak memory 225604 kb
Host smart-151cbd66-a499-4c15-818e-3e5b5e817416
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239138128 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1239138128
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3265990604
Short name T316
Test name
Test status
Simulation time 61861609 ps
CPU time 1.41 seconds
Started Jul 27 05:58:13 PM PDT 24
Finished Jul 27 05:58:15 PM PDT 24
Peak memory 220096 kb
Host smart-23479c17-0d21-4355-86e1-d25da49bda18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265990604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3265990604
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2281516896
Short name T412
Test name
Test status
Simulation time 50854349 ps
CPU time 1.76 seconds
Started Jul 27 05:57:58 PM PDT 24
Finished Jul 27 05:58:00 PM PDT 24
Peak memory 218432 kb
Host smart-cb50286c-2636-4795-b854-2633cf05ca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281516896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2281516896
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3006091843
Short name T407
Test name
Test status
Simulation time 68755634 ps
CPU time 1.07 seconds
Started Jul 27 05:58:02 PM PDT 24
Finished Jul 27 05:58:03 PM PDT 24
Peak memory 217196 kb
Host smart-df7f17a5-d601-4f41-8dc9-6bf4b6201305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006091843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3006091843
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1315643724
Short name T630
Test name
Test status
Simulation time 69868512 ps
CPU time 1.4 seconds
Started Jul 27 05:58:04 PM PDT 24
Finished Jul 27 05:58:05 PM PDT 24
Peak memory 217160 kb
Host smart-5abcb3d0-8607-405c-af35-196390b6eb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315643724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1315643724
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1096944750
Short name T601
Test name
Test status
Simulation time 269811841 ps
CPU time 1.11 seconds
Started Jul 27 05:58:13 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 217164 kb
Host smart-0feeba19-5c44-42fe-9d8d-4bcc79c2e0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096944750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1096944750
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2955920661
Short name T875
Test name
Test status
Simulation time 58508039 ps
CPU time 1.47 seconds
Started Jul 27 05:58:10 PM PDT 24
Finished Jul 27 05:58:11 PM PDT 24
Peak memory 218652 kb
Host smart-8374f461-4e43-40c3-8fd1-4a021988cd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955920661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2955920661
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1002386481
Short name T326
Test name
Test status
Simulation time 257251168 ps
CPU time 3.58 seconds
Started Jul 27 05:58:01 PM PDT 24
Finished Jul 27 05:58:05 PM PDT 24
Peak memory 220020 kb
Host smart-f314c04c-4366-4154-adc8-43bb40fceff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002386481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1002386481
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2541870217
Short name T334
Test name
Test status
Simulation time 62065865 ps
CPU time 1.24 seconds
Started Jul 27 05:58:03 PM PDT 24
Finished Jul 27 05:58:05 PM PDT 24
Peak memory 218784 kb
Host smart-9be58ce0-ec35-4b9b-877d-377c301ac9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541870217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2541870217
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.957156456
Short name T332
Test name
Test status
Simulation time 57865382 ps
CPU time 1.28 seconds
Started Jul 27 05:58:06 PM PDT 24
Finished Jul 27 05:58:08 PM PDT 24
Peak memory 219672 kb
Host smart-47c02903-8719-439d-8796-96bd5e80a4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957156456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.957156456
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.53285892
Short name T858
Test name
Test status
Simulation time 47327036 ps
CPU time 1.25 seconds
Started Jul 27 05:58:06 PM PDT 24
Finished Jul 27 05:58:08 PM PDT 24
Peak memory 219856 kb
Host smart-e1a797b3-9dd2-4ac2-bf3a-d1ebf0d661ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53285892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.53285892
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.724228023
Short name T218
Test name
Test status
Simulation time 76811334 ps
CPU time 1.23 seconds
Started Jul 27 05:56:21 PM PDT 24
Finished Jul 27 05:56:22 PM PDT 24
Peak memory 218488 kb
Host smart-5963e70d-a59a-435b-883d-9ebb6ad7d9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724228023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.724228023
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1049365154
Short name T254
Test name
Test status
Simulation time 29415071 ps
CPU time 0.95 seconds
Started Jul 27 05:56:29 PM PDT 24
Finished Jul 27 05:56:30 PM PDT 24
Peak memory 215064 kb
Host smart-7a9f479e-0db2-42a2-b647-3f5241d449ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049365154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1049365154
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2225625247
Short name T562
Test name
Test status
Simulation time 11650894 ps
CPU time 0.88 seconds
Started Jul 27 05:56:21 PM PDT 24
Finished Jul 27 05:56:22 PM PDT 24
Peak memory 215912 kb
Host smart-e2605be5-8568-4856-a5a9-186738ec800e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225625247 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2225625247
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.4034641945
Short name T936
Test name
Test status
Simulation time 22885481 ps
CPU time 1.02 seconds
Started Jul 27 05:56:26 PM PDT 24
Finished Jul 27 05:56:27 PM PDT 24
Peak memory 216732 kb
Host smart-365777e4-702a-47e9-acc2-9dd1bbf9e149
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034641945 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.4034641945
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.574355314
Short name T993
Test name
Test status
Simulation time 18405117 ps
CPU time 1.06 seconds
Started Jul 27 05:56:19 PM PDT 24
Finished Jul 27 05:56:20 PM PDT 24
Peak memory 218608 kb
Host smart-e63f7e20-c9f6-43dd-b695-8201e622fd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574355314 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.574355314
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_intr.2447093249
Short name T851
Test name
Test status
Simulation time 24075990 ps
CPU time 1.03 seconds
Started Jul 27 05:56:23 PM PDT 24
Finished Jul 27 05:56:24 PM PDT 24
Peak memory 215264 kb
Host smart-8fd48cab-a405-4ca9-8b15-a5e5420263b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447093249 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2447093249
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1158329800
Short name T381
Test name
Test status
Simulation time 18477165 ps
CPU time 0.98 seconds
Started Jul 27 05:56:19 PM PDT 24
Finished Jul 27 05:56:21 PM PDT 24
Peak memory 215364 kb
Host smart-9614adde-6671-4720-8c78-9f6a5a1b289c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158329800 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1158329800
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3979525086
Short name T350
Test name
Test status
Simulation time 904951950 ps
CPU time 5.31 seconds
Started Jul 27 05:56:32 PM PDT 24
Finished Jul 27 05:56:37 PM PDT 24
Peak memory 216940 kb
Host smart-7849106e-d1a2-4598-ae0a-809bf34d9a19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979525086 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3979525086
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3087292051
Short name T447
Test name
Test status
Simulation time 101185795444 ps
CPU time 1760.02 seconds
Started Jul 27 05:56:30 PM PDT 24
Finished Jul 27 06:25:50 PM PDT 24
Peak memory 228432 kb
Host smart-9532b6d6-53af-4f54-8527-eb3eaabd830b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087292051 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3087292051
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2386338713
Short name T829
Test name
Test status
Simulation time 105578891 ps
CPU time 1.23 seconds
Started Jul 27 05:58:08 PM PDT 24
Finished Jul 27 05:58:09 PM PDT 24
Peak memory 218952 kb
Host smart-753fbd3c-5531-4407-9be4-6d35701637ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386338713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2386338713
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.481556854
Short name T387
Test name
Test status
Simulation time 81789455 ps
CPU time 1.6 seconds
Started Jul 27 05:57:59 PM PDT 24
Finished Jul 27 05:58:01 PM PDT 24
Peak memory 218860 kb
Host smart-c871a655-9c07-441b-a8f1-5b1fd206fb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481556854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.481556854
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.271182287
Short name T403
Test name
Test status
Simulation time 70581494 ps
CPU time 1.35 seconds
Started Jul 27 05:58:10 PM PDT 24
Finished Jul 27 05:58:12 PM PDT 24
Peak memory 218528 kb
Host smart-7287765c-8a2b-4bef-9909-398f56519410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271182287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.271182287
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.699410151
Short name T624
Test name
Test status
Simulation time 46617919 ps
CPU time 1.3 seconds
Started Jul 27 05:58:09 PM PDT 24
Finished Jul 27 05:58:10 PM PDT 24
Peak memory 218560 kb
Host smart-365904a4-ab2f-4b97-953e-7ce592eaf2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699410151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.699410151
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.2738458707
Short name T371
Test name
Test status
Simulation time 42115556 ps
CPU time 1.43 seconds
Started Jul 27 05:58:03 PM PDT 24
Finished Jul 27 05:58:05 PM PDT 24
Peak memory 219088 kb
Host smart-c7f24a95-b497-48e4-9774-ce47cad2802f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738458707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2738458707
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2239088505
Short name T491
Test name
Test status
Simulation time 31075760 ps
CPU time 1.22 seconds
Started Jul 27 05:58:04 PM PDT 24
Finished Jul 27 05:58:05 PM PDT 24
Peak memory 217148 kb
Host smart-a418615f-4367-4bd1-8f60-54949a661a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239088505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2239088505
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3054222472
Short name T807
Test name
Test status
Simulation time 77517115 ps
CPU time 1.26 seconds
Started Jul 27 05:58:04 PM PDT 24
Finished Jul 27 05:58:05 PM PDT 24
Peak memory 218748 kb
Host smart-bab895f5-508c-4ebd-a05e-69347d83639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054222472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3054222472
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3864098085
Short name T846
Test name
Test status
Simulation time 41162581 ps
CPU time 1.18 seconds
Started Jul 27 05:57:58 PM PDT 24
Finished Jul 27 05:57:59 PM PDT 24
Peak memory 217092 kb
Host smart-ff6621d5-15a4-4c48-827f-f23b6d4f03ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864098085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3864098085
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3951372395
Short name T987
Test name
Test status
Simulation time 59630428 ps
CPU time 1.29 seconds
Started Jul 27 05:58:10 PM PDT 24
Finished Jul 27 05:58:11 PM PDT 24
Peak memory 219200 kb
Host smart-76f4a425-55cd-4075-b989-0a40ee5433cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951372395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3951372395
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1312859956
Short name T671
Test name
Test status
Simulation time 63951835 ps
CPU time 1.4 seconds
Started Jul 27 05:58:03 PM PDT 24
Finished Jul 27 05:58:05 PM PDT 24
Peak memory 218440 kb
Host smart-85634c74-5c3a-4db2-ab57-5e8ee79b3626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312859956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1312859956
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1759532732
Short name T353
Test name
Test status
Simulation time 44145257 ps
CPU time 1.26 seconds
Started Jul 27 05:56:28 PM PDT 24
Finished Jul 27 05:56:29 PM PDT 24
Peak memory 215524 kb
Host smart-5eed296a-0226-4364-b6d5-d5e52ebc357d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759532732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1759532732
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.4023214235
Short name T140
Test name
Test status
Simulation time 22014256 ps
CPU time 0.85 seconds
Started Jul 27 05:56:17 PM PDT 24
Finished Jul 27 05:56:18 PM PDT 24
Peak memory 206648 kb
Host smart-8b77f24a-7794-4bc4-8bc4-db6d80c80c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023214235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.4023214235
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2791961145
Short name T91
Test name
Test status
Simulation time 13966637 ps
CPU time 0.96 seconds
Started Jul 27 05:56:31 PM PDT 24
Finished Jul 27 05:56:32 PM PDT 24
Peak memory 216248 kb
Host smart-0b513763-af57-4d19-a98d-12e784756561
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791961145 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2791961145
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1298746064
Short name T523
Test name
Test status
Simulation time 25877817 ps
CPU time 0.94 seconds
Started Jul 27 05:56:18 PM PDT 24
Finished Jul 27 05:56:19 PM PDT 24
Peak memory 218228 kb
Host smart-cc991d44-a86d-4890-9f52-bf9dda9e1b9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298746064 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1298746064
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_genbits.2684349284
Short name T566
Test name
Test status
Simulation time 39168460 ps
CPU time 1.81 seconds
Started Jul 27 05:56:30 PM PDT 24
Finished Jul 27 05:56:32 PM PDT 24
Peak memory 217104 kb
Host smart-04df8efa-44e8-42f7-8199-fb54f7d7c0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684349284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2684349284
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3062420487
Short name T845
Test name
Test status
Simulation time 24273362 ps
CPU time 0.93 seconds
Started Jul 27 05:56:30 PM PDT 24
Finished Jul 27 05:56:31 PM PDT 24
Peak memory 215412 kb
Host smart-16c0eb83-450d-410b-8b2c-81cd75efca24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062420487 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3062420487
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2587746563
Short name T355
Test name
Test status
Simulation time 29165667 ps
CPU time 0.94 seconds
Started Jul 27 05:56:22 PM PDT 24
Finished Jul 27 05:56:23 PM PDT 24
Peak memory 215124 kb
Host smart-a4e5540e-ff69-4f69-9b81-3f2224e58811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587746563 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2587746563
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1335040525
Short name T606
Test name
Test status
Simulation time 285880225 ps
CPU time 6.29 seconds
Started Jul 27 05:56:18 PM PDT 24
Finished Jul 27 05:56:25 PM PDT 24
Peak memory 218312 kb
Host smart-c2f9641b-6054-41f1-b505-3c0c51189557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335040525 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1335040525
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.84639189
Short name T560
Test name
Test status
Simulation time 58866098228 ps
CPU time 1301.02 seconds
Started Jul 27 05:56:24 PM PDT 24
Finished Jul 27 06:18:05 PM PDT 24
Peak memory 222072 kb
Host smart-8a9334ae-9e49-4f37-8117-92f7559a2b54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84639189 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.84639189
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1967131442
Short name T787
Test name
Test status
Simulation time 82258551 ps
CPU time 1.11 seconds
Started Jul 27 05:58:09 PM PDT 24
Finished Jul 27 05:58:10 PM PDT 24
Peak memory 217216 kb
Host smart-d5f0f1eb-6590-446a-9bf7-2ccda8e2556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967131442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1967131442
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3152354998
Short name T484
Test name
Test status
Simulation time 41863099 ps
CPU time 1.63 seconds
Started Jul 27 05:58:10 PM PDT 24
Finished Jul 27 05:58:11 PM PDT 24
Peak memory 219056 kb
Host smart-dd42a0d9-8018-4153-a5db-42f6d3ee380a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152354998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3152354998
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1765639754
Short name T28
Test name
Test status
Simulation time 56586460 ps
CPU time 1.22 seconds
Started Jul 27 05:58:00 PM PDT 24
Finished Jul 27 05:58:02 PM PDT 24
Peak memory 215188 kb
Host smart-fca962ab-37a5-4abe-8ea4-0229cf4fb412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765639754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1765639754
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3235007611
Short name T990
Test name
Test status
Simulation time 119465827 ps
CPU time 1.02 seconds
Started Jul 27 05:58:09 PM PDT 24
Finished Jul 27 05:58:10 PM PDT 24
Peak memory 217344 kb
Host smart-c9004943-009e-4d10-885f-cda9193483fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235007611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3235007611
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1662461706
Short name T731
Test name
Test status
Simulation time 37237165 ps
CPU time 1.26 seconds
Started Jul 27 05:58:06 PM PDT 24
Finished Jul 27 05:58:07 PM PDT 24
Peak memory 217532 kb
Host smart-0e28f2d8-11cd-49d1-a10f-df85b65e68e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662461706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1662461706
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2577790629
Short name T443
Test name
Test status
Simulation time 67421561 ps
CPU time 1.22 seconds
Started Jul 27 05:58:05 PM PDT 24
Finished Jul 27 05:58:07 PM PDT 24
Peak memory 218960 kb
Host smart-17f15ece-c3b0-4984-be73-7e66bddf32ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577790629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2577790629
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.975297497
Short name T25
Test name
Test status
Simulation time 35755858 ps
CPU time 1.32 seconds
Started Jul 27 05:58:12 PM PDT 24
Finished Jul 27 05:58:14 PM PDT 24
Peak memory 219804 kb
Host smart-aac4b752-f32e-4d86-b006-72a59e5eb9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975297497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.975297497
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.974160259
Short name T608
Test name
Test status
Simulation time 49760057 ps
CPU time 1.37 seconds
Started Jul 27 05:58:03 PM PDT 24
Finished Jul 27 05:58:04 PM PDT 24
Peak memory 220124 kb
Host smart-41f90803-5653-44bb-9710-75f444966b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974160259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.974160259
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3698919218
Short name T793
Test name
Test status
Simulation time 35874428 ps
CPU time 1.38 seconds
Started Jul 27 05:58:10 PM PDT 24
Finished Jul 27 05:58:11 PM PDT 24
Peak memory 218764 kb
Host smart-c5260957-9d27-4694-a300-7d2548fca7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698919218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3698919218
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.43999394
Short name T388
Test name
Test status
Simulation time 41196047 ps
CPU time 1.21 seconds
Started Jul 27 05:56:26 PM PDT 24
Finished Jul 27 05:56:27 PM PDT 24
Peak memory 220304 kb
Host smart-44d91a82-8c78-40ad-9f66-11d1fbd44cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43999394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.43999394
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1478441550
Short name T557
Test name
Test status
Simulation time 34871149 ps
CPU time 1.03 seconds
Started Jul 27 05:56:26 PM PDT 24
Finished Jul 27 05:56:27 PM PDT 24
Peak memory 206792 kb
Host smart-390bde0e-b031-4534-b8b8-65bb34997e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478441550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1478441550
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2218308572
Short name T105
Test name
Test status
Simulation time 43146420 ps
CPU time 0.85 seconds
Started Jul 27 05:56:20 PM PDT 24
Finished Jul 27 05:56:21 PM PDT 24
Peak memory 216012 kb
Host smart-751f353f-d5e0-47b7-aba0-222d0a64e6e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218308572 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2218308572
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1076442045
Short name T840
Test name
Test status
Simulation time 36465187 ps
CPU time 1.28 seconds
Started Jul 27 05:56:21 PM PDT 24
Finished Jul 27 05:56:22 PM PDT 24
Peak memory 216892 kb
Host smart-79506539-6e18-416e-8c4a-5832b9867076
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076442045 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1076442045
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3146423487
Short name T117
Test name
Test status
Simulation time 18662023 ps
CPU time 1.05 seconds
Started Jul 27 05:56:33 PM PDT 24
Finished Jul 27 05:56:35 PM PDT 24
Peak memory 218244 kb
Host smart-0ab73cd7-0245-4810-bd63-1a31f9e7745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146423487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3146423487
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.348191975
Short name T471
Test name
Test status
Simulation time 34637680 ps
CPU time 1.05 seconds
Started Jul 27 05:56:23 PM PDT 24
Finished Jul 27 05:56:24 PM PDT 24
Peak memory 218452 kb
Host smart-382b7b99-8369-47ad-b477-23e489b196da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348191975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.348191975
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.328593209
Short name T852
Test name
Test status
Simulation time 21584299 ps
CPU time 1.09 seconds
Started Jul 27 05:56:33 PM PDT 24
Finished Jul 27 05:56:34 PM PDT 24
Peak memory 215288 kb
Host smart-26868c4e-c5e3-4631-bf22-a087fd236cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328593209 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.328593209
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1261095369
Short name T776
Test name
Test status
Simulation time 52090002 ps
CPU time 1.04 seconds
Started Jul 27 05:56:34 PM PDT 24
Finished Jul 27 05:56:35 PM PDT 24
Peak memory 215160 kb
Host smart-3e91cab2-1c3e-46eb-9d89-e11f32832cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261095369 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1261095369
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3823722870
Short name T744
Test name
Test status
Simulation time 346774567 ps
CPU time 6.44 seconds
Started Jul 27 05:56:22 PM PDT 24
Finished Jul 27 05:56:28 PM PDT 24
Peak memory 216992 kb
Host smart-3b6d9fd5-1612-4992-b266-8e6787aa0f47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823722870 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3823722870
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3378489124
Short name T655
Test name
Test status
Simulation time 59246580564 ps
CPU time 335.23 seconds
Started Jul 27 05:56:31 PM PDT 24
Finished Jul 27 06:02:06 PM PDT 24
Peak memory 223576 kb
Host smart-f4e58014-d7ae-4e98-823e-895b03f5d00d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378489124 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3378489124
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2923338334
Short name T31
Test name
Test status
Simulation time 40466327 ps
CPU time 1.51 seconds
Started Jul 27 05:58:10 PM PDT 24
Finished Jul 27 05:58:12 PM PDT 24
Peak memory 218452 kb
Host smart-d0b2a894-d24a-4bae-9e5b-9ceb9f20b45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923338334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2923338334
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3221279927
Short name T497
Test name
Test status
Simulation time 56291025 ps
CPU time 1.02 seconds
Started Jul 27 05:58:07 PM PDT 24
Finished Jul 27 05:58:08 PM PDT 24
Peak memory 217308 kb
Host smart-f0662d95-847a-4fdb-b48f-42914271e07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221279927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3221279927
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.455340426
Short name T429
Test name
Test status
Simulation time 92421619 ps
CPU time 1.4 seconds
Started Jul 27 05:58:11 PM PDT 24
Finished Jul 27 05:58:12 PM PDT 24
Peak memory 218840 kb
Host smart-9638c3ab-3f16-4fc7-a1db-2e0c35fce15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455340426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.455340426
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3207996305
Short name T621
Test name
Test status
Simulation time 55686623 ps
CPU time 1.42 seconds
Started Jul 27 05:58:05 PM PDT 24
Finished Jul 27 05:58:06 PM PDT 24
Peak memory 218420 kb
Host smart-ab419795-7625-4a61-83ff-35a03b9d4546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207996305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3207996305
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3727420130
Short name T85
Test name
Test status
Simulation time 43448917 ps
CPU time 1.22 seconds
Started Jul 27 05:58:07 PM PDT 24
Finished Jul 27 05:58:08 PM PDT 24
Peak memory 219632 kb
Host smart-cb9f54de-3db3-40f2-b6f4-b5d6145a5f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727420130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3727420130
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.68863555
Short name T521
Test name
Test status
Simulation time 120152544 ps
CPU time 1.82 seconds
Started Jul 27 05:58:08 PM PDT 24
Finished Jul 27 05:58:10 PM PDT 24
Peak memory 218660 kb
Host smart-31188c8e-63fd-4c6f-ac6e-6eb192729389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68863555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.68863555
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.4101955849
Short name T440
Test name
Test status
Simulation time 49470806 ps
CPU time 1.66 seconds
Started Jul 27 05:58:35 PM PDT 24
Finished Jul 27 05:58:37 PM PDT 24
Peak memory 217412 kb
Host smart-8a6114e1-6e5c-44f0-8d9f-a650ea75a778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101955849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.4101955849
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3723590119
Short name T645
Test name
Test status
Simulation time 44943217 ps
CPU time 0.96 seconds
Started Jul 27 05:58:15 PM PDT 24
Finished Jul 27 05:58:17 PM PDT 24
Peak memory 217352 kb
Host smart-a4fd5dca-8a01-47c9-948d-bfce6f0f0a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723590119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3723590119
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2568219769
Short name T629
Test name
Test status
Simulation time 277843814 ps
CPU time 3.54 seconds
Started Jul 27 05:58:14 PM PDT 24
Finished Jul 27 05:58:17 PM PDT 24
Peak memory 219072 kb
Host smart-8370af39-6bfa-477c-8c7a-05b08408ed21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568219769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2568219769
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2406283670
Short name T810
Test name
Test status
Simulation time 40296587 ps
CPU time 1.39 seconds
Started Jul 27 05:58:13 PM PDT 24
Finished Jul 27 05:58:15 PM PDT 24
Peak memory 219884 kb
Host smart-a9b382bd-8c97-4208-98af-0345211d4d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406283670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2406283670
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.64351154
Short name T425
Test name
Test status
Simulation time 24482846 ps
CPU time 1.25 seconds
Started Jul 27 05:55:38 PM PDT 24
Finished Jul 27 05:55:39 PM PDT 24
Peak memory 218984 kb
Host smart-e94175ff-fca6-466f-b7a2-a20efa8cebcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64351154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.64351154
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3832315181
Short name T252
Test name
Test status
Simulation time 26514601 ps
CPU time 0.88 seconds
Started Jul 27 05:55:48 PM PDT 24
Finished Jul 27 05:55:49 PM PDT 24
Peak memory 214816 kb
Host smart-3ce0f9ba-4bf2-4360-923c-5609317f2b82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832315181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3832315181
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1145036561
Short name T68
Test name
Test status
Simulation time 52792186 ps
CPU time 0.86 seconds
Started Jul 27 05:55:40 PM PDT 24
Finished Jul 27 05:55:40 PM PDT 24
Peak memory 216184 kb
Host smart-ec8c3c25-69cf-4377-b311-bb84ffaebda0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145036561 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1145036561
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2050485505
Short name T125
Test name
Test status
Simulation time 60984324 ps
CPU time 1.05 seconds
Started Jul 27 05:55:38 PM PDT 24
Finished Jul 27 05:55:39 PM PDT 24
Peak memory 216840 kb
Host smart-4d288395-5de6-4966-8375-714c9285d507
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050485505 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2050485505
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2982253782
Short name T692
Test name
Test status
Simulation time 35158485 ps
CPU time 1.19 seconds
Started Jul 27 05:55:39 PM PDT 24
Finished Jul 27 05:55:40 PM PDT 24
Peak memory 223836 kb
Host smart-983598fd-fde5-4642-8854-bd4ebf287235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982253782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2982253782
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3851521502
Short name T609
Test name
Test status
Simulation time 61584383 ps
CPU time 1.3 seconds
Started Jul 27 05:55:49 PM PDT 24
Finished Jul 27 05:55:51 PM PDT 24
Peak memory 218260 kb
Host smart-f2c27835-f3d2-469a-bad4-d5b3990fcdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851521502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3851521502
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3717220141
Short name T420
Test name
Test status
Simulation time 61023775 ps
CPU time 0.91 seconds
Started Jul 27 05:55:50 PM PDT 24
Finished Jul 27 05:55:51 PM PDT 24
Peak memory 215100 kb
Host smart-714e6af2-2e50-4e64-83db-fae647d7d99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717220141 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3717220141
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3399029837
Short name T652
Test name
Test status
Simulation time 14424052 ps
CPU time 0.97 seconds
Started Jul 27 05:55:42 PM PDT 24
Finished Jul 27 05:55:43 PM PDT 24
Peak memory 206964 kb
Host smart-9889128f-7a88-472a-8ef5-1cc9aac3ca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399029837 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3399029837
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.2663887357
Short name T930
Test name
Test status
Simulation time 27320638 ps
CPU time 0.93 seconds
Started Jul 27 05:55:37 PM PDT 24
Finished Jul 27 05:55:39 PM PDT 24
Peak memory 215156 kb
Host smart-d076387b-0021-410d-aa0c-2c8e9fc9097f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663887357 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2663887357
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3239377103
Short name T589
Test name
Test status
Simulation time 96070986 ps
CPU time 1.5 seconds
Started Jul 27 05:55:39 PM PDT 24
Finished Jul 27 05:55:40 PM PDT 24
Peak memory 206884 kb
Host smart-eee286cc-23f6-4f84-9128-e758ba5fa274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239377103 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3239377103
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1818162087
Short name T780
Test name
Test status
Simulation time 106526981352 ps
CPU time 1882.91 seconds
Started Jul 27 05:55:38 PM PDT 24
Finished Jul 27 06:27:02 PM PDT 24
Peak memory 226856 kb
Host smart-f6a74136-6223-45df-b05a-0201b8aca4ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818162087 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1818162087
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.4253915120
Short name T796
Test name
Test status
Simulation time 28260550 ps
CPU time 1.33 seconds
Started Jul 27 05:56:44 PM PDT 24
Finished Jul 27 05:56:46 PM PDT 24
Peak memory 218488 kb
Host smart-5cff8703-4437-4d0e-8857-02cedeccd9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253915120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.4253915120
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3657589180
Short name T376
Test name
Test status
Simulation time 18381824 ps
CPU time 0.99 seconds
Started Jul 27 05:56:28 PM PDT 24
Finished Jul 27 05:56:29 PM PDT 24
Peak memory 214820 kb
Host smart-86669332-31fa-4a28-a778-a4f3eb6f32bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657589180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3657589180
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1140449080
Short name T831
Test name
Test status
Simulation time 18033297 ps
CPU time 0.85 seconds
Started Jul 27 05:56:45 PM PDT 24
Finished Jul 27 05:56:46 PM PDT 24
Peak memory 215816 kb
Host smart-46a3bfe5-ef4a-4a0d-8b8b-67581f6d316b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140449080 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1140449080
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1929657669
Short name T115
Test name
Test status
Simulation time 108766776 ps
CPU time 1.23 seconds
Started Jul 27 05:56:31 PM PDT 24
Finished Jul 27 05:56:32 PM PDT 24
Peak memory 216840 kb
Host smart-1d4de68f-6e47-4982-bfe9-88161800278f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929657669 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1929657669
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3872997768
Short name T106
Test name
Test status
Simulation time 25524116 ps
CPU time 1.23 seconds
Started Jul 27 05:56:25 PM PDT 24
Finished Jul 27 05:56:26 PM PDT 24
Peak memory 219828 kb
Host smart-5fc80559-a617-4060-a85d-2a701e1accb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872997768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3872997768
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2222006052
Short name T755
Test name
Test status
Simulation time 43300671 ps
CPU time 1.45 seconds
Started Jul 27 05:56:23 PM PDT 24
Finished Jul 27 05:56:25 PM PDT 24
Peak memory 217048 kb
Host smart-e1b7f8d4-9ff4-41ae-81b6-e110a09e948f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222006052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2222006052
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3578459227
Short name T507
Test name
Test status
Simulation time 21090005 ps
CPU time 1.16 seconds
Started Jul 27 05:56:30 PM PDT 24
Finished Jul 27 05:56:31 PM PDT 24
Peak memory 215420 kb
Host smart-308cc1a9-43ab-4778-a8f7-f8ea8a15fac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578459227 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3578459227
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3359025581
Short name T580
Test name
Test status
Simulation time 53264268 ps
CPU time 0.94 seconds
Started Jul 27 05:56:23 PM PDT 24
Finished Jul 27 05:56:24 PM PDT 24
Peak memory 215140 kb
Host smart-f1da0ab7-31c8-476e-a54d-d8276daf15cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359025581 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3359025581
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1470059117
Short name T547
Test name
Test status
Simulation time 263791259 ps
CPU time 1.61 seconds
Started Jul 27 05:56:36 PM PDT 24
Finished Jul 27 05:56:38 PM PDT 24
Peak memory 220016 kb
Host smart-d2192e7b-6aa6-4ddd-a563-07d816dba632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470059117 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1470059117
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.916646865
Short name T239
Test name
Test status
Simulation time 88369704089 ps
CPU time 964.9 seconds
Started Jul 27 05:56:32 PM PDT 24
Finished Jul 27 06:12:37 PM PDT 24
Peak memory 220880 kb
Host smart-a9dbabc9-202a-4041-9fe9-d979083fa9cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916646865 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.916646865
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.4073498387
Short name T868
Test name
Test status
Simulation time 103697418 ps
CPU time 1.17 seconds
Started Jul 27 05:56:24 PM PDT 24
Finished Jul 27 05:56:25 PM PDT 24
Peak memory 219684 kb
Host smart-cab8909b-8213-46e3-838a-b7187a445f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073498387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.4073498387
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2042968646
Short name T869
Test name
Test status
Simulation time 32255145 ps
CPU time 0.93 seconds
Started Jul 27 05:56:26 PM PDT 24
Finished Jul 27 05:56:27 PM PDT 24
Peak memory 206512 kb
Host smart-a6eb10e4-1770-4f38-87ca-20833a44566d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042968646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2042968646
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2404877949
Short name T706
Test name
Test status
Simulation time 24717557 ps
CPU time 0.85 seconds
Started Jul 27 05:56:42 PM PDT 24
Finished Jul 27 05:56:43 PM PDT 24
Peak memory 215812 kb
Host smart-bd32ed68-6585-43d7-a879-80f4f557f157
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404877949 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2404877949
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3123937480
Short name T155
Test name
Test status
Simulation time 40157217 ps
CPU time 1.34 seconds
Started Jul 27 05:56:32 PM PDT 24
Finished Jul 27 05:56:34 PM PDT 24
Peak memory 216976 kb
Host smart-3de9d27d-f1d2-47b2-86eb-7b0a51029279
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123937480 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3123937480
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2624030571
Short name T146
Test name
Test status
Simulation time 49723097 ps
CPU time 1.14 seconds
Started Jul 27 05:56:32 PM PDT 24
Finished Jul 27 05:56:34 PM PDT 24
Peak memory 229512 kb
Host smart-b42b8b69-be5d-453f-ae09-8abaeb31e0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624030571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2624030571
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.611239036
Short name T602
Test name
Test status
Simulation time 77764773 ps
CPU time 1.04 seconds
Started Jul 27 05:56:32 PM PDT 24
Finished Jul 27 05:56:33 PM PDT 24
Peak memory 217188 kb
Host smart-bfa0558d-0d6d-40e6-a380-43eef32f6e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611239036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.611239036
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3266843589
Short name T985
Test name
Test status
Simulation time 20920025 ps
CPU time 1.07 seconds
Started Jul 27 05:56:35 PM PDT 24
Finished Jul 27 05:56:36 PM PDT 24
Peak memory 215756 kb
Host smart-459bba21-88a5-4fc7-96e1-af86f35fa931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266843589 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3266843589
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.952725922
Short name T853
Test name
Test status
Simulation time 42150991 ps
CPU time 0.85 seconds
Started Jul 27 05:56:41 PM PDT 24
Finished Jul 27 05:56:42 PM PDT 24
Peak memory 206928 kb
Host smart-b4e9c5d8-0b1b-40c0-80c0-a0863d0fe258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952725922 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.952725922
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1443891515
Short name T612
Test name
Test status
Simulation time 228212253 ps
CPU time 4.69 seconds
Started Jul 27 05:56:32 PM PDT 24
Finished Jul 27 05:56:37 PM PDT 24
Peak memory 219888 kb
Host smart-54c5165c-969d-45d9-adba-1438746051bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443891515 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1443891515
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3699247014
Short name T394
Test name
Test status
Simulation time 30122206773 ps
CPU time 377.3 seconds
Started Jul 27 05:56:36 PM PDT 24
Finished Jul 27 06:02:53 PM PDT 24
Peak memory 218316 kb
Host smart-0d066f82-b5be-43f3-9cc9-7a13b833da5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699247014 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3699247014
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1550575905
Short name T170
Test name
Test status
Simulation time 79061278 ps
CPU time 1.1 seconds
Started Jul 27 05:56:30 PM PDT 24
Finished Jul 27 05:56:31 PM PDT 24
Peak memory 220468 kb
Host smart-abd24c41-4663-43f9-8380-6107116e8fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550575905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1550575905
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3424511977
Short name T939
Test name
Test status
Simulation time 68821137 ps
CPU time 0.92 seconds
Started Jul 27 05:56:29 PM PDT 24
Finished Jul 27 05:56:30 PM PDT 24
Peak memory 206740 kb
Host smart-79704f6e-7a4d-4652-b661-a24a3588b49c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424511977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3424511977
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1342854702
Short name T208
Test name
Test status
Simulation time 25204227 ps
CPU time 0.89 seconds
Started Jul 27 05:56:32 PM PDT 24
Finished Jul 27 05:56:33 PM PDT 24
Peak memory 216088 kb
Host smart-1a9690da-214a-4be3-9764-bef29a8f483f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342854702 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1342854702
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.352080355
Short name T380
Test name
Test status
Simulation time 234875348 ps
CPU time 1.09 seconds
Started Jul 27 05:56:38 PM PDT 24
Finished Jul 27 05:56:39 PM PDT 24
Peak memory 216876 kb
Host smart-d76f7714-19b4-499b-8a0d-f6b7da52fdf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352080355 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.352080355
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2086376680
Short name T110
Test name
Test status
Simulation time 33742061 ps
CPU time 1.15 seconds
Started Jul 27 05:56:33 PM PDT 24
Finished Jul 27 05:56:34 PM PDT 24
Peak memory 219488 kb
Host smart-ce3ea78b-82c4-4198-8127-95d1108a9258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086376680 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2086376680
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.857243989
Short name T297
Test name
Test status
Simulation time 30516319 ps
CPU time 1.19 seconds
Started Jul 27 05:56:31 PM PDT 24
Finished Jul 27 05:56:32 PM PDT 24
Peak memory 217084 kb
Host smart-f4f0bdd1-41df-4ec7-a98a-97f43da24d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857243989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.857243989
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3594221144
Short name T373
Test name
Test status
Simulation time 41729438 ps
CPU time 0.88 seconds
Started Jul 27 05:56:29 PM PDT 24
Finished Jul 27 05:56:30 PM PDT 24
Peak memory 215312 kb
Host smart-493f5827-c9ff-4479-93ff-08406ed518ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594221144 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3594221144
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2320734600
Short name T735
Test name
Test status
Simulation time 24222755 ps
CPU time 0.91 seconds
Started Jul 27 05:56:30 PM PDT 24
Finished Jul 27 05:56:31 PM PDT 24
Peak memory 215192 kb
Host smart-decabd58-9ae2-49c3-954c-7244418a06db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320734600 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2320734600
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1791414185
Short name T680
Test name
Test status
Simulation time 180976326 ps
CPU time 3.96 seconds
Started Jul 27 05:56:47 PM PDT 24
Finished Jul 27 05:56:51 PM PDT 24
Peak memory 216920 kb
Host smart-52d66856-9749-4f5d-8960-738bb93c51e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791414185 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1791414185
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3856790190
Short name T235
Test name
Test status
Simulation time 42830954424 ps
CPU time 677.33 seconds
Started Jul 27 05:56:33 PM PDT 24
Finished Jul 27 06:07:51 PM PDT 24
Peak memory 220380 kb
Host smart-9f9800a4-6a4c-4dfd-8b21-6a073ddab98b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856790190 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3856790190
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.233961990
Short name T190
Test name
Test status
Simulation time 26804861 ps
CPU time 1.12 seconds
Started Jul 27 05:56:30 PM PDT 24
Finished Jul 27 05:56:31 PM PDT 24
Peak memory 219472 kb
Host smart-cd95e49f-0911-4f99-b17e-28060f3354cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233961990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.233961990
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.133503712
Short name T783
Test name
Test status
Simulation time 25089735 ps
CPU time 0.93 seconds
Started Jul 27 05:56:37 PM PDT 24
Finished Jul 27 05:56:38 PM PDT 24
Peak memory 214768 kb
Host smart-9e80215a-1fe3-4c87-a09e-67ed6ddf0928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133503712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.133503712
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2437254348
Short name T529
Test name
Test status
Simulation time 13790749 ps
CPU time 0.93 seconds
Started Jul 27 05:56:32 PM PDT 24
Finished Jul 27 05:56:33 PM PDT 24
Peak memory 216080 kb
Host smart-512e9ef1-7598-4125-94c5-c409b32ee470
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437254348 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2437254348
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.42238742
Short name T933
Test name
Test status
Simulation time 33433465 ps
CPU time 1.24 seconds
Started Jul 27 05:56:32 PM PDT 24
Finished Jul 27 05:56:34 PM PDT 24
Peak memory 216748 kb
Host smart-8de44a30-5140-4b56-be86-c08f31f66205
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42238742 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_dis
able_auto_req_mode.42238742
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2985770673
Short name T833
Test name
Test status
Simulation time 20579514 ps
CPU time 1.08 seconds
Started Jul 27 05:56:30 PM PDT 24
Finished Jul 27 05:56:31 PM PDT 24
Peak memory 218572 kb
Host smart-0da85bac-3599-4fda-8b90-37f9a42dc828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985770673 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2985770673
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.4043918620
Short name T299
Test name
Test status
Simulation time 68313284 ps
CPU time 1.24 seconds
Started Jul 27 05:56:27 PM PDT 24
Finished Jul 27 05:56:29 PM PDT 24
Peak memory 218360 kb
Host smart-55d821e2-6417-4b2c-beac-838231414e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043918620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.4043918620
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2346673743
Short name T395
Test name
Test status
Simulation time 61307160 ps
CPU time 0.85 seconds
Started Jul 27 05:56:37 PM PDT 24
Finished Jul 27 05:56:38 PM PDT 24
Peak memory 215208 kb
Host smart-9942c2bb-6c39-40fd-9881-e16e864e649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346673743 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2346673743
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.4109396735
Short name T637
Test name
Test status
Simulation time 19956389 ps
CPU time 1.02 seconds
Started Jul 27 05:56:30 PM PDT 24
Finished Jul 27 05:56:31 PM PDT 24
Peak memory 215168 kb
Host smart-9a9c7034-ad18-40ca-b9ba-f52ceff4e4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109396735 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.4109396735
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2878601367
Short name T250
Test name
Test status
Simulation time 408576569 ps
CPU time 3.24 seconds
Started Jul 27 05:56:34 PM PDT 24
Finished Jul 27 05:56:37 PM PDT 24
Peak memory 218524 kb
Host smart-c818528d-8ee4-4965-8318-ae92032c756f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878601367 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2878601367
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2412692842
Short name T382
Test name
Test status
Simulation time 202773844364 ps
CPU time 1273.2 seconds
Started Jul 27 05:56:34 PM PDT 24
Finished Jul 27 06:17:48 PM PDT 24
Peak memory 225444 kb
Host smart-1a6e562f-7b01-406b-a4e9-6188cdf805c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412692842 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2412692842
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1933302231
Short name T202
Test name
Test status
Simulation time 48496323 ps
CPU time 1.18 seconds
Started Jul 27 05:56:45 PM PDT 24
Finished Jul 27 05:56:46 PM PDT 24
Peak memory 218360 kb
Host smart-31c175be-0129-46af-b4d9-057b4ee7f332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933302231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1933302231
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2145988393
Short name T919
Test name
Test status
Simulation time 19285659 ps
CPU time 1.06 seconds
Started Jul 27 05:56:37 PM PDT 24
Finished Jul 27 05:56:38 PM PDT 24
Peak memory 206708 kb
Host smart-0f3024f4-2961-4475-bb9b-7832d9332ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145988393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2145988393
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1633957767
Short name T184
Test name
Test status
Simulation time 46183128 ps
CPU time 0.88 seconds
Started Jul 27 05:56:33 PM PDT 24
Finished Jul 27 05:56:34 PM PDT 24
Peak memory 207024 kb
Host smart-c7cb8372-d0ce-441d-9ba1-00b11398d5aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633957767 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1633957767
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.3911610375
Short name T446
Test name
Test status
Simulation time 19513515 ps
CPU time 1.17 seconds
Started Jul 27 05:56:34 PM PDT 24
Finished Jul 27 05:56:35 PM PDT 24
Peak memory 218468 kb
Host smart-b4c49da1-b43a-4a15-91a3-2d6f60470c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911610375 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3911610375
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.460382408
Short name T434
Test name
Test status
Simulation time 216789797 ps
CPU time 1.22 seconds
Started Jul 27 05:56:50 PM PDT 24
Finished Jul 27 05:56:51 PM PDT 24
Peak memory 217460 kb
Host smart-c7b25583-e97a-48c3-be3d-4869581d6cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460382408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.460382408
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2846957624
Short name T77
Test name
Test status
Simulation time 31231221 ps
CPU time 0.84 seconds
Started Jul 27 05:56:38 PM PDT 24
Finished Jul 27 05:56:39 PM PDT 24
Peak memory 215684 kb
Host smart-5a00728e-65f0-4af2-93e9-0c7710f1f400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846957624 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2846957624
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.697030417
Short name T422
Test name
Test status
Simulation time 35082962 ps
CPU time 0.99 seconds
Started Jul 27 05:56:45 PM PDT 24
Finished Jul 27 05:56:46 PM PDT 24
Peak memory 215172 kb
Host smart-63185485-7ca4-4af1-a556-42acee6dea08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697030417 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.697030417
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.4273077507
Short name T408
Test name
Test status
Simulation time 857101980 ps
CPU time 5.33 seconds
Started Jul 27 05:56:41 PM PDT 24
Finished Jul 27 05:56:47 PM PDT 24
Peak memory 217068 kb
Host smart-e4362881-82a4-4003-916e-c3bf94dd03de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273077507 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.4273077507
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.99719207
Short name T843
Test name
Test status
Simulation time 223776101206 ps
CPU time 1269.37 seconds
Started Jul 27 05:56:36 PM PDT 24
Finished Jul 27 06:17:46 PM PDT 24
Peak memory 223768 kb
Host smart-8f7f47b7-7325-4409-a850-2553aeba3bac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99719207 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.99719207
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1077586333
Short name T567
Test name
Test status
Simulation time 52627792 ps
CPU time 1.3 seconds
Started Jul 27 05:56:34 PM PDT 24
Finished Jul 27 05:56:36 PM PDT 24
Peak memory 219996 kb
Host smart-88e9cfb8-7b6d-491c-8b46-0690b8a0ff03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077586333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1077586333
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1676094525
Short name T383
Test name
Test status
Simulation time 15845549 ps
CPU time 0.96 seconds
Started Jul 27 05:56:33 PM PDT 24
Finished Jul 27 05:56:34 PM PDT 24
Peak memory 206620 kb
Host smart-829f04ae-b8e2-42eb-9b47-20dbc85b9989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676094525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1676094525
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3560180396
Short name T699
Test name
Test status
Simulation time 11668943 ps
CPU time 0.91 seconds
Started Jul 27 05:56:38 PM PDT 24
Finished Jul 27 05:56:39 PM PDT 24
Peak memory 216184 kb
Host smart-bf2544fd-07c4-494f-9947-072f5f0eb893
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560180396 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3560180396
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1795676794
Short name T374
Test name
Test status
Simulation time 92148408 ps
CPU time 1.19 seconds
Started Jul 27 05:56:33 PM PDT 24
Finished Jul 27 05:56:34 PM PDT 24
Peak memory 219740 kb
Host smart-b39c9818-e0ce-43dc-8f8f-8b091f600bf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795676794 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1795676794
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.992294165
Short name T17
Test name
Test status
Simulation time 32610532 ps
CPU time 1.17 seconds
Started Jul 27 05:56:47 PM PDT 24
Finished Jul 27 05:56:48 PM PDT 24
Peak memory 229444 kb
Host smart-2fe92c5a-f97d-4638-8cdd-0f5d32fef485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992294165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.992294165
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1290437336
Short name T889
Test name
Test status
Simulation time 82771787 ps
CPU time 1.18 seconds
Started Jul 27 05:56:30 PM PDT 24
Finished Jul 27 05:56:32 PM PDT 24
Peak memory 220020 kb
Host smart-0251d03e-31de-44b0-a816-499dff489e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290437336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1290437336
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3415729369
Short name T795
Test name
Test status
Simulation time 38281536 ps
CPU time 0.97 seconds
Started Jul 27 05:56:32 PM PDT 24
Finished Jul 27 05:56:33 PM PDT 24
Peak memory 215260 kb
Host smart-a60c0daa-a41a-4d14-9b8a-5280f2e1a1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415729369 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3415729369
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2102323009
Short name T887
Test name
Test status
Simulation time 18103193 ps
CPU time 1.06 seconds
Started Jul 27 05:56:36 PM PDT 24
Finished Jul 27 05:56:37 PM PDT 24
Peak memory 215100 kb
Host smart-3b82560b-6772-4ce3-8db9-a1f5494e331b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102323009 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2102323009
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3529711313
Short name T42
Test name
Test status
Simulation time 1473925057 ps
CPU time 4.35 seconds
Started Jul 27 05:56:34 PM PDT 24
Finished Jul 27 05:56:38 PM PDT 24
Peak memory 219724 kb
Host smart-88684ff8-89d7-449d-8a8c-cbe66070b0d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529711313 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3529711313
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2056055380
Short name T675
Test name
Test status
Simulation time 20411326451 ps
CPU time 526.14 seconds
Started Jul 27 05:56:32 PM PDT 24
Finished Jul 27 06:05:19 PM PDT 24
Peak memory 223552 kb
Host smart-96c08391-1cf3-4c6f-ad1e-da54da6200c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056055380 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2056055380
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert_test.3233217943
Short name T888
Test name
Test status
Simulation time 44675046 ps
CPU time 0.94 seconds
Started Jul 27 05:56:40 PM PDT 24
Finished Jul 27 05:56:41 PM PDT 24
Peak memory 214800 kb
Host smart-64059c14-a843-4859-b978-d5ec6b74a966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233217943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3233217943
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3385465806
Short name T119
Test name
Test status
Simulation time 37448373 ps
CPU time 0.86 seconds
Started Jul 27 05:56:37 PM PDT 24
Finished Jul 27 05:56:38 PM PDT 24
Peak memory 216192 kb
Host smart-cd72f1ae-2f08-4b71-afd5-91abf8e5818c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385465806 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3385465806
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.4012072970
Short name T642
Test name
Test status
Simulation time 44220594 ps
CPU time 1.1 seconds
Started Jul 27 05:56:32 PM PDT 24
Finished Jul 27 05:56:33 PM PDT 24
Peak memory 216672 kb
Host smart-be127893-3cf3-4cfd-b739-10fed373cde1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012072970 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.4012072970
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.4182897155
Short name T49
Test name
Test status
Simulation time 19838767 ps
CPU time 1.17 seconds
Started Jul 27 05:56:31 PM PDT 24
Finished Jul 27 05:56:33 PM PDT 24
Peak memory 224092 kb
Host smart-292f0cf2-4428-4e55-b8d9-8c87aa25d1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182897155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.4182897155
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3043784152
Short name T298
Test name
Test status
Simulation time 64558934 ps
CPU time 1.04 seconds
Started Jul 27 05:56:39 PM PDT 24
Finished Jul 27 05:56:40 PM PDT 24
Peak memory 219468 kb
Host smart-ad89836b-2fc9-494c-b0ef-5e23be63d694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043784152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3043784152
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2990839236
Short name T80
Test name
Test status
Simulation time 32961727 ps
CPU time 0.89 seconds
Started Jul 27 05:56:34 PM PDT 24
Finished Jul 27 05:56:35 PM PDT 24
Peak memory 215528 kb
Host smart-ffdc5cb5-1a6b-49a2-b323-6136ddb26b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990839236 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2990839236
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.33713097
Short name T711
Test name
Test status
Simulation time 18488399 ps
CPU time 1.07 seconds
Started Jul 27 05:56:41 PM PDT 24
Finished Jul 27 05:56:42 PM PDT 24
Peak memory 215120 kb
Host smart-b7bf84c1-4fd5-4adb-bd78-25a4532c0bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33713097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.33713097
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3744573288
Short name T714
Test name
Test status
Simulation time 69163366 ps
CPU time 1.63 seconds
Started Jul 27 05:56:34 PM PDT 24
Finished Jul 27 05:56:36 PM PDT 24
Peak memory 217032 kb
Host smart-b77244a0-bd4d-4214-bbc1-37f77c23ef62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744573288 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3744573288
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.553094299
Short name T765
Test name
Test status
Simulation time 185615940858 ps
CPU time 1184.69 seconds
Started Jul 27 05:56:34 PM PDT 24
Finished Jul 27 06:16:19 PM PDT 24
Peak memory 222884 kb
Host smart-b5280b7f-b484-432b-886e-4b872394dfc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553094299 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.553094299
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.407597996
Short name T571
Test name
Test status
Simulation time 86437106 ps
CPU time 1.18 seconds
Started Jul 27 05:56:43 PM PDT 24
Finished Jul 27 05:56:44 PM PDT 24
Peak memory 219588 kb
Host smart-3de504ae-e78d-4d82-a909-06a81019ee9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407597996 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.407597996
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2240613808
Short name T444
Test name
Test status
Simulation time 149239818 ps
CPU time 0.88 seconds
Started Jul 27 05:56:56 PM PDT 24
Finished Jul 27 05:56:57 PM PDT 24
Peak memory 206652 kb
Host smart-fa56395b-6b17-417e-b879-ad7621020ffa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240613808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2240613808
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2118976188
Short name T104
Test name
Test status
Simulation time 13887361 ps
CPU time 0.95 seconds
Started Jul 27 05:56:47 PM PDT 24
Finished Jul 27 05:56:48 PM PDT 24
Peak memory 216308 kb
Host smart-e87310f2-b4c5-428b-803c-9203ffaf8da7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118976188 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2118976188
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.4097331823
Short name T617
Test name
Test status
Simulation time 62666571 ps
CPU time 1.4 seconds
Started Jul 27 05:56:43 PM PDT 24
Finished Jul 27 05:56:45 PM PDT 24
Peak memory 216812 kb
Host smart-8f9f7015-672e-47b9-a571-3c5f96109fb8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097331823 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.4097331823
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3837057516
Short name T912
Test name
Test status
Simulation time 30595904 ps
CPU time 0.92 seconds
Started Jul 27 05:56:41 PM PDT 24
Finished Jul 27 05:56:42 PM PDT 24
Peak memory 218400 kb
Host smart-5c79e14e-6b79-4ad3-9bb0-fcfb270eaa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837057516 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3837057516
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3544196227
Short name T979
Test name
Test status
Simulation time 45809626 ps
CPU time 1.41 seconds
Started Jul 27 05:56:42 PM PDT 24
Finished Jul 27 05:56:43 PM PDT 24
Peak memory 218572 kb
Host smart-cca6fa51-dc89-4cbe-b08c-2dec816625da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544196227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3544196227
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_smoke.4029712110
Short name T559
Test name
Test status
Simulation time 14681904 ps
CPU time 0.96 seconds
Started Jul 27 05:56:38 PM PDT 24
Finished Jul 27 05:56:39 PM PDT 24
Peak memory 215192 kb
Host smart-cb6d355d-6c73-4576-a142-a1eb82ddda50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029712110 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.4029712110
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2164840527
Short name T809
Test name
Test status
Simulation time 190044096 ps
CPU time 2.4 seconds
Started Jul 27 05:56:58 PM PDT 24
Finished Jul 27 05:57:00 PM PDT 24
Peak memory 216940 kb
Host smart-ac4891ee-b5cc-48fd-8f89-870deebd2f6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164840527 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2164840527
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2637026912
Short name T241
Test name
Test status
Simulation time 56063695492 ps
CPU time 1186.84 seconds
Started Jul 27 05:56:52 PM PDT 24
Finished Jul 27 06:16:39 PM PDT 24
Peak memory 221120 kb
Host smart-45284a8c-ee2a-417e-b6a4-0f089276c49e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637026912 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2637026912
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.2292036175
Short name T258
Test name
Test status
Simulation time 28044135 ps
CPU time 1.25 seconds
Started Jul 27 05:56:43 PM PDT 24
Finished Jul 27 05:56:44 PM PDT 24
Peak memory 220592 kb
Host smart-623bc04f-255c-49fe-899f-42c273ef7f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292036175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2292036175
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.328431371
Short name T723
Test name
Test status
Simulation time 27569514 ps
CPU time 0.89 seconds
Started Jul 27 05:56:42 PM PDT 24
Finished Jul 27 05:56:44 PM PDT 24
Peak memory 206752 kb
Host smart-e5efdaa6-8418-4e72-a993-09ddf796d109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328431371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.328431371
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3786951012
Short name T818
Test name
Test status
Simulation time 16934767 ps
CPU time 0.86 seconds
Started Jul 27 05:56:39 PM PDT 24
Finished Jul 27 05:56:40 PM PDT 24
Peak memory 216080 kb
Host smart-304b6acc-8696-4c7b-b088-bd2d501dc503
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786951012 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3786951012
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1866627217
Short name T413
Test name
Test status
Simulation time 101728628 ps
CPU time 1.1 seconds
Started Jul 27 05:56:47 PM PDT 24
Finished Jul 27 05:56:48 PM PDT 24
Peak memory 216776 kb
Host smart-90124a8c-60fe-461f-9611-89d829758d41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866627217 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1866627217
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1711193199
Short name T659
Test name
Test status
Simulation time 18052316 ps
CPU time 1.05 seconds
Started Jul 27 05:56:39 PM PDT 24
Finished Jul 27 05:56:41 PM PDT 24
Peak memory 218144 kb
Host smart-cd5519d8-23d7-42f7-a505-ad539c05ede3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711193199 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1711193199
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.4012952033
Short name T552
Test name
Test status
Simulation time 48203282 ps
CPU time 1.86 seconds
Started Jul 27 05:56:51 PM PDT 24
Finished Jul 27 05:56:53 PM PDT 24
Peak memory 218744 kb
Host smart-dfc30fe8-6d2c-49f9-83e3-f041e6a6c549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012952033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.4012952033
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3313484819
Short name T822
Test name
Test status
Simulation time 46773886 ps
CPU time 0.95 seconds
Started Jul 27 05:57:02 PM PDT 24
Finished Jul 27 05:57:03 PM PDT 24
Peak memory 215260 kb
Host smart-546e6781-184e-4072-99a7-0e520595b806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313484819 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3313484819
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3039487807
Short name T573
Test name
Test status
Simulation time 44912132 ps
CPU time 0.93 seconds
Started Jul 27 05:56:42 PM PDT 24
Finished Jul 27 05:56:43 PM PDT 24
Peak memory 215156 kb
Host smart-e0516c9c-83a7-4cd1-82ab-38c648cd6aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039487807 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3039487807
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1767339114
Short name T579
Test name
Test status
Simulation time 435734958 ps
CPU time 5.18 seconds
Started Jul 27 05:57:01 PM PDT 24
Finished Jul 27 05:57:06 PM PDT 24
Peak memory 218308 kb
Host smart-6d9854d1-cd55-4cbf-849f-6fa99050d572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767339114 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1767339114
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2819905651
Short name T715
Test name
Test status
Simulation time 100869541023 ps
CPU time 1654.73 seconds
Started Jul 27 05:56:39 PM PDT 24
Finished Jul 27 06:24:14 PM PDT 24
Peak memory 225168 kb
Host smart-89b581ac-6725-48f6-9159-2b2b95f4d0fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819905651 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2819905651
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1617954869
Short name T473
Test name
Test status
Simulation time 36025306 ps
CPU time 1.28 seconds
Started Jul 27 05:56:49 PM PDT 24
Finished Jul 27 05:56:50 PM PDT 24
Peak memory 220984 kb
Host smart-d927b6ac-b5fc-4bb6-bdf9-20d26dfb493f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617954869 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1617954869
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1566677194
Short name T972
Test name
Test status
Simulation time 39188924 ps
CPU time 0.95 seconds
Started Jul 27 05:56:57 PM PDT 24
Finished Jul 27 05:56:58 PM PDT 24
Peak memory 215076 kb
Host smart-e8425a5d-0e61-416d-885b-02e3a01caf20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566677194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1566677194
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1294631301
Short name T879
Test name
Test status
Simulation time 13055413 ps
CPU time 0.92 seconds
Started Jul 27 05:56:41 PM PDT 24
Finished Jul 27 05:56:42 PM PDT 24
Peak memory 215988 kb
Host smart-03d0030c-3fc1-4b9c-a035-49da28d8acd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294631301 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1294631301
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.4241295332
Short name T100
Test name
Test status
Simulation time 65718106 ps
CPU time 1.31 seconds
Started Jul 27 05:56:47 PM PDT 24
Finished Jul 27 05:56:48 PM PDT 24
Peak memory 216844 kb
Host smart-f46ca81e-b5d9-4c80-bca5-9ff45e200cb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241295332 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.4241295332
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2089434187
Short name T97
Test name
Test status
Simulation time 21634383 ps
CPU time 0.9 seconds
Started Jul 27 05:56:43 PM PDT 24
Finished Jul 27 05:56:44 PM PDT 24
Peak memory 218548 kb
Host smart-66e29817-22fe-411c-84bc-000d37f3c8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089434187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2089434187
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1805659199
Short name T862
Test name
Test status
Simulation time 37105862 ps
CPU time 1.46 seconds
Started Jul 27 05:56:47 PM PDT 24
Finished Jul 27 05:56:49 PM PDT 24
Peak memory 218380 kb
Host smart-5b58d618-a47c-4802-8a4c-5b03ecf5fb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805659199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1805659199
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1068473281
Short name T78
Test name
Test status
Simulation time 22182554 ps
CPU time 1.12 seconds
Started Jul 27 05:56:56 PM PDT 24
Finished Jul 27 05:56:57 PM PDT 24
Peak memory 215740 kb
Host smart-0b40e91f-2d47-4b1e-8b74-be3382729ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068473281 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1068473281
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2615532690
Short name T904
Test name
Test status
Simulation time 26291880 ps
CPU time 0.97 seconds
Started Jul 27 05:56:41 PM PDT 24
Finished Jul 27 05:56:42 PM PDT 24
Peak memory 215176 kb
Host smart-e60de897-3a44-483f-b904-5a05a1aa8088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615532690 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2615532690
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.430958428
Short name T986
Test name
Test status
Simulation time 35012466 ps
CPU time 1.25 seconds
Started Jul 27 05:56:38 PM PDT 24
Finished Jul 27 05:56:40 PM PDT 24
Peak memory 218224 kb
Host smart-f391866f-4d94-4f1d-9f7c-5c07c0e46298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430958428 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.430958428
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3128092957
Short name T29
Test name
Test status
Simulation time 85125150491 ps
CPU time 495.68 seconds
Started Jul 27 05:56:40 PM PDT 24
Finished Jul 27 06:04:55 PM PDT 24
Peak memory 219132 kb
Host smart-f39f59df-44e4-491f-aa48-a8cf60672754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128092957 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3128092957
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.4108182094
Short name T813
Test name
Test status
Simulation time 51231024 ps
CPU time 1.32 seconds
Started Jul 27 05:55:49 PM PDT 24
Finished Jul 27 05:55:50 PM PDT 24
Peak memory 220076 kb
Host smart-579396f7-7f35-4440-b500-7f15f1bc1a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108182094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.4108182094
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.4085585901
Short name T391
Test name
Test status
Simulation time 89371557 ps
CPU time 0.79 seconds
Started Jul 27 05:55:45 PM PDT 24
Finished Jul 27 05:55:46 PM PDT 24
Peak memory 206464 kb
Host smart-4ceea116-067c-44c5-820f-45491db0f924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085585901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.4085585901
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3928592417
Short name T527
Test name
Test status
Simulation time 21687305 ps
CPU time 0.86 seconds
Started Jul 27 05:55:39 PM PDT 24
Finished Jul 27 05:55:40 PM PDT 24
Peak memory 216128 kb
Host smart-8dae86c9-d4b7-4425-bebe-97e957cd0ec7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928592417 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3928592417
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3748611246
Short name T178
Test name
Test status
Simulation time 105016099 ps
CPU time 1.2 seconds
Started Jul 27 05:55:40 PM PDT 24
Finished Jul 27 05:55:41 PM PDT 24
Peak memory 216744 kb
Host smart-1dd2a643-3414-4232-a3dc-2cc17ed1fbc4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748611246 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3748611246
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1356247038
Short name T980
Test name
Test status
Simulation time 44850812 ps
CPU time 1 seconds
Started Jul 27 05:55:39 PM PDT 24
Finished Jul 27 05:55:40 PM PDT 24
Peak memory 218516 kb
Host smart-51fd3cb8-18bc-4b17-85ed-ea43046f1024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356247038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1356247038
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1690021080
Short name T389
Test name
Test status
Simulation time 41361925 ps
CPU time 1.09 seconds
Started Jul 27 05:55:41 PM PDT 24
Finished Jul 27 05:55:42 PM PDT 24
Peak memory 217244 kb
Host smart-11ee2acf-783a-41fd-ac0f-8a90fb904005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690021080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1690021080
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.1089771030
Short name T982
Test name
Test status
Simulation time 25121683 ps
CPU time 0.92 seconds
Started Jul 27 05:55:49 PM PDT 24
Finished Jul 27 05:55:50 PM PDT 24
Peak memory 206956 kb
Host smart-d32220d0-df83-40a3-a209-10927416a020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089771030 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1089771030
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.594380789
Short name T784
Test name
Test status
Simulation time 45037683 ps
CPU time 0.94 seconds
Started Jul 27 05:55:39 PM PDT 24
Finished Jul 27 05:55:40 PM PDT 24
Peak memory 215176 kb
Host smart-d0a37cf7-b175-4fb9-af8d-616d4f8c3487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594380789 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.594380789
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.4110931684
Short name T725
Test name
Test status
Simulation time 47910393 ps
CPU time 1.47 seconds
Started Jul 27 05:55:48 PM PDT 24
Finished Jul 27 05:55:50 PM PDT 24
Peak memory 217088 kb
Host smart-4898ab6b-bd0e-4c04-b32f-f78f1c814dda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110931684 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.4110931684
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3908399487
Short name T668
Test name
Test status
Simulation time 249079274482 ps
CPU time 1336.88 seconds
Started Jul 27 05:55:48 PM PDT 24
Finished Jul 27 06:18:06 PM PDT 24
Peak memory 224420 kb
Host smart-63da6b64-f5b5-4c97-9380-2095357bf320
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908399487 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3908399487
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1056616869
Short name T292
Test name
Test status
Simulation time 109880271 ps
CPU time 1.14 seconds
Started Jul 27 05:56:44 PM PDT 24
Finished Jul 27 05:56:45 PM PDT 24
Peak memory 218360 kb
Host smart-17f20b91-972e-41dd-8890-a5443f45d5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056616869 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1056616869
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1200553356
Short name T901
Test name
Test status
Simulation time 23457174 ps
CPU time 1.02 seconds
Started Jul 27 05:56:46 PM PDT 24
Finished Jul 27 05:56:48 PM PDT 24
Peak memory 206688 kb
Host smart-01acf973-825d-4373-825e-c1a8a273169e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200553356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1200553356
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1920972053
Short name T761
Test name
Test status
Simulation time 29194752 ps
CPU time 0.78 seconds
Started Jul 27 05:56:55 PM PDT 24
Finished Jul 27 05:56:56 PM PDT 24
Peak memory 215212 kb
Host smart-e5eb2cfa-a008-4d83-ae7d-0e56d61a0da2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920972053 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1920972053
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.731031615
Short name T811
Test name
Test status
Simulation time 118658354 ps
CPU time 1.23 seconds
Started Jul 27 05:56:48 PM PDT 24
Finished Jul 27 05:56:49 PM PDT 24
Peak memory 216868 kb
Host smart-b25c1fcc-97c2-4921-a8be-624ad0d85a5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731031615 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.731031615
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.4120567757
Short name T967
Test name
Test status
Simulation time 35371292 ps
CPU time 0.95 seconds
Started Jul 27 05:56:40 PM PDT 24
Finished Jul 27 05:56:41 PM PDT 24
Peak memory 218396 kb
Host smart-c36a542d-b1b7-4d97-807f-366727ef9f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120567757 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.4120567757
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2059486796
Short name T798
Test name
Test status
Simulation time 85261361 ps
CPU time 1.09 seconds
Started Jul 27 05:56:43 PM PDT 24
Finished Jul 27 05:56:44 PM PDT 24
Peak memory 217192 kb
Host smart-97616338-a209-4739-8f6f-d28bee21f77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059486796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2059486796
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_smoke.1481117275
Short name T774
Test name
Test status
Simulation time 23613292 ps
CPU time 0.99 seconds
Started Jul 27 05:56:39 PM PDT 24
Finished Jul 27 05:56:40 PM PDT 24
Peak memory 215024 kb
Host smart-47fe4cf9-2a22-4ac2-b0e5-1478dc63833f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481117275 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1481117275
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1452867419
Short name T973
Test name
Test status
Simulation time 388543472 ps
CPU time 7.17 seconds
Started Jul 27 05:56:46 PM PDT 24
Finished Jul 27 05:56:53 PM PDT 24
Peak memory 216884 kb
Host smart-c659dd74-a498-4133-9159-8d2cba144c0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452867419 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1452867419
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.130881955
Short name T240
Test name
Test status
Simulation time 67949038583 ps
CPU time 751.48 seconds
Started Jul 27 05:56:47 PM PDT 24
Finished Jul 27 06:09:19 PM PDT 24
Peak memory 218928 kb
Host smart-7d3d3ce0-8521-42ab-9ce9-22b8bdf59ed4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130881955 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.130881955
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3513452283
Short name T340
Test name
Test status
Simulation time 72345137 ps
CPU time 1.12 seconds
Started Jul 27 05:56:40 PM PDT 24
Finished Jul 27 05:56:41 PM PDT 24
Peak memory 219716 kb
Host smart-1cf43e7d-6d48-4993-9a6b-fd15f0c13602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513452283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3513452283
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2353215054
Short name T857
Test name
Test status
Simulation time 43933139 ps
CPU time 1.06 seconds
Started Jul 27 05:56:47 PM PDT 24
Finished Jul 27 05:56:48 PM PDT 24
Peak memory 214980 kb
Host smart-d8f2da7a-f700-4d74-9dec-1bb2a42fa128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353215054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2353215054
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3948560966
Short name T185
Test name
Test status
Simulation time 14655660 ps
CPU time 0.96 seconds
Started Jul 27 05:56:39 PM PDT 24
Finished Jul 27 05:56:40 PM PDT 24
Peak memory 215460 kb
Host smart-f403ca17-d9be-4d1f-a15b-bc968b362889
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948560966 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3948560966
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1631775002
Short name T742
Test name
Test status
Simulation time 61551410 ps
CPU time 1.14 seconds
Started Jul 27 05:56:47 PM PDT 24
Finished Jul 27 05:56:48 PM PDT 24
Peak memory 216796 kb
Host smart-0583bb98-2b7e-496a-a687-44e3c1f74ed6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631775002 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1631775002
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3099511354
Short name T992
Test name
Test status
Simulation time 19756097 ps
CPU time 1.13 seconds
Started Jul 27 05:56:51 PM PDT 24
Finished Jul 27 05:56:52 PM PDT 24
Peak memory 218516 kb
Host smart-600d213d-b3ba-4114-80ca-0604a166ee00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099511354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3099511354
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3179272688
Short name T362
Test name
Test status
Simulation time 62534341 ps
CPU time 1.21 seconds
Started Jul 27 05:57:02 PM PDT 24
Finished Jul 27 05:57:04 PM PDT 24
Peak memory 217064 kb
Host smart-df7c9b8d-2671-46f8-b240-d495d088c7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179272688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3179272688
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3133436504
Short name T595
Test name
Test status
Simulation time 52804168 ps
CPU time 1 seconds
Started Jul 27 05:56:45 PM PDT 24
Finished Jul 27 05:56:46 PM PDT 24
Peak memory 223720 kb
Host smart-49e18f47-246f-4656-855f-cee04b19200e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133436504 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3133436504
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.310238445
Short name T386
Test name
Test status
Simulation time 21207665 ps
CPU time 1.03 seconds
Started Jul 27 05:56:52 PM PDT 24
Finished Jul 27 05:56:53 PM PDT 24
Peak memory 215116 kb
Host smart-1add9391-0b79-4f88-91a0-24ca3aebd512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310238445 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.310238445
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.4259398263
Short name T503
Test name
Test status
Simulation time 1159603961 ps
CPU time 2.93 seconds
Started Jul 27 05:56:40 PM PDT 24
Finished Jul 27 05:56:43 PM PDT 24
Peak memory 217420 kb
Host smart-0e43fcb5-69cf-40a1-acc6-db8b5f938b23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259398263 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.4259398263
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.4126372410
Short name T695
Test name
Test status
Simulation time 62700162192 ps
CPU time 856.48 seconds
Started Jul 27 05:57:00 PM PDT 24
Finished Jul 27 06:11:16 PM PDT 24
Peak memory 221280 kb
Host smart-6b057864-a81a-47d9-8992-5aea9ac786ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126372410 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.4126372410
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2183487494
Short name T165
Test name
Test status
Simulation time 79647662 ps
CPU time 1.11 seconds
Started Jul 27 05:56:43 PM PDT 24
Finished Jul 27 05:56:44 PM PDT 24
Peak memory 220660 kb
Host smart-457d773a-0ea0-4c82-b9d2-786cba1dd1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183487494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2183487494
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1705889741
Short name T409
Test name
Test status
Simulation time 18013522 ps
CPU time 0.81 seconds
Started Jul 27 05:56:57 PM PDT 24
Finished Jul 27 05:56:58 PM PDT 24
Peak memory 206456 kb
Host smart-8b870fc7-4d49-43d7-becd-e498442a6dfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705889741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1705889741
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1954323420
Short name T685
Test name
Test status
Simulation time 17447694 ps
CPU time 0.87 seconds
Started Jul 27 05:56:49 PM PDT 24
Finished Jul 27 05:56:50 PM PDT 24
Peak memory 216132 kb
Host smart-a182dea9-9e0a-4ff6-86fd-4ee805872e36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954323420 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1954323420
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1322800875
Short name T688
Test name
Test status
Simulation time 61846512 ps
CPU time 1.16 seconds
Started Jul 27 05:56:48 PM PDT 24
Finished Jul 27 05:56:49 PM PDT 24
Peak memory 216708 kb
Host smart-2fbb520d-83f6-48f6-817f-c811ea6d45ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322800875 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1322800875
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1404701857
Short name T828
Test name
Test status
Simulation time 22029376 ps
CPU time 0.96 seconds
Started Jul 27 05:56:53 PM PDT 24
Finished Jul 27 05:56:54 PM PDT 24
Peak memory 218120 kb
Host smart-d16e91d5-7f85-4171-b2d1-983f29f908f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404701857 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1404701857
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1705498448
Short name T672
Test name
Test status
Simulation time 155366984 ps
CPU time 1.03 seconds
Started Jul 27 05:56:51 PM PDT 24
Finished Jul 27 05:56:52 PM PDT 24
Peak memory 217192 kb
Host smart-fefc73de-272e-4a8d-832a-6720a2707c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705498448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1705498448
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1106206704
Short name T98
Test name
Test status
Simulation time 24193420 ps
CPU time 1.05 seconds
Started Jul 27 05:56:47 PM PDT 24
Finished Jul 27 05:56:48 PM PDT 24
Peak memory 215288 kb
Host smart-40e5ede2-e18a-4bf4-9d7d-c5272708e3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106206704 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1106206704
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.955505288
Short name T964
Test name
Test status
Simulation time 15975553 ps
CPU time 1.02 seconds
Started Jul 27 05:56:44 PM PDT 24
Finished Jul 27 05:56:46 PM PDT 24
Peak memory 215196 kb
Host smart-78102085-5d7c-48b8-8d81-0da4bff05748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955505288 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.955505288
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.895478390
Short name T385
Test name
Test status
Simulation time 411778828 ps
CPU time 2.12 seconds
Started Jul 27 05:57:00 PM PDT 24
Finished Jul 27 05:57:03 PM PDT 24
Peak memory 216908 kb
Host smart-fbb422d9-feda-4320-9ba8-03db395cc9de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895478390 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.895478390
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1345588419
Short name T238
Test name
Test status
Simulation time 159427034104 ps
CPU time 1824.01 seconds
Started Jul 27 05:56:50 PM PDT 24
Finished Jul 27 06:27:15 PM PDT 24
Peak memory 224328 kb
Host smart-d397a8b8-4432-440c-af00-4b60592ca0e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345588419 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1345588419
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2069064804
Short name T977
Test name
Test status
Simulation time 261982391 ps
CPU time 1.36 seconds
Started Jul 27 05:56:48 PM PDT 24
Finished Jul 27 05:56:50 PM PDT 24
Peak memory 218724 kb
Host smart-33e7208f-f80b-44ee-bcf2-f984dd3731ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069064804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2069064804
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2214548141
Short name T421
Test name
Test status
Simulation time 35362039 ps
CPU time 1.29 seconds
Started Jul 27 05:56:49 PM PDT 24
Finished Jul 27 05:56:50 PM PDT 24
Peak memory 206928 kb
Host smart-50492536-55e4-4936-9b8e-53f3592a0554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214548141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2214548141
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1711956656
Short name T156
Test name
Test status
Simulation time 29825397 ps
CPU time 1.13 seconds
Started Jul 27 05:56:58 PM PDT 24
Finished Jul 27 05:56:59 PM PDT 24
Peak memory 216752 kb
Host smart-d3dac1fd-0f0f-4f2c-911b-3f5c7d0f9238
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711956656 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1711956656
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3390290138
Short name T634
Test name
Test status
Simulation time 33026110 ps
CPU time 0.99 seconds
Started Jul 27 05:56:48 PM PDT 24
Finished Jul 27 05:56:50 PM PDT 24
Peak memory 229112 kb
Host smart-d1cdcae8-5a1c-4003-8df7-5acd8cb09150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390290138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3390290138
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.767532218
Short name T333
Test name
Test status
Simulation time 42537751 ps
CPU time 1.67 seconds
Started Jul 27 05:56:45 PM PDT 24
Finished Jul 27 05:56:47 PM PDT 24
Peak memory 218564 kb
Host smart-89bc4e03-56ad-4567-8d33-742fb3968ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767532218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.767532218
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3999371698
Short name T130
Test name
Test status
Simulation time 33132865 ps
CPU time 0.82 seconds
Started Jul 27 05:56:46 PM PDT 24
Finished Jul 27 05:56:47 PM PDT 24
Peak memory 215436 kb
Host smart-c42dc964-65e2-4af4-898d-02e2ab9d91ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999371698 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3999371698
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2360243903
Short name T479
Test name
Test status
Simulation time 15908459 ps
CPU time 1 seconds
Started Jul 27 05:56:51 PM PDT 24
Finished Jul 27 05:56:53 PM PDT 24
Peak memory 215168 kb
Host smart-644fb857-395e-4031-b74c-ac7788e1f705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360243903 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2360243903
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3354752024
Short name T565
Test name
Test status
Simulation time 277099490 ps
CPU time 4.67 seconds
Started Jul 27 05:56:58 PM PDT 24
Finished Jul 27 05:57:03 PM PDT 24
Peak memory 217028 kb
Host smart-5c5cfc2e-8702-480a-957c-65c9daf51abb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354752024 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3354752024
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3063789845
Short name T959
Test name
Test status
Simulation time 335462994285 ps
CPU time 2030.06 seconds
Started Jul 27 05:56:45 PM PDT 24
Finished Jul 27 06:30:35 PM PDT 24
Peak memory 226524 kb
Host smart-5d069246-18ea-4b91-9010-6c601d4620aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063789845 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3063789845
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1225739499
Short name T67
Test name
Test status
Simulation time 38691028 ps
CPU time 1.15 seconds
Started Jul 27 05:56:47 PM PDT 24
Finished Jul 27 05:56:48 PM PDT 24
Peak memory 218712 kb
Host smart-9a628962-80c2-4bd9-8673-04e2a63022cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225739499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1225739499
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.233726597
Short name T727
Test name
Test status
Simulation time 195598459 ps
CPU time 0.94 seconds
Started Jul 27 05:56:48 PM PDT 24
Finished Jul 27 05:56:49 PM PDT 24
Peak memory 206688 kb
Host smart-457876d6-bc72-421a-b6fc-df0f8392f1dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233726597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.233726597
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3099574544
Short name T880
Test name
Test status
Simulation time 12796583 ps
CPU time 0.91 seconds
Started Jul 27 05:56:47 PM PDT 24
Finished Jul 27 05:56:48 PM PDT 24
Peak memory 216256 kb
Host smart-6050b49e-5b44-40c9-98b9-e6d28ab289bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099574544 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3099574544
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.4260552595
Short name T905
Test name
Test status
Simulation time 34787113 ps
CPU time 1.25 seconds
Started Jul 27 05:56:55 PM PDT 24
Finished Jul 27 05:56:57 PM PDT 24
Peak memory 216792 kb
Host smart-2b2b58a6-d317-46de-bd26-90cec5365c71
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260552595 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.4260552595
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2063706637
Short name T812
Test name
Test status
Simulation time 31302694 ps
CPU time 0.85 seconds
Started Jul 27 05:56:48 PM PDT 24
Finished Jul 27 05:56:49 PM PDT 24
Peak memory 217856 kb
Host smart-5f5da604-80e3-48db-b532-c0d9ccfdcb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063706637 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2063706637
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3098627235
Short name T351
Test name
Test status
Simulation time 61315527 ps
CPU time 1.26 seconds
Started Jul 27 05:56:57 PM PDT 24
Finished Jul 27 05:56:59 PM PDT 24
Peak memory 218260 kb
Host smart-78697116-fd5e-4881-b839-beecceea1158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098627235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3098627235
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1351310140
Short name T728
Test name
Test status
Simulation time 23040043 ps
CPU time 1.08 seconds
Started Jul 27 05:56:51 PM PDT 24
Finished Jul 27 05:56:52 PM PDT 24
Peak memory 215324 kb
Host smart-2aeafd7c-e348-49d4-a03f-146a23315cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351310140 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1351310140
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3929542265
Short name T918
Test name
Test status
Simulation time 52245162 ps
CPU time 0.95 seconds
Started Jul 27 05:56:57 PM PDT 24
Finished Jul 27 05:56:58 PM PDT 24
Peak memory 215180 kb
Host smart-b2fa7fe6-e343-4f03-b312-edb6db86031f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929542265 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3929542265
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.887682737
Short name T502
Test name
Test status
Simulation time 146811065 ps
CPU time 3.18 seconds
Started Jul 27 05:56:46 PM PDT 24
Finished Jul 27 05:56:50 PM PDT 24
Peak memory 215192 kb
Host smart-49123337-9676-41fb-acdf-07418114e880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887682737 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.887682737
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.646978541
Short name T327
Test name
Test status
Simulation time 235933018121 ps
CPU time 889.08 seconds
Started Jul 27 05:56:47 PM PDT 24
Finished Jul 27 06:11:36 PM PDT 24
Peak memory 221168 kb
Host smart-a374f972-b81d-46f6-8460-40343545a18f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646978541 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.646978541
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1403019758
Short name T677
Test name
Test status
Simulation time 28306297 ps
CPU time 1.27 seconds
Started Jul 27 05:56:46 PM PDT 24
Finished Jul 27 05:56:48 PM PDT 24
Peak memory 219604 kb
Host smart-043bb2b0-5017-42d8-977b-5856e85fe793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403019758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1403019758
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.944916466
Short name T577
Test name
Test status
Simulation time 19302339 ps
CPU time 1 seconds
Started Jul 27 05:56:51 PM PDT 24
Finished Jul 27 05:56:52 PM PDT 24
Peak memory 206664 kb
Host smart-ce596ce2-c7ad-4ab8-8e32-f72d024e3251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944916466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.944916466
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2301985675
Short name T644
Test name
Test status
Simulation time 26487433 ps
CPU time 0.85 seconds
Started Jul 27 05:56:56 PM PDT 24
Finished Jul 27 05:56:57 PM PDT 24
Peak memory 216076 kb
Host smart-848cc959-787f-43ef-8e42-310025a2bdc0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301985675 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2301985675
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.4177373454
Short name T705
Test name
Test status
Simulation time 260789581 ps
CPU time 1 seconds
Started Jul 27 05:56:48 PM PDT 24
Finished Jul 27 05:56:49 PM PDT 24
Peak memory 216856 kb
Host smart-011a4705-5ca7-4779-b8de-bdaeba8996a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177373454 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.4177373454
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.97914439
Short name T483
Test name
Test status
Simulation time 33322946 ps
CPU time 0.88 seconds
Started Jul 27 05:56:48 PM PDT 24
Finished Jul 27 05:56:49 PM PDT 24
Peak memory 219216 kb
Host smart-7573d3b8-1e7c-4796-b427-74076b0a70d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97914439 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.97914439
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3582966217
Short name T492
Test name
Test status
Simulation time 52071402 ps
CPU time 1.21 seconds
Started Jul 27 05:56:57 PM PDT 24
Finished Jul 27 05:56:58 PM PDT 24
Peak memory 217140 kb
Host smart-d3946c04-eb38-4e19-a357-28fc17749e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582966217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3582966217
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.4062990024
Short name T943
Test name
Test status
Simulation time 29194670 ps
CPU time 0.99 seconds
Started Jul 27 05:56:49 PM PDT 24
Finished Jul 27 05:56:50 PM PDT 24
Peak memory 215388 kb
Host smart-70fa7281-d89b-400e-96a3-4ea2779ce74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062990024 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.4062990024
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.4138699742
Short name T877
Test name
Test status
Simulation time 18627093 ps
CPU time 0.94 seconds
Started Jul 27 05:56:59 PM PDT 24
Finished Jul 27 05:57:00 PM PDT 24
Peak memory 215156 kb
Host smart-c9995132-11b6-4f91-b25c-e55364bb76d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138699742 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.4138699742
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2414751722
Short name T978
Test name
Test status
Simulation time 314200093 ps
CPU time 3.79 seconds
Started Jul 27 05:56:52 PM PDT 24
Finished Jul 27 05:56:56 PM PDT 24
Peak memory 219720 kb
Host smart-8a99606c-53ab-4b74-b309-7e618b11ce69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414751722 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2414751722
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.4019772644
Short name T229
Test name
Test status
Simulation time 31090089427 ps
CPU time 365.11 seconds
Started Jul 27 05:56:56 PM PDT 24
Finished Jul 27 06:03:01 PM PDT 24
Peak memory 217748 kb
Host smart-fe30221c-85d6-4420-86c7-35974f130504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019772644 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.4019772644
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.184798790
Short name T741
Test name
Test status
Simulation time 27079926 ps
CPU time 1.2 seconds
Started Jul 27 05:56:52 PM PDT 24
Finished Jul 27 05:56:53 PM PDT 24
Peak memory 219480 kb
Host smart-cce68502-aa19-4bf1-a1b1-2d71e345beb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184798790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.184798790
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2323685878
Short name T649
Test name
Test status
Simulation time 27360460 ps
CPU time 0.85 seconds
Started Jul 27 05:56:53 PM PDT 24
Finished Jul 27 05:56:54 PM PDT 24
Peak memory 214636 kb
Host smart-6d1aacdc-7eeb-4641-aed8-5eee68c99472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323685878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2323685878
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.323431618
Short name T763
Test name
Test status
Simulation time 20117763 ps
CPU time 0.9 seconds
Started Jul 27 05:56:58 PM PDT 24
Finished Jul 27 05:56:59 PM PDT 24
Peak memory 215972 kb
Host smart-3be08b89-4c97-4a23-8e92-2c0301ba52b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323431618 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.323431618
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2280562711
Short name T908
Test name
Test status
Simulation time 35492950 ps
CPU time 1.19 seconds
Started Jul 27 05:56:58 PM PDT 24
Finished Jul 27 05:56:59 PM PDT 24
Peak memory 218440 kb
Host smart-fd6372b6-5646-4769-88eb-c163e7e4239f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280562711 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2280562711
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.4268068853
Short name T436
Test name
Test status
Simulation time 28041636 ps
CPU time 0.83 seconds
Started Jul 27 05:56:50 PM PDT 24
Finished Jul 27 05:56:51 PM PDT 24
Peak memory 218260 kb
Host smart-3b55b4af-9b18-4c34-8c67-683aeab988f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268068853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.4268068853
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2507337092
Short name T651
Test name
Test status
Simulation time 71710268 ps
CPU time 1.13 seconds
Started Jul 27 05:56:51 PM PDT 24
Finished Jul 27 05:56:52 PM PDT 24
Peak memory 218408 kb
Host smart-293cd7cd-95d6-428b-96bd-04563d2755b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507337092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2507337092
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1625112396
Short name T732
Test name
Test status
Simulation time 89383935 ps
CPU time 0.89 seconds
Started Jul 27 05:56:47 PM PDT 24
Finished Jul 27 05:56:48 PM PDT 24
Peak memory 215424 kb
Host smart-98e7a7af-679f-408e-8eef-0a9d7ed5f160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625112396 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1625112396
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3984950301
Short name T56
Test name
Test status
Simulation time 16381170 ps
CPU time 1.01 seconds
Started Jul 27 05:57:06 PM PDT 24
Finished Jul 27 05:57:08 PM PDT 24
Peak memory 215152 kb
Host smart-b564dfd4-c657-41ad-8268-10e0612df211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984950301 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3984950301
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3176385268
Short name T504
Test name
Test status
Simulation time 143966347 ps
CPU time 2.01 seconds
Started Jul 27 05:56:48 PM PDT 24
Finished Jul 27 05:56:50 PM PDT 24
Peak memory 215308 kb
Host smart-89e9b458-fab9-4b7f-891d-f704e454fc99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176385268 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3176385268
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2651177418
Short name T232
Test name
Test status
Simulation time 66107653350 ps
CPU time 415.91 seconds
Started Jul 27 05:56:49 PM PDT 24
Finished Jul 27 06:03:45 PM PDT 24
Peak memory 218952 kb
Host smart-1bc35603-6f85-4720-87e9-4627e892115d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651177418 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2651177418
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1844537936
Short name T962
Test name
Test status
Simulation time 88523078 ps
CPU time 1.21 seconds
Started Jul 27 05:56:48 PM PDT 24
Finished Jul 27 05:56:50 PM PDT 24
Peak memory 220060 kb
Host smart-ec21a99d-5e7d-4a5c-b393-4ca23e3d942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844537936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1844537936
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3617024152
Short name T572
Test name
Test status
Simulation time 16345445 ps
CPU time 0.94 seconds
Started Jul 27 05:56:49 PM PDT 24
Finished Jul 27 05:56:50 PM PDT 24
Peak memory 206604 kb
Host smart-8ba0f979-33f0-4900-9a0c-b10fdbdf687b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617024152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3617024152
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.338390491
Short name T954
Test name
Test status
Simulation time 12077823 ps
CPU time 0.9 seconds
Started Jul 27 05:56:59 PM PDT 24
Finished Jul 27 05:57:00 PM PDT 24
Peak memory 216196 kb
Host smart-afe829a9-2183-49d6-974a-484cc0fc3cdc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338390491 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.338390491
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1985159084
Short name T600
Test name
Test status
Simulation time 65761966 ps
CPU time 1.04 seconds
Started Jul 27 05:56:58 PM PDT 24
Finished Jul 27 05:56:59 PM PDT 24
Peak memory 218504 kb
Host smart-29e80e6c-f4bd-4fd0-ae47-f34d0a9a1635
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985159084 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1985159084
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2735973455
Short name T151
Test name
Test status
Simulation time 157960053 ps
CPU time 1 seconds
Started Jul 27 05:56:59 PM PDT 24
Finished Jul 27 05:57:00 PM PDT 24
Peak memory 219480 kb
Host smart-4aa39ede-794b-47d4-a6c8-4f9b97f125b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735973455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2735973455
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2544104925
Short name T614
Test name
Test status
Simulation time 27679337 ps
CPU time 1.21 seconds
Started Jul 27 05:56:48 PM PDT 24
Finished Jul 27 05:56:49 PM PDT 24
Peak memory 219580 kb
Host smart-58278da0-eedd-425c-9faf-27f2dee40d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544104925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2544104925
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.482545251
Short name T86
Test name
Test status
Simulation time 22158646 ps
CPU time 0.96 seconds
Started Jul 27 05:56:51 PM PDT 24
Finished Jul 27 05:56:52 PM PDT 24
Peak memory 215632 kb
Host smart-03294f0e-b1b3-4cd0-9041-6ef18cf8c861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482545251 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.482545251
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2941985643
Short name T968
Test name
Test status
Simulation time 20434145 ps
CPU time 1.01 seconds
Started Jul 27 05:57:00 PM PDT 24
Finished Jul 27 05:57:02 PM PDT 24
Peak memory 215144 kb
Host smart-169b11de-6bb3-44de-97c2-d56b000fb677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941985643 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2941985643
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.317025415
Short name T618
Test name
Test status
Simulation time 2013166545 ps
CPU time 4.9 seconds
Started Jul 27 05:56:55 PM PDT 24
Finished Jul 27 05:57:00 PM PDT 24
Peak memory 217080 kb
Host smart-bb5569b6-3b40-4f39-b3a1-cb36b0b92575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317025415 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.317025415
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2532988132
Short name T881
Test name
Test status
Simulation time 28759236752 ps
CPU time 646.54 seconds
Started Jul 27 05:57:01 PM PDT 24
Finished Jul 27 06:07:48 PM PDT 24
Peak memory 223812 kb
Host smart-ecb224de-8d21-4992-a181-11b1d2cf1fa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532988132 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2532988132
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.474923050
Short name T657
Test name
Test status
Simulation time 26014459 ps
CPU time 1.23 seconds
Started Jul 27 05:56:52 PM PDT 24
Finished Jul 27 05:56:53 PM PDT 24
Peak memory 220420 kb
Host smart-ae8c34dc-f19b-458a-9ec5-fd652efad8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474923050 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.474923050
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1428825477
Short name T368
Test name
Test status
Simulation time 44286073 ps
CPU time 0.89 seconds
Started Jul 27 05:56:52 PM PDT 24
Finished Jul 27 05:56:53 PM PDT 24
Peak memory 215072 kb
Host smart-a01b92dd-aef9-4f29-bcf6-eb26687e4758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428825477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1428825477
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.930550072
Short name T200
Test name
Test status
Simulation time 19682999 ps
CPU time 0.85 seconds
Started Jul 27 05:56:51 PM PDT 24
Finished Jul 27 05:56:52 PM PDT 24
Peak memory 216112 kb
Host smart-018c411f-a4ef-402d-bb9b-f724508eaca9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930550072 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.930550072
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2883615938
Short name T664
Test name
Test status
Simulation time 31014145 ps
CPU time 1.21 seconds
Started Jul 27 05:56:58 PM PDT 24
Finished Jul 27 05:56:59 PM PDT 24
Peak memory 216984 kb
Host smart-b83c2e95-e6e8-4091-a466-72bbc3e41ea7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883615938 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2883615938
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3980649526
Short name T393
Test name
Test status
Simulation time 64895040 ps
CPU time 0.86 seconds
Started Jul 27 05:57:16 PM PDT 24
Finished Jul 27 05:57:17 PM PDT 24
Peak memory 218220 kb
Host smart-e90078e3-bdb8-4420-959f-1050ac9560f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980649526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3980649526
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2722290375
Short name T435
Test name
Test status
Simulation time 446947596 ps
CPU time 1.44 seconds
Started Jul 27 05:56:50 PM PDT 24
Finished Jul 27 05:56:52 PM PDT 24
Peak memory 217240 kb
Host smart-2969c89f-4784-48b4-a395-2a9a29205c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722290375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2722290375
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2500903266
Short name T79
Test name
Test status
Simulation time 32320283 ps
CPU time 0.83 seconds
Started Jul 27 05:56:50 PM PDT 24
Finished Jul 27 05:56:51 PM PDT 24
Peak memory 215440 kb
Host smart-7da6eee0-c4d4-414b-9a4f-e84695c630fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500903266 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2500903266
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2625762058
Short name T515
Test name
Test status
Simulation time 45171040 ps
CPU time 0.94 seconds
Started Jul 27 05:56:53 PM PDT 24
Finished Jul 27 05:56:54 PM PDT 24
Peak memory 215108 kb
Host smart-97e598ce-eae3-4eea-a75e-63d5109ceb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625762058 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2625762058
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1700791304
Short name T458
Test name
Test status
Simulation time 429314402 ps
CPU time 2.85 seconds
Started Jul 27 05:56:51 PM PDT 24
Finished Jul 27 05:56:54 PM PDT 24
Peak memory 217084 kb
Host smart-d6f0c2f9-a6ef-4cde-ab23-26f582c0804e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700791304 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1700791304
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1138492400
Short name T899
Test name
Test status
Simulation time 86107604800 ps
CPU time 2050.21 seconds
Started Jul 27 05:56:51 PM PDT 24
Finished Jul 27 06:31:02 PM PDT 24
Peak memory 229888 kb
Host smart-bcdef20f-9975-47c5-bbb6-3e41c24d0988
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138492400 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1138492400
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.4018030419
Short name T883
Test name
Test status
Simulation time 26738682 ps
CPU time 1.25 seconds
Started Jul 27 05:57:05 PM PDT 24
Finished Jul 27 05:57:06 PM PDT 24
Peak memory 220668 kb
Host smart-4cad47dc-69a8-42a2-a37d-b99eadf2ad1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018030419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.4018030419
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1514008588
Short name T445
Test name
Test status
Simulation time 46917024 ps
CPU time 1.03 seconds
Started Jul 27 05:56:53 PM PDT 24
Finished Jul 27 05:56:55 PM PDT 24
Peak memory 214812 kb
Host smart-a531483a-5f28-4c1a-8c36-bd5bf1b0876f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514008588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1514008588
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.4199590692
Short name T729
Test name
Test status
Simulation time 37418634 ps
CPU time 0.8 seconds
Started Jul 27 05:56:56 PM PDT 24
Finished Jul 27 05:56:57 PM PDT 24
Peak memory 215252 kb
Host smart-d9e65219-ac5d-4670-9d8f-dc4e37a195fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199590692 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.4199590692
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2659270384
Short name T22
Test name
Test status
Simulation time 122207577 ps
CPU time 1.22 seconds
Started Jul 27 05:57:08 PM PDT 24
Finished Jul 27 05:57:09 PM PDT 24
Peak memory 215396 kb
Host smart-7d699798-bbdc-4a5a-ba2d-a87bc4659952
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659270384 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2659270384
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2616140968
Short name T8
Test name
Test status
Simulation time 25513805 ps
CPU time 1.19 seconds
Started Jul 27 05:56:52 PM PDT 24
Finished Jul 27 05:56:54 PM PDT 24
Peak memory 218308 kb
Host smart-ed71048e-e7b5-4d2f-9a31-564b3b169cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616140968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2616140968
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2466568374
Short name T404
Test name
Test status
Simulation time 62538146 ps
CPU time 1.33 seconds
Started Jul 27 05:56:58 PM PDT 24
Finished Jul 27 05:56:59 PM PDT 24
Peak memory 217416 kb
Host smart-bec81dec-fb5a-4031-b732-6d084c1aa616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466568374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2466568374
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_smoke.3584041654
Short name T477
Test name
Test status
Simulation time 50335316 ps
CPU time 0.91 seconds
Started Jul 27 05:57:04 PM PDT 24
Finished Jul 27 05:57:05 PM PDT 24
Peak memory 215160 kb
Host smart-50ec1c8d-c83c-4648-af71-3b1fc70c18bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584041654 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3584041654
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.163541773
Short name T95
Test name
Test status
Simulation time 111042321 ps
CPU time 1.7 seconds
Started Jul 27 05:56:52 PM PDT 24
Finished Jul 27 05:56:54 PM PDT 24
Peak memory 216956 kb
Host smart-607fc0bc-36e0-4c59-9ade-456c318213ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163541773 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.163541773
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3289781466
Short name T231
Test name
Test status
Simulation time 86401379353 ps
CPU time 1211.98 seconds
Started Jul 27 05:57:02 PM PDT 24
Finished Jul 27 06:17:14 PM PDT 24
Peak memory 225096 kb
Host smart-1dff6c99-d5b7-4a4d-9eda-e36f43b57995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289781466 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3289781466
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.165411578
Short name T60
Test name
Test status
Simulation time 39503501 ps
CPU time 1.26 seconds
Started Jul 27 05:55:46 PM PDT 24
Finished Jul 27 05:55:47 PM PDT 24
Peak memory 219436 kb
Host smart-31c81519-740d-4f24-8b2f-7e7b1ef10d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165411578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.165411578
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2281097077
Short name T599
Test name
Test status
Simulation time 70393212 ps
CPU time 0.99 seconds
Started Jul 27 05:55:49 PM PDT 24
Finished Jul 27 05:55:50 PM PDT 24
Peak memory 206576 kb
Host smart-445a8e5f-d682-41a7-8e02-b5e0c6d75c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281097077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2281097077
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.710536984
Short name T401
Test name
Test status
Simulation time 33762648 ps
CPU time 1.23 seconds
Started Jul 27 05:55:48 PM PDT 24
Finished Jul 27 05:55:49 PM PDT 24
Peak memory 218416 kb
Host smart-cade8647-9f06-4137-86ce-b852e1d2c3b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710536984 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.710536984
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3700273570
Short name T44
Test name
Test status
Simulation time 20334749 ps
CPU time 1.1 seconds
Started Jul 27 05:55:48 PM PDT 24
Finished Jul 27 05:55:49 PM PDT 24
Peak memory 223908 kb
Host smart-09b4bd82-59ab-4cb7-a5b4-0cc1b226f429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700273570 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3700273570
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3789083534
Short name T392
Test name
Test status
Simulation time 28487075 ps
CPU time 1.39 seconds
Started Jul 27 05:55:49 PM PDT 24
Finished Jul 27 05:55:50 PM PDT 24
Peak memory 219992 kb
Host smart-9d49c924-3289-4615-a5a4-b65e33ac0754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789083534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3789083534
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1462164904
Short name T900
Test name
Test status
Simulation time 20700082 ps
CPU time 1.13 seconds
Started Jul 27 05:55:46 PM PDT 24
Finished Jul 27 05:55:47 PM PDT 24
Peak memory 223892 kb
Host smart-c9c5660c-1d0a-44e3-84ea-34ff65872a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462164904 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1462164904
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.335520100
Short name T836
Test name
Test status
Simulation time 52017162 ps
CPU time 0.99 seconds
Started Jul 27 05:55:48 PM PDT 24
Finished Jul 27 05:55:49 PM PDT 24
Peak memory 206976 kb
Host smart-517f4e5c-fd73-4b7c-aed4-7b48353c0eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335520100 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.335520100
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.4054086720
Short name T592
Test name
Test status
Simulation time 18306636 ps
CPU time 0.99 seconds
Started Jul 27 05:55:47 PM PDT 24
Finished Jul 27 05:55:48 PM PDT 24
Peak memory 215156 kb
Host smart-3cfa2b79-67f4-4491-ab21-2289ccb0ccb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054086720 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.4054086720
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1831759180
Short name T96
Test name
Test status
Simulation time 87147894 ps
CPU time 1.53 seconds
Started Jul 27 05:55:44 PM PDT 24
Finished Jul 27 05:55:46 PM PDT 24
Peak memory 216972 kb
Host smart-57c32bc1-e805-45cd-8739-c17a50fd7867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831759180 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1831759180
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3793017054
Short name T564
Test name
Test status
Simulation time 72528564782 ps
CPU time 954.28 seconds
Started Jul 27 05:55:51 PM PDT 24
Finished Jul 27 06:11:45 PM PDT 24
Peak memory 223732 kb
Host smart-3735959e-3514-46b7-8939-a89d119eb9dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793017054 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3793017054
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2834982238
Short name T786
Test name
Test status
Simulation time 85295961 ps
CPU time 1.18 seconds
Started Jul 27 05:57:00 PM PDT 24
Finished Jul 27 05:57:02 PM PDT 24
Peak memory 218616 kb
Host smart-8465e2da-d870-4b00-900b-814d12e24ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834982238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2834982238
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.2332025613
Short name T432
Test name
Test status
Simulation time 74815147 ps
CPU time 0.9 seconds
Started Jul 27 05:57:01 PM PDT 24
Finished Jul 27 05:57:02 PM PDT 24
Peak memory 218192 kb
Host smart-7748903d-7001-4731-b665-cf69fcb0a6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332025613 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2332025613
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.622823404
Short name T453
Test name
Test status
Simulation time 49053104 ps
CPU time 1.33 seconds
Started Jul 27 05:56:57 PM PDT 24
Finished Jul 27 05:56:59 PM PDT 24
Peak memory 218864 kb
Host smart-64b5407a-4ec2-435a-895f-0a361b7e065e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622823404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.622823404
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.887897068
Short name T305
Test name
Test status
Simulation time 41430234 ps
CPU time 1.26 seconds
Started Jul 27 05:56:54 PM PDT 24
Finished Jul 27 05:56:55 PM PDT 24
Peak memory 215564 kb
Host smart-6b8e3dda-41a5-47f4-83ab-06d7bfcd0d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887897068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.887897068
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.4139738565
Short name T94
Test name
Test status
Simulation time 19746404 ps
CPU time 1.12 seconds
Started Jul 27 05:57:05 PM PDT 24
Finished Jul 27 05:57:06 PM PDT 24
Peak memory 219380 kb
Host smart-acc8e988-daf7-4aac-b8f7-0b9c59beb15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139738565 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.4139738565
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3997398386
Short name T575
Test name
Test status
Simulation time 60630857 ps
CPU time 1.11 seconds
Started Jul 27 05:57:03 PM PDT 24
Finished Jul 27 05:57:04 PM PDT 24
Peak memory 217140 kb
Host smart-c0fddb8a-f9e3-4888-83d9-814a061865c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997398386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3997398386
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.3491367703
Short name T687
Test name
Test status
Simulation time 28091485 ps
CPU time 1.29 seconds
Started Jul 27 05:57:04 PM PDT 24
Finished Jul 27 05:57:05 PM PDT 24
Peak memory 218572 kb
Host smart-969d8367-4c77-4990-9b2e-b47b83cbfa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491367703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.3491367703
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.2518880550
Short name T168
Test name
Test status
Simulation time 45708341 ps
CPU time 1 seconds
Started Jul 27 05:57:00 PM PDT 24
Finished Jul 27 05:57:01 PM PDT 24
Peak memory 223696 kb
Host smart-76574abf-35b2-477d-bfc1-7305f38e1fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518880550 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2518880550
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2328880550
Short name T821
Test name
Test status
Simulation time 43000709 ps
CPU time 1.71 seconds
Started Jul 27 05:57:00 PM PDT 24
Finished Jul 27 05:57:02 PM PDT 24
Peak memory 218596 kb
Host smart-24edda5d-62b0-4df2-aff0-caa20bd81245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328880550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2328880550
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.4002816289
Short name T217
Test name
Test status
Simulation time 100388319 ps
CPU time 1.27 seconds
Started Jul 27 05:56:53 PM PDT 24
Finished Jul 27 05:56:55 PM PDT 24
Peak memory 215552 kb
Host smart-34b4bec3-6792-4575-8a0f-51cf57fc6605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002816289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.4002816289
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.515143275
Short name T182
Test name
Test status
Simulation time 89547455 ps
CPU time 1.2 seconds
Started Jul 27 05:56:54 PM PDT 24
Finished Jul 27 05:56:55 PM PDT 24
Peak memory 225752 kb
Host smart-f82eb15a-ebf8-4d1b-88f6-7182468074d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515143275 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.515143275
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1705958439
Short name T490
Test name
Test status
Simulation time 88516425 ps
CPU time 1.23 seconds
Started Jul 27 05:57:05 PM PDT 24
Finished Jul 27 05:57:06 PM PDT 24
Peak memory 218856 kb
Host smart-7007bcdc-7290-4e77-b6bd-fc6824900fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705958439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1705958439
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.1337060376
Short name T871
Test name
Test status
Simulation time 93607837 ps
CPU time 1.2 seconds
Started Jul 27 05:56:54 PM PDT 24
Finished Jul 27 05:56:55 PM PDT 24
Peak memory 221212 kb
Host smart-80c28127-4bfc-4373-b39c-99af32d980ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337060376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.1337060376
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2225000148
Short name T121
Test name
Test status
Simulation time 132738480 ps
CPU time 1.1 seconds
Started Jul 27 05:57:03 PM PDT 24
Finished Jul 27 05:57:04 PM PDT 24
Peak memory 215372 kb
Host smart-938215c8-00b2-4172-b18f-cf69ad6f5efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225000148 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2225000148
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2449756349
Short name T323
Test name
Test status
Simulation time 28115316 ps
CPU time 1.24 seconds
Started Jul 27 05:57:05 PM PDT 24
Finished Jul 27 05:57:06 PM PDT 24
Peak memory 218752 kb
Host smart-bbc03512-c1ae-4449-aec0-8613bd6eb799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449756349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2449756349
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1800057722
Short name T256
Test name
Test status
Simulation time 30032096 ps
CPU time 1.34 seconds
Started Jul 27 05:57:04 PM PDT 24
Finished Jul 27 05:57:05 PM PDT 24
Peak memory 219316 kb
Host smart-301990c5-6543-45d5-8953-d41fdc12a044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800057722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1800057722
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.135260218
Short name T932
Test name
Test status
Simulation time 29165250 ps
CPU time 0.94 seconds
Started Jul 27 05:56:56 PM PDT 24
Finished Jul 27 05:56:57 PM PDT 24
Peak memory 223700 kb
Host smart-2acd4e39-0d00-43d3-bb58-1b49fa56a64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135260218 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.135260218
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.872455261
Short name T329
Test name
Test status
Simulation time 38849891 ps
CPU time 1.41 seconds
Started Jul 27 05:57:05 PM PDT 24
Finished Jul 27 05:57:07 PM PDT 24
Peak memory 218376 kb
Host smart-f323826d-13c3-4e3a-a1ca-5641dfbc9b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872455261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.872455261
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.1390819205
Short name T150
Test name
Test status
Simulation time 54175001 ps
CPU time 1.27 seconds
Started Jul 27 05:57:08 PM PDT 24
Finished Jul 27 05:57:10 PM PDT 24
Peak memory 219744 kb
Host smart-72c695cd-490d-4f42-b204-9ffbad741bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390819205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.1390819205
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.983265401
Short name T58
Test name
Test status
Simulation time 29527318 ps
CPU time 1.24 seconds
Started Jul 27 05:57:00 PM PDT 24
Finished Jul 27 05:57:02 PM PDT 24
Peak memory 219740 kb
Host smart-948b85eb-3d93-407c-9849-7c97429f9fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983265401 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.983265401
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3333557330
Short name T347
Test name
Test status
Simulation time 187302311 ps
CPU time 1.57 seconds
Started Jul 27 05:57:01 PM PDT 24
Finished Jul 27 05:57:02 PM PDT 24
Peak memory 218908 kb
Host smart-f2602127-b5c9-4d11-9455-a707018845d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333557330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3333557330
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3721985744
Short name T181
Test name
Test status
Simulation time 30392566 ps
CPU time 1.31 seconds
Started Jul 27 05:57:05 PM PDT 24
Finished Jul 27 05:57:06 PM PDT 24
Peak memory 219272 kb
Host smart-bfa2ae2c-af3d-4169-be45-a00c58ed493b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721985744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3721985744
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.3256548381
Short name T176
Test name
Test status
Simulation time 56571834 ps
CPU time 1.04 seconds
Started Jul 27 05:57:15 PM PDT 24
Finished Jul 27 05:57:16 PM PDT 24
Peak memory 220344 kb
Host smart-ffa4870f-5ab6-4ef4-b67c-e763e05047a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256548381 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3256548381
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2637674051
Short name T678
Test name
Test status
Simulation time 63790591 ps
CPU time 1.07 seconds
Started Jul 27 05:56:56 PM PDT 24
Finished Jul 27 05:56:57 PM PDT 24
Peak memory 217056 kb
Host smart-6b438ebb-97bc-459b-bc2a-6a0bb6b7512b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637674051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2637674051
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.2234577275
Short name T286
Test name
Test status
Simulation time 30071251 ps
CPU time 1.29 seconds
Started Jul 27 05:57:11 PM PDT 24
Finished Jul 27 05:57:12 PM PDT 24
Peak memory 215504 kb
Host smart-4cf636a2-27be-4f4e-a94b-5f2dd4415b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234577275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.2234577275
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.3311421687
Short name T7
Test name
Test status
Simulation time 30903835 ps
CPU time 1.14 seconds
Started Jul 27 05:57:02 PM PDT 24
Finished Jul 27 05:57:04 PM PDT 24
Peak memory 219508 kb
Host smart-054cca4e-c472-419b-acdb-a9ed6d2f7ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311421687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3311421687
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.4262537418
Short name T34
Test name
Test status
Simulation time 54173710 ps
CPU time 1.21 seconds
Started Jul 27 05:56:55 PM PDT 24
Finished Jul 27 05:56:57 PM PDT 24
Peak memory 217268 kb
Host smart-afcd4381-8a35-485e-a5fa-5566d6b08b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262537418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.4262537418
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.2622021816
Short name T689
Test name
Test status
Simulation time 79354545 ps
CPU time 1.2 seconds
Started Jul 27 05:57:10 PM PDT 24
Finished Jul 27 05:57:11 PM PDT 24
Peak memory 219480 kb
Host smart-79485023-64ea-4518-a24d-f6f8f32ba301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622021816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2622021816
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.1085098229
Short name T191
Test name
Test status
Simulation time 20178497 ps
CPU time 1.09 seconds
Started Jul 27 05:57:02 PM PDT 24
Finished Jul 27 05:57:03 PM PDT 24
Peak memory 223924 kb
Host smart-63e96b04-de3e-441e-bc24-f4c2f1f1d552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085098229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1085098229
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3341969774
Short name T907
Test name
Test status
Simulation time 119798293 ps
CPU time 1.82 seconds
Started Jul 27 05:57:01 PM PDT 24
Finished Jul 27 05:57:03 PM PDT 24
Peak memory 217572 kb
Host smart-8b5677f2-c539-477f-8c0e-3078c519d499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341969774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3341969774
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2161130730
Short name T137
Test name
Test status
Simulation time 23119651 ps
CPU time 1.21 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:56 PM PDT 24
Peak memory 219492 kb
Host smart-8719ddb2-687e-4226-923b-e730e9a567fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161130730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2161130730
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.350894889
Short name T640
Test name
Test status
Simulation time 22315045 ps
CPU time 1.05 seconds
Started Jul 27 05:55:56 PM PDT 24
Finished Jul 27 05:55:57 PM PDT 24
Peak memory 206632 kb
Host smart-5f51ca41-94f2-473a-85c2-d78206c28aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350894889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.350894889
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.632760318
Short name T66
Test name
Test status
Simulation time 12312231 ps
CPU time 0.91 seconds
Started Jul 27 05:55:56 PM PDT 24
Finished Jul 27 05:55:57 PM PDT 24
Peak memory 216288 kb
Host smart-295a7d42-f0f0-4dfe-8c6b-3d24396821b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632760318 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.632760318
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.755003572
Short name T816
Test name
Test status
Simulation time 113468951 ps
CPU time 1.06 seconds
Started Jul 27 05:56:01 PM PDT 24
Finished Jul 27 05:56:02 PM PDT 24
Peak memory 218284 kb
Host smart-fe62a17a-4106-4994-a65b-a77ed9686e83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755003572 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.755003572
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.666358596
Short name T189
Test name
Test status
Simulation time 34875206 ps
CPU time 0.95 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:56 PM PDT 24
Peak memory 218220 kb
Host smart-1f0e3d01-6914-4120-a6c1-0a8676d5d873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666358596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.666358596
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.950329946
Short name T320
Test name
Test status
Simulation time 155959560 ps
CPU time 2.09 seconds
Started Jul 27 05:55:45 PM PDT 24
Finished Jul 27 05:55:48 PM PDT 24
Peak memory 218524 kb
Host smart-36c383e1-c020-4f0f-8c24-05b029481016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950329946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.950329946
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2372236026
Short name T83
Test name
Test status
Simulation time 26670352 ps
CPU time 0.94 seconds
Started Jul 27 05:55:58 PM PDT 24
Finished Jul 27 05:55:59 PM PDT 24
Peak memory 215700 kb
Host smart-da470724-a324-4212-bddb-20593d533864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372236026 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2372236026
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1230401940
Short name T719
Test name
Test status
Simulation time 25059336 ps
CPU time 1.05 seconds
Started Jul 27 05:55:49 PM PDT 24
Finished Jul 27 05:55:50 PM PDT 24
Peak memory 206944 kb
Host smart-7541df29-9cd1-4312-9505-9e61993c04cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230401940 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1230401940
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1851184530
Short name T514
Test name
Test status
Simulation time 51635337 ps
CPU time 0.93 seconds
Started Jul 27 05:55:50 PM PDT 24
Finished Jul 27 05:55:51 PM PDT 24
Peak memory 215108 kb
Host smart-3986dc9a-4c9b-49ec-a7c1-9539263f4674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851184530 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1851184530
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3422027567
Short name T244
Test name
Test status
Simulation time 349272512 ps
CPU time 7.04 seconds
Started Jul 27 05:55:49 PM PDT 24
Finished Jul 27 05:55:56 PM PDT 24
Peak memory 215092 kb
Host smart-a9ed802f-a871-4e03-972f-137fb5f37361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422027567 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3422027567
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.713639386
Short name T590
Test name
Test status
Simulation time 280228564726 ps
CPU time 1122.02 seconds
Started Jul 27 05:55:57 PM PDT 24
Finished Jul 27 06:14:39 PM PDT 24
Peak memory 223544 kb
Host smart-19892d62-1c58-49f5-bca7-62059e7b1b89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713639386 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.713639386
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2471501613
Short name T304
Test name
Test status
Simulation time 80558884 ps
CPU time 1.27 seconds
Started Jul 27 05:57:02 PM PDT 24
Finished Jul 27 05:57:03 PM PDT 24
Peak memory 218436 kb
Host smart-c25de7e8-0e7d-445a-997a-171930800161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471501613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2471501613
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3606944714
Short name T707
Test name
Test status
Simulation time 38441530 ps
CPU time 1.02 seconds
Started Jul 27 05:57:00 PM PDT 24
Finished Jul 27 05:57:01 PM PDT 24
Peak memory 229236 kb
Host smart-ecf724ee-29a3-4e51-9050-a88328401693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606944714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3606944714
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1954723651
Short name T427
Test name
Test status
Simulation time 62121492 ps
CPU time 1.24 seconds
Started Jul 27 05:57:12 PM PDT 24
Finished Jul 27 05:57:13 PM PDT 24
Peak memory 217172 kb
Host smart-a09fd87f-eb0c-4d51-99dd-dd2fccf71a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954723651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1954723651
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.3377135136
Short name T669
Test name
Test status
Simulation time 23371955 ps
CPU time 1.22 seconds
Started Jul 27 05:57:03 PM PDT 24
Finished Jul 27 05:57:05 PM PDT 24
Peak memory 219708 kb
Host smart-104c24be-60cd-4df3-acfa-f24c83e4716c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377135136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.3377135136
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1337314830
Short name T531
Test name
Test status
Simulation time 32305257 ps
CPU time 0.9 seconds
Started Jul 27 05:56:59 PM PDT 24
Finished Jul 27 05:57:00 PM PDT 24
Peak memory 218224 kb
Host smart-2c717984-9c3b-4a28-9a91-cc55bc4ca969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337314830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1337314830
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2234788095
Short name T480
Test name
Test status
Simulation time 93892554 ps
CPU time 1.15 seconds
Started Jul 27 05:57:10 PM PDT 24
Finished Jul 27 05:57:11 PM PDT 24
Peak memory 216980 kb
Host smart-3cbc319e-6361-41ec-b223-3a149a5a8d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234788095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2234788095
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.1089003876
Short name T935
Test name
Test status
Simulation time 80684393 ps
CPU time 1.1 seconds
Started Jul 27 05:57:12 PM PDT 24
Finished Jul 27 05:57:13 PM PDT 24
Peak memory 218368 kb
Host smart-95f98fe8-466b-4ed9-98ff-adbe5804967f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089003876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1089003876
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1455242415
Short name T127
Test name
Test status
Simulation time 49253598 ps
CPU time 1.01 seconds
Started Jul 27 05:57:06 PM PDT 24
Finished Jul 27 05:57:07 PM PDT 24
Peak memory 219740 kb
Host smart-e446408a-cc4a-45b4-b79b-a42888ec7e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455242415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1455242415
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.4031879148
Short name T541
Test name
Test status
Simulation time 63555735 ps
CPU time 1.35 seconds
Started Jul 27 05:57:06 PM PDT 24
Finished Jul 27 05:57:07 PM PDT 24
Peak memory 218752 kb
Host smart-e83815b7-b32b-4818-ac8a-9fc791097a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031879148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.4031879148
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.3176373938
Short name T704
Test name
Test status
Simulation time 129341823 ps
CPU time 1.27 seconds
Started Jul 27 05:57:04 PM PDT 24
Finished Jul 27 05:57:10 PM PDT 24
Peak memory 215520 kb
Host smart-43d7e2ff-d057-4b2e-b3ea-8791b8948e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176373938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3176373938
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1771359942
Short name T215
Test name
Test status
Simulation time 37865426 ps
CPU time 0.92 seconds
Started Jul 27 05:57:11 PM PDT 24
Finished Jul 27 05:57:12 PM PDT 24
Peak memory 219208 kb
Host smart-e5604abb-964b-4a73-8796-97960d6e5e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771359942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1771359942
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3465226314
Short name T493
Test name
Test status
Simulation time 107473816 ps
CPU time 1.33 seconds
Started Jul 27 05:57:03 PM PDT 24
Finished Jul 27 05:57:04 PM PDT 24
Peak memory 218384 kb
Host smart-c7ca2943-dae5-490b-a71a-8b28fdddd9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465226314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3465226314
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2955039874
Short name T345
Test name
Test status
Simulation time 429614926 ps
CPU time 1.35 seconds
Started Jul 27 05:57:07 PM PDT 24
Finished Jul 27 05:57:09 PM PDT 24
Peak memory 215488 kb
Host smart-b43e7108-e872-41fa-b4fb-7d2412302a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955039874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2955039874
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.995429397
Short name T152
Test name
Test status
Simulation time 37894736 ps
CPU time 1.24 seconds
Started Jul 27 05:57:01 PM PDT 24
Finished Jul 27 05:57:03 PM PDT 24
Peak memory 229680 kb
Host smart-7c85df76-0e41-49cd-ba95-a4da05f7759f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995429397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.995429397
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.371945216
Short name T501
Test name
Test status
Simulation time 42883620 ps
CPU time 1.6 seconds
Started Jul 27 05:57:03 PM PDT 24
Finished Jul 27 05:57:05 PM PDT 24
Peak memory 218264 kb
Host smart-1ada943d-26ef-4adb-8e4d-9f92ef22092e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371945216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.371945216
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.484068197
Short name T196
Test name
Test status
Simulation time 27591524 ps
CPU time 1.22 seconds
Started Jul 27 05:57:03 PM PDT 24
Finished Jul 27 05:57:04 PM PDT 24
Peak memory 218496 kb
Host smart-4c45e0f7-f561-4954-8bb5-227dbf78f889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484068197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.484068197
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.3641757308
Short name T198
Test name
Test status
Simulation time 18840322 ps
CPU time 1.06 seconds
Started Jul 27 05:57:02 PM PDT 24
Finished Jul 27 05:57:03 PM PDT 24
Peak memory 218288 kb
Host smart-52cff1a2-1f06-4d0a-90ae-e9d5484af688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641757308 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3641757308
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.559812016
Short name T667
Test name
Test status
Simulation time 119827669 ps
CPU time 1.09 seconds
Started Jul 27 05:57:15 PM PDT 24
Finished Jul 27 05:57:17 PM PDT 24
Peak memory 217464 kb
Host smart-f264d362-fd63-4da6-997c-3e9757a10d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559812016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.559812016
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.673074860
Short name T159
Test name
Test status
Simulation time 96702206 ps
CPU time 1.31 seconds
Started Jul 27 05:57:07 PM PDT 24
Finished Jul 27 05:57:09 PM PDT 24
Peak memory 218356 kb
Host smart-4f706afc-6bac-4265-9ee0-4d0d35d8773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673074860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.673074860
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.919585436
Short name T102
Test name
Test status
Simulation time 40858654 ps
CPU time 0.95 seconds
Started Jul 27 05:57:06 PM PDT 24
Finished Jul 27 05:57:07 PM PDT 24
Peak memory 219556 kb
Host smart-debc7c0e-7471-4800-9ca4-12c5bc5fb5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919585436 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.919585436
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1126018723
Short name T676
Test name
Test status
Simulation time 119093542 ps
CPU time 1.06 seconds
Started Jul 27 05:57:08 PM PDT 24
Finished Jul 27 05:57:09 PM PDT 24
Peak memory 217228 kb
Host smart-b209ab47-76ca-4832-be9c-2cd6e9305afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126018723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1126018723
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.717012718
Short name T827
Test name
Test status
Simulation time 82178941 ps
CPU time 1.31 seconds
Started Jul 27 05:57:04 PM PDT 24
Finished Jul 27 05:57:05 PM PDT 24
Peak memory 218160 kb
Host smart-bf0b1e01-7fd8-4b91-a331-9c31827cc86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717012718 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.717012718
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.2638357142
Short name T974
Test name
Test status
Simulation time 18360351 ps
CPU time 1.07 seconds
Started Jul 27 05:57:03 PM PDT 24
Finished Jul 27 05:57:04 PM PDT 24
Peak memory 218180 kb
Host smart-b35d5b8e-ea56-45d8-8262-4a6e76686ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638357142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2638357142
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3934464465
Short name T779
Test name
Test status
Simulation time 54266291 ps
CPU time 1.73 seconds
Started Jul 27 05:57:13 PM PDT 24
Finished Jul 27 05:57:15 PM PDT 24
Peak memory 218548 kb
Host smart-cf369371-98ea-4f61-8395-96a88c003f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934464465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3934464465
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.2411617727
Short name T915
Test name
Test status
Simulation time 20703834 ps
CPU time 1.07 seconds
Started Jul 27 05:57:03 PM PDT 24
Finished Jul 27 05:57:04 PM PDT 24
Peak memory 215376 kb
Host smart-6aaadfb0-cadc-45e0-97f9-a4e134360de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411617727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2411617727
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3841826900
Short name T487
Test name
Test status
Simulation time 37265770 ps
CPU time 1.51 seconds
Started Jul 27 05:57:00 PM PDT 24
Finished Jul 27 05:57:02 PM PDT 24
Peak memory 219316 kb
Host smart-fa05c87f-2b7a-4b83-a56c-2226f93c03b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841826900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3841826900
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.954326168
Short name T500
Test name
Test status
Simulation time 45625770 ps
CPU time 1.18 seconds
Started Jul 27 05:57:02 PM PDT 24
Finished Jul 27 05:57:04 PM PDT 24
Peak memory 215548 kb
Host smart-db78ab3b-6fdd-490b-8793-8f15f36d668d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954326168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.954326168
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2698442332
Short name T145
Test name
Test status
Simulation time 26690959 ps
CPU time 1.03 seconds
Started Jul 27 05:57:05 PM PDT 24
Finished Jul 27 05:57:06 PM PDT 24
Peak memory 219596 kb
Host smart-7241011a-cb7c-46c5-a889-bb1dc55892d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698442332 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2698442332
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2900583987
Short name T536
Test name
Test status
Simulation time 54251197 ps
CPU time 1.28 seconds
Started Jul 27 05:57:01 PM PDT 24
Finished Jul 27 05:57:02 PM PDT 24
Peak memory 217232 kb
Host smart-baae64e5-fbad-4c31-b30c-4fa14bb0286d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900583987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2900583987
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3187880809
Short name T293
Test name
Test status
Simulation time 162487222 ps
CPU time 1.12 seconds
Started Jul 27 05:56:00 PM PDT 24
Finished Jul 27 05:56:01 PM PDT 24
Peak memory 220688 kb
Host smart-e454c295-fed3-48e2-86c6-b7c4c3226150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187880809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3187880809
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.440577343
Short name T850
Test name
Test status
Simulation time 157728267 ps
CPU time 0.96 seconds
Started Jul 27 05:55:57 PM PDT 24
Finished Jul 27 05:55:58 PM PDT 24
Peak memory 214856 kb
Host smart-c188fae1-a493-4f3f-bd11-3035891f88f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440577343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.440577343
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.558874902
Short name T221
Test name
Test status
Simulation time 37324637 ps
CPU time 0.88 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:56 PM PDT 24
Peak memory 215252 kb
Host smart-9917cde4-36a5-4c7e-a22f-9c647a13ab69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558874902 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.558874902
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3707655597
Short name T101
Test name
Test status
Simulation time 34744615 ps
CPU time 1.22 seconds
Started Jul 27 05:56:00 PM PDT 24
Finished Jul 27 05:56:02 PM PDT 24
Peak memory 216648 kb
Host smart-039f5834-2d22-494a-8ff4-24991a171f22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707655597 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3707655597
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.4248344157
Short name T206
Test name
Test status
Simulation time 22051430 ps
CPU time 1.05 seconds
Started Jul 27 05:55:57 PM PDT 24
Finished Jul 27 05:55:58 PM PDT 24
Peak memory 223824 kb
Host smart-819bcc1b-afe7-4602-9e87-dfbe1569b451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248344157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.4248344157
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.13363360
Short name T902
Test name
Test status
Simulation time 37322438 ps
CPU time 1.12 seconds
Started Jul 27 05:55:58 PM PDT 24
Finished Jul 27 05:55:59 PM PDT 24
Peak memory 219756 kb
Host smart-7e82d151-a654-4bfe-905e-c24a01730421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13363360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.13363360
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2078827691
Short name T459
Test name
Test status
Simulation time 25927182 ps
CPU time 0.92 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:56 PM PDT 24
Peak memory 215700 kb
Host smart-2e45a98a-5e13-4575-aba4-ec51e7ff50cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078827691 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2078827691
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3819716433
Short name T75
Test name
Test status
Simulation time 28693207 ps
CPU time 0.96 seconds
Started Jul 27 05:55:56 PM PDT 24
Finished Jul 27 05:55:58 PM PDT 24
Peak memory 206944 kb
Host smart-ede67f85-39f8-4538-bd1a-0727ff989cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819716433 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3819716433
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2292979979
Short name T356
Test name
Test status
Simulation time 46003052 ps
CPU time 0.95 seconds
Started Jul 27 05:55:58 PM PDT 24
Finished Jul 27 05:55:59 PM PDT 24
Peak memory 215168 kb
Host smart-661ab3e1-629c-43b8-9bff-9e9c8977a7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292979979 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2292979979
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2177622983
Short name T835
Test name
Test status
Simulation time 451118595 ps
CPU time 1.68 seconds
Started Jul 27 05:55:56 PM PDT 24
Finished Jul 27 05:55:58 PM PDT 24
Peak memory 215296 kb
Host smart-ad8d83a9-6f6c-4041-9e06-3117f93ae728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177622983 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2177622983
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3057138497
Short name T819
Test name
Test status
Simulation time 179176121212 ps
CPU time 686.05 seconds
Started Jul 27 05:56:02 PM PDT 24
Finished Jul 27 06:07:28 PM PDT 24
Peak memory 221328 kb
Host smart-bafa5e83-e21c-486c-9337-4889f9646249
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057138497 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3057138497
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.2770201813
Short name T971
Test name
Test status
Simulation time 261576332 ps
CPU time 1.21 seconds
Started Jul 27 05:57:05 PM PDT 24
Finished Jul 27 05:57:06 PM PDT 24
Peak memory 218212 kb
Host smart-623378a8-5406-42a2-968f-721b558a4ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770201813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2770201813
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.952984647
Short name T522
Test name
Test status
Simulation time 49468194 ps
CPU time 0.84 seconds
Started Jul 27 05:57:07 PM PDT 24
Finished Jul 27 05:57:08 PM PDT 24
Peak memory 218280 kb
Host smart-7c370058-6827-467f-9373-6153ac17e0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952984647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.952984647
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3537434996
Short name T797
Test name
Test status
Simulation time 58921835 ps
CPU time 1.09 seconds
Started Jul 27 05:57:04 PM PDT 24
Finished Jul 27 05:57:05 PM PDT 24
Peak memory 217532 kb
Host smart-239a1101-ef7d-44a0-82f3-83444464e534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537434996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3537434996
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2753696767
Short name T136
Test name
Test status
Simulation time 48285898 ps
CPU time 1.16 seconds
Started Jul 27 05:57:06 PM PDT 24
Finished Jul 27 05:57:07 PM PDT 24
Peak memory 221088 kb
Host smart-3863ea1d-493e-4b8c-ae31-34b8a4854266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753696767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2753696767
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_genbits.2074334028
Short name T525
Test name
Test status
Simulation time 47324939 ps
CPU time 1.94 seconds
Started Jul 27 05:57:03 PM PDT 24
Finished Jul 27 05:57:05 PM PDT 24
Peak memory 218416 kb
Host smart-0d768b56-8b53-425e-996f-ae7dc8cf7d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074334028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2074334028
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.3731203019
Short name T663
Test name
Test status
Simulation time 171507688 ps
CPU time 1.1 seconds
Started Jul 27 05:57:15 PM PDT 24
Finished Jul 27 05:57:17 PM PDT 24
Peak memory 218480 kb
Host smart-3d767e67-02a8-4cba-9984-8ae72c27e1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731203019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.3731203019
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3149186395
Short name T47
Test name
Test status
Simulation time 22129558 ps
CPU time 1.04 seconds
Started Jul 27 05:57:21 PM PDT 24
Finished Jul 27 05:57:22 PM PDT 24
Peak memory 223660 kb
Host smart-cc4efd9a-0b36-4dca-a8b4-33b7be59d61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149186395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3149186395
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.550066812
Short name T721
Test name
Test status
Simulation time 42266075 ps
CPU time 1.06 seconds
Started Jul 27 05:57:07 PM PDT 24
Finished Jul 27 05:57:08 PM PDT 24
Peak memory 217392 kb
Host smart-4ccffbc7-3d8c-485d-9273-cf8c6db50c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550066812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.550066812
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2490935324
Short name T139
Test name
Test status
Simulation time 28103486 ps
CPU time 1.22 seconds
Started Jul 27 05:57:10 PM PDT 24
Finished Jul 27 05:57:11 PM PDT 24
Peak memory 219456 kb
Host smart-5d753425-2516-44be-a154-b808fda9fc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490935324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2490935324
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.953735268
Short name T128
Test name
Test status
Simulation time 35280117 ps
CPU time 1.13 seconds
Started Jul 27 05:57:17 PM PDT 24
Finished Jul 27 05:57:18 PM PDT 24
Peak memory 220612 kb
Host smart-959176f3-d9ee-45a2-844d-c03c8453b557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953735268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.953735268
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1773562881
Short name T513
Test name
Test status
Simulation time 52486186 ps
CPU time 1.32 seconds
Started Jul 27 05:57:13 PM PDT 24
Finished Jul 27 05:57:15 PM PDT 24
Peak memory 217228 kb
Host smart-4d184c18-f2f9-4ed9-ae3d-6abdaea5caad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773562881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1773562881
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.311633863
Short name T162
Test name
Test status
Simulation time 208301738 ps
CPU time 1.28 seconds
Started Jul 27 05:57:20 PM PDT 24
Finished Jul 27 05:57:21 PM PDT 24
Peak memory 218340 kb
Host smart-33d3ebd7-b5aa-4543-9aae-c698d5d4d37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311633863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.311633863
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.488777231
Short name T147
Test name
Test status
Simulation time 51066632 ps
CPU time 1.14 seconds
Started Jul 27 05:57:13 PM PDT 24
Finished Jul 27 05:57:14 PM PDT 24
Peak memory 229404 kb
Host smart-98221c46-9875-47f5-a2db-99db82b893d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488777231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.488777231
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.4005961862
Short name T53
Test name
Test status
Simulation time 39206386 ps
CPU time 1.39 seconds
Started Jul 27 05:57:08 PM PDT 24
Finished Jul 27 05:57:10 PM PDT 24
Peak memory 218192 kb
Host smart-12c561dc-63d8-4a55-9be0-0574c1f0f617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005961862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.4005961862
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.29492983
Short name T143
Test name
Test status
Simulation time 111695015 ps
CPU time 1.23 seconds
Started Jul 27 05:57:10 PM PDT 24
Finished Jul 27 05:57:11 PM PDT 24
Peak memory 218832 kb
Host smart-2389d4e7-d0d7-4fbc-8e3d-f7afe6be34ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29492983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.29492983
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.1374927101
Short name T46
Test name
Test status
Simulation time 25061906 ps
CPU time 1.09 seconds
Started Jul 27 05:57:14 PM PDT 24
Finished Jul 27 05:57:15 PM PDT 24
Peak memory 223868 kb
Host smart-b97915cb-999c-465a-9237-2594a8728290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374927101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1374927101
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/76.edn_alert.2625426420
Short name T808
Test name
Test status
Simulation time 58939929 ps
CPU time 1.17 seconds
Started Jul 27 05:57:23 PM PDT 24
Finished Jul 27 05:57:24 PM PDT 24
Peak memory 219596 kb
Host smart-517cce22-9035-420b-bf23-f7d80baf0fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625426420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.2625426420
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.728038710
Short name T701
Test name
Test status
Simulation time 35544348 ps
CPU time 1.29 seconds
Started Jul 27 05:57:06 PM PDT 24
Finished Jul 27 05:57:07 PM PDT 24
Peak memory 223844 kb
Host smart-883b2072-34da-4077-84e5-e8f3be8d24d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728038710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.728038710
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1514300808
Short name T799
Test name
Test status
Simulation time 38967992 ps
CPU time 1.47 seconds
Started Jul 27 05:57:15 PM PDT 24
Finished Jul 27 05:57:17 PM PDT 24
Peak memory 218128 kb
Host smart-3abab7bf-67be-484a-9665-6ffd0be8d927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514300808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1514300808
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.2779989571
Short name T610
Test name
Test status
Simulation time 69745409 ps
CPU time 1.19 seconds
Started Jul 27 05:57:12 PM PDT 24
Finished Jul 27 05:57:13 PM PDT 24
Peak memory 220432 kb
Host smart-9d904b1d-dbb0-4f46-a3ab-a5e50359bb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779989571 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.2779989571
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.598088838
Short name T193
Test name
Test status
Simulation time 20537168 ps
CPU time 1.21 seconds
Started Jul 27 05:57:17 PM PDT 24
Finished Jul 27 05:57:18 PM PDT 24
Peak memory 223832 kb
Host smart-c46ebb8b-0a8c-4522-9bed-2c7f21be555a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598088838 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.598088838
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3503716382
Short name T963
Test name
Test status
Simulation time 53804085 ps
CPU time 1.59 seconds
Started Jul 27 05:57:15 PM PDT 24
Finished Jul 27 05:57:17 PM PDT 24
Peak memory 218404 kb
Host smart-535c992b-eea9-4ced-826b-bf7fa8bd1b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503716382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3503716382
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.1369375667
Short name T450
Test name
Test status
Simulation time 308152188 ps
CPU time 1.35 seconds
Started Jul 27 05:57:13 PM PDT 24
Finished Jul 27 05:57:15 PM PDT 24
Peak memory 219368 kb
Host smart-25804d66-9e3a-4a7a-a1bb-eceaa3c7dce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369375667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.1369375667
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.4241845844
Short name T174
Test name
Test status
Simulation time 33209500 ps
CPU time 1.04 seconds
Started Jul 27 05:57:19 PM PDT 24
Finished Jul 27 05:57:20 PM PDT 24
Peak memory 229644 kb
Host smart-6d2e59b3-6cab-4f2e-8acf-c542cf22458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241845844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.4241845844
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.103779876
Short name T505
Test name
Test status
Simulation time 116283135 ps
CPU time 1.11 seconds
Started Jul 27 05:57:13 PM PDT 24
Finished Jul 27 05:57:14 PM PDT 24
Peak memory 217212 kb
Host smart-7d7894c6-eff8-42ec-b771-b6452d661612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103779876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.103779876
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1258719263
Short name T472
Test name
Test status
Simulation time 45697616 ps
CPU time 1.14 seconds
Started Jul 27 05:57:23 PM PDT 24
Finished Jul 27 05:57:24 PM PDT 24
Peak memory 220528 kb
Host smart-1546cb64-9317-4b6d-a79f-d9cda2f4f7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258719263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1258719263
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.2440388396
Short name T363
Test name
Test status
Simulation time 28539833 ps
CPU time 0.82 seconds
Started Jul 27 05:57:22 PM PDT 24
Finished Jul 27 05:57:23 PM PDT 24
Peak memory 218092 kb
Host smart-bcc0b63d-6fdb-48dc-86b0-ce8690526d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440388396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2440388396
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3925720607
Short name T475
Test name
Test status
Simulation time 112998023 ps
CPU time 3.05 seconds
Started Jul 27 05:57:10 PM PDT 24
Finished Jul 27 05:57:13 PM PDT 24
Peak memory 220200 kb
Host smart-e30d3543-9909-4653-8938-424d930e1cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925720607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3925720607
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2395195304
Short name T635
Test name
Test status
Simulation time 46823302 ps
CPU time 1.14 seconds
Started Jul 27 05:55:54 PM PDT 24
Finished Jul 27 05:55:56 PM PDT 24
Peak memory 219372 kb
Host smart-fef3885f-a09d-4ace-b74a-ea2880e0bf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395195304 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2395195304
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3461223593
Short name T944
Test name
Test status
Simulation time 13713497 ps
CPU time 0.84 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:56 PM PDT 24
Peak memory 206604 kb
Host smart-a1a451ed-1cd3-40f0-9cc1-962723b17fcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461223593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3461223593
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.797799359
Short name T108
Test name
Test status
Simulation time 15343065 ps
CPU time 0.85 seconds
Started Jul 27 05:55:57 PM PDT 24
Finished Jul 27 05:55:58 PM PDT 24
Peak memory 216076 kb
Host smart-179dc7cf-a941-426c-a8b8-178679e67b76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797799359 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.797799359
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1791098634
Short name T539
Test name
Test status
Simulation time 62415010 ps
CPU time 1.26 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:57 PM PDT 24
Peak memory 219636 kb
Host smart-b5e751d7-e971-4710-b9f6-267b71f4484e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791098634 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1791098634
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.813024020
Short name T212
Test name
Test status
Simulation time 21413877 ps
CPU time 0.92 seconds
Started Jul 27 05:55:58 PM PDT 24
Finished Jul 27 05:55:59 PM PDT 24
Peak memory 218320 kb
Host smart-da71e2c0-eaa4-4999-859c-6fa08bccead7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813024020 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.813024020
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2043649234
Short name T532
Test name
Test status
Simulation time 94888133 ps
CPU time 1.62 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:57 PM PDT 24
Peak memory 220220 kb
Host smart-1a481e7c-550a-4c39-8bf3-7bc74a796c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043649234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2043649234
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.747401065
Short name T88
Test name
Test status
Simulation time 20630276 ps
CPU time 1.07 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 05:55:56 PM PDT 24
Peak memory 215800 kb
Host smart-2c6cb82b-2703-41c1-bcda-41393b858096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747401065 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.747401065
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2713549540
Short name T817
Test name
Test status
Simulation time 15623521 ps
CPU time 1.01 seconds
Started Jul 27 05:55:56 PM PDT 24
Finished Jul 27 05:55:57 PM PDT 24
Peak memory 206972 kb
Host smart-e4cbead8-0580-4235-912c-51f4101cd845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713549540 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2713549540
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3364238446
Short name T488
Test name
Test status
Simulation time 50197733 ps
CPU time 0.88 seconds
Started Jul 27 05:56:00 PM PDT 24
Finished Jul 27 05:56:01 PM PDT 24
Peak memory 215144 kb
Host smart-9949e189-dd6d-4b1d-b307-f0e6ccab6881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364238446 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3364238446
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3892818284
Short name T991
Test name
Test status
Simulation time 1166033029 ps
CPU time 4.79 seconds
Started Jul 27 05:55:57 PM PDT 24
Finished Jul 27 05:56:02 PM PDT 24
Peak memory 217044 kb
Host smart-4a100ff5-fe52-426b-86e6-1c6cf057da46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892818284 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3892818284
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2938211944
Short name T463
Test name
Test status
Simulation time 55923750909 ps
CPU time 1428.23 seconds
Started Jul 27 05:55:59 PM PDT 24
Finished Jul 27 06:19:48 PM PDT 24
Peak memory 224248 kb
Host smart-bc116260-ceff-4a22-ae0f-471c3635277c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938211944 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2938211944
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.3157733627
Short name T948
Test name
Test status
Simulation time 26091874 ps
CPU time 1.23 seconds
Started Jul 27 05:57:06 PM PDT 24
Finished Jul 27 05:57:08 PM PDT 24
Peak memory 219084 kb
Host smart-257e194a-5300-407d-8915-4e5c38d6f19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157733627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.3157733627
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.35963686
Short name T103
Test name
Test status
Simulation time 22156456 ps
CPU time 1.04 seconds
Started Jul 27 05:57:15 PM PDT 24
Finished Jul 27 05:57:16 PM PDT 24
Peak memory 219708 kb
Host smart-23eda376-6df7-4bbf-84a5-7120644451f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35963686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.35963686
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3593180935
Short name T321
Test name
Test status
Simulation time 28731849 ps
CPU time 1.3 seconds
Started Jul 27 05:57:10 PM PDT 24
Finished Jul 27 05:57:11 PM PDT 24
Peak memory 219856 kb
Host smart-01c78412-41da-4336-869f-2ef7672ae1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593180935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3593180935
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.4043340795
Short name T684
Test name
Test status
Simulation time 38285366 ps
CPU time 1.11 seconds
Started Jul 27 05:57:13 PM PDT 24
Finished Jul 27 05:57:14 PM PDT 24
Peak memory 219672 kb
Host smart-507e3751-ed6e-497a-8daf-beb751309bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043340795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.4043340795
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.204375935
Short name T802
Test name
Test status
Simulation time 32498225 ps
CPU time 0.93 seconds
Started Jul 27 05:57:13 PM PDT 24
Finished Jul 27 05:57:14 PM PDT 24
Peak memory 218420 kb
Host smart-b559aa82-b052-423c-b811-5793fccf663d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204375935 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.204375935
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.4202185918
Short name T328
Test name
Test status
Simulation time 34306548 ps
CPU time 1.07 seconds
Started Jul 27 05:57:05 PM PDT 24
Finished Jul 27 05:57:06 PM PDT 24
Peak memory 218736 kb
Host smart-b2c17f58-9ceb-4823-a795-315a216e5f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202185918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.4202185918
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3858917129
Short name T969
Test name
Test status
Simulation time 41728794 ps
CPU time 1.16 seconds
Started Jul 27 05:57:18 PM PDT 24
Finished Jul 27 05:57:19 PM PDT 24
Peak memory 220068 kb
Host smart-5953457d-be75-4fa8-9607-b33aff4e9f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858917129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3858917129
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.2292496599
Short name T112
Test name
Test status
Simulation time 23277158 ps
CPU time 1.13 seconds
Started Jul 27 05:57:17 PM PDT 24
Finished Jul 27 05:57:18 PM PDT 24
Peak memory 219500 kb
Host smart-26048f8b-7fde-4d2f-bfa7-1ac024fbb897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292496599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2292496599
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3174336525
Short name T470
Test name
Test status
Simulation time 87299524 ps
CPU time 1.38 seconds
Started Jul 27 05:57:07 PM PDT 24
Finished Jul 27 05:57:09 PM PDT 24
Peak memory 218396 kb
Host smart-36a7a57a-5e69-4784-a30c-00ffc72cf934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174336525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3174336525
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1303718870
Short name T650
Test name
Test status
Simulation time 29295052 ps
CPU time 1.12 seconds
Started Jul 27 05:57:07 PM PDT 24
Finished Jul 27 05:57:09 PM PDT 24
Peak memory 219800 kb
Host smart-8236dbb4-50cf-4ac8-8614-40776e498e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303718870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1303718870
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.982933223
Short name T698
Test name
Test status
Simulation time 32842306 ps
CPU time 1.56 seconds
Started Jul 27 05:57:16 PM PDT 24
Finished Jul 27 05:57:17 PM PDT 24
Peak memory 225580 kb
Host smart-b8fb9226-7d44-4ca2-8897-b01ce850b022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982933223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.982933223
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_alert.1453704843
Short name T405
Test name
Test status
Simulation time 109657460 ps
CPU time 1.24 seconds
Started Jul 27 05:57:19 PM PDT 24
Finished Jul 27 05:57:21 PM PDT 24
Peak memory 219076 kb
Host smart-6a1b5781-9a9d-4aab-8b21-56db653b1ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453704843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1453704843
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.2061911059
Short name T569
Test name
Test status
Simulation time 19034495 ps
CPU time 1.14 seconds
Started Jul 27 05:57:15 PM PDT 24
Finished Jul 27 05:57:16 PM PDT 24
Peak memory 218632 kb
Host smart-1d9d35f6-2dc5-4538-acb5-7e1309f4a5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061911059 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2061911059
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2153336708
Short name T518
Test name
Test status
Simulation time 81287617 ps
CPU time 1.33 seconds
Started Jul 27 05:57:17 PM PDT 24
Finished Jul 27 05:57:19 PM PDT 24
Peak memory 218700 kb
Host smart-73d91b63-4487-4560-bdfd-ea59a95e6117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153336708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2153336708
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.2029473459
Short name T61
Test name
Test status
Simulation time 23741306 ps
CPU time 1.2 seconds
Started Jul 27 05:57:14 PM PDT 24
Finished Jul 27 05:57:15 PM PDT 24
Peak memory 218456 kb
Host smart-89b08417-10ec-46f1-bdf8-7d74b3638e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029473459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2029473459
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3638169023
Short name T183
Test name
Test status
Simulation time 24930928 ps
CPU time 1.12 seconds
Started Jul 27 05:57:14 PM PDT 24
Finished Jul 27 05:57:16 PM PDT 24
Peak memory 223936 kb
Host smart-d4525bbd-60e0-4a3c-a977-ff957fde4fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638169023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3638169023
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2838542453
Short name T426
Test name
Test status
Simulation time 190748081 ps
CPU time 2.95 seconds
Started Jul 27 05:57:07 PM PDT 24
Finished Jul 27 05:57:11 PM PDT 24
Peak memory 219080 kb
Host smart-2ff75750-9f7c-4aa2-8d01-81a7ea4e674c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838542453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2838542453
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.933551091
Short name T132
Test name
Test status
Simulation time 82461101 ps
CPU time 1.16 seconds
Started Jul 27 05:57:10 PM PDT 24
Finished Jul 27 05:57:11 PM PDT 24
Peak memory 219668 kb
Host smart-95d89630-307a-41a0-bde0-477ccf27be68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933551091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.933551091
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.1210813944
Short name T806
Test name
Test status
Simulation time 22268583 ps
CPU time 1.13 seconds
Started Jul 27 05:57:20 PM PDT 24
Finished Jul 27 05:57:21 PM PDT 24
Peak memory 219432 kb
Host smart-75730739-1325-42e3-837d-bb9e498ec7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210813944 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1210813944
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.495909578
Short name T32
Test name
Test status
Simulation time 103390741 ps
CPU time 1.36 seconds
Started Jul 27 05:57:15 PM PDT 24
Finished Jul 27 05:57:17 PM PDT 24
Peak memory 218564 kb
Host smart-f17e880d-6912-45f8-bc47-059cf0b893c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495909578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.495909578
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3065288840
Short name T441
Test name
Test status
Simulation time 18938295 ps
CPU time 1.16 seconds
Started Jul 27 05:57:22 PM PDT 24
Finished Jul 27 05:57:23 PM PDT 24
Peak memory 232676 kb
Host smart-c60a968b-fbf0-4b18-8d0d-1c7d8bb48851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065288840 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3065288840
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1797932318
Short name T73
Test name
Test status
Simulation time 75880496 ps
CPU time 1.56 seconds
Started Jul 27 05:57:20 PM PDT 24
Finished Jul 27 05:57:21 PM PDT 24
Peak memory 218760 kb
Host smart-0592e2b2-d0b3-4383-bd2a-333c4c064c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797932318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1797932318
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.4119725841
Short name T805
Test name
Test status
Simulation time 40375815 ps
CPU time 1.13 seconds
Started Jul 27 05:57:24 PM PDT 24
Finished Jul 27 05:57:26 PM PDT 24
Peak memory 219616 kb
Host smart-d70c17bb-b07f-414f-be14-8586b5b7ed49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119725841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.4119725841
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.685629586
Short name T111
Test name
Test status
Simulation time 22813727 ps
CPU time 1.1 seconds
Started Jul 27 05:57:17 PM PDT 24
Finished Jul 27 05:57:18 PM PDT 24
Peak memory 218332 kb
Host smart-4dca2c82-cc16-4b4e-9302-244ae9852127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685629586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.685629586
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1765847961
Short name T511
Test name
Test status
Simulation time 25176205 ps
CPU time 1.3 seconds
Started Jul 27 05:57:16 PM PDT 24
Finished Jul 27 05:57:18 PM PDT 24
Peak memory 218388 kb
Host smart-bde5d7a8-11e2-429b-acc1-fcfa0926b599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765847961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1765847961
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.1204923802
Short name T498
Test name
Test status
Simulation time 25690807 ps
CPU time 1.32 seconds
Started Jul 27 05:57:17 PM PDT 24
Finished Jul 27 05:57:18 PM PDT 24
Peak memory 218160 kb
Host smart-fbf372bd-e2ae-4fee-9175-485a8bc8f128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204923802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.1204923802
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.1318168060
Short name T830
Test name
Test status
Simulation time 33246486 ps
CPU time 1.09 seconds
Started Jul 27 05:57:21 PM PDT 24
Finished Jul 27 05:57:22 PM PDT 24
Peak memory 223704 kb
Host smart-3e829aea-233d-4da4-b660-caa595b6ee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318168060 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1318168060
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3577226975
Short name T365
Test name
Test status
Simulation time 220771172 ps
CPU time 1.64 seconds
Started Jul 27 05:57:23 PM PDT 24
Finished Jul 27 05:57:24 PM PDT 24
Peak memory 219944 kb
Host smart-e79738de-256a-4532-9f95-3e9d28389652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577226975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3577226975
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2069532356
Short name T205
Test name
Test status
Simulation time 46701296 ps
CPU time 1.19 seconds
Started Jul 27 05:55:59 PM PDT 24
Finished Jul 27 05:56:00 PM PDT 24
Peak memory 218404 kb
Host smart-ea5df21d-8847-4223-b161-ec7ae3e46859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069532356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2069532356
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1100337082
Short name T357
Test name
Test status
Simulation time 29621938 ps
CPU time 0.94 seconds
Started Jul 27 05:55:56 PM PDT 24
Finished Jul 27 05:55:57 PM PDT 24
Peak memory 206564 kb
Host smart-d9f3785f-5c0e-48fb-be2e-b64c3d74c935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100337082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1100337082
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3471569747
Short name T841
Test name
Test status
Simulation time 19397298 ps
CPU time 0.87 seconds
Started Jul 27 05:55:56 PM PDT 24
Finished Jul 27 05:55:57 PM PDT 24
Peak memory 216112 kb
Host smart-a6ec723d-400c-43dd-9e40-3c9aedfc60af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471569747 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3471569747
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.517955446
Short name T430
Test name
Test status
Simulation time 74254642 ps
CPU time 1.06 seconds
Started Jul 27 05:55:58 PM PDT 24
Finished Jul 27 05:55:59 PM PDT 24
Peak memory 218388 kb
Host smart-afe2cd05-55e2-401e-b7ff-bc9c6a1d7a4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517955446 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.517955446
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3929997325
Short name T207
Test name
Test status
Simulation time 27179611 ps
CPU time 1.04 seconds
Started Jul 27 05:55:57 PM PDT 24
Finished Jul 27 05:55:58 PM PDT 24
Peak memory 224056 kb
Host smart-274a511a-3b40-45e9-9651-165d5a1d6fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929997325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3929997325
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.4154021133
Short name T633
Test name
Test status
Simulation time 652108924 ps
CPU time 4.87 seconds
Started Jul 27 05:55:58 PM PDT 24
Finished Jul 27 05:56:03 PM PDT 24
Peak memory 219656 kb
Host smart-837d7b79-491a-4294-848d-b13ad5a530dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154021133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4154021133
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3813436684
Short name T87
Test name
Test status
Simulation time 34166514 ps
CPU time 0.92 seconds
Started Jul 27 05:55:56 PM PDT 24
Finished Jul 27 05:55:57 PM PDT 24
Peak memory 215516 kb
Host smart-5657f5bb-1806-46b2-bb30-28878e7057cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813436684 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3813436684
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.958097456
Short name T970
Test name
Test status
Simulation time 91820544 ps
CPU time 0.87 seconds
Started Jul 27 05:56:00 PM PDT 24
Finished Jul 27 05:56:01 PM PDT 24
Peak memory 215156 kb
Host smart-decc9b21-3712-4a00-a8f1-e1f5ae96d25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958097456 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.958097456
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1219467480
Short name T55
Test name
Test status
Simulation time 874822050 ps
CPU time 3.32 seconds
Started Jul 27 05:56:00 PM PDT 24
Finished Jul 27 05:56:04 PM PDT 24
Peak memory 217044 kb
Host smart-0a63589d-51f4-4a79-b14c-f247f3584a8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219467480 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1219467480
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.4242877295
Short name T230
Test name
Test status
Simulation time 41899446415 ps
CPU time 563.08 seconds
Started Jul 27 05:55:55 PM PDT 24
Finished Jul 27 06:05:19 PM PDT 24
Peak memory 223552 kb
Host smart-7e36e715-6712-4e7e-857f-ba068a06a599
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242877295 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.4242877295
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.1716247451
Short name T820
Test name
Test status
Simulation time 258093159 ps
CPU time 1.33 seconds
Started Jul 27 05:57:19 PM PDT 24
Finished Jul 27 05:57:21 PM PDT 24
Peak memory 215528 kb
Host smart-f83a7f0b-fd85-44d8-b3af-760f51be97d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716247451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.1716247451
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.1854530189
Short name T377
Test name
Test status
Simulation time 18302156 ps
CPU time 1.07 seconds
Started Jul 27 05:57:25 PM PDT 24
Finished Jul 27 05:57:26 PM PDT 24
Peak memory 218276 kb
Host smart-484357b2-1d33-4b81-83cb-58f4bf9b7d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854530189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1854530189
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1351166473
Short name T310
Test name
Test status
Simulation time 42961110 ps
CPU time 1.11 seconds
Started Jul 27 05:57:16 PM PDT 24
Finished Jul 27 05:57:17 PM PDT 24
Peak memory 217440 kb
Host smart-fee5af1d-4a84-415b-a4d4-96585a62fcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351166473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1351166473
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1099508607
Short name T914
Test name
Test status
Simulation time 42112739 ps
CPU time 1.22 seconds
Started Jul 27 05:57:14 PM PDT 24
Finished Jul 27 05:57:15 PM PDT 24
Peak memory 218480 kb
Host smart-12e60801-2588-4b45-8ddc-f177953bfbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099508607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1099508607
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.1180547594
Short name T126
Test name
Test status
Simulation time 30566036 ps
CPU time 0.92 seconds
Started Jul 27 05:57:16 PM PDT 24
Finished Jul 27 05:57:17 PM PDT 24
Peak memory 219136 kb
Host smart-9218adf5-2ee4-43ec-9feb-50011bfa3622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180547594 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1180547594
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2398924809
Short name T596
Test name
Test status
Simulation time 68418748 ps
CPU time 1.58 seconds
Started Jul 27 05:57:17 PM PDT 24
Finished Jul 27 05:57:18 PM PDT 24
Peak memory 218768 kb
Host smart-124ce80d-83a7-423a-8f73-c249e88421f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398924809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2398924809
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.3748166125
Short name T920
Test name
Test status
Simulation time 23423281 ps
CPU time 1.12 seconds
Started Jul 27 05:57:13 PM PDT 24
Finished Jul 27 05:57:15 PM PDT 24
Peak memory 218368 kb
Host smart-9fc992fa-be39-4053-bec3-5df122af466f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748166125 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.3748166125
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.1774402238
Short name T937
Test name
Test status
Simulation time 40502439 ps
CPU time 1.04 seconds
Started Jul 27 05:57:16 PM PDT 24
Finished Jul 27 05:57:17 PM PDT 24
Peak memory 223892 kb
Host smart-911fb3fd-30ce-41fb-8fe0-b9774803d71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774402238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1774402238
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2845288008
Short name T375
Test name
Test status
Simulation time 84724782 ps
CPU time 1.43 seconds
Started Jul 27 05:57:25 PM PDT 24
Finished Jul 27 05:57:26 PM PDT 24
Peak memory 219900 kb
Host smart-89d2b6d1-2038-40f4-93c3-a8907cd4f1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845288008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2845288008
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.3812847005
Short name T957
Test name
Test status
Simulation time 72907590 ps
CPU time 1.19 seconds
Started Jul 27 05:57:18 PM PDT 24
Finished Jul 27 05:57:19 PM PDT 24
Peak memory 219520 kb
Host smart-3e149205-22c8-40c0-ae91-c426dba3e2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812847005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.3812847005
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.2822100912
Short name T949
Test name
Test status
Simulation time 20157706 ps
CPU time 1.07 seconds
Started Jul 27 05:57:17 PM PDT 24
Finished Jul 27 05:57:19 PM PDT 24
Peak memory 219472 kb
Host smart-04aea1c0-ff22-4825-9f32-ad6cdb6d1998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822100912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2822100912
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2226214570
Short name T752
Test name
Test status
Simulation time 226199130 ps
CPU time 3.15 seconds
Started Jul 27 05:57:16 PM PDT 24
Finished Jul 27 05:57:19 PM PDT 24
Peak memory 219916 kb
Host smart-41854d67-fb80-45f9-9670-beaf0236556c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226214570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2226214570
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1604893443
Short name T306
Test name
Test status
Simulation time 200791750 ps
CPU time 1.26 seconds
Started Jul 27 05:57:14 PM PDT 24
Finished Jul 27 05:57:16 PM PDT 24
Peak memory 218808 kb
Host smart-c0c5347e-192b-41b6-8045-8b6c56cd42ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604893443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1604893443
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.3049155622
Short name T197
Test name
Test status
Simulation time 19023670 ps
CPU time 1.14 seconds
Started Jul 27 05:57:27 PM PDT 24
Finished Jul 27 05:57:28 PM PDT 24
Peak memory 223912 kb
Host smart-ea3ed30f-3a24-4c78-9945-d5edfa7a42bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049155622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3049155622
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2076139596
Short name T585
Test name
Test status
Simulation time 58752264 ps
CPU time 1.33 seconds
Started Jul 27 05:57:18 PM PDT 24
Finished Jul 27 05:57:20 PM PDT 24
Peak memory 218264 kb
Host smart-43019a78-dcaa-4872-8707-03940bdc7066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076139596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2076139596
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.1137524129
Short name T679
Test name
Test status
Simulation time 79679418 ps
CPU time 1.21 seconds
Started Jul 27 05:57:24 PM PDT 24
Finished Jul 27 05:57:25 PM PDT 24
Peak memory 219692 kb
Host smart-d5c06706-7be3-4f6a-a926-f84ddd26c0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137524129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.1137524129
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.3056071321
Short name T988
Test name
Test status
Simulation time 19114119 ps
CPU time 1.15 seconds
Started Jul 27 05:57:28 PM PDT 24
Finished Jul 27 05:57:29 PM PDT 24
Peak memory 229476 kb
Host smart-8a80c07e-90ba-4a2f-a998-cb393de524ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056071321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3056071321
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3180578983
Short name T399
Test name
Test status
Simulation time 192482870 ps
CPU time 1.69 seconds
Started Jul 27 05:57:21 PM PDT 24
Finished Jul 27 05:57:23 PM PDT 24
Peak memory 219040 kb
Host smart-070dd2e8-5ed3-4668-8d38-b806a5283d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180578983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3180578983
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.111505270
Short name T738
Test name
Test status
Simulation time 26619611 ps
CPU time 1.26 seconds
Started Jul 27 05:57:16 PM PDT 24
Finished Jul 27 05:57:17 PM PDT 24
Peak memory 220752 kb
Host smart-2338b7de-6355-4430-bc14-f2214c67c2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111505270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.111505270
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3811980543
Short name T48
Test name
Test status
Simulation time 21581739 ps
CPU time 1.1 seconds
Started Jul 27 05:57:23 PM PDT 24
Finished Jul 27 05:57:25 PM PDT 24
Peak memory 223920 kb
Host smart-98cf8c02-7b09-4782-8455-5f40bc8cd75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811980543 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3811980543
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3599854722
Short name T834
Test name
Test status
Simulation time 46672968 ps
CPU time 1.46 seconds
Started Jul 27 05:57:17 PM PDT 24
Finished Jul 27 05:57:19 PM PDT 24
Peak memory 218256 kb
Host smart-32082ec3-c729-4ff4-8674-336070a728e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599854722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3599854722
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.1292350516
Short name T530
Test name
Test status
Simulation time 45364038 ps
CPU time 1.27 seconds
Started Jul 27 05:57:16 PM PDT 24
Finished Jul 27 05:57:17 PM PDT 24
Peak memory 219516 kb
Host smart-da8e450d-d83c-4796-b71d-6f2666f99206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292350516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.1292350516
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.291123876
Short name T690
Test name
Test status
Simulation time 23291997 ps
CPU time 1.33 seconds
Started Jul 27 05:57:18 PM PDT 24
Finished Jul 27 05:57:19 PM PDT 24
Peak memory 223820 kb
Host smart-6892d974-6890-45a3-a085-17625cce5e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291123876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.291123876
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1286222094
Short name T697
Test name
Test status
Simulation time 63026128 ps
CPU time 1.3 seconds
Started Jul 27 05:57:17 PM PDT 24
Finished Jul 27 05:57:18 PM PDT 24
Peak memory 218544 kb
Host smart-58f167c8-daff-4a0c-b373-9f7f1f0e0872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286222094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1286222094
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.869053732
Short name T142
Test name
Test status
Simulation time 105108484 ps
CPU time 1.08 seconds
Started Jul 27 05:57:15 PM PDT 24
Finished Jul 27 05:57:16 PM PDT 24
Peak memory 220532 kb
Host smart-f895ddec-9e25-48e5-b9a3-3f96bcd28f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869053732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.869053732
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2186721375
Short name T593
Test name
Test status
Simulation time 52812866 ps
CPU time 1.64 seconds
Started Jul 27 05:57:27 PM PDT 24
Finished Jul 27 05:57:29 PM PDT 24
Peak memory 215172 kb
Host smart-c1f20072-7e92-4d45-b597-34dfb9459807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186721375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2186721375
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.1902247837
Short name T161
Test name
Test status
Simulation time 118037208 ps
CPU time 1.02 seconds
Started Jul 27 05:57:18 PM PDT 24
Finished Jul 27 05:57:20 PM PDT 24
Peak memory 220532 kb
Host smart-43670633-bb84-4d1d-b649-810ac9b27dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902247837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1902247837
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1881863020
Short name T838
Test name
Test status
Simulation time 128417638 ps
CPU time 1.27 seconds
Started Jul 27 05:57:25 PM PDT 24
Finished Jul 27 05:57:26 PM PDT 24
Peak memory 217292 kb
Host smart-21aff724-c1c2-457f-8617-4613ed073e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881863020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1881863020
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%