Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.54 98.25 93.31 90.85 88.37 95.50 96.83 91.70


Total test records in report: 1125
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T1014 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4268727270 Jul 28 05:31:36 PM PDT 24 Jul 28 05:31:37 PM PDT 24 14684831 ps
T281 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3955794910 Jul 28 05:31:36 PM PDT 24 Jul 28 05:31:37 PM PDT 24 78294323 ps
T1015 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2719466032 Jul 28 05:31:57 PM PDT 24 Jul 28 05:31:59 PM PDT 24 49138520 ps
T1016 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2881467507 Jul 28 05:31:42 PM PDT 24 Jul 28 05:31:44 PM PDT 24 117907921 ps
T1017 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2133525070 Jul 28 05:31:35 PM PDT 24 Jul 28 05:31:38 PM PDT 24 159850271 ps
T282 /workspace/coverage/cover_reg_top/7.edn_csr_rw.4157929754 Jul 28 05:31:45 PM PDT 24 Jul 28 05:31:46 PM PDT 24 26507269 ps
T293 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1845339668 Jul 28 05:31:48 PM PDT 24 Jul 28 05:31:49 PM PDT 24 12988714 ps
T294 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4115708334 Jul 28 05:31:45 PM PDT 24 Jul 28 05:31:46 PM PDT 24 19503736 ps
T1018 /workspace/coverage/cover_reg_top/8.edn_intr_test.3248273105 Jul 28 05:31:44 PM PDT 24 Jul 28 05:31:45 PM PDT 24 44038089 ps
T283 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1731131637 Jul 28 05:31:39 PM PDT 24 Jul 28 05:31:45 PM PDT 24 667250227 ps
T1019 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3518535908 Jul 28 05:31:51 PM PDT 24 Jul 28 05:31:52 PM PDT 24 21931083 ps
T1020 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1415426508 Jul 28 05:31:43 PM PDT 24 Jul 28 05:31:48 PM PDT 24 109424719 ps
T1021 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.618981109 Jul 28 05:31:36 PM PDT 24 Jul 28 05:31:37 PM PDT 24 13244351 ps
T295 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2193006368 Jul 28 05:31:53 PM PDT 24 Jul 28 05:31:54 PM PDT 24 22793974 ps
T284 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.143293733 Jul 28 05:31:32 PM PDT 24 Jul 28 05:31:33 PM PDT 24 28425534 ps
T1022 /workspace/coverage/cover_reg_top/42.edn_intr_test.1802903358 Jul 28 05:31:58 PM PDT 24 Jul 28 05:31:59 PM PDT 24 12537204 ps
T1023 /workspace/coverage/cover_reg_top/39.edn_intr_test.2902870392 Jul 28 05:31:59 PM PDT 24 Jul 28 05:32:00 PM PDT 24 20980764 ps
T285 /workspace/coverage/cover_reg_top/2.edn_csr_rw.4258079111 Jul 28 05:31:38 PM PDT 24 Jul 28 05:31:39 PM PDT 24 19834548 ps
T1024 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3332926872 Jul 28 05:31:41 PM PDT 24 Jul 28 05:31:46 PM PDT 24 733339683 ps
T1025 /workspace/coverage/cover_reg_top/1.edn_intr_test.659616455 Jul 28 05:31:31 PM PDT 24 Jul 28 05:31:32 PM PDT 24 51221566 ps
T1026 /workspace/coverage/cover_reg_top/25.edn_intr_test.1844902201 Jul 28 05:32:03 PM PDT 24 Jul 28 05:32:04 PM PDT 24 47392638 ps
T1027 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3057730357 Jul 28 05:31:58 PM PDT 24 Jul 28 05:31:59 PM PDT 24 48604624 ps
T1028 /workspace/coverage/cover_reg_top/36.edn_intr_test.1212253904 Jul 28 05:32:03 PM PDT 24 Jul 28 05:32:04 PM PDT 24 14360373 ps
T1029 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3745382957 Jul 28 05:31:36 PM PDT 24 Jul 28 05:31:38 PM PDT 24 449041141 ps
T1030 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.538566015 Jul 28 05:31:31 PM PDT 24 Jul 28 05:31:32 PM PDT 24 30281254 ps
T286 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1310255221 Jul 28 05:31:40 PM PDT 24 Jul 28 05:31:41 PM PDT 24 16599580 ps
T1031 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1283320613 Jul 28 05:31:50 PM PDT 24 Jul 28 05:31:53 PM PDT 24 35456779 ps
T1032 /workspace/coverage/cover_reg_top/37.edn_intr_test.3239980734 Jul 28 05:32:01 PM PDT 24 Jul 28 05:32:02 PM PDT 24 19656852 ps
T1033 /workspace/coverage/cover_reg_top/5.edn_intr_test.4087145082 Jul 28 05:31:42 PM PDT 24 Jul 28 05:31:43 PM PDT 24 31415687 ps
T1034 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3214827884 Jul 28 05:31:50 PM PDT 24 Jul 28 05:31:53 PM PDT 24 94980286 ps
T1035 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2834943716 Jul 28 05:32:03 PM PDT 24 Jul 28 05:32:04 PM PDT 24 18738447 ps
T304 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2278187151 Jul 28 05:31:29 PM PDT 24 Jul 28 05:31:32 PM PDT 24 88127567 ps
T1036 /workspace/coverage/cover_reg_top/18.edn_csr_rw.354281035 Jul 28 05:32:02 PM PDT 24 Jul 28 05:32:03 PM PDT 24 68812564 ps
T1037 /workspace/coverage/cover_reg_top/45.edn_intr_test.1076961264 Jul 28 05:31:59 PM PDT 24 Jul 28 05:32:00 PM PDT 24 12801818 ps
T1038 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.325808171 Jul 28 05:31:43 PM PDT 24 Jul 28 05:31:45 PM PDT 24 41893905 ps
T287 /workspace/coverage/cover_reg_top/8.edn_csr_rw.659871140 Jul 28 05:31:44 PM PDT 24 Jul 28 05:31:45 PM PDT 24 50284003 ps
T1039 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1420520348 Jul 28 05:31:48 PM PDT 24 Jul 28 05:31:49 PM PDT 24 50101966 ps
T1040 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1347208875 Jul 28 05:31:44 PM PDT 24 Jul 28 05:31:46 PM PDT 24 90693675 ps
T1041 /workspace/coverage/cover_reg_top/49.edn_intr_test.271359789 Jul 28 05:32:05 PM PDT 24 Jul 28 05:32:06 PM PDT 24 46510748 ps
T1042 /workspace/coverage/cover_reg_top/9.edn_tl_errors.4037808508 Jul 28 05:31:43 PM PDT 24 Jul 28 05:31:46 PM PDT 24 137408443 ps
T1043 /workspace/coverage/cover_reg_top/43.edn_intr_test.3715954004 Jul 28 05:32:00 PM PDT 24 Jul 28 05:32:01 PM PDT 24 38556121 ps
T1044 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.828235457 Jul 28 05:31:51 PM PDT 24 Jul 28 05:31:52 PM PDT 24 30093061 ps
T1045 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1773831286 Jul 28 05:32:05 PM PDT 24 Jul 28 05:32:08 PM PDT 24 397433182 ps
T1046 /workspace/coverage/cover_reg_top/1.edn_tl_errors.4063043665 Jul 28 05:31:31 PM PDT 24 Jul 28 05:31:34 PM PDT 24 555336659 ps
T1047 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3617215546 Jul 28 05:31:52 PM PDT 24 Jul 28 05:32:07 PM PDT 24 923622133 ps
T1048 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3239180703 Jul 28 05:31:50 PM PDT 24 Jul 28 05:31:54 PM PDT 24 166601769 ps
T1049 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.188736817 Jul 28 05:31:51 PM PDT 24 Jul 28 05:31:52 PM PDT 24 16948401 ps
T1050 /workspace/coverage/cover_reg_top/17.edn_intr_test.2170705365 Jul 28 05:32:01 PM PDT 24 Jul 28 05:32:01 PM PDT 24 40673684 ps
T1051 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3599191936 Jul 28 05:31:30 PM PDT 24 Jul 28 05:31:32 PM PDT 24 118368131 ps
T1052 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2359902895 Jul 28 05:31:42 PM PDT 24 Jul 28 05:31:44 PM PDT 24 105838027 ps
T1053 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3555681856 Jul 28 05:31:48 PM PDT 24 Jul 28 05:31:49 PM PDT 24 21373738 ps
T1054 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1458561980 Jul 28 05:31:55 PM PDT 24 Jul 28 05:31:56 PM PDT 24 19111070 ps
T1055 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2519652730 Jul 28 05:31:59 PM PDT 24 Jul 28 05:32:01 PM PDT 24 73025199 ps
T1056 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1999050246 Jul 28 05:31:52 PM PDT 24 Jul 28 05:31:53 PM PDT 24 63093745 ps
T1057 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.16213864 Jul 28 05:31:50 PM PDT 24 Jul 28 05:31:52 PM PDT 24 142489302 ps
T1058 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1435144382 Jul 28 05:31:37 PM PDT 24 Jul 28 05:31:44 PM PDT 24 436961610 ps
T1059 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1366238936 Jul 28 05:31:39 PM PDT 24 Jul 28 05:31:40 PM PDT 24 32670558 ps
T1060 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2413904528 Jul 28 05:31:28 PM PDT 24 Jul 28 05:31:29 PM PDT 24 46569931 ps
T1061 /workspace/coverage/cover_reg_top/18.edn_intr_test.521201091 Jul 28 05:31:59 PM PDT 24 Jul 28 05:32:00 PM PDT 24 13206162 ps
T1062 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2543541454 Jul 28 05:31:35 PM PDT 24 Jul 28 05:31:37 PM PDT 24 81421032 ps
T1063 /workspace/coverage/cover_reg_top/28.edn_intr_test.2685887102 Jul 28 05:32:02 PM PDT 24 Jul 28 05:32:03 PM PDT 24 61387643 ps
T1064 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2487797121 Jul 28 05:31:35 PM PDT 24 Jul 28 05:31:41 PM PDT 24 577057842 ps
T1065 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.845097868 Jul 28 05:31:35 PM PDT 24 Jul 28 05:31:37 PM PDT 24 57212466 ps
T1066 /workspace/coverage/cover_reg_top/7.edn_intr_test.4219015871 Jul 28 05:31:46 PM PDT 24 Jul 28 05:31:47 PM PDT 24 19553477 ps
T288 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2304100584 Jul 28 05:31:35 PM PDT 24 Jul 28 05:31:36 PM PDT 24 127379181 ps
T1067 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3822355633 Jul 28 05:32:01 PM PDT 24 Jul 28 05:32:02 PM PDT 24 15258898 ps
T1068 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1424387235 Jul 28 05:32:00 PM PDT 24 Jul 28 05:32:01 PM PDT 24 31479811 ps
T1069 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1027190008 Jul 28 05:31:51 PM PDT 24 Jul 28 05:31:52 PM PDT 24 14500660 ps
T1070 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3211495032 Jul 28 05:31:30 PM PDT 24 Jul 28 05:31:34 PM PDT 24 416893239 ps
T1071 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1828990621 Jul 28 05:31:59 PM PDT 24 Jul 28 05:32:04 PM PDT 24 266233682 ps
T1072 /workspace/coverage/cover_reg_top/14.edn_intr_test.16640489 Jul 28 05:31:56 PM PDT 24 Jul 28 05:31:57 PM PDT 24 42576385 ps
T1073 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1145037677 Jul 28 05:31:50 PM PDT 24 Jul 28 05:31:52 PM PDT 24 175985535 ps
T1074 /workspace/coverage/cover_reg_top/21.edn_intr_test.915648304 Jul 28 05:31:58 PM PDT 24 Jul 28 05:31:59 PM PDT 24 14211775 ps
T1075 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3812509474 Jul 28 05:31:42 PM PDT 24 Jul 28 05:31:44 PM PDT 24 67338753 ps
T1076 /workspace/coverage/cover_reg_top/38.edn_intr_test.1213976582 Jul 28 05:32:02 PM PDT 24 Jul 28 05:32:03 PM PDT 24 30903420 ps
T1077 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3440324863 Jul 28 05:31:45 PM PDT 24 Jul 28 05:31:49 PM PDT 24 91889239 ps
T1078 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1137299826 Jul 28 05:31:50 PM PDT 24 Jul 28 05:31:52 PM PDT 24 145022884 ps
T1079 /workspace/coverage/cover_reg_top/3.edn_intr_test.1481310351 Jul 28 05:31:36 PM PDT 24 Jul 28 05:31:37 PM PDT 24 50609792 ps
T1080 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1690304767 Jul 28 05:31:59 PM PDT 24 Jul 28 05:32:02 PM PDT 24 152726079 ps
T1081 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1845714340 Jul 28 05:31:51 PM PDT 24 Jul 28 05:31:57 PM PDT 24 363211400 ps
T1082 /workspace/coverage/cover_reg_top/23.edn_intr_test.1806761634 Jul 28 05:32:01 PM PDT 24 Jul 28 05:32:02 PM PDT 24 57715505 ps
T1083 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4199729099 Jul 28 05:31:29 PM PDT 24 Jul 28 05:31:31 PM PDT 24 769448326 ps
T1084 /workspace/coverage/cover_reg_top/17.edn_tl_errors.583233284 Jul 28 05:31:53 PM PDT 24 Jul 28 05:31:56 PM PDT 24 69778113 ps
T1085 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2311687321 Jul 28 05:31:51 PM PDT 24 Jul 28 05:31:53 PM PDT 24 696382844 ps
T1086 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2572506050 Jul 28 05:31:56 PM PDT 24 Jul 28 05:31:58 PM PDT 24 25916960 ps
T1087 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3061834453 Jul 28 05:32:02 PM PDT 24 Jul 28 05:32:03 PM PDT 24 22954030 ps
T1088 /workspace/coverage/cover_reg_top/35.edn_intr_test.1145757776 Jul 28 05:32:00 PM PDT 24 Jul 28 05:32:01 PM PDT 24 15558490 ps
T1089 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2015449060 Jul 28 05:31:48 PM PDT 24 Jul 28 05:31:50 PM PDT 24 37550791 ps
T1090 /workspace/coverage/cover_reg_top/11.edn_intr_test.2204402977 Jul 28 05:31:55 PM PDT 24 Jul 28 05:31:56 PM PDT 24 55548279 ps
T1091 /workspace/coverage/cover_reg_top/12.edn_intr_test.198044469 Jul 28 05:31:50 PM PDT 24 Jul 28 05:31:51 PM PDT 24 177776821 ps
T1092 /workspace/coverage/cover_reg_top/9.edn_intr_test.2353360697 Jul 28 05:31:43 PM PDT 24 Jul 28 05:31:44 PM PDT 24 37302549 ps
T1093 /workspace/coverage/cover_reg_top/41.edn_intr_test.1877679742 Jul 28 05:32:02 PM PDT 24 Jul 28 05:32:03 PM PDT 24 17573249 ps
T1094 /workspace/coverage/cover_reg_top/20.edn_intr_test.3412328019 Jul 28 05:32:03 PM PDT 24 Jul 28 05:32:04 PM PDT 24 15257711 ps
T1095 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3877679710 Jul 28 05:31:47 PM PDT 24 Jul 28 05:31:51 PM PDT 24 808568751 ps
T1096 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2609321189 Jul 28 05:31:53 PM PDT 24 Jul 28 05:31:55 PM PDT 24 53420957 ps
T1097 /workspace/coverage/cover_reg_top/2.edn_intr_test.2618281154 Jul 28 05:31:36 PM PDT 24 Jul 28 05:31:37 PM PDT 24 16522615 ps
T1098 /workspace/coverage/cover_reg_top/14.edn_csr_rw.704740716 Jul 28 05:31:51 PM PDT 24 Jul 28 05:31:52 PM PDT 24 50543314 ps
T1099 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1962453254 Jul 28 05:31:43 PM PDT 24 Jul 28 05:31:45 PM PDT 24 31153652 ps
T1100 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1575814194 Jul 28 05:31:42 PM PDT 24 Jul 28 05:31:43 PM PDT 24 54289289 ps
T1101 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2790523536 Jul 28 05:31:52 PM PDT 24 Jul 28 05:31:54 PM PDT 24 228797811 ps
T1102 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.379246034 Jul 28 05:31:43 PM PDT 24 Jul 28 05:31:45 PM PDT 24 174205130 ps
T1103 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2222155335 Jul 28 05:31:30 PM PDT 24 Jul 28 05:31:32 PM PDT 24 137548298 ps
T1104 /workspace/coverage/cover_reg_top/10.edn_intr_test.3298723330 Jul 28 05:31:54 PM PDT 24 Jul 28 05:31:55 PM PDT 24 36013302 ps
T1105 /workspace/coverage/cover_reg_top/40.edn_intr_test.271124163 Jul 28 05:31:59 PM PDT 24 Jul 28 05:31:59 PM PDT 24 28474248 ps
T1106 /workspace/coverage/cover_reg_top/27.edn_intr_test.3604725116 Jul 28 05:32:00 PM PDT 24 Jul 28 05:32:01 PM PDT 24 50396257 ps
T1107 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2746133055 Jul 28 05:31:59 PM PDT 24 Jul 28 05:32:00 PM PDT 24 19723992 ps
T1108 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1214551144 Jul 28 05:31:51 PM PDT 24 Jul 28 05:31:53 PM PDT 24 76648677 ps
T1109 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3787199743 Jul 28 05:31:55 PM PDT 24 Jul 28 05:31:56 PM PDT 24 17425354 ps
T289 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1202126823 Jul 28 05:31:37 PM PDT 24 Jul 28 05:31:39 PM PDT 24 44010946 ps
T1110 /workspace/coverage/cover_reg_top/48.edn_intr_test.4215523416 Jul 28 05:32:06 PM PDT 24 Jul 28 05:32:07 PM PDT 24 39171074 ps
T1111 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1600100271 Jul 28 05:32:01 PM PDT 24 Jul 28 05:32:02 PM PDT 24 61558180 ps
T1112 /workspace/coverage/cover_reg_top/32.edn_intr_test.2117309685 Jul 28 05:31:57 PM PDT 24 Jul 28 05:31:58 PM PDT 24 22479440 ps
T1113 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1896127141 Jul 28 05:31:37 PM PDT 24 Jul 28 05:31:39 PM PDT 24 255191703 ps
T1114 /workspace/coverage/cover_reg_top/4.edn_intr_test.2173769673 Jul 28 05:31:37 PM PDT 24 Jul 28 05:31:38 PM PDT 24 13045917 ps
T1115 /workspace/coverage/cover_reg_top/47.edn_intr_test.4224860353 Jul 28 05:32:09 PM PDT 24 Jul 28 05:32:10 PM PDT 24 42010346 ps
T1116 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1599269647 Jul 28 05:31:35 PM PDT 24 Jul 28 05:31:37 PM PDT 24 223257167 ps
T1117 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.282408215 Jul 28 05:31:44 PM PDT 24 Jul 28 05:31:46 PM PDT 24 49342976 ps
T1118 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2825772064 Jul 28 05:31:51 PM PDT 24 Jul 28 05:31:52 PM PDT 24 14175733 ps
T1119 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1933396792 Jul 28 05:31:59 PM PDT 24 Jul 28 05:32:04 PM PDT 24 189702306 ps
T1120 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.613542921 Jul 28 05:31:36 PM PDT 24 Jul 28 05:31:38 PM PDT 24 40816483 ps
T1121 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2193488315 Jul 28 05:32:00 PM PDT 24 Jul 28 05:32:02 PM PDT 24 27470214 ps
T1122 /workspace/coverage/cover_reg_top/19.edn_intr_test.175914125 Jul 28 05:32:00 PM PDT 24 Jul 28 05:32:01 PM PDT 24 18037452 ps
T1123 /workspace/coverage/cover_reg_top/6.edn_intr_test.3789148525 Jul 28 05:31:48 PM PDT 24 Jul 28 05:31:49 PM PDT 24 28023743 ps
T1124 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1893466901 Jul 28 05:31:36 PM PDT 24 Jul 28 05:31:37 PM PDT 24 27542064 ps
T1125 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3530449355 Jul 28 05:31:32 PM PDT 24 Jul 28 05:31:33 PM PDT 24 73526885 ps

Test location /workspace/coverage/default/19.edn_err.387266670
Short name T5
Test name
Test status
Simulation time 37333807 ps
CPU time 1.06 seconds
Started Jul 28 05:37:08 PM PDT 24
Finished Jul 28 05:37:09 PM PDT 24
Peak memory 219616 kb
Host smart-1a1010a6-fd10-4b90-a9f9-5cc16a46eb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387266670 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.387266670
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3681130858
Short name T18
Test name
Test status
Simulation time 57677163 ps
CPU time 1.84 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 219872 kb
Host smart-29538eb4-f46d-495c-9ebd-36fc3e062b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681130858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3681130858
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3090822787
Short name T23
Test name
Test status
Simulation time 48156262917 ps
CPU time 521.41 seconds
Started Jul 28 05:37:15 PM PDT 24
Finished Jul 28 05:45:57 PM PDT 24
Peak memory 217928 kb
Host smart-669ad5d5-bb7e-4ada-a7f9-def426ceb92d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090822787 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3090822787
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.edn_alert.558009769
Short name T67
Test name
Test status
Simulation time 29273437 ps
CPU time 1.34 seconds
Started Jul 28 05:38:14 PM PDT 24
Finished Jul 28 05:38:15 PM PDT 24
Peak memory 218604 kb
Host smart-64755431-6f17-411b-9c1f-3c86931e943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558009769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.558009769
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/5.edn_genbits.1078260959
Short name T28
Test name
Test status
Simulation time 111223894 ps
CPU time 1.52 seconds
Started Jul 28 05:36:40 PM PDT 24
Finished Jul 28 05:36:41 PM PDT 24
Peak memory 217532 kb
Host smart-d5fecfea-b675-4e0b-949e-05c84151eacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078260959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1078260959
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_disable.60794534
Short name T33
Test name
Test status
Simulation time 10095748 ps
CPU time 0.89 seconds
Started Jul 28 05:37:12 PM PDT 24
Finished Jul 28 05:37:13 PM PDT 24
Peak memory 215860 kb
Host smart-28e8f1de-5fc0-45bb-814b-820d170a33e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60794534 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.60794534
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.3753671182
Short name T123
Test name
Test status
Simulation time 81843259 ps
CPU time 0.84 seconds
Started Jul 28 05:37:01 PM PDT 24
Finished Jul 28 05:37:02 PM PDT 24
Peak memory 215216 kb
Host smart-3e8c4312-a29f-43cd-aec8-429cf7d47542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753671182 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3753671182
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/164.edn_alert.3044296688
Short name T16
Test name
Test status
Simulation time 25018244 ps
CPU time 1.19 seconds
Started Jul 28 05:38:51 PM PDT 24
Finished Jul 28 05:38:52 PM PDT 24
Peak memory 218508 kb
Host smart-1f257790-ab58-4ff8-a945-d958cd5691af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044296688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3044296688
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1544835939
Short name T243
Test name
Test status
Simulation time 106486220651 ps
CPU time 437.83 seconds
Started Jul 28 05:37:25 PM PDT 24
Finished Jul 28 05:44:43 PM PDT 24
Peak memory 220816 kb
Host smart-c25e3008-fa28-4da5-82e8-357c5868bdb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544835939 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1544835939
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/123.edn_alert.423193941
Short name T21
Test name
Test status
Simulation time 366931520 ps
CPU time 1.2 seconds
Started Jul 28 05:38:31 PM PDT 24
Finished Jul 28 05:38:32 PM PDT 24
Peak memory 219404 kb
Host smart-07b892ca-1b29-4601-879e-7944ed00190c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423193941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.423193941
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2260432311
Short name T116
Test name
Test status
Simulation time 20246584 ps
CPU time 1.1 seconds
Started Jul 28 05:36:40 PM PDT 24
Finished Jul 28 05:36:41 PM PDT 24
Peak memory 216748 kb
Host smart-75830d26-0c73-495b-9b1b-1a5afbf087b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260432311 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2260432311
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_regwen.4268457826
Short name T95
Test name
Test status
Simulation time 67571918 ps
CPU time 0.91 seconds
Started Jul 28 05:36:42 PM PDT 24
Finished Jul 28 05:36:43 PM PDT 24
Peak memory 206912 kb
Host smart-a92755d9-bf91-4ba0-bd09-6d9f7560dbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268457826 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.4268457826
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/15.edn_intr.2862237368
Short name T13
Test name
Test status
Simulation time 21455923 ps
CPU time 1.16 seconds
Started Jul 28 05:37:03 PM PDT 24
Finished Jul 28 05:37:04 PM PDT 24
Peak memory 223900 kb
Host smart-f16bfe8b-8513-49c4-847b-b4543567d437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862237368 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2862237368
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/40.edn_intr.2476182832
Short name T103
Test name
Test status
Simulation time 26897177 ps
CPU time 1.01 seconds
Started Jul 28 05:37:41 PM PDT 24
Finished Jul 28 05:37:42 PM PDT 24
Peak memory 215796 kb
Host smart-35a5cf47-7210-4972-896d-9a523af6b221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476182832 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2476182832
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/157.edn_genbits.1698009462
Short name T22
Test name
Test status
Simulation time 39158170 ps
CPU time 1.04 seconds
Started Jul 28 05:38:46 PM PDT 24
Finished Jul 28 05:38:48 PM PDT 24
Peak memory 218828 kb
Host smart-c4d4e758-f863-4c0d-b815-e25198f9eb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698009462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1698009462
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1497434958
Short name T306
Test name
Test status
Simulation time 539122869 ps
CPU time 2.63 seconds
Started Jul 28 05:31:51 PM PDT 24
Finished Jul 28 05:31:53 PM PDT 24
Peak memory 206640 kb
Host smart-da0cbd8e-8abe-4d93-8ea1-45ec032c7f7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497434958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1497434958
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/default/11.edn_alert.1834674202
Short name T298
Test name
Test status
Simulation time 115407806 ps
CPU time 1.37 seconds
Started Jul 28 05:36:50 PM PDT 24
Finished Jul 28 05:36:51 PM PDT 24
Peak memory 215468 kb
Host smart-b58733e8-0e68-495c-82a4-ece38fa17dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834674202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1834674202
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/226.edn_genbits.4182140314
Short name T347
Test name
Test status
Simulation time 162618679 ps
CPU time 1.38 seconds
Started Jul 28 05:39:21 PM PDT 24
Finished Jul 28 05:39:23 PM PDT 24
Peak memory 219420 kb
Host smart-0f086c83-f0c6-4c1d-b1a8-93e38ba455c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182140314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.4182140314
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3812365752
Short name T188
Test name
Test status
Simulation time 104244229 ps
CPU time 1.18 seconds
Started Jul 28 05:36:46 PM PDT 24
Finished Jul 28 05:36:47 PM PDT 24
Peak memory 218464 kb
Host smart-b8e62ed5-1f36-4579-a834-a5306af0081e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812365752 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3812365752
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/82.edn_alert.4165837164
Short name T201
Test name
Test status
Simulation time 65409419 ps
CPU time 1.13 seconds
Started Jul 28 05:38:17 PM PDT 24
Finished Jul 28 05:38:19 PM PDT 24
Peak memory 218440 kb
Host smart-72c0dc6a-973f-4715-94a1-58f159551677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165837164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.4165837164
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/29.edn_disable.1458930365
Short name T113
Test name
Test status
Simulation time 105915807 ps
CPU time 0.82 seconds
Started Jul 28 05:37:19 PM PDT 24
Finished Jul 28 05:37:20 PM PDT 24
Peak memory 216184 kb
Host smart-5e50b508-2f81-4fac-bbfa-499c4a8f9506
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458930365 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1458930365
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable.3869982632
Short name T115
Test name
Test status
Simulation time 31678131 ps
CPU time 0.88 seconds
Started Jul 28 05:37:16 PM PDT 24
Finished Jul 28 05:37:17 PM PDT 24
Peak memory 216060 kb
Host smart-b1aa41f2-cf60-4ee1-ad94-b81a7958d7ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869982632 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3869982632
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable.3369796228
Short name T125
Test name
Test status
Simulation time 14098870 ps
CPU time 0.92 seconds
Started Jul 28 05:36:55 PM PDT 24
Finished Jul 28 05:36:56 PM PDT 24
Peak memory 216184 kb
Host smart-2d690afa-5a45-44ad-aa74-37f5e637baec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369796228 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3369796228
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3774433466
Short name T129
Test name
Test status
Simulation time 42336724 ps
CPU time 1.21 seconds
Started Jul 28 05:37:19 PM PDT 24
Finished Jul 28 05:37:20 PM PDT 24
Peak memory 216820 kb
Host smart-be492745-1827-446f-bccb-81528af48a69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774433466 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3774433466
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3955794910
Short name T281
Test name
Test status
Simulation time 78294323 ps
CPU time 1.15 seconds
Started Jul 28 05:31:36 PM PDT 24
Finished Jul 28 05:31:37 PM PDT 24
Peak memory 206456 kb
Host smart-b5e1c2c8-d8c7-46e8-a821-f1d636424a7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955794910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3955794910
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/default/18.edn_intr.444742538
Short name T110
Test name
Test status
Simulation time 22243594 ps
CPU time 0.97 seconds
Started Jul 28 05:37:12 PM PDT 24
Finished Jul 28 05:37:13 PM PDT 24
Peak memory 215644 kb
Host smart-12d82ba7-fc0a-455b-87ff-aea23773ac54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444742538 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.444742538
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/175.edn_alert.1736686207
Short name T310
Test name
Test status
Simulation time 297091553 ps
CPU time 1.32 seconds
Started Jul 28 05:38:59 PM PDT 24
Finished Jul 28 05:39:01 PM PDT 24
Peak memory 220640 kb
Host smart-02b8db62-f4fa-49f5-812e-4725d64891bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736686207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1736686207
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2029980531
Short name T157
Test name
Test status
Simulation time 1901547089644 ps
CPU time 2747.87 seconds
Started Jul 28 05:37:25 PM PDT 24
Finished Jul 28 06:23:13 PM PDT 24
Peak memory 228188 kb
Host smart-353fc8e0-194c-4c92-a366-5e8bd613da81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029980531 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2029980531
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.edn_alert.1094219235
Short name T258
Test name
Test status
Simulation time 58062438 ps
CPU time 1.21 seconds
Started Jul 28 05:38:27 PM PDT 24
Finished Jul 28 05:38:29 PM PDT 24
Peak memory 219444 kb
Host smart-55ad3d00-d230-44eb-9dca-122052294be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094219235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1094219235
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/131.edn_alert.3944997690
Short name T212
Test name
Test status
Simulation time 94483593 ps
CPU time 1.21 seconds
Started Jul 28 05:38:33 PM PDT 24
Finished Jul 28 05:38:34 PM PDT 24
Peak memory 215552 kb
Host smart-4d027de3-a02a-4d3f-a135-c442187b2f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944997690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3944997690
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/193.edn_alert.2597302985
Short name T55
Test name
Test status
Simulation time 22758958 ps
CPU time 1.16 seconds
Started Jul 28 05:39:15 PM PDT 24
Finished Jul 28 05:39:16 PM PDT 24
Peak memory 220668 kb
Host smart-dccc59d4-6506-49e2-89a9-edadb46900d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597302985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2597302985
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert.1666021561
Short name T698
Test name
Test status
Simulation time 23068444 ps
CPU time 1.22 seconds
Started Jul 28 05:37:23 PM PDT 24
Finished Jul 28 05:37:25 PM PDT 24
Peak memory 219668 kb
Host smart-e5f3b5f6-444c-4e83-9f9f-468f61a014d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666021561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1666021561
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert.1720481299
Short name T73
Test name
Test status
Simulation time 32843144 ps
CPU time 1.38 seconds
Started Jul 28 05:36:36 PM PDT 24
Finished Jul 28 05:36:37 PM PDT 24
Peak memory 215552 kb
Host smart-ed0e04a0-a4a7-4f23-86b5-e28e12b15679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720481299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1720481299
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/11.edn_err.2494618605
Short name T49
Test name
Test status
Simulation time 20280400 ps
CPU time 1.23 seconds
Started Jul 28 05:36:50 PM PDT 24
Finished Jul 28 05:36:51 PM PDT 24
Peak memory 223952 kb
Host smart-19079a8c-543a-4c09-aea6-ede7346d3bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494618605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2494618605
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/119.edn_alert.1827947496
Short name T221
Test name
Test status
Simulation time 27388507 ps
CPU time 1.28 seconds
Started Jul 28 05:38:34 PM PDT 24
Finished Jul 28 05:38:35 PM PDT 24
Peak memory 219580 kb
Host smart-ef14c07f-659a-4f79-9a60-799d35b24560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827947496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1827947496
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert.1107529940
Short name T185
Test name
Test status
Simulation time 45308130 ps
CPU time 1.24 seconds
Started Jul 28 05:37:05 PM PDT 24
Finished Jul 28 05:37:07 PM PDT 24
Peak memory 220464 kb
Host smart-86e51b4c-7e33-483b-9544-1451edf136cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107529940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1107529940
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert.1700460703
Short name T299
Test name
Test status
Simulation time 28329047 ps
CPU time 1.23 seconds
Started Jul 28 05:37:04 PM PDT 24
Finished Jul 28 05:37:05 PM PDT 24
Peak memory 218188 kb
Host smart-a9b4f364-a71b-4d37-8218-d70cf835ff8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700460703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1700460703
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/126.edn_alert.3824749355
Short name T78
Test name
Test status
Simulation time 37914343 ps
CPU time 1.08 seconds
Started Jul 28 05:38:35 PM PDT 24
Finished Jul 28 05:38:36 PM PDT 24
Peak memory 219816 kb
Host smart-c4a74eb0-676b-460e-9345-d5cece660070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824749355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3824749355
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable.418165885
Short name T207
Test name
Test status
Simulation time 40207394 ps
CPU time 0.87 seconds
Started Jul 28 05:37:03 PM PDT 24
Finished Jul 28 05:37:04 PM PDT 24
Peak memory 215252 kb
Host smart-3631e4b9-1c92-4eb3-a1b1-1cfc8f4f754f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418165885 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.418165885
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.625775511
Short name T60
Test name
Test status
Simulation time 107853321 ps
CPU time 1.26 seconds
Started Jul 28 05:37:45 PM PDT 24
Finished Jul 28 05:37:47 PM PDT 24
Peak memory 216688 kb
Host smart-c60dd380-6f7f-4d18-b5d4-ca0f41992721
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625775511 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.625775511
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_disable.579004936
Short name T132
Test name
Test status
Simulation time 14390850 ps
CPU time 0.9 seconds
Started Jul 28 05:37:55 PM PDT 24
Finished Jul 28 05:37:56 PM PDT 24
Peak memory 216404 kb
Host smart-c8a3b4ce-c2a9-4495-ac51-2eb7f614f3e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579004936 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.579004936
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.1595863544
Short name T230
Test name
Test status
Simulation time 21437144 ps
CPU time 1.11 seconds
Started Jul 28 05:36:33 PM PDT 24
Finished Jul 28 05:36:35 PM PDT 24
Peak memory 219564 kb
Host smart-96b30766-8970-4e15-a527-e591a6fa8cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595863544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1595863544
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.427130385
Short name T448
Test name
Test status
Simulation time 50315709 ps
CPU time 1.44 seconds
Started Jul 28 05:36:51 PM PDT 24
Finished Jul 28 05:36:53 PM PDT 24
Peak memory 216764 kb
Host smart-977c3097-88dc-48f0-b08a-8cf2d4565c38
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427130385 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.427130385
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/108.edn_alert.2041441290
Short name T612
Test name
Test status
Simulation time 70569933 ps
CPU time 1.23 seconds
Started Jul 28 05:38:24 PM PDT 24
Finished Jul 28 05:38:25 PM PDT 24
Peak memory 218532 kb
Host smart-33a79dd0-7eb4-4591-ae33-4d5bd5063edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041441290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2041441290
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2205172181
Short name T177
Test name
Test status
Simulation time 49701215 ps
CPU time 1.15 seconds
Started Jul 28 05:36:52 PM PDT 24
Finished Jul 28 05:36:53 PM PDT 24
Peak memory 216872 kb
Host smart-e4304b8e-24be-4612-a6dd-3488086671d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205172181 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2205172181
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/110.edn_alert.3629993537
Short name T831
Test name
Test status
Simulation time 38885268 ps
CPU time 1.32 seconds
Started Jul 28 05:38:37 PM PDT 24
Finished Jul 28 05:38:39 PM PDT 24
Peak memory 215556 kb
Host smart-6595efc3-75a7-4198-bda2-eca4c721554b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629993537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.3629993537
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.3593945271
Short name T143
Test name
Test status
Simulation time 14329388 ps
CPU time 0.96 seconds
Started Jul 28 05:36:54 PM PDT 24
Finished Jul 28 05:36:55 PM PDT 24
Peak memory 216264 kb
Host smart-22b9e86c-354b-4651-accb-232448a97a49
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593945271 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3593945271
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable.4130033508
Short name T112
Test name
Test status
Simulation time 12923511 ps
CPU time 0.95 seconds
Started Jul 28 05:37:17 PM PDT 24
Finished Jul 28 05:37:18 PM PDT 24
Peak memory 216280 kb
Host smart-5899d4e0-f52d-43a6-a29c-2e227a72b344
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130033508 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4130033508
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable.1772217058
Short name T114
Test name
Test status
Simulation time 31650994 ps
CPU time 0.9 seconds
Started Jul 28 05:37:20 PM PDT 24
Finished Jul 28 05:37:21 PM PDT 24
Peak memory 216108 kb
Host smart-ea1ff14d-f439-4588-a415-c61bf73efebb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772217058 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1772217058
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/74.edn_err.1807023870
Short name T219
Test name
Test status
Simulation time 24014750 ps
CPU time 1.19 seconds
Started Jul 28 05:38:07 PM PDT 24
Finished Jul 28 05:38:09 PM PDT 24
Peak memory 223908 kb
Host smart-d8bfa100-bcb8-4541-9d76-9c93dc4abf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807023870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1807023870
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/10.edn_alert_test.223312596
Short name T359
Test name
Test status
Simulation time 16229380 ps
CPU time 0.97 seconds
Started Jul 28 05:36:51 PM PDT 24
Finished Jul 28 05:36:52 PM PDT 24
Peak memory 206644 kb
Host smart-050f10d1-e043-4549-8bb1-864aa7edef6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223312596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.223312596
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/143.edn_genbits.342762187
Short name T26
Test name
Test status
Simulation time 111767040 ps
CPU time 1.67 seconds
Started Jul 28 05:38:37 PM PDT 24
Finished Jul 28 05:38:39 PM PDT 24
Peak memory 218556 kb
Host smart-f07f3f61-42bf-433e-ad28-3ddf504edee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342762187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.342762187
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2682830168
Short name T160
Test name
Test status
Simulation time 104081024 ps
CPU time 1.38 seconds
Started Jul 28 05:38:17 PM PDT 24
Finished Jul 28 05:38:19 PM PDT 24
Peak memory 218768 kb
Host smart-70e75ed5-2b33-4191-8662-f66f8255aaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682830168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2682830168
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_genbits.1899051580
Short name T27
Test name
Test status
Simulation time 105946360 ps
CPU time 1.52 seconds
Started Jul 28 05:38:20 PM PDT 24
Finished Jul 28 05:38:22 PM PDT 24
Peak memory 218404 kb
Host smart-85824e4d-e983-416f-bb21-aab1a8fdab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899051580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1899051580
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_stress_all.3029876037
Short name T331
Test name
Test status
Simulation time 558307471 ps
CPU time 6.27 seconds
Started Jul 28 05:36:49 PM PDT 24
Finished Jul 28 05:36:56 PM PDT 24
Peak memory 217040 kb
Host smart-2b2ab6f5-bdcb-40ad-946b-80e3f3dd220f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029876037 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3029876037
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_intr.3830531763
Short name T106
Test name
Test status
Simulation time 22528024 ps
CPU time 1.11 seconds
Started Jul 28 05:37:03 PM PDT 24
Finished Jul 28 05:37:04 PM PDT 24
Peak memory 215796 kb
Host smart-6c714266-125a-48fb-9167-a3b6ade1628c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830531763 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3830531763
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2601813182
Short name T235
Test name
Test status
Simulation time 70148550 ps
CPU time 1.07 seconds
Started Jul 28 05:37:54 PM PDT 24
Finished Jul 28 05:37:55 PM PDT 24
Peak memory 219364 kb
Host smart-cd2d2944-7473-4c6b-a2ec-f95960167a99
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601813182 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2601813182
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/70.edn_genbits.821973118
Short name T335
Test name
Test status
Simulation time 93084165 ps
CPU time 1.48 seconds
Started Jul 28 05:38:09 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 219980 kb
Host smart-00db8424-e1ac-4304-98e3-10e17ddc08c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821973118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.821973118
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2925404163
Short name T290
Test name
Test status
Simulation time 13823705 ps
CPU time 0.97 seconds
Started Jul 28 05:31:31 PM PDT 24
Finished Jul 28 05:31:33 PM PDT 24
Peak memory 206568 kb
Host smart-1aa8d410-d59a-4a99-8c03-f6b7f3906ee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925404163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2925404163
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.edn_intr.3316050097
Short name T374
Test name
Test status
Simulation time 32175927 ps
CPU time 0.9 seconds
Started Jul 28 05:36:33 PM PDT 24
Finished Jul 28 05:36:34 PM PDT 24
Peak memory 215212 kb
Host smart-7bebc4fd-04ae-4f55-9faa-901c3dc363f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316050097 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3316050097
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2278187151
Short name T304
Test name
Test status
Simulation time 88127567 ps
CPU time 2.55 seconds
Started Jul 28 05:31:29 PM PDT 24
Finished Jul 28 05:31:32 PM PDT 24
Peak memory 206596 kb
Host smart-e0f53d80-5f32-482c-bda8-df4d60f040f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278187151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2278187151
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1514465574
Short name T340
Test name
Test status
Simulation time 92530700 ps
CPU time 1.02 seconds
Started Jul 28 05:36:29 PM PDT 24
Finished Jul 28 05:36:30 PM PDT 24
Peak memory 217264 kb
Host smart-f0d91c96-b9bb-48c3-8f05-2eb166294d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514465574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1514465574
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2385170661
Short name T349
Test name
Test status
Simulation time 107275831 ps
CPU time 1.15 seconds
Started Jul 28 05:38:22 PM PDT 24
Finished Jul 28 05:38:24 PM PDT 24
Peak memory 218412 kb
Host smart-6691715e-b203-4ff0-8e27-d6083f2fa577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385170661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2385170661
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.357368687
Short name T795
Test name
Test status
Simulation time 28250607 ps
CPU time 1.27 seconds
Started Jul 28 05:38:44 PM PDT 24
Finished Jul 28 05:38:46 PM PDT 24
Peak memory 217236 kb
Host smart-676bf580-65b1-4e0b-b7d3-8aabe160c662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357368687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.357368687
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_genbits.992783386
Short name T338
Test name
Test status
Simulation time 169421087 ps
CPU time 1.31 seconds
Started Jul 28 05:37:04 PM PDT 24
Finished Jul 28 05:37:05 PM PDT 24
Peak memory 217272 kb
Host smart-c0cac308-f3d4-4748-9601-1d49dfa1234f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992783386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.992783386
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2261868995
Short name T343
Test name
Test status
Simulation time 70797424 ps
CPU time 1.35 seconds
Started Jul 28 05:39:00 PM PDT 24
Finished Jul 28 05:39:01 PM PDT 24
Peak memory 220068 kb
Host smart-43fde3bb-f7a9-4216-9191-8768cf831d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261868995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2261868995
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2532128661
Short name T322
Test name
Test status
Simulation time 51121368 ps
CPU time 1.77 seconds
Started Jul 28 05:39:03 PM PDT 24
Finished Jul 28 05:39:05 PM PDT 24
Peak memory 217240 kb
Host smart-0d7e9e95-3f3b-4677-a5a2-d28cc46e6072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532128661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2532128661
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1651272325
Short name T342
Test name
Test status
Simulation time 96540240 ps
CPU time 1.21 seconds
Started Jul 28 05:39:35 PM PDT 24
Finished Jul 28 05:39:36 PM PDT 24
Peak memory 218636 kb
Host smart-255b3983-b2de-4a57-adbe-54668f1af7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651272325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1651272325
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_genbits.239498999
Short name T346
Test name
Test status
Simulation time 232193001 ps
CPU time 1.93 seconds
Started Jul 28 05:38:17 PM PDT 24
Finished Jul 28 05:38:19 PM PDT 24
Peak memory 218808 kb
Host smart-38cea0f7-351c-4770-b350-f85e736cfd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239498999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.239498999
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_genbits.317212832
Short name T329
Test name
Test status
Simulation time 76259814 ps
CPU time 1.82 seconds
Started Jul 28 05:38:18 PM PDT 24
Finished Jul 28 05:38:20 PM PDT 24
Peak memory 220060 kb
Host smart-346d16d4-97d5-4950-b54f-393e28ac0439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317212832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.317212832
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3280944283
Short name T100
Test name
Test status
Simulation time 28638558 ps
CPU time 0.85 seconds
Started Jul 28 05:36:35 PM PDT 24
Finished Jul 28 05:36:36 PM PDT 24
Peak memory 215732 kb
Host smart-0641b3fc-921e-467b-bb0c-ff13a4d151f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280944283 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3280944283
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/103.edn_alert.4133896777
Short name T168
Test name
Test status
Simulation time 92511253 ps
CPU time 1.28 seconds
Started Jul 28 05:38:24 PM PDT 24
Finished Jul 28 05:38:25 PM PDT 24
Peak memory 215548 kb
Host smart-529166c0-fdcc-4b57-ab51-9a6fa07c3451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133896777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.4133896777
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2222155335
Short name T1103
Test name
Test status
Simulation time 137548298 ps
CPU time 1.62 seconds
Started Jul 28 05:31:30 PM PDT 24
Finished Jul 28 05:31:32 PM PDT 24
Peak memory 206500 kb
Host smart-84bc811a-e1a8-408c-b44e-d886c16481fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222155335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2222155335
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3211495032
Short name T1070
Test name
Test status
Simulation time 416893239 ps
CPU time 3.66 seconds
Started Jul 28 05:31:30 PM PDT 24
Finished Jul 28 05:31:34 PM PDT 24
Peak memory 206436 kb
Host smart-d3bd5246-4254-4327-b4cc-789e10711ce8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211495032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3211495032
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3059705069
Short name T1009
Test name
Test status
Simulation time 17338781 ps
CPU time 0.96 seconds
Started Jul 28 05:31:29 PM PDT 24
Finished Jul 28 05:31:30 PM PDT 24
Peak memory 206452 kb
Host smart-9a6c146f-a00c-4061-9e61-d6fd87c41725
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059705069 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3059705069
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.538566015
Short name T1030
Test name
Test status
Simulation time 30281254 ps
CPU time 1.34 seconds
Started Jul 28 05:31:31 PM PDT 24
Finished Jul 28 05:31:32 PM PDT 24
Peak memory 217556 kb
Host smart-a64c7ab9-d5b9-480a-9d33-8ecd196087ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538566015 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.538566015
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2413904528
Short name T1060
Test name
Test status
Simulation time 46569931 ps
CPU time 0.92 seconds
Started Jul 28 05:31:28 PM PDT 24
Finished Jul 28 05:31:29 PM PDT 24
Peak memory 206460 kb
Host smart-cb6962a9-f4fb-4240-9a62-c9eafaa88b01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413904528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2413904528
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.166068732
Short name T1005
Test name
Test status
Simulation time 40900220 ps
CPU time 0.8 seconds
Started Jul 28 05:31:30 PM PDT 24
Finished Jul 28 05:31:31 PM PDT 24
Peak memory 206312 kb
Host smart-0e0854d3-3081-4cf8-a739-84f10d057d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166068732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.166068732
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3599191936
Short name T1051
Test name
Test status
Simulation time 118368131 ps
CPU time 2.68 seconds
Started Jul 28 05:31:30 PM PDT 24
Finished Jul 28 05:31:32 PM PDT 24
Peak memory 214864 kb
Host smart-142313de-b0cd-4d39-9a1b-b0e49c0efb8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599191936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3599191936
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4199729099
Short name T1083
Test name
Test status
Simulation time 769448326 ps
CPU time 2.56 seconds
Started Jul 28 05:31:29 PM PDT 24
Finished Jul 28 05:31:31 PM PDT 24
Peak memory 206576 kb
Host smart-c30a2990-8243-4b84-90b8-9060439708bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199729099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4199729099
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2133525070
Short name T1017
Test name
Test status
Simulation time 159850271 ps
CPU time 3.67 seconds
Started Jul 28 05:31:35 PM PDT 24
Finished Jul 28 05:31:38 PM PDT 24
Peak memory 206432 kb
Host smart-02bb5d9e-b5d7-416b-8613-8255feabd1ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133525070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2133525070
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.143293733
Short name T284
Test name
Test status
Simulation time 28425534 ps
CPU time 0.99 seconds
Started Jul 28 05:31:32 PM PDT 24
Finished Jul 28 05:31:33 PM PDT 24
Peak memory 206400 kb
Host smart-be4f0841-2f0e-44f8-8b6f-362666dd75a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143293733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.143293733
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4268727270
Short name T1014
Test name
Test status
Simulation time 14684831 ps
CPU time 1 seconds
Started Jul 28 05:31:36 PM PDT 24
Finished Jul 28 05:31:37 PM PDT 24
Peak memory 206652 kb
Host smart-ac7cda67-1740-4477-88a4-945d698dfb28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268727270 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.4268727270
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3530449355
Short name T1125
Test name
Test status
Simulation time 73526885 ps
CPU time 0.88 seconds
Started Jul 28 05:31:32 PM PDT 24
Finished Jul 28 05:31:33 PM PDT 24
Peak memory 206364 kb
Host smart-b69ca75d-13a4-4406-9fb9-5d988585cd01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530449355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3530449355
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.659616455
Short name T1025
Test name
Test status
Simulation time 51221566 ps
CPU time 0.78 seconds
Started Jul 28 05:31:31 PM PDT 24
Finished Jul 28 05:31:32 PM PDT 24
Peak memory 206248 kb
Host smart-06af9f9c-7d40-4f83-a2a9-e138e9765d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659616455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.659616455
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1188883705
Short name T291
Test name
Test status
Simulation time 93107360 ps
CPU time 1.23 seconds
Started Jul 28 05:31:34 PM PDT 24
Finished Jul 28 05:31:36 PM PDT 24
Peak memory 206656 kb
Host smart-a4b261cd-d066-4f13-9c7e-bdc12e0bd65c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188883705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1188883705
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.4063043665
Short name T1046
Test name
Test status
Simulation time 555336659 ps
CPU time 2.72 seconds
Started Jul 28 05:31:31 PM PDT 24
Finished Jul 28 05:31:34 PM PDT 24
Peak memory 214788 kb
Host smart-71d70e3c-90bd-42ca-88f3-5e725697a48b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063043665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.4063043665
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3518535908
Short name T1019
Test name
Test status
Simulation time 21931083 ps
CPU time 1.21 seconds
Started Jul 28 05:31:51 PM PDT 24
Finished Jul 28 05:31:52 PM PDT 24
Peak memory 214968 kb
Host smart-612eace6-d300-49ff-9487-516dfcc44b1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518535908 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3518535908
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3345611137
Short name T1003
Test name
Test status
Simulation time 16268238 ps
CPU time 0.99 seconds
Started Jul 28 05:31:51 PM PDT 24
Finished Jul 28 05:31:52 PM PDT 24
Peak memory 206448 kb
Host smart-14d8ee71-a2c5-4682-9254-db8951448477
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345611137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3345611137
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3298723330
Short name T1104
Test name
Test status
Simulation time 36013302 ps
CPU time 0.82 seconds
Started Jul 28 05:31:54 PM PDT 24
Finished Jul 28 05:31:55 PM PDT 24
Peak memory 206280 kb
Host smart-12469b69-23af-4391-8999-db43908f80c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298723330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3298723330
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.410633449
Short name T271
Test name
Test status
Simulation time 167061754 ps
CPU time 1.07 seconds
Started Jul 28 05:31:52 PM PDT 24
Finished Jul 28 05:31:53 PM PDT 24
Peak memory 206556 kb
Host smart-89d390ee-ab50-4bbd-a106-a071270771ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410633449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.410633449
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3877679710
Short name T1095
Test name
Test status
Simulation time 808568751 ps
CPU time 4.13 seconds
Started Jul 28 05:31:47 PM PDT 24
Finished Jul 28 05:31:51 PM PDT 24
Peak memory 214888 kb
Host smart-ac7f6eab-7384-4a0b-a193-f20a7a566b8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877679710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3877679710
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3214827884
Short name T1034
Test name
Test status
Simulation time 94980286 ps
CPU time 2.66 seconds
Started Jul 28 05:31:50 PM PDT 24
Finished Jul 28 05:31:53 PM PDT 24
Peak memory 206508 kb
Host smart-0b827494-6cd1-40df-918a-67f767faef89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214827884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3214827884
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1600100271
Short name T1111
Test name
Test status
Simulation time 61558180 ps
CPU time 1.2 seconds
Started Jul 28 05:32:01 PM PDT 24
Finished Jul 28 05:32:02 PM PDT 24
Peak memory 214844 kb
Host smart-fb33a4c5-269c-45f7-9971-e97a310c78c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600100271 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1600100271
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1458561980
Short name T1054
Test name
Test status
Simulation time 19111070 ps
CPU time 0.98 seconds
Started Jul 28 05:31:55 PM PDT 24
Finished Jul 28 05:31:56 PM PDT 24
Peak memory 206460 kb
Host smart-9043a232-b2f8-4dd6-be39-b2385981fa03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458561980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1458561980
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2204402977
Short name T1090
Test name
Test status
Simulation time 55548279 ps
CPU time 0.93 seconds
Started Jul 28 05:31:55 PM PDT 24
Finished Jul 28 05:31:56 PM PDT 24
Peak memory 206436 kb
Host smart-69a3302c-a38a-4c88-9922-e26b28926581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204402977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2204402977
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.188736817
Short name T1049
Test name
Test status
Simulation time 16948401 ps
CPU time 1.04 seconds
Started Jul 28 05:31:51 PM PDT 24
Finished Jul 28 05:31:52 PM PDT 24
Peak memory 206576 kb
Host smart-8f96c161-a319-4912-8229-76265cf8bc72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188736817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.188736817
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2790523536
Short name T1101
Test name
Test status
Simulation time 228797811 ps
CPU time 2.33 seconds
Started Jul 28 05:31:52 PM PDT 24
Finished Jul 28 05:31:54 PM PDT 24
Peak memory 214852 kb
Host smart-2a215fda-2027-4e2d-af65-41913a662e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790523536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2790523536
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.16213864
Short name T1057
Test name
Test status
Simulation time 142489302 ps
CPU time 1.48 seconds
Started Jul 28 05:31:50 PM PDT 24
Finished Jul 28 05:31:52 PM PDT 24
Peak memory 206580 kb
Host smart-fbc50b56-9d72-49ac-b63a-04094743fd83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16213864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.16213864
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3787199743
Short name T1109
Test name
Test status
Simulation time 17425354 ps
CPU time 1.1 seconds
Started Jul 28 05:31:55 PM PDT 24
Finished Jul 28 05:31:56 PM PDT 24
Peak memory 216280 kb
Host smart-6bd7d6a7-1781-4132-b611-86c0cf466419
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787199743 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3787199743
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2128060409
Short name T1011
Test name
Test status
Simulation time 30082904 ps
CPU time 0.95 seconds
Started Jul 28 05:31:55 PM PDT 24
Finished Jul 28 05:31:56 PM PDT 24
Peak memory 206568 kb
Host smart-f65205e5-e264-4cae-9947-836ce042dac9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128060409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2128060409
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.198044469
Short name T1091
Test name
Test status
Simulation time 177776821 ps
CPU time 0.88 seconds
Started Jul 28 05:31:50 PM PDT 24
Finished Jul 28 05:31:51 PM PDT 24
Peak memory 206388 kb
Host smart-bd901de0-2594-4204-881d-b9c2c55b0bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198044469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.198044469
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1420520348
Short name T1039
Test name
Test status
Simulation time 50101966 ps
CPU time 1.13 seconds
Started Jul 28 05:31:48 PM PDT 24
Finished Jul 28 05:31:49 PM PDT 24
Peak memory 206588 kb
Host smart-8c6f5d75-1b50-4af3-b0db-907889515f41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420520348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1420520348
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1845714340
Short name T1081
Test name
Test status
Simulation time 363211400 ps
CPU time 5.23 seconds
Started Jul 28 05:31:51 PM PDT 24
Finished Jul 28 05:31:57 PM PDT 24
Peak memory 223020 kb
Host smart-0da3e515-785c-477f-aebf-5acb6fc832b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845714340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1845714340
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2311687321
Short name T1085
Test name
Test status
Simulation time 696382844 ps
CPU time 1.8 seconds
Started Jul 28 05:31:51 PM PDT 24
Finished Jul 28 05:31:53 PM PDT 24
Peak memory 206684 kb
Host smart-e3ddf0b3-33f3-45b7-b81d-b1a71851333f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311687321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2311687321
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2572506050
Short name T1086
Test name
Test status
Simulation time 25916960 ps
CPU time 1.55 seconds
Started Jul 28 05:31:56 PM PDT 24
Finished Jul 28 05:31:58 PM PDT 24
Peak memory 214924 kb
Host smart-7cdcd6ca-fd59-4c5c-abfa-43d4b0f906ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572506050 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2572506050
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1999050246
Short name T1056
Test name
Test status
Simulation time 63093745 ps
CPU time 0.93 seconds
Started Jul 28 05:31:52 PM PDT 24
Finished Jul 28 05:31:53 PM PDT 24
Peak memory 206428 kb
Host smart-fdc9309f-4c2d-426b-bb4c-d68ad35f2d1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999050246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1999050246
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1147311731
Short name T998
Test name
Test status
Simulation time 31464069 ps
CPU time 0.82 seconds
Started Jul 28 05:31:51 PM PDT 24
Finished Jul 28 05:31:52 PM PDT 24
Peak memory 206256 kb
Host smart-1659dbdd-280f-431f-a42c-edca940e80a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147311731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1147311731
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2825772064
Short name T1118
Test name
Test status
Simulation time 14175733 ps
CPU time 1.08 seconds
Started Jul 28 05:31:51 PM PDT 24
Finished Jul 28 05:31:52 PM PDT 24
Peak memory 206572 kb
Host smart-399debf0-6b34-4524-90bd-1d781e81c2bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825772064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2825772064
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1933396792
Short name T1119
Test name
Test status
Simulation time 189702306 ps
CPU time 4.19 seconds
Started Jul 28 05:31:59 PM PDT 24
Finished Jul 28 05:32:04 PM PDT 24
Peak memory 214824 kb
Host smart-2b968f26-746c-443a-8959-122430c7e79f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933396792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1933396792
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2490395661
Short name T987
Test name
Test status
Simulation time 28312433 ps
CPU time 1.86 seconds
Started Jul 28 05:31:54 PM PDT 24
Finished Jul 28 05:31:56 PM PDT 24
Peak memory 214832 kb
Host smart-da32bfe3-b4b5-457b-9aa8-6a2922518e76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490395661 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2490395661
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.704740716
Short name T1098
Test name
Test status
Simulation time 50543314 ps
CPU time 0.91 seconds
Started Jul 28 05:31:51 PM PDT 24
Finished Jul 28 05:31:52 PM PDT 24
Peak memory 206432 kb
Host smart-f3851436-4bd1-4789-b866-c9db6994c700
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704740716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.704740716
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.16640489
Short name T1072
Test name
Test status
Simulation time 42576385 ps
CPU time 0.87 seconds
Started Jul 28 05:31:56 PM PDT 24
Finished Jul 28 05:31:57 PM PDT 24
Peak memory 206432 kb
Host smart-efe9aaa6-3e83-4f0e-ac21-a773295cdf03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16640489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.16640489
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2193006368
Short name T295
Test name
Test status
Simulation time 22793974 ps
CPU time 1.11 seconds
Started Jul 28 05:31:53 PM PDT 24
Finished Jul 28 05:31:54 PM PDT 24
Peak memory 206532 kb
Host smart-62e18f04-33ab-4fdf-8178-8d45fd6a7183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193006368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2193006368
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3239180703
Short name T1048
Test name
Test status
Simulation time 166601769 ps
CPU time 3.47 seconds
Started Jul 28 05:31:50 PM PDT 24
Finished Jul 28 05:31:54 PM PDT 24
Peak memory 215120 kb
Host smart-086ada2e-679f-437d-be34-2aa5b2e4a8e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239180703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3239180703
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1214551144
Short name T1108
Test name
Test status
Simulation time 76648677 ps
CPU time 1.51 seconds
Started Jul 28 05:31:51 PM PDT 24
Finished Jul 28 05:31:53 PM PDT 24
Peak memory 206648 kb
Host smart-59d46231-7253-45a2-9f9a-9a3acf17fdcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214551144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1214551144
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2609321189
Short name T1096
Test name
Test status
Simulation time 53420957 ps
CPU time 1.42 seconds
Started Jul 28 05:31:53 PM PDT 24
Finished Jul 28 05:31:55 PM PDT 24
Peak memory 215024 kb
Host smart-8b99c6e9-0786-4d14-bffc-089590f505ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609321189 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2609321189
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3715740902
Short name T996
Test name
Test status
Simulation time 13878739 ps
CPU time 0.94 seconds
Started Jul 28 05:31:49 PM PDT 24
Finished Jul 28 05:31:50 PM PDT 24
Peak memory 206456 kb
Host smart-387a3800-3db7-475e-9cfc-095ae2e094ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715740902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3715740902
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2271220354
Short name T1012
Test name
Test status
Simulation time 13641943 ps
CPU time 0.89 seconds
Started Jul 28 05:31:51 PM PDT 24
Finished Jul 28 05:31:52 PM PDT 24
Peak memory 206516 kb
Host smart-a9b81ad1-e56c-4a6b-a2b1-12e44c650e9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271220354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2271220354
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1703998095
Short name T270
Test name
Test status
Simulation time 66532759 ps
CPU time 1.13 seconds
Started Jul 28 05:31:54 PM PDT 24
Finished Jul 28 05:31:55 PM PDT 24
Peak memory 206520 kb
Host smart-170b80b2-b014-40bc-b777-d71fb9031dda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703998095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1703998095
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1828990621
Short name T1071
Test name
Test status
Simulation time 266233682 ps
CPU time 4.72 seconds
Started Jul 28 05:31:59 PM PDT 24
Finished Jul 28 05:32:04 PM PDT 24
Peak memory 214884 kb
Host smart-9c078394-356d-4ac2-9f3f-4ff4f3624344
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828990621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1828990621
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3617215546
Short name T1047
Test name
Test status
Simulation time 923622133 ps
CPU time 15.09 seconds
Started Jul 28 05:31:52 PM PDT 24
Finished Jul 28 05:32:07 PM PDT 24
Peak memory 214788 kb
Host smart-48abd9cf-def1-4684-b582-cc50bb1e5fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617215546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3617215546
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.828235457
Short name T1044
Test name
Test status
Simulation time 30093061 ps
CPU time 1.53 seconds
Started Jul 28 05:31:51 PM PDT 24
Finished Jul 28 05:31:52 PM PDT 24
Peak memory 214872 kb
Host smart-49d6c811-ffa2-4164-b21a-dd60f8796f12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828235457 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.828235457
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1027190008
Short name T1069
Test name
Test status
Simulation time 14500660 ps
CPU time 0.94 seconds
Started Jul 28 05:31:51 PM PDT 24
Finished Jul 28 05:31:52 PM PDT 24
Peak memory 206388 kb
Host smart-ba82e423-504e-408c-a6b0-e69a68f13afa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027190008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1027190008
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.975990959
Short name T1002
Test name
Test status
Simulation time 16035874 ps
CPU time 0.93 seconds
Started Jul 28 05:31:51 PM PDT 24
Finished Jul 28 05:31:52 PM PDT 24
Peak memory 206452 kb
Host smart-0b1a11e7-21f8-442a-a72f-d429b86ed9f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975990959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.975990959
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1145037677
Short name T1073
Test name
Test status
Simulation time 175985535 ps
CPU time 1.25 seconds
Started Jul 28 05:31:50 PM PDT 24
Finished Jul 28 05:31:52 PM PDT 24
Peak memory 206644 kb
Host smart-3202866c-991f-42f8-940d-f4245280336f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145037677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1145037677
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1283320613
Short name T1031
Test name
Test status
Simulation time 35456779 ps
CPU time 2.54 seconds
Started Jul 28 05:31:50 PM PDT 24
Finished Jul 28 05:31:53 PM PDT 24
Peak memory 214896 kb
Host smart-98382a72-2b1b-4db5-bb84-fb9885fb07d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283320613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1283320613
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1137299826
Short name T1078
Test name
Test status
Simulation time 145022884 ps
CPU time 1.74 seconds
Started Jul 28 05:31:50 PM PDT 24
Finished Jul 28 05:31:52 PM PDT 24
Peak memory 206620 kb
Host smart-c51c6e5a-d891-4fd8-bb81-366b184cf62e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137299826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1137299826
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1424387235
Short name T1068
Test name
Test status
Simulation time 31479811 ps
CPU time 1.39 seconds
Started Jul 28 05:32:00 PM PDT 24
Finished Jul 28 05:32:01 PM PDT 24
Peak memory 214836 kb
Host smart-2fb8c41b-759d-45d6-8474-ffc19d366942
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424387235 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1424387235
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3057730357
Short name T1027
Test name
Test status
Simulation time 48604624 ps
CPU time 0.89 seconds
Started Jul 28 05:31:58 PM PDT 24
Finished Jul 28 05:31:59 PM PDT 24
Peak memory 206460 kb
Host smart-cbe62d8a-fc71-4903-ac6a-6c782319b4af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057730357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3057730357
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2170705365
Short name T1050
Test name
Test status
Simulation time 40673684 ps
CPU time 0.86 seconds
Started Jul 28 05:32:01 PM PDT 24
Finished Jul 28 05:32:01 PM PDT 24
Peak memory 206500 kb
Host smart-c8ea1f53-09fa-4aa7-af37-d7e238ce1e09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170705365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2170705365
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2519652730
Short name T1055
Test name
Test status
Simulation time 73025199 ps
CPU time 1.38 seconds
Started Jul 28 05:31:59 PM PDT 24
Finished Jul 28 05:32:01 PM PDT 24
Peak memory 206648 kb
Host smart-84a29198-e56f-40bb-b067-a70a20bba8c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519652730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2519652730
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.583233284
Short name T1084
Test name
Test status
Simulation time 69778113 ps
CPU time 2.48 seconds
Started Jul 28 05:31:53 PM PDT 24
Finished Jul 28 05:31:56 PM PDT 24
Peak memory 214848 kb
Host smart-f6bda6b0-e69e-49d8-81da-2d3c6de2779a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583233284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.583233284
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2975912995
Short name T994
Test name
Test status
Simulation time 54398520 ps
CPU time 1.61 seconds
Started Jul 28 05:32:05 PM PDT 24
Finished Jul 28 05:32:07 PM PDT 24
Peak memory 206640 kb
Host smart-06a099c2-01bc-4d58-9687-18dba8966fff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975912995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2975912995
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3061834453
Short name T1087
Test name
Test status
Simulation time 22954030 ps
CPU time 1.15 seconds
Started Jul 28 05:32:02 PM PDT 24
Finished Jul 28 05:32:03 PM PDT 24
Peak memory 214744 kb
Host smart-cc8f0efd-76d2-4c64-a177-a2a91f04f4d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061834453 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3061834453
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.354281035
Short name T1036
Test name
Test status
Simulation time 68812564 ps
CPU time 0.87 seconds
Started Jul 28 05:32:02 PM PDT 24
Finished Jul 28 05:32:03 PM PDT 24
Peak memory 206380 kb
Host smart-72a20a86-d05f-4258-8df2-a36222805c07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354281035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.354281035
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.521201091
Short name T1061
Test name
Test status
Simulation time 13206162 ps
CPU time 0.95 seconds
Started Jul 28 05:31:59 PM PDT 24
Finished Jul 28 05:32:00 PM PDT 24
Peak memory 206480 kb
Host smart-54abe041-fe2e-4280-9163-647921186c7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521201091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.521201091
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2746133055
Short name T1107
Test name
Test status
Simulation time 19723992 ps
CPU time 1.15 seconds
Started Jul 28 05:31:59 PM PDT 24
Finished Jul 28 05:32:00 PM PDT 24
Peak memory 206660 kb
Host smart-532a1286-0379-405c-9570-cda36d557486
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746133055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2746133055
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1690304767
Short name T1080
Test name
Test status
Simulation time 152726079 ps
CPU time 2.69 seconds
Started Jul 28 05:31:59 PM PDT 24
Finished Jul 28 05:32:02 PM PDT 24
Peak memory 214756 kb
Host smart-5e003277-f645-4d51-b905-0a4ac71c7aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690304767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1690304767
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2763908883
Short name T305
Test name
Test status
Simulation time 192579223 ps
CPU time 2.14 seconds
Started Jul 28 05:32:01 PM PDT 24
Finished Jul 28 05:32:03 PM PDT 24
Peak memory 206672 kb
Host smart-98c7dbf9-ab9e-414c-b8c7-16198c99d2f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763908883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2763908883
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2719466032
Short name T1015
Test name
Test status
Simulation time 49138520 ps
CPU time 1.93 seconds
Started Jul 28 05:31:57 PM PDT 24
Finished Jul 28 05:31:59 PM PDT 24
Peak memory 214868 kb
Host smart-cd8ad268-54a3-446e-98b6-ee79067f0432
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719466032 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2719466032
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2834943716
Short name T1035
Test name
Test status
Simulation time 18738447 ps
CPU time 0.89 seconds
Started Jul 28 05:32:03 PM PDT 24
Finished Jul 28 05:32:04 PM PDT 24
Peak memory 206452 kb
Host smart-f400fc9a-03a4-412f-b206-aa398df40772
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834943716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2834943716
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.175914125
Short name T1122
Test name
Test status
Simulation time 18037452 ps
CPU time 0.89 seconds
Started Jul 28 05:32:00 PM PDT 24
Finished Jul 28 05:32:01 PM PDT 24
Peak memory 206500 kb
Host smart-45f3b9ca-7ec8-4769-a606-54091bb7d701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175914125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.175914125
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3822355633
Short name T1067
Test name
Test status
Simulation time 15258898 ps
CPU time 1.01 seconds
Started Jul 28 05:32:01 PM PDT 24
Finished Jul 28 05:32:02 PM PDT 24
Peak memory 206600 kb
Host smart-929211cd-1edc-4f6e-a501-844701517a91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822355633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3822355633
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2193488315
Short name T1121
Test name
Test status
Simulation time 27470214 ps
CPU time 1.93 seconds
Started Jul 28 05:32:00 PM PDT 24
Finished Jul 28 05:32:02 PM PDT 24
Peak memory 214860 kb
Host smart-e1f91ae7-2049-4ed6-8957-6e381055b8f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193488315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2193488315
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1773831286
Short name T1045
Test name
Test status
Simulation time 397433182 ps
CPU time 2.75 seconds
Started Jul 28 05:32:05 PM PDT 24
Finished Jul 28 05:32:08 PM PDT 24
Peak memory 214908 kb
Host smart-033cd809-20bc-4a92-93bc-851b8c3511a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773831286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1773831286
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1202126823
Short name T289
Test name
Test status
Simulation time 44010946 ps
CPU time 1.7 seconds
Started Jul 28 05:31:37 PM PDT 24
Finished Jul 28 05:31:39 PM PDT 24
Peak memory 206480 kb
Host smart-7ce316e9-3775-4719-894c-d139491c3dff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202126823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1202126823
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1435144382
Short name T1058
Test name
Test status
Simulation time 436961610 ps
CPU time 6.2 seconds
Started Jul 28 05:31:37 PM PDT 24
Finished Jul 28 05:31:44 PM PDT 24
Peak memory 206468 kb
Host smart-5aac5436-75a0-4a9f-8b3c-bfede561686c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435144382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1435144382
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.618981109
Short name T1021
Test name
Test status
Simulation time 13244351 ps
CPU time 0.89 seconds
Started Jul 28 05:31:36 PM PDT 24
Finished Jul 28 05:31:37 PM PDT 24
Peak memory 206376 kb
Host smart-4c2f9f68-d57c-424d-9124-08d88ca5e175
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618981109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.618981109
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.613542921
Short name T1120
Test name
Test status
Simulation time 40816483 ps
CPU time 1.71 seconds
Started Jul 28 05:31:36 PM PDT 24
Finished Jul 28 05:31:38 PM PDT 24
Peak memory 214868 kb
Host smart-1491c77f-4b84-4638-9f56-1d16a6923d10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613542921 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.613542921
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.4258079111
Short name T285
Test name
Test status
Simulation time 19834548 ps
CPU time 0.86 seconds
Started Jul 28 05:31:38 PM PDT 24
Finished Jul 28 05:31:39 PM PDT 24
Peak memory 206280 kb
Host smart-a948ffb6-418f-4fcb-ad66-c59cde28ee0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258079111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.4258079111
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2618281154
Short name T1097
Test name
Test status
Simulation time 16522615 ps
CPU time 0.93 seconds
Started Jul 28 05:31:36 PM PDT 24
Finished Jul 28 05:31:37 PM PDT 24
Peak memory 206388 kb
Host smart-1b98514d-0d71-4e56-b1a7-4da946e2e426
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618281154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2618281154
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3745382957
Short name T1029
Test name
Test status
Simulation time 449041141 ps
CPU time 1.46 seconds
Started Jul 28 05:31:36 PM PDT 24
Finished Jul 28 05:31:38 PM PDT 24
Peak memory 206688 kb
Host smart-a621058d-b25e-423e-b715-7082fd502526
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745382957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3745382957
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.932035639
Short name T993
Test name
Test status
Simulation time 144298263 ps
CPU time 4.73 seconds
Started Jul 28 05:31:37 PM PDT 24
Finished Jul 28 05:31:42 PM PDT 24
Peak memory 214868 kb
Host smart-bee917b0-6587-4190-87a6-ed2138f082de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932035639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.932035639
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4092246096
Short name T1006
Test name
Test status
Simulation time 200903896 ps
CPU time 1.75 seconds
Started Jul 28 05:31:35 PM PDT 24
Finished Jul 28 05:31:37 PM PDT 24
Peak memory 206492 kb
Host smart-e2d03233-33c4-41b9-b208-60fbb3868674
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092246096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.4092246096
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3412328019
Short name T1094
Test name
Test status
Simulation time 15257711 ps
CPU time 0.99 seconds
Started Jul 28 05:32:03 PM PDT 24
Finished Jul 28 05:32:04 PM PDT 24
Peak memory 206508 kb
Host smart-ae0de5d9-87b7-4905-b07e-a6a085f25d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412328019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3412328019
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.915648304
Short name T1074
Test name
Test status
Simulation time 14211775 ps
CPU time 0.89 seconds
Started Jul 28 05:31:58 PM PDT 24
Finished Jul 28 05:31:59 PM PDT 24
Peak memory 206544 kb
Host smart-898a58a4-175b-4d8d-97d9-64105ce7e3d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915648304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.915648304
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.562073667
Short name T1001
Test name
Test status
Simulation time 34488469 ps
CPU time 0.82 seconds
Started Jul 28 05:32:01 PM PDT 24
Finished Jul 28 05:32:02 PM PDT 24
Peak memory 206204 kb
Host smart-af8edcdb-e5c5-4741-9519-f8a5bbee7525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562073667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.562073667
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1806761634
Short name T1082
Test name
Test status
Simulation time 57715505 ps
CPU time 0.82 seconds
Started Jul 28 05:32:01 PM PDT 24
Finished Jul 28 05:32:02 PM PDT 24
Peak memory 206260 kb
Host smart-cd667d2d-38f8-4823-bf23-6fbb34fe14f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806761634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1806761634
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3337100344
Short name T992
Test name
Test status
Simulation time 21236616 ps
CPU time 0.88 seconds
Started Jul 28 05:32:01 PM PDT 24
Finished Jul 28 05:32:02 PM PDT 24
Peak memory 206500 kb
Host smart-c26428f4-e6c8-4350-b0d9-d6b6d4a2d653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337100344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3337100344
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1844902201
Short name T1026
Test name
Test status
Simulation time 47392638 ps
CPU time 0.91 seconds
Started Jul 28 05:32:03 PM PDT 24
Finished Jul 28 05:32:04 PM PDT 24
Peak memory 206508 kb
Host smart-c49fc744-b359-45dd-8cbf-af38b29c0ad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844902201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1844902201
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2645902395
Short name T990
Test name
Test status
Simulation time 12135571 ps
CPU time 0.83 seconds
Started Jul 28 05:32:00 PM PDT 24
Finished Jul 28 05:32:01 PM PDT 24
Peak memory 206408 kb
Host smart-3baec4c5-e333-434d-afab-e6a2d8d5447e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645902395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2645902395
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3604725116
Short name T1106
Test name
Test status
Simulation time 50396257 ps
CPU time 0.85 seconds
Started Jul 28 05:32:00 PM PDT 24
Finished Jul 28 05:32:01 PM PDT 24
Peak memory 206460 kb
Host smart-c0ea99ab-fb75-47f2-89cc-02f7168b22c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604725116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3604725116
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2685887102
Short name T1063
Test name
Test status
Simulation time 61387643 ps
CPU time 0.87 seconds
Started Jul 28 05:32:02 PM PDT 24
Finished Jul 28 05:32:03 PM PDT 24
Peak memory 206388 kb
Host smart-1affb051-05d3-4b5c-b689-0c0b0a0efbfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685887102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2685887102
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2913658040
Short name T995
Test name
Test status
Simulation time 19779110 ps
CPU time 0.91 seconds
Started Jul 28 05:31:59 PM PDT 24
Finished Jul 28 05:32:00 PM PDT 24
Peak memory 206444 kb
Host smart-9f5f63df-11b7-487e-b34d-c083d511e689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913658040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2913658040
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.896542464
Short name T988
Test name
Test status
Simulation time 14343258 ps
CPU time 1.05 seconds
Started Jul 28 05:31:36 PM PDT 24
Finished Jul 28 05:31:37 PM PDT 24
Peak memory 206468 kb
Host smart-26f4adca-c185-4eb0-86cf-e15a2c653b7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896542464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.896542464
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1731131637
Short name T283
Test name
Test status
Simulation time 667250227 ps
CPU time 5.88 seconds
Started Jul 28 05:31:39 PM PDT 24
Finished Jul 28 05:31:45 PM PDT 24
Peak memory 206484 kb
Host smart-f0afa593-1abe-4b5e-bf05-614f673a8c2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731131637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1731131637
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1893466901
Short name T1124
Test name
Test status
Simulation time 27542064 ps
CPU time 0.92 seconds
Started Jul 28 05:31:36 PM PDT 24
Finished Jul 28 05:31:37 PM PDT 24
Peak memory 206464 kb
Host smart-3a619f48-5c51-4507-bed7-bad61e2be390
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893466901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1893466901
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4123933188
Short name T1007
Test name
Test status
Simulation time 23303019 ps
CPU time 1.52 seconds
Started Jul 28 05:31:36 PM PDT 24
Finished Jul 28 05:31:38 PM PDT 24
Peak memory 214916 kb
Host smart-d7e932b3-a6ef-47bd-a127-b1cfb5539cdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123933188 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.4123933188
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1310255221
Short name T286
Test name
Test status
Simulation time 16599580 ps
CPU time 0.93 seconds
Started Jul 28 05:31:40 PM PDT 24
Finished Jul 28 05:31:41 PM PDT 24
Peak memory 206444 kb
Host smart-d876ee1e-3dff-4373-96c9-ab674dd69ef1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310255221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1310255221
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1481310351
Short name T1079
Test name
Test status
Simulation time 50609792 ps
CPU time 0.83 seconds
Started Jul 28 05:31:36 PM PDT 24
Finished Jul 28 05:31:37 PM PDT 24
Peak memory 206468 kb
Host smart-8cc82b95-5873-4944-8906-a00804c46a6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481310351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1481310351
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1366238936
Short name T1059
Test name
Test status
Simulation time 32670558 ps
CPU time 1.43 seconds
Started Jul 28 05:31:39 PM PDT 24
Finished Jul 28 05:31:40 PM PDT 24
Peak memory 206664 kb
Host smart-6aa3c11b-4457-4e78-b385-b1d80eaf76fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366238936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1366238936
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2543541454
Short name T1062
Test name
Test status
Simulation time 81421032 ps
CPU time 1.78 seconds
Started Jul 28 05:31:35 PM PDT 24
Finished Jul 28 05:31:37 PM PDT 24
Peak memory 218648 kb
Host smart-606db3fb-b81d-4413-bea8-aaf64a52a474
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543541454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2543541454
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.870939633
Short name T240
Test name
Test status
Simulation time 166155784 ps
CPU time 3.84 seconds
Started Jul 28 05:31:36 PM PDT 24
Finished Jul 28 05:31:40 PM PDT 24
Peak memory 214824 kb
Host smart-969f9f81-57b6-49ee-a348-a1d1f1fce507
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870939633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.870939633
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.874711133
Short name T991
Test name
Test status
Simulation time 101498993 ps
CPU time 0.81 seconds
Started Jul 28 05:31:59 PM PDT 24
Finished Jul 28 05:32:00 PM PDT 24
Peak memory 206228 kb
Host smart-dbf74693-ff77-490d-ba85-05670cca5ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874711133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.874711133
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2045171757
Short name T1004
Test name
Test status
Simulation time 13421159 ps
CPU time 0.87 seconds
Started Jul 28 05:31:59 PM PDT 24
Finished Jul 28 05:32:00 PM PDT 24
Peak memory 206492 kb
Host smart-ae19a025-ff38-41b9-8e98-635a6b9b040f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045171757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2045171757
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2117309685
Short name T1112
Test name
Test status
Simulation time 22479440 ps
CPU time 0.95 seconds
Started Jul 28 05:31:57 PM PDT 24
Finished Jul 28 05:31:58 PM PDT 24
Peak memory 206464 kb
Host smart-22bdd118-76a0-455c-934a-4629985b7977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117309685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2117309685
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2009958415
Short name T989
Test name
Test status
Simulation time 15989196 ps
CPU time 0.97 seconds
Started Jul 28 05:31:59 PM PDT 24
Finished Jul 28 05:32:00 PM PDT 24
Peak memory 206476 kb
Host smart-d59c4dad-624c-4efd-90b6-3b6872564ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009958415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2009958415
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3471257898
Short name T1010
Test name
Test status
Simulation time 25943044 ps
CPU time 0.89 seconds
Started Jul 28 05:31:58 PM PDT 24
Finished Jul 28 05:31:59 PM PDT 24
Peak memory 206432 kb
Host smart-36610195-cdfe-446e-9f4f-24244d2f89a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471257898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3471257898
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1145757776
Short name T1088
Test name
Test status
Simulation time 15558490 ps
CPU time 0.93 seconds
Started Jul 28 05:32:00 PM PDT 24
Finished Jul 28 05:32:01 PM PDT 24
Peak memory 206444 kb
Host smart-250c5241-3aa8-42df-b194-4d9bf433632e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145757776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1145757776
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1212253904
Short name T1028
Test name
Test status
Simulation time 14360373 ps
CPU time 0.94 seconds
Started Jul 28 05:32:03 PM PDT 24
Finished Jul 28 05:32:04 PM PDT 24
Peak memory 206440 kb
Host smart-7527ef8c-ea6e-4ace-93c1-f69ec0953833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212253904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1212253904
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3239980734
Short name T1032
Test name
Test status
Simulation time 19656852 ps
CPU time 0.88 seconds
Started Jul 28 05:32:01 PM PDT 24
Finished Jul 28 05:32:02 PM PDT 24
Peak memory 206368 kb
Host smart-3a263a08-6ee6-4110-9e65-c5afd188711c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239980734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3239980734
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1213976582
Short name T1076
Test name
Test status
Simulation time 30903420 ps
CPU time 0.86 seconds
Started Jul 28 05:32:02 PM PDT 24
Finished Jul 28 05:32:03 PM PDT 24
Peak memory 206520 kb
Host smart-104abe1d-9d4c-4359-8fe3-5f5ab66c79ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213976582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1213976582
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2902870392
Short name T1023
Test name
Test status
Simulation time 20980764 ps
CPU time 0.85 seconds
Started Jul 28 05:31:59 PM PDT 24
Finished Jul 28 05:32:00 PM PDT 24
Peak memory 206304 kb
Host smart-de624551-5c93-4625-9ba0-66ef01a76897
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902870392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2902870392
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1896127141
Short name T1113
Test name
Test status
Simulation time 255191703 ps
CPU time 1.17 seconds
Started Jul 28 05:31:37 PM PDT 24
Finished Jul 28 05:31:39 PM PDT 24
Peak memory 206472 kb
Host smart-c6ba4350-bc5e-4062-8cbc-8f27135a76a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896127141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1896127141
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2487797121
Short name T1064
Test name
Test status
Simulation time 577057842 ps
CPU time 5.62 seconds
Started Jul 28 05:31:35 PM PDT 24
Finished Jul 28 05:31:41 PM PDT 24
Peak memory 206420 kb
Host smart-10e8ad30-c055-4e50-9022-2c6df22f3bfe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487797121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2487797121
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2163655554
Short name T1008
Test name
Test status
Simulation time 15249453 ps
CPU time 0.95 seconds
Started Jul 28 05:31:36 PM PDT 24
Finished Jul 28 05:31:37 PM PDT 24
Peak memory 206388 kb
Host smart-288b8a38-ca75-4243-98b3-2054945439c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163655554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2163655554
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2881467507
Short name T1016
Test name
Test status
Simulation time 117907921 ps
CPU time 1.44 seconds
Started Jul 28 05:31:42 PM PDT 24
Finished Jul 28 05:31:44 PM PDT 24
Peak memory 214828 kb
Host smart-9c441e83-eff6-4ce9-b30c-2f97d23ac8ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881467507 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2881467507
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2304100584
Short name T288
Test name
Test status
Simulation time 127379181 ps
CPU time 1.1 seconds
Started Jul 28 05:31:35 PM PDT 24
Finished Jul 28 05:31:36 PM PDT 24
Peak memory 206532 kb
Host smart-f356a84d-1915-4569-8d06-e88ca369ac91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304100584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2304100584
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2173769673
Short name T1114
Test name
Test status
Simulation time 13045917 ps
CPU time 0.87 seconds
Started Jul 28 05:31:37 PM PDT 24
Finished Jul 28 05:31:38 PM PDT 24
Peak memory 206440 kb
Host smart-715ac769-02e2-4aac-bfc8-12a1bcb4f300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173769673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2173769673
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.382943287
Short name T292
Test name
Test status
Simulation time 31068993 ps
CPU time 1.25 seconds
Started Jul 28 05:31:36 PM PDT 24
Finished Jul 28 05:31:38 PM PDT 24
Peak memory 206832 kb
Host smart-41a24b12-81c6-4bfe-bd68-44fa48149a05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382943287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.382943287
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1599269647
Short name T1116
Test name
Test status
Simulation time 223257167 ps
CPU time 2.58 seconds
Started Jul 28 05:31:35 PM PDT 24
Finished Jul 28 05:31:37 PM PDT 24
Peak memory 214940 kb
Host smart-5916a8c4-8fa8-4a2e-a5d3-b265f386692a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599269647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1599269647
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.845097868
Short name T1065
Test name
Test status
Simulation time 57212466 ps
CPU time 1.79 seconds
Started Jul 28 05:31:35 PM PDT 24
Finished Jul 28 05:31:37 PM PDT 24
Peak memory 206596 kb
Host smart-befc9999-811e-4ac0-8778-5fafba6e0067
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845097868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.845097868
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.271124163
Short name T1105
Test name
Test status
Simulation time 28474248 ps
CPU time 0.8 seconds
Started Jul 28 05:31:59 PM PDT 24
Finished Jul 28 05:31:59 PM PDT 24
Peak memory 206244 kb
Host smart-2ff5c7bd-7318-4753-bbd0-2aac1921facd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271124163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.271124163
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1877679742
Short name T1093
Test name
Test status
Simulation time 17573249 ps
CPU time 0.83 seconds
Started Jul 28 05:32:02 PM PDT 24
Finished Jul 28 05:32:03 PM PDT 24
Peak memory 206336 kb
Host smart-cc136ed3-20f0-4b17-afa3-991b0ab6c966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877679742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1877679742
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1802903358
Short name T1022
Test name
Test status
Simulation time 12537204 ps
CPU time 0.97 seconds
Started Jul 28 05:31:58 PM PDT 24
Finished Jul 28 05:31:59 PM PDT 24
Peak memory 206372 kb
Host smart-2ecff7f6-dcfd-449a-903d-51a3aa54fa95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802903358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1802903358
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3715954004
Short name T1043
Test name
Test status
Simulation time 38556121 ps
CPU time 0.85 seconds
Started Jul 28 05:32:00 PM PDT 24
Finished Jul 28 05:32:01 PM PDT 24
Peak memory 206288 kb
Host smart-20b433b5-39ec-4eae-83c0-0cf9f4711204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715954004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3715954004
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2647361333
Short name T997
Test name
Test status
Simulation time 11423164 ps
CPU time 0.89 seconds
Started Jul 28 05:32:01 PM PDT 24
Finished Jul 28 05:32:02 PM PDT 24
Peak memory 206464 kb
Host smart-561d0dcb-7735-4e04-bc51-5c93d0e6ac76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647361333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2647361333
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1076961264
Short name T1037
Test name
Test status
Simulation time 12801818 ps
CPU time 0.89 seconds
Started Jul 28 05:31:59 PM PDT 24
Finished Jul 28 05:32:00 PM PDT 24
Peak memory 206432 kb
Host smart-9869e1c2-877c-41c5-95d8-034755a68471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076961264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1076961264
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.868442637
Short name T1013
Test name
Test status
Simulation time 25141474 ps
CPU time 0.9 seconds
Started Jul 28 05:32:08 PM PDT 24
Finished Jul 28 05:32:09 PM PDT 24
Peak memory 206496 kb
Host smart-d08fafb6-638b-4498-957f-d4f3939c664c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868442637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.868442637
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.4224860353
Short name T1115
Test name
Test status
Simulation time 42010346 ps
CPU time 0.85 seconds
Started Jul 28 05:32:09 PM PDT 24
Finished Jul 28 05:32:10 PM PDT 24
Peak memory 206408 kb
Host smart-d54bf0a0-b0c2-42c4-ab82-c35f8117b153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224860353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.4224860353
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.4215523416
Short name T1110
Test name
Test status
Simulation time 39171074 ps
CPU time 0.89 seconds
Started Jul 28 05:32:06 PM PDT 24
Finished Jul 28 05:32:07 PM PDT 24
Peak memory 206256 kb
Host smart-557fa699-a55c-411d-b337-6e888b641c16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215523416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.4215523416
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.271359789
Short name T1041
Test name
Test status
Simulation time 46510748 ps
CPU time 0.87 seconds
Started Jul 28 05:32:05 PM PDT 24
Finished Jul 28 05:32:06 PM PDT 24
Peak memory 206456 kb
Host smart-3cb3df4a-3726-4b88-aa7c-c28ae1bd332f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271359789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.271359789
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1575814194
Short name T1100
Test name
Test status
Simulation time 54289289 ps
CPU time 1.38 seconds
Started Jul 28 05:31:42 PM PDT 24
Finished Jul 28 05:31:43 PM PDT 24
Peak memory 217736 kb
Host smart-be49774b-e150-44dd-9a3a-1017c34487c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575814194 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1575814194
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1516748974
Short name T280
Test name
Test status
Simulation time 119190162 ps
CPU time 0.83 seconds
Started Jul 28 05:31:48 PM PDT 24
Finished Jul 28 05:31:49 PM PDT 24
Peak memory 206216 kb
Host smart-d02b6d7f-4ca2-43b4-b72e-22084460bb14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516748974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1516748974
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.4087145082
Short name T1033
Test name
Test status
Simulation time 31415687 ps
CPU time 0.8 seconds
Started Jul 28 05:31:42 PM PDT 24
Finished Jul 28 05:31:43 PM PDT 24
Peak memory 206232 kb
Host smart-7ce76a46-c1b9-4a0c-aa79-e1f2b3252a30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087145082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.4087145082
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.379246034
Short name T1102
Test name
Test status
Simulation time 174205130 ps
CPU time 1.07 seconds
Started Jul 28 05:31:43 PM PDT 24
Finished Jul 28 05:31:45 PM PDT 24
Peak memory 206588 kb
Host smart-d533ae05-f474-4179-9ccc-538ab4d82b51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379246034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.379246034
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1415426508
Short name T1020
Test name
Test status
Simulation time 109424719 ps
CPU time 3.9 seconds
Started Jul 28 05:31:43 PM PDT 24
Finished Jul 28 05:31:48 PM PDT 24
Peak memory 214896 kb
Host smart-8b4d5fe4-a0f6-4613-a198-66388e1012da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415426508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1415426508
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2761239693
Short name T241
Test name
Test status
Simulation time 154345288 ps
CPU time 2.4 seconds
Started Jul 28 05:31:45 PM PDT 24
Finished Jul 28 05:31:48 PM PDT 24
Peak memory 206744 kb
Host smart-f90465cc-fd00-418c-8469-12a290c55844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761239693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2761239693
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.282408215
Short name T1117
Test name
Test status
Simulation time 49342976 ps
CPU time 1.71 seconds
Started Jul 28 05:31:44 PM PDT 24
Finished Jul 28 05:31:46 PM PDT 24
Peak memory 214928 kb
Host smart-12160497-6af0-4e47-9fcf-fe137626efbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282408215 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.282408215
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1845339668
Short name T293
Test name
Test status
Simulation time 12988714 ps
CPU time 0.9 seconds
Started Jul 28 05:31:48 PM PDT 24
Finished Jul 28 05:31:49 PM PDT 24
Peak memory 206448 kb
Host smart-b301f640-343f-4340-8db5-a6348c778062
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845339668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1845339668
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3789148525
Short name T1123
Test name
Test status
Simulation time 28023743 ps
CPU time 0.81 seconds
Started Jul 28 05:31:48 PM PDT 24
Finished Jul 28 05:31:49 PM PDT 24
Peak memory 206268 kb
Host smart-e3b6b6e0-b365-43f1-a5b0-c220526bcc7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789148525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3789148525
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1962453254
Short name T1099
Test name
Test status
Simulation time 31153652 ps
CPU time 1.41 seconds
Started Jul 28 05:31:43 PM PDT 24
Finished Jul 28 05:31:45 PM PDT 24
Peak memory 206596 kb
Host smart-fe708c5a-58d8-4bb1-879f-2f553158f1de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962453254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1962453254
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3332926872
Short name T1024
Test name
Test status
Simulation time 733339683 ps
CPU time 4.97 seconds
Started Jul 28 05:31:41 PM PDT 24
Finished Jul 28 05:31:46 PM PDT 24
Peak memory 215164 kb
Host smart-d5cfb50c-3e7c-4a0c-b33b-eba8aff6c806
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332926872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3332926872
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3799150592
Short name T242
Test name
Test status
Simulation time 177773364 ps
CPU time 2.27 seconds
Started Jul 28 05:31:42 PM PDT 24
Finished Jul 28 05:31:45 PM PDT 24
Peak memory 206684 kb
Host smart-de2ad2c4-6a7a-492a-bc66-6b2fa6b1393c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799150592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3799150592
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2178567805
Short name T1000
Test name
Test status
Simulation time 58092500 ps
CPU time 0.99 seconds
Started Jul 28 05:31:43 PM PDT 24
Finished Jul 28 05:31:44 PM PDT 24
Peak memory 206648 kb
Host smart-54202904-b515-4ddb-9a29-054184ca2ac5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178567805 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2178567805
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.4157929754
Short name T282
Test name
Test status
Simulation time 26507269 ps
CPU time 0.91 seconds
Started Jul 28 05:31:45 PM PDT 24
Finished Jul 28 05:31:46 PM PDT 24
Peak memory 206448 kb
Host smart-d4397c7a-fd6f-454c-a62e-abb3b50ef448
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157929754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.4157929754
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.4219015871
Short name T1066
Test name
Test status
Simulation time 19553477 ps
CPU time 0.85 seconds
Started Jul 28 05:31:46 PM PDT 24
Finished Jul 28 05:31:47 PM PDT 24
Peak memory 206452 kb
Host smart-661e305c-4e93-4868-9afb-69c3e31e1eff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219015871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.4219015871
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2015449060
Short name T1089
Test name
Test status
Simulation time 37550791 ps
CPU time 1.2 seconds
Started Jul 28 05:31:48 PM PDT 24
Finished Jul 28 05:31:50 PM PDT 24
Peak memory 206600 kb
Host smart-e8e9ed14-2251-4273-b468-b4f2ffee165e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015449060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2015449060
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3440324863
Short name T1077
Test name
Test status
Simulation time 91889239 ps
CPU time 3.53 seconds
Started Jul 28 05:31:45 PM PDT 24
Finished Jul 28 05:31:49 PM PDT 24
Peak memory 214880 kb
Host smart-1aabe4f4-19c9-487a-adb7-00d20d89507c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440324863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3440324863
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4064307150
Short name T307
Test name
Test status
Simulation time 102249524 ps
CPU time 2.65 seconds
Started Jul 28 05:31:43 PM PDT 24
Finished Jul 28 05:31:46 PM PDT 24
Peak memory 214760 kb
Host smart-e4c3e4a3-3fab-4bb2-b343-b1796f25e1b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064307150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.4064307150
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.325808171
Short name T1038
Test name
Test status
Simulation time 41893905 ps
CPU time 1.48 seconds
Started Jul 28 05:31:43 PM PDT 24
Finished Jul 28 05:31:45 PM PDT 24
Peak memory 214864 kb
Host smart-f11dcb0e-af9e-4416-b442-96b653eb51da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325808171 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.325808171
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.659871140
Short name T287
Test name
Test status
Simulation time 50284003 ps
CPU time 0.89 seconds
Started Jul 28 05:31:44 PM PDT 24
Finished Jul 28 05:31:45 PM PDT 24
Peak memory 206404 kb
Host smart-30591442-d811-454d-8642-d2e7f0dbc5a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659871140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.659871140
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3248273105
Short name T1018
Test name
Test status
Simulation time 44038089 ps
CPU time 0.85 seconds
Started Jul 28 05:31:44 PM PDT 24
Finished Jul 28 05:31:45 PM PDT 24
Peak memory 206388 kb
Host smart-31e5df95-2c1d-4dde-a8a0-1cc292b22172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248273105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3248273105
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2359902895
Short name T1052
Test name
Test status
Simulation time 105838027 ps
CPU time 1.57 seconds
Started Jul 28 05:31:42 PM PDT 24
Finished Jul 28 05:31:44 PM PDT 24
Peak memory 206640 kb
Host smart-d2ddb777-cbe9-4e50-8d23-a3795396bd4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359902895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2359902895
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3884846228
Short name T999
Test name
Test status
Simulation time 151092972 ps
CPU time 1.91 seconds
Started Jul 28 05:31:44 PM PDT 24
Finished Jul 28 05:31:46 PM PDT 24
Peak memory 214796 kb
Host smart-9b18a766-a5ef-40d0-8c93-bc45c7055c54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884846228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3884846228
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1347208875
Short name T1040
Test name
Test status
Simulation time 90693675 ps
CPU time 1.64 seconds
Started Jul 28 05:31:44 PM PDT 24
Finished Jul 28 05:31:46 PM PDT 24
Peak memory 206708 kb
Host smart-b448a3e3-fd7d-4995-9c83-17ca6693a4ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347208875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1347208875
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3555681856
Short name T1053
Test name
Test status
Simulation time 21373738 ps
CPU time 1.47 seconds
Started Jul 28 05:31:48 PM PDT 24
Finished Jul 28 05:31:49 PM PDT 24
Peak memory 214864 kb
Host smart-f04db183-d27b-4f72-a380-3ce16d1fb471
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555681856 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3555681856
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3009267812
Short name T279
Test name
Test status
Simulation time 24915499 ps
CPU time 0.9 seconds
Started Jul 28 05:31:43 PM PDT 24
Finished Jul 28 05:31:44 PM PDT 24
Peak memory 206428 kb
Host smart-5b89185f-5b8b-43c2-bade-0fd00c119c08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009267812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3009267812
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2353360697
Short name T1092
Test name
Test status
Simulation time 37302549 ps
CPU time 0.87 seconds
Started Jul 28 05:31:43 PM PDT 24
Finished Jul 28 05:31:44 PM PDT 24
Peak memory 206464 kb
Host smart-1c3bba33-b174-4ab6-a01c-6ab89102218a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353360697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2353360697
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4115708334
Short name T294
Test name
Test status
Simulation time 19503736 ps
CPU time 1.1 seconds
Started Jul 28 05:31:45 PM PDT 24
Finished Jul 28 05:31:46 PM PDT 24
Peak memory 206608 kb
Host smart-ec7bc3db-0762-4c0f-be75-fcb52735d279
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115708334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.4115708334
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4037808508
Short name T1042
Test name
Test status
Simulation time 137408443 ps
CPU time 2.84 seconds
Started Jul 28 05:31:43 PM PDT 24
Finished Jul 28 05:31:46 PM PDT 24
Peak memory 214820 kb
Host smart-694c5261-1451-4d75-9113-7ec602fe9521
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037808508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4037808508
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3812509474
Short name T1075
Test name
Test status
Simulation time 67338753 ps
CPU time 1.44 seconds
Started Jul 28 05:31:42 PM PDT 24
Finished Jul 28 05:31:44 PM PDT 24
Peak memory 206660 kb
Host smart-1b53658f-8248-477f-a177-2be2c9399afd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812509474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3812509474
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1822307808
Short name T179
Test name
Test status
Simulation time 69012007 ps
CPU time 1.25 seconds
Started Jul 28 05:36:30 PM PDT 24
Finished Jul 28 05:36:32 PM PDT 24
Peak memory 218488 kb
Host smart-5b3b39df-1824-4574-9f39-b44a17a5fe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822307808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1822307808
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.4076300597
Short name T695
Test name
Test status
Simulation time 19807112 ps
CPU time 0.87 seconds
Started Jul 28 05:36:33 PM PDT 24
Finished Jul 28 05:36:34 PM PDT 24
Peak memory 206400 kb
Host smart-785df2c0-9d05-41af-a5cc-f6425beedb9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076300597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.4076300597
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.730707884
Short name T565
Test name
Test status
Simulation time 74676938 ps
CPU time 0.95 seconds
Started Jul 28 05:36:37 PM PDT 24
Finished Jul 28 05:36:38 PM PDT 24
Peak memory 216056 kb
Host smart-1bc44ed8-c3fd-449c-80f3-1b7aea036470
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730707884 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.730707884
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.988839685
Short name T278
Test name
Test status
Simulation time 60698408 ps
CPU time 1.24 seconds
Started Jul 28 05:36:35 PM PDT 24
Finished Jul 28 05:36:37 PM PDT 24
Peak memory 216712 kb
Host smart-b7504b2d-b20a-4dbf-8562-ccf779d58d7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988839685 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.988839685
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_regwen.809405779
Short name T932
Test name
Test status
Simulation time 45408649 ps
CPU time 0.97 seconds
Started Jul 28 05:36:30 PM PDT 24
Finished Jul 28 05:36:32 PM PDT 24
Peak memory 206976 kb
Host smart-2ae94a78-0c66-44c9-8c65-de0649288b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809405779 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.809405779
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.70327641
Short name T422
Test name
Test status
Simulation time 25633754 ps
CPU time 0.94 seconds
Started Jul 28 05:36:32 PM PDT 24
Finished Jul 28 05:36:33 PM PDT 24
Peak memory 215160 kb
Host smart-ea3098f9-d84b-4b81-af2f-76ba7783874f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70327641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.70327641
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2389402826
Short name T576
Test name
Test status
Simulation time 521922376 ps
CPU time 2.71 seconds
Started Jul 28 05:36:27 PM PDT 24
Finished Jul 28 05:36:30 PM PDT 24
Peak memory 217024 kb
Host smart-fc6b4016-2f33-4b01-bbd8-f238accd9570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389402826 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2389402826
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.86728553
Short name T774
Test name
Test status
Simulation time 104071236309 ps
CPU time 1155.41 seconds
Started Jul 28 05:36:30 PM PDT 24
Finished Jul 28 05:55:45 PM PDT 24
Peak memory 223704 kb
Host smart-0c08511c-6052-426e-8c55-fbe47e931a42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86728553 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.86728553
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.1543620897
Short name T509
Test name
Test status
Simulation time 39428167 ps
CPU time 1.04 seconds
Started Jul 28 05:36:36 PM PDT 24
Finished Jul 28 05:36:37 PM PDT 24
Peak memory 206736 kb
Host smart-04432ebe-f383-4498-9def-bc86518021b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543620897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1543620897
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.53955532
Short name T455
Test name
Test status
Simulation time 29399251 ps
CPU time 0.82 seconds
Started Jul 28 05:36:36 PM PDT 24
Finished Jul 28 05:36:37 PM PDT 24
Peak memory 216084 kb
Host smart-90e7d568-e150-49b6-90d6-4f753aa7b8a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53955532 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.53955532
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.181043200
Short name T583
Test name
Test status
Simulation time 82105350 ps
CPU time 1.35 seconds
Started Jul 28 05:36:35 PM PDT 24
Finished Jul 28 05:36:37 PM PDT 24
Peak memory 216860 kb
Host smart-53a38061-1db7-4d6e-9fb1-245d5da8ec77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181043200 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.181043200
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3811903822
Short name T813
Test name
Test status
Simulation time 67419718 ps
CPU time 0.86 seconds
Started Jul 28 05:36:33 PM PDT 24
Finished Jul 28 05:36:35 PM PDT 24
Peak memory 218180 kb
Host smart-deb8c73f-060f-4d14-bef8-144495ae11f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811903822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3811903822
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.584177562
Short name T454
Test name
Test status
Simulation time 66597506 ps
CPU time 1.29 seconds
Started Jul 28 05:36:34 PM PDT 24
Finished Jul 28 05:36:36 PM PDT 24
Peak memory 218652 kb
Host smart-6fc86a5a-9f5e-430e-88f8-0573d6596b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584177562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.584177562
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.3960640203
Short name T832
Test name
Test status
Simulation time 157927609 ps
CPU time 0.95 seconds
Started Jul 28 05:36:37 PM PDT 24
Finished Jul 28 05:36:38 PM PDT 24
Peak memory 206960 kb
Host smart-76018a47-56a9-4a87-bf03-15b2477fc9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960640203 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3960640203
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.663894491
Short name T373
Test name
Test status
Simulation time 18365589 ps
CPU time 1.02 seconds
Started Jul 28 05:36:36 PM PDT 24
Finished Jul 28 05:36:37 PM PDT 24
Peak memory 215192 kb
Host smart-138047c5-3f83-4342-a9c6-538db42cc734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663894491 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.663894491
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1473485291
Short name T387
Test name
Test status
Simulation time 117139014 ps
CPU time 1.8 seconds
Started Jul 28 05:36:32 PM PDT 24
Finished Jul 28 05:36:34 PM PDT 24
Peak memory 216992 kb
Host smart-3c5ec655-8247-43b3-a8b7-0888ba33d0ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473485291 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1473485291
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3429834372
Short name T833
Test name
Test status
Simulation time 857387663268 ps
CPU time 2128.17 seconds
Started Jul 28 05:36:33 PM PDT 24
Finished Jul 28 06:12:02 PM PDT 24
Peak memory 228388 kb
Host smart-0df45fc8-a9ee-4bc1-a97f-2ac88787e84d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429834372 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3429834372
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.4291355419
Short name T297
Test name
Test status
Simulation time 50129974 ps
CPU time 1.22 seconds
Started Jul 28 05:36:52 PM PDT 24
Finished Jul 28 05:36:53 PM PDT 24
Peak memory 219132 kb
Host smart-92f385af-efd6-49ef-bceb-3132db19e6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291355419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.4291355419
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.3854458937
Short name T133
Test name
Test status
Simulation time 20715610 ps
CPU time 0.91 seconds
Started Jul 28 05:36:50 PM PDT 24
Finished Jul 28 05:36:51 PM PDT 24
Peak memory 216060 kb
Host smart-cf15d7f0-78ee-4ed4-9af4-c8eb7f43579c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854458937 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3854458937
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.2974120115
Short name T135
Test name
Test status
Simulation time 26539410 ps
CPU time 1 seconds
Started Jul 28 05:36:49 PM PDT 24
Finished Jul 28 05:36:50 PM PDT 24
Peak memory 223704 kb
Host smart-a6ab16a9-3722-4cb7-9b73-2fdf1e1b4a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974120115 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2974120115
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2262193215
Short name T887
Test name
Test status
Simulation time 72420678 ps
CPU time 2.72 seconds
Started Jul 28 05:36:44 PM PDT 24
Finished Jul 28 05:36:47 PM PDT 24
Peak memory 220008 kb
Host smart-5fceec49-3440-437c-8b0b-dba3d863a76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262193215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2262193215
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2330632383
Short name T98
Test name
Test status
Simulation time 24722432 ps
CPU time 0.93 seconds
Started Jul 28 05:36:55 PM PDT 24
Finished Jul 28 05:36:56 PM PDT 24
Peak memory 215608 kb
Host smart-4a8f22f0-c206-4d70-b7d2-a7df29fd5b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330632383 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2330632383
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.524982090
Short name T730
Test name
Test status
Simulation time 48134615 ps
CPU time 1 seconds
Started Jul 28 05:36:41 PM PDT 24
Finished Jul 28 05:36:43 PM PDT 24
Peak memory 215164 kb
Host smart-203b0701-8b23-4443-9998-27d8db8256f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524982090 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.524982090
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3949200586
Short name T246
Test name
Test status
Simulation time 728235967193 ps
CPU time 1535.08 seconds
Started Jul 28 05:36:51 PM PDT 24
Finished Jul 28 06:02:26 PM PDT 24
Peak memory 222804 kb
Host smart-c0faa587-de4d-49b7-b1b1-994e519c5d71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949200586 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3949200586
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.1399160442
Short name T960
Test name
Test status
Simulation time 141339029 ps
CPU time 1.22 seconds
Started Jul 28 05:38:20 PM PDT 24
Finished Jul 28 05:38:21 PM PDT 24
Peak memory 219700 kb
Host smart-0d90522d-8d28-40c6-aad5-4d890c14b697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399160442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.1399160442
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.1970603118
Short name T362
Test name
Test status
Simulation time 58516603 ps
CPU time 0.95 seconds
Started Jul 28 05:38:23 PM PDT 24
Finished Jul 28 05:38:24 PM PDT 24
Peak memory 217156 kb
Host smart-4bab0d47-1c4e-44e0-8be3-34b17bb8b93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970603118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1970603118
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.111635063
Short name T167
Test name
Test status
Simulation time 51957087 ps
CPU time 1.06 seconds
Started Jul 28 05:38:22 PM PDT 24
Finished Jul 28 05:38:23 PM PDT 24
Peak memory 218728 kb
Host smart-01318c8e-9001-43ba-b672-d72e856de612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111635063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.111635063
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.3642303267
Short name T653
Test name
Test status
Simulation time 111250252 ps
CPU time 1.13 seconds
Started Jul 28 05:38:18 PM PDT 24
Finished Jul 28 05:38:19 PM PDT 24
Peak memory 217144 kb
Host smart-ae35a1ba-0968-44a0-bfb9-453bc2e41abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642303267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3642303267
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.3799220422
Short name T498
Test name
Test status
Simulation time 49605358 ps
CPU time 1.21 seconds
Started Jul 28 05:38:21 PM PDT 24
Finished Jul 28 05:38:22 PM PDT 24
Peak memory 218700 kb
Host smart-d7ddd5f1-edcb-4394-a276-d7cdf706fad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799220422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.3799220422
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.1533807655
Short name T56
Test name
Test status
Simulation time 40674113 ps
CPU time 1.38 seconds
Started Jul 28 05:38:21 PM PDT 24
Finished Jul 28 05:38:23 PM PDT 24
Peak memory 218356 kb
Host smart-37488106-0699-4b19-8304-aefc124e33da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533807655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1533807655
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.321163768
Short name T747
Test name
Test status
Simulation time 84030027 ps
CPU time 1.13 seconds
Started Jul 28 05:38:18 PM PDT 24
Finished Jul 28 05:38:19 PM PDT 24
Peak memory 219428 kb
Host smart-b1386c14-34f7-4c08-b338-bd54432eb838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321163768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.321163768
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.2409159727
Short name T548
Test name
Test status
Simulation time 53383242 ps
CPU time 2.11 seconds
Started Jul 28 05:38:23 PM PDT 24
Finished Jul 28 05:38:25 PM PDT 24
Peak memory 218672 kb
Host smart-349f2531-85b6-4a79-b293-b50639b54c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409159727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2409159727
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.2298162870
Short name T196
Test name
Test status
Simulation time 174256915 ps
CPU time 1.33 seconds
Started Jul 28 05:38:20 PM PDT 24
Finished Jul 28 05:38:21 PM PDT 24
Peak memory 218848 kb
Host smart-8c779d97-67da-4bad-8ca0-efb222f5f77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298162870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.2298162870
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/106.edn_alert.1317470891
Short name T727
Test name
Test status
Simulation time 89721351 ps
CPU time 1.32 seconds
Started Jul 28 05:38:22 PM PDT 24
Finished Jul 28 05:38:24 PM PDT 24
Peak memory 220428 kb
Host smart-6b80fa47-5066-45b3-84ac-bf6c716d9257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317470891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.1317470891
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.3672261544
Short name T661
Test name
Test status
Simulation time 92543890 ps
CPU time 2.01 seconds
Started Jul 28 05:38:21 PM PDT 24
Finished Jul 28 05:38:23 PM PDT 24
Peak memory 218484 kb
Host smart-6072c859-d42c-47b1-84e0-3dd60ebd6db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672261544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3672261544
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.4076858852
Short name T666
Test name
Test status
Simulation time 90509197 ps
CPU time 1.17 seconds
Started Jul 28 05:38:25 PM PDT 24
Finished Jul 28 05:38:27 PM PDT 24
Peak memory 219344 kb
Host smart-e810a293-4b91-43a9-b638-95030343e433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076858852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.4076858852
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.2575086944
Short name T406
Test name
Test status
Simulation time 288051363 ps
CPU time 4.28 seconds
Started Jul 28 05:38:24 PM PDT 24
Finished Jul 28 05:38:29 PM PDT 24
Peak memory 220096 kb
Host smart-8239f1f5-a84b-441a-aaed-a8c9fc2b06ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575086944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2575086944
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.4002610011
Short name T702
Test name
Test status
Simulation time 45246141 ps
CPU time 1.66 seconds
Started Jul 28 05:38:25 PM PDT 24
Finished Jul 28 05:38:27 PM PDT 24
Peak memory 218328 kb
Host smart-fca2a1b0-059f-4b12-a683-7b567bf2ac81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002610011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.4002610011
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.2526800140
Short name T691
Test name
Test status
Simulation time 28134630 ps
CPU time 1.19 seconds
Started Jul 28 05:38:27 PM PDT 24
Finished Jul 28 05:38:28 PM PDT 24
Peak memory 218364 kb
Host smart-eb1f1aab-bdba-4165-9b23-92eb08df4f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526800140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.2526800140
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3829150834
Short name T585
Test name
Test status
Simulation time 221857364 ps
CPU time 1.23 seconds
Started Jul 28 05:38:25 PM PDT 24
Finished Jul 28 05:38:26 PM PDT 24
Peak memory 217280 kb
Host smart-bf768b55-3a94-4906-88a3-953a996f7795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829150834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3829150834
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.4213031734
Short name T605
Test name
Test status
Simulation time 21266473 ps
CPU time 0.87 seconds
Started Jul 28 05:36:52 PM PDT 24
Finished Jul 28 05:36:53 PM PDT 24
Peak memory 206636 kb
Host smart-20574ce2-2eca-4769-af41-d857c3e70197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213031734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4213031734
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3219791245
Short name T592
Test name
Test status
Simulation time 11268687 ps
CPU time 0.89 seconds
Started Jul 28 05:36:52 PM PDT 24
Finished Jul 28 05:36:53 PM PDT 24
Peak memory 216104 kb
Host smart-7ffc5862-0ab6-400c-9111-131135e41c9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219791245 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3219791245
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_genbits.4011562521
Short name T680
Test name
Test status
Simulation time 80588462 ps
CPU time 1.07 seconds
Started Jul 28 05:36:55 PM PDT 24
Finished Jul 28 05:36:56 PM PDT 24
Peak memory 216960 kb
Host smart-126f24ff-bbe6-4e1f-8a06-eca2f607c0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011562521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.4011562521
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3999620115
Short name T962
Test name
Test status
Simulation time 21162827 ps
CPU time 1.1 seconds
Started Jul 28 05:36:49 PM PDT 24
Finished Jul 28 05:36:50 PM PDT 24
Peak memory 215772 kb
Host smart-f9d63469-58cc-4af1-8a7b-5c3e55aba57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999620115 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3999620115
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2851937135
Short name T677
Test name
Test status
Simulation time 34300052 ps
CPU time 0.88 seconds
Started Jul 28 05:36:51 PM PDT 24
Finished Jul 28 05:36:52 PM PDT 24
Peak memory 215132 kb
Host smart-f9754aa1-1905-45cf-9b4a-70182492a87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851937135 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2851937135
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.775334268
Short name T489
Test name
Test status
Simulation time 225073058 ps
CPU time 1.68 seconds
Started Jul 28 05:36:51 PM PDT 24
Finished Jul 28 05:36:53 PM PDT 24
Peak memory 215244 kb
Host smart-db52f099-2963-4c08-a511-643b40b7c19c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775334268 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.775334268
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1954154007
Short name T703
Test name
Test status
Simulation time 51915484511 ps
CPU time 564.97 seconds
Started Jul 28 05:36:54 PM PDT 24
Finished Jul 28 05:46:20 PM PDT 24
Peak memory 218464 kb
Host smart-e1c40abd-1562-49d2-adea-fa3670670b76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954154007 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1954154007
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.1624026744
Short name T595
Test name
Test status
Simulation time 89839687 ps
CPU time 1.28 seconds
Started Jul 28 05:38:29 PM PDT 24
Finished Jul 28 05:38:31 PM PDT 24
Peak memory 217044 kb
Host smart-c1ed3e51-0a8e-4fe3-9e6f-108e8bf87b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624026744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1624026744
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.1482760224
Short name T852
Test name
Test status
Simulation time 49669782 ps
CPU time 1.23 seconds
Started Jul 28 05:38:29 PM PDT 24
Finished Jul 28 05:38:30 PM PDT 24
Peak memory 219436 kb
Host smart-05efec9b-a9b5-4de8-a517-594c87ad9c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482760224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.1482760224
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.560760153
Short name T163
Test name
Test status
Simulation time 67948957 ps
CPU time 0.97 seconds
Started Jul 28 05:38:28 PM PDT 24
Finished Jul 28 05:38:29 PM PDT 24
Peak memory 217392 kb
Host smart-be9b99ff-e78b-49ff-9204-d89576819cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560760153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.560760153
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3657050984
Short name T511
Test name
Test status
Simulation time 100586645 ps
CPU time 1.1 seconds
Started Jul 28 05:38:28 PM PDT 24
Finished Jul 28 05:38:29 PM PDT 24
Peak memory 219528 kb
Host smart-8984b5f6-52a8-4342-a0e3-e5bc75f11ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657050984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3657050984
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.1611945347
Short name T468
Test name
Test status
Simulation time 160312665 ps
CPU time 2.95 seconds
Started Jul 28 05:38:27 PM PDT 24
Finished Jul 28 05:38:30 PM PDT 24
Peak memory 219668 kb
Host smart-93af133a-2a74-4799-8269-6fd79519ec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611945347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1611945347
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2599999695
Short name T587
Test name
Test status
Simulation time 68637303 ps
CPU time 1.12 seconds
Started Jul 28 05:38:25 PM PDT 24
Finished Jul 28 05:38:26 PM PDT 24
Peak memory 220628 kb
Host smart-b06398da-dbe3-40b8-accb-3eb197424af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599999695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2599999695
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.448174624
Short name T466
Test name
Test status
Simulation time 62608418 ps
CPU time 1.2 seconds
Started Jul 28 05:38:30 PM PDT 24
Finished Jul 28 05:38:31 PM PDT 24
Peak memory 218608 kb
Host smart-f5f7d76d-36fb-4381-9ab6-17bbecc7fba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448174624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.448174624
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.291568738
Short name T681
Test name
Test status
Simulation time 85114258 ps
CPU time 1.15 seconds
Started Jul 28 05:38:26 PM PDT 24
Finished Jul 28 05:38:28 PM PDT 24
Peak memory 219280 kb
Host smart-049573d6-643c-4691-9b5b-9d65ee9d62d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291568738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.291568738
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3442032540
Short name T442
Test name
Test status
Simulation time 201274425 ps
CPU time 3.7 seconds
Started Jul 28 05:38:23 PM PDT 24
Finished Jul 28 05:38:27 PM PDT 24
Peak memory 218700 kb
Host smart-dba9ec90-8edf-41c8-99b5-93e4de46f9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442032540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3442032540
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.3333923955
Short name T463
Test name
Test status
Simulation time 38696829 ps
CPU time 1.14 seconds
Started Jul 28 05:38:27 PM PDT 24
Finished Jul 28 05:38:29 PM PDT 24
Peak memory 219024 kb
Host smart-ee23218d-f9a5-4146-86ff-073ab5c9a843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333923955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3333923955
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.1025506297
Short name T745
Test name
Test status
Simulation time 115988297 ps
CPU time 1.15 seconds
Started Jul 28 05:38:24 PM PDT 24
Finished Jul 28 05:38:25 PM PDT 24
Peak memory 217176 kb
Host smart-59f2e48d-8956-4e35-99b0-ec4ac30bbb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025506297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1025506297
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3215150572
Short name T237
Test name
Test status
Simulation time 38334527 ps
CPU time 1.17 seconds
Started Jul 28 05:38:24 PM PDT 24
Finished Jul 28 05:38:26 PM PDT 24
Peak memory 219864 kb
Host smart-f8bf6072-b63b-4c6a-b67e-172bd9eddc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215150572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3215150572
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.3693953153
Short name T615
Test name
Test status
Simulation time 24787967 ps
CPU time 1.26 seconds
Started Jul 28 05:38:25 PM PDT 24
Finished Jul 28 05:38:26 PM PDT 24
Peak memory 219472 kb
Host smart-4ecb1822-431a-4afa-9349-bc818a1d7874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693953153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3693953153
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.2702938632
Short name T471
Test name
Test status
Simulation time 28219567 ps
CPU time 1.27 seconds
Started Jul 28 05:38:33 PM PDT 24
Finished Jul 28 05:38:34 PM PDT 24
Peak memory 219636 kb
Host smart-b2d95fbf-b82c-4367-919e-961f223c0c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702938632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.2702938632
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.2633564885
Short name T461
Test name
Test status
Simulation time 298869976 ps
CPU time 3.79 seconds
Started Jul 28 05:38:24 PM PDT 24
Finished Jul 28 05:38:28 PM PDT 24
Peak memory 217488 kb
Host smart-badcbe3a-9443-4571-8f31-959e6cca6bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633564885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2633564885
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2499637986
Short name T389
Test name
Test status
Simulation time 57582467 ps
CPU time 1.21 seconds
Started Jul 28 05:38:29 PM PDT 24
Finished Jul 28 05:38:30 PM PDT 24
Peak memory 218376 kb
Host smart-d21b82f6-2d02-4790-a968-17aa90cc9b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499637986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2499637986
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.4255977747
Short name T439
Test name
Test status
Simulation time 40208450 ps
CPU time 1.18 seconds
Started Jul 28 05:38:26 PM PDT 24
Finished Jul 28 05:38:28 PM PDT 24
Peak memory 217212 kb
Host smart-9ebafaf3-bddf-4746-b9e3-67b6eb3dd68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255977747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.4255977747
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.553428148
Short name T478
Test name
Test status
Simulation time 51024975 ps
CPU time 1.25 seconds
Started Jul 28 05:36:59 PM PDT 24
Finished Jul 28 05:37:00 PM PDT 24
Peak memory 219444 kb
Host smart-a00209a8-73a9-40a8-b850-dccc8ddce1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553428148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.553428148
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1056427659
Short name T357
Test name
Test status
Simulation time 22822268 ps
CPU time 0.94 seconds
Started Jul 28 05:36:55 PM PDT 24
Finished Jul 28 05:36:56 PM PDT 24
Peak memory 206696 kb
Host smart-54345d30-bbd2-4b3d-a111-e30904862659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056427659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1056427659
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.637176096
Short name T708
Test name
Test status
Simulation time 56528396 ps
CPU time 1.12 seconds
Started Jul 28 05:36:55 PM PDT 24
Finished Jul 28 05:36:56 PM PDT 24
Peak memory 216864 kb
Host smart-cc99d29a-6cf2-4fda-8739-fcee1baa19d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637176096 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.637176096
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.433777927
Short name T214
Test name
Test status
Simulation time 34190997 ps
CPU time 0.84 seconds
Started Jul 28 05:36:55 PM PDT 24
Finished Jul 28 05:36:56 PM PDT 24
Peak memory 218028 kb
Host smart-4774da7f-bb40-403c-866f-0b4594791218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433777927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.433777927
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.190224365
Short name T94
Test name
Test status
Simulation time 44679281 ps
CPU time 1.21 seconds
Started Jul 28 05:36:50 PM PDT 24
Finished Jul 28 05:36:51 PM PDT 24
Peak memory 218392 kb
Host smart-2ec9fe21-6262-4ad3-aad0-ea4115a3c5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190224365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.190224365
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2058267370
Short name T105
Test name
Test status
Simulation time 33322293 ps
CPU time 0.86 seconds
Started Jul 28 05:36:58 PM PDT 24
Finished Jul 28 05:36:59 PM PDT 24
Peak memory 215552 kb
Host smart-e28369c7-5102-4b4b-909c-d5ca349559e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058267370 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2058267370
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.779186837
Short name T66
Test name
Test status
Simulation time 15363123 ps
CPU time 1.01 seconds
Started Jul 28 05:36:52 PM PDT 24
Finished Jul 28 05:36:53 PM PDT 24
Peak memory 215180 kb
Host smart-385dfdbc-0d7c-4ddc-98c5-ddad77ac7a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779186837 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.779186837
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2576206236
Short name T43
Test name
Test status
Simulation time 259912186 ps
CPU time 5.33 seconds
Started Jul 28 05:36:55 PM PDT 24
Finished Jul 28 05:37:00 PM PDT 24
Peak memory 216856 kb
Host smart-d1f75436-b360-4929-aad5-ebed974416e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576206236 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2576206236
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2288372840
Short name T459
Test name
Test status
Simulation time 37399968822 ps
CPU time 479.22 seconds
Started Jul 28 05:36:59 PM PDT 24
Finished Jul 28 05:44:59 PM PDT 24
Peak memory 218412 kb
Host smart-d8acd453-16ef-40f5-83d0-18848511f618
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288372840 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2288372840
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.4060499531
Short name T716
Test name
Test status
Simulation time 73730016 ps
CPU time 1.12 seconds
Started Jul 28 05:38:31 PM PDT 24
Finished Jul 28 05:38:32 PM PDT 24
Peak memory 220304 kb
Host smart-04dfa104-de86-4d8f-9513-6935d1e84907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060499531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.4060499531
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.3197691716
Short name T925
Test name
Test status
Simulation time 56752527 ps
CPU time 1.07 seconds
Started Jul 28 05:38:44 PM PDT 24
Finished Jul 28 05:38:46 PM PDT 24
Peak memory 217256 kb
Host smart-51526c26-0cfb-4934-8862-ff758cdebff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197691716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3197691716
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.1090325672
Short name T527
Test name
Test status
Simulation time 82995280 ps
CPU time 1.19 seconds
Started Jul 28 05:38:33 PM PDT 24
Finished Jul 28 05:38:34 PM PDT 24
Peak memory 220864 kb
Host smart-5898a6a7-494d-4ba2-ac56-65b1f7354a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090325672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1090325672
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.1640872318
Short name T326
Test name
Test status
Simulation time 69073521 ps
CPU time 1.29 seconds
Started Jul 28 05:38:30 PM PDT 24
Finished Jul 28 05:38:31 PM PDT 24
Peak memory 218788 kb
Host smart-4272d7ec-039f-4d77-a31a-50f748556e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640872318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1640872318
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.1768064805
Short name T267
Test name
Test status
Simulation time 28564063 ps
CPU time 1.25 seconds
Started Jul 28 05:38:31 PM PDT 24
Finished Jul 28 05:38:32 PM PDT 24
Peak memory 220708 kb
Host smart-f9537681-ca24-4c3a-9867-9e1baa121089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768064805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1768064805
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.1508847111
Short name T263
Test name
Test status
Simulation time 36682186 ps
CPU time 1.45 seconds
Started Jul 28 05:38:32 PM PDT 24
Finished Jul 28 05:38:33 PM PDT 24
Peak memory 219988 kb
Host smart-545a612c-fdfa-4d54-8da5-4c1ce7445b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508847111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1508847111
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3577735278
Short name T414
Test name
Test status
Simulation time 22012532 ps
CPU time 1.12 seconds
Started Jul 28 05:38:34 PM PDT 24
Finished Jul 28 05:38:35 PM PDT 24
Peak memory 217284 kb
Host smart-9bc3a721-cb6b-407e-b8c1-659fb8f1f995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577735278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3577735278
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2996714144
Short name T849
Test name
Test status
Simulation time 78087040 ps
CPU time 1.13 seconds
Started Jul 28 05:38:36 PM PDT 24
Finished Jul 28 05:38:37 PM PDT 24
Peak memory 219672 kb
Host smart-5ded8bd3-27da-4306-b4a7-db74adfeec33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996714144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2996714144
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/125.edn_alert.1369964731
Short name T320
Test name
Test status
Simulation time 80053499 ps
CPU time 1.25 seconds
Started Jul 28 05:38:44 PM PDT 24
Finished Jul 28 05:38:46 PM PDT 24
Peak memory 218224 kb
Host smart-faba8f1c-8719-4ac1-91ca-1655b8c6ccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369964731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1369964731
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.3815307931
Short name T737
Test name
Test status
Simulation time 117013631 ps
CPU time 1.13 seconds
Started Jul 28 05:38:30 PM PDT 24
Finished Jul 28 05:38:31 PM PDT 24
Peak memory 217048 kb
Host smart-b55bc117-5435-464b-9991-06edd0f57b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815307931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3815307931
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1294300183
Short name T83
Test name
Test status
Simulation time 64887940 ps
CPU time 1.9 seconds
Started Jul 28 05:38:35 PM PDT 24
Finished Jul 28 05:38:37 PM PDT 24
Peak memory 218412 kb
Host smart-16d2efac-d396-4f8a-abc8-e4b277411149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294300183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1294300183
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.80653985
Short name T777
Test name
Test status
Simulation time 174059207 ps
CPU time 1.1 seconds
Started Jul 28 05:38:34 PM PDT 24
Finished Jul 28 05:38:35 PM PDT 24
Peak memory 218572 kb
Host smart-89eaf927-b1a6-44cc-a874-bacc6182d46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80653985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.80653985
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.3468283255
Short name T328
Test name
Test status
Simulation time 46087800 ps
CPU time 1.27 seconds
Started Jul 28 05:38:33 PM PDT 24
Finished Jul 28 05:38:34 PM PDT 24
Peak memory 219700 kb
Host smart-b8c3985e-c574-4c37-90de-148844d989be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468283255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3468283255
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2832830649
Short name T623
Test name
Test status
Simulation time 51301255 ps
CPU time 1.13 seconds
Started Jul 28 05:38:30 PM PDT 24
Finished Jul 28 05:38:32 PM PDT 24
Peak memory 218420 kb
Host smart-14948737-ac4a-4aea-8434-2a8c11d7c38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832830649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2832830649
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.1742498008
Short name T958
Test name
Test status
Simulation time 67597162 ps
CPU time 1.45 seconds
Started Jul 28 05:38:30 PM PDT 24
Finished Jul 28 05:38:31 PM PDT 24
Peak memory 217268 kb
Host smart-8dec169d-9c45-4425-8c79-5ffd1bc2b62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742498008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1742498008
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.3455284906
Short name T412
Test name
Test status
Simulation time 24883136 ps
CPU time 1.21 seconds
Started Jul 28 05:38:33 PM PDT 24
Finished Jul 28 05:38:34 PM PDT 24
Peak memory 218624 kb
Host smart-a9d287a7-b630-42b1-bbbb-e498cf3e565f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455284906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3455284906
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.1479703835
Short name T17
Test name
Test status
Simulation time 647977350 ps
CPU time 5.64 seconds
Started Jul 28 05:38:29 PM PDT 24
Finished Jul 28 05:38:35 PM PDT 24
Peak memory 218460 kb
Host smart-58809e78-7d33-4c36-962d-8e448abe43c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479703835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1479703835
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.994190362
Short name T181
Test name
Test status
Simulation time 90418651 ps
CPU time 1.31 seconds
Started Jul 28 05:36:56 PM PDT 24
Finished Jul 28 05:36:57 PM PDT 24
Peak memory 218744 kb
Host smart-8c580e65-f72c-41fc-917b-3b651ef82af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994190362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.994190362
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3118721890
Short name T517
Test name
Test status
Simulation time 38070192 ps
CPU time 0.87 seconds
Started Jul 28 05:36:58 PM PDT 24
Finished Jul 28 05:36:59 PM PDT 24
Peak memory 214764 kb
Host smart-34577094-10f3-438b-8ae2-d627ee9eb5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118721890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3118721890
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.847750458
Short name T965
Test name
Test status
Simulation time 77931261 ps
CPU time 1.07 seconds
Started Jul 28 05:36:56 PM PDT 24
Finished Jul 28 05:36:57 PM PDT 24
Peak memory 218292 kb
Host smart-26b03bfa-ea36-4690-af25-71e08594dc76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847750458 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.847750458
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2477021921
Short name T205
Test name
Test status
Simulation time 20997622 ps
CPU time 1.11 seconds
Started Jul 28 05:36:56 PM PDT 24
Finished Jul 28 05:36:58 PM PDT 24
Peak memory 223908 kb
Host smart-477a4161-d70c-4632-a594-2cfb19948e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477021921 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2477021921
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1746648532
Short name T819
Test name
Test status
Simulation time 88228725 ps
CPU time 1.3 seconds
Started Jul 28 05:36:57 PM PDT 24
Finished Jul 28 05:36:59 PM PDT 24
Peak memory 218928 kb
Host smart-9a80229f-89db-42ad-be62-471a2fc7f79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746648532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1746648532
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.912304053
Short name T38
Test name
Test status
Simulation time 29230818 ps
CPU time 1.01 seconds
Started Jul 28 05:36:56 PM PDT 24
Finished Jul 28 05:36:57 PM PDT 24
Peak memory 215408 kb
Host smart-f3ad47ab-43fc-446a-8e7f-66e1612d4c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912304053 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.912304053
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.4118664090
Short name T75
Test name
Test status
Simulation time 16803994 ps
CPU time 0.95 seconds
Started Jul 28 05:36:57 PM PDT 24
Finished Jul 28 05:36:58 PM PDT 24
Peak memory 215088 kb
Host smart-ea6dfd7c-eee2-453c-be34-8226301846a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118664090 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.4118664090
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2559172838
Short name T397
Test name
Test status
Simulation time 547954753 ps
CPU time 5.61 seconds
Started Jul 28 05:36:57 PM PDT 24
Finished Jul 28 05:37:03 PM PDT 24
Peak memory 215352 kb
Host smart-afd06470-af0f-44a5-8b5c-0c1400b7b183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559172838 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2559172838
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3748421351
Short name T862
Test name
Test status
Simulation time 60723243223 ps
CPU time 1497.78 seconds
Started Jul 28 05:36:57 PM PDT 24
Finished Jul 28 06:01:55 PM PDT 24
Peak memory 223748 kb
Host smart-22e10d75-9194-4f40-96b5-23173e304065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748421351 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3748421351
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.443090387
Short name T233
Test name
Test status
Simulation time 25153804 ps
CPU time 1.19 seconds
Started Jul 28 05:38:34 PM PDT 24
Finished Jul 28 05:38:35 PM PDT 24
Peak memory 219104 kb
Host smart-0834fca3-0081-4d95-a217-cc734d5469af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443090387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.443090387
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1594178048
Short name T767
Test name
Test status
Simulation time 118543001 ps
CPU time 1.15 seconds
Started Jul 28 05:38:34 PM PDT 24
Finished Jul 28 05:38:35 PM PDT 24
Peak memory 217124 kb
Host smart-ca3e1058-06c4-42e3-b0c0-288d3ec23d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594178048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1594178048
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3043105285
Short name T31
Test name
Test status
Simulation time 152021992 ps
CPU time 1.5 seconds
Started Jul 28 05:38:34 PM PDT 24
Finished Jul 28 05:38:35 PM PDT 24
Peak memory 217488 kb
Host smart-0f364707-4824-4877-95e5-a2ddcccc5615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043105285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3043105285
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.1528335984
Short name T514
Test name
Test status
Simulation time 108250638 ps
CPU time 1.24 seconds
Started Jul 28 05:38:44 PM PDT 24
Finished Jul 28 05:38:46 PM PDT 24
Peak memory 218316 kb
Host smart-0bde19c5-bac1-43c3-9393-80bf8465c6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528335984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1528335984
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.1599821124
Short name T302
Test name
Test status
Simulation time 46713062 ps
CPU time 1.75 seconds
Started Jul 28 05:38:32 PM PDT 24
Finished Jul 28 05:38:34 PM PDT 24
Peak memory 218256 kb
Host smart-cad1734c-371c-4567-b117-43984f8fc555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599821124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1599821124
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.611776603
Short name T884
Test name
Test status
Simulation time 29743541 ps
CPU time 1.3 seconds
Started Jul 28 05:38:34 PM PDT 24
Finished Jul 28 05:38:35 PM PDT 24
Peak memory 215488 kb
Host smart-08f11b1b-fbea-48f7-abfe-425a908138aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611776603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.611776603
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3135800443
Short name T601
Test name
Test status
Simulation time 80547744 ps
CPU time 1.6 seconds
Started Jul 28 05:38:32 PM PDT 24
Finished Jul 28 05:38:33 PM PDT 24
Peak memory 218580 kb
Host smart-3ce5a7a1-d5d0-4986-9901-d030538dd87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135800443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3135800443
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.4235556569
Short name T687
Test name
Test status
Simulation time 67762352 ps
CPU time 1.18 seconds
Started Jul 28 05:38:33 PM PDT 24
Finished Jul 28 05:38:34 PM PDT 24
Peak memory 215464 kb
Host smart-ec9e9fff-53a6-47f9-9b3b-f9dc889f4c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235556569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.4235556569
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3703956347
Short name T906
Test name
Test status
Simulation time 49057623 ps
CPU time 1.96 seconds
Started Jul 28 05:38:31 PM PDT 24
Finished Jul 28 05:38:33 PM PDT 24
Peak memory 218420 kb
Host smart-440b714b-8ee3-4ff6-8d49-f8be34fce777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703956347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3703956347
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.689411865
Short name T158
Test name
Test status
Simulation time 79720752 ps
CPU time 1.27 seconds
Started Jul 28 05:38:32 PM PDT 24
Finished Jul 28 05:38:33 PM PDT 24
Peak memory 219520 kb
Host smart-be95ba79-9d70-4872-bbb4-988cfaf0371e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689411865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.689411865
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.1997435925
Short name T402
Test name
Test status
Simulation time 66455435 ps
CPU time 2.08 seconds
Started Jul 28 05:38:35 PM PDT 24
Finished Jul 28 05:38:37 PM PDT 24
Peak memory 219884 kb
Host smart-7394a9df-cbd4-44fb-ab42-de6ca18a250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997435925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1997435925
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.3253494258
Short name T854
Test name
Test status
Simulation time 31484060 ps
CPU time 1.34 seconds
Started Jul 28 05:38:34 PM PDT 24
Finished Jul 28 05:38:35 PM PDT 24
Peak memory 219624 kb
Host smart-b24ebe2c-7d3d-462f-9970-b78440806256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253494258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.3253494258
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.3715789453
Short name T882
Test name
Test status
Simulation time 62971135 ps
CPU time 1.09 seconds
Started Jul 28 05:38:32 PM PDT 24
Finished Jul 28 05:38:34 PM PDT 24
Peak memory 217320 kb
Host smart-1f0a0369-07ef-4b62-a180-203bc9939c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715789453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3715789453
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.2504002827
Short name T450
Test name
Test status
Simulation time 37057608 ps
CPU time 1.13 seconds
Started Jul 28 05:38:33 PM PDT 24
Finished Jul 28 05:38:35 PM PDT 24
Peak memory 219588 kb
Host smart-6a91c164-676c-435f-ac00-e90a5edea12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504002827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2504002827
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.3750062770
Short name T582
Test name
Test status
Simulation time 44494915 ps
CPU time 1.84 seconds
Started Jul 28 05:38:30 PM PDT 24
Finished Jul 28 05:38:32 PM PDT 24
Peak memory 218356 kb
Host smart-622f98ba-9870-4d7d-9cf7-3caeeb5800d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750062770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3750062770
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.377425927
Short name T952
Test name
Test status
Simulation time 23713952 ps
CPU time 1.15 seconds
Started Jul 28 05:38:37 PM PDT 24
Finished Jul 28 05:38:38 PM PDT 24
Peak memory 218448 kb
Host smart-fd4f134e-2133-4cf6-8ada-e596770d312b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377425927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.377425927
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.562115918
Short name T793
Test name
Test status
Simulation time 50210431 ps
CPU time 1.23 seconds
Started Jul 28 05:38:38 PM PDT 24
Finished Jul 28 05:38:39 PM PDT 24
Peak memory 215168 kb
Host smart-0be20543-68d4-4006-8c84-f9a8d74352b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562115918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.562115918
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.1706749437
Short name T637
Test name
Test status
Simulation time 27480090 ps
CPU time 1.28 seconds
Started Jul 28 05:38:41 PM PDT 24
Finished Jul 28 05:38:42 PM PDT 24
Peak memory 218500 kb
Host smart-d75741bf-d7cd-43a1-8cc6-1965f618636c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706749437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1706749437
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.2345968305
Short name T393
Test name
Test status
Simulation time 110757997 ps
CPU time 1.28 seconds
Started Jul 28 05:38:38 PM PDT 24
Finished Jul 28 05:38:40 PM PDT 24
Peak memory 217184 kb
Host smart-6ecbdfba-f5ff-4a02-9174-9362993fcf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345968305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2345968305
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.1851015081
Short name T533
Test name
Test status
Simulation time 57533011 ps
CPU time 0.97 seconds
Started Jul 28 05:37:05 PM PDT 24
Finished Jul 28 05:37:06 PM PDT 24
Peak memory 206616 kb
Host smart-bbd0401f-fa63-4af9-864a-bd89f5c14cc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851015081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1851015081
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1858993683
Short name T384
Test name
Test status
Simulation time 67110210 ps
CPU time 0.94 seconds
Started Jul 28 05:37:06 PM PDT 24
Finished Jul 28 05:37:07 PM PDT 24
Peak memory 216108 kb
Host smart-be6505b3-7e03-44f7-aef0-01d2f5b20287
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858993683 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1858993683
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2453512864
Short name T520
Test name
Test status
Simulation time 45773093 ps
CPU time 1.17 seconds
Started Jul 28 05:37:03 PM PDT 24
Finished Jul 28 05:37:04 PM PDT 24
Peak memory 216824 kb
Host smart-3f3a3252-3733-4e23-8c96-c044284b0cbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453512864 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2453512864
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_genbits.970301702
Short name T379
Test name
Test status
Simulation time 91533012 ps
CPU time 1.35 seconds
Started Jul 28 05:36:59 PM PDT 24
Finished Jul 28 05:37:01 PM PDT 24
Peak memory 218376 kb
Host smart-31d60512-ef7c-46ee-9505-c9c9d0301034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970301702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.970301702
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1580387571
Short name T428
Test name
Test status
Simulation time 21078151 ps
CPU time 1.09 seconds
Started Jul 28 05:37:05 PM PDT 24
Finished Jul 28 05:37:06 PM PDT 24
Peak memory 215408 kb
Host smart-3cc5bdcb-f031-40ce-bbca-6c5a161c297e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580387571 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1580387571
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2301627901
Short name T313
Test name
Test status
Simulation time 18792435 ps
CPU time 1 seconds
Started Jul 28 05:37:00 PM PDT 24
Finished Jul 28 05:37:01 PM PDT 24
Peak memory 206944 kb
Host smart-f6ba8d84-a344-40b5-a00b-e0a2d717b664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301627901 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2301627901
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3716344605
Short name T861
Test name
Test status
Simulation time 162943034 ps
CPU time 1.54 seconds
Started Jul 28 05:36:57 PM PDT 24
Finished Jul 28 05:36:58 PM PDT 24
Peak memory 215200 kb
Host smart-9c281f51-7de7-49bd-a5ed-ddb9b0c86444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716344605 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3716344605
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3991323126
Short name T953
Test name
Test status
Simulation time 625683196319 ps
CPU time 1097.97 seconds
Started Jul 28 05:36:55 PM PDT 24
Finished Jul 28 05:55:13 PM PDT 24
Peak memory 221544 kb
Host smart-6476b73e-a2da-4528-b75f-8602320b3347
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991323126 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3991323126
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.1316728724
Short name T301
Test name
Test status
Simulation time 255748301 ps
CPU time 1.43 seconds
Started Jul 28 05:38:37 PM PDT 24
Finished Jul 28 05:38:38 PM PDT 24
Peak memory 218432 kb
Host smart-bcfc22ab-b581-4ae0-92e2-209958bff622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316728724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1316728724
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.719391743
Short name T332
Test name
Test status
Simulation time 184664027 ps
CPU time 1.83 seconds
Started Jul 28 05:38:37 PM PDT 24
Finished Jul 28 05:38:39 PM PDT 24
Peak memory 218680 kb
Host smart-0a319b16-5b3a-4af0-baf0-5b6d069cc159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719391743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.719391743
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.3920900692
Short name T165
Test name
Test status
Simulation time 23305108 ps
CPU time 1.27 seconds
Started Jul 28 05:38:38 PM PDT 24
Finished Jul 28 05:38:40 PM PDT 24
Peak memory 218596 kb
Host smart-fb867162-d638-4fba-b45d-76e619b4163e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920900692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.3920900692
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.3620385744
Short name T893
Test name
Test status
Simulation time 65528437 ps
CPU time 1.12 seconds
Started Jul 28 05:38:40 PM PDT 24
Finished Jul 28 05:38:41 PM PDT 24
Peak memory 217304 kb
Host smart-d37023bc-2c55-4c0e-8871-72d801b65fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620385744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3620385744
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3804912471
Short name T802
Test name
Test status
Simulation time 27554308 ps
CPU time 1.26 seconds
Started Jul 28 05:38:43 PM PDT 24
Finished Jul 28 05:38:44 PM PDT 24
Peak memory 218504 kb
Host smart-a9efde02-8db2-4c3e-a802-474aea3ab4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804912471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3804912471
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.281343152
Short name T770
Test name
Test status
Simulation time 145275645 ps
CPU time 1.29 seconds
Started Jul 28 05:38:37 PM PDT 24
Finished Jul 28 05:38:38 PM PDT 24
Peak memory 217308 kb
Host smart-b7fab1ff-940d-4f4e-90b0-16067d4be5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281343152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.281343152
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.3713576884
Short name T229
Test name
Test status
Simulation time 24150019 ps
CPU time 1.17 seconds
Started Jul 28 05:38:36 PM PDT 24
Finished Jul 28 05:38:38 PM PDT 24
Peak memory 220908 kb
Host smart-31398acd-861a-414a-8411-f8fee57117d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713576884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.3713576884
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/144.edn_alert.2166236312
Short name T500
Test name
Test status
Simulation time 123605392 ps
CPU time 1.24 seconds
Started Jul 28 05:38:36 PM PDT 24
Finished Jul 28 05:38:38 PM PDT 24
Peak memory 219648 kb
Host smart-5c7bc2df-f81b-4d6a-a09a-c184bb3509c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166236312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.2166236312
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.2214204823
Short name T606
Test name
Test status
Simulation time 120625685 ps
CPU time 1.78 seconds
Started Jul 28 05:38:38 PM PDT 24
Finished Jul 28 05:38:40 PM PDT 24
Peak memory 220216 kb
Host smart-59c3697d-33b1-477d-9dea-7977a4859168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214204823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2214204823
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2645737306
Short name T933
Test name
Test status
Simulation time 29436230 ps
CPU time 1.26 seconds
Started Jul 28 05:38:36 PM PDT 24
Finished Jul 28 05:38:38 PM PDT 24
Peak memory 218312 kb
Host smart-23d6aaae-7683-43bd-afcb-549d6761aa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645737306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2645737306
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.1978994727
Short name T809
Test name
Test status
Simulation time 24566424 ps
CPU time 1.23 seconds
Started Jul 28 05:38:37 PM PDT 24
Finished Jul 28 05:38:38 PM PDT 24
Peak memory 218336 kb
Host smart-5cb74c16-7a8a-4ebb-a996-6c904a3f13bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978994727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1978994727
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.693556180
Short name T694
Test name
Test status
Simulation time 21578564 ps
CPU time 1.14 seconds
Started Jul 28 05:38:37 PM PDT 24
Finished Jul 28 05:38:39 PM PDT 24
Peak memory 219356 kb
Host smart-0f9de570-9477-4ef9-9b6a-a57b296d50f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693556180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.693556180
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2045402673
Short name T485
Test name
Test status
Simulation time 57210100 ps
CPU time 1.49 seconds
Started Jul 28 05:38:37 PM PDT 24
Finished Jul 28 05:38:38 PM PDT 24
Peak memory 217348 kb
Host smart-e3663a72-d481-4c0a-a7ac-e8c56e5828ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045402673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2045402673
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.689964601
Short name T189
Test name
Test status
Simulation time 61475341 ps
CPU time 1.06 seconds
Started Jul 28 05:38:53 PM PDT 24
Finished Jul 28 05:38:54 PM PDT 24
Peak memory 218396 kb
Host smart-f05af995-d6e2-41f3-a0bd-b4abb2393448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689964601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.689964601
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3795045530
Short name T902
Test name
Test status
Simulation time 56635904 ps
CPU time 1.5 seconds
Started Jul 28 05:38:40 PM PDT 24
Finished Jul 28 05:38:42 PM PDT 24
Peak memory 218504 kb
Host smart-e10bf4bc-b35d-4938-837d-13f4a8eb2416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795045530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3795045530
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.2165585417
Short name T656
Test name
Test status
Simulation time 200881302 ps
CPU time 1.36 seconds
Started Jul 28 05:38:43 PM PDT 24
Finished Jul 28 05:38:45 PM PDT 24
Peak memory 219456 kb
Host smart-89f79f9b-d5c5-46a5-97fb-dc4b331ff5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165585417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.2165585417
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.293319161
Short name T697
Test name
Test status
Simulation time 36189524 ps
CPU time 1.44 seconds
Started Jul 28 05:38:42 PM PDT 24
Finished Jul 28 05:38:43 PM PDT 24
Peak memory 217516 kb
Host smart-26a6d3d3-84e2-49cd-9680-ce7853a7c34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293319161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.293319161
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3658433081
Short name T266
Test name
Test status
Simulation time 31339814 ps
CPU time 1.33 seconds
Started Jul 28 05:38:53 PM PDT 24
Finished Jul 28 05:38:54 PM PDT 24
Peak memory 219224 kb
Host smart-b80a6283-79de-4fd7-9b48-d9cd410fd6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658433081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3658433081
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.1366546154
Short name T732
Test name
Test status
Simulation time 50663844 ps
CPU time 1.76 seconds
Started Jul 28 05:38:45 PM PDT 24
Finished Jul 28 05:38:47 PM PDT 24
Peak memory 218564 kb
Host smart-95be8c6e-d503-4c0f-bd0c-3ac9ad9657dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366546154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1366546154
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.651084781
Short name T228
Test name
Test status
Simulation time 62509196 ps
CPU time 1.17 seconds
Started Jul 28 05:37:02 PM PDT 24
Finished Jul 28 05:37:04 PM PDT 24
Peak memory 219596 kb
Host smart-0806cf95-99f9-43c3-8da3-bad66fbfad27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651084781 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.651084781
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3821445695
Short name T486
Test name
Test status
Simulation time 35066870 ps
CPU time 0.92 seconds
Started Jul 28 05:37:02 PM PDT 24
Finished Jul 28 05:37:03 PM PDT 24
Peak memory 215084 kb
Host smart-5fd850c0-2619-43b7-939b-a2972a7e9c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821445695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3821445695
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.229100593
Short name T199
Test name
Test status
Simulation time 83625367 ps
CPU time 1.01 seconds
Started Jul 28 05:37:02 PM PDT 24
Finished Jul 28 05:37:04 PM PDT 24
Peak memory 216848 kb
Host smart-9b80cbb0-ae0f-4c8a-a1c0-8d316e1bb1f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229100593 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.229100593
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.396387446
Short name T52
Test name
Test status
Simulation time 24159986 ps
CPU time 1.3 seconds
Started Jul 28 05:37:04 PM PDT 24
Finished Jul 28 05:37:05 PM PDT 24
Peak memory 223892 kb
Host smart-a5295f11-837c-40a5-8059-1788c994d5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396387446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.396387446
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.4010151851
Short name T556
Test name
Test status
Simulation time 88782067 ps
CPU time 1.14 seconds
Started Jul 28 05:37:04 PM PDT 24
Finished Jul 28 05:37:05 PM PDT 24
Peak memory 217216 kb
Host smart-610feea5-e484-462b-ac38-76466cf8450a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010151851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.4010151851
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.3753616091
Short name T447
Test name
Test status
Simulation time 36487362 ps
CPU time 0.88 seconds
Started Jul 28 05:37:02 PM PDT 24
Finished Jul 28 05:37:03 PM PDT 24
Peak memory 215132 kb
Host smart-ff1ddc1c-7443-471e-a027-39cdf5be0aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753616091 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3753616091
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3367005159
Short name T945
Test name
Test status
Simulation time 146122960 ps
CPU time 2.1 seconds
Started Jul 28 05:37:02 PM PDT 24
Finished Jul 28 05:37:04 PM PDT 24
Peak memory 215200 kb
Host smart-45940db7-b3f4-40fd-aade-a68dde166b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367005159 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3367005159
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3371889157
Short name T254
Test name
Test status
Simulation time 732477224184 ps
CPU time 1782.92 seconds
Started Jul 28 05:37:04 PM PDT 24
Finished Jul 28 06:06:47 PM PDT 24
Peak memory 236816 kb
Host smart-b4de65b8-8a95-4691-84d4-fea177a068f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371889157 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3371889157
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2212666190
Short name T316
Test name
Test status
Simulation time 65929117 ps
CPU time 0.99 seconds
Started Jul 28 05:38:46 PM PDT 24
Finished Jul 28 05:38:47 PM PDT 24
Peak memory 218324 kb
Host smart-45deafbb-56d6-4cee-bfbb-73fa5b216b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212666190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2212666190
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.1217185970
Short name T752
Test name
Test status
Simulation time 120249934 ps
CPU time 1.22 seconds
Started Jul 28 05:38:43 PM PDT 24
Finished Jul 28 05:38:45 PM PDT 24
Peak memory 217336 kb
Host smart-12e2fb51-5525-4f33-a98f-ed932b7935aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217185970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1217185970
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.1371675489
Short name T773
Test name
Test status
Simulation time 29655412 ps
CPU time 1.3 seconds
Started Jul 28 05:38:41 PM PDT 24
Finished Jul 28 05:38:43 PM PDT 24
Peak memory 215548 kb
Host smart-20d5f905-9519-4678-8d5b-bf8c7785c310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371675489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1371675489
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.247717989
Short name T522
Test name
Test status
Simulation time 39859054 ps
CPU time 1.61 seconds
Started Jul 28 05:38:40 PM PDT 24
Finished Jul 28 05:38:42 PM PDT 24
Peak memory 217488 kb
Host smart-91044ca1-929b-4a3d-bac4-45460909da57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247717989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.247717989
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.1693274557
Short name T37
Test name
Test status
Simulation time 52930692 ps
CPU time 1.28 seconds
Started Jul 28 05:38:53 PM PDT 24
Finished Jul 28 05:38:54 PM PDT 24
Peak memory 219620 kb
Host smart-882777f6-8999-4883-95f0-e7f65cf70377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693274557 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.1693274557
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.108271616
Short name T886
Test name
Test status
Simulation time 92067040 ps
CPU time 1.08 seconds
Started Jul 28 05:38:42 PM PDT 24
Finished Jul 28 05:38:44 PM PDT 24
Peak memory 217272 kb
Host smart-479068cc-6fdc-4e85-9b64-8c6a13d7b752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108271616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.108271616
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.3783930877
Short name T888
Test name
Test status
Simulation time 40782462 ps
CPU time 1.17 seconds
Started Jul 28 05:38:53 PM PDT 24
Finished Jul 28 05:38:54 PM PDT 24
Peak memory 218580 kb
Host smart-9433f65a-f1f6-4065-8260-2a5157677463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783930877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3783930877
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.2761046818
Short name T801
Test name
Test status
Simulation time 41200610 ps
CPU time 1.54 seconds
Started Jul 28 05:38:45 PM PDT 24
Finished Jul 28 05:38:47 PM PDT 24
Peak memory 218332 kb
Host smart-70a920a0-3b17-4dc9-a3ca-c92ed460f0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761046818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2761046818
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.2609840358
Short name T586
Test name
Test status
Simulation time 106795952 ps
CPU time 1.08 seconds
Started Jul 28 05:38:47 PM PDT 24
Finished Jul 28 05:38:48 PM PDT 24
Peak memory 218524 kb
Host smart-cb01aa4e-52e3-4db2-adf2-85bf8e2d858c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609840358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.2609840358
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.4251402656
Short name T400
Test name
Test status
Simulation time 53131105 ps
CPU time 1.19 seconds
Started Jul 28 05:38:46 PM PDT 24
Finished Jul 28 05:38:47 PM PDT 24
Peak memory 217208 kb
Host smart-bce001af-68ee-49bc-8a75-a241ee460b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251402656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.4251402656
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.782193862
Short name T296
Test name
Test status
Simulation time 60131814 ps
CPU time 1.29 seconds
Started Jul 28 05:38:48 PM PDT 24
Finished Jul 28 05:38:49 PM PDT 24
Peak memory 220288 kb
Host smart-12845cbe-af55-4892-8d23-4932649e460c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782193862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.782193862
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1571362176
Short name T705
Test name
Test status
Simulation time 37015791 ps
CPU time 1.44 seconds
Started Jul 28 05:38:48 PM PDT 24
Finished Jul 28 05:38:49 PM PDT 24
Peak memory 219644 kb
Host smart-0df2c2fb-d4df-4d04-a4cc-6f0d6435ee5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571362176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1571362176
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.4097798275
Short name T700
Test name
Test status
Simulation time 27471897 ps
CPU time 1.3 seconds
Started Jul 28 05:38:48 PM PDT 24
Finished Jul 28 05:38:49 PM PDT 24
Peak memory 218464 kb
Host smart-582650e4-4491-4a50-b3f3-d9e96350d7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097798275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.4097798275
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.799738245
Short name T715
Test name
Test status
Simulation time 44954729 ps
CPU time 1.25 seconds
Started Jul 28 05:38:49 PM PDT 24
Finished Jul 28 05:38:51 PM PDT 24
Peak memory 218236 kb
Host smart-8552923a-5313-4698-b748-5f525e5b02b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799738245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.799738245
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.2652747405
Short name T796
Test name
Test status
Simulation time 29539733 ps
CPU time 1.37 seconds
Started Jul 28 05:38:45 PM PDT 24
Finished Jul 28 05:38:47 PM PDT 24
Peak memory 215472 kb
Host smart-957e63ca-a691-48f0-8747-88ba899c2b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652747405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.2652747405
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/158.edn_alert.781925975
Short name T210
Test name
Test status
Simulation time 23497836 ps
CPU time 1.18 seconds
Started Jul 28 05:38:49 PM PDT 24
Finished Jul 28 05:38:50 PM PDT 24
Peak memory 219824 kb
Host smart-c74a53e1-cfcf-4114-a0ed-d3012a1a76ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781925975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.781925975
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1821750229
Short name T484
Test name
Test status
Simulation time 139605643 ps
CPU time 1.7 seconds
Started Jul 28 05:38:47 PM PDT 24
Finished Jul 28 05:38:49 PM PDT 24
Peak memory 219828 kb
Host smart-c08943bd-46be-4eb6-ae04-6d8adfdbea98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821750229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1821750229
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.218540801
Short name T512
Test name
Test status
Simulation time 45402961 ps
CPU time 1.23 seconds
Started Jul 28 05:38:47 PM PDT 24
Finished Jul 28 05:38:48 PM PDT 24
Peak memory 219008 kb
Host smart-02c0c38d-1de7-43a8-b0d3-d1dac9bd1bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218540801 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.218540801
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.627927828
Short name T327
Test name
Test status
Simulation time 43717203 ps
CPU time 1.5 seconds
Started Jul 28 05:38:49 PM PDT 24
Finished Jul 28 05:38:51 PM PDT 24
Peak memory 219828 kb
Host smart-270187a3-f768-46c7-a348-e2c154aa496f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627927828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.627927828
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3804165850
Short name T184
Test name
Test status
Simulation time 43598412 ps
CPU time 1.15 seconds
Started Jul 28 05:37:02 PM PDT 24
Finished Jul 28 05:37:03 PM PDT 24
Peak memory 218464 kb
Host smart-60621c3f-d20f-4708-86f7-fa681a1539f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804165850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3804165850
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3318170208
Short name T650
Test name
Test status
Simulation time 41128977 ps
CPU time 0.94 seconds
Started Jul 28 05:37:02 PM PDT 24
Finished Jul 28 05:37:04 PM PDT 24
Peak memory 214820 kb
Host smart-6cdb6704-86e8-445e-ba0c-f1732c83279f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318170208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3318170208
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3460526515
Short name T216
Test name
Test status
Simulation time 23025815 ps
CPU time 0.92 seconds
Started Jul 28 05:37:05 PM PDT 24
Finished Jul 28 05:37:06 PM PDT 24
Peak memory 216116 kb
Host smart-b0c2d732-2443-403a-a22e-d9845bc5521e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460526515 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3460526515
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2425341302
Short name T858
Test name
Test status
Simulation time 100370390 ps
CPU time 1.24 seconds
Started Jul 28 05:37:01 PM PDT 24
Finished Jul 28 05:37:03 PM PDT 24
Peak memory 216656 kb
Host smart-092bf143-f5c4-4eca-8d7b-635da4d8c824
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425341302 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2425341302
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1822799109
Short name T211
Test name
Test status
Simulation time 23525775 ps
CPU time 0.94 seconds
Started Jul 28 05:37:01 PM PDT 24
Finished Jul 28 05:37:02 PM PDT 24
Peak memory 223560 kb
Host smart-09e5935b-cf5a-4143-bd1f-91de6e1807b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822799109 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1822799109
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2888184129
Short name T879
Test name
Test status
Simulation time 59799823 ps
CPU time 1.34 seconds
Started Jul 28 05:37:05 PM PDT 24
Finished Jul 28 05:37:07 PM PDT 24
Peak memory 218368 kb
Host smart-0ae6eb0f-fc71-4fa0-adb5-e55f1fd539eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888184129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2888184129
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_smoke.3317606033
Short name T772
Test name
Test status
Simulation time 15337359 ps
CPU time 1.06 seconds
Started Jul 28 05:37:02 PM PDT 24
Finished Jul 28 05:37:04 PM PDT 24
Peak memory 215280 kb
Host smart-9946f36c-1e98-45b1-8333-0018512f53f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317606033 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3317606033
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1650714623
Short name T341
Test name
Test status
Simulation time 317523887 ps
CPU time 5.18 seconds
Started Jul 28 05:37:03 PM PDT 24
Finished Jul 28 05:37:08 PM PDT 24
Peak memory 217280 kb
Host smart-b4c5db33-4fb7-483e-b565-9857860f2c97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650714623 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1650714623
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.923455032
Short name T495
Test name
Test status
Simulation time 85636390062 ps
CPU time 748.33 seconds
Started Jul 28 05:37:02 PM PDT 24
Finished Jul 28 05:49:31 PM PDT 24
Peak memory 223612 kb
Host smart-431e4729-7022-4393-bd09-d5a3ba09f141
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923455032 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.923455032
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.799459703
Short name T846
Test name
Test status
Simulation time 33297536 ps
CPU time 1.38 seconds
Started Jul 28 05:38:45 PM PDT 24
Finished Jul 28 05:38:47 PM PDT 24
Peak memory 220588 kb
Host smart-a471c641-4b46-4e69-b05f-9db640630ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799459703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.799459703
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.820888495
Short name T786
Test name
Test status
Simulation time 309253077 ps
CPU time 1.2 seconds
Started Jul 28 05:38:47 PM PDT 24
Finished Jul 28 05:38:49 PM PDT 24
Peak memory 215152 kb
Host smart-48ba1b38-37d5-4e8d-b000-35c4219bc7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820888495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.820888495
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.1734578088
Short name T589
Test name
Test status
Simulation time 78929857 ps
CPU time 1.2 seconds
Started Jul 28 05:38:49 PM PDT 24
Finished Jul 28 05:38:51 PM PDT 24
Peak memory 218520 kb
Host smart-26383a8a-9e18-463b-aefd-712f21264feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734578088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.1734578088
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.51294237
Short name T367
Test name
Test status
Simulation time 283686898 ps
CPU time 2.64 seconds
Started Jul 28 05:38:54 PM PDT 24
Finished Jul 28 05:38:57 PM PDT 24
Peak memory 219528 kb
Host smart-4fc65af5-40a4-416b-83cb-971aa3af1134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51294237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.51294237
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.149660194
Short name T415
Test name
Test status
Simulation time 33882882 ps
CPU time 1.07 seconds
Started Jul 28 05:38:54 PM PDT 24
Finished Jul 28 05:38:55 PM PDT 24
Peak memory 218568 kb
Host smart-c1183209-ba6f-437b-bb87-4228e51d2e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149660194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.149660194
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.1115127613
Short name T356
Test name
Test status
Simulation time 36886444 ps
CPU time 1.6 seconds
Started Jul 28 05:38:50 PM PDT 24
Finished Jul 28 05:38:52 PM PDT 24
Peak memory 217244 kb
Host smart-10d9d0c3-8eb6-4037-bedd-c3d0904af3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115127613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1115127613
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1762516555
Short name T268
Test name
Test status
Simulation time 51606987 ps
CPU time 1.25 seconds
Started Jul 28 05:38:50 PM PDT 24
Finished Jul 28 05:38:51 PM PDT 24
Peak memory 220072 kb
Host smart-056f8873-772e-4c67-9f3d-b70c7f0056cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762516555 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1762516555
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.3890337469
Short name T980
Test name
Test status
Simulation time 22156415 ps
CPU time 1.1 seconds
Started Jul 28 05:38:59 PM PDT 24
Finished Jul 28 05:39:00 PM PDT 24
Peak memory 218348 kb
Host smart-9dbd5219-ff62-4398-89e0-696d9bc676f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890337469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3890337469
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.3993879839
Short name T584
Test name
Test status
Simulation time 62012965 ps
CPU time 1.28 seconds
Started Jul 28 05:38:58 PM PDT 24
Finished Jul 28 05:38:59 PM PDT 24
Peak memory 217136 kb
Host smart-a45469c1-4ccc-48a1-98b7-aae8d4860a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993879839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3993879839
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3062546774
Short name T524
Test name
Test status
Simulation time 86288765 ps
CPU time 1.22 seconds
Started Jul 28 05:38:53 PM PDT 24
Finished Jul 28 05:38:54 PM PDT 24
Peak memory 215552 kb
Host smart-111416f1-b555-4727-8905-a8e4542faa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062546774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3062546774
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3430897928
Short name T759
Test name
Test status
Simulation time 63562073 ps
CPU time 1.42 seconds
Started Jul 28 05:38:51 PM PDT 24
Finished Jul 28 05:38:52 PM PDT 24
Peak memory 215272 kb
Host smart-eab30a4e-238b-4763-89d4-69fe811193ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430897928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3430897928
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.2252580550
Short name T671
Test name
Test status
Simulation time 103197130 ps
CPU time 1.34 seconds
Started Jul 28 05:39:02 PM PDT 24
Finished Jul 28 05:39:04 PM PDT 24
Peak memory 219788 kb
Host smart-03e90da5-6914-4001-84be-a61976c729fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252580550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2252580550
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.2081748793
Short name T894
Test name
Test status
Simulation time 53916018 ps
CPU time 1.97 seconds
Started Jul 28 05:38:59 PM PDT 24
Finished Jul 28 05:39:01 PM PDT 24
Peak memory 215184 kb
Host smart-1ae9cb6e-30bf-4981-afab-7d22213b3614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081748793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2081748793
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2268398989
Short name T874
Test name
Test status
Simulation time 33796711 ps
CPU time 1.26 seconds
Started Jul 28 05:38:51 PM PDT 24
Finished Jul 28 05:38:52 PM PDT 24
Peak memory 218400 kb
Host smart-5d28ac4c-bbe9-4d3f-b02e-88210b981624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268398989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2268398989
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.3819684522
Short name T417
Test name
Test status
Simulation time 55655861 ps
CPU time 1.05 seconds
Started Jul 28 05:39:03 PM PDT 24
Finished Jul 28 05:39:04 PM PDT 24
Peak memory 217356 kb
Host smart-c5425738-cfa7-42ce-b643-55fa1122b9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819684522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3819684522
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.1304553855
Short name T159
Test name
Test status
Simulation time 42154645 ps
CPU time 1.19 seconds
Started Jul 28 05:39:00 PM PDT 24
Finished Jul 28 05:39:02 PM PDT 24
Peak memory 218668 kb
Host smart-42e82aa0-5403-4b9d-a3db-dd873d58ec39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304553855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1304553855
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.2387419998
Short name T954
Test name
Test status
Simulation time 152963992 ps
CPU time 2.67 seconds
Started Jul 28 05:38:54 PM PDT 24
Finished Jul 28 05:38:57 PM PDT 24
Peak memory 219848 kb
Host smart-f3fd6d38-c01e-4577-a3df-b8df4597f5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387419998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2387419998
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2795493837
Short name T202
Test name
Test status
Simulation time 98464833 ps
CPU time 1.32 seconds
Started Jul 28 05:38:58 PM PDT 24
Finished Jul 28 05:38:59 PM PDT 24
Peak memory 215532 kb
Host smart-5af0a0bf-c0f7-45bb-bac3-b075a12639c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795493837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2795493837
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.3745383142
Short name T768
Test name
Test status
Simulation time 184636347 ps
CPU time 1.38 seconds
Started Jul 28 05:39:01 PM PDT 24
Finished Jul 28 05:39:02 PM PDT 24
Peak memory 218852 kb
Host smart-20690b3f-e743-42e1-b7e8-82629bbf8793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745383142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3745383142
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.368710938
Short name T433
Test name
Test status
Simulation time 92446729 ps
CPU time 1 seconds
Started Jul 28 05:37:11 PM PDT 24
Finished Jul 28 05:37:12 PM PDT 24
Peak memory 214632 kb
Host smart-8ed85307-2b4d-4dc9-8fce-90cf257632de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368710938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.368710938
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2410334828
Short name T138
Test name
Test status
Simulation time 21644509 ps
CPU time 1.01 seconds
Started Jul 28 05:37:03 PM PDT 24
Finished Jul 28 05:37:04 PM PDT 24
Peak memory 216120 kb
Host smart-34c63a6b-04b8-4bfd-bb72-5f4805c4f31b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410334828 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2410334828
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.636253473
Short name T108
Test name
Test status
Simulation time 81227777 ps
CPU time 1.03 seconds
Started Jul 28 05:37:04 PM PDT 24
Finished Jul 28 05:37:05 PM PDT 24
Peak memory 216728 kb
Host smart-3cea84b6-a1db-4e46-a473-b5625b4494fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636253473 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.636253473
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.2597599094
Short name T183
Test name
Test status
Simulation time 31138136 ps
CPU time 1.07 seconds
Started Jul 28 05:37:03 PM PDT 24
Finished Jul 28 05:37:04 PM PDT 24
Peak memory 219584 kb
Host smart-68638857-966d-4574-91bb-ed797df0e28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597599094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2597599094
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.2736053196
Short name T57
Test name
Test status
Simulation time 37710174 ps
CPU time 0.98 seconds
Started Jul 28 05:37:03 PM PDT 24
Finished Jul 28 05:37:04 PM PDT 24
Peak memory 215152 kb
Host smart-0d889afa-9893-427e-b00c-6fe70116be9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736053196 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2736053196
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3072733705
Short name T366
Test name
Test status
Simulation time 18481445 ps
CPU time 1.06 seconds
Started Jul 28 05:37:01 PM PDT 24
Finished Jul 28 05:37:02 PM PDT 24
Peak memory 215180 kb
Host smart-1d6cd7b7-95bb-4596-b590-3247eeaa0456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072733705 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3072733705
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1620745582
Short name T377
Test name
Test status
Simulation time 822557376 ps
CPU time 5.35 seconds
Started Jul 28 05:37:06 PM PDT 24
Finished Jul 28 05:37:11 PM PDT 24
Peak memory 217204 kb
Host smart-41f1009a-8222-4d00-b283-fcda1c1fe309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620745582 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1620745582
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1914536242
Short name T250
Test name
Test status
Simulation time 130486223044 ps
CPU time 1367.65 seconds
Started Jul 28 05:37:03 PM PDT 24
Finished Jul 28 05:59:51 PM PDT 24
Peak memory 223564 kb
Host smart-ab6a0032-7c0f-4417-a78c-7123b96adfc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914536242 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1914536242
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.330441108
Short name T937
Test name
Test status
Simulation time 45163125 ps
CPU time 1.18 seconds
Started Jul 28 05:38:59 PM PDT 24
Finished Jul 28 05:39:01 PM PDT 24
Peak memory 218300 kb
Host smart-3e9adaa5-0fe6-4a9d-b750-c08e587fe957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330441108 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.330441108
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1879701471
Short name T333
Test name
Test status
Simulation time 28134101 ps
CPU time 1.3 seconds
Started Jul 28 05:38:56 PM PDT 24
Finished Jul 28 05:38:57 PM PDT 24
Peak memory 219868 kb
Host smart-2e430817-a536-4157-8f0b-3961f9604952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879701471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1879701471
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.2965455166
Short name T446
Test name
Test status
Simulation time 47912830 ps
CPU time 1.24 seconds
Started Jul 28 05:38:57 PM PDT 24
Finished Jul 28 05:38:59 PM PDT 24
Peak memory 218788 kb
Host smart-47fb763b-1f96-47a2-9d73-f8350a7b9039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965455166 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2965455166
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.476123456
Short name T760
Test name
Test status
Simulation time 27243070 ps
CPU time 1.29 seconds
Started Jul 28 05:38:56 PM PDT 24
Finished Jul 28 05:38:57 PM PDT 24
Peak memory 215292 kb
Host smart-35071f3f-9bc0-4709-a4a9-ef9498542f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476123456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.476123456
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1853297279
Short name T607
Test name
Test status
Simulation time 32915559 ps
CPU time 1.27 seconds
Started Jul 28 05:38:57 PM PDT 24
Finished Jul 28 05:38:58 PM PDT 24
Peak memory 219388 kb
Host smart-cdf42ae3-ab97-4e6d-814b-2c2cd28089e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853297279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1853297279
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.1191565818
Short name T900
Test name
Test status
Simulation time 86268159 ps
CPU time 1.23 seconds
Started Jul 28 05:39:03 PM PDT 24
Finished Jul 28 05:39:04 PM PDT 24
Peak memory 217100 kb
Host smart-4d7b50da-6824-43e0-b3b6-02d24e9d9198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191565818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1191565818
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.631610669
Short name T315
Test name
Test status
Simulation time 26201360 ps
CPU time 1.25 seconds
Started Jul 28 05:39:04 PM PDT 24
Finished Jul 28 05:39:06 PM PDT 24
Peak memory 218620 kb
Host smart-16a42ae0-2804-4a09-943c-dfc451075795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631610669 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.631610669
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/174.edn_alert.2968566261
Short name T901
Test name
Test status
Simulation time 138422852 ps
CPU time 1.1 seconds
Started Jul 28 05:38:58 PM PDT 24
Finished Jul 28 05:38:59 PM PDT 24
Peak memory 218520 kb
Host smart-5968f628-735d-49fb-bacc-9e6ddb59003a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968566261 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.2968566261
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.2751353209
Short name T652
Test name
Test status
Simulation time 115126966 ps
CPU time 1.56 seconds
Started Jul 28 05:38:59 PM PDT 24
Finished Jul 28 05:39:01 PM PDT 24
Peak memory 218908 kb
Host smart-74c2c3f8-139a-4d18-a2ef-560bec795c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751353209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2751353209
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2909819563
Short name T775
Test name
Test status
Simulation time 41641325 ps
CPU time 1.18 seconds
Started Jul 28 05:39:00 PM PDT 24
Finished Jul 28 05:39:01 PM PDT 24
Peak memory 219228 kb
Host smart-02731fb9-078d-4e74-a4c0-f8c15ba733ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909819563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2909819563
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.287133025
Short name T808
Test name
Test status
Simulation time 85583031 ps
CPU time 1.38 seconds
Started Jul 28 05:39:03 PM PDT 24
Finished Jul 28 05:39:04 PM PDT 24
Peak memory 217280 kb
Host smart-3e4112cc-fb78-4368-8095-b941c1ed8fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287133025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.287133025
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.1680764136
Short name T739
Test name
Test status
Simulation time 22837222 ps
CPU time 1.25 seconds
Started Jul 28 05:39:03 PM PDT 24
Finished Jul 28 05:39:04 PM PDT 24
Peak memory 218556 kb
Host smart-14e93f4e-90bd-411d-822e-a1748a0e0eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680764136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.1680764136
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.4074187582
Short name T885
Test name
Test status
Simulation time 94112779 ps
CPU time 1.26 seconds
Started Jul 28 05:39:03 PM PDT 24
Finished Jul 28 05:39:04 PM PDT 24
Peak memory 219764 kb
Host smart-1ce5fcb5-95e5-4b42-8089-5e5374429392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074187582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.4074187582
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.3589226488
Short name T472
Test name
Test status
Simulation time 32050018 ps
CPU time 1.34 seconds
Started Jul 28 05:39:03 PM PDT 24
Finished Jul 28 05:39:05 PM PDT 24
Peak memory 219844 kb
Host smart-2e46a385-c517-4381-b2f7-2fc584198c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589226488 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3589226488
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.2234803093
Short name T68
Test name
Test status
Simulation time 77417294 ps
CPU time 1.27 seconds
Started Jul 28 05:39:03 PM PDT 24
Finished Jul 28 05:39:04 PM PDT 24
Peak memory 218740 kb
Host smart-5b60b0dd-8106-410c-8535-30b4672935c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234803093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2234803093
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.1349650619
Short name T269
Test name
Test status
Simulation time 67187372 ps
CPU time 1.27 seconds
Started Jul 28 05:39:01 PM PDT 24
Finished Jul 28 05:39:02 PM PDT 24
Peak memory 220264 kb
Host smart-cb0f37fe-b9c0-4ba7-9d69-b026b26d172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349650619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.1349650619
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.3501976151
Short name T621
Test name
Test status
Simulation time 49345709 ps
CPU time 1.31 seconds
Started Jul 28 05:39:04 PM PDT 24
Finished Jul 28 05:39:06 PM PDT 24
Peak memory 217076 kb
Host smart-f596f0a2-294a-4dd1-bfb0-99632199b3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501976151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3501976151
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2628201995
Short name T528
Test name
Test status
Simulation time 24942806 ps
CPU time 1.27 seconds
Started Jul 28 05:37:13 PM PDT 24
Finished Jul 28 05:37:14 PM PDT 24
Peak memory 218572 kb
Host smart-2de10f31-1e1f-4610-afea-1b3d5d3a193c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628201995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2628201995
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1921766020
Short name T451
Test name
Test status
Simulation time 79227766 ps
CPU time 1.08 seconds
Started Jul 28 05:37:08 PM PDT 24
Finished Jul 28 05:37:10 PM PDT 24
Peak memory 206708 kb
Host smart-b374ba9e-9df8-41ea-b17f-80e1396dc160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921766020 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1921766020
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1799086781
Short name T927
Test name
Test status
Simulation time 13533904 ps
CPU time 0.89 seconds
Started Jul 28 05:37:09 PM PDT 24
Finished Jul 28 05:37:10 PM PDT 24
Peak memory 215448 kb
Host smart-209c271d-65de-40c1-b807-5bcc2f00f827
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799086781 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1799086781
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.181961773
Short name T957
Test name
Test status
Simulation time 82361698 ps
CPU time 1.07 seconds
Started Jul 28 05:37:12 PM PDT 24
Finished Jul 28 05:37:13 PM PDT 24
Peak memory 218256 kb
Host smart-b6e14798-4c3e-44cb-861f-66c2b93a0b98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181961773 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.181961773
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1589303067
Short name T568
Test name
Test status
Simulation time 32265675 ps
CPU time 0.92 seconds
Started Jul 28 05:37:13 PM PDT 24
Finished Jul 28 05:37:15 PM PDT 24
Peak memory 218364 kb
Host smart-497c07a0-37ed-42a6-a52b-ceceb2faea31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589303067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1589303067
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.769279017
Short name T421
Test name
Test status
Simulation time 99661586 ps
CPU time 1.25 seconds
Started Jul 28 05:37:12 PM PDT 24
Finished Jul 28 05:37:14 PM PDT 24
Peak memory 217140 kb
Host smart-28f062bf-1334-4734-872a-2ef3e8713d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769279017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.769279017
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.2200441599
Short name T588
Test name
Test status
Simulation time 17077616 ps
CPU time 0.96 seconds
Started Jul 28 05:37:10 PM PDT 24
Finished Jul 28 05:37:11 PM PDT 24
Peak memory 215128 kb
Host smart-59abf518-a602-40b0-b34c-2b3d7e32cab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200441599 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2200441599
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3379635747
Short name T324
Test name
Test status
Simulation time 242585578 ps
CPU time 2.99 seconds
Started Jul 28 05:37:10 PM PDT 24
Finished Jul 28 05:37:13 PM PDT 24
Peak memory 215172 kb
Host smart-9d57d819-7e34-4299-9205-07bd394bcb19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379635747 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3379635747
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1447801275
Short name T627
Test name
Test status
Simulation time 89635007472 ps
CPU time 498.45 seconds
Started Jul 28 05:37:11 PM PDT 24
Finished Jul 28 05:45:29 PM PDT 24
Peak memory 219200 kb
Host smart-055d1d9f-f71c-4ec2-854a-b7e42eb9b550
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447801275 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1447801275
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.4285149192
Short name T93
Test name
Test status
Simulation time 36060416 ps
CPU time 1.07 seconds
Started Jul 28 05:39:07 PM PDT 24
Finished Jul 28 05:39:09 PM PDT 24
Peak memory 218308 kb
Host smart-61900115-20b1-43f1-862f-55678a73d4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285149192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.4285149192
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1756193431
Short name T633
Test name
Test status
Simulation time 72249964 ps
CPU time 1.14 seconds
Started Jul 28 05:39:03 PM PDT 24
Finished Jul 28 05:39:05 PM PDT 24
Peak memory 217140 kb
Host smart-000edeff-c995-4641-b96c-559a5dda3f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756193431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1756193431
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.3425326679
Short name T672
Test name
Test status
Simulation time 46052699 ps
CPU time 1.21 seconds
Started Jul 28 05:39:04 PM PDT 24
Finished Jul 28 05:39:05 PM PDT 24
Peak memory 220348 kb
Host smart-112db42e-318b-4608-b5be-c2eaa2e54e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425326679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.3425326679
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.588387179
Short name T555
Test name
Test status
Simulation time 184472237 ps
CPU time 2.29 seconds
Started Jul 28 05:39:02 PM PDT 24
Finished Jul 28 05:39:04 PM PDT 24
Peak memory 219876 kb
Host smart-eb892e92-d138-4e1c-8c80-dbcc5593b1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588387179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.588387179
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3445507584
Short name T930
Test name
Test status
Simulation time 25399493 ps
CPU time 1.33 seconds
Started Jul 28 05:39:04 PM PDT 24
Finished Jul 28 05:39:05 PM PDT 24
Peak memory 218628 kb
Host smart-5098e629-0fda-40d4-ac0b-7f02d877f845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445507584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3445507584
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.3589672970
Short name T76
Test name
Test status
Simulation time 99931288 ps
CPU time 1.29 seconds
Started Jul 28 05:39:01 PM PDT 24
Finished Jul 28 05:39:02 PM PDT 24
Peak memory 218796 kb
Host smart-ec0cf7ba-cbfa-426b-99e7-bfd1e7eff8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589672970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3589672970
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1462404174
Short name T172
Test name
Test status
Simulation time 25329199 ps
CPU time 1.17 seconds
Started Jul 28 05:39:01 PM PDT 24
Finished Jul 28 05:39:02 PM PDT 24
Peak memory 219672 kb
Host smart-d01dcfdc-0092-4357-afeb-94bb9d658ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462404174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1462404174
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.1790906124
Short name T404
Test name
Test status
Simulation time 234338324 ps
CPU time 2.08 seconds
Started Jul 28 05:39:07 PM PDT 24
Finished Jul 28 05:39:10 PM PDT 24
Peak memory 218612 kb
Host smart-638dec4e-05ed-40cb-a3bb-8c5b11cf8931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790906124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1790906124
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.202265430
Short name T317
Test name
Test status
Simulation time 76960682 ps
CPU time 1.21 seconds
Started Jul 28 05:39:06 PM PDT 24
Finished Jul 28 05:39:07 PM PDT 24
Peak memory 218816 kb
Host smart-15bc92b7-402a-4696-b1a4-c12aa8e8a0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202265430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.202265430
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.2151290408
Short name T761
Test name
Test status
Simulation time 159811700 ps
CPU time 2.44 seconds
Started Jul 28 05:39:02 PM PDT 24
Finished Jul 28 05:39:05 PM PDT 24
Peak memory 220004 kb
Host smart-8510d3dd-e2cf-4e80-a532-e8a90d931444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151290408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2151290408
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.2324907148
Short name T72
Test name
Test status
Simulation time 93619888 ps
CPU time 1.27 seconds
Started Jul 28 05:39:07 PM PDT 24
Finished Jul 28 05:39:09 PM PDT 24
Peak memory 219676 kb
Host smart-06bff337-763c-4b4a-9013-8dd9503770e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324907148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2324907148
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2361262252
Short name T539
Test name
Test status
Simulation time 118174356 ps
CPU time 1.18 seconds
Started Jul 28 05:39:05 PM PDT 24
Finished Jul 28 05:39:06 PM PDT 24
Peak memory 217572 kb
Host smart-27cb5757-308d-4806-9914-352b6b3ed439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361262252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2361262252
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.654261683
Short name T191
Test name
Test status
Simulation time 250725121 ps
CPU time 1.13 seconds
Started Jul 28 05:39:07 PM PDT 24
Finished Jul 28 05:39:09 PM PDT 24
Peak memory 218352 kb
Host smart-46b79fd0-702b-42b1-8182-9423c93da28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654261683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.654261683
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.2539289378
Short name T452
Test name
Test status
Simulation time 24464071 ps
CPU time 1.11 seconds
Started Jul 28 05:39:08 PM PDT 24
Finished Jul 28 05:39:09 PM PDT 24
Peak memory 218252 kb
Host smart-944d56b9-2882-4145-947f-f3dd24a18a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539289378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2539289378
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.3623269176
Short name T654
Test name
Test status
Simulation time 27631610 ps
CPU time 1.22 seconds
Started Jul 28 05:39:07 PM PDT 24
Finished Jul 28 05:39:09 PM PDT 24
Peak memory 218324 kb
Host smart-970153e9-8449-47cb-afea-b92ee3eacbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623269176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3623269176
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.1194552143
Short name T688
Test name
Test status
Simulation time 80860128 ps
CPU time 1.42 seconds
Started Jul 28 05:39:09 PM PDT 24
Finished Jul 28 05:39:10 PM PDT 24
Peak memory 218416 kb
Host smart-7f57e2e4-0bbe-4ff4-9e3e-9cb33f21efe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194552143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1194552143
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2598507825
Short name T776
Test name
Test status
Simulation time 48908177 ps
CPU time 1.21 seconds
Started Jul 28 05:39:07 PM PDT 24
Finished Jul 28 05:39:08 PM PDT 24
Peak memory 219320 kb
Host smart-3b6bae41-72a8-4ad1-8f46-8440ab3f8753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598507825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2598507825
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.620715943
Short name T840
Test name
Test status
Simulation time 48845973 ps
CPU time 1.16 seconds
Started Jul 28 05:39:07 PM PDT 24
Finished Jul 28 05:39:09 PM PDT 24
Peak memory 219648 kb
Host smart-e80a71cf-f110-4f20-8c98-0c42125f9552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620715943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.620715943
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3290405659
Short name T915
Test name
Test status
Simulation time 54272882 ps
CPU time 1.22 seconds
Started Jul 28 05:39:05 PM PDT 24
Finished Jul 28 05:39:07 PM PDT 24
Peak memory 219344 kb
Host smart-bf3233eb-df71-4e60-9b77-09344a3aa080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290405659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3290405659
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2476467465
Short name T669
Test name
Test status
Simulation time 65321054 ps
CPU time 1.19 seconds
Started Jul 28 05:39:07 PM PDT 24
Finished Jul 28 05:39:08 PM PDT 24
Peak memory 218928 kb
Host smart-fcf6c609-e8d0-4709-b29a-3cae3d797c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476467465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2476467465
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3293417972
Short name T197
Test name
Test status
Simulation time 61531791 ps
CPU time 1.2 seconds
Started Jul 28 05:37:11 PM PDT 24
Finished Jul 28 05:37:12 PM PDT 24
Peak memory 219028 kb
Host smart-c5e6b738-66e8-4e6a-ba80-bced8b1ef515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293417972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3293417972
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3338317880
Short name T857
Test name
Test status
Simulation time 151848913 ps
CPU time 0.99 seconds
Started Jul 28 05:37:10 PM PDT 24
Finished Jul 28 05:37:11 PM PDT 24
Peak memory 206700 kb
Host smart-ba429071-4db6-4b2c-a3dc-ec9bbb2b8e3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338317880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3338317880
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2297799118
Short name T224
Test name
Test status
Simulation time 10833425 ps
CPU time 0.88 seconds
Started Jul 28 05:37:11 PM PDT 24
Finished Jul 28 05:37:12 PM PDT 24
Peak memory 216076 kb
Host smart-7f62c6ec-f8d6-473b-9169-170f45bc35cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297799118 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2297799118
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3279330510
Short name T877
Test name
Test status
Simulation time 41260795 ps
CPU time 1.12 seconds
Started Jul 28 05:37:13 PM PDT 24
Finished Jul 28 05:37:14 PM PDT 24
Peak memory 216800 kb
Host smart-2e7d576b-9ac4-45ec-9a7b-4a65ef02fdd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279330510 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3279330510
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_genbits.4177640329
Short name T436
Test name
Test status
Simulation time 41794094 ps
CPU time 1.41 seconds
Started Jul 28 05:37:09 PM PDT 24
Finished Jul 28 05:37:10 PM PDT 24
Peak memory 218288 kb
Host smart-bf1bcdda-acc4-49bc-8eef-1fdbcc457831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177640329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.4177640329
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.884359233
Short name T155
Test name
Test status
Simulation time 24317410 ps
CPU time 0.99 seconds
Started Jul 28 05:37:13 PM PDT 24
Finished Jul 28 05:37:14 PM PDT 24
Peak memory 215924 kb
Host smart-c813eb8c-fa1e-4ec1-86d1-67481ddfdd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884359233 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.884359233
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.821491359
Short name T971
Test name
Test status
Simulation time 130945402 ps
CPU time 0.96 seconds
Started Jul 28 05:37:11 PM PDT 24
Finished Jul 28 05:37:12 PM PDT 24
Peak memory 215176 kb
Host smart-fe2e9354-734b-4952-9ee5-0cf66958737f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821491359 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.821491359
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2560955879
Short name T910
Test name
Test status
Simulation time 191841932 ps
CPU time 2.48 seconds
Started Jul 28 05:37:11 PM PDT 24
Finished Jul 28 05:37:14 PM PDT 24
Peak memory 217032 kb
Host smart-14ce3b98-b402-4f44-ab83-63d9cf4500a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560955879 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2560955879
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.782676804
Short name T244
Test name
Test status
Simulation time 84637066674 ps
CPU time 593.79 seconds
Started Jul 28 05:37:13 PM PDT 24
Finished Jul 28 05:47:07 PM PDT 24
Peak memory 219092 kb
Host smart-0d2c9ba5-cbe9-4e7e-ba60-8c8e2862a105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782676804 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.782676804
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.2373564950
Short name T619
Test name
Test status
Simulation time 73888054 ps
CPU time 1.14 seconds
Started Jul 28 05:39:14 PM PDT 24
Finished Jul 28 05:39:15 PM PDT 24
Peak memory 220676 kb
Host smart-4e0d8887-084b-4a78-85b6-83e0f0b143cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373564950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2373564950
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3466974743
Short name T440
Test name
Test status
Simulation time 96943802 ps
CPU time 1.14 seconds
Started Jul 28 05:39:12 PM PDT 24
Finished Jul 28 05:39:13 PM PDT 24
Peak memory 217072 kb
Host smart-a00c2123-05db-4994-a5ed-30c37b673a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466974743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3466974743
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3206989257
Short name T635
Test name
Test status
Simulation time 26005928 ps
CPU time 1.24 seconds
Started Jul 28 05:39:12 PM PDT 24
Finished Jul 28 05:39:13 PM PDT 24
Peak memory 218600 kb
Host smart-5eaee68b-00dc-438e-ada6-761af6b6a08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206989257 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3206989257
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.1493067936
Short name T90
Test name
Test status
Simulation time 37336854 ps
CPU time 1.02 seconds
Started Jul 28 05:39:17 PM PDT 24
Finished Jul 28 05:39:18 PM PDT 24
Peak memory 217080 kb
Host smart-f5f02196-0a05-4c92-9ac7-c37b5b1c635e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493067936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1493067936
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.4085649831
Short name T239
Test name
Test status
Simulation time 44874498 ps
CPU time 1.23 seconds
Started Jul 28 05:39:14 PM PDT 24
Finished Jul 28 05:39:15 PM PDT 24
Peak memory 218776 kb
Host smart-9acc821e-6d9f-450d-8233-207a6093e270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085649831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.4085649831
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.1034413475
Short name T712
Test name
Test status
Simulation time 72721027 ps
CPU time 1.44 seconds
Started Jul 28 05:39:15 PM PDT 24
Finished Jul 28 05:39:17 PM PDT 24
Peak memory 218456 kb
Host smart-08532e69-5f75-4970-825e-f003e89c61c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034413475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1034413475
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.1077367697
Short name T469
Test name
Test status
Simulation time 57550504 ps
CPU time 1.6 seconds
Started Jul 28 05:39:13 PM PDT 24
Finished Jul 28 05:39:15 PM PDT 24
Peak memory 218220 kb
Host smart-e5aa1037-017c-4bc1-92fe-c04e5f7fccc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077367697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1077367697
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.93010484
Short name T35
Test name
Test status
Simulation time 137063891 ps
CPU time 1.19 seconds
Started Jul 28 05:39:13 PM PDT 24
Finished Jul 28 05:39:14 PM PDT 24
Peak memory 218392 kb
Host smart-605ae72f-a65f-46d8-890b-daceceb03a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93010484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.93010484
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.1185333390
Short name T476
Test name
Test status
Simulation time 69597617 ps
CPU time 1.84 seconds
Started Jul 28 05:39:12 PM PDT 24
Finished Jul 28 05:39:14 PM PDT 24
Peak memory 218800 kb
Host smart-7cdc8103-82de-4adb-bb65-e9a67d37a7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185333390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1185333390
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.813441857
Short name T162
Test name
Test status
Simulation time 73862511 ps
CPU time 1.14 seconds
Started Jul 28 05:39:13 PM PDT 24
Finished Jul 28 05:39:14 PM PDT 24
Peak memory 219504 kb
Host smart-6e7e3a3e-d00d-4cd9-9e24-62a52637d50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813441857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.813441857
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3711348301
Short name T507
Test name
Test status
Simulation time 27652970 ps
CPU time 1.38 seconds
Started Jul 28 05:39:10 PM PDT 24
Finished Jul 28 05:39:11 PM PDT 24
Peak memory 218476 kb
Host smart-8ea404de-4157-4ebe-82a9-af8d0398765e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711348301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3711348301
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.163175188
Short name T209
Test name
Test status
Simulation time 35453886 ps
CPU time 1.14 seconds
Started Jul 28 05:39:13 PM PDT 24
Finished Jul 28 05:39:14 PM PDT 24
Peak memory 219900 kb
Host smart-ed79c3b1-2e72-4d3a-b921-aa30c05b0be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163175188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.163175188
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3596887943
Short name T80
Test name
Test status
Simulation time 59430417 ps
CPU time 2.57 seconds
Started Jul 28 05:39:10 PM PDT 24
Finished Jul 28 05:39:12 PM PDT 24
Peak memory 218600 kb
Host smart-46e6050f-1281-4ff1-9389-be4be471ab6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596887943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3596887943
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3538567996
Short name T549
Test name
Test status
Simulation time 109437616 ps
CPU time 1.29 seconds
Started Jul 28 05:39:14 PM PDT 24
Finished Jul 28 05:39:15 PM PDT 24
Peak memory 215548 kb
Host smart-ae36f249-24c1-4e72-adb8-3daa8c32d1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538567996 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3538567996
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.2028897379
Short name T82
Test name
Test status
Simulation time 43972807 ps
CPU time 1.4 seconds
Started Jul 28 05:39:11 PM PDT 24
Finished Jul 28 05:39:13 PM PDT 24
Peak memory 218256 kb
Host smart-d701bc71-8b8a-4330-adcb-141a1abbd2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028897379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2028897379
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.4137140291
Short name T663
Test name
Test status
Simulation time 80016725 ps
CPU time 1.2 seconds
Started Jul 28 05:39:23 PM PDT 24
Finished Jul 28 05:39:24 PM PDT 24
Peak memory 219044 kb
Host smart-dea37e34-bfa6-4f2e-a895-8833edd2a02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137140291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.4137140291
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.2536480042
Short name T798
Test name
Test status
Simulation time 53514737 ps
CPU time 1.29 seconds
Started Jul 28 05:39:16 PM PDT 24
Finished Jul 28 05:39:17 PM PDT 24
Peak memory 219748 kb
Host smart-ff8c04a2-2453-439c-a08d-463554a1a209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536480042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2536480042
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.3279919508
Short name T318
Test name
Test status
Simulation time 45267119 ps
CPU time 1.33 seconds
Started Jul 28 05:39:16 PM PDT 24
Finished Jul 28 05:39:18 PM PDT 24
Peak memory 219776 kb
Host smart-791ade75-b720-4bf8-9f01-75f38603f430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279919508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.3279919508
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.3154561450
Short name T803
Test name
Test status
Simulation time 11031146530 ps
CPU time 133.56 seconds
Started Jul 28 05:39:18 PM PDT 24
Finished Jul 28 05:41:32 PM PDT 24
Peak memory 218744 kb
Host smart-fe1d544f-38b1-485c-95e4-d3a2cd8b0010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154561450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3154561450
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.306297821
Short name T81
Test name
Test status
Simulation time 78542788 ps
CPU time 1.17 seconds
Started Jul 28 05:36:35 PM PDT 24
Finished Jul 28 05:36:37 PM PDT 24
Peak memory 215468 kb
Host smart-59a4d559-1473-4267-9f39-7665389b60f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306297821 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.306297821
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3370778890
Short name T535
Test name
Test status
Simulation time 30065284 ps
CPU time 0.88 seconds
Started Jul 28 05:36:33 PM PDT 24
Finished Jul 28 05:36:34 PM PDT 24
Peak memory 206472 kb
Host smart-cd622b8c-ce62-456c-9f2b-8864e90e5967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370778890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3370778890
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2887260480
Short name T225
Test name
Test status
Simulation time 12001752 ps
CPU time 0.9 seconds
Started Jul 28 05:36:33 PM PDT 24
Finished Jul 28 05:36:34 PM PDT 24
Peak memory 216284 kb
Host smart-73c1597f-e60c-4b5a-a742-f213f7409f08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887260480 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2887260480
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3967120198
Short name T149
Test name
Test status
Simulation time 49410679 ps
CPU time 1.08 seconds
Started Jul 28 05:36:35 PM PDT 24
Finished Jul 28 05:36:37 PM PDT 24
Peak memory 216740 kb
Host smart-7d185e99-07e4-434b-a8ce-2f776ff0b7c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967120198 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3967120198
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1116449891
Short name T182
Test name
Test status
Simulation time 31895386 ps
CPU time 1.02 seconds
Started Jul 28 05:36:38 PM PDT 24
Finished Jul 28 05:36:40 PM PDT 24
Peak memory 229732 kb
Host smart-4d8ada89-da2d-48da-898d-12d69380df7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116449891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1116449891
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3260612766
Short name T956
Test name
Test status
Simulation time 187709983 ps
CPU time 2.85 seconds
Started Jul 28 05:36:34 PM PDT 24
Finished Jul 28 05:36:37 PM PDT 24
Peak memory 218484 kb
Host smart-8bed2033-e351-477d-90e7-af978ffdcd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260612766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3260612766
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2673964476
Short name T102
Test name
Test status
Simulation time 21772644 ps
CPU time 1.07 seconds
Started Jul 28 05:36:34 PM PDT 24
Finished Jul 28 05:36:36 PM PDT 24
Peak memory 215716 kb
Host smart-d5b12bd6-c143-4c36-8c0a-412b6b7f7086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673964476 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2673964476
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1494184113
Short name T947
Test name
Test status
Simulation time 185851732 ps
CPU time 0.95 seconds
Started Jul 28 05:36:35 PM PDT 24
Finished Jul 28 05:36:36 PM PDT 24
Peak memory 206896 kb
Host smart-27e5a632-e636-4531-8315-dd28453f3011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494184113 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1494184113
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.3558795095
Short name T371
Test name
Test status
Simulation time 44539180 ps
CPU time 0.97 seconds
Started Jul 28 05:36:37 PM PDT 24
Finished Jul 28 05:36:38 PM PDT 24
Peak memory 215144 kb
Host smart-9f2ec801-78ab-4d39-8bfa-01b14e3527ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558795095 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3558795095
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3953648859
Short name T323
Test name
Test status
Simulation time 199165532 ps
CPU time 3.95 seconds
Started Jul 28 05:36:33 PM PDT 24
Finished Jul 28 05:36:38 PM PDT 24
Peak memory 218328 kb
Host smart-718fbc82-b722-403a-895a-4da68964ad4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953648859 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3953648859
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.830225165
Short name T903
Test name
Test status
Simulation time 743043092792 ps
CPU time 1806.51 seconds
Started Jul 28 05:36:38 PM PDT 24
Finished Jul 28 06:06:45 PM PDT 24
Peak memory 225092 kb
Host smart-6a2f617a-a87b-4c65-abeb-96d89cbe821f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830225165 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.830225165
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2779782660
Short name T722
Test name
Test status
Simulation time 145721548 ps
CPU time 1.28 seconds
Started Jul 28 05:37:10 PM PDT 24
Finished Jul 28 05:37:12 PM PDT 24
Peak memory 218588 kb
Host smart-e2ffdff6-fa4d-4850-9b0b-c950a69d29f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779782660 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2779782660
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3006635904
Short name T443
Test name
Test status
Simulation time 30125173 ps
CPU time 0.95 seconds
Started Jul 28 05:37:10 PM PDT 24
Finished Jul 28 05:37:11 PM PDT 24
Peak memory 206708 kb
Host smart-b3f4c9fc-5511-4a71-94e2-f009b5a8aab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006635904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3006635904
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.4209573288
Short name T643
Test name
Test status
Simulation time 49247969 ps
CPU time 1.12 seconds
Started Jul 28 05:37:09 PM PDT 24
Finished Jul 28 05:37:10 PM PDT 24
Peak memory 216836 kb
Host smart-daedd92a-e982-4c28-af57-f23c3a0584ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209573288 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.4209573288
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.4285086573
Short name T477
Test name
Test status
Simulation time 56516384 ps
CPU time 1.02 seconds
Started Jul 28 05:37:12 PM PDT 24
Finished Jul 28 05:37:13 PM PDT 24
Peak memory 218400 kb
Host smart-9655bed7-0a61-4fb4-9eab-ff88340355c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285086573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.4285086573
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3239912857
Short name T352
Test name
Test status
Simulation time 65408040 ps
CPU time 2.12 seconds
Started Jul 28 05:37:09 PM PDT 24
Finished Jul 28 05:37:11 PM PDT 24
Peak memory 220056 kb
Host smart-0c98c4fd-3337-4d77-b1ea-9cbcfa6ad8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239912857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3239912857
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1019165721
Short name T14
Test name
Test status
Simulation time 31003534 ps
CPU time 0.97 seconds
Started Jul 28 05:37:09 PM PDT 24
Finished Jul 28 05:37:10 PM PDT 24
Peak memory 223700 kb
Host smart-e0765d1f-dd78-447b-956b-a195513b822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019165721 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1019165721
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1643025506
Short name T859
Test name
Test status
Simulation time 27527765 ps
CPU time 0.93 seconds
Started Jul 28 05:37:10 PM PDT 24
Finished Jul 28 05:37:12 PM PDT 24
Peak memory 215124 kb
Host smart-ba9cc4bc-db52-4f65-b374-62e8aaee25dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643025506 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1643025506
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1434371695
Short name T276
Test name
Test status
Simulation time 706540110 ps
CPU time 3.96 seconds
Started Jul 28 05:37:09 PM PDT 24
Finished Jul 28 05:37:13 PM PDT 24
Peak memory 215240 kb
Host smart-74630c89-3b68-40c1-8018-3faccdc09403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434371695 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1434371695
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3284841652
Short name T881
Test name
Test status
Simulation time 161571075329 ps
CPU time 729.88 seconds
Started Jul 28 05:37:14 PM PDT 24
Finished Jul 28 05:49:25 PM PDT 24
Peak memory 220796 kb
Host smart-2ee3d37e-b478-4e1b-9a27-499c94c3e379
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284841652 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3284841652
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.932485818
Short name T749
Test name
Test status
Simulation time 42088847 ps
CPU time 1.55 seconds
Started Jul 28 05:39:19 PM PDT 24
Finished Jul 28 05:39:21 PM PDT 24
Peak memory 219744 kb
Host smart-31bec8bd-d355-477c-9a92-2bda1ea329ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932485818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.932485818
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2326437852
Short name T866
Test name
Test status
Simulation time 98565355 ps
CPU time 1.48 seconds
Started Jul 28 05:39:18 PM PDT 24
Finished Jul 28 05:39:19 PM PDT 24
Peak memory 218696 kb
Host smart-344660e2-d1a3-4630-b94e-bc9fbec65189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326437852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2326437852
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3120637767
Short name T689
Test name
Test status
Simulation time 87106893 ps
CPU time 1.72 seconds
Started Jul 28 05:39:16 PM PDT 24
Finished Jul 28 05:39:18 PM PDT 24
Peak memory 218608 kb
Host smart-598c58e9-9ca3-4c3f-a9f5-5c91570cd0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120637767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3120637767
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1770748981
Short name T648
Test name
Test status
Simulation time 60260409 ps
CPU time 2.42 seconds
Started Jul 28 05:39:17 PM PDT 24
Finished Jul 28 05:39:19 PM PDT 24
Peak memory 219756 kb
Host smart-79f1a154-a597-48c7-9444-936086f109ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770748981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1770748981
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3491131222
Short name T707
Test name
Test status
Simulation time 84414745 ps
CPU time 1.1 seconds
Started Jul 28 05:39:18 PM PDT 24
Finished Jul 28 05:39:20 PM PDT 24
Peak memory 217168 kb
Host smart-c20d8823-54c4-41f9-951b-e92dc0f70e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491131222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3491131222
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3993226769
Short name T784
Test name
Test status
Simulation time 58280707 ps
CPU time 1.48 seconds
Started Jul 28 05:39:20 PM PDT 24
Finished Jul 28 05:39:22 PM PDT 24
Peak memory 218436 kb
Host smart-3b8c0e88-b802-486e-a8ee-8212a582517c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993226769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3993226769
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2446118822
Short name T892
Test name
Test status
Simulation time 129136847 ps
CPU time 1.62 seconds
Started Jul 28 05:39:19 PM PDT 24
Finished Jul 28 05:39:21 PM PDT 24
Peak memory 218836 kb
Host smart-132067c3-3495-4765-9f54-0b4e421645f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446118822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2446118822
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.825841952
Short name T794
Test name
Test status
Simulation time 57588081 ps
CPU time 1.46 seconds
Started Jul 28 05:39:21 PM PDT 24
Finished Jul 28 05:39:23 PM PDT 24
Peak memory 218484 kb
Host smart-b03c613a-6a7c-4207-b1da-6cc11c210076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825841952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.825841952
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2836065610
Short name T536
Test name
Test status
Simulation time 24882858 ps
CPU time 1.2 seconds
Started Jul 28 05:39:21 PM PDT 24
Finished Jul 28 05:39:22 PM PDT 24
Peak memory 217208 kb
Host smart-a4d62e0e-76b4-4497-8db0-bb4303e18b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836065610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2836065610
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2163406471
Short name T36
Test name
Test status
Simulation time 36080477 ps
CPU time 1.55 seconds
Started Jul 28 05:39:20 PM PDT 24
Finished Jul 28 05:39:21 PM PDT 24
Peak memory 218352 kb
Host smart-f5e6e942-f1fc-4d9c-968f-7e59d1d46ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163406471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2163406471
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.803418340
Short name T314
Test name
Test status
Simulation time 42583108 ps
CPU time 1.27 seconds
Started Jul 28 05:37:13 PM PDT 24
Finished Jul 28 05:37:14 PM PDT 24
Peak memory 218956 kb
Host smart-86fdcb27-9700-45d8-bd6c-2f14ed038769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803418340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.803418340
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1970724161
Short name T504
Test name
Test status
Simulation time 33062152 ps
CPU time 0.84 seconds
Started Jul 28 05:37:15 PM PDT 24
Finished Jul 28 05:37:16 PM PDT 24
Peak memory 206276 kb
Host smart-e079b896-2a25-4f27-b4d6-87639fb79686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970724161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1970724161
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.655999553
Short name T800
Test name
Test status
Simulation time 31358410 ps
CPU time 0.81 seconds
Started Jul 28 05:37:14 PM PDT 24
Finished Jul 28 05:37:15 PM PDT 24
Peak memory 215440 kb
Host smart-c7ec7071-33bf-4590-b5fd-c2e3ca4c7ae2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655999553 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.655999553
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.795059086
Short name T19
Test name
Test status
Simulation time 37034328 ps
CPU time 1.23 seconds
Started Jul 28 05:37:12 PM PDT 24
Finished Jul 28 05:37:14 PM PDT 24
Peak memory 216740 kb
Host smart-c9b29081-dcae-4d62-8895-20b169fb41ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795059086 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.795059086
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3549560479
Short name T175
Test name
Test status
Simulation time 26230911 ps
CPU time 0.99 seconds
Started Jul 28 05:37:11 PM PDT 24
Finished Jul 28 05:37:12 PM PDT 24
Peak memory 219400 kb
Host smart-21fac800-5e6f-4a24-bf9b-26ac9ee66b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549560479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3549560479
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2322002118
Short name T416
Test name
Test status
Simulation time 84172182 ps
CPU time 2.43 seconds
Started Jul 28 05:37:15 PM PDT 24
Finished Jul 28 05:37:17 PM PDT 24
Peak memory 219888 kb
Host smart-0f5365e3-48f8-4d59-a7ce-d2e3cd403e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322002118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2322002118
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.990294156
Short name T701
Test name
Test status
Simulation time 21584728 ps
CPU time 1.17 seconds
Started Jul 28 05:37:10 PM PDT 24
Finished Jul 28 05:37:11 PM PDT 24
Peak memory 223832 kb
Host smart-8c526e25-31c6-413a-ad73-c14f7d5da5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990294156 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.990294156
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.923351017
Short name T670
Test name
Test status
Simulation time 42313103 ps
CPU time 1.02 seconds
Started Jul 28 05:37:11 PM PDT 24
Finished Jul 28 05:37:12 PM PDT 24
Peak memory 207088 kb
Host smart-97929cc4-418b-4788-8994-8ee9287a8df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923351017 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.923351017
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.4283491917
Short name T339
Test name
Test status
Simulation time 198158576 ps
CPU time 4.36 seconds
Started Jul 28 05:37:12 PM PDT 24
Finished Jul 28 05:37:16 PM PDT 24
Peak memory 217000 kb
Host smart-cccc966e-b631-4216-aa2f-377faa0e3de1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283491917 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.4283491917
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3146111589
Short name T825
Test name
Test status
Simulation time 70120332975 ps
CPU time 324.4 seconds
Started Jul 28 05:37:08 PM PDT 24
Finished Jul 28 05:42:33 PM PDT 24
Peak memory 217784 kb
Host smart-df37907a-657c-4668-b46e-02939701dbde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146111589 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3146111589
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1736597764
Short name T8
Test name
Test status
Simulation time 25425230 ps
CPU time 1.16 seconds
Started Jul 28 05:39:19 PM PDT 24
Finished Jul 28 05:39:20 PM PDT 24
Peak memory 219844 kb
Host smart-3c7853a0-7e8a-48ba-a61c-3b0958f4e5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736597764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1736597764
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2454089854
Short name T855
Test name
Test status
Simulation time 115142083 ps
CPU time 1.22 seconds
Started Jul 28 05:39:16 PM PDT 24
Finished Jul 28 05:39:17 PM PDT 24
Peak memory 217156 kb
Host smart-6ff857c1-fe09-46df-b67b-d13c37165607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454089854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2454089854
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3811047351
Short name T337
Test name
Test status
Simulation time 151942920 ps
CPU time 3.53 seconds
Started Jul 28 05:39:18 PM PDT 24
Finished Jul 28 05:39:22 PM PDT 24
Peak memory 217600 kb
Host smart-13943c26-a0bf-4971-8e7e-55bc7bd19625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811047351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3811047351
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2559059265
Short name T543
Test name
Test status
Simulation time 78079016 ps
CPU time 1.88 seconds
Started Jul 28 05:39:21 PM PDT 24
Finished Jul 28 05:39:24 PM PDT 24
Peak memory 218564 kb
Host smart-5a9690b6-ee81-4a32-9366-41209986c958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559059265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2559059265
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1885847345
Short name T2
Test name
Test status
Simulation time 82572188 ps
CPU time 1.23 seconds
Started Jul 28 05:39:21 PM PDT 24
Finished Jul 28 05:39:22 PM PDT 24
Peak memory 219020 kb
Host smart-9cc218d2-6f3e-43f6-aaf1-17c02a33e7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885847345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1885847345
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.677106368
Short name T826
Test name
Test status
Simulation time 41137064 ps
CPU time 1.32 seconds
Started Jul 28 05:39:21 PM PDT 24
Finished Jul 28 05:39:22 PM PDT 24
Peak memory 218732 kb
Host smart-2b656453-9785-436c-99c2-5680acd68fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677106368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.677106368
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2804309046
Short name T704
Test name
Test status
Simulation time 384068085 ps
CPU time 3.5 seconds
Started Jul 28 05:39:20 PM PDT 24
Finished Jul 28 05:39:24 PM PDT 24
Peak memory 219760 kb
Host smart-7930897a-f54f-45b0-8103-084170b241d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804309046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2804309046
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2606323677
Short name T12
Test name
Test status
Simulation time 42394113 ps
CPU time 1.57 seconds
Started Jul 28 05:39:23 PM PDT 24
Finished Jul 28 05:39:25 PM PDT 24
Peak memory 219884 kb
Host smart-d8e88c59-521f-41d4-8c22-b3fc7a6271d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606323677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2606323677
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3437564161
Short name T552
Test name
Test status
Simulation time 38462086 ps
CPU time 1.33 seconds
Started Jul 28 05:39:20 PM PDT 24
Finished Jul 28 05:39:22 PM PDT 24
Peak memory 218376 kb
Host smart-886d435e-9e1e-4fa2-a840-ee5f59910698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437564161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3437564161
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3361472061
Short name T399
Test name
Test status
Simulation time 48857577 ps
CPU time 1.35 seconds
Started Jul 28 05:39:22 PM PDT 24
Finished Jul 28 05:39:24 PM PDT 24
Peak memory 218332 kb
Host smart-0425551b-1b69-42b9-8201-a8bf0201afe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361472061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3361472061
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.22147189
Short name T464
Test name
Test status
Simulation time 77162946 ps
CPU time 1.21 seconds
Started Jul 28 05:37:14 PM PDT 24
Finished Jul 28 05:37:15 PM PDT 24
Peak memory 219292 kb
Host smart-a95d5ba7-6535-49dc-ad96-2fcf66dbe885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22147189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.22147189
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.855724671
Short name T487
Test name
Test status
Simulation time 41689626 ps
CPU time 1.04 seconds
Started Jul 28 05:37:14 PM PDT 24
Finished Jul 28 05:37:16 PM PDT 24
Peak memory 206648 kb
Host smart-14cf9802-3f83-4fba-875f-a9800fd2865a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855724671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.855724671
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3180174689
Short name T372
Test name
Test status
Simulation time 22794787 ps
CPU time 0.85 seconds
Started Jul 28 05:37:35 PM PDT 24
Finished Jul 28 05:37:36 PM PDT 24
Peak memory 216128 kb
Host smart-3b405be8-adb3-4dc4-9581-fa0ee84275f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180174689 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3180174689
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.948628919
Short name T870
Test name
Test status
Simulation time 66757267 ps
CPU time 1.15 seconds
Started Jul 28 05:37:17 PM PDT 24
Finished Jul 28 05:37:18 PM PDT 24
Peak memory 216756 kb
Host smart-bbd8c097-e9ee-4b88-a6d1-9c96db4c134c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948628919 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.948628919
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2448195969
Short name T491
Test name
Test status
Simulation time 28866430 ps
CPU time 1.03 seconds
Started Jul 28 05:37:17 PM PDT 24
Finished Jul 28 05:37:18 PM PDT 24
Peak memory 223860 kb
Host smart-b513ff6e-604f-49d1-b706-9f27a616759f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448195969 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2448195969
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3299934545
Short name T869
Test name
Test status
Simulation time 53033721 ps
CPU time 1.31 seconds
Started Jul 28 05:37:33 PM PDT 24
Finished Jul 28 05:37:34 PM PDT 24
Peak memory 217164 kb
Host smart-a562ea01-4d63-4352-8d35-bfabc4b5e909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299934545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3299934545
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1337710169
Short name T89
Test name
Test status
Simulation time 125624554 ps
CPU time 0.88 seconds
Started Jul 28 05:37:19 PM PDT 24
Finished Jul 28 05:37:20 PM PDT 24
Peak memory 215232 kb
Host smart-016d69df-2dad-4ad6-9d30-fb3e00279cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337710169 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1337710169
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1811236780
Short name T354
Test name
Test status
Simulation time 42156696 ps
CPU time 0.89 seconds
Started Jul 28 05:37:15 PM PDT 24
Finished Jul 28 05:37:16 PM PDT 24
Peak memory 215236 kb
Host smart-a521f358-42e4-46da-9a0e-bb0fc7715531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811236780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1811236780
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3279901038
Short name T696
Test name
Test status
Simulation time 818835105 ps
CPU time 4.4 seconds
Started Jul 28 05:37:19 PM PDT 24
Finished Jul 28 05:37:23 PM PDT 24
Peak memory 219504 kb
Host smart-fdf9f4bc-7ae6-4990-ab0e-3b3b25d37dc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279901038 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3279901038
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3594850337
Short name T835
Test name
Test status
Simulation time 20131714917 ps
CPU time 248.38 seconds
Started Jul 28 05:37:27 PM PDT 24
Finished Jul 28 05:41:36 PM PDT 24
Peak memory 217920 kb
Host smart-b3eba39d-9250-42c1-968d-2d380c142bb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594850337 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3594850337
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1413679615
Short name T841
Test name
Test status
Simulation time 51463152 ps
CPU time 1.63 seconds
Started Jul 28 05:39:27 PM PDT 24
Finished Jul 28 05:39:28 PM PDT 24
Peak memory 218220 kb
Host smart-335e359f-4551-46b7-a54d-b6970e7667e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413679615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1413679615
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1807520697
Short name T391
Test name
Test status
Simulation time 100756424 ps
CPU time 1.28 seconds
Started Jul 28 05:39:21 PM PDT 24
Finished Jul 28 05:39:22 PM PDT 24
Peak memory 219772 kb
Host smart-46251d2d-236d-4638-9731-4a5096bd2fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807520697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1807520697
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3281421962
Short name T515
Test name
Test status
Simulation time 123534724 ps
CPU time 1.5 seconds
Started Jul 28 05:39:23 PM PDT 24
Finished Jul 28 05:39:25 PM PDT 24
Peak memory 219556 kb
Host smart-b8cd88bf-8098-484c-92e5-fa9b289937d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281421962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3281421962
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3354143192
Short name T659
Test name
Test status
Simulation time 48485141 ps
CPU time 1.38 seconds
Started Jul 28 05:39:24 PM PDT 24
Finished Jul 28 05:39:25 PM PDT 24
Peak memory 218692 kb
Host smart-07c299c1-3404-46d0-b33d-321966800619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354143192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3354143192
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.481329238
Short name T629
Test name
Test status
Simulation time 140048496 ps
CPU time 3.5 seconds
Started Jul 28 05:39:26 PM PDT 24
Finished Jul 28 05:39:30 PM PDT 24
Peak memory 218700 kb
Host smart-a206efcc-faed-4a6c-b6b5-3b512ca5caee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481329238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.481329238
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.196772768
Short name T530
Test name
Test status
Simulation time 53890407 ps
CPU time 1.35 seconds
Started Jul 28 05:39:24 PM PDT 24
Finished Jul 28 05:39:25 PM PDT 24
Peak memory 218316 kb
Host smart-96751273-7038-40ae-b9e9-367797c687f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196772768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.196772768
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1758320632
Short name T891
Test name
Test status
Simulation time 312723055 ps
CPU time 1.24 seconds
Started Jul 28 05:39:27 PM PDT 24
Finished Jul 28 05:39:29 PM PDT 24
Peak memory 217296 kb
Host smart-cb2fd0fb-78cc-420c-8811-cad3df9abb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758320632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1758320632
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.4155401798
Short name T591
Test name
Test status
Simulation time 62392235 ps
CPU time 1.38 seconds
Started Jul 28 05:39:21 PM PDT 24
Finished Jul 28 05:39:22 PM PDT 24
Peak memory 217076 kb
Host smart-8baa35dc-4a48-49b8-b984-ca6b79ab9999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155401798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.4155401798
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2365447003
Short name T740
Test name
Test status
Simulation time 57687570 ps
CPU time 1.71 seconds
Started Jul 28 05:39:25 PM PDT 24
Finished Jul 28 05:39:26 PM PDT 24
Peak memory 218500 kb
Host smart-32607486-83b1-46e2-a7ef-52623336f0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365447003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2365447003
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3675198553
Short name T603
Test name
Test status
Simulation time 124661844 ps
CPU time 1.11 seconds
Started Jul 28 05:37:18 PM PDT 24
Finished Jul 28 05:37:20 PM PDT 24
Peak memory 218268 kb
Host smart-7d926ba3-8bc0-4a2b-8932-0f7dede2cd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675198553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3675198553
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1594914999
Short name T764
Test name
Test status
Simulation time 22388269 ps
CPU time 1.02 seconds
Started Jul 28 05:37:15 PM PDT 24
Finished Jul 28 05:37:16 PM PDT 24
Peak memory 206724 kb
Host smart-ad359dc3-2462-4cea-a5f5-77e28b7d8b3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594914999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1594914999
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2625672560
Short name T921
Test name
Test status
Simulation time 48098495 ps
CPU time 1.48 seconds
Started Jul 28 05:37:19 PM PDT 24
Finished Jul 28 05:37:20 PM PDT 24
Peak memory 216852 kb
Host smart-778f318d-f48d-4d01-9697-68392547a872
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625672560 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2625672560
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1591943538
Short name T610
Test name
Test status
Simulation time 25345594 ps
CPU time 0.89 seconds
Started Jul 28 05:37:13 PM PDT 24
Finished Jul 28 05:37:14 PM PDT 24
Peak memory 218380 kb
Host smart-2721e816-d3ca-464b-b544-9fd439cb7554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591943538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1591943538
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3753732102
Short name T419
Test name
Test status
Simulation time 54839948 ps
CPU time 1.51 seconds
Started Jul 28 05:37:14 PM PDT 24
Finished Jul 28 05:37:16 PM PDT 24
Peak memory 218420 kb
Host smart-2c830acb-9795-4e5a-a6b0-64a229e98c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753732102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3753732102
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2891819989
Short name T70
Test name
Test status
Simulation time 27199624 ps
CPU time 1 seconds
Started Jul 28 05:37:15 PM PDT 24
Finished Jul 28 05:37:17 PM PDT 24
Peak memory 215440 kb
Host smart-c8a673ae-ea6d-482e-811f-82d91aa77c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891819989 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2891819989
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.248846728
Short name T364
Test name
Test status
Simulation time 16959003 ps
CPU time 0.97 seconds
Started Jul 28 05:37:18 PM PDT 24
Finished Jul 28 05:37:19 PM PDT 24
Peak memory 215124 kb
Host smart-e6247a1d-6103-4007-9048-9bdb370ab406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248846728 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.248846728
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.875374855
Short name T973
Test name
Test status
Simulation time 169257858 ps
CPU time 2.21 seconds
Started Jul 28 05:37:28 PM PDT 24
Finished Jul 28 05:37:31 PM PDT 24
Peak memory 218276 kb
Host smart-0c404c46-18aa-47f8-a487-2b772e8d78c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875374855 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.875374855
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2078681171
Short name T449
Test name
Test status
Simulation time 49276031329 ps
CPU time 526.71 seconds
Started Jul 28 05:37:14 PM PDT 24
Finished Jul 28 05:46:01 PM PDT 24
Peak memory 223508 kb
Host smart-26cf1d0c-f114-4fdc-843f-1a679d9b82a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078681171 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2078681171
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.347540528
Short name T334
Test name
Test status
Simulation time 54631077 ps
CPU time 1.48 seconds
Started Jul 28 05:39:22 PM PDT 24
Finished Jul 28 05:39:24 PM PDT 24
Peak memory 220340 kb
Host smart-1f0a92cf-75e3-49c9-9d93-08b1c4450cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347540528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.347540528
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1476539700
Short name T942
Test name
Test status
Simulation time 53640852 ps
CPU time 1.43 seconds
Started Jul 28 05:39:28 PM PDT 24
Finished Jul 28 05:39:29 PM PDT 24
Peak memory 218236 kb
Host smart-2ae20c5d-d67b-489c-83a4-7c49ac869f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476539700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1476539700
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1410672544
Short name T30
Test name
Test status
Simulation time 81350982 ps
CPU time 1.1 seconds
Started Jul 28 05:39:27 PM PDT 24
Finished Jul 28 05:39:28 PM PDT 24
Peak memory 217212 kb
Host smart-a3f5de07-df4b-466b-bdba-c585008ea9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410672544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1410672544
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3566533712
Short name T445
Test name
Test status
Simulation time 54489518 ps
CPU time 1.79 seconds
Started Jul 28 05:39:25 PM PDT 24
Finished Jul 28 05:39:27 PM PDT 24
Peak memory 218468 kb
Host smart-2901fc98-64c2-4fdd-b2c2-a4506c4a77c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566533712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3566533712
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.619484168
Short name T257
Test name
Test status
Simulation time 66772783 ps
CPU time 1.09 seconds
Started Jul 28 05:39:28 PM PDT 24
Finished Jul 28 05:39:30 PM PDT 24
Peak memory 218720 kb
Host smart-30ab463d-aee5-4739-b78d-857dd022e889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619484168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.619484168
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2173791686
Short name T321
Test name
Test status
Simulation time 36605231 ps
CPU time 1.62 seconds
Started Jul 28 05:39:31 PM PDT 24
Finished Jul 28 05:39:32 PM PDT 24
Peak memory 218212 kb
Host smart-5622cc82-9b1e-4924-bbef-86122dbb489e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173791686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2173791686
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2177066563
Short name T161
Test name
Test status
Simulation time 79613515 ps
CPU time 1.13 seconds
Started Jul 28 05:39:28 PM PDT 24
Finished Jul 28 05:39:29 PM PDT 24
Peak memory 217172 kb
Host smart-7c217d96-22af-4f2f-8cd3-1b73d7f143d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177066563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2177066563
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3314946605
Short name T249
Test name
Test status
Simulation time 24806347 ps
CPU time 1.26 seconds
Started Jul 28 05:39:25 PM PDT 24
Finished Jul 28 05:39:27 PM PDT 24
Peak memory 218488 kb
Host smart-2e93381d-8114-4ffa-99da-db335f651ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314946605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3314946605
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2968409194
Short name T531
Test name
Test status
Simulation time 60440703 ps
CPU time 1.39 seconds
Started Jul 28 05:39:25 PM PDT 24
Finished Jul 28 05:39:27 PM PDT 24
Peak memory 220188 kb
Host smart-52743bce-55c2-4463-94e9-362f6d46b3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968409194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2968409194
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3511454399
Short name T407
Test name
Test status
Simulation time 34804040 ps
CPU time 1.33 seconds
Started Jul 28 05:39:28 PM PDT 24
Finished Jul 28 05:39:29 PM PDT 24
Peak memory 217148 kb
Host smart-4abe281d-d7de-47ba-ac56-84854e54db3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511454399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3511454399
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3493624672
Short name T465
Test name
Test status
Simulation time 28390808 ps
CPU time 1.2 seconds
Started Jul 28 05:37:26 PM PDT 24
Finished Jul 28 05:37:28 PM PDT 24
Peak memory 218568 kb
Host smart-619e5fa4-c758-4e32-ba02-93e8bec73022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493624672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3493624672
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.360628428
Short name T275
Test name
Test status
Simulation time 20811920 ps
CPU time 0.92 seconds
Started Jul 28 05:37:27 PM PDT 24
Finished Jul 28 05:37:28 PM PDT 24
Peak memory 206676 kb
Host smart-542d1698-f7c1-4cc7-abda-afc6516b92c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360628428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.360628428
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.657472697
Short name T120
Test name
Test status
Simulation time 12561649 ps
CPU time 0.89 seconds
Started Jul 28 05:37:28 PM PDT 24
Finished Jul 28 05:37:29 PM PDT 24
Peak memory 216296 kb
Host smart-7eefd976-3cc3-4353-90d9-6912eab94952
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657472697 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.657472697
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1760552250
Short name T924
Test name
Test status
Simulation time 42253526 ps
CPU time 1.18 seconds
Started Jul 28 05:37:19 PM PDT 24
Finished Jul 28 05:37:20 PM PDT 24
Peak memory 216820 kb
Host smart-4bbfc770-adfb-4f31-b800-21c7614e3bc1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760552250 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1760552250
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3374912752
Short name T130
Test name
Test status
Simulation time 30943031 ps
CPU time 0.91 seconds
Started Jul 28 05:37:12 PM PDT 24
Finished Jul 28 05:37:13 PM PDT 24
Peak memory 218444 kb
Host smart-36cc019b-9779-4b76-aaaf-3a94984068cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374912752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3374912752
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.77794238
Short name T806
Test name
Test status
Simulation time 37654240 ps
CPU time 1.47 seconds
Started Jul 28 05:37:27 PM PDT 24
Finished Jul 28 05:37:29 PM PDT 24
Peak memory 218252 kb
Host smart-6b38c75c-5844-404f-a74c-e1563d21f319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77794238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.77794238
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1638321442
Short name T378
Test name
Test status
Simulation time 25354197 ps
CPU time 1.05 seconds
Started Jul 28 05:37:15 PM PDT 24
Finished Jul 28 05:37:17 PM PDT 24
Peak memory 215416 kb
Host smart-0b8582d5-f22c-4163-9fbc-a8f99a318266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638321442 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1638321442
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1812002651
Short name T799
Test name
Test status
Simulation time 18153942 ps
CPU time 1.04 seconds
Started Jul 28 05:37:14 PM PDT 24
Finished Jul 28 05:37:16 PM PDT 24
Peak memory 215116 kb
Host smart-6c65a626-834b-462a-9850-0a8636b49c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812002651 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1812002651
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3734865898
Short name T763
Test name
Test status
Simulation time 210852734 ps
CPU time 2.21 seconds
Started Jul 28 05:37:16 PM PDT 24
Finished Jul 28 05:37:18 PM PDT 24
Peak memory 217064 kb
Host smart-f6b76402-2e44-4d71-9d55-cfc6e017df4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734865898 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3734865898
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.4256543735
Short name T946
Test name
Test status
Simulation time 1017618517508 ps
CPU time 1693.36 seconds
Started Jul 28 05:37:13 PM PDT 24
Finished Jul 28 06:05:27 PM PDT 24
Peak memory 225892 kb
Host smart-47a65eb7-c523-4f48-81b1-3c3469c35671
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256543735 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.4256543735
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1120281279
Short name T647
Test name
Test status
Simulation time 400131081 ps
CPU time 2.13 seconds
Started Jul 28 05:39:31 PM PDT 24
Finished Jul 28 05:39:33 PM PDT 24
Peak memory 218796 kb
Host smart-3bbcd523-ed3e-4bf2-ab70-118811b3de8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120281279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1120281279
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2886282319
Short name T474
Test name
Test status
Simulation time 40417921 ps
CPU time 1.73 seconds
Started Jul 28 05:39:27 PM PDT 24
Finished Jul 28 05:39:29 PM PDT 24
Peak memory 218500 kb
Host smart-70b2f3b2-9ead-4e5d-8b64-ecbc7bacfc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886282319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2886282319
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3906156557
Short name T929
Test name
Test status
Simulation time 47849418 ps
CPU time 1.18 seconds
Started Jul 28 05:39:25 PM PDT 24
Finished Jul 28 05:39:26 PM PDT 24
Peak memory 219792 kb
Host smart-cf92b191-45c1-4f22-882f-6ed3d2a9dc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906156557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3906156557
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.463120060
Short name T573
Test name
Test status
Simulation time 77851257 ps
CPU time 1.19 seconds
Started Jul 28 05:39:28 PM PDT 24
Finished Jul 28 05:39:29 PM PDT 24
Peak memory 217352 kb
Host smart-7dfbc5c2-ee58-4067-92c6-49411b5fa81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463120060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.463120060
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3455366158
Short name T851
Test name
Test status
Simulation time 141275588 ps
CPU time 2.11 seconds
Started Jul 28 05:39:29 PM PDT 24
Finished Jul 28 05:39:31 PM PDT 24
Peak memory 219852 kb
Host smart-443b6f45-efdc-4ebf-8e30-94dcc51d451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455366158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3455366158
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1671595653
Short name T537
Test name
Test status
Simulation time 165264933 ps
CPU time 1.3 seconds
Started Jul 28 05:39:31 PM PDT 24
Finished Jul 28 05:39:33 PM PDT 24
Peak memory 217204 kb
Host smart-b9ded56b-aef7-47b6-a357-3c71f5671639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671595653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1671595653
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2220417322
Short name T904
Test name
Test status
Simulation time 148726630 ps
CPU time 1.48 seconds
Started Jul 28 05:39:32 PM PDT 24
Finished Jul 28 05:39:34 PM PDT 24
Peak memory 218892 kb
Host smart-da4241c7-6252-4782-9e66-16df356f70e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220417322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2220417322
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1603413386
Short name T728
Test name
Test status
Simulation time 48093731 ps
CPU time 1.17 seconds
Started Jul 28 05:39:31 PM PDT 24
Finished Jul 28 05:39:32 PM PDT 24
Peak memory 217148 kb
Host smart-e9a61615-2f6c-4379-92d7-e85c9ee4fbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603413386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1603413386
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1687151469
Short name T32
Test name
Test status
Simulation time 61763950 ps
CPU time 1.08 seconds
Started Jul 28 05:39:30 PM PDT 24
Finished Jul 28 05:39:32 PM PDT 24
Peak memory 217108 kb
Host smart-506e254b-c2c5-4e2f-b918-309a71576bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687151469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1687151469
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1775763228
Short name T164
Test name
Test status
Simulation time 32320886 ps
CPU time 1.41 seconds
Started Jul 28 05:39:36 PM PDT 24
Finished Jul 28 05:39:37 PM PDT 24
Peak memory 218572 kb
Host smart-10bcdbf9-c3e8-4860-89ca-a3ae3faeffb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775763228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1775763228
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.419488139
Short name T265
Test name
Test status
Simulation time 28424573 ps
CPU time 1.26 seconds
Started Jul 28 05:37:19 PM PDT 24
Finished Jul 28 05:37:20 PM PDT 24
Peak memory 218448 kb
Host smart-ea479e90-e7a3-4461-a959-8d75aa616153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419488139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.419488139
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3566741838
Short name T897
Test name
Test status
Simulation time 45374202 ps
CPU time 0.86 seconds
Started Jul 28 05:37:19 PM PDT 24
Finished Jul 28 05:37:20 PM PDT 24
Peak memory 206680 kb
Host smart-c8ec729f-6163-464d-9aa0-25baf4e7563e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566741838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3566741838
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1275367221
Short name T836
Test name
Test status
Simulation time 31710533 ps
CPU time 0.87 seconds
Started Jul 28 05:37:17 PM PDT 24
Finished Jul 28 05:37:18 PM PDT 24
Peak memory 216060 kb
Host smart-9f0f5fb9-056d-422c-9518-021d084fc570
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275367221 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1275367221
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.3314078022
Short name T215
Test name
Test status
Simulation time 20190758 ps
CPU time 1.03 seconds
Started Jul 28 05:37:14 PM PDT 24
Finished Jul 28 05:37:15 PM PDT 24
Peak memory 218320 kb
Host smart-d6dfc83f-8102-4a99-89ec-cd2c70223bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314078022 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3314078022
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.182506877
Short name T729
Test name
Test status
Simulation time 49975698 ps
CPU time 1.01 seconds
Started Jul 28 05:37:16 PM PDT 24
Finished Jul 28 05:37:17 PM PDT 24
Peak memory 217064 kb
Host smart-0b817584-f9dd-4ab4-8ccf-a11039b0e96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182506877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.182506877
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2987436017
Short name T44
Test name
Test status
Simulation time 22198112 ps
CPU time 1.17 seconds
Started Jul 28 05:37:18 PM PDT 24
Finished Jul 28 05:37:19 PM PDT 24
Peak memory 215344 kb
Host smart-b490692a-d0d0-46de-b31d-b90706155719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987436017 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2987436017
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.4207636280
Short name T970
Test name
Test status
Simulation time 24468555 ps
CPU time 0.94 seconds
Started Jul 28 05:37:19 PM PDT 24
Finished Jul 28 05:37:20 PM PDT 24
Peak memory 215108 kb
Host smart-4be8f8b1-1ed9-452f-808e-f592b7ffa8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207636280 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.4207636280
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1281876112
Short name T382
Test name
Test status
Simulation time 428888524 ps
CPU time 4.46 seconds
Started Jul 28 05:37:19 PM PDT 24
Finished Jul 28 05:37:23 PM PDT 24
Peak memory 215228 kb
Host smart-c11aa85e-ceef-4bad-a576-2df7fe749658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281876112 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1281876112
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2555902556
Short name T248
Test name
Test status
Simulation time 20214278953 ps
CPU time 418.52 seconds
Started Jul 28 05:37:14 PM PDT 24
Finished Jul 28 05:44:13 PM PDT 24
Peak memory 222664 kb
Host smart-aee2dbec-d3c9-48eb-b36d-6eff437a9ee0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555902556 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2555902556
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1740929854
Short name T943
Test name
Test status
Simulation time 101869244 ps
CPU time 1.77 seconds
Started Jul 28 05:39:34 PM PDT 24
Finished Jul 28 05:39:36 PM PDT 24
Peak memory 219868 kb
Host smart-7ef1eb90-445d-4ca1-8874-cbeb86e53024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740929854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1740929854
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2762320029
Short name T792
Test name
Test status
Simulation time 101763701 ps
CPU time 1.67 seconds
Started Jul 28 05:39:32 PM PDT 24
Finished Jul 28 05:39:33 PM PDT 24
Peak memory 218552 kb
Host smart-ab799e22-d5a6-40d0-b4a4-7765e236133d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762320029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2762320029
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.490009809
Short name T911
Test name
Test status
Simulation time 90786735 ps
CPU time 1.21 seconds
Started Jul 28 05:39:33 PM PDT 24
Finished Jul 28 05:39:35 PM PDT 24
Peak memory 217272 kb
Host smart-a7cecdb5-f81e-465e-99b6-b46544b99fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490009809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.490009809
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.4018987471
Short name T353
Test name
Test status
Simulation time 93407384 ps
CPU time 2.01 seconds
Started Jul 28 05:39:35 PM PDT 24
Finished Jul 28 05:39:37 PM PDT 24
Peak memory 219320 kb
Host smart-1b647454-faae-4146-bde9-631437dc2375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018987471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.4018987471
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2277869003
Short name T330
Test name
Test status
Simulation time 39588555 ps
CPU time 1.46 seconds
Started Jul 28 05:39:33 PM PDT 24
Finished Jul 28 05:39:35 PM PDT 24
Peak memory 218208 kb
Host smart-f808052c-2f4a-42ee-bc5c-a553423b150d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277869003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2277869003
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.4178869290
Short name T918
Test name
Test status
Simulation time 77742961 ps
CPU time 1.89 seconds
Started Jul 28 05:39:35 PM PDT 24
Finished Jul 28 05:39:37 PM PDT 24
Peak memory 217384 kb
Host smart-7e6f4560-42a7-45ec-aeaf-dcf0d96a2c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178869290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.4178869290
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1594137064
Short name T966
Test name
Test status
Simulation time 271737937 ps
CPU time 3.34 seconds
Started Jul 28 05:39:33 PM PDT 24
Finished Jul 28 05:39:37 PM PDT 24
Peak memory 220196 kb
Host smart-42fbc495-6a6d-4c6e-a7ad-1567c660b76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594137064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1594137064
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1977788219
Short name T480
Test name
Test status
Simulation time 32953431 ps
CPU time 1.01 seconds
Started Jul 28 05:39:35 PM PDT 24
Finished Jul 28 05:39:36 PM PDT 24
Peak memory 217204 kb
Host smart-4db4f63c-e9ef-41f7-99f5-a5006d2b5c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977788219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1977788219
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3084569684
Short name T550
Test name
Test status
Simulation time 51733648 ps
CPU time 1.41 seconds
Started Jul 28 05:39:38 PM PDT 24
Finished Jul 28 05:39:40 PM PDT 24
Peak memory 218460 kb
Host smart-1e15c8ca-3022-4e55-9398-ba887bce3b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084569684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3084569684
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.457450144
Short name T676
Test name
Test status
Simulation time 64870570 ps
CPU time 1.36 seconds
Started Jul 28 05:39:35 PM PDT 24
Finished Jul 28 05:39:36 PM PDT 24
Peak memory 218432 kb
Host smart-ee80b4dd-8d5c-40d9-9f5d-64960dfb27a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457450144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.457450144
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.789370956
Short name T192
Test name
Test status
Simulation time 22357841 ps
CPU time 1.14 seconds
Started Jul 28 05:37:17 PM PDT 24
Finished Jul 28 05:37:18 PM PDT 24
Peak memory 218468 kb
Host smart-745de2ea-2a4e-486f-b0dd-4457c1f25081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789370956 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.789370956
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2153015332
Short name T518
Test name
Test status
Simulation time 82976765 ps
CPU time 0.81 seconds
Started Jul 28 05:37:18 PM PDT 24
Finished Jul 28 05:37:19 PM PDT 24
Peak memory 205904 kb
Host smart-84c89029-232d-41ec-bb23-c54d9f71fe53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153015332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2153015332
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2512861230
Short name T481
Test name
Test status
Simulation time 49558013 ps
CPU time 1.15 seconds
Started Jul 28 05:37:15 PM PDT 24
Finished Jul 28 05:37:17 PM PDT 24
Peak memory 216772 kb
Host smart-30f5edb4-f47c-4518-a495-0a739c44051f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512861230 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2512861230
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1180105240
Short name T714
Test name
Test status
Simulation time 21695635 ps
CPU time 0.88 seconds
Started Jul 28 05:37:17 PM PDT 24
Finished Jul 28 05:37:18 PM PDT 24
Peak memory 218204 kb
Host smart-093454cd-a793-43ed-be72-a0246ccb211f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180105240 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1180105240
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1041085970
Short name T562
Test name
Test status
Simulation time 77849794 ps
CPU time 1.14 seconds
Started Jul 28 05:37:14 PM PDT 24
Finished Jul 28 05:37:15 PM PDT 24
Peak memory 217348 kb
Host smart-2835ba96-9a5a-4ff7-9916-306f67ac558f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041085970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1041085970
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1394416702
Short name T46
Test name
Test status
Simulation time 26129261 ps
CPU time 1.03 seconds
Started Jul 28 05:37:28 PM PDT 24
Finished Jul 28 05:37:30 PM PDT 24
Peak memory 223908 kb
Host smart-e8153938-b14b-49b4-aa6f-58ee537e02e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394416702 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1394416702
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2692816263
Short name T521
Test name
Test status
Simulation time 23177304 ps
CPU time 0.94 seconds
Started Jul 28 05:37:14 PM PDT 24
Finished Jul 28 05:37:15 PM PDT 24
Peak memory 215164 kb
Host smart-2a6e3eee-33cd-482c-8c30-40f0ceffe9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692816263 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2692816263
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1460098834
Short name T260
Test name
Test status
Simulation time 201081760 ps
CPU time 4.1 seconds
Started Jul 28 05:37:27 PM PDT 24
Finished Jul 28 05:37:31 PM PDT 24
Peak memory 218576 kb
Host smart-9bf50275-d5fd-41f7-a6f3-a3fc6e46aee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460098834 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1460098834
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/260.edn_genbits.2897083937
Short name T360
Test name
Test status
Simulation time 29019470 ps
CPU time 1.33 seconds
Started Jul 28 05:39:32 PM PDT 24
Finished Jul 28 05:39:33 PM PDT 24
Peak memory 218484 kb
Host smart-22050e00-c68c-4e2a-8464-865678c5bde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897083937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2897083937
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2809681957
Short name T602
Test name
Test status
Simulation time 35770376 ps
CPU time 1.16 seconds
Started Jul 28 05:39:32 PM PDT 24
Finished Jul 28 05:39:33 PM PDT 24
Peak memory 217164 kb
Host smart-532c54dd-e027-4772-8ad4-320c4415de21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809681957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2809681957
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.91109866
Short name T526
Test name
Test status
Simulation time 55636622 ps
CPU time 1.08 seconds
Started Jul 28 05:39:35 PM PDT 24
Finished Jul 28 05:39:36 PM PDT 24
Peak memory 218812 kb
Host smart-614c2512-b08f-4274-9495-3ae06374e1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91109866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.91109866
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1679394460
Short name T604
Test name
Test status
Simulation time 49076762 ps
CPU time 1.07 seconds
Started Jul 28 05:39:33 PM PDT 24
Finished Jul 28 05:39:34 PM PDT 24
Peak memory 217120 kb
Host smart-0ef4a03d-f59a-4fe5-a30c-f7c9fc302b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679394460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1679394460
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3408756152
Short name T815
Test name
Test status
Simulation time 145383941 ps
CPU time 1.26 seconds
Started Jul 28 05:39:39 PM PDT 24
Finished Jul 28 05:39:41 PM PDT 24
Peak memory 218436 kb
Host smart-0ac430aa-1c11-4af1-ad14-287bc305f4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408756152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3408756152
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3864846836
Short name T369
Test name
Test status
Simulation time 212060188 ps
CPU time 1.49 seconds
Started Jul 28 05:39:33 PM PDT 24
Finished Jul 28 05:39:35 PM PDT 24
Peak memory 218860 kb
Host smart-3122b7cc-68ee-4cc4-ad8a-4028393bde7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864846836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3864846836
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.4227021102
Short name T375
Test name
Test status
Simulation time 93623920 ps
CPU time 1.16 seconds
Started Jul 28 05:39:32 PM PDT 24
Finished Jul 28 05:39:34 PM PDT 24
Peak memory 217252 kb
Host smart-8fb0dbf3-1ebd-4eb3-894e-4200df118f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227021102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.4227021102
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1676225551
Short name T789
Test name
Test status
Simulation time 35038119 ps
CPU time 1.47 seconds
Started Jul 28 05:39:30 PM PDT 24
Finished Jul 28 05:39:31 PM PDT 24
Peak memory 218380 kb
Host smart-0f4d010c-4cd6-47ea-9f80-779ecef58d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676225551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1676225551
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1541739939
Short name T660
Test name
Test status
Simulation time 41485090 ps
CPU time 1.55 seconds
Started Jul 28 05:39:31 PM PDT 24
Finished Jul 28 05:39:33 PM PDT 24
Peak memory 218364 kb
Host smart-36ff6eac-d4d6-4139-85fc-c16d0c16f4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541739939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1541739939
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1875485531
Short name T345
Test name
Test status
Simulation time 46051146 ps
CPU time 1.43 seconds
Started Jul 28 05:39:36 PM PDT 24
Finished Jul 28 05:39:38 PM PDT 24
Peak memory 218952 kb
Host smart-622c35e7-034d-4db5-94d0-977bf9ef7689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875485531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1875485531
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.4262527984
Short name T438
Test name
Test status
Simulation time 23830627 ps
CPU time 0.89 seconds
Started Jul 28 05:37:20 PM PDT 24
Finished Jul 28 05:37:21 PM PDT 24
Peak memory 214772 kb
Host smart-52ace5ac-034b-4be6-a90d-b8381d85b495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262527984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.4262527984
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1160743176
Short name T119
Test name
Test status
Simulation time 13718036 ps
CPU time 0.97 seconds
Started Jul 28 05:37:21 PM PDT 24
Finished Jul 28 05:37:22 PM PDT 24
Peak memory 216256 kb
Host smart-10bab24f-db78-4ad6-8a1d-3440c865988b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160743176 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1160743176
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.438255052
Short name T718
Test name
Test status
Simulation time 51991258 ps
CPU time 1.06 seconds
Started Jul 28 05:37:20 PM PDT 24
Finished Jul 28 05:37:21 PM PDT 24
Peak memory 218480 kb
Host smart-e6458e83-21ad-49e2-8f89-c69c24c9592f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438255052 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.438255052
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1789292739
Short name T782
Test name
Test status
Simulation time 31639131 ps
CPU time 0.87 seconds
Started Jul 28 05:37:22 PM PDT 24
Finished Jul 28 05:37:23 PM PDT 24
Peak memory 218060 kb
Host smart-682b0e29-f6e3-4ea4-bac6-2e1151375918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789292739 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1789292739
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.599906871
Short name T392
Test name
Test status
Simulation time 90875888 ps
CPU time 1.21 seconds
Started Jul 28 05:37:17 PM PDT 24
Finished Jul 28 05:37:18 PM PDT 24
Peak memory 217176 kb
Host smart-677dc73b-7a46-475f-8f61-6fd14649bb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599906871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.599906871
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.215306327
Short name T111
Test name
Test status
Simulation time 41171572 ps
CPU time 0.85 seconds
Started Jul 28 05:37:20 PM PDT 24
Finished Jul 28 05:37:21 PM PDT 24
Peak memory 215500 kb
Host smart-a0186b34-c9ff-497d-bf02-a0a83a07f7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215306327 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.215306327
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3005240842
Short name T386
Test name
Test status
Simulation time 48812388 ps
CPU time 1.01 seconds
Started Jul 28 05:37:17 PM PDT 24
Finished Jul 28 05:37:18 PM PDT 24
Peak memory 215152 kb
Host smart-c911ba42-8d0b-4380-9b70-3053daaacfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005240842 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3005240842
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1603507374
Short name T780
Test name
Test status
Simulation time 349385609 ps
CPU time 6.8 seconds
Started Jul 28 05:37:19 PM PDT 24
Finished Jul 28 05:37:26 PM PDT 24
Peak memory 217180 kb
Host smart-26ffad3a-ab52-46a9-bdd0-309a8be589e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603507374 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1603507374
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3451622169
Short name T253
Test name
Test status
Simulation time 81693126949 ps
CPU time 953.77 seconds
Started Jul 28 05:37:23 PM PDT 24
Finished Jul 28 05:53:17 PM PDT 24
Peak memory 221568 kb
Host smart-df95c006-4557-47e4-b855-ac7bd88e0e45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451622169 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3451622169
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1713629497
Short name T432
Test name
Test status
Simulation time 44848929 ps
CPU time 1.66 seconds
Started Jul 28 05:39:32 PM PDT 24
Finished Jul 28 05:39:34 PM PDT 24
Peak memory 218452 kb
Host smart-9861bc5e-ee8b-4ae7-85bc-eed466063ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713629497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1713629497
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1640357466
Short name T863
Test name
Test status
Simulation time 20978766 ps
CPU time 1.09 seconds
Started Jul 28 05:39:44 PM PDT 24
Finished Jul 28 05:39:46 PM PDT 24
Peak memory 217288 kb
Host smart-0a187bda-80f3-4a14-af8f-51cd33be180a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640357466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1640357466
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1985860319
Short name T686
Test name
Test status
Simulation time 68129611 ps
CPU time 1.15 seconds
Started Jul 28 05:39:37 PM PDT 24
Finished Jul 28 05:39:38 PM PDT 24
Peak memory 217048 kb
Host smart-418b38fe-9640-421b-84a9-42e9768080f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985860319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1985860319
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.353046386
Short name T600
Test name
Test status
Simulation time 49003077 ps
CPU time 1.6 seconds
Started Jul 28 05:39:36 PM PDT 24
Finished Jul 28 05:39:37 PM PDT 24
Peak memory 218464 kb
Host smart-e985fbf0-c470-4186-85a9-47f7a506c3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353046386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.353046386
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3929155877
Short name T824
Test name
Test status
Simulation time 145784249 ps
CPU time 1.18 seconds
Started Jul 28 05:39:36 PM PDT 24
Finished Jul 28 05:39:38 PM PDT 24
Peak memory 219864 kb
Host smart-bdbc8393-5d55-46ee-a0a3-a504966128de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929155877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3929155877
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3584413773
Short name T482
Test name
Test status
Simulation time 56340634 ps
CPU time 1.32 seconds
Started Jul 28 05:39:35 PM PDT 24
Finished Jul 28 05:39:37 PM PDT 24
Peak memory 217032 kb
Host smart-f4286b9e-a0bb-48b6-b8a9-bc27df81c3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584413773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3584413773
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.4055050421
Short name T645
Test name
Test status
Simulation time 35665009 ps
CPU time 1.2 seconds
Started Jul 28 05:39:35 PM PDT 24
Finished Jul 28 05:39:36 PM PDT 24
Peak memory 217168 kb
Host smart-c7f6e8d2-441a-410e-a917-612a5daf52d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055050421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.4055050421
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2209128316
Short name T11
Test name
Test status
Simulation time 33021143 ps
CPU time 1.36 seconds
Started Jul 28 05:39:37 PM PDT 24
Finished Jul 28 05:39:38 PM PDT 24
Peak memory 219696 kb
Host smart-0dc46cb7-aad1-4a49-916c-abf22ea09f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209128316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2209128316
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.901521190
Short name T889
Test name
Test status
Simulation time 47611448 ps
CPU time 1.67 seconds
Started Jul 28 05:39:34 PM PDT 24
Finished Jul 28 05:39:36 PM PDT 24
Peak memory 218364 kb
Host smart-91c9ea9f-b0ce-4369-b9a9-355a6ec52cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901521190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.901521190
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3715558234
Short name T381
Test name
Test status
Simulation time 39286235 ps
CPU time 1.09 seconds
Started Jul 28 05:39:35 PM PDT 24
Finished Jul 28 05:39:36 PM PDT 24
Peak memory 217128 kb
Host smart-e8106e51-3c94-4fbb-bb59-da7ae801a3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715558234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3715558234
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.68706837
Short name T709
Test name
Test status
Simulation time 25549340 ps
CPU time 1.24 seconds
Started Jul 28 05:37:20 PM PDT 24
Finished Jul 28 05:37:21 PM PDT 24
Peak memory 219384 kb
Host smart-f4c4a64d-446a-4e22-b961-85c0df590406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68706837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.68706837
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2827354569
Short name T3
Test name
Test status
Simulation time 29688055 ps
CPU time 0.84 seconds
Started Jul 28 05:37:22 PM PDT 24
Finished Jul 28 05:37:23 PM PDT 24
Peak memory 206624 kb
Host smart-9525a7d1-778a-4024-ac64-b5fdfe4178e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827354569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2827354569
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2667312619
Short name T816
Test name
Test status
Simulation time 26155621 ps
CPU time 0.81 seconds
Started Jul 28 05:37:20 PM PDT 24
Finished Jul 28 05:37:21 PM PDT 24
Peak memory 216100 kb
Host smart-41bf65f0-cee4-4e4e-80d1-384ab9b2e6a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667312619 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2667312619
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.304612829
Short name T458
Test name
Test status
Simulation time 54654413 ps
CPU time 1.32 seconds
Started Jul 28 05:37:21 PM PDT 24
Finished Jul 28 05:37:22 PM PDT 24
Peak memory 218416 kb
Host smart-42b55838-83c9-4326-98f4-fed3384b71f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304612829 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.304612829
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.4294618239
Short name T166
Test name
Test status
Simulation time 26480524 ps
CPU time 1.31 seconds
Started Jul 28 05:37:22 PM PDT 24
Finished Jul 28 05:37:23 PM PDT 24
Peak memory 220588 kb
Host smart-47834306-d3f2-400f-8462-54916173b630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294618239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.4294618239
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1971472399
Short name T423
Test name
Test status
Simulation time 81010594 ps
CPU time 1.25 seconds
Started Jul 28 05:37:21 PM PDT 24
Finished Jul 28 05:37:23 PM PDT 24
Peak memory 219800 kb
Host smart-4f9ff4b8-6a59-4c56-95ec-31faf393b6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971472399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1971472399
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.504348096
Short name T383
Test name
Test status
Simulation time 29376764 ps
CPU time 1.01 seconds
Started Jul 28 05:37:24 PM PDT 24
Finished Jul 28 05:37:26 PM PDT 24
Peak memory 215520 kb
Host smart-fa4671c6-2405-4671-bd46-3664ee902b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504348096 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.504348096
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1474495613
Short name T762
Test name
Test status
Simulation time 14546026 ps
CPU time 0.99 seconds
Started Jul 28 05:37:24 PM PDT 24
Finished Jul 28 05:37:25 PM PDT 24
Peak memory 215188 kb
Host smart-15c4092b-afcf-4b90-b427-94e776ac53de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474495613 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1474495613
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1349334428
Short name T261
Test name
Test status
Simulation time 176567325 ps
CPU time 1.95 seconds
Started Jul 28 05:37:20 PM PDT 24
Finished Jul 28 05:37:22 PM PDT 24
Peak memory 217260 kb
Host smart-54510927-f0c3-4056-9362-5756914573c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349334428 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1349334428
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2508364288
Short name T733
Test name
Test status
Simulation time 70892709513 ps
CPU time 460.41 seconds
Started Jul 28 05:37:21 PM PDT 24
Finished Jul 28 05:45:01 PM PDT 24
Peak memory 218552 kb
Host smart-d4003f01-1572-4d4f-bffd-38017fe77b3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508364288 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2508364288
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1990913213
Short name T985
Test name
Test status
Simulation time 33070344 ps
CPU time 1.39 seconds
Started Jul 28 05:39:38 PM PDT 24
Finished Jul 28 05:39:40 PM PDT 24
Peak memory 218496 kb
Host smart-87e941f8-7c54-49e4-b38c-4e63bf858e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990913213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1990913213
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2549001715
Short name T618
Test name
Test status
Simulation time 38715460 ps
CPU time 1.46 seconds
Started Jul 28 05:39:37 PM PDT 24
Finished Jul 28 05:39:38 PM PDT 24
Peak memory 217216 kb
Host smart-3b3f7acd-69b9-4014-a8b3-22407cffe318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549001715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2549001715
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1128538211
Short name T736
Test name
Test status
Simulation time 57845148 ps
CPU time 1.41 seconds
Started Jul 28 05:39:37 PM PDT 24
Finished Jul 28 05:39:38 PM PDT 24
Peak memory 218484 kb
Host smart-2cea8abd-8789-4c0a-894c-ee435181cb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128538211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1128538211
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1299416943
Short name T429
Test name
Test status
Simulation time 45598490 ps
CPU time 1.8 seconds
Started Jul 28 05:39:35 PM PDT 24
Finished Jul 28 05:39:37 PM PDT 24
Peak memory 218400 kb
Host smart-b03de229-9aa5-44f6-955d-505e8bfab2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299416943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1299416943
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.547724647
Short name T534
Test name
Test status
Simulation time 34327945 ps
CPU time 1.31 seconds
Started Jul 28 05:39:36 PM PDT 24
Finished Jul 28 05:39:37 PM PDT 24
Peak memory 218404 kb
Host smart-d2141aab-1dbd-4a63-99bb-88dc1633a4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547724647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.547724647
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.4117483366
Short name T649
Test name
Test status
Simulation time 41365132 ps
CPU time 1.11 seconds
Started Jul 28 05:39:39 PM PDT 24
Finished Jul 28 05:39:41 PM PDT 24
Peak memory 217184 kb
Host smart-41082af6-b47b-4ebb-b891-41be10a2b9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117483366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.4117483366
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2147083589
Short name T804
Test name
Test status
Simulation time 74344036 ps
CPU time 1.23 seconds
Started Jul 28 05:39:37 PM PDT 24
Finished Jul 28 05:39:39 PM PDT 24
Peak memory 219728 kb
Host smart-52116b69-cc97-4eae-97bd-1b780e9891b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147083589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2147083589
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2961054260
Short name T756
Test name
Test status
Simulation time 60246153 ps
CPU time 1.49 seconds
Started Jul 28 05:39:49 PM PDT 24
Finished Jul 28 05:39:50 PM PDT 24
Peak memory 218324 kb
Host smart-e6e2a03e-3603-49c3-b49a-ed0fa1a7b69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961054260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2961054260
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.4212850504
Short name T843
Test name
Test status
Simulation time 50734639 ps
CPU time 1.22 seconds
Started Jul 28 05:39:36 PM PDT 24
Finished Jul 28 05:39:38 PM PDT 24
Peak memory 219692 kb
Host smart-a590a9aa-ae28-4d82-9c06-51989d057951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212850504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.4212850504
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2059529115
Short name T579
Test name
Test status
Simulation time 99032325 ps
CPU time 1.08 seconds
Started Jul 28 05:37:20 PM PDT 24
Finished Jul 28 05:37:22 PM PDT 24
Peak memory 219368 kb
Host smart-c7da8e50-089c-426b-b929-7838a94ba700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059529115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2059529115
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3420952520
Short name T909
Test name
Test status
Simulation time 44998920 ps
CPU time 0.96 seconds
Started Jul 28 05:37:21 PM PDT 24
Finished Jul 28 05:37:22 PM PDT 24
Peak memory 206644 kb
Host smart-a8b8e0ea-283f-4105-b0e4-c9922df25d09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420952520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3420952520
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.911491588
Short name T567
Test name
Test status
Simulation time 67164009 ps
CPU time 0.97 seconds
Started Jul 28 05:37:22 PM PDT 24
Finished Jul 28 05:37:23 PM PDT 24
Peak memory 218388 kb
Host smart-dc1e7b8f-ae27-4e67-bc5a-65e95b848631
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911491588 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.911491588
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1233333228
Short name T71
Test name
Test status
Simulation time 19660421 ps
CPU time 1.06 seconds
Started Jul 28 05:37:23 PM PDT 24
Finished Jul 28 05:37:24 PM PDT 24
Peak memory 218644 kb
Host smart-5ad96f7b-c8bb-4688-b805-fb39d59b611e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233333228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1233333228
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1919790994
Short name T547
Test name
Test status
Simulation time 59235626 ps
CPU time 1.02 seconds
Started Jul 28 05:37:20 PM PDT 24
Finished Jul 28 05:37:21 PM PDT 24
Peak memory 217320 kb
Host smart-f6ab91a5-eb27-4c57-bc34-f5f924b29e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919790994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1919790994
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.798615634
Short name T109
Test name
Test status
Simulation time 32698139 ps
CPU time 0.88 seconds
Started Jul 28 05:37:24 PM PDT 24
Finished Jul 28 05:37:25 PM PDT 24
Peak memory 215520 kb
Host smart-a2619725-4adc-4ec8-9182-72b037f4144b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798615634 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.798615634
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2242028301
Short name T430
Test name
Test status
Simulation time 15660898 ps
CPU time 0.97 seconds
Started Jul 28 05:37:23 PM PDT 24
Finished Jul 28 05:37:24 PM PDT 24
Peak memory 215164 kb
Host smart-d35ace8e-1940-4095-b1a4-8bc67e91ce06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242028301 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2242028301
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2001609652
Short name T42
Test name
Test status
Simulation time 1272456523 ps
CPU time 4.27 seconds
Started Jul 28 05:37:35 PM PDT 24
Finished Jul 28 05:37:39 PM PDT 24
Peak memory 215248 kb
Host smart-32b3fa8f-b682-4066-bdaa-6b9b74ee51df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001609652 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2001609652
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/290.edn_genbits.1910991409
Short name T69
Test name
Test status
Simulation time 23989842 ps
CPU time 1.24 seconds
Started Jul 28 05:39:37 PM PDT 24
Finished Jul 28 05:39:38 PM PDT 24
Peak memory 218344 kb
Host smart-b7244d3f-828c-42b1-82c0-c34c6cab0a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910991409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1910991409
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.756138485
Short name T657
Test name
Test status
Simulation time 63237540 ps
CPU time 1.03 seconds
Started Jul 28 05:39:36 PM PDT 24
Finished Jul 28 05:39:38 PM PDT 24
Peak memory 215156 kb
Host smart-c0cb5b63-7f87-4372-b600-296cf5c3692e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756138485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.756138485
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3559708861
Short name T875
Test name
Test status
Simulation time 91578939 ps
CPU time 1.44 seconds
Started Jul 28 05:39:35 PM PDT 24
Finished Jul 28 05:39:37 PM PDT 24
Peak memory 215196 kb
Host smart-c20b2591-f385-4290-b89d-2970de18f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559708861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3559708861
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2841611396
Short name T566
Test name
Test status
Simulation time 70120063 ps
CPU time 1.12 seconds
Started Jul 28 05:39:46 PM PDT 24
Finished Jul 28 05:39:47 PM PDT 24
Peak memory 217224 kb
Host smart-08223095-1791-48e4-8274-7a9181c1ab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841611396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2841611396
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.4011662273
Short name T86
Test name
Test status
Simulation time 40556031 ps
CPU time 1.61 seconds
Started Jul 28 05:39:43 PM PDT 24
Finished Jul 28 05:39:45 PM PDT 24
Peak memory 218428 kb
Host smart-804e3347-0ac1-40f7-8adb-624de3cc9f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011662273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.4011662273
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3218706604
Short name T758
Test name
Test status
Simulation time 32283830 ps
CPU time 1.29 seconds
Started Jul 28 05:39:36 PM PDT 24
Finished Jul 28 05:39:38 PM PDT 24
Peak memory 217180 kb
Host smart-9d1a8a5f-242e-4a72-9a09-6d9ecfced515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218706604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3218706604
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.605581105
Short name T814
Test name
Test status
Simulation time 33445782 ps
CPU time 1.25 seconds
Started Jul 28 05:39:44 PM PDT 24
Finished Jul 28 05:39:45 PM PDT 24
Peak memory 218316 kb
Host smart-8418fbb3-64ca-43e4-9c69-014223c7b4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605581105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.605581105
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.232345995
Short name T394
Test name
Test status
Simulation time 38461039 ps
CPU time 1.55 seconds
Started Jul 28 05:39:42 PM PDT 24
Finished Jul 28 05:39:44 PM PDT 24
Peak memory 218476 kb
Host smart-da892fba-b688-49fb-aa08-0a3386067a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232345995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.232345995
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2612719216
Short name T850
Test name
Test status
Simulation time 36451887 ps
CPU time 1.53 seconds
Started Jul 28 05:39:34 PM PDT 24
Finished Jul 28 05:39:36 PM PDT 24
Peak memory 218596 kb
Host smart-48991300-af73-4060-8abf-b1b4c23234fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612719216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2612719216
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1796337273
Short name T620
Test name
Test status
Simulation time 43550031 ps
CPU time 1.51 seconds
Started Jul 28 05:39:37 PM PDT 24
Finished Jul 28 05:39:39 PM PDT 24
Peak memory 219496 kb
Host smart-64451813-97c0-4c3a-8253-5e5c219bccfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796337273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1796337273
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1194316419
Short name T742
Test name
Test status
Simulation time 21421033 ps
CPU time 1.17 seconds
Started Jul 28 05:36:40 PM PDT 24
Finished Jul 28 05:36:41 PM PDT 24
Peak memory 220572 kb
Host smart-4455a506-4b79-4187-8061-e68dc9842742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194316419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1194316419
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.255042827
Short name T561
Test name
Test status
Simulation time 43325038 ps
CPU time 0.86 seconds
Started Jul 28 05:36:41 PM PDT 24
Finished Jul 28 05:36:42 PM PDT 24
Peak memory 206440 kb
Host smart-eb822ee5-3a9b-4086-b347-03cce469dd7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255042827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.255042827
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1143576136
Short name T312
Test name
Test status
Simulation time 31804099 ps
CPU time 0.91 seconds
Started Jul 28 05:36:41 PM PDT 24
Finished Jul 28 05:36:42 PM PDT 24
Peak memory 215808 kb
Host smart-d9dc61e3-98cc-40b9-af9f-eaf711d69ece
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143576136 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1143576136
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2144524531
Short name T462
Test name
Test status
Simulation time 32432013 ps
CPU time 1 seconds
Started Jul 28 05:36:41 PM PDT 24
Finished Jul 28 05:36:42 PM PDT 24
Peak memory 218428 kb
Host smart-c88faae2-6800-44bf-bcba-c26d7d8aa5d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144524531 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2144524531
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3285770483
Short name T502
Test name
Test status
Simulation time 29510230 ps
CPU time 1 seconds
Started Jul 28 05:36:42 PM PDT 24
Finished Jul 28 05:36:43 PM PDT 24
Peak memory 223644 kb
Host smart-5a83e02e-51d1-42b9-b98d-d3fea32e8292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285770483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3285770483
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1269609444
Short name T501
Test name
Test status
Simulation time 20668391 ps
CPU time 1.06 seconds
Started Jul 28 05:36:32 PM PDT 24
Finished Jul 28 05:36:34 PM PDT 24
Peak memory 217300 kb
Host smart-01f22bbd-297f-4d65-b2da-317a5cdf31ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269609444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1269609444
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1512515519
Short name T950
Test name
Test status
Simulation time 53999412 ps
CPU time 0.88 seconds
Started Jul 28 05:36:39 PM PDT 24
Finished Jul 28 05:36:40 PM PDT 24
Peak memory 215200 kb
Host smart-c2f44f52-0fc3-4e50-8414-7107cacedb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512515519 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1512515519
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1252938234
Short name T97
Test name
Test status
Simulation time 84556280 ps
CPU time 0.91 seconds
Started Jul 28 05:36:37 PM PDT 24
Finished Jul 28 05:36:38 PM PDT 24
Peak memory 206968 kb
Host smart-8e3448bd-250a-4d03-8f24-c58e935012fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252938234 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1252938234
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.4007075337
Short name T426
Test name
Test status
Simulation time 51752685 ps
CPU time 0.95 seconds
Started Jul 28 05:36:36 PM PDT 24
Finished Jul 28 05:36:37 PM PDT 24
Peak memory 215240 kb
Host smart-5deee52d-1513-45fa-a0b2-a23ac97efcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007075337 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.4007075337
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.4047434842
Short name T444
Test name
Test status
Simulation time 61976673 ps
CPU time 1.78 seconds
Started Jul 28 05:36:35 PM PDT 24
Finished Jul 28 05:36:37 PM PDT 24
Peak memory 215128 kb
Host smart-ac755a70-21f8-4735-b8ca-34c070d09839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047434842 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.4047434842
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1535313585
Short name T247
Test name
Test status
Simulation time 398855957759 ps
CPU time 2104.46 seconds
Started Jul 28 05:36:35 PM PDT 24
Finished Jul 28 06:11:39 PM PDT 24
Peak memory 227088 kb
Host smart-35f424fd-d638-4b1e-9450-7813a2348251
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535313585 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1535313585
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1629371505
Short name T765
Test name
Test status
Simulation time 23525698 ps
CPU time 1.15 seconds
Started Jul 28 05:37:25 PM PDT 24
Finished Jul 28 05:37:26 PM PDT 24
Peak memory 218652 kb
Host smart-7bfabacb-c1ec-463e-b2b9-f56c57d34015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629371505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1629371505
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.782287916
Short name T525
Test name
Test status
Simulation time 72519975 ps
CPU time 1.09 seconds
Started Jul 28 05:37:22 PM PDT 24
Finished Jul 28 05:37:23 PM PDT 24
Peak memory 206676 kb
Host smart-4d87fc93-7a03-4b3c-a9b7-d412047964b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782287916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.782287916
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3002461433
Short name T821
Test name
Test status
Simulation time 52968268 ps
CPU time 1.09 seconds
Started Jul 28 05:37:24 PM PDT 24
Finished Jul 28 05:37:25 PM PDT 24
Peak memory 216732 kb
Host smart-b2f36379-5787-4403-9904-f0d968a630a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002461433 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3002461433
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2982509744
Short name T51
Test name
Test status
Simulation time 19707501 ps
CPU time 1.11 seconds
Started Jul 28 05:37:23 PM PDT 24
Finished Jul 28 05:37:24 PM PDT 24
Peak memory 223896 kb
Host smart-d72447a1-4d4f-41a2-9dec-ed61796eec58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982509744 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2982509744
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3889297584
Short name T594
Test name
Test status
Simulation time 32393144 ps
CPU time 1.09 seconds
Started Jul 28 05:37:22 PM PDT 24
Finished Jul 28 05:37:23 PM PDT 24
Peak memory 219784 kb
Host smart-79fabba5-64b8-4dce-9ecb-3fedf542727a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889297584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3889297584
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3914795947
Short name T868
Test name
Test status
Simulation time 25361957 ps
CPU time 1.15 seconds
Started Jul 28 05:37:20 PM PDT 24
Finished Jul 28 05:37:21 PM PDT 24
Peak memory 215372 kb
Host smart-5103f2d5-e416-4fe8-b90f-fcb6581b896c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914795947 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3914795947
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2071078814
Short name T403
Test name
Test status
Simulation time 65820468 ps
CPU time 0.92 seconds
Started Jul 28 05:37:22 PM PDT 24
Finished Jul 28 05:37:23 PM PDT 24
Peak memory 215104 kb
Host smart-b38a3444-c977-4ca7-bd3f-4f301552b3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071078814 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2071078814
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.816138938
Short name T872
Test name
Test status
Simulation time 206248972 ps
CPU time 2.53 seconds
Started Jul 28 05:37:23 PM PDT 24
Finished Jul 28 05:37:26 PM PDT 24
Peak memory 217424 kb
Host smart-d5423559-3c4a-4124-b5ae-3c0c7475885b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816138938 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.816138938
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3896183320
Short name T963
Test name
Test status
Simulation time 37143843418 ps
CPU time 959.88 seconds
Started Jul 28 05:37:21 PM PDT 24
Finished Jul 28 05:53:21 PM PDT 24
Peak memory 220296 kb
Host smart-c7c5cc33-2a54-47d2-bf62-7e7642ff470d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896183320 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3896183320
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3797847979
Short name T309
Test name
Test status
Simulation time 304383633 ps
CPU time 1.33 seconds
Started Jul 28 05:37:30 PM PDT 24
Finished Jul 28 05:37:31 PM PDT 24
Peak memory 219324 kb
Host smart-57c416a3-f370-4fff-80b2-27b0fa58d0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797847979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3797847979
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2462609505
Short name T599
Test name
Test status
Simulation time 24152822 ps
CPU time 0.95 seconds
Started Jul 28 05:37:25 PM PDT 24
Finished Jul 28 05:37:26 PM PDT 24
Peak memory 206652 kb
Host smart-0b9cdcc1-d157-4588-8e4b-c839c99c037d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462609505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2462609505
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3719741784
Short name T79
Test name
Test status
Simulation time 51412147 ps
CPU time 0.82 seconds
Started Jul 28 05:37:27 PM PDT 24
Finished Jul 28 05:37:28 PM PDT 24
Peak memory 216084 kb
Host smart-1de9757a-5314-4f35-a91a-f33fef1ce54b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719741784 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3719741784
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.532118339
Short name T644
Test name
Test status
Simulation time 52758639 ps
CPU time 1.09 seconds
Started Jul 28 05:37:26 PM PDT 24
Finished Jul 28 05:37:27 PM PDT 24
Peak memory 216760 kb
Host smart-80bc7a95-06b6-42b4-8da8-70c484361cdf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532118339 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.532118339
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1298844758
Short name T639
Test name
Test status
Simulation time 34549418 ps
CPU time 0.9 seconds
Started Jul 28 05:37:26 PM PDT 24
Finished Jul 28 05:37:27 PM PDT 24
Peak memory 218136 kb
Host smart-09b6d3cf-40ee-47cd-a271-21cef5ec2031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298844758 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1298844758
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.275751137
Short name T411
Test name
Test status
Simulation time 29894878 ps
CPU time 1.41 seconds
Started Jul 28 05:37:23 PM PDT 24
Finished Jul 28 05:37:24 PM PDT 24
Peak memory 217104 kb
Host smart-1170ef28-fdc8-4b3f-88f2-3b40ccb64101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275751137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.275751137
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2244314139
Short name T570
Test name
Test status
Simulation time 28119449 ps
CPU time 1.08 seconds
Started Jul 28 05:37:29 PM PDT 24
Finished Jul 28 05:37:31 PM PDT 24
Peak memory 223844 kb
Host smart-bd99e1f2-85d0-4d61-83fd-297a8216951a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244314139 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2244314139
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1286608879
Short name T640
Test name
Test status
Simulation time 61505257 ps
CPU time 0.86 seconds
Started Jul 28 05:37:22 PM PDT 24
Finished Jul 28 05:37:23 PM PDT 24
Peak memory 215148 kb
Host smart-3183580e-1fec-402b-9aa5-40bf62dbf962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286608879 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1286608879
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4240741924
Short name T810
Test name
Test status
Simulation time 576418377 ps
CPU time 3.63 seconds
Started Jul 28 05:37:31 PM PDT 24
Finished Jul 28 05:37:35 PM PDT 24
Peak memory 217024 kb
Host smart-f0611399-0557-4a64-b6c4-538bbba0d7a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240741924 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4240741924
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3442813067
Short name T853
Test name
Test status
Simulation time 83326798593 ps
CPU time 1142.78 seconds
Started Jul 28 05:37:26 PM PDT 24
Finished Jul 28 05:56:29 PM PDT 24
Peak memory 223588 kb
Host smart-432b6cd9-0dc0-4366-96d0-dcb5071c2c62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442813067 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3442813067
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2032449448
Short name T898
Test name
Test status
Simulation time 24979181 ps
CPU time 1.14 seconds
Started Jul 28 05:37:29 PM PDT 24
Finished Jul 28 05:37:30 PM PDT 24
Peak memory 218244 kb
Host smart-8bd36dc3-c9e0-418d-a4d7-ab870e2b2d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032449448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2032449448
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2641807071
Short name T540
Test name
Test status
Simulation time 42258079 ps
CPU time 0.82 seconds
Started Jul 28 05:37:26 PM PDT 24
Finished Jul 28 05:37:27 PM PDT 24
Peak memory 206392 kb
Host smart-7c964fe9-77e8-4d14-878a-f78752c46f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641807071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2641807071
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.57732661
Short name T238
Test name
Test status
Simulation time 24360526 ps
CPU time 0.9 seconds
Started Jul 28 05:37:23 PM PDT 24
Finished Jul 28 05:37:24 PM PDT 24
Peak memory 216272 kb
Host smart-063a1c02-9432-4a1c-a9e0-cc7e0766880d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57732661 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.57732661
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1285714837
Short name T693
Test name
Test status
Simulation time 125435334 ps
CPU time 1.25 seconds
Started Jul 28 05:37:28 PM PDT 24
Finished Jul 28 05:37:29 PM PDT 24
Peak memory 216912 kb
Host smart-e0c1e9a8-6e14-447c-b8f0-007d36b44dee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285714837 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1285714837
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3650470512
Short name T488
Test name
Test status
Simulation time 22133501 ps
CPU time 0.99 seconds
Started Jul 28 05:37:24 PM PDT 24
Finished Jul 28 05:37:25 PM PDT 24
Peak memory 223840 kb
Host smart-16c676b4-079f-4503-936e-f139f347d9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650470512 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3650470512
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2298444512
Short name T731
Test name
Test status
Simulation time 51858710 ps
CPU time 1.18 seconds
Started Jul 28 05:37:30 PM PDT 24
Finished Jul 28 05:37:32 PM PDT 24
Peak memory 217260 kb
Host smart-0be27d2f-09d0-49f3-b83f-12254eb37158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298444512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2298444512
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2711662975
Short name T398
Test name
Test status
Simulation time 70317807 ps
CPU time 0.86 seconds
Started Jul 28 05:37:28 PM PDT 24
Finished Jul 28 05:37:29 PM PDT 24
Peak memory 215052 kb
Host smart-337e2199-5b82-4156-80fc-16a52fbf564a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711662975 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2711662975
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1311093367
Short name T529
Test name
Test status
Simulation time 18033013 ps
CPU time 1.04 seconds
Started Jul 28 05:37:26 PM PDT 24
Finished Jul 28 05:37:27 PM PDT 24
Peak memory 215152 kb
Host smart-085c9e31-596d-4cf0-ad1d-540c0cf0971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311093367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1311093367
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1590035524
Short name T441
Test name
Test status
Simulation time 318530678 ps
CPU time 4.8 seconds
Started Jul 28 05:37:26 PM PDT 24
Finished Jul 28 05:37:31 PM PDT 24
Peak memory 217040 kb
Host smart-e16bfce5-fb1a-4b10-9c44-9dee502b1cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590035524 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1590035524
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.919941921
Short name T830
Test name
Test status
Simulation time 102916852931 ps
CPU time 2470.82 seconds
Started Jul 28 05:37:26 PM PDT 24
Finished Jul 28 06:18:38 PM PDT 24
Peak memory 233160 kb
Host smart-d0c2f315-9b25-4450-a8fb-1108c330b982
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919941921 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.919941921
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.840208442
Short name T611
Test name
Test status
Simulation time 34431134 ps
CPU time 1.2 seconds
Started Jul 28 05:37:27 PM PDT 24
Finished Jul 28 05:37:28 PM PDT 24
Peak memory 220636 kb
Host smart-b8f67033-e708-48ba-a2b7-ef933a4ce472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840208442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.840208442
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1520436728
Short name T410
Test name
Test status
Simulation time 22437400 ps
CPU time 0.97 seconds
Started Jul 28 05:37:28 PM PDT 24
Finished Jul 28 05:37:29 PM PDT 24
Peak memory 206596 kb
Host smart-f84db4a6-416b-4836-9094-96b537fe14f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520436728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1520436728
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1761308668
Short name T503
Test name
Test status
Simulation time 12230186 ps
CPU time 0.94 seconds
Started Jul 28 05:37:30 PM PDT 24
Finished Jul 28 05:37:31 PM PDT 24
Peak memory 216248 kb
Host smart-ee495eb4-dda6-4938-a51c-4c3fb9a77e25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761308668 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1761308668
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1694147586
Short name T685
Test name
Test status
Simulation time 87083553 ps
CPU time 1.15 seconds
Started Jul 28 05:37:32 PM PDT 24
Finished Jul 28 05:37:33 PM PDT 24
Peak memory 216680 kb
Host smart-711ea830-f734-4ed9-8afb-2804b98045f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694147586 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1694147586
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.722024708
Short name T227
Test name
Test status
Simulation time 20657934 ps
CPU time 1.08 seconds
Started Jul 28 05:37:28 PM PDT 24
Finished Jul 28 05:37:30 PM PDT 24
Peak memory 218264 kb
Host smart-e4e4e64e-50a1-4144-8b9e-dd9c282261e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722024708 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.722024708
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2266611666
Short name T658
Test name
Test status
Simulation time 50064785 ps
CPU time 1.59 seconds
Started Jul 28 05:37:25 PM PDT 24
Finished Jul 28 05:37:27 PM PDT 24
Peak memory 218376 kb
Host smart-71e393d0-c980-41df-abfa-eb37410f5432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266611666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2266611666
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.968064235
Short name T791
Test name
Test status
Simulation time 33905841 ps
CPU time 0.98 seconds
Started Jul 28 05:37:31 PM PDT 24
Finished Jul 28 05:37:32 PM PDT 24
Peak memory 215592 kb
Host smart-78cd1a5d-dc81-4108-b0fb-8f1f97b4dc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968064235 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.968064235
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.862601338
Short name T380
Test name
Test status
Simulation time 24863221 ps
CPU time 1 seconds
Started Jul 28 05:37:30 PM PDT 24
Finished Jul 28 05:37:31 PM PDT 24
Peak memory 215032 kb
Host smart-98137b82-4d3e-4603-9296-3d67fb6f0012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862601338 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.862601338
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1776831713
Short name T390
Test name
Test status
Simulation time 1531336900 ps
CPU time 3.97 seconds
Started Jul 28 05:37:31 PM PDT 24
Finished Jul 28 05:37:35 PM PDT 24
Peak memory 217136 kb
Host smart-22a1b9ce-072d-40cd-a676-aa0987835bd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776831713 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1776831713
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1882179597
Short name T593
Test name
Test status
Simulation time 294190477072 ps
CPU time 1832.04 seconds
Started Jul 28 05:37:26 PM PDT 24
Finished Jul 28 06:07:58 PM PDT 24
Peak memory 225284 kb
Host smart-a5fa7566-b945-49da-b856-707490743863
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882179597 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1882179597
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1055969017
Short name T41
Test name
Test status
Simulation time 24978317 ps
CPU time 1.17 seconds
Started Jul 28 05:37:31 PM PDT 24
Finished Jul 28 05:37:32 PM PDT 24
Peak memory 218316 kb
Host smart-adf4b749-dd37-463c-8eb5-9f58aeb144af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055969017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1055969017
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3279387696
Short name T974
Test name
Test status
Simulation time 84785412 ps
CPU time 0.86 seconds
Started Jul 28 05:37:27 PM PDT 24
Finished Jul 28 05:37:28 PM PDT 24
Peak memory 214608 kb
Host smart-c042ad4a-b7c8-432d-b481-e6ff2bdadb30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279387696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3279387696
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1940187436
Short name T967
Test name
Test status
Simulation time 17156856 ps
CPU time 0.85 seconds
Started Jul 28 05:37:33 PM PDT 24
Finished Jul 28 05:37:34 PM PDT 24
Peak memory 216196 kb
Host smart-faebc7d8-516e-4037-a495-32b8627a7b1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940187436 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1940187436
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2101957612
Short name T748
Test name
Test status
Simulation time 87056791 ps
CPU time 1.09 seconds
Started Jul 28 05:37:30 PM PDT 24
Finished Jul 28 05:37:31 PM PDT 24
Peak memory 219308 kb
Host smart-09efd434-0ffb-4b6f-9321-954665ae06e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101957612 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2101957612
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2638062708
Short name T141
Test name
Test status
Simulation time 21583428 ps
CPU time 0.97 seconds
Started Jul 28 05:37:30 PM PDT 24
Finished Jul 28 05:37:31 PM PDT 24
Peak memory 218464 kb
Host smart-7b87af5b-e10b-4b5e-987d-12b82ffc9068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638062708 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2638062708
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.773306862
Short name T664
Test name
Test status
Simulation time 60971360 ps
CPU time 1.32 seconds
Started Jul 28 05:37:25 PM PDT 24
Finished Jul 28 05:37:26 PM PDT 24
Peak memory 218376 kb
Host smart-61257809-d78d-4891-9035-08d6fed19ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773306862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.773306862
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.130947495
Short name T683
Test name
Test status
Simulation time 41920521 ps
CPU time 0.99 seconds
Started Jul 28 05:37:24 PM PDT 24
Finished Jul 28 05:37:26 PM PDT 24
Peak memory 215300 kb
Host smart-1ece01c1-84c7-4757-ac0d-002b86f7712f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130947495 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.130947495
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3069867798
Short name T580
Test name
Test status
Simulation time 18156837 ps
CPU time 1.07 seconds
Started Jul 28 05:37:27 PM PDT 24
Finished Jul 28 05:37:28 PM PDT 24
Peak memory 206964 kb
Host smart-670e0dfd-79dd-4e84-8059-5e2010895e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069867798 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3069867798
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.471193547
Short name T545
Test name
Test status
Simulation time 28190709 ps
CPU time 1.11 seconds
Started Jul 28 05:37:28 PM PDT 24
Finished Jul 28 05:37:29 PM PDT 24
Peak memory 215184 kb
Host smart-c16b5db1-f90f-4035-a553-8d7dae6ce40d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471193547 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.471193547
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_alert.413973374
Short name T180
Test name
Test status
Simulation time 31185686 ps
CPU time 1.25 seconds
Started Jul 28 05:37:33 PM PDT 24
Finished Jul 28 05:37:34 PM PDT 24
Peak memory 219012 kb
Host smart-a9ad3473-b321-48ce-bfd3-9e0459bf6edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413973374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.413973374
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2939973874
Short name T710
Test name
Test status
Simulation time 93297695 ps
CPU time 0.94 seconds
Started Jul 28 05:37:32 PM PDT 24
Finished Jul 28 05:37:33 PM PDT 24
Peak memory 206632 kb
Host smart-355b594b-bf0c-4c48-84d7-2f8fa72babaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939973874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2939973874
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.630238270
Short name T711
Test name
Test status
Simulation time 16135410 ps
CPU time 0.85 seconds
Started Jul 28 05:37:32 PM PDT 24
Finished Jul 28 05:37:33 PM PDT 24
Peak memory 215228 kb
Host smart-1e9dfb56-d66b-47d3-9ce6-8fbc7c205782
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630238270 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.630238270
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1777154853
Short name T170
Test name
Test status
Simulation time 57048691 ps
CPU time 1.11 seconds
Started Jul 28 05:37:32 PM PDT 24
Finished Jul 28 05:37:34 PM PDT 24
Peak memory 216916 kb
Host smart-9d7127a0-1268-48f3-badc-e62cd5240801
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777154853 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1777154853
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3719273646
Short name T839
Test name
Test status
Simulation time 22043823 ps
CPU time 1.06 seconds
Started Jul 28 05:37:30 PM PDT 24
Finished Jul 28 05:37:31 PM PDT 24
Peak memory 219576 kb
Host smart-8b892078-cfd6-4ff6-9f8f-696d4924f6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719273646 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3719273646
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1607914779
Short name T769
Test name
Test status
Simulation time 33900700 ps
CPU time 1.29 seconds
Started Jul 28 05:37:29 PM PDT 24
Finished Jul 28 05:37:30 PM PDT 24
Peak memory 217132 kb
Host smart-b0804311-4648-4323-aa4a-58edccce6ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607914779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1607914779
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.895525830
Short name T771
Test name
Test status
Simulation time 26437678 ps
CPU time 0.94 seconds
Started Jul 28 05:37:34 PM PDT 24
Finished Jul 28 05:37:35 PM PDT 24
Peak memory 215236 kb
Host smart-29b844c9-0300-4c01-8d26-93885f0d0108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895525830 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.895525830
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2222703704
Short name T554
Test name
Test status
Simulation time 17155472 ps
CPU time 1.03 seconds
Started Jul 28 05:37:30 PM PDT 24
Finished Jul 28 05:37:31 PM PDT 24
Peak memory 215064 kb
Host smart-2f14ca07-dad2-4884-898b-4ade6d7f4e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222703704 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2222703704
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2053891310
Short name T376
Test name
Test status
Simulation time 149721772 ps
CPU time 1.44 seconds
Started Jul 28 05:37:31 PM PDT 24
Finished Jul 28 05:37:33 PM PDT 24
Peak memory 215180 kb
Host smart-e83261d6-cc9b-4b3f-a008-e50e5c725af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053891310 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2053891310
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2068899683
Short name T457
Test name
Test status
Simulation time 85774543580 ps
CPU time 2192.96 seconds
Started Jul 28 05:37:33 PM PDT 24
Finished Jul 28 06:14:06 PM PDT 24
Peak memory 230836 kb
Host smart-7640a5f1-76de-4a65-9ac8-8ee246e53837
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068899683 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2068899683
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1506098295
Short name T725
Test name
Test status
Simulation time 32732892 ps
CPU time 1.31 seconds
Started Jul 28 05:37:34 PM PDT 24
Finished Jul 28 05:37:35 PM PDT 24
Peak memory 215492 kb
Host smart-91fd0737-e840-493e-8bd8-fb813cc7f1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506098295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1506098295
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2794742833
Short name T738
Test name
Test status
Simulation time 27352854 ps
CPU time 0.94 seconds
Started Jul 28 05:37:34 PM PDT 24
Finished Jul 28 05:37:35 PM PDT 24
Peak memory 206660 kb
Host smart-c0240f87-8b5e-452c-aab4-5591875cd6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794742833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2794742833
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3360856177
Short name T751
Test name
Test status
Simulation time 69752021 ps
CPU time 0.85 seconds
Started Jul 28 05:37:33 PM PDT 24
Finished Jul 28 05:37:34 PM PDT 24
Peak memory 215248 kb
Host smart-2a88ad6a-3c2d-426e-970d-328f02e8a82c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360856177 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3360856177
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2396228724
Short name T979
Test name
Test status
Simulation time 79224234 ps
CPU time 1.12 seconds
Started Jul 28 05:37:33 PM PDT 24
Finished Jul 28 05:37:35 PM PDT 24
Peak memory 218464 kb
Host smart-b1535d43-13d3-4212-be59-090a69ee8d0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396228724 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2396228724
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.776145799
Short name T136
Test name
Test status
Simulation time 34518830 ps
CPU time 1.11 seconds
Started Jul 28 05:37:28 PM PDT 24
Finished Jul 28 05:37:30 PM PDT 24
Peak memory 229528 kb
Host smart-27868ab3-36b0-4621-b856-ccf0073a246c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776145799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.776145799
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.135508588
Short name T350
Test name
Test status
Simulation time 125883509 ps
CPU time 2.79 seconds
Started Jul 28 05:37:34 PM PDT 24
Finished Jul 28 05:37:37 PM PDT 24
Peak memory 220136 kb
Host smart-c47bfc6e-9be0-465c-a6da-736ffe5cc0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135508588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.135508588
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.173608284
Short name T99
Test name
Test status
Simulation time 29631555 ps
CPU time 0.83 seconds
Started Jul 28 05:37:31 PM PDT 24
Finished Jul 28 05:37:32 PM PDT 24
Peak memory 215552 kb
Host smart-7437535d-d210-40a9-98e1-ab45eb1161d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173608284 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.173608284
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2455345819
Short name T388
Test name
Test status
Simulation time 19321654 ps
CPU time 0.93 seconds
Started Jul 28 05:37:31 PM PDT 24
Finished Jul 28 05:37:32 PM PDT 24
Peak memory 215176 kb
Host smart-23779dd7-5698-4be8-aadf-3b08ad2faf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455345819 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2455345819
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2370050536
Short name T325
Test name
Test status
Simulation time 654227256 ps
CPU time 2.4 seconds
Started Jul 28 05:37:34 PM PDT 24
Finished Jul 28 05:37:36 PM PDT 24
Peak memory 217108 kb
Host smart-cf2ffe64-7454-4863-8a6d-bd06d9c20dbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370050536 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2370050536
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.358544086
Short name T667
Test name
Test status
Simulation time 131938209478 ps
CPU time 786.76 seconds
Started Jul 28 05:37:28 PM PDT 24
Finished Jul 28 05:50:35 PM PDT 24
Peak memory 223624 kb
Host smart-95de85c7-6ab4-4bc4-aef5-0c92391c6601
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358544086 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.358544086
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1337298338
Short name T757
Test name
Test status
Simulation time 47334458 ps
CPU time 1.13 seconds
Started Jul 28 05:37:33 PM PDT 24
Finished Jul 28 05:37:34 PM PDT 24
Peak memory 219772 kb
Host smart-091bd3ab-f98d-4d5c-9468-dc61c552c7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337298338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1337298338
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2028458192
Short name T61
Test name
Test status
Simulation time 11667306 ps
CPU time 0.86 seconds
Started Jul 28 05:37:35 PM PDT 24
Finished Jul 28 05:37:36 PM PDT 24
Peak memory 206904 kb
Host smart-06ffe19a-08ee-4f52-b74a-6d887b55d1e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028458192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2028458192
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1453397464
Short name T778
Test name
Test status
Simulation time 10891133 ps
CPU time 0.9 seconds
Started Jul 28 05:37:33 PM PDT 24
Finished Jul 28 05:37:34 PM PDT 24
Peak memory 215264 kb
Host smart-2d0e75bf-ca79-41ad-b5b8-17ff5e935ca4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453397464 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1453397464
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3568662999
Short name T59
Test name
Test status
Simulation time 31910938 ps
CPU time 1.19 seconds
Started Jul 28 05:37:37 PM PDT 24
Finished Jul 28 05:37:39 PM PDT 24
Peak memory 216976 kb
Host smart-765b86fc-5db4-4939-9b81-42dc6a204239
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568662999 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3568662999
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3187115051
Short name T542
Test name
Test status
Simulation time 45023843 ps
CPU time 0.89 seconds
Started Jul 28 05:37:35 PM PDT 24
Finished Jul 28 05:37:36 PM PDT 24
Peak memory 218320 kb
Host smart-7a59a242-fc90-462a-a19e-a7ac49c29db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187115051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3187115051
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.262888283
Short name T641
Test name
Test status
Simulation time 36156939 ps
CPU time 1.32 seconds
Started Jul 28 05:37:34 PM PDT 24
Finished Jul 28 05:37:36 PM PDT 24
Peak memory 219552 kb
Host smart-9f2fc3bf-f2d8-4560-957f-fdec2fa552ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262888283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.262888283
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.831645693
Short name T361
Test name
Test status
Simulation time 22039383 ps
CPU time 1.1 seconds
Started Jul 28 05:37:34 PM PDT 24
Finished Jul 28 05:37:36 PM PDT 24
Peak memory 215268 kb
Host smart-e3a0c474-4d1f-4db4-87df-0d8cfa0c38c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831645693 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.831645693
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2179091725
Short name T805
Test name
Test status
Simulation time 27064924 ps
CPU time 0.98 seconds
Started Jul 28 05:37:32 PM PDT 24
Finished Jul 28 05:37:33 PM PDT 24
Peak memory 215120 kb
Host smart-7fdcf7b0-c74c-4791-b2e8-7c69e3ba5a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179091725 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2179091725
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2531938851
Short name T532
Test name
Test status
Simulation time 558783564 ps
CPU time 1.96 seconds
Started Jul 28 05:37:32 PM PDT 24
Finished Jul 28 05:37:35 PM PDT 24
Peak memory 217184 kb
Host smart-a3edff46-6830-463b-a189-545477034348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531938851 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2531938851
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.4084781142
Short name T788
Test name
Test status
Simulation time 107154200502 ps
CPU time 432.19 seconds
Started Jul 28 05:37:33 PM PDT 24
Finished Jul 28 05:44:45 PM PDT 24
Peak memory 223588 kb
Host smart-070ce41a-d5eb-4b52-aa7e-60beb8178905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084781142 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.4084781142
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3427613570
Short name T564
Test name
Test status
Simulation time 31018576 ps
CPU time 1.15 seconds
Started Jul 28 05:37:43 PM PDT 24
Finished Jul 28 05:37:44 PM PDT 24
Peak memory 215456 kb
Host smart-66cbe9d7-897f-42c4-81c6-5a6fd4f7f1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427613570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3427613570
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.4070027999
Short name T256
Test name
Test status
Simulation time 81032114 ps
CPU time 0.88 seconds
Started Jul 28 05:37:43 PM PDT 24
Finished Jul 28 05:37:44 PM PDT 24
Peak memory 206568 kb
Host smart-7d77b0eb-cf31-40d8-b81f-28b89bdaa7d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070027999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.4070027999
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3805414797
Short name T368
Test name
Test status
Simulation time 33689429 ps
CPU time 0.89 seconds
Started Jul 28 05:37:42 PM PDT 24
Finished Jul 28 05:37:43 PM PDT 24
Peak memory 216104 kb
Host smart-07c50c85-5681-4fce-b5ad-58ecba7bc657
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805414797 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3805414797
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1446841105
Short name T178
Test name
Test status
Simulation time 53040119 ps
CPU time 1.25 seconds
Started Jul 28 05:37:42 PM PDT 24
Finished Jul 28 05:37:43 PM PDT 24
Peak memory 216796 kb
Host smart-6293c09c-9c2d-4b63-905c-398d1c74ca1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446841105 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1446841105
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.295587097
Short name T169
Test name
Test status
Simulation time 34764096 ps
CPU time 1.04 seconds
Started Jul 28 05:37:43 PM PDT 24
Finished Jul 28 05:37:44 PM PDT 24
Peak memory 229484 kb
Host smart-105b74d1-e41a-460c-a0a6-4ab09efce3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295587097 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.295587097
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2924466636
Short name T651
Test name
Test status
Simulation time 39332151 ps
CPU time 1.4 seconds
Started Jul 28 05:37:40 PM PDT 24
Finished Jul 28 05:37:41 PM PDT 24
Peak memory 219864 kb
Host smart-d6205081-bd44-4dd1-8262-8378a5215fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924466636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2924466636
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1664808167
Short name T54
Test name
Test status
Simulation time 34921794 ps
CPU time 0.85 seconds
Started Jul 28 05:37:39 PM PDT 24
Finished Jul 28 05:37:40 PM PDT 24
Peak memory 215540 kb
Host smart-2536a059-f017-44d1-8264-7dc8ab2dcde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664808167 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1664808167
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.2718485064
Short name T355
Test name
Test status
Simulation time 29514062 ps
CPU time 0.96 seconds
Started Jul 28 05:37:32 PM PDT 24
Finished Jul 28 05:37:34 PM PDT 24
Peak memory 215180 kb
Host smart-da9d8025-a57c-417c-8672-6184de444bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718485064 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2718485064
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1656177615
Short name T273
Test name
Test status
Simulation time 523788290 ps
CPU time 5.16 seconds
Started Jul 28 05:37:42 PM PDT 24
Finished Jul 28 05:37:47 PM PDT 24
Peak memory 217036 kb
Host smart-8bf3da79-a73c-4ce7-ab29-c456b37494a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656177615 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1656177615
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1691549290
Short name T848
Test name
Test status
Simulation time 425863772164 ps
CPU time 2182.39 seconds
Started Jul 28 05:37:40 PM PDT 24
Finished Jul 28 06:14:02 PM PDT 24
Peak memory 236004 kb
Host smart-9c7ad003-b32e-4149-931b-db6384bd835b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691549290 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1691549290
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1892076410
Short name T87
Test name
Test status
Simulation time 77268527 ps
CPU time 1.16 seconds
Started Jul 28 05:37:42 PM PDT 24
Finished Jul 28 05:37:44 PM PDT 24
Peak memory 218452 kb
Host smart-72aeec29-ba7e-4b7c-b16b-5fc55a772ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892076410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1892076410
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3092753879
Short name T563
Test name
Test status
Simulation time 19437014 ps
CPU time 1.05 seconds
Started Jul 28 05:37:44 PM PDT 24
Finished Jul 28 05:37:45 PM PDT 24
Peak memory 214788 kb
Host smart-6f28a0d5-64d3-48bf-9ceb-6d9fca18b4dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092753879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3092753879
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2934755320
Short name T717
Test name
Test status
Simulation time 32016339 ps
CPU time 0.88 seconds
Started Jul 28 05:37:40 PM PDT 24
Finished Jul 28 05:37:41 PM PDT 24
Peak memory 215292 kb
Host smart-a9ef76af-bfe1-4a54-8c61-95fc7f173f64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934755320 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2934755320
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.755196290
Short name T204
Test name
Test status
Simulation time 50505652 ps
CPU time 1.18 seconds
Started Jul 28 05:37:40 PM PDT 24
Finished Jul 28 05:37:41 PM PDT 24
Peak memory 224864 kb
Host smart-c22305b6-8bd0-4530-9a27-4aea4cd6339e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755196290 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.755196290
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.386625925
Short name T675
Test name
Test status
Simulation time 32771727 ps
CPU time 1.18 seconds
Started Jul 28 05:37:37 PM PDT 24
Finished Jul 28 05:37:39 PM PDT 24
Peak memory 218224 kb
Host smart-f36b79b3-a69a-49bf-8f22-7fb4c66828e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386625925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.386625925
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1173396831
Short name T493
Test name
Test status
Simulation time 32106434 ps
CPU time 0.89 seconds
Started Jul 28 05:37:42 PM PDT 24
Finished Jul 28 05:37:43 PM PDT 24
Peak memory 215656 kb
Host smart-12f8d56c-0d1e-4d8e-a95d-0001006668c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173396831 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1173396831
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.501982292
Short name T865
Test name
Test status
Simulation time 25011468 ps
CPU time 0.94 seconds
Started Jul 28 05:37:42 PM PDT 24
Finished Jul 28 05:37:43 PM PDT 24
Peak memory 215168 kb
Host smart-0fa0816e-87b5-4243-af45-eda62d3f1498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501982292 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.501982292
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3597770765
Short name T721
Test name
Test status
Simulation time 85230143 ps
CPU time 2.2 seconds
Started Jul 28 05:37:41 PM PDT 24
Finished Jul 28 05:37:43 PM PDT 24
Peak memory 218540 kb
Host smart-55284949-0552-4fdf-b1a3-a4ae3daf59f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597770765 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3597770765
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3061331996
Short name T245
Test name
Test status
Simulation time 112857516066 ps
CPU time 2434.86 seconds
Started Jul 28 05:37:42 PM PDT 24
Finished Jul 28 06:18:17 PM PDT 24
Peak memory 228260 kb
Host smart-ac2eed00-999c-477f-8b5e-36a41b049826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061331996 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3061331996
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1288129363
Short name T319
Test name
Test status
Simulation time 89722590 ps
CPU time 1.32 seconds
Started Jul 28 05:36:40 PM PDT 24
Finished Jul 28 05:36:41 PM PDT 24
Peak memory 218468 kb
Host smart-209116d5-552e-4cd4-b8c5-a2ce444e7cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288129363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1288129363
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2259629527
Short name T396
Test name
Test status
Simulation time 40685694 ps
CPU time 1.1 seconds
Started Jul 28 05:36:42 PM PDT 24
Finished Jul 28 05:36:43 PM PDT 24
Peak memory 214864 kb
Host smart-071d13c5-83e2-41fe-85b7-31b4bb8c575a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259629527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2259629527
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1928110280
Short name T124
Test name
Test status
Simulation time 31346989 ps
CPU time 0.88 seconds
Started Jul 28 05:36:42 PM PDT 24
Finished Jul 28 05:36:43 PM PDT 24
Peak memory 216268 kb
Host smart-7de2a003-1faa-4c0d-beb2-5ae93addd6cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928110280 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1928110280
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.2139081740
Short name T126
Test name
Test status
Simulation time 18457900 ps
CPU time 1.04 seconds
Started Jul 28 05:36:40 PM PDT 24
Finished Jul 28 05:36:41 PM PDT 24
Peak memory 218392 kb
Host smart-6b2297cf-5145-47d1-b8c1-76b5bdd37be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139081740 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2139081740
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.812617695
Short name T625
Test name
Test status
Simulation time 586077160 ps
CPU time 4.22 seconds
Started Jul 28 05:36:43 PM PDT 24
Finished Jul 28 05:36:48 PM PDT 24
Peak memory 217420 kb
Host smart-ac8a7fbd-0f71-4cce-a15f-be7139e32aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812617695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.812617695
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3355556179
Short name T706
Test name
Test status
Simulation time 43409139 ps
CPU time 0.86 seconds
Started Jul 28 05:36:38 PM PDT 24
Finished Jul 28 05:36:39 PM PDT 24
Peak memory 215488 kb
Host smart-62cda9d3-27cd-46c0-a52b-6d6bf6b9174b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355556179 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3355556179
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.4065909130
Short name T896
Test name
Test status
Simulation time 47520207 ps
CPU time 0.94 seconds
Started Jul 28 05:36:42 PM PDT 24
Finished Jul 28 05:36:43 PM PDT 24
Peak memory 206960 kb
Host smart-ff80c4f3-9771-47c9-819b-c95c1d5f8927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065909130 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.4065909130
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.1278959757
Short name T420
Test name
Test status
Simulation time 27816665 ps
CPU time 0.99 seconds
Started Jul 28 05:36:42 PM PDT 24
Finished Jul 28 05:36:43 PM PDT 24
Peak memory 215160 kb
Host smart-ff2987ca-82a0-463c-8e81-4f26b9759b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278959757 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1278959757
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.62928238
Short name T713
Test name
Test status
Simulation time 384824379 ps
CPU time 7.51 seconds
Started Jul 28 05:36:39 PM PDT 24
Finished Jul 28 05:36:47 PM PDT 24
Peak memory 219756 kb
Host smart-66e27ca4-9592-4b1d-bf03-12f855e371c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62928238 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.62928238
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2329952220
Short name T838
Test name
Test status
Simulation time 45762742776 ps
CPU time 1090.34 seconds
Started Jul 28 05:36:41 PM PDT 24
Finished Jul 28 05:54:52 PM PDT 24
Peak memory 219772 kb
Host smart-27c64f7c-732c-42f4-bdf0-6018f823d529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329952220 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2329952220
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2929746912
Short name T856
Test name
Test status
Simulation time 70503898 ps
CPU time 1.2 seconds
Started Jul 28 05:37:42 PM PDT 24
Finished Jul 28 05:37:43 PM PDT 24
Peak memory 218368 kb
Host smart-5a138e35-2969-4668-b399-8069290657ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929746912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2929746912
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2631176197
Short name T811
Test name
Test status
Simulation time 19280764 ps
CPU time 0.95 seconds
Started Jul 28 05:37:44 PM PDT 24
Finished Jul 28 05:37:46 PM PDT 24
Peak memory 206624 kb
Host smart-a8111c22-f95f-439c-ba5f-92d39ba37344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631176197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2631176197
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.53676430
Short name T949
Test name
Test status
Simulation time 18600471 ps
CPU time 0.87 seconds
Started Jul 28 05:37:40 PM PDT 24
Finished Jul 28 05:37:42 PM PDT 24
Peak memory 216084 kb
Host smart-7124d463-9b6a-4e1c-be6c-5af9bc10fa39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53676430 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.53676430
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3238738459
Short name T150
Test name
Test status
Simulation time 184856706 ps
CPU time 1.3 seconds
Started Jul 28 05:37:42 PM PDT 24
Finished Jul 28 05:37:44 PM PDT 24
Peak memory 216844 kb
Host smart-263fd746-a3c8-4a6b-be14-7328a72c0c5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238738459 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3238738459
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3740806589
Short name T50
Test name
Test status
Simulation time 23242288 ps
CPU time 1.3 seconds
Started Jul 28 05:37:39 PM PDT 24
Finished Jul 28 05:37:41 PM PDT 24
Peak memory 229484 kb
Host smart-ae1955e6-7e6a-4c8e-83db-2307c6a9df7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740806589 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3740806589
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3013032395
Short name T699
Test name
Test status
Simulation time 341845209 ps
CPU time 1.26 seconds
Started Jul 28 05:37:39 PM PDT 24
Finished Jul 28 05:37:41 PM PDT 24
Peak memory 217252 kb
Host smart-2331a2d5-59ae-452d-9b3e-aea1580ee8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013032395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3013032395
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_smoke.3803352086
Short name T823
Test name
Test status
Simulation time 52939821 ps
CPU time 0.98 seconds
Started Jul 28 05:37:41 PM PDT 24
Finished Jul 28 05:37:42 PM PDT 24
Peak memory 215204 kb
Host smart-5023fd8c-b4ab-43f9-bfa2-7dd868bbb911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803352086 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3803352086
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.681956492
Short name T262
Test name
Test status
Simulation time 532161866 ps
CPU time 3.02 seconds
Started Jul 28 05:37:44 PM PDT 24
Finished Jul 28 05:37:48 PM PDT 24
Peak memory 215136 kb
Host smart-5bab4c40-357c-4656-9817-559dc7bb772b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681956492 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.681956492
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1902925779
Short name T983
Test name
Test status
Simulation time 24588138700 ps
CPU time 558.21 seconds
Started Jul 28 05:37:42 PM PDT 24
Finished Jul 28 05:47:00 PM PDT 24
Peak memory 223620 kb
Host smart-ace2e256-d01c-4e68-945b-5b428f63018a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902925779 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1902925779
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2639213750
Short name T941
Test name
Test status
Simulation time 38648281 ps
CPU time 1.13 seconds
Started Jul 28 05:37:48 PM PDT 24
Finished Jul 28 05:37:49 PM PDT 24
Peak memory 219936 kb
Host smart-707b6df9-a010-4f96-8ef9-10e85bab33bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639213750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2639213750
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1725743896
Short name T64
Test name
Test status
Simulation time 63496681 ps
CPU time 1.03 seconds
Started Jul 28 05:37:44 PM PDT 24
Finished Jul 28 05:37:45 PM PDT 24
Peak memory 214860 kb
Host smart-2a1e2c82-84d9-4513-a96e-a0fdf3785d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725743896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1725743896
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.49287168
Short name T85
Test name
Test status
Simulation time 125683141 ps
CPU time 0.92 seconds
Started Jul 28 05:37:44 PM PDT 24
Finished Jul 28 05:37:46 PM PDT 24
Peak memory 216180 kb
Host smart-4093079a-8a54-4a1a-85cf-bff655d485fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49287168 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.49287168
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.991671432
Short name T559
Test name
Test status
Simulation time 95264425 ps
CPU time 1.06 seconds
Started Jul 28 05:37:47 PM PDT 24
Finished Jul 28 05:37:49 PM PDT 24
Peak memory 218628 kb
Host smart-ca028c07-f46b-4cdd-98ac-6e9ed377def1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991671432 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.991671432
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2887039027
Short name T198
Test name
Test status
Simulation time 50841361 ps
CPU time 0.95 seconds
Started Jul 28 05:37:40 PM PDT 24
Finished Jul 28 05:37:41 PM PDT 24
Peak memory 219688 kb
Host smart-dd00748e-5ac2-46b9-bc59-df6a126056d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887039027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2887039027
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.456213785
Short name T662
Test name
Test status
Simulation time 155120865 ps
CPU time 1.18 seconds
Started Jul 28 05:37:42 PM PDT 24
Finished Jul 28 05:37:44 PM PDT 24
Peak memory 220116 kb
Host smart-6f415924-e023-47a6-9ae3-3dd668cbc1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456213785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.456213785
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1237961079
Short name T920
Test name
Test status
Simulation time 29060918 ps
CPU time 1.04 seconds
Started Jul 28 05:37:40 PM PDT 24
Finished Jul 28 05:37:41 PM PDT 24
Peak memory 215256 kb
Host smart-50e0d4c1-d12d-4c30-980e-8606515b1178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237961079 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1237961079
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.891814030
Short name T746
Test name
Test status
Simulation time 35082075 ps
CPU time 0.99 seconds
Started Jul 28 05:37:39 PM PDT 24
Finished Jul 28 05:37:40 PM PDT 24
Peak memory 215156 kb
Host smart-f840ee3a-f8d0-4226-95cc-94ff9c22b507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891814030 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.891814030
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3059351689
Short name T917
Test name
Test status
Simulation time 483864215 ps
CPU time 5.07 seconds
Started Jul 28 05:37:41 PM PDT 24
Finished Jul 28 05:37:46 PM PDT 24
Peak memory 215188 kb
Host smart-48c5f2be-f800-4922-89fc-577e17d9d8fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059351689 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3059351689
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3173861460
Short name T975
Test name
Test status
Simulation time 116208161541 ps
CPU time 1341.08 seconds
Started Jul 28 05:37:40 PM PDT 24
Finished Jul 28 06:00:01 PM PDT 24
Peak memory 224336 kb
Host smart-18abd052-f120-430b-91ee-1b0ba8503292
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173861460 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3173861460
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3161583648
Short name T913
Test name
Test status
Simulation time 90380203 ps
CPU time 1.17 seconds
Started Jul 28 05:37:48 PM PDT 24
Finished Jul 28 05:37:49 PM PDT 24
Peak memory 220424 kb
Host smart-ce311dec-5d5f-4058-88aa-99744d34f38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161583648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3161583648
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2973856297
Short name T63
Test name
Test status
Simulation time 17680002 ps
CPU time 0.97 seconds
Started Jul 28 05:37:45 PM PDT 24
Finished Jul 28 05:37:46 PM PDT 24
Peak memory 215060 kb
Host smart-5c420ac6-96fd-4f3c-9b6d-2495f04c5280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973856297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2973856297
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3306048551
Short name T206
Test name
Test status
Simulation time 19303983 ps
CPU time 0.86 seconds
Started Jul 28 05:37:47 PM PDT 24
Finished Jul 28 05:37:48 PM PDT 24
Peak memory 215248 kb
Host smart-212f942b-e35e-4999-b8b9-fc2b340ff645
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306048551 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3306048551
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2736056342
Short name T200
Test name
Test status
Simulation time 36918575 ps
CPU time 1.37 seconds
Started Jul 28 05:37:48 PM PDT 24
Finished Jul 28 05:37:50 PM PDT 24
Peak memory 216920 kb
Host smart-69d47fe2-ca26-4315-bfb5-9f7672ad2e8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736056342 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2736056342
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3185268752
Short name T47
Test name
Test status
Simulation time 21704790 ps
CPU time 1 seconds
Started Jul 28 05:37:42 PM PDT 24
Finished Jul 28 05:37:43 PM PDT 24
Peak memory 223880 kb
Host smart-a8121d37-1394-4cfc-8809-3a0db4c9d52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185268752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3185268752
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.90578466
Short name T827
Test name
Test status
Simulation time 40565380 ps
CPU time 1.42 seconds
Started Jul 28 05:37:47 PM PDT 24
Finished Jul 28 05:37:49 PM PDT 24
Peak memory 218232 kb
Host smart-b7e58244-fbd0-400b-a6e9-4488b8c5df8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90578466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.90578466
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2132131878
Short name T617
Test name
Test status
Simulation time 47338792 ps
CPU time 0.88 seconds
Started Jul 28 05:37:46 PM PDT 24
Finished Jul 28 05:37:47 PM PDT 24
Peak memory 215220 kb
Host smart-a759e348-5441-4432-84fd-5d7ff7fe40f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132131878 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2132131878
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.113110763
Short name T508
Test name
Test status
Simulation time 26006515 ps
CPU time 0.94 seconds
Started Jul 28 05:37:46 PM PDT 24
Finished Jul 28 05:37:47 PM PDT 24
Peak memory 215124 kb
Host smart-7c700e47-1dca-484b-80d5-7e73121a3404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113110763 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.113110763
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3945314142
Short name T336
Test name
Test status
Simulation time 243598939 ps
CPU time 2.89 seconds
Started Jul 28 05:37:46 PM PDT 24
Finished Jul 28 05:37:49 PM PDT 24
Peak memory 217224 kb
Host smart-e3da6de6-634d-4837-85f4-8c6d8369aabc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945314142 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3945314142
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1746573783
Short name T935
Test name
Test status
Simulation time 146256714759 ps
CPU time 1891.04 seconds
Started Jul 28 05:37:45 PM PDT 24
Finished Jul 28 06:09:17 PM PDT 24
Peak memory 229000 kb
Host smart-c5c10d79-9ab8-41fc-8302-b02be14f3105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746573783 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1746573783
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.4146000885
Short name T674
Test name
Test status
Simulation time 21641820 ps
CPU time 1.13 seconds
Started Jul 28 05:37:46 PM PDT 24
Finished Jul 28 05:37:47 PM PDT 24
Peak memory 219440 kb
Host smart-9559c8eb-4c22-4c0b-a245-3b9eb9550d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146000885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.4146000885
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3660186371
Short name T365
Test name
Test status
Simulation time 31268503 ps
CPU time 0.9 seconds
Started Jul 28 05:37:50 PM PDT 24
Finished Jul 28 05:37:51 PM PDT 24
Peak memory 206684 kb
Host smart-5ec5c041-a1bf-4f75-93e9-f20cb6e081d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660186371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3660186371
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3264152540
Short name T405
Test name
Test status
Simulation time 28482008 ps
CPU time 0.82 seconds
Started Jul 28 05:37:44 PM PDT 24
Finished Jul 28 05:37:45 PM PDT 24
Peak memory 215864 kb
Host smart-f7dbb789-415a-4ae2-9869-6f397016c308
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264152540 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3264152540
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1956210558
Short name T187
Test name
Test status
Simulation time 133813833 ps
CPU time 1 seconds
Started Jul 28 05:37:44 PM PDT 24
Finished Jul 28 05:37:45 PM PDT 24
Peak memory 216864 kb
Host smart-0885b410-0e27-4ba8-a890-6620171dac03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956210558 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1956210558
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.183501536
Short name T968
Test name
Test status
Simulation time 64859990 ps
CPU time 1.02 seconds
Started Jul 28 05:37:47 PM PDT 24
Finished Jul 28 05:37:48 PM PDT 24
Peak memory 220320 kb
Host smart-1dd398ec-45c8-4728-a16c-a17b2bacfc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183501536 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.183501536
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3722257331
Short name T84
Test name
Test status
Simulation time 174893873 ps
CPU time 2.16 seconds
Started Jul 28 05:37:49 PM PDT 24
Finished Jul 28 05:37:51 PM PDT 24
Peak memory 220188 kb
Host smart-7212ab5c-1d7b-4a2d-970d-5ca4acf297e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722257331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3722257331
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2008912966
Short name T15
Test name
Test status
Simulation time 25504955 ps
CPU time 1.21 seconds
Started Jul 28 05:37:45 PM PDT 24
Finished Jul 28 05:37:46 PM PDT 24
Peak memory 223952 kb
Host smart-782a5c42-212c-4c05-ba15-e350054b216d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008912966 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2008912966
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1327485334
Short name T370
Test name
Test status
Simulation time 85312214 ps
CPU time 0.9 seconds
Started Jul 28 05:37:45 PM PDT 24
Finished Jul 28 05:37:46 PM PDT 24
Peak memory 215172 kb
Host smart-5bb46ae3-a4d8-4648-b6dd-d04eee4b0ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327485334 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1327485334
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3008247861
Short name T259
Test name
Test status
Simulation time 60082123 ps
CPU time 1.26 seconds
Started Jul 28 05:37:46 PM PDT 24
Finished Jul 28 05:37:47 PM PDT 24
Peak memory 207012 kb
Host smart-75d8549e-eccf-4447-9902-7c47943cac2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008247861 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3008247861
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3896829814
Short name T251
Test name
Test status
Simulation time 24045631186 ps
CPU time 283.84 seconds
Started Jul 28 05:37:43 PM PDT 24
Finished Jul 28 05:42:28 PM PDT 24
Peak memory 223720 kb
Host smart-845ca5f7-ab02-4227-9023-376c2cfedf6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896829814 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3896829814
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2268638185
Short name T92
Test name
Test status
Simulation time 167942131 ps
CPU time 1.23 seconds
Started Jul 28 05:38:01 PM PDT 24
Finished Jul 28 05:38:03 PM PDT 24
Peak memory 219744 kb
Host smart-7f7622ba-3cba-4c4d-b1ea-90bf831b4b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268638185 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2268638185
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.602101859
Short name T781
Test name
Test status
Simulation time 22038225 ps
CPU time 0.87 seconds
Started Jul 28 05:37:53 PM PDT 24
Finished Jul 28 05:37:54 PM PDT 24
Peak memory 214752 kb
Host smart-266b98d6-b9a8-4288-aff1-bda9f65caadb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602101859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.602101859
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1416492012
Short name T208
Test name
Test status
Simulation time 18001873 ps
CPU time 0.82 seconds
Started Jul 28 05:37:53 PM PDT 24
Finished Jul 28 05:37:54 PM PDT 24
Peak memory 215212 kb
Host smart-0a8a5e85-443c-45e7-a810-314932d0b86a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416492012 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1416492012
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1309580699
Short name T923
Test name
Test status
Simulation time 198975190 ps
CPU time 1.01 seconds
Started Jul 28 05:37:50 PM PDT 24
Finished Jul 28 05:37:51 PM PDT 24
Peak memory 218616 kb
Host smart-111eb959-e46e-4fea-a710-f16f29e2efd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309580699 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1309580699
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.727415913
Short name T107
Test name
Test status
Simulation time 35623662 ps
CPU time 0.95 seconds
Started Jul 28 05:37:49 PM PDT 24
Finished Jul 28 05:37:50 PM PDT 24
Peak memory 219556 kb
Host smart-318996fb-d753-4370-ad51-4911fe40b516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727415913 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.727415913
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.751898284
Short name T895
Test name
Test status
Simulation time 60259303 ps
CPU time 2.11 seconds
Started Jul 28 05:37:53 PM PDT 24
Finished Jul 28 05:37:55 PM PDT 24
Peak memory 218168 kb
Host smart-e6cdcd37-0b62-4467-8b1c-a36a90190916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751898284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.751898284
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3671387759
Short name T48
Test name
Test status
Simulation time 22873311 ps
CPU time 1.25 seconds
Started Jul 28 05:37:52 PM PDT 24
Finished Jul 28 05:37:53 PM PDT 24
Peak memory 224004 kb
Host smart-37214a43-8237-484e-ae84-4dd55467fb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671387759 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3671387759
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.86132634
Short name T912
Test name
Test status
Simulation time 36067136 ps
CPU time 0.91 seconds
Started Jul 28 05:37:53 PM PDT 24
Finished Jul 28 05:37:54 PM PDT 24
Peak memory 206920 kb
Host smart-11eca0b9-7336-4e54-91e9-591de12846f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86132634 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.86132634
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1825815730
Short name T834
Test name
Test status
Simulation time 88562080 ps
CPU time 2.37 seconds
Started Jul 28 05:37:52 PM PDT 24
Finished Jul 28 05:37:55 PM PDT 24
Peak memory 215136 kb
Host smart-9af4ee5f-beef-4790-914c-6dd0a1cc3f97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825815730 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1825815730
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3212179294
Short name T922
Test name
Test status
Simulation time 12415045310 ps
CPU time 330.32 seconds
Started Jul 28 05:37:49 PM PDT 24
Finished Jul 28 05:43:20 PM PDT 24
Peak memory 218412 kb
Host smart-4e776b5a-7271-476f-a18a-c54ed8d68716
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212179294 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3212179294
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1082168006
Short name T29
Test name
Test status
Simulation time 25813979 ps
CPU time 1.25 seconds
Started Jul 28 05:37:53 PM PDT 24
Finished Jul 28 05:37:54 PM PDT 24
Peak memory 219360 kb
Host smart-d3f0c9ee-6bf9-4932-b05a-4cb869386fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082168006 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1082168006
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3916714900
Short name T630
Test name
Test status
Simulation time 78844582 ps
CPU time 0.91 seconds
Started Jul 28 05:37:50 PM PDT 24
Finished Jul 28 05:37:51 PM PDT 24
Peak memory 214828 kb
Host smart-adb08e34-0bca-42b2-9c3b-d7037b52d8fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916714900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3916714900
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1557527316
Short name T152
Test name
Test status
Simulation time 36144111 ps
CPU time 0.91 seconds
Started Jul 28 05:37:53 PM PDT 24
Finished Jul 28 05:37:54 PM PDT 24
Peak memory 216112 kb
Host smart-6ed727e5-b896-417a-b5bf-02f14cb54ba6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557527316 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1557527316
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_err.3704997756
Short name T878
Test name
Test status
Simulation time 31779346 ps
CPU time 0.91 seconds
Started Jul 28 05:38:01 PM PDT 24
Finished Jul 28 05:38:02 PM PDT 24
Peak memory 218488 kb
Host smart-d224aba9-0888-48c1-9f61-2f044e31590a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704997756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3704997756
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2531511375
Short name T351
Test name
Test status
Simulation time 55943682 ps
CPU time 1.57 seconds
Started Jul 28 05:37:49 PM PDT 24
Finished Jul 28 05:37:51 PM PDT 24
Peak memory 218428 kb
Host smart-bcabd5db-1231-42d7-9abd-00217b18005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531511375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2531511375
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3065538107
Short name T1
Test name
Test status
Simulation time 42020376 ps
CPU time 0.87 seconds
Started Jul 28 05:37:54 PM PDT 24
Finished Jul 28 05:37:55 PM PDT 24
Peak memory 215100 kb
Host smart-f73748f7-fc0b-4751-ae7b-343ba7762aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065538107 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3065538107
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1065811373
Short name T741
Test name
Test status
Simulation time 21680328 ps
CPU time 0.95 seconds
Started Jul 28 05:37:50 PM PDT 24
Finished Jul 28 05:37:52 PM PDT 24
Peak memory 215220 kb
Host smart-daf09dce-8cbe-47a9-93d5-dc9e9d384bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065811373 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1065811373
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2442897111
Short name T424
Test name
Test status
Simulation time 212724461 ps
CPU time 3.01 seconds
Started Jul 28 05:37:47 PM PDT 24
Finished Jul 28 05:37:51 PM PDT 24
Peak memory 217080 kb
Host smart-19aea0f6-c43d-472f-89d4-8456452d809f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442897111 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2442897111
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1693849205
Short name T435
Test name
Test status
Simulation time 21467311555 ps
CPU time 466.31 seconds
Started Jul 28 05:37:50 PM PDT 24
Finished Jul 28 05:45:36 PM PDT 24
Peak memory 223528 kb
Host smart-e16ae8c2-e9bb-450d-86be-37e83ccbd987
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693849205 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1693849205
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2128593877
Short name T631
Test name
Test status
Simulation time 78615192 ps
CPU time 1.13 seconds
Started Jul 28 05:37:53 PM PDT 24
Finished Jul 28 05:37:55 PM PDT 24
Peak memory 221264 kb
Host smart-fe171ddb-a1e6-4d53-a132-2d23f0e60f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128593877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2128593877
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3391239352
Short name T62
Test name
Test status
Simulation time 16757154 ps
CPU time 1.06 seconds
Started Jul 28 05:37:53 PM PDT 24
Finished Jul 28 05:37:54 PM PDT 24
Peak memory 206660 kb
Host smart-09cf75e3-d0a1-4c73-a974-dfa958448358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391239352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3391239352
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.110785689
Short name T255
Test name
Test status
Simulation time 31970886 ps
CPU time 0.89 seconds
Started Jul 28 05:38:01 PM PDT 24
Finished Jul 28 05:38:02 PM PDT 24
Peak memory 216068 kb
Host smart-7d5ffeb2-3e41-4af5-8210-68b71c0f5bc3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110785689 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.110785689
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2204778344
Short name T842
Test name
Test status
Simulation time 123137860 ps
CPU time 1.23 seconds
Started Jul 28 05:37:52 PM PDT 24
Finished Jul 28 05:37:53 PM PDT 24
Peak memory 216992 kb
Host smart-b2b047a5-3d48-4b4d-8974-3258532a1c1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204778344 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2204778344
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2551027851
Short name T194
Test name
Test status
Simulation time 22902531 ps
CPU time 1.24 seconds
Started Jul 28 05:38:01 PM PDT 24
Finished Jul 28 05:38:03 PM PDT 24
Peak memory 219572 kb
Host smart-ae8a65eb-7b40-447f-b4d1-ce53f28e41e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551027851 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2551027851
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1423549270
Short name T984
Test name
Test status
Simulation time 35177003 ps
CPU time 1.43 seconds
Started Jul 28 05:38:01 PM PDT 24
Finished Jul 28 05:38:03 PM PDT 24
Peak memory 219888 kb
Host smart-da8ccd38-901c-40be-bd1b-f990fa2d4dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423549270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1423549270
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1521898501
Short name T104
Test name
Test status
Simulation time 22722235 ps
CPU time 1.01 seconds
Started Jul 28 05:37:50 PM PDT 24
Finished Jul 28 05:37:51 PM PDT 24
Peak memory 215700 kb
Host smart-ce85cb17-c79e-4058-98dc-aa7a82993aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521898501 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1521898501
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.148944119
Short name T783
Test name
Test status
Simulation time 26735078 ps
CPU time 1.01 seconds
Started Jul 28 05:37:52 PM PDT 24
Finished Jul 28 05:37:53 PM PDT 24
Peak memory 215120 kb
Host smart-a75f67fe-f724-4398-9078-a13078854356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148944119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.148944119
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3842478413
Short name T358
Test name
Test status
Simulation time 291331931 ps
CPU time 2.2 seconds
Started Jul 28 05:37:53 PM PDT 24
Finished Jul 28 05:37:55 PM PDT 24
Peak memory 217148 kb
Host smart-d4731e96-799f-4114-b48a-54712ad0e1c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842478413 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3842478413
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1151225362
Short name T25
Test name
Test status
Simulation time 273946961239 ps
CPU time 1458.85 seconds
Started Jul 28 05:37:49 PM PDT 24
Finished Jul 28 06:02:08 PM PDT 24
Peak memory 223092 kb
Host smart-ba7e1a08-0aa1-487d-b768-93323431f303
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151225362 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1151225362
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1563870367
Short name T614
Test name
Test status
Simulation time 44088539 ps
CPU time 1.18 seconds
Started Jul 28 05:37:52 PM PDT 24
Finished Jul 28 05:37:53 PM PDT 24
Peak memory 219772 kb
Host smart-f83eb290-c961-4051-a2ed-bca0b9ed49e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563870367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1563870367
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1502110254
Short name T418
Test name
Test status
Simulation time 16134343 ps
CPU time 0.92 seconds
Started Jul 28 05:37:57 PM PDT 24
Finished Jul 28 05:37:59 PM PDT 24
Peak memory 214784 kb
Host smart-84a089e3-018b-4fc6-b68a-5588ef5a6806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502110254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1502110254
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3833448440
Short name T148
Test name
Test status
Simulation time 131645901 ps
CPU time 0.87 seconds
Started Jul 28 05:37:53 PM PDT 24
Finished Jul 28 05:37:54 PM PDT 24
Peak memory 216088 kb
Host smart-2969f627-f459-46ff-8c20-8db0c9fd9397
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833448440 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3833448440
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3372247755
Short name T65
Test name
Test status
Simulation time 46055492 ps
CPU time 1.27 seconds
Started Jul 28 05:38:02 PM PDT 24
Finished Jul 28 05:38:03 PM PDT 24
Peak memory 217028 kb
Host smart-79ef3e5c-d102-4419-af64-9dae6c1dd723
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372247755 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3372247755
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2669831162
Short name T787
Test name
Test status
Simulation time 23436872 ps
CPU time 1.3 seconds
Started Jul 28 05:37:52 PM PDT 24
Finished Jul 28 05:37:54 PM PDT 24
Peak memory 223880 kb
Host smart-3fa63c12-5b73-4882-b233-110ed3900344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669831162 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2669831162
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2604104520
Short name T9
Test name
Test status
Simulation time 285568173 ps
CPU time 4.09 seconds
Started Jul 28 05:37:50 PM PDT 24
Finished Jul 28 05:37:54 PM PDT 24
Peak memory 220004 kb
Host smart-4942a52c-a112-4992-958a-66d8b4e3363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604104520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2604104520
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1275678268
Short name T409
Test name
Test status
Simulation time 24341350 ps
CPU time 1.02 seconds
Started Jul 28 05:38:01 PM PDT 24
Finished Jul 28 05:38:02 PM PDT 24
Peak memory 215568 kb
Host smart-fd814479-68a7-40a4-bd13-be06a18fac57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275678268 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1275678268
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2232573572
Short name T541
Test name
Test status
Simulation time 19703600 ps
CPU time 1.03 seconds
Started Jul 28 05:37:50 PM PDT 24
Finished Jul 28 05:37:51 PM PDT 24
Peak memory 215072 kb
Host smart-c90d88c5-f5d0-41c1-933d-f7968da029b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232573572 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2232573572
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3685960380
Short name T829
Test name
Test status
Simulation time 127445321 ps
CPU time 2.94 seconds
Started Jul 28 05:37:51 PM PDT 24
Finished Jul 28 05:37:54 PM PDT 24
Peak memory 215196 kb
Host smart-1f348713-10ba-45e0-964e-7e0e7e90e4af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685960380 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3685960380
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3809262801
Short name T616
Test name
Test status
Simulation time 131838335741 ps
CPU time 829.71 seconds
Started Jul 28 05:37:47 PM PDT 24
Finished Jul 28 05:51:37 PM PDT 24
Peak memory 221380 kb
Host smart-49e198c2-dc87-4468-b727-7cd6e7dea868
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809262801 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3809262801
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.316646240
Short name T724
Test name
Test status
Simulation time 84753509 ps
CPU time 1.17 seconds
Started Jul 28 05:37:57 PM PDT 24
Finished Jul 28 05:37:58 PM PDT 24
Peak memory 219472 kb
Host smart-359637d4-18e7-4727-b842-98b62368da55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316646240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.316646240
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.527848615
Short name T596
Test name
Test status
Simulation time 15454271 ps
CPU time 0.97 seconds
Started Jul 28 05:37:55 PM PDT 24
Finished Jul 28 05:37:57 PM PDT 24
Peak memory 215108 kb
Host smart-6cb32639-7c21-4341-845d-54e6f917bb26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527848615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.527848615
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2576694225
Short name T844
Test name
Test status
Simulation time 16013944 ps
CPU time 0.87 seconds
Started Jul 28 05:37:56 PM PDT 24
Finished Jul 28 05:37:57 PM PDT 24
Peak memory 216052 kb
Host smart-9ff6d7c5-0b8a-4259-9e50-4c6399a8d071
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576694225 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2576694225
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1813843527
Short name T581
Test name
Test status
Simulation time 56415344 ps
CPU time 1.01 seconds
Started Jul 28 05:38:00 PM PDT 24
Finished Jul 28 05:38:01 PM PDT 24
Peak memory 216776 kb
Host smart-e2ddb671-3367-415a-8c9f-8a4e2a7141d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813843527 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1813843527
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.348180395
Short name T137
Test name
Test status
Simulation time 26776819 ps
CPU time 0.96 seconds
Started Jul 28 05:37:55 PM PDT 24
Finished Jul 28 05:37:56 PM PDT 24
Peak memory 218452 kb
Host smart-3d676591-f665-4ed1-b86b-5f1130c447c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348180395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.348180395
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3049389550
Short name T597
Test name
Test status
Simulation time 55217368 ps
CPU time 1.25 seconds
Started Jul 28 05:38:00 PM PDT 24
Finished Jul 28 05:38:01 PM PDT 24
Peak memory 217292 kb
Host smart-0fb69729-a769-4d70-b66b-6d97dda46ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049389550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3049389550
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1358824233
Short name T822
Test name
Test status
Simulation time 22272665 ps
CPU time 1.06 seconds
Started Jul 28 05:37:52 PM PDT 24
Finished Jul 28 05:37:54 PM PDT 24
Peak memory 215400 kb
Host smart-6fa2f18d-82f4-4e95-a1ca-afb8e4de45aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358824233 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1358824233
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2315082459
Short name T272
Test name
Test status
Simulation time 47842627 ps
CPU time 0.92 seconds
Started Jul 28 05:37:55 PM PDT 24
Finished Jul 28 05:37:56 PM PDT 24
Peak memory 215172 kb
Host smart-58cf6fee-ca39-424e-8ab5-bd9b77f75009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315082459 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2315082459
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1782025692
Short name T431
Test name
Test status
Simulation time 375289553 ps
CPU time 2.52 seconds
Started Jul 28 05:37:58 PM PDT 24
Finished Jul 28 05:38:01 PM PDT 24
Peak memory 217188 kb
Host smart-2d886baf-056d-46a6-b0e5-fedd8c3eb271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782025692 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1782025692
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3698134909
Short name T24
Test name
Test status
Simulation time 12001830211 ps
CPU time 322.63 seconds
Started Jul 28 05:37:53 PM PDT 24
Finished Jul 28 05:43:16 PM PDT 24
Peak memory 222212 kb
Host smart-e08c761f-16b5-46b1-9633-dbb5e2f9628e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698134909 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3698134909
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1479907317
Short name T790
Test name
Test status
Simulation time 248835247 ps
CPU time 1.15 seconds
Started Jul 28 05:37:57 PM PDT 24
Finished Jul 28 05:37:58 PM PDT 24
Peak memory 220188 kb
Host smart-914168da-8032-4908-be73-8848a0988177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479907317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1479907317
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3191160711
Short name T871
Test name
Test status
Simulation time 22056622 ps
CPU time 0.92 seconds
Started Jul 28 05:37:59 PM PDT 24
Finished Jul 28 05:38:00 PM PDT 24
Peak memory 206616 kb
Host smart-58a43319-3ae5-460b-9a17-1bb8f39f2c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191160711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3191160711
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1933938231
Short name T134
Test name
Test status
Simulation time 82136304 ps
CPU time 1.15 seconds
Started Jul 28 05:37:56 PM PDT 24
Finished Jul 28 05:37:58 PM PDT 24
Peak memory 216804 kb
Host smart-e04b6c9f-32c0-499e-b5b3-a2a0d2956bbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933938231 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1933938231
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3205770307
Short name T218
Test name
Test status
Simulation time 31582191 ps
CPU time 0.87 seconds
Started Jul 28 05:37:56 PM PDT 24
Finished Jul 28 05:37:57 PM PDT 24
Peak memory 218320 kb
Host smart-6b7291d6-ba89-45b8-b4ad-9ef6a9e4cf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205770307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3205770307
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.610511387
Short name T574
Test name
Test status
Simulation time 32892255 ps
CPU time 1.38 seconds
Started Jul 28 05:37:55 PM PDT 24
Finished Jul 28 05:37:57 PM PDT 24
Peak memory 218468 kb
Host smart-8e254bba-728e-403b-b112-2a9b20656af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610511387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.610511387
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.366584005
Short name T961
Test name
Test status
Simulation time 25907568 ps
CPU time 0.97 seconds
Started Jul 28 05:37:56 PM PDT 24
Finished Jul 28 05:37:57 PM PDT 24
Peak memory 215388 kb
Host smart-582e4d6d-085e-4a38-889e-d1d9d99fd5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366584005 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.366584005
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.561955653
Short name T538
Test name
Test status
Simulation time 19549002 ps
CPU time 1 seconds
Started Jul 28 05:37:54 PM PDT 24
Finished Jul 28 05:37:55 PM PDT 24
Peak memory 215176 kb
Host smart-598c8aef-3d6c-4d11-8904-6303795c2a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561955653 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.561955653
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3125574293
Short name T720
Test name
Test status
Simulation time 278088291 ps
CPU time 5.07 seconds
Started Jul 28 05:37:54 PM PDT 24
Finished Jul 28 05:37:59 PM PDT 24
Peak memory 215252 kb
Host smart-b3ec4771-8533-4180-92f4-a6af28af76bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125574293 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3125574293
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1296215447
Short name T928
Test name
Test status
Simulation time 24292192315 ps
CPU time 638.9 seconds
Started Jul 28 05:37:59 PM PDT 24
Finished Jul 28 05:48:38 PM PDT 24
Peak memory 217980 kb
Host smart-c1bfd785-9a35-4cf9-baea-0885b9f2ff4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296215447 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1296215447
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3999233230
Short name T598
Test name
Test status
Simulation time 81097868 ps
CPU time 1.13 seconds
Started Jul 28 05:36:44 PM PDT 24
Finished Jul 28 05:36:45 PM PDT 24
Peak memory 218512 kb
Host smart-36202ecc-61f6-4ef7-9626-631911ce32cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999233230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3999233230
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.832177886
Short name T385
Test name
Test status
Simulation time 20108364 ps
CPU time 0.86 seconds
Started Jul 28 05:36:42 PM PDT 24
Finished Jul 28 05:36:43 PM PDT 24
Peak memory 206820 kb
Host smart-6b8686e4-07f1-4b42-aca0-336c9fe406c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832177886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.832177886
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.77694656
Short name T460
Test name
Test status
Simulation time 38258628 ps
CPU time 0.87 seconds
Started Jul 28 05:36:41 PM PDT 24
Finished Jul 28 05:36:42 PM PDT 24
Peak memory 215800 kb
Host smart-19bbb6ea-6c01-471b-8838-593413327933
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77694656 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.77694656
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3746993396
Short name T91
Test name
Test status
Simulation time 52299022 ps
CPU time 1.24 seconds
Started Jul 28 05:36:41 PM PDT 24
Finished Jul 28 05:36:43 PM PDT 24
Peak memory 216812 kb
Host smart-98a8b2a8-bf45-4352-86f1-6fd37bf84585
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746993396 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3746993396
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3287646431
Short name T118
Test name
Test status
Simulation time 26789817 ps
CPU time 0.94 seconds
Started Jul 28 05:36:42 PM PDT 24
Finished Jul 28 05:36:43 PM PDT 24
Peak memory 218480 kb
Host smart-58749907-0ce9-43ab-8fed-158e92148693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287646431 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3287646431
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_intr.1147297668
Short name T628
Test name
Test status
Simulation time 29368581 ps
CPU time 0.93 seconds
Started Jul 28 05:36:39 PM PDT 24
Finished Jul 28 05:36:40 PM PDT 24
Peak memory 215440 kb
Host smart-ad9e8f68-1121-4f8b-ab08-19568d079b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147297668 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1147297668
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.1712385003
Short name T754
Test name
Test status
Simulation time 67966816 ps
CPU time 0.94 seconds
Started Jul 28 05:36:42 PM PDT 24
Finished Jul 28 05:36:43 PM PDT 24
Peak memory 215180 kb
Host smart-b226c6eb-9994-4785-bff2-189f58dde1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712385003 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1712385003
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.276728429
Short name T348
Test name
Test status
Simulation time 129427505 ps
CPU time 2.91 seconds
Started Jul 28 05:36:41 PM PDT 24
Finished Jul 28 05:36:44 PM PDT 24
Peak memory 215156 kb
Host smart-3444987c-9fb8-418f-801f-32e27c580e39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276728429 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.276728429
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2690279018
Short name T608
Test name
Test status
Simulation time 52058960640 ps
CPU time 1297.02 seconds
Started Jul 28 05:36:42 PM PDT 24
Finished Jul 28 05:58:19 PM PDT 24
Peak memory 223748 kb
Host smart-548d4628-39b3-4f26-b9b5-1feebbd64b23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690279018 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2690279018
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2780378588
Short name T873
Test name
Test status
Simulation time 80712492 ps
CPU time 1.18 seconds
Started Jul 28 05:37:57 PM PDT 24
Finished Jul 28 05:37:58 PM PDT 24
Peak memory 219640 kb
Host smart-75c6847f-d660-4fab-b505-9020ad9b4de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780378588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2780378588
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.850378060
Short name T523
Test name
Test status
Simulation time 22092257 ps
CPU time 1.15 seconds
Started Jul 28 05:37:54 PM PDT 24
Finished Jul 28 05:37:55 PM PDT 24
Peak memory 219780 kb
Host smart-40d32152-e089-4011-a25e-319bb1360775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850378060 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.850378060
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.364747547
Short name T890
Test name
Test status
Simulation time 29546991 ps
CPU time 1.23 seconds
Started Jul 28 05:37:55 PM PDT 24
Finished Jul 28 05:37:57 PM PDT 24
Peak memory 218304 kb
Host smart-c59f63bf-74d0-4702-b443-5d16cf233271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364747547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.364747547
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.2668519404
Short name T899
Test name
Test status
Simulation time 60144037 ps
CPU time 1.26 seconds
Started Jul 28 05:37:57 PM PDT 24
Finished Jul 28 05:37:59 PM PDT 24
Peak memory 219180 kb
Host smart-5d5eb4b1-703f-4f84-8d26-4f6afe73dca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668519404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.2668519404
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.568304855
Short name T147
Test name
Test status
Simulation time 24468167 ps
CPU time 1.06 seconds
Started Jul 28 05:37:55 PM PDT 24
Finished Jul 28 05:37:56 PM PDT 24
Peak memory 224004 kb
Host smart-49140df3-4b84-4c8f-a968-afa9fc8b9afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568304855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.568304855
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3580672735
Short name T673
Test name
Test status
Simulation time 41781577 ps
CPU time 1.21 seconds
Started Jul 28 05:37:58 PM PDT 24
Finished Jul 28 05:37:59 PM PDT 24
Peak memory 219280 kb
Host smart-3b8819f9-e62c-42c0-8a91-2d9b64efde6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580672735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3580672735
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.3834798768
Short name T171
Test name
Test status
Simulation time 26611134 ps
CPU time 1.25 seconds
Started Jul 28 05:37:57 PM PDT 24
Finished Jul 28 05:37:59 PM PDT 24
Peak memory 219352 kb
Host smart-298b7679-9f6a-43b4-8cbf-912384731a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834798768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.3834798768
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.2817603737
Short name T151
Test name
Test status
Simulation time 23714107 ps
CPU time 1.01 seconds
Started Jul 28 05:38:00 PM PDT 24
Finished Jul 28 05:38:01 PM PDT 24
Peak memory 218540 kb
Host smart-ce25553e-5d82-4c2f-8651-dc080f125dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817603737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2817603737
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.304017778
Short name T934
Test name
Test status
Simulation time 30133570 ps
CPU time 1.37 seconds
Started Jul 28 05:37:57 PM PDT 24
Finished Jul 28 05:37:59 PM PDT 24
Peak memory 218272 kb
Host smart-52459c37-5a5c-43a9-8904-1a7f6fd375aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304017778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.304017778
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.547795709
Short name T425
Test name
Test status
Simulation time 24932889 ps
CPU time 1.09 seconds
Started Jul 28 05:37:55 PM PDT 24
Finished Jul 28 05:37:56 PM PDT 24
Peak memory 219768 kb
Host smart-9bfaff81-3f9b-4144-ac2b-81c03bc89ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547795709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.547795709
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2330377168
Short name T817
Test name
Test status
Simulation time 34863900 ps
CPU time 1.11 seconds
Started Jul 28 05:37:55 PM PDT 24
Finished Jul 28 05:37:56 PM PDT 24
Peak memory 218520 kb
Host smart-c5abc392-3902-4c4c-9549-68cdab0b8efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330377168 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2330377168
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3039083690
Short name T74
Test name
Test status
Simulation time 65336403 ps
CPU time 1.16 seconds
Started Jul 28 05:37:52 PM PDT 24
Finished Jul 28 05:37:53 PM PDT 24
Peak memory 218740 kb
Host smart-1cbecdf8-a078-47f8-b181-e7774f450f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039083690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3039083690
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.2754538861
Short name T88
Test name
Test status
Simulation time 25982019 ps
CPU time 1.25 seconds
Started Jul 28 05:38:01 PM PDT 24
Finished Jul 28 05:38:02 PM PDT 24
Peak memory 218948 kb
Host smart-a76cdd05-12c7-45be-b910-0d504351e9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754538861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2754538861
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.688683751
Short name T972
Test name
Test status
Simulation time 19788140 ps
CPU time 1.06 seconds
Started Jul 28 05:37:54 PM PDT 24
Finished Jul 28 05:37:55 PM PDT 24
Peak memory 218308 kb
Host smart-4d869d00-780d-45f4-a5c7-895cebdc6538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688683751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.688683751
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2844012296
Short name T303
Test name
Test status
Simulation time 79302454 ps
CPU time 2.15 seconds
Started Jul 28 05:37:55 PM PDT 24
Finished Jul 28 05:37:58 PM PDT 24
Peak memory 219552 kb
Host smart-8ee1175b-465e-47d1-98c7-f5ea636ce3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844012296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2844012296
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.72303412
Short name T499
Test name
Test status
Simulation time 24450436 ps
CPU time 1.14 seconds
Started Jul 28 05:37:55 PM PDT 24
Finished Jul 28 05:37:56 PM PDT 24
Peak memory 218356 kb
Host smart-3d39f317-45d1-448f-923f-a230e05b838c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72303412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.72303412
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2483102091
Short name T122
Test name
Test status
Simulation time 24489310 ps
CPU time 0.93 seconds
Started Jul 28 05:37:56 PM PDT 24
Finished Jul 28 05:37:57 PM PDT 24
Peak memory 218108 kb
Host smart-b429292c-014c-4d3d-af6b-d74b01ba015e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483102091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2483102091
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.256752750
Short name T551
Test name
Test status
Simulation time 44172194 ps
CPU time 1.29 seconds
Started Jul 28 05:38:00 PM PDT 24
Finished Jul 28 05:38:01 PM PDT 24
Peak memory 218516 kb
Host smart-aaf33567-2d14-4fac-a56d-80b6414e178a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256752750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.256752750
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.3348995008
Short name T456
Test name
Test status
Simulation time 61335464 ps
CPU time 1.28 seconds
Started Jul 28 05:38:01 PM PDT 24
Finished Jul 28 05:38:03 PM PDT 24
Peak memory 218436 kb
Host smart-7320d855-02a3-4abf-901c-f7f5a7bb134f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348995008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.3348995008
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1403055052
Short name T146
Test name
Test status
Simulation time 58059504 ps
CPU time 0.87 seconds
Started Jul 28 05:38:05 PM PDT 24
Finished Jul 28 05:38:06 PM PDT 24
Peak memory 218360 kb
Host smart-1f57f9c3-41d8-4094-ab1a-652f1eab3e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403055052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1403055052
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2461636227
Short name T951
Test name
Test status
Simulation time 96475953 ps
CPU time 1.05 seconds
Started Jul 28 05:38:04 PM PDT 24
Finished Jul 28 05:38:05 PM PDT 24
Peak memory 217340 kb
Host smart-5232f2b1-5e3f-4ab9-a364-000fd6347f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461636227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2461636227
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3008884580
Short name T453
Test name
Test status
Simulation time 80297741 ps
CPU time 1.29 seconds
Started Jul 28 05:38:01 PM PDT 24
Finished Jul 28 05:38:03 PM PDT 24
Peak memory 218720 kb
Host smart-82690b47-42ef-47b5-833e-02fc8bb9245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008884580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3008884580
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.2840344879
Short name T195
Test name
Test status
Simulation time 45173522 ps
CPU time 0.88 seconds
Started Jul 28 05:38:10 PM PDT 24
Finished Jul 28 05:38:11 PM PDT 24
Peak memory 219444 kb
Host smart-e0989c0c-5264-4848-8611-98b980bfdee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840344879 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2840344879
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2707128862
Short name T571
Test name
Test status
Simulation time 259893501 ps
CPU time 3.58 seconds
Started Jul 28 05:38:00 PM PDT 24
Finished Jul 28 05:38:04 PM PDT 24
Peak memory 218540 kb
Host smart-c941890b-5a75-45cb-8bb3-f81b17254039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707128862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2707128862
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.2806571983
Short name T220
Test name
Test status
Simulation time 73587532 ps
CPU time 1.12 seconds
Started Jul 28 05:38:10 PM PDT 24
Finished Jul 28 05:38:11 PM PDT 24
Peak memory 220268 kb
Host smart-df7d6169-7c45-4a96-8915-210a2f4d9f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806571983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.2806571983
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.3245086200
Short name T437
Test name
Test status
Simulation time 149487969 ps
CPU time 1 seconds
Started Jul 28 05:38:05 PM PDT 24
Finished Jul 28 05:38:06 PM PDT 24
Peak memory 218388 kb
Host smart-9e43e6b6-8ecf-4052-9779-10e1365597a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245086200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3245086200
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1300153217
Short name T546
Test name
Test status
Simulation time 85517426 ps
CPU time 2.94 seconds
Started Jul 28 05:38:02 PM PDT 24
Finished Jul 28 05:38:05 PM PDT 24
Peak memory 218496 kb
Host smart-9c45f614-8de7-4765-8f2c-2034d716721d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300153217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1300153217
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.320440203
Short name T847
Test name
Test status
Simulation time 29317288 ps
CPU time 1.26 seconds
Started Jul 28 05:38:02 PM PDT 24
Finished Jul 28 05:38:03 PM PDT 24
Peak memory 218180 kb
Host smart-acad6f27-ede3-45d3-9faa-65da86d72f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320440203 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.320440203
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.115209094
Short name T750
Test name
Test status
Simulation time 29564755 ps
CPU time 1.37 seconds
Started Jul 28 05:38:05 PM PDT 24
Finished Jul 28 05:38:06 PM PDT 24
Peak memory 225808 kb
Host smart-ab4d4c0d-87f7-4a59-a874-ce4d12eb153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115209094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.115209094
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3464088163
Short name T413
Test name
Test status
Simulation time 41702427 ps
CPU time 1.86 seconds
Started Jul 28 05:38:03 PM PDT 24
Finished Jul 28 05:38:05 PM PDT 24
Peak memory 220332 kb
Host smart-6723e6f8-4958-4293-9d0d-6b77cdd11391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464088163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3464088163
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3762542606
Short name T876
Test name
Test status
Simulation time 26525907 ps
CPU time 1.3 seconds
Started Jul 28 05:36:42 PM PDT 24
Finished Jul 28 05:36:43 PM PDT 24
Peak memory 218556 kb
Host smart-38dc8e9d-954e-481b-8423-bfdc02623380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762542606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3762542606
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.419533287
Short name T735
Test name
Test status
Simulation time 21867282 ps
CPU time 0.97 seconds
Started Jul 28 05:36:42 PM PDT 24
Finished Jul 28 05:36:43 PM PDT 24
Peak memory 214752 kb
Host smart-0ec60a6f-b892-45d5-89bb-ed98e6f1ae82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419533287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.419533287
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.308496266
Short name T665
Test name
Test status
Simulation time 32821778 ps
CPU time 0.86 seconds
Started Jul 28 05:36:44 PM PDT 24
Finished Jul 28 05:36:45 PM PDT 24
Peak memory 216140 kb
Host smart-7b1124be-f65a-4e3b-bfdf-a82f041237e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308496266 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.308496266
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1952661380
Short name T575
Test name
Test status
Simulation time 30811478 ps
CPU time 1.18 seconds
Started Jul 28 05:36:39 PM PDT 24
Finished Jul 28 05:36:41 PM PDT 24
Peak memory 218368 kb
Host smart-1d983542-1432-46f8-afc0-c838ce2d5a6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952661380 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1952661380
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2002196751
Short name T638
Test name
Test status
Simulation time 30134321 ps
CPU time 1.27 seconds
Started Jul 28 05:36:38 PM PDT 24
Finished Jul 28 05:36:40 PM PDT 24
Peak memory 225516 kb
Host smart-f29be59e-bcdc-4349-aa1a-588cf2c39ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002196751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2002196751
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1398477130
Short name T77
Test name
Test status
Simulation time 33751795 ps
CPU time 1.47 seconds
Started Jul 28 05:36:39 PM PDT 24
Finished Jul 28 05:36:40 PM PDT 24
Peak memory 218500 kb
Host smart-81940bd6-4c89-4ec9-b8c2-61adbc105f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398477130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1398477130
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.4024510149
Short name T634
Test name
Test status
Simulation time 21149438 ps
CPU time 1.22 seconds
Started Jul 28 05:36:40 PM PDT 24
Finished Jul 28 05:36:41 PM PDT 24
Peak memory 225036 kb
Host smart-dc943fc1-9ead-41f1-8521-37e5bf4fc482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024510149 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.4024510149
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.793688401
Short name T755
Test name
Test status
Simulation time 17819685 ps
CPU time 0.99 seconds
Started Jul 28 05:36:39 PM PDT 24
Finished Jul 28 05:36:40 PM PDT 24
Peak memory 207044 kb
Host smart-81664709-c512-458e-9281-6dcd0a496e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793688401 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.793688401
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.630958919
Short name T494
Test name
Test status
Simulation time 90040596 ps
CPU time 0.96 seconds
Started Jul 28 05:36:39 PM PDT 24
Finished Jul 28 05:36:40 PM PDT 24
Peak memory 207004 kb
Host smart-c164ac6e-2943-4e96-8288-4c1e1c1fc1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630958919 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.630958919
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3668225424
Short name T577
Test name
Test status
Simulation time 189086830 ps
CPU time 3.53 seconds
Started Jul 28 05:36:41 PM PDT 24
Finished Jul 28 05:36:45 PM PDT 24
Peak memory 217396 kb
Host smart-7ba6271e-da21-4465-ad33-ab760dc18d92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668225424 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3668225424
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.621294349
Short name T726
Test name
Test status
Simulation time 225402234484 ps
CPU time 3142.95 seconds
Started Jul 28 05:36:38 PM PDT 24
Finished Jul 28 06:29:02 PM PDT 24
Peak memory 230472 kb
Host smart-fde88a14-a36b-45c1-bc34-b14089dc23b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621294349 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.621294349
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1374479944
Short name T234
Test name
Test status
Simulation time 71586949 ps
CPU time 1.3 seconds
Started Jul 28 05:38:00 PM PDT 24
Finished Jul 28 05:38:02 PM PDT 24
Peak memory 218500 kb
Host smart-83eb77be-c560-4719-970f-ce8210a16ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374479944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1374479944
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.2409706637
Short name T45
Test name
Test status
Simulation time 50037883 ps
CPU time 0.88 seconds
Started Jul 28 05:38:02 PM PDT 24
Finished Jul 28 05:38:03 PM PDT 24
Peak memory 218072 kb
Host smart-b37267f5-dc2e-461b-a1aa-c4e860d333b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409706637 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2409706637
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.645167929
Short name T655
Test name
Test status
Simulation time 33774606 ps
CPU time 1.3 seconds
Started Jul 28 05:38:07 PM PDT 24
Finished Jul 28 05:38:08 PM PDT 24
Peak memory 218384 kb
Host smart-c2dbed71-9b21-4cac-b7b8-15fcd62651f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645167929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.645167929
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1460785287
Short name T678
Test name
Test status
Simulation time 25620765 ps
CPU time 1.22 seconds
Started Jul 28 05:38:00 PM PDT 24
Finished Jul 28 05:38:02 PM PDT 24
Peak memory 218416 kb
Host smart-37d86883-caad-483d-baf3-76e0a5404808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460785287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1460785287
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.2046169307
Short name T58
Test name
Test status
Simulation time 23293233 ps
CPU time 0.94 seconds
Started Jul 28 05:38:04 PM PDT 24
Finished Jul 28 05:38:05 PM PDT 24
Peak memory 218220 kb
Host smart-21ab999e-2502-49a7-92a7-3aa04904e55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046169307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2046169307
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3760224515
Short name T940
Test name
Test status
Simulation time 205434510 ps
CPU time 1.55 seconds
Started Jul 28 05:38:01 PM PDT 24
Finished Jul 28 05:38:03 PM PDT 24
Peak memory 219872 kb
Host smart-8e6d5413-2166-4193-81d5-f9c95e463e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760224515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3760224515
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.4131351737
Short name T173
Test name
Test status
Simulation time 44618395 ps
CPU time 1.19 seconds
Started Jul 28 05:38:05 PM PDT 24
Finished Jul 28 05:38:06 PM PDT 24
Peak memory 220264 kb
Host smart-a659276c-57d0-4ca3-bbe1-b6d1212d88bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131351737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.4131351737
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1624674567
Short name T828
Test name
Test status
Simulation time 31850733 ps
CPU time 0.88 seconds
Started Jul 28 05:38:03 PM PDT 24
Finished Jul 28 05:38:04 PM PDT 24
Peak memory 218108 kb
Host smart-19f7e6f4-7e6d-486a-87db-b04558a85b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624674567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1624674567
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1710658062
Short name T926
Test name
Test status
Simulation time 52796546 ps
CPU time 1.38 seconds
Started Jul 28 05:38:02 PM PDT 24
Finished Jul 28 05:38:03 PM PDT 24
Peak memory 218364 kb
Host smart-1d71cb58-ad7f-48b3-9302-98019e7eadfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710658062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1710658062
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.1952876666
Short name T519
Test name
Test status
Simulation time 44922839 ps
CPU time 1.3 seconds
Started Jul 28 05:38:01 PM PDT 24
Finished Jul 28 05:38:02 PM PDT 24
Peak memory 218856 kb
Host smart-bea6502f-acae-4857-bf3d-8731658af824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952876666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.1952876666
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.820408565
Short name T624
Test name
Test status
Simulation time 76387276 ps
CPU time 1.2 seconds
Started Jul 28 05:38:00 PM PDT 24
Finished Jul 28 05:38:01 PM PDT 24
Peak memory 225632 kb
Host smart-4c2adf74-0dae-4dcd-b077-c82f930d9c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820408565 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.820408565
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3018796357
Short name T744
Test name
Test status
Simulation time 135916142 ps
CPU time 1.26 seconds
Started Jul 28 05:38:03 PM PDT 24
Finished Jul 28 05:38:04 PM PDT 24
Peak memory 218532 kb
Host smart-8cb12e9f-4ae5-46e2-9b41-f5b37812c30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018796357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3018796357
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.879028437
Short name T812
Test name
Test status
Simulation time 111353410 ps
CPU time 1.2 seconds
Started Jul 28 05:38:00 PM PDT 24
Finished Jul 28 05:38:02 PM PDT 24
Peak memory 218804 kb
Host smart-2255ca67-ce91-4bdf-91c8-b64da9dede41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879028437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.879028437
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.2979118716
Short name T682
Test name
Test status
Simulation time 27370890 ps
CPU time 0.88 seconds
Started Jul 28 05:38:04 PM PDT 24
Finished Jul 28 05:38:05 PM PDT 24
Peak memory 218384 kb
Host smart-38b0d422-5017-4e54-8191-99710ae75692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979118716 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2979118716
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2771674780
Short name T483
Test name
Test status
Simulation time 35303340 ps
CPU time 1.3 seconds
Started Jul 28 05:38:10 PM PDT 24
Finished Jul 28 05:38:11 PM PDT 24
Peak memory 219704 kb
Host smart-15ae64a7-09c5-4712-95a1-4fac79d42802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771674780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2771674780
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3662475149
Short name T743
Test name
Test status
Simulation time 76182946 ps
CPU time 1.24 seconds
Started Jul 28 05:38:01 PM PDT 24
Finished Jul 28 05:38:03 PM PDT 24
Peak memory 218556 kb
Host smart-dd2369f6-b6a3-41ed-9022-6f15880e7cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662475149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3662475149
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.1812062592
Short name T867
Test name
Test status
Simulation time 41955068 ps
CPU time 0.83 seconds
Started Jul 28 05:38:00 PM PDT 24
Finished Jul 28 05:38:01 PM PDT 24
Peak memory 219012 kb
Host smart-9a9b86bd-e1a3-4e95-a00c-48a9f06df389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812062592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1812062592
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3210364548
Short name T613
Test name
Test status
Simulation time 375685844 ps
CPU time 3.76 seconds
Started Jul 28 05:38:02 PM PDT 24
Finished Jul 28 05:38:06 PM PDT 24
Peak memory 217324 kb
Host smart-c4a40679-db3f-4e2b-9a68-71353a3ebcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210364548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3210364548
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.3288333686
Short name T590
Test name
Test status
Simulation time 33093444 ps
CPU time 1.15 seconds
Started Jul 28 05:38:03 PM PDT 24
Finished Jul 28 05:38:05 PM PDT 24
Peak memory 218752 kb
Host smart-23fc5e63-0526-491f-9278-adc51e23d749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288333686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.3288333686
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1235631985
Short name T277
Test name
Test status
Simulation time 28737985 ps
CPU time 0.97 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:09 PM PDT 24
Peak memory 217988 kb
Host smart-fe61e565-c101-4a67-89f4-7cd24dd33212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235631985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1235631985
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2530078423
Short name T690
Test name
Test status
Simulation time 35759601 ps
CPU time 1.53 seconds
Started Jul 28 05:38:04 PM PDT 24
Finished Jul 28 05:38:06 PM PDT 24
Peak memory 218420 kb
Host smart-a080eef7-8e2f-4cf5-af96-abf82660e4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530078423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2530078423
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.2105190665
Short name T914
Test name
Test status
Simulation time 74511319 ps
CPU time 1.21 seconds
Started Jul 28 05:38:01 PM PDT 24
Finished Jul 28 05:38:02 PM PDT 24
Peak memory 218516 kb
Host smart-dd5924dc-d811-491d-b2bc-ad087a6a04e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105190665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2105190665
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.114794376
Short name T117
Test name
Test status
Simulation time 97677831 ps
CPU time 0.98 seconds
Started Jul 28 05:38:00 PM PDT 24
Finished Jul 28 05:38:01 PM PDT 24
Peak memory 219452 kb
Host smart-44e3d0b8-6b11-4017-a0de-1f28d66f940d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114794376 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.114794376
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3267316760
Short name T572
Test name
Test status
Simulation time 82773232 ps
CPU time 1.28 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 218244 kb
Host smart-01d40569-60c2-499a-9267-78a3a5ac9c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267316760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3267316760
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1098949131
Short name T20
Test name
Test status
Simulation time 65261787 ps
CPU time 1.04 seconds
Started Jul 28 05:38:15 PM PDT 24
Finished Jul 28 05:38:16 PM PDT 24
Peak memory 219260 kb
Host smart-c463b980-9716-49d8-9c64-0d8239748622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098949131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1098949131
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.2965176249
Short name T779
Test name
Test status
Simulation time 20548892 ps
CPU time 1.1 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:09 PM PDT 24
Peak memory 218612 kb
Host smart-f9b456ca-12b0-4cc2-b2a8-ee4868fda93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965176249 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2965176249
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2333804140
Short name T807
Test name
Test status
Simulation time 110916398 ps
CPU time 2.6 seconds
Started Jul 28 05:38:01 PM PDT 24
Finished Jul 28 05:38:04 PM PDT 24
Peak memory 219620 kb
Host smart-42cf853c-e848-4a06-912c-1a37e03c7c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333804140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2333804140
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.427707148
Short name T719
Test name
Test status
Simulation time 123820791 ps
CPU time 1.22 seconds
Started Jul 28 05:38:09 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 215492 kb
Host smart-7deeef6c-be9f-4e88-ae9d-2643895d7acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427707148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.427707148
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2301596570
Short name T837
Test name
Test status
Simulation time 19371490 ps
CPU time 1.1 seconds
Started Jul 28 05:38:09 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 218548 kb
Host smart-ea845dbc-aa46-4dad-83f0-34ad62fe9c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301596570 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2301596570
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.3365457936
Short name T264
Test name
Test status
Simulation time 47800322 ps
CPU time 1.17 seconds
Started Jul 28 05:36:46 PM PDT 24
Finished Jul 28 05:36:47 PM PDT 24
Peak memory 218384 kb
Host smart-bf49960a-ccc0-4715-a71f-2783f69d77d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365457936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3365457936
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.386342344
Short name T938
Test name
Test status
Simulation time 40227126 ps
CPU time 0.88 seconds
Started Jul 28 05:36:44 PM PDT 24
Finished Jul 28 05:36:45 PM PDT 24
Peak memory 206564 kb
Host smart-f0a67a60-4471-4ce5-9b28-19503c924cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386342344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.386342344
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.4253796356
Short name T144
Test name
Test status
Simulation time 37150969 ps
CPU time 0.82 seconds
Started Jul 28 05:36:45 PM PDT 24
Finished Jul 28 05:36:46 PM PDT 24
Peak memory 216160 kb
Host smart-3f173fcf-6381-45bf-a5cd-5809fb4fec28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253796356 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.4253796356
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2725965108
Short name T948
Test name
Test status
Simulation time 33456337 ps
CPU time 1.22 seconds
Started Jul 28 05:36:47 PM PDT 24
Finished Jul 28 05:36:49 PM PDT 24
Peak memory 218352 kb
Host smart-c993056a-2c16-4728-bb94-e97a38c8f138
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725965108 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2725965108
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1523964193
Short name T231
Test name
Test status
Simulation time 22876831 ps
CPU time 1.11 seconds
Started Jul 28 05:36:46 PM PDT 24
Finished Jul 28 05:36:47 PM PDT 24
Peak memory 219560 kb
Host smart-2a4386b1-b845-4cdf-beec-28655130c6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523964193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1523964193
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.4123047451
Short name T40
Test name
Test status
Simulation time 122182462 ps
CPU time 1.33 seconds
Started Jul 28 05:36:47 PM PDT 24
Finished Jul 28 05:36:49 PM PDT 24
Peak memory 218488 kb
Host smart-a92d3be4-7b47-486d-8d0c-d45e62133e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123047451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.4123047451
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1488330845
Short name T154
Test name
Test status
Simulation time 23048058 ps
CPU time 0.94 seconds
Started Jul 28 05:36:51 PM PDT 24
Finished Jul 28 05:36:52 PM PDT 24
Peak memory 215880 kb
Host smart-880714cb-d508-4015-bc8f-7484e3b30c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488330845 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1488330845
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2366337145
Short name T96
Test name
Test status
Simulation time 19024116 ps
CPU time 1.08 seconds
Started Jul 28 05:36:45 PM PDT 24
Finished Jul 28 05:36:46 PM PDT 24
Peak memory 206964 kb
Host smart-f9e2819f-08ce-46a0-89b9-35de4503ca5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366337145 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2366337145
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1473752926
Short name T864
Test name
Test status
Simulation time 31309305 ps
CPU time 1.01 seconds
Started Jul 28 05:36:48 PM PDT 24
Finished Jul 28 05:36:49 PM PDT 24
Peak memory 215324 kb
Host smart-44cdfbf7-afa3-44fb-8542-f21fa985c53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473752926 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1473752926
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2411219262
Short name T646
Test name
Test status
Simulation time 475364721 ps
CPU time 3.03 seconds
Started Jul 28 05:36:43 PM PDT 24
Finished Jul 28 05:36:47 PM PDT 24
Peak memory 215232 kb
Host smart-46a7eae2-f64a-4adc-b0e5-14b8c750c0eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411219262 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2411219262
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2332505857
Short name T959
Test name
Test status
Simulation time 78959536435 ps
CPU time 521.1 seconds
Started Jul 28 05:36:47 PM PDT 24
Finished Jul 28 05:45:28 PM PDT 24
Peak memory 223624 kb
Host smart-e2b425ea-bce6-4ba0-86f8-b9f33159136a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332505857 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2332505857
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.3117376382
Short name T222
Test name
Test status
Simulation time 78968992 ps
CPU time 1.19 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:09 PM PDT 24
Peak memory 220128 kb
Host smart-de36efbc-d5c1-434d-bf25-abaa69a405c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117376382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.3117376382
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.3022905282
Short name T569
Test name
Test status
Simulation time 18566971 ps
CPU time 1.03 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 218284 kb
Host smart-e6f185cc-3e3e-4ff2-b66a-e56b3b23f60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022905282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3022905282
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/71.edn_alert.2413975461
Short name T766
Test name
Test status
Simulation time 84566059 ps
CPU time 1.28 seconds
Started Jul 28 05:38:09 PM PDT 24
Finished Jul 28 05:38:11 PM PDT 24
Peak memory 219044 kb
Host smart-f46dd417-64e2-4ed6-9817-441bfdcb9a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413975461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2413975461
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.3199079146
Short name T931
Test name
Test status
Simulation time 18181355 ps
CPU time 1.1 seconds
Started Jul 28 05:38:07 PM PDT 24
Finished Jul 28 05:38:08 PM PDT 24
Peak memory 218412 kb
Host smart-9c5b9f37-2caa-4c43-a4e9-fcd7a218df4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199079146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3199079146
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.167813003
Short name T344
Test name
Test status
Simulation time 117329220 ps
CPU time 2.59 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:11 PM PDT 24
Peak memory 218560 kb
Host smart-85c9b5c6-173e-458c-90f6-9742000ad7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167813003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.167813003
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1869620760
Short name T492
Test name
Test status
Simulation time 42030850 ps
CPU time 1.17 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 218600 kb
Host smart-d18d91c8-2d87-4e68-8af0-4d13f0b0f566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869620760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1869620760
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.2866709084
Short name T153
Test name
Test status
Simulation time 78395748 ps
CPU time 1.01 seconds
Started Jul 28 05:38:09 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 219624 kb
Host smart-a9e2671e-c2bd-453e-a440-7bfb1408b9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866709084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2866709084
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2499278593
Short name T883
Test name
Test status
Simulation time 84263851 ps
CPU time 0.99 seconds
Started Jul 28 05:38:15 PM PDT 24
Finished Jul 28 05:38:16 PM PDT 24
Peak memory 217256 kb
Host smart-d8564f9f-d138-4f49-a57c-e8404eabe012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499278593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2499278593
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.1665067806
Short name T475
Test name
Test status
Simulation time 76777651 ps
CPU time 1.2 seconds
Started Jul 28 05:38:07 PM PDT 24
Finished Jul 28 05:38:09 PM PDT 24
Peak memory 220300 kb
Host smart-b1c31d1a-f350-409e-8a89-64ba10a36781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665067806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.1665067806
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3888816264
Short name T4
Test name
Test status
Simulation time 21097603 ps
CPU time 0.91 seconds
Started Jul 28 05:38:10 PM PDT 24
Finished Jul 28 05:38:11 PM PDT 24
Peak memory 218348 kb
Host smart-87e03ee1-2a3c-461c-a316-a515dd22e20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888816264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3888816264
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2279914293
Short name T496
Test name
Test status
Simulation time 65685296 ps
CPU time 1.35 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 218456 kb
Host smart-aae0c6a5-ef53-438b-96c4-1ddb7ca5eb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279914293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2279914293
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.1573737383
Short name T723
Test name
Test status
Simulation time 90156539 ps
CPU time 1.13 seconds
Started Jul 28 05:38:15 PM PDT 24
Finished Jul 28 05:38:16 PM PDT 24
Peak memory 218392 kb
Host smart-dbfc3f4a-b2c7-4670-8055-b4dbb3a18936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573737383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.1573737383
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_genbits.1500383196
Short name T408
Test name
Test status
Simulation time 52792084 ps
CPU time 1.29 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 218220 kb
Host smart-0b379616-af14-4352-a932-0df296c43dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500383196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1500383196
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.4264922553
Short name T226
Test name
Test status
Simulation time 28416503 ps
CPU time 1.19 seconds
Started Jul 28 05:38:09 PM PDT 24
Finished Jul 28 05:38:11 PM PDT 24
Peak memory 218676 kb
Host smart-0313b374-7a95-4c9a-803d-d64b14b74a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264922553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.4264922553
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.1396633729
Short name T139
Test name
Test status
Simulation time 36421861 ps
CPU time 0.89 seconds
Started Jul 28 05:38:07 PM PDT 24
Finished Jul 28 05:38:08 PM PDT 24
Peak memory 218392 kb
Host smart-0ef207ce-1172-4170-b50f-059a69b93ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396633729 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1396633729
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1560342912
Short name T919
Test name
Test status
Simulation time 88791750 ps
CPU time 1.75 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:09 PM PDT 24
Peak memory 218564 kb
Host smart-7462c5b4-115d-49d0-a574-baa1c615ad17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560342912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1560342912
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.2761640777
Short name T880
Test name
Test status
Simulation time 21291265 ps
CPU time 1.07 seconds
Started Jul 28 05:38:07 PM PDT 24
Finished Jul 28 05:38:08 PM PDT 24
Peak memory 218228 kb
Host smart-f7e43db4-0a36-4ec3-8bda-9f8b733c0363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761640777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.2761640777
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.334816806
Short name T7
Test name
Test status
Simulation time 24053062 ps
CPU time 1.22 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 220676 kb
Host smart-c2b894d3-5991-4aa6-ae01-dcab7e8a6c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334816806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.334816806
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2023714887
Short name T34
Test name
Test status
Simulation time 82251714 ps
CPU time 2.96 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:12 PM PDT 24
Peak memory 218408 kb
Host smart-af234588-9c30-4ede-969c-04e5ca5bf734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023714887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2023714887
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.2943548399
Short name T820
Test name
Test status
Simulation time 29053813 ps
CPU time 1.15 seconds
Started Jul 28 05:38:09 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 218396 kb
Host smart-84acddfb-b541-4467-9116-25ee8be4f1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943548399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.2943548399
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.954271991
Short name T936
Test name
Test status
Simulation time 29786728 ps
CPU time 1.13 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:09 PM PDT 24
Peak memory 220520 kb
Host smart-2227bb3d-2079-4a9e-8b59-2c1331ea7dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954271991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.954271991
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1567501463
Short name T490
Test name
Test status
Simulation time 77895012 ps
CPU time 1.22 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:09 PM PDT 24
Peak memory 218332 kb
Host smart-575e885a-4d05-4882-ab42-a59188abc826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567501463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1567501463
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.2477263722
Short name T470
Test name
Test status
Simulation time 25668359 ps
CPU time 1.16 seconds
Started Jul 28 05:38:07 PM PDT 24
Finished Jul 28 05:38:08 PM PDT 24
Peak memory 218396 kb
Host smart-bef5f235-671b-4aad-b589-fd83461b654c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477263722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.2477263722
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.796576640
Short name T632
Test name
Test status
Simulation time 33014501 ps
CPU time 0.96 seconds
Started Jul 28 05:38:07 PM PDT 24
Finished Jul 28 05:38:08 PM PDT 24
Peak memory 218236 kb
Host smart-8fc636eb-f6d3-40b1-8c73-61e817d5b2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796576640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.796576640
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1123732566
Short name T479
Test name
Test status
Simulation time 106069569 ps
CPU time 1.21 seconds
Started Jul 28 05:38:12 PM PDT 24
Finished Jul 28 05:38:14 PM PDT 24
Peak memory 217200 kb
Host smart-0e6f72b0-6ade-430c-a25e-13d7862ac2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123732566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1123732566
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.2857412729
Short name T193
Test name
Test status
Simulation time 50710788 ps
CPU time 1.2 seconds
Started Jul 28 05:38:09 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 220688 kb
Host smart-025d62c4-ddf6-4c15-a564-fc960c4adc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857412729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2857412729
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.4117086292
Short name T203
Test name
Test status
Simulation time 18861189 ps
CPU time 1.19 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 223844 kb
Host smart-c468aee4-93cd-464d-8e13-6873036ab3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117086292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.4117086292
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2057551580
Short name T497
Test name
Test status
Simulation time 27956284 ps
CPU time 1.34 seconds
Started Jul 28 05:38:08 PM PDT 24
Finished Jul 28 05:38:10 PM PDT 24
Peak memory 218352 kb
Host smart-ab88dac8-3f38-42ed-8c14-3ac89eb297b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057551580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2057551580
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3103196383
Short name T300
Test name
Test status
Simulation time 29608200 ps
CPU time 1.27 seconds
Started Jul 28 05:36:47 PM PDT 24
Finished Jul 28 05:36:49 PM PDT 24
Peak memory 220724 kb
Host smart-a05a4ba1-2b2b-48a1-8d06-f2075920824b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103196383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3103196383
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2687382148
Short name T692
Test name
Test status
Simulation time 34925072 ps
CPU time 0.83 seconds
Started Jul 28 05:36:47 PM PDT 24
Finished Jul 28 05:36:48 PM PDT 24
Peak memory 206576 kb
Host smart-ff8a0157-7c6f-425e-b6d3-d0773eb98360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687382148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2687382148
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2338335260
Short name T510
Test name
Test status
Simulation time 14816412 ps
CPU time 1 seconds
Started Jul 28 05:36:48 PM PDT 24
Finished Jul 28 05:36:49 PM PDT 24
Peak memory 216276 kb
Host smart-a57c7194-305d-4919-828c-20c7f105dcce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338335260 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2338335260
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3638989491
Short name T145
Test name
Test status
Simulation time 47679756 ps
CPU time 1.09 seconds
Started Jul 28 05:36:46 PM PDT 24
Finished Jul 28 05:36:47 PM PDT 24
Peak memory 216700 kb
Host smart-96ca8180-5165-46a0-92a4-dfc05c829068
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638989491 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3638989491
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2545377500
Short name T121
Test name
Test status
Simulation time 18015547 ps
CPU time 1.05 seconds
Started Jul 28 05:36:46 PM PDT 24
Finished Jul 28 05:36:47 PM PDT 24
Peak memory 218112 kb
Host smart-c7c5edf3-66b1-4aea-b0d7-f0523c4fd3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545377500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2545377500
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2429280011
Short name T905
Test name
Test status
Simulation time 93447530 ps
CPU time 2.6 seconds
Started Jul 28 05:36:47 PM PDT 24
Finished Jul 28 05:36:50 PM PDT 24
Peak memory 219792 kb
Host smart-3dc7c1c5-6987-4aee-beb8-b91c8da90427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429280011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2429280011
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.4017896318
Short name T516
Test name
Test status
Simulation time 30502907 ps
CPU time 1.13 seconds
Started Jul 28 05:36:50 PM PDT 24
Finished Jul 28 05:36:51 PM PDT 24
Peak memory 223912 kb
Host smart-a194b41b-e0ba-4e2e-b0fb-40c10d2d4d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017896318 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.4017896318
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1031125072
Short name T679
Test name
Test status
Simulation time 19084729 ps
CPU time 1.04 seconds
Started Jul 28 05:36:45 PM PDT 24
Finished Jul 28 05:36:46 PM PDT 24
Peak memory 206976 kb
Host smart-a5e0783c-f719-49f7-b336-6270cc6b3923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031125072 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1031125072
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1603929326
Short name T473
Test name
Test status
Simulation time 38083563 ps
CPU time 0.89 seconds
Started Jul 28 05:36:44 PM PDT 24
Finished Jul 28 05:36:45 PM PDT 24
Peak memory 215128 kb
Host smart-09ae04d0-0971-4899-a2b0-af7075a54f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603929326 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1603929326
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2064965158
Short name T578
Test name
Test status
Simulation time 117992136 ps
CPU time 2.09 seconds
Started Jul 28 05:36:44 PM PDT 24
Finished Jul 28 05:36:46 PM PDT 24
Peak memory 217148 kb
Host smart-a647db07-385e-4512-b90a-97fc36ca0d00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064965158 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2064965158
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.623389467
Short name T252
Test name
Test status
Simulation time 327757699697 ps
CPU time 1213.76 seconds
Started Jul 28 05:36:45 PM PDT 24
Finished Jul 28 05:56:59 PM PDT 24
Peak memory 223708 kb
Host smart-e0faf1fe-6bda-4b64-aa85-6a554f36b65f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623389467 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.623389467
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.215441439
Short name T53
Test name
Test status
Simulation time 116680619 ps
CPU time 1.09 seconds
Started Jul 28 05:38:15 PM PDT 24
Finished Jul 28 05:38:17 PM PDT 24
Peak memory 218420 kb
Host smart-b1ac975f-effe-4373-a4e0-fa6eeeb66096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215441439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.215441439
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.2646848099
Short name T668
Test name
Test status
Simulation time 18249783 ps
CPU time 1.21 seconds
Started Jul 28 05:38:11 PM PDT 24
Finished Jul 28 05:38:12 PM PDT 24
Peak memory 223840 kb
Host smart-cecdd885-7b2d-47d3-93d1-2439a0e2cb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646848099 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2646848099
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2504345321
Short name T964
Test name
Test status
Simulation time 42469876 ps
CPU time 1.78 seconds
Started Jul 28 05:38:10 PM PDT 24
Finished Jul 28 05:38:11 PM PDT 24
Peak memory 219120 kb
Host smart-d13bc76d-823a-4912-a7af-6e6a720f23d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504345321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2504345321
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1544305170
Short name T506
Test name
Test status
Simulation time 74727588 ps
CPU time 1.18 seconds
Started Jul 28 05:38:16 PM PDT 24
Finished Jul 28 05:38:17 PM PDT 24
Peak memory 218460 kb
Host smart-dc814d90-ecc0-4522-95ca-43253dbe000e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544305170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1544305170
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2360962422
Short name T176
Test name
Test status
Simulation time 26359843 ps
CPU time 1.14 seconds
Started Jul 28 05:38:15 PM PDT 24
Finished Jul 28 05:38:16 PM PDT 24
Peak memory 229464 kb
Host smart-0c3d5fa5-3298-4c47-bc1d-bdbcb5264aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360962422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2360962422
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.11077617
Short name T860
Test name
Test status
Simulation time 135838167 ps
CPU time 1.02 seconds
Started Jul 28 05:38:07 PM PDT 24
Finished Jul 28 05:38:08 PM PDT 24
Peak memory 217120 kb
Host smart-7af53cf6-6186-4e30-996c-ea736a6646c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11077617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.11077617
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2768500635
Short name T622
Test name
Test status
Simulation time 28546983 ps
CPU time 1.25 seconds
Started Jul 28 05:38:11 PM PDT 24
Finished Jul 28 05:38:12 PM PDT 24
Peak memory 219712 kb
Host smart-dc48965a-9849-43ac-84f7-228e48e21547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768500635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2768500635
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.4284125034
Short name T977
Test name
Test status
Simulation time 50759793 ps
CPU time 1.8 seconds
Started Jul 28 05:38:17 PM PDT 24
Finished Jul 28 05:38:18 PM PDT 24
Peak memory 219888 kb
Host smart-39ed4135-8435-4c49-82a0-27e22a7e9dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284125034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.4284125034
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.3963565760
Short name T544
Test name
Test status
Simulation time 25694417 ps
CPU time 1.28 seconds
Started Jul 28 05:38:15 PM PDT 24
Finished Jul 28 05:38:17 PM PDT 24
Peak memory 218768 kb
Host smart-19d9cc3c-adec-4080-b649-f7fe627b30f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963565760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.3963565760
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.1688364293
Short name T186
Test name
Test status
Simulation time 46919269 ps
CPU time 1.01 seconds
Started Jul 28 05:38:16 PM PDT 24
Finished Jul 28 05:38:17 PM PDT 24
Peak memory 219668 kb
Host smart-a332d414-7fb2-4a27-ab1a-3076313f43be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688364293 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1688364293
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1525269174
Short name T845
Test name
Test status
Simulation time 200501124 ps
CPU time 2.79 seconds
Started Jul 28 05:38:16 PM PDT 24
Finished Jul 28 05:38:19 PM PDT 24
Peak memory 219356 kb
Host smart-98b0b4b0-5270-4ed3-8aa4-dc82c7bb5956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525269174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1525269174
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.770423455
Short name T976
Test name
Test status
Simulation time 92566695 ps
CPU time 1.25 seconds
Started Jul 28 05:38:17 PM PDT 24
Finished Jul 28 05:38:19 PM PDT 24
Peak memory 220516 kb
Host smart-8f67b137-25be-4f72-b1db-33b3819b5110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770423455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.770423455
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3223697837
Short name T174
Test name
Test status
Simulation time 33600656 ps
CPU time 1.12 seconds
Started Jul 28 05:38:17 PM PDT 24
Finished Jul 28 05:38:18 PM PDT 24
Peak memory 219440 kb
Host smart-ccd8ee7a-dd65-4ccc-82ee-ed7bf19c5b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223697837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3223697837
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3946632986
Short name T969
Test name
Test status
Simulation time 74906222 ps
CPU time 1.19 seconds
Started Jul 28 05:38:18 PM PDT 24
Finished Jul 28 05:38:20 PM PDT 24
Peak memory 219648 kb
Host smart-b46d263b-a69b-4222-a08f-582c5fad5da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946632986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3946632986
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.1269337583
Short name T427
Test name
Test status
Simulation time 46256525 ps
CPU time 1.32 seconds
Started Jul 28 05:38:17 PM PDT 24
Finished Jul 28 05:38:18 PM PDT 24
Peak memory 219332 kb
Host smart-2521abfb-4844-4282-84f5-2892ad6d0eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269337583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.1269337583
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3077905491
Short name T753
Test name
Test status
Simulation time 42019802 ps
CPU time 0.87 seconds
Started Jul 28 05:38:16 PM PDT 24
Finished Jul 28 05:38:17 PM PDT 24
Peak memory 218264 kb
Host smart-63cc1a68-83eb-48d4-92d6-8bdb15ac402f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077905491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3077905491
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/86.edn_err.1960763971
Short name T557
Test name
Test status
Simulation time 18105595 ps
CPU time 1.08 seconds
Started Jul 28 05:38:17 PM PDT 24
Finished Jul 28 05:38:18 PM PDT 24
Peak memory 218220 kb
Host smart-137eb632-a932-4ff4-95b6-53fcc46f2f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960763971 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1960763971
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2156945834
Short name T10
Test name
Test status
Simulation time 126929553 ps
CPU time 1.1 seconds
Started Jul 28 05:38:18 PM PDT 24
Finished Jul 28 05:38:19 PM PDT 24
Peak memory 218480 kb
Host smart-65397ea7-7f3d-4e03-8b3c-6755d55fbae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156945834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2156945834
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.2919376690
Short name T274
Test name
Test status
Simulation time 33939654 ps
CPU time 1.08 seconds
Started Jul 28 05:38:13 PM PDT 24
Finished Jul 28 05:38:14 PM PDT 24
Peak memory 219684 kb
Host smart-4836f8b1-06ce-47ab-ad47-b1b8803d8535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919376690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.2919376690
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.3565848781
Short name T127
Test name
Test status
Simulation time 33096579 ps
CPU time 0.91 seconds
Started Jul 28 05:38:15 PM PDT 24
Finished Jul 28 05:38:16 PM PDT 24
Peak memory 218212 kb
Host smart-cf4c745e-e786-470d-8228-e85e948dc03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565848781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3565848781
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2042399684
Short name T636
Test name
Test status
Simulation time 58321173 ps
CPU time 1.3 seconds
Started Jul 28 05:38:18 PM PDT 24
Finished Jul 28 05:38:19 PM PDT 24
Peak memory 217564 kb
Host smart-bdb03109-c7f4-4428-b8bb-1df4da3c05bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042399684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2042399684
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.1152523451
Short name T513
Test name
Test status
Simulation time 74100529 ps
CPU time 1.18 seconds
Started Jul 28 05:38:15 PM PDT 24
Finished Jul 28 05:38:17 PM PDT 24
Peak memory 220304 kb
Host smart-a432edf3-063c-4c58-98f4-8324491e7981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152523451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1152523451
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.1909810164
Short name T140
Test name
Test status
Simulation time 28091636 ps
CPU time 1.35 seconds
Started Jul 28 05:38:19 PM PDT 24
Finished Jul 28 05:38:21 PM PDT 24
Peak memory 225560 kb
Host smart-fbaa9bc6-af8b-4904-820c-dc3241e59f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909810164 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1909810164
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1314530938
Short name T401
Test name
Test status
Simulation time 65391490 ps
CPU time 1.57 seconds
Started Jul 28 05:38:12 PM PDT 24
Finished Jul 28 05:38:14 PM PDT 24
Peak memory 218424 kb
Host smart-be8606a0-d80c-4397-90b8-efd444c12061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314530938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1314530938
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.1567187562
Short name T311
Test name
Test status
Simulation time 72065869 ps
CPU time 1.05 seconds
Started Jul 28 05:38:15 PM PDT 24
Finished Jul 28 05:38:16 PM PDT 24
Peak memory 219372 kb
Host smart-b5a0fdf7-9d3f-4e7d-b533-de0fce6ac2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567187562 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.1567187562
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.934683573
Short name T223
Test name
Test status
Simulation time 20189290 ps
CPU time 1.24 seconds
Started Jul 28 05:38:14 PM PDT 24
Finished Jul 28 05:38:15 PM PDT 24
Peak memory 223892 kb
Host smart-2afa36d3-908f-4894-a9c8-a108044c7966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934683573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.934683573
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.2881396204
Short name T236
Test name
Test status
Simulation time 52411288 ps
CPU time 1.28 seconds
Started Jul 28 05:36:48 PM PDT 24
Finished Jul 28 05:36:49 PM PDT 24
Peak memory 215516 kb
Host smart-10648996-7750-4700-95e5-bc648049589b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881396204 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2881396204
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1029555285
Short name T978
Test name
Test status
Simulation time 21708207 ps
CPU time 0.86 seconds
Started Jul 28 05:36:47 PM PDT 24
Finished Jul 28 05:36:48 PM PDT 24
Peak memory 206676 kb
Host smart-df64cd88-dd67-4cfb-a80c-5c80b8348d03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029555285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1029555285
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.269203991
Short name T467
Test name
Test status
Simulation time 16727664 ps
CPU time 0.88 seconds
Started Jul 28 05:36:46 PM PDT 24
Finished Jul 28 05:36:47 PM PDT 24
Peak memory 216060 kb
Host smart-411d248b-8651-4946-9525-990610f2eb0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269203991 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.269203991
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_err.1567447897
Short name T363
Test name
Test status
Simulation time 55999104 ps
CPU time 1.03 seconds
Started Jul 28 05:36:47 PM PDT 24
Finished Jul 28 05:36:49 PM PDT 24
Peak memory 218452 kb
Host smart-bb141c99-40f2-4b8f-9626-f9f707cf6be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567447897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1567447897
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3243496077
Short name T955
Test name
Test status
Simulation time 141008590 ps
CPU time 3.41 seconds
Started Jul 28 05:36:46 PM PDT 24
Finished Jul 28 05:36:49 PM PDT 24
Peak memory 220060 kb
Host smart-1fce4511-862f-450c-99a3-6c94e19d2b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243496077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3243496077
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2636041678
Short name T101
Test name
Test status
Simulation time 23645104 ps
CPU time 1.02 seconds
Started Jul 28 05:36:45 PM PDT 24
Finished Jul 28 05:36:46 PM PDT 24
Peak memory 215720 kb
Host smart-d6c239f4-eebd-4242-96a6-498f6c137c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636041678 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2636041678
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1397376059
Short name T797
Test name
Test status
Simulation time 134970229 ps
CPU time 0.97 seconds
Started Jul 28 05:36:43 PM PDT 24
Finished Jul 28 05:36:44 PM PDT 24
Peak memory 207040 kb
Host smart-786362d1-70ea-4ea1-8da6-35e2287e0254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397376059 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1397376059
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1255474342
Short name T908
Test name
Test status
Simulation time 26342331 ps
CPU time 0.91 seconds
Started Jul 28 05:36:47 PM PDT 24
Finished Jul 28 05:36:48 PM PDT 24
Peak memory 215280 kb
Host smart-cbe2447b-15c8-43c3-9787-1fc5bbef9675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255474342 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1255474342
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2629309490
Short name T558
Test name
Test status
Simulation time 75968169 ps
CPU time 1.39 seconds
Started Jul 28 05:36:45 PM PDT 24
Finished Jul 28 05:36:46 PM PDT 24
Peak memory 215276 kb
Host smart-3830df0c-3553-4413-bef8-cb2ad62c8e96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629309490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2629309490
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1211985952
Short name T505
Test name
Test status
Simulation time 68473303376 ps
CPU time 893.83 seconds
Started Jul 28 05:36:46 PM PDT 24
Finished Jul 28 05:51:40 PM PDT 24
Peak memory 220864 kb
Host smart-d363ed29-2692-40bd-bf37-754d88c0bd61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211985952 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1211985952
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.2893526453
Short name T213
Test name
Test status
Simulation time 47780371 ps
CPU time 1.13 seconds
Started Jul 28 05:38:22 PM PDT 24
Finished Jul 28 05:38:24 PM PDT 24
Peak memory 219640 kb
Host smart-ff098ad4-6a93-41fa-b82b-8167655a1f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893526453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.2893526453
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.762197940
Short name T190
Test name
Test status
Simulation time 18881590 ps
CPU time 1.1 seconds
Started Jul 28 05:38:23 PM PDT 24
Finished Jul 28 05:38:24 PM PDT 24
Peak memory 218428 kb
Host smart-519ca6a5-9403-40b6-ba69-5944e65151eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762197940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.762197940
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1769560014
Short name T684
Test name
Test status
Simulation time 18634674 ps
CPU time 1.08 seconds
Started Jul 28 05:38:15 PM PDT 24
Finished Jul 28 05:38:16 PM PDT 24
Peak memory 217180 kb
Host smart-e768205f-c44d-4880-8e80-a3727f59544e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769560014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1769560014
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.702761078
Short name T308
Test name
Test status
Simulation time 43915551 ps
CPU time 1.15 seconds
Started Jul 28 05:38:21 PM PDT 24
Finished Jul 28 05:38:23 PM PDT 24
Peak memory 218684 kb
Host smart-d8bf4a9e-ab70-435b-8275-17738e0a527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702761078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.702761078
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.4271555454
Short name T131
Test name
Test status
Simulation time 25804552 ps
CPU time 0.98 seconds
Started Jul 28 05:38:25 PM PDT 24
Finished Jul 28 05:38:26 PM PDT 24
Peak memory 223748 kb
Host smart-f5b3ef7e-76e7-4c79-8e3d-0afea7121a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271555454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.4271555454
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3765108056
Short name T553
Test name
Test status
Simulation time 95643977 ps
CPU time 1.18 seconds
Started Jul 28 05:38:20 PM PDT 24
Finished Jul 28 05:38:22 PM PDT 24
Peak memory 217252 kb
Host smart-ed84d1d1-b7df-4c8e-bc8e-91cce1efcba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765108056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3765108056
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.426273877
Short name T986
Test name
Test status
Simulation time 72652852 ps
CPU time 1.26 seconds
Started Jul 28 05:38:23 PM PDT 24
Finished Jul 28 05:38:24 PM PDT 24
Peak memory 215608 kb
Host smart-91553946-764b-426e-aea8-937c2415a9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426273877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.426273877
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.1131663130
Short name T981
Test name
Test status
Simulation time 28653662 ps
CPU time 0.94 seconds
Started Jul 28 05:38:25 PM PDT 24
Finished Jul 28 05:38:26 PM PDT 24
Peak memory 219496 kb
Host smart-be0e37e5-649c-4327-9cc8-687145e4eafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131663130 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1131663130
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.570277532
Short name T944
Test name
Test status
Simulation time 33246559 ps
CPU time 1.2 seconds
Started Jul 28 05:38:20 PM PDT 24
Finished Jul 28 05:38:21 PM PDT 24
Peak memory 217168 kb
Host smart-13e7da53-50c2-47ab-b6fc-5d4fe7de92a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570277532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.570277532
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2877924013
Short name T785
Test name
Test status
Simulation time 31356808 ps
CPU time 1.37 seconds
Started Jul 28 05:38:19 PM PDT 24
Finished Jul 28 05:38:20 PM PDT 24
Peak memory 220880 kb
Host smart-7f0c72ae-2e99-4889-98d9-1c6e2d4b5c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877924013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2877924013
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.1845743721
Short name T232
Test name
Test status
Simulation time 19769415 ps
CPU time 1.05 seconds
Started Jul 28 05:38:20 PM PDT 24
Finished Jul 28 05:38:21 PM PDT 24
Peak memory 219416 kb
Host smart-4f2c0486-ea24-4454-8e50-36011413cb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845743721 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1845743721
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3642041598
Short name T39
Test name
Test status
Simulation time 47096562 ps
CPU time 1.23 seconds
Started Jul 28 05:38:19 PM PDT 24
Finished Jul 28 05:38:20 PM PDT 24
Peak memory 217252 kb
Host smart-947fba8b-6af8-4ce6-9504-dc7477a35baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642041598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3642041598
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.3022037023
Short name T609
Test name
Test status
Simulation time 63635513 ps
CPU time 1.06 seconds
Started Jul 28 05:38:24 PM PDT 24
Finished Jul 28 05:38:25 PM PDT 24
Peak memory 218704 kb
Host smart-fd5f624d-f515-4d58-98e6-6a8f1e28b893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022037023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.3022037023
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1558345374
Short name T907
Test name
Test status
Simulation time 28517337 ps
CPU time 0.98 seconds
Started Jul 28 05:38:21 PM PDT 24
Finished Jul 28 05:38:22 PM PDT 24
Peak memory 223644 kb
Host smart-d6e839cd-8ef8-40a6-83c3-110257c17d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558345374 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1558345374
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.539587519
Short name T395
Test name
Test status
Simulation time 51831025 ps
CPU time 1.18 seconds
Started Jul 28 05:38:23 PM PDT 24
Finished Jul 28 05:38:24 PM PDT 24
Peak memory 217144 kb
Host smart-8919bb97-6a58-43fa-a0f1-76e612a7c16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539587519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.539587519
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.1853397443
Short name T217
Test name
Test status
Simulation time 52689882 ps
CPU time 1.2 seconds
Started Jul 28 05:38:18 PM PDT 24
Finished Jul 28 05:38:19 PM PDT 24
Peak memory 219644 kb
Host smart-827e7e8c-59ee-40de-8852-1824a9898ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853397443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.1853397443
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.2630928745
Short name T6
Test name
Test status
Simulation time 44050833 ps
CPU time 1.05 seconds
Started Jul 28 05:38:20 PM PDT 24
Finished Jul 28 05:38:21 PM PDT 24
Peak memory 218540 kb
Host smart-934a8f50-a8e9-484a-b4df-d8483bb9764a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630928745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2630928745
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/96.edn_alert.4148869778
Short name T982
Test name
Test status
Simulation time 26999711 ps
CPU time 1.27 seconds
Started Jul 28 05:38:22 PM PDT 24
Finished Jul 28 05:38:24 PM PDT 24
Peak memory 219616 kb
Host smart-21d7e21e-7881-47a4-9463-86dccabff873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148869778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.4148869778
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.432571172
Short name T128
Test name
Test status
Simulation time 18974090 ps
CPU time 1.16 seconds
Started Jul 28 05:38:21 PM PDT 24
Finished Jul 28 05:38:23 PM PDT 24
Peak memory 223932 kb
Host smart-715d0960-bb79-48a5-a750-38c83bdfc918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432571172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.432571172
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3694750799
Short name T916
Test name
Test status
Simulation time 48732804 ps
CPU time 1.57 seconds
Started Jul 28 05:38:22 PM PDT 24
Finished Jul 28 05:38:24 PM PDT 24
Peak memory 217152 kb
Host smart-926b4a9b-9627-4783-bd14-1136789e25c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694750799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3694750799
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.22538193
Short name T156
Test name
Test status
Simulation time 28464781 ps
CPU time 1.33 seconds
Started Jul 28 05:38:23 PM PDT 24
Finished Jul 28 05:38:24 PM PDT 24
Peak memory 220484 kb
Host smart-609f37d4-dccc-4f44-ac7a-cc9cab8a70fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22538193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.22538193
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.4227445347
Short name T142
Test name
Test status
Simulation time 22524070 ps
CPU time 1.24 seconds
Started Jul 28 05:38:20 PM PDT 24
Finished Jul 28 05:38:22 PM PDT 24
Peak memory 223896 kb
Host smart-5b87b172-2d10-4305-a31e-c81d5655ede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227445347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.4227445347
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2628501813
Short name T626
Test name
Test status
Simulation time 139684500 ps
CPU time 1.04 seconds
Started Jul 28 05:38:20 PM PDT 24
Finished Jul 28 05:38:21 PM PDT 24
Peak memory 217088 kb
Host smart-d0606e88-3fa7-4997-ac81-6465aa329ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628501813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2628501813
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2565777369
Short name T434
Test name
Test status
Simulation time 46887207 ps
CPU time 1.24 seconds
Started Jul 28 05:38:21 PM PDT 24
Finished Jul 28 05:38:22 PM PDT 24
Peak memory 219552 kb
Host smart-415bdbd4-8e9f-4c5e-9316-d4a343448b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565777369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2565777369
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1979387213
Short name T642
Test name
Test status
Simulation time 257759828 ps
CPU time 1.11 seconds
Started Jul 28 05:38:24 PM PDT 24
Finished Jul 28 05:38:25 PM PDT 24
Peak memory 219768 kb
Host smart-e5f2ebb3-096d-4f05-bbb4-80b219733c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979387213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1979387213
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2952445500
Short name T734
Test name
Test status
Simulation time 108808369 ps
CPU time 1.14 seconds
Started Jul 28 05:38:24 PM PDT 24
Finished Jul 28 05:38:25 PM PDT 24
Peak memory 217168 kb
Host smart-34e93b08-68d2-4927-9e86-c8f856f5ecfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952445500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2952445500
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.3783541974
Short name T560
Test name
Test status
Simulation time 91690993 ps
CPU time 1.27 seconds
Started Jul 28 05:38:21 PM PDT 24
Finished Jul 28 05:38:23 PM PDT 24
Peak memory 215588 kb
Host smart-2b2aec50-30bd-40ea-9aa8-d673734ddb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783541974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.3783541974
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2418717521
Short name T939
Test name
Test status
Simulation time 50996599 ps
CPU time 0.92 seconds
Started Jul 28 05:38:23 PM PDT 24
Finished Jul 28 05:38:24 PM PDT 24
Peak memory 219580 kb
Host smart-08bb6f34-d31c-499d-b7b6-2a9517a8ca11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418717521 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2418717521
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.4137714307
Short name T818
Test name
Test status
Simulation time 139739941 ps
CPU time 1.94 seconds
Started Jul 28 05:38:22 PM PDT 24
Finished Jul 28 05:38:24 PM PDT 24
Peak memory 215152 kb
Host smart-72f55d73-720f-4895-b320-cab270849d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137714307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.4137714307
Directory /workspace/99.edn_genbits/latest
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