Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

7216

1

T4

26

T5

11

T20

166

all_values[1]

7216

1

T4

26

T5

11

T20

166

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7479

1

T4

26

T5

14

T20

167

auto[1]

6953

1

T4

26

T5

8

T20

165

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5792

1

T4

17

T5

7

T20

149

auto[1]

8640

1

T4

35

T5

15

T20

183

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8587

1

T4

25

T5

10

T20

204

auto[1]

5845

1

T4

27

T5

12

T20

128

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	0	12	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

1491

1

T4

5

T5

3

T20

40

all_values[0]

auto[0]

auto[0]

auto[1]

730

1

T4

1

T20

10

T21

28

all_values[0]

auto[0]

auto[1]

auto[0]

1373

1

T4

6

T20

31

T71

1

all_values[0]

auto[0]

auto[1]

auto[1]

681

1

T4

2

T5

1

T20

17

all_values[0]

auto[1]

auto[0]

auto[1]

1569

1

T4

4

T5

4

T20

36

all_values[0]

auto[1]

auto[1]

auto[1]

1372

1

T4

8

T5

3

T20

32

all_values[1]

auto[0]

auto[0]

auto[0]

1524

1

T4

6

T5

3

T20

38

all_values[1]

auto[0]

auto[0]

auto[1]

696

1

T4

2

T5

1

T20

14

all_values[1]

auto[0]

auto[1]

auto[0]

1404

1

T5

1

T20

40

T71

2

all_values[1]

auto[0]

auto[1]

auto[1]

688

1

T4

3

T5

1

T20

14

all_values[1]

auto[1]

auto[0]

auto[1]

1469

1

T4

8

T5

3

T20

29

all_values[1]

auto[1]

auto[1]

auto[1]

1435

1

T4

7

T5

2

T20

31

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal