Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.37 98.25 93.25 90.85 87.21 95.50 96.83 91.70


Total test records in report: 1125
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T1012 /workspace/coverage/cover_reg_top/0.edn_intr_test.3757015742 Jul 29 07:11:40 PM PDT 24 Jul 29 07:11:41 PM PDT 24 24733378 ps
T1013 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1952820718 Jul 29 07:12:02 PM PDT 24 Jul 29 07:12:03 PM PDT 24 18956214 ps
T1014 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1477559443 Jul 29 07:11:56 PM PDT 24 Jul 29 07:11:58 PM PDT 24 13987599 ps
T251 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2980491893 Jul 29 07:11:39 PM PDT 24 Jul 29 07:11:40 PM PDT 24 25669922 ps
T274 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3405780902 Jul 29 07:11:55 PM PDT 24 Jul 29 07:11:56 PM PDT 24 221515085 ps
T1015 /workspace/coverage/cover_reg_top/38.edn_intr_test.1680206603 Jul 29 07:12:18 PM PDT 24 Jul 29 07:12:19 PM PDT 24 14634505 ps
T1016 /workspace/coverage/cover_reg_top/10.edn_intr_test.138441693 Jul 29 07:11:56 PM PDT 24 Jul 29 07:11:57 PM PDT 24 64305100 ps
T1017 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.841370737 Jul 29 07:12:06 PM PDT 24 Jul 29 07:12:08 PM PDT 24 102301688 ps
T1018 /workspace/coverage/cover_reg_top/11.edn_intr_test.3920035417 Jul 29 07:11:56 PM PDT 24 Jul 29 07:11:58 PM PDT 24 14463874 ps
T1019 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3538645450 Jul 29 07:11:42 PM PDT 24 Jul 29 07:11:44 PM PDT 24 34787199 ps
T1020 /workspace/coverage/cover_reg_top/33.edn_intr_test.218048806 Jul 29 07:12:12 PM PDT 24 Jul 29 07:12:13 PM PDT 24 44438023 ps
T1021 /workspace/coverage/cover_reg_top/21.edn_intr_test.3802386810 Jul 29 07:12:05 PM PDT 24 Jul 29 07:12:06 PM PDT 24 17516932 ps
T277 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3829983755 Jul 29 07:11:39 PM PDT 24 Jul 29 07:11:42 PM PDT 24 181965954 ps
T252 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1724885344 Jul 29 07:11:42 PM PDT 24 Jul 29 07:11:44 PM PDT 24 84278494 ps
T1022 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.873711520 Jul 29 07:11:40 PM PDT 24 Jul 29 07:11:43 PM PDT 24 184268946 ps
T1023 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3408058046 Jul 29 07:11:38 PM PDT 24 Jul 29 07:11:41 PM PDT 24 213929594 ps
T1024 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.955502398 Jul 29 07:11:58 PM PDT 24 Jul 29 07:12:01 PM PDT 24 92042486 ps
T1025 /workspace/coverage/cover_reg_top/34.edn_intr_test.4106377609 Jul 29 07:12:12 PM PDT 24 Jul 29 07:12:13 PM PDT 24 42452998 ps
T1026 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.442036434 Jul 29 07:11:54 PM PDT 24 Jul 29 07:11:55 PM PDT 24 23573619 ps
T1027 /workspace/coverage/cover_reg_top/35.edn_intr_test.2793843557 Jul 29 07:12:08 PM PDT 24 Jul 29 07:12:09 PM PDT 24 18522384 ps
T1028 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.190071072 Jul 29 07:11:57 PM PDT 24 Jul 29 07:11:58 PM PDT 24 74513528 ps
T1029 /workspace/coverage/cover_reg_top/20.edn_intr_test.9153754 Jul 29 07:12:09 PM PDT 24 Jul 29 07:12:10 PM PDT 24 18038174 ps
T253 /workspace/coverage/cover_reg_top/11.edn_csr_rw.855067416 Jul 29 07:11:57 PM PDT 24 Jul 29 07:11:58 PM PDT 24 21990875 ps
T1030 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3538245243 Jul 29 07:11:38 PM PDT 24 Jul 29 07:11:40 PM PDT 24 88422517 ps
T1031 /workspace/coverage/cover_reg_top/32.edn_intr_test.128198986 Jul 29 07:12:08 PM PDT 24 Jul 29 07:12:09 PM PDT 24 25848427 ps
T1032 /workspace/coverage/cover_reg_top/3.edn_intr_test.3599264529 Jul 29 07:11:40 PM PDT 24 Jul 29 07:11:42 PM PDT 24 20046777 ps
T254 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1035463001 Jul 29 07:11:40 PM PDT 24 Jul 29 07:11:41 PM PDT 24 18881605 ps
T1033 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3228024821 Jul 29 07:11:54 PM PDT 24 Jul 29 07:11:55 PM PDT 24 69833176 ps
T1034 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1943496303 Jul 29 07:11:35 PM PDT 24 Jul 29 07:11:36 PM PDT 24 15703003 ps
T1035 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1122676304 Jul 29 07:11:57 PM PDT 24 Jul 29 07:11:59 PM PDT 24 35751722 ps
T1036 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3644325370 Jul 29 07:12:07 PM PDT 24 Jul 29 07:12:08 PM PDT 24 48657700 ps
T1037 /workspace/coverage/cover_reg_top/45.edn_intr_test.2265742647 Jul 29 07:12:17 PM PDT 24 Jul 29 07:12:18 PM PDT 24 68488945 ps
T1038 /workspace/coverage/cover_reg_top/16.edn_intr_test.1523552650 Jul 29 07:12:07 PM PDT 24 Jul 29 07:12:08 PM PDT 24 23705093 ps
T1039 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2740155146 Jul 29 07:11:53 PM PDT 24 Jul 29 07:11:54 PM PDT 24 45555884 ps
T1040 /workspace/coverage/cover_reg_top/18.edn_tl_errors.4226745739 Jul 29 07:12:03 PM PDT 24 Jul 29 07:12:08 PM PDT 24 141794821 ps
T1041 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2728998557 Jul 29 07:11:56 PM PDT 24 Jul 29 07:11:59 PM PDT 24 103079020 ps
T1042 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3184990155 Jul 29 07:11:54 PM PDT 24 Jul 29 07:11:59 PM PDT 24 1098039552 ps
T1043 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1035547789 Jul 29 07:12:07 PM PDT 24 Jul 29 07:12:08 PM PDT 24 60998897 ps
T1044 /workspace/coverage/cover_reg_top/26.edn_intr_test.3634588148 Jul 29 07:12:07 PM PDT 24 Jul 29 07:12:08 PM PDT 24 41438675 ps
T1045 /workspace/coverage/cover_reg_top/42.edn_intr_test.2896371417 Jul 29 07:12:18 PM PDT 24 Jul 29 07:12:20 PM PDT 24 80495937 ps
T1046 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1158176544 Jul 29 07:11:53 PM PDT 24 Jul 29 07:11:55 PM PDT 24 72936762 ps
T1047 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1446498871 Jul 29 07:11:57 PM PDT 24 Jul 29 07:11:59 PM PDT 24 31689909 ps
T1048 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2973752579 Jul 29 07:11:53 PM PDT 24 Jul 29 07:11:54 PM PDT 24 13288993 ps
T1049 /workspace/coverage/cover_reg_top/6.edn_intr_test.352194196 Jul 29 07:11:53 PM PDT 24 Jul 29 07:11:54 PM PDT 24 72717746 ps
T1050 /workspace/coverage/cover_reg_top/44.edn_intr_test.791487784 Jul 29 07:12:18 PM PDT 24 Jul 29 07:12:19 PM PDT 24 15210608 ps
T1051 /workspace/coverage/cover_reg_top/5.edn_intr_test.2174097886 Jul 29 07:11:40 PM PDT 24 Jul 29 07:11:42 PM PDT 24 18299046 ps
T1052 /workspace/coverage/cover_reg_top/25.edn_intr_test.1865660094 Jul 29 07:12:07 PM PDT 24 Jul 29 07:12:08 PM PDT 24 41775984 ps
T278 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2064595251 Jul 29 07:11:56 PM PDT 24 Jul 29 07:11:58 PM PDT 24 57150871 ps
T1053 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.152623257 Jul 29 07:11:31 PM PDT 24 Jul 29 07:11:32 PM PDT 24 31420487 ps
T1054 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2534282152 Jul 29 07:11:54 PM PDT 24 Jul 29 07:11:56 PM PDT 24 392926564 ps
T1055 /workspace/coverage/cover_reg_top/4.edn_csr_rw.4195243116 Jul 29 07:11:42 PM PDT 24 Jul 29 07:11:43 PM PDT 24 37780550 ps
T275 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.4264334504 Jul 29 07:12:10 PM PDT 24 Jul 29 07:12:12 PM PDT 24 47446438 ps
T1056 /workspace/coverage/cover_reg_top/2.edn_tl_errors.509687002 Jul 29 07:11:37 PM PDT 24 Jul 29 07:11:40 PM PDT 24 43697357 ps
T1057 /workspace/coverage/cover_reg_top/43.edn_intr_test.1938510569 Jul 29 07:12:16 PM PDT 24 Jul 29 07:12:17 PM PDT 24 45053842 ps
T1058 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3479516691 Jul 29 07:12:10 PM PDT 24 Jul 29 07:12:14 PM PDT 24 722953335 ps
T1059 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1581919022 Jul 29 07:11:57 PM PDT 24 Jul 29 07:11:58 PM PDT 24 21161348 ps
T1060 /workspace/coverage/cover_reg_top/23.edn_intr_test.2537769314 Jul 29 07:12:06 PM PDT 24 Jul 29 07:12:07 PM PDT 24 137772756 ps
T1061 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2419380896 Jul 29 07:12:07 PM PDT 24 Jul 29 07:12:09 PM PDT 24 24085964 ps
T1062 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3142208001 Jul 29 07:11:37 PM PDT 24 Jul 29 07:11:39 PM PDT 24 36551339 ps
T1063 /workspace/coverage/cover_reg_top/15.edn_intr_test.1489579307 Jul 29 07:12:07 PM PDT 24 Jul 29 07:12:08 PM PDT 24 122386772 ps
T1064 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3582016339 Jul 29 07:11:54 PM PDT 24 Jul 29 07:11:55 PM PDT 24 38182472 ps
T1065 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3679123561 Jul 29 07:12:07 PM PDT 24 Jul 29 07:12:08 PM PDT 24 15450777 ps
T1066 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1556431855 Jul 29 07:11:42 PM PDT 24 Jul 29 07:11:43 PM PDT 24 19899586 ps
T1067 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1558047925 Jul 29 07:12:07 PM PDT 24 Jul 29 07:12:10 PM PDT 24 38468484 ps
T255 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2245018526 Jul 29 07:11:36 PM PDT 24 Jul 29 07:11:37 PM PDT 24 34827949 ps
T1068 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3371307746 Jul 29 07:11:37 PM PDT 24 Jul 29 07:11:39 PM PDT 24 279277953 ps
T1069 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.266909107 Jul 29 07:11:38 PM PDT 24 Jul 29 07:11:39 PM PDT 24 19209801 ps
T1070 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3241963583 Jul 29 07:11:42 PM PDT 24 Jul 29 07:11:44 PM PDT 24 52487623 ps
T1071 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1215405670 Jul 29 07:11:55 PM PDT 24 Jul 29 07:11:57 PM PDT 24 263249083 ps
T1072 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1304425507 Jul 29 07:11:42 PM PDT 24 Jul 29 07:11:43 PM PDT 24 111983258 ps
T1073 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3152125694 Jul 29 07:11:56 PM PDT 24 Jul 29 07:11:58 PM PDT 24 137079830 ps
T1074 /workspace/coverage/cover_reg_top/15.edn_tl_errors.4294229262 Jul 29 07:12:08 PM PDT 24 Jul 29 07:12:12 PM PDT 24 462276088 ps
T1075 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1553403327 Jul 29 07:12:07 PM PDT 24 Jul 29 07:12:08 PM PDT 24 22264847 ps
T1076 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3272395999 Jul 29 07:11:56 PM PDT 24 Jul 29 07:11:59 PM PDT 24 183970183 ps
T1077 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1413531668 Jul 29 07:12:08 PM PDT 24 Jul 29 07:12:09 PM PDT 24 32447077 ps
T276 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1815240865 Jul 29 07:11:57 PM PDT 24 Jul 29 07:12:00 PM PDT 24 124991300 ps
T1078 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1572843616 Jul 29 07:12:06 PM PDT 24 Jul 29 07:12:08 PM PDT 24 60522042 ps
T1079 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2106279815 Jul 29 07:11:42 PM PDT 24 Jul 29 07:11:45 PM PDT 24 128217833 ps
T1080 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1746703015 Jul 29 07:11:53 PM PDT 24 Jul 29 07:11:54 PM PDT 24 181997962 ps
T1081 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2251111379 Jul 29 07:11:57 PM PDT 24 Jul 29 07:11:58 PM PDT 24 57503882 ps
T1082 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1797726451 Jul 29 07:11:57 PM PDT 24 Jul 29 07:11:59 PM PDT 24 102708128 ps
T1083 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1911264138 Jul 29 07:11:56 PM PDT 24 Jul 29 07:11:59 PM PDT 24 310335299 ps
T1084 /workspace/coverage/cover_reg_top/19.edn_intr_test.1545414131 Jul 29 07:12:09 PM PDT 24 Jul 29 07:12:10 PM PDT 24 44326415 ps
T1085 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3218334429 Jul 29 07:11:54 PM PDT 24 Jul 29 07:11:58 PM PDT 24 435940562 ps
T1086 /workspace/coverage/cover_reg_top/29.edn_intr_test.1521209212 Jul 29 07:12:06 PM PDT 24 Jul 29 07:12:07 PM PDT 24 18069756 ps
T1087 /workspace/coverage/cover_reg_top/37.edn_intr_test.2893267890 Jul 29 07:12:14 PM PDT 24 Jul 29 07:12:15 PM PDT 24 21681290 ps
T1088 /workspace/coverage/cover_reg_top/19.edn_csr_rw.500704700 Jul 29 07:12:05 PM PDT 24 Jul 29 07:12:07 PM PDT 24 47661954 ps
T1089 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2710111937 Jul 29 07:11:42 PM PDT 24 Jul 29 07:11:46 PM PDT 24 91251993 ps
T1090 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.4182142413 Jul 29 07:11:36 PM PDT 24 Jul 29 07:11:38 PM PDT 24 62292943 ps
T1091 /workspace/coverage/cover_reg_top/14.edn_intr_test.191795715 Jul 29 07:12:03 PM PDT 24 Jul 29 07:12:04 PM PDT 24 50285691 ps
T1092 /workspace/coverage/cover_reg_top/17.edn_intr_test.1382369881 Jul 29 07:12:02 PM PDT 24 Jul 29 07:12:03 PM PDT 24 17441667 ps
T256 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2067353246 Jul 29 07:11:39 PM PDT 24 Jul 29 07:11:41 PM PDT 24 121535878 ps
T1093 /workspace/coverage/cover_reg_top/49.edn_intr_test.1092162111 Jul 29 07:12:12 PM PDT 24 Jul 29 07:12:13 PM PDT 24 29186651 ps
T1094 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1699075006 Jul 29 07:11:37 PM PDT 24 Jul 29 07:11:38 PM PDT 24 87260516 ps
T1095 /workspace/coverage/cover_reg_top/22.edn_intr_test.911332957 Jul 29 07:12:07 PM PDT 24 Jul 29 07:12:09 PM PDT 24 14077957 ps
T1096 /workspace/coverage/cover_reg_top/36.edn_intr_test.1011418790 Jul 29 07:12:12 PM PDT 24 Jul 29 07:12:13 PM PDT 24 13456219 ps
T1097 /workspace/coverage/cover_reg_top/2.edn_intr_test.1907490886 Jul 29 07:11:39 PM PDT 24 Jul 29 07:11:40 PM PDT 24 42991429 ps
T1098 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4178527697 Jul 29 07:11:38 PM PDT 24 Jul 29 07:11:40 PM PDT 24 191269688 ps
T1099 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2512703440 Jul 29 07:11:39 PM PDT 24 Jul 29 07:11:41 PM PDT 24 104137648 ps
T1100 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.777479730 Jul 29 07:11:38 PM PDT 24 Jul 29 07:11:40 PM PDT 24 50956521 ps
T1101 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3129757459 Jul 29 07:12:04 PM PDT 24 Jul 29 07:12:05 PM PDT 24 13408874 ps
T1102 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3288557114 Jul 29 07:12:02 PM PDT 24 Jul 29 07:12:04 PM PDT 24 186244144 ps
T1103 /workspace/coverage/cover_reg_top/12.edn_intr_test.856287168 Jul 29 07:11:56 PM PDT 24 Jul 29 07:11:57 PM PDT 24 22211750 ps
T1104 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2364189932 Jul 29 07:12:06 PM PDT 24 Jul 29 07:12:07 PM PDT 24 69220414 ps
T1105 /workspace/coverage/cover_reg_top/9.edn_intr_test.691672516 Jul 29 07:11:56 PM PDT 24 Jul 29 07:11:57 PM PDT 24 23987853 ps
T1106 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2225263080 Jul 29 07:11:39 PM PDT 24 Jul 29 07:11:40 PM PDT 24 64090961 ps
T1107 /workspace/coverage/cover_reg_top/13.edn_intr_test.2467500051 Jul 29 07:11:57 PM PDT 24 Jul 29 07:11:58 PM PDT 24 21828788 ps
T1108 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1700476878 Jul 29 07:12:01 PM PDT 24 Jul 29 07:12:02 PM PDT 24 32094429 ps
T1109 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3238617851 Jul 29 07:12:10 PM PDT 24 Jul 29 07:12:11 PM PDT 24 54066391 ps
T1110 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.88648265 Jul 29 07:11:38 PM PDT 24 Jul 29 07:11:40 PM PDT 24 65919978 ps
T1111 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.545565805 Jul 29 07:11:41 PM PDT 24 Jul 29 07:11:43 PM PDT 24 29072810 ps
T1112 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2426530235 Jul 29 07:11:39 PM PDT 24 Jul 29 07:11:41 PM PDT 24 89864120 ps
T1113 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1013239299 Jul 29 07:12:03 PM PDT 24 Jul 29 07:12:06 PM PDT 24 40826093 ps
T1114 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3136031786 Jul 29 07:11:57 PM PDT 24 Jul 29 07:11:58 PM PDT 24 12067596 ps
T1115 /workspace/coverage/cover_reg_top/31.edn_intr_test.4212713591 Jul 29 07:12:07 PM PDT 24 Jul 29 07:12:08 PM PDT 24 19314829 ps
T1116 /workspace/coverage/cover_reg_top/1.edn_intr_test.4157609148 Jul 29 07:11:39 PM PDT 24 Jul 29 07:11:40 PM PDT 24 17623320 ps
T1117 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3352924389 Jul 29 07:11:41 PM PDT 24 Jul 29 07:11:44 PM PDT 24 204385790 ps
T1118 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1977040915 Jul 29 07:11:42 PM PDT 24 Jul 29 07:11:46 PM PDT 24 346470345 ps
T1119 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2811878981 Jul 29 07:12:10 PM PDT 24 Jul 29 07:12:15 PM PDT 24 372026107 ps
T1120 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2293721753 Jul 29 07:11:56 PM PDT 24 Jul 29 07:11:58 PM PDT 24 28411104 ps
T1121 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4195219672 Jul 29 07:12:09 PM PDT 24 Jul 29 07:12:11 PM PDT 24 45793457 ps
T1122 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3950877294 Jul 29 07:12:05 PM PDT 24 Jul 29 07:12:06 PM PDT 24 31618900 ps
T1123 /workspace/coverage/cover_reg_top/24.edn_intr_test.901525066 Jul 29 07:12:06 PM PDT 24 Jul 29 07:12:07 PM PDT 24 11654361 ps
T1124 /workspace/coverage/cover_reg_top/13.edn_tl_errors.674948811 Jul 29 07:11:57 PM PDT 24 Jul 29 07:12:00 PM PDT 24 65938701 ps
T1125 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2336587592 Jul 29 07:11:41 PM PDT 24 Jul 29 07:11:43 PM PDT 24 36162247 ps

Test location /workspace/coverage/default/102.edn_genbits.3834695634
Short name T3
Test name
Test status
Simulation time 54900780 ps
CPU time 1.7 seconds
Started Jul 29 06:22:29 PM PDT 24
Finished Jul 29 06:22:31 PM PDT 24
Peak memory 218512 kb
Host smart-8a0f7c23-a6a6-4c5b-81df-45c3ac59e1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834695634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3834695634
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.1126401181
Short name T19
Test name
Test status
Simulation time 48578210 ps
CPU time 1.22 seconds
Started Jul 29 06:22:34 PM PDT 24
Finished Jul 29 06:22:35 PM PDT 24
Peak memory 219804 kb
Host smart-2e00bb83-12c9-4952-9e8f-323d7c2d9ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126401181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1126401181
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1717902889
Short name T20
Test name
Test status
Simulation time 66490788448 ps
CPU time 758.42 seconds
Started Jul 29 06:22:05 PM PDT 24
Finished Jul 29 06:34:44 PM PDT 24
Peak memory 223660 kb
Host smart-9fb6196c-db02-4878-bb00-310874d21410
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717902889 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1717902889
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2227744826
Short name T27
Test name
Test status
Simulation time 41984532 ps
CPU time 1.29 seconds
Started Jul 29 06:21:20 PM PDT 24
Finished Jul 29 06:21:21 PM PDT 24
Peak memory 217024 kb
Host smart-bb42d7a4-8d54-49b3-aa01-02c63a9866f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227744826 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2227744826
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/78.edn_err.838322743
Short name T14
Test name
Test status
Simulation time 19757411 ps
CPU time 1.12 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 224092 kb
Host smart-db2e8478-32a5-4661-99c4-38ccba7e105b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838322743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.838322743
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/241.edn_genbits.1680754763
Short name T40
Test name
Test status
Simulation time 65289707 ps
CPU time 2.08 seconds
Started Jul 29 06:23:24 PM PDT 24
Finished Jul 29 06:23:26 PM PDT 24
Peak memory 220088 kb
Host smart-a6b1db06-f588-40c3-a96e-49be59733c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680754763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1680754763
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_disable.1878949421
Short name T187
Test name
Test status
Simulation time 13511136 ps
CPU time 0.93 seconds
Started Jul 29 06:22:04 PM PDT 24
Finished Jul 29 06:22:05 PM PDT 24
Peak memory 216512 kb
Host smart-bdbfa73b-449a-42d5-a2a9-abd0caf0a86c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878949421 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1878949421
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/8.edn_intr.1775167002
Short name T48
Test name
Test status
Simulation time 46237487 ps
CPU time 0.99 seconds
Started Jul 29 06:21:14 PM PDT 24
Finished Jul 29 06:21:15 PM PDT 24
Peak memory 223824 kb
Host smart-88eebe8d-556e-48e5-9c26-8d9bce5fdcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775167002 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1775167002
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/6.edn_alert.473556778
Short name T24
Test name
Test status
Simulation time 66848513 ps
CPU time 1.17 seconds
Started Jul 29 06:21:02 PM PDT 24
Finished Jul 29 06:21:04 PM PDT 24
Peak memory 220860 kb
Host smart-58967bc6-4cdf-4466-b9dd-a5a167876de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473556778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.473556778
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/25.edn_intr.2341840139
Short name T43
Test name
Test status
Simulation time 23990595 ps
CPU time 1.01 seconds
Started Jul 29 06:21:56 PM PDT 24
Finished Jul 29 06:21:57 PM PDT 24
Peak memory 215896 kb
Host smart-3de945e1-7276-4f67-a5f3-e8cb3dd6bb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341840139 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2341840139
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/41.edn_alert.2349726513
Short name T69
Test name
Test status
Simulation time 40729402 ps
CPU time 1.11 seconds
Started Jul 29 06:21:56 PM PDT 24
Finished Jul 29 06:21:57 PM PDT 24
Peak memory 218760 kb
Host smart-880a886f-eb4d-408d-94de-487d72ba7759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349726513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2349726513
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/3.edn_regwen.2954300871
Short name T78
Test name
Test status
Simulation time 14497308 ps
CPU time 0.94 seconds
Started Jul 29 06:21:04 PM PDT 24
Finished Jul 29 06:21:05 PM PDT 24
Peak memory 207068 kb
Host smart-19e83e6e-e481-4b97-80ee-b0b3d0999079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954300871 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2954300871
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/195.edn_alert.2620071777
Short name T107
Test name
Test status
Simulation time 364205606 ps
CPU time 1.49 seconds
Started Jul 29 06:23:30 PM PDT 24
Finished Jul 29 06:23:31 PM PDT 24
Peak memory 221176 kb
Host smart-204f2745-3e1c-4553-b89f-b482e2051f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620071777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2620071777
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.4264334504
Short name T275
Test name
Test status
Simulation time 47446438 ps
CPU time 1.66 seconds
Started Jul 29 07:12:10 PM PDT 24
Finished Jul 29 07:12:12 PM PDT 24
Peak memory 206816 kb
Host smart-5b61bb23-5ca4-4062-90cd-7aeb92e364a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264334504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.4264334504
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1752060085
Short name T225
Test name
Test status
Simulation time 301701020403 ps
CPU time 1676.66 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:49:39 PM PDT 24
Peak memory 225112 kb
Host smart-dde2d770-1b2b-496e-9d5b-129d536c6500
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752060085 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1752060085
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1968485742
Short name T56
Test name
Test status
Simulation time 32351118 ps
CPU time 1.22 seconds
Started Jul 29 06:21:32 PM PDT 24
Finished Jul 29 06:21:33 PM PDT 24
Peak memory 216844 kb
Host smart-a5c62053-18de-41a2-b43f-b2384da9c139
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968485742 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1968485742
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/116.edn_genbits.2089966345
Short name T16
Test name
Test status
Simulation time 100973727 ps
CPU time 1.5 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 217468 kb
Host smart-0f960a0b-6b19-47f8-81c6-da344ea3caac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089966345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2089966345
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_disable.2929999083
Short name T134
Test name
Test status
Simulation time 18214817 ps
CPU time 0.88 seconds
Started Jul 29 06:21:37 PM PDT 24
Finished Jul 29 06:21:38 PM PDT 24
Peak memory 216240 kb
Host smart-faba8da2-870e-4ac4-846c-86ca77ac0d39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929999083 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2929999083
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable.3096174529
Short name T114
Test name
Test status
Simulation time 84376400 ps
CPU time 0.87 seconds
Started Jul 29 06:21:32 PM PDT 24
Finished Jul 29 06:21:33 PM PDT 24
Peak memory 216228 kb
Host smart-d6b1c396-5e44-42ff-a22a-b07f1f7cfb77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096174529 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3096174529
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1724885344
Short name T252
Test name
Test status
Simulation time 84278494 ps
CPU time 1.04 seconds
Started Jul 29 07:11:42 PM PDT 24
Finished Jul 29 07:11:44 PM PDT 24
Peak memory 206584 kb
Host smart-fc173e34-27f1-437a-a84c-9c0180b13b06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724885344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1724885344
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/default/14.edn_intr.3606560760
Short name T83
Test name
Test status
Simulation time 25503105 ps
CPU time 0.91 seconds
Started Jul 29 06:21:33 PM PDT 24
Finished Jul 29 06:21:34 PM PDT 24
Peak memory 215832 kb
Host smart-b4a2a167-28f8-4f40-91a5-0e9f61ceee9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606560760 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3606560760
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/141.edn_alert.1620641775
Short name T205
Test name
Test status
Simulation time 117753620 ps
CPU time 1.26 seconds
Started Jul 29 06:22:57 PM PDT 24
Finished Jul 29 06:22:58 PM PDT 24
Peak memory 220664 kb
Host smart-c6fa70f1-471b-460a-93f3-08e05a54c263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620641775 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1620641775
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/134.edn_alert.2392487922
Short name T75
Test name
Test status
Simulation time 75297712 ps
CPU time 1.32 seconds
Started Jul 29 06:22:41 PM PDT 24
Finished Jul 29 06:22:42 PM PDT 24
Peak memory 219100 kb
Host smart-4e4ba155-676d-4fef-9091-e983696dcee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392487922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2392487922
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/190.edn_alert.4011215371
Short name T98
Test name
Test status
Simulation time 94630547 ps
CPU time 1.14 seconds
Started Jul 29 06:23:02 PM PDT 24
Finished Jul 29 06:23:04 PM PDT 24
Peak memory 215648 kb
Host smart-6e99df91-75cb-4653-9cf5-95d2163124f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011215371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.4011215371
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3215799373
Short name T161
Test name
Test status
Simulation time 81158232 ps
CPU time 1.08 seconds
Started Jul 29 06:21:16 PM PDT 24
Finished Jul 29 06:21:18 PM PDT 24
Peak memory 219520 kb
Host smart-7092e62b-865a-42cc-b3be-dd9044739bca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215799373 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3215799373
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/107.edn_alert.3198497906
Short name T176
Test name
Test status
Simulation time 52950325 ps
CPU time 1.29 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:40 PM PDT 24
Peak memory 220504 kb
Host smart-f35aceb0-6e64-4448-9f05-98e0a8234481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198497906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3198497906
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/74.edn_genbits.2805077171
Short name T36
Test name
Test status
Simulation time 23604225 ps
CPU time 1.27 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 220044 kb
Host smart-ed71c5ad-75b8-48db-bfca-bbae84ec6cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805077171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2805077171
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3790135361
Short name T129
Test name
Test status
Simulation time 23817588 ps
CPU time 0.95 seconds
Started Jul 29 06:22:32 PM PDT 24
Finished Jul 29 06:22:33 PM PDT 24
Peak memory 219456 kb
Host smart-a7f2e30b-f999-4b8d-8de7-55f664927b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790135361 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3790135361
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/147.edn_alert.3491862527
Short name T284
Test name
Test status
Simulation time 23460034 ps
CPU time 1.26 seconds
Started Jul 29 06:23:08 PM PDT 24
Finished Jul 29 06:23:09 PM PDT 24
Peak memory 220600 kb
Host smart-86dd20c0-9c4d-40d3-b397-4048e4dafb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491862527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.3491862527
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/149.edn_alert.560911080
Short name T930
Test name
Test status
Simulation time 78694571 ps
CPU time 1.15 seconds
Started Jul 29 06:22:50 PM PDT 24
Finished Jul 29 06:22:51 PM PDT 24
Peak memory 218572 kb
Host smart-fcd0bb16-abd8-478d-9b6b-ed75516d50f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560911080 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.560911080
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/154.edn_alert.944019919
Short name T155
Test name
Test status
Simulation time 67560245 ps
CPU time 1.12 seconds
Started Jul 29 06:22:54 PM PDT 24
Finished Jul 29 06:22:55 PM PDT 24
Peak memory 218516 kb
Host smart-407ade0d-0e6a-4c65-88b0-d7da424235d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944019919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.944019919
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert.2724064474
Short name T244
Test name
Test status
Simulation time 46198929 ps
CPU time 1.11 seconds
Started Jul 29 06:21:54 PM PDT 24
Finished Jul 29 06:21:55 PM PDT 24
Peak memory 218488 kb
Host smart-7dfe15b7-6b6f-4a6b-835c-3ea3bd2836f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724064474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2724064474
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/95.edn_alert.936811951
Short name T183
Test name
Test status
Simulation time 39203105 ps
CPU time 1.01 seconds
Started Jul 29 06:22:48 PM PDT 24
Finished Jul 29 06:22:49 PM PDT 24
Peak memory 218356 kb
Host smart-f8e51721-3877-4237-ae90-7d97b6cf4825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936811951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.936811951
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/240.edn_genbits.3015754826
Short name T293
Test name
Test status
Simulation time 127913649 ps
CPU time 1.27 seconds
Started Jul 29 06:23:29 PM PDT 24
Finished Jul 29 06:23:30 PM PDT 24
Peak memory 218856 kb
Host smart-b7fd3e37-976b-4eec-81ca-c83c10258a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015754826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3015754826
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_disable.1383014785
Short name T856
Test name
Test status
Simulation time 23245471 ps
CPU time 0.9 seconds
Started Jul 29 06:21:36 PM PDT 24
Finished Jul 29 06:21:37 PM PDT 24
Peak memory 215620 kb
Host smart-fe60a4ae-aafb-49b5-9330-d4d2d1c25af5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383014785 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1383014785
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1469303991
Short name T91
Test name
Test status
Simulation time 31029810 ps
CPU time 1.15 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 216960 kb
Host smart-415f173a-b365-47b4-8718-5df347b8b104
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469303991 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1469303991
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_disable.1131818311
Short name T110
Test name
Test status
Simulation time 13031452 ps
CPU time 0.93 seconds
Started Jul 29 06:21:53 PM PDT 24
Finished Jul 29 06:21:54 PM PDT 24
Peak memory 215576 kb
Host smart-f34d7fc9-a2f2-417e-8ca5-467ce955328e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131818311 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1131818311
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable.1076713781
Short name T198
Test name
Test status
Simulation time 36039100 ps
CPU time 0.79 seconds
Started Jul 29 06:21:53 PM PDT 24
Finished Jul 29 06:21:54 PM PDT 24
Peak memory 216172 kb
Host smart-43217da2-206c-4cb5-a3d6-eea8d21f6c83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076713781 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1076713781
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.543749606
Short name T131
Test name
Test status
Simulation time 123229046 ps
CPU time 1.2 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 216976 kb
Host smart-3c6a20f3-c6b1-44b2-be23-f0f35e7961e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543749606 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.543749606
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/278.edn_genbits.3043660532
Short name T39
Test name
Test status
Simulation time 92152349 ps
CPU time 1.13 seconds
Started Jul 29 06:23:31 PM PDT 24
Finished Jul 29 06:23:32 PM PDT 24
Peak memory 217080 kb
Host smart-91527510-25c8-4dd4-a639-aec0ef71fb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043660532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3043660532
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert.4083595330
Short name T246
Test name
Test status
Simulation time 31467258 ps
CPU time 1.39 seconds
Started Jul 29 06:21:01 PM PDT 24
Finished Jul 29 06:21:03 PM PDT 24
Peak memory 215728 kb
Host smart-a88279bf-650f-470f-a72c-c7e3bd5e84c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083595330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.4083595330
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/101.edn_alert.4200302369
Short name T159
Test name
Test status
Simulation time 48160605 ps
CPU time 1.17 seconds
Started Jul 29 06:22:33 PM PDT 24
Finished Jul 29 06:22:35 PM PDT 24
Peak memory 219792 kb
Host smart-23ffd3d8-144e-4fda-b6eb-3e9344262465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200302369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.4200302369
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.2410014473
Short name T38
Test name
Test status
Simulation time 10826500 ps
CPU time 0.86 seconds
Started Jul 29 06:21:20 PM PDT 24
Finished Jul 29 06:21:21 PM PDT 24
Peak memory 216236 kb
Host smart-cde51cc6-26e8-4247-98e9-f755285a0499
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410014473 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2410014473
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/123.edn_alert.774911749
Short name T452
Test name
Test status
Simulation time 221187217 ps
CPU time 1.3 seconds
Started Jul 29 06:22:46 PM PDT 24
Finished Jul 29 06:22:47 PM PDT 24
Peak memory 220920 kb
Host smart-beee03d5-9947-4498-8650-a291f20fbda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774911749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.774911749
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/138.edn_alert.2277284683
Short name T979
Test name
Test status
Simulation time 29877006 ps
CPU time 1.18 seconds
Started Jul 29 06:22:59 PM PDT 24
Finished Jul 29 06:23:00 PM PDT 24
Peak memory 219532 kb
Host smart-7a68b525-4882-4fa1-9ebe-a37d3a0bb9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277284683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.2277284683
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2908955606
Short name T124
Test name
Test status
Simulation time 178848380 ps
CPU time 1.02 seconds
Started Jul 29 06:21:36 PM PDT 24
Finished Jul 29 06:21:37 PM PDT 24
Peak memory 216872 kb
Host smart-b7fdad7b-eb76-409e-955a-bdb54bbb57c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908955606 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2908955606
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2841710458
Short name T152
Test name
Test status
Simulation time 125061638 ps
CPU time 1.04 seconds
Started Jul 29 06:21:39 PM PDT 24
Finished Jul 29 06:21:40 PM PDT 24
Peak memory 216892 kb
Host smart-0a593875-9479-4c18-b270-28a4d1ca8181
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841710458 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2841710458
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.477389643
Short name T122
Test name
Test status
Simulation time 30708186 ps
CPU time 0.87 seconds
Started Jul 29 06:22:16 PM PDT 24
Finished Jul 29 06:22:17 PM PDT 24
Peak memory 218368 kb
Host smart-b961b080-851d-44c2-bfe5-dc5fbb389cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477389643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.477389643
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/68.edn_err.2890669411
Short name T202
Test name
Test status
Simulation time 32255469 ps
CPU time 0.98 seconds
Started Jul 29 06:22:23 PM PDT 24
Finished Jul 29 06:22:25 PM PDT 24
Peak memory 223832 kb
Host smart-4ee6a0ef-b27e-411a-86a3-82ffcbd8c78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890669411 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2890669411
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.1353285494
Short name T355
Test name
Test status
Simulation time 19226225 ps
CPU time 0.95 seconds
Started Jul 29 06:21:00 PM PDT 24
Finished Jul 29 06:21:02 PM PDT 24
Peak memory 206696 kb
Host smart-99c6fe1d-7347-4cc5-9034-c8ce6b4cfc08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353285494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1353285494
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/52.edn_genbits.1639317790
Short name T959
Test name
Test status
Simulation time 66093199 ps
CPU time 1.34 seconds
Started Jul 29 06:22:19 PM PDT 24
Finished Jul 29 06:22:21 PM PDT 24
Peak memory 220048 kb
Host smart-fe8a049e-de0e-426e-ace3-90c5a8325968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639317790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1639317790
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3028626789
Short name T57
Test name
Test status
Simulation time 139947976154 ps
CPU time 1767.77 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:51:11 PM PDT 24
Peak memory 226904 kb
Host smart-a3d00353-90c9-49f0-98ea-b851579fef99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028626789 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3028626789
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_genbits.1567535266
Short name T309
Test name
Test status
Simulation time 45337550 ps
CPU time 1.94 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:40 PM PDT 24
Peak memory 220092 kb
Host smart-1c524257-e4c3-41d8-aa60-f4957c3d1c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567535266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1567535266
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1100790596
Short name T81
Test name
Test status
Simulation time 22861635 ps
CPU time 0.97 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:21:42 PM PDT 24
Peak memory 215784 kb
Host smart-05210f34-571b-444e-8824-fd77a7d9f6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100790596 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1100790596
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/70.edn_err.2302371132
Short name T7
Test name
Test status
Simulation time 142568577 ps
CPU time 1.06 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:37 PM PDT 24
Peak memory 229648 kb
Host smart-f9b8e241-c497-4848-bedd-c0a7c4999f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302371132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2302371132
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/106.edn_genbits.3349625768
Short name T430
Test name
Test status
Simulation time 72110438 ps
CPU time 1.24 seconds
Started Jul 29 06:22:44 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 219940 kb
Host smart-e76dc274-7bb2-47e6-b368-7c068cc4fecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349625768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3349625768
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.855067416
Short name T253
Test name
Test status
Simulation time 21990875 ps
CPU time 0.88 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 206596 kb
Host smart-87947557-ab37-4f89-acc6-96ef591af54a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855067416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.855067416
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/default/16.edn_err.1019404043
Short name T92
Test name
Test status
Simulation time 33671560 ps
CPU time 0.9 seconds
Started Jul 29 06:21:32 PM PDT 24
Finished Jul 29 06:21:33 PM PDT 24
Peak memory 218352 kb
Host smart-263a123b-0b98-4cd8-9943-7df82ff5e008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019404043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1019404043
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3838312313
Short name T219
Test name
Test status
Simulation time 272324594 ps
CPU time 1.72 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:11:59 PM PDT 24
Peak memory 206936 kb
Host smart-94ea0e0f-d6a1-41e5-b9df-7ce8d6a2ff3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838312313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3838312313
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/122.edn_genbits.4101490988
Short name T298
Test name
Test status
Simulation time 68149068 ps
CPU time 1.39 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 218680 kb
Host smart-67f70dcc-276a-4a44-9d80-df28c9461a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101490988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.4101490988
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.2004927439
Short name T897
Test name
Test status
Simulation time 76468133 ps
CPU time 1.21 seconds
Started Jul 29 06:22:34 PM PDT 24
Finished Jul 29 06:22:35 PM PDT 24
Peak memory 218704 kb
Host smart-ae588b47-f7e9-4537-ab7d-995375c8f9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004927439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2004927439
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3309241607
Short name T291
Test name
Test status
Simulation time 58120980 ps
CPU time 0.97 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 217240 kb
Host smart-dd1fc03d-ae1e-4b4f-bebe-efa529ca64ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309241607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3309241607
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_genbits.105313794
Short name T297
Test name
Test status
Simulation time 49065665 ps
CPU time 1.83 seconds
Started Jul 29 06:21:40 PM PDT 24
Finished Jul 29 06:21:42 PM PDT 24
Peak memory 218292 kb
Host smart-11d7c19d-1b97-4bb6-8489-6ed190880ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105313794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.105313794
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.69985193
Short name T312
Test name
Test status
Simulation time 27298373 ps
CPU time 1.15 seconds
Started Jul 29 06:22:49 PM PDT 24
Finished Jul 29 06:22:50 PM PDT 24
Peak memory 218484 kb
Host smart-607bcc64-3885-426b-b9d1-9eda3934e012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69985193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.69985193
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.554813198
Short name T819
Test name
Test status
Simulation time 44413339 ps
CPU time 1.17 seconds
Started Jul 29 06:22:57 PM PDT 24
Finished Jul 29 06:23:03 PM PDT 24
Peak memory 219632 kb
Host smart-d7b82f90-ae6c-41a0-a8cf-6424e2f6e6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554813198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.554813198
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.4219210951
Short name T21
Test name
Test status
Simulation time 95464744472 ps
CPU time 675.85 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:32:58 PM PDT 24
Peak memory 221824 kb
Host smart-9f127419-509f-4bcd-b886-3b01df0c910a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219210951 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.4219210951
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/203.edn_genbits.881699166
Short name T292
Test name
Test status
Simulation time 74555263 ps
CPU time 1.24 seconds
Started Jul 29 06:23:08 PM PDT 24
Finished Jul 29 06:23:10 PM PDT 24
Peak memory 218516 kb
Host smart-c6715735-64bc-4e4d-91e4-e4702f0a1b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881699166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.881699166
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3399394902
Short name T854
Test name
Test status
Simulation time 83307606 ps
CPU time 1.19 seconds
Started Jul 29 06:23:07 PM PDT 24
Finished Jul 29 06:23:09 PM PDT 24
Peak memory 219840 kb
Host smart-d711a6ac-9112-4689-87e9-349e8f490cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399394902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3399394902
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.535501096
Short name T84
Test name
Test status
Simulation time 20969742 ps
CPU time 1.1 seconds
Started Jul 29 06:20:56 PM PDT 24
Finished Jul 29 06:20:57 PM PDT 24
Peak memory 215884 kb
Host smart-b10cd2b4-abe2-44d5-9045-201347debd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535501096 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.535501096
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/139.edn_alert.3567255258
Short name T949
Test name
Test status
Simulation time 54878287 ps
CPU time 1.35 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 215640 kb
Host smart-3a3a4071-088a-4676-98d0-083399cca997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567255258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.3567255258
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.88648265
Short name T1110
Test name
Test status
Simulation time 65919978 ps
CPU time 1.49 seconds
Started Jul 29 07:11:38 PM PDT 24
Finished Jul 29 07:11:40 PM PDT 24
Peak memory 206512 kb
Host smart-c9e679e9-a559-4583-a35b-e0fdc590005f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88648265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.88648265
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2710111937
Short name T1089
Test name
Test status
Simulation time 91251993 ps
CPU time 2.95 seconds
Started Jul 29 07:11:42 PM PDT 24
Finished Jul 29 07:11:46 PM PDT 24
Peak memory 206532 kb
Host smart-c8869e0f-3a7f-47b5-ab03-c303338e78e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710111937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2710111937
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1943496303
Short name T1034
Test name
Test status
Simulation time 15703003 ps
CPU time 0.91 seconds
Started Jul 29 07:11:35 PM PDT 24
Finished Jul 29 07:11:36 PM PDT 24
Peak memory 206516 kb
Host smart-aae5544b-209e-4172-af2b-e1ca165be3fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943496303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1943496303
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.4182142413
Short name T1090
Test name
Test status
Simulation time 62292943 ps
CPU time 1.14 seconds
Started Jul 29 07:11:36 PM PDT 24
Finished Jul 29 07:11:38 PM PDT 24
Peak memory 215052 kb
Host smart-dc796072-11de-43b4-b062-f065d1ad1b6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182142413 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.4182142413
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3641911077
Short name T1002
Test name
Test status
Simulation time 41687109 ps
CPU time 0.9 seconds
Started Jul 29 07:11:35 PM PDT 24
Finished Jul 29 07:11:36 PM PDT 24
Peak memory 206520 kb
Host smart-9d421907-2ba4-4c71-b512-0e440558786c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641911077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3641911077
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3757015742
Short name T1012
Test name
Test status
Simulation time 24733378 ps
CPU time 0.87 seconds
Started Jul 29 07:11:40 PM PDT 24
Finished Jul 29 07:11:41 PM PDT 24
Peak memory 206612 kb
Host smart-e02173c7-24dc-4360-b34a-c2d39775c954
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757015742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3757015742
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2426530235
Short name T1112
Test name
Test status
Simulation time 89864120 ps
CPU time 1.13 seconds
Started Jul 29 07:11:39 PM PDT 24
Finished Jul 29 07:11:41 PM PDT 24
Peak memory 206640 kb
Host smart-479c9ad8-94cc-4f9d-bf4c-d8f57ba06785
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426530235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2426530235
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3408058046
Short name T1023
Test name
Test status
Simulation time 213929594 ps
CPU time 3.19 seconds
Started Jul 29 07:11:38 PM PDT 24
Finished Jul 29 07:11:41 PM PDT 24
Peak memory 215032 kb
Host smart-c7f25908-7c80-4988-a22f-2250e00cca6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408058046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3408058046
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3829983755
Short name T277
Test name
Test status
Simulation time 181965954 ps
CPU time 2.65 seconds
Started Jul 29 07:11:39 PM PDT 24
Finished Jul 29 07:11:42 PM PDT 24
Peak memory 206672 kb
Host smart-f878b221-8c93-477c-ba8a-47e27b85d641
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829983755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3829983755
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2225263080
Short name T1106
Test name
Test status
Simulation time 64090961 ps
CPU time 1.2 seconds
Started Jul 29 07:11:39 PM PDT 24
Finished Jul 29 07:11:40 PM PDT 24
Peak memory 206568 kb
Host smart-055153c2-80f5-45bd-8bd0-3879cc35b228
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225263080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2225263080
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2067353246
Short name T256
Test name
Test status
Simulation time 121535878 ps
CPU time 2 seconds
Started Jul 29 07:11:39 PM PDT 24
Finished Jul 29 07:11:41 PM PDT 24
Peak memory 206648 kb
Host smart-c6119d5c-c35b-4ec0-a725-0c5c0ec669e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067353246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2067353246
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2512703440
Short name T1099
Test name
Test status
Simulation time 104137648 ps
CPU time 0.95 seconds
Started Jul 29 07:11:39 PM PDT 24
Finished Jul 29 07:11:41 PM PDT 24
Peak memory 206504 kb
Host smart-4d0b115e-eecc-4f9a-9395-7b233524e0ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512703440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2512703440
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1699075006
Short name T1094
Test name
Test status
Simulation time 87260516 ps
CPU time 1.24 seconds
Started Jul 29 07:11:37 PM PDT 24
Finished Jul 29 07:11:38 PM PDT 24
Peak memory 215008 kb
Host smart-b3fb8f96-4c32-4154-bebe-b5f7c65cd6c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699075006 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1699075006
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2245018526
Short name T255
Test name
Test status
Simulation time 34827949 ps
CPU time 0.86 seconds
Started Jul 29 07:11:36 PM PDT 24
Finished Jul 29 07:11:37 PM PDT 24
Peak memory 206524 kb
Host smart-cc48f53f-1b93-4bd7-968a-c1d3ff39658f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245018526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2245018526
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.4157609148
Short name T1116
Test name
Test status
Simulation time 17623320 ps
CPU time 0.86 seconds
Started Jul 29 07:11:39 PM PDT 24
Finished Jul 29 07:11:40 PM PDT 24
Peak memory 206420 kb
Host smart-578b1c87-ea5a-4399-a518-da206c9a4db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157609148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.4157609148
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4178527697
Short name T1098
Test name
Test status
Simulation time 191269688 ps
CPU time 1.43 seconds
Started Jul 29 07:11:38 PM PDT 24
Finished Jul 29 07:11:40 PM PDT 24
Peak memory 206756 kb
Host smart-3b78a81e-bde9-4ac0-a948-8a3abcdb1f8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178527697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.4178527697
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.4110912152
Short name T993
Test name
Test status
Simulation time 343787640 ps
CPU time 3.59 seconds
Started Jul 29 07:11:35 PM PDT 24
Finished Jul 29 07:11:39 PM PDT 24
Peak memory 214928 kb
Host smart-a2e648d6-1dba-431c-9435-2278ec67c10e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110912152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.4110912152
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.873711520
Short name T1022
Test name
Test status
Simulation time 184268946 ps
CPU time 2.32 seconds
Started Jul 29 07:11:40 PM PDT 24
Finished Jul 29 07:11:43 PM PDT 24
Peak memory 206724 kb
Host smart-42fc2513-4fac-48bd-a798-80c74ec4437b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873711520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.873711520
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.190071072
Short name T1028
Test name
Test status
Simulation time 74513528 ps
CPU time 1.21 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 217296 kb
Host smart-d1d251d5-a686-4eec-ba8c-3ad1fd3a9543
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190071072 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.190071072
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2740155146
Short name T1039
Test name
Test status
Simulation time 45555884 ps
CPU time 0.83 seconds
Started Jul 29 07:11:53 PM PDT 24
Finished Jul 29 07:11:54 PM PDT 24
Peak memory 206408 kb
Host smart-bda372eb-f85a-4759-b935-f0e050277a30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740155146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2740155146
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.138441693
Short name T1016
Test name
Test status
Simulation time 64305100 ps
CPU time 0.84 seconds
Started Jul 29 07:11:56 PM PDT 24
Finished Jul 29 07:11:57 PM PDT 24
Peak memory 206504 kb
Host smart-bd552be1-95e3-4d8e-aa01-8aa477c397fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138441693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.138441693
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1158176544
Short name T1046
Test name
Test status
Simulation time 72936762 ps
CPU time 1.14 seconds
Started Jul 29 07:11:53 PM PDT 24
Finished Jul 29 07:11:55 PM PDT 24
Peak memory 206668 kb
Host smart-72eb7525-58be-47da-a7f9-2338429b4f32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158176544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1158176544
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2534282152
Short name T1054
Test name
Test status
Simulation time 392926564 ps
CPU time 2.02 seconds
Started Jul 29 07:11:54 PM PDT 24
Finished Jul 29 07:11:56 PM PDT 24
Peak memory 215008 kb
Host smart-cf6a341f-dd23-4e48-8230-9798b1e73a79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534282152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2534282152
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1746703015
Short name T1080
Test name
Test status
Simulation time 181997962 ps
CPU time 1.28 seconds
Started Jul 29 07:11:53 PM PDT 24
Finished Jul 29 07:11:54 PM PDT 24
Peak memory 214912 kb
Host smart-18309d9a-db03-45a6-b35e-aca25a2d4713
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746703015 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1746703015
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3920035417
Short name T1018
Test name
Test status
Simulation time 14463874 ps
CPU time 0.93 seconds
Started Jul 29 07:11:56 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 206676 kb
Host smart-a5138958-0c81-4309-a4bb-5386579c8fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920035417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3920035417
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1122676304
Short name T1035
Test name
Test status
Simulation time 35751722 ps
CPU time 1.46 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:11:59 PM PDT 24
Peak memory 206740 kb
Host smart-9cd7d882-1c15-4688-a2e0-f004e96d67ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122676304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1122676304
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3184990155
Short name T1042
Test name
Test status
Simulation time 1098039552 ps
CPU time 4.23 seconds
Started Jul 29 07:11:54 PM PDT 24
Finished Jul 29 07:11:59 PM PDT 24
Peak memory 214952 kb
Host smart-f5433a78-a63b-4233-bbc6-0a8bf0cf977d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184990155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3184990155
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1815240865
Short name T276
Test name
Test status
Simulation time 124991300 ps
CPU time 3.14 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:12:00 PM PDT 24
Peak memory 214864 kb
Host smart-fdd87e6d-e865-4679-b56e-aa65cd69e8a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815240865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1815240865
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.442036434
Short name T1026
Test name
Test status
Simulation time 23573619 ps
CPU time 1.18 seconds
Started Jul 29 07:11:54 PM PDT 24
Finished Jul 29 07:11:55 PM PDT 24
Peak memory 214916 kb
Host smart-febd69d2-e218-44e4-89ff-63957e23682b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442036434 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.442036434
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1700476878
Short name T1108
Test name
Test status
Simulation time 32094429 ps
CPU time 0.8 seconds
Started Jul 29 07:12:01 PM PDT 24
Finished Jul 29 07:12:02 PM PDT 24
Peak memory 206540 kb
Host smart-88002ef4-8f45-4269-85e5-cb9063113eb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700476878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1700476878
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.856287168
Short name T1103
Test name
Test status
Simulation time 22211750 ps
CPU time 0.83 seconds
Started Jul 29 07:11:56 PM PDT 24
Finished Jul 29 07:11:57 PM PDT 24
Peak memory 206552 kb
Host smart-af581187-1e34-46c6-a37a-c1e2db8e866f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856287168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.856287168
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1581919022
Short name T1059
Test name
Test status
Simulation time 21161348 ps
CPU time 1.21 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 206796 kb
Host smart-dfb36a46-16fe-4421-ae6d-7ea7339c9973
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581919022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1581919022
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2728998557
Short name T1041
Test name
Test status
Simulation time 103079020 ps
CPU time 2.88 seconds
Started Jul 29 07:11:56 PM PDT 24
Finished Jul 29 07:11:59 PM PDT 24
Peak memory 215072 kb
Host smart-1f0542fd-64ee-4480-93d9-a112a0115319
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728998557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2728998557
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3405780902
Short name T274
Test name
Test status
Simulation time 221515085 ps
CPU time 1.48 seconds
Started Jul 29 07:11:55 PM PDT 24
Finished Jul 29 07:11:56 PM PDT 24
Peak memory 206892 kb
Host smart-53dd47a0-b0a1-414d-965e-c187f9c3db2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405780902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3405780902
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.96964313
Short name T1004
Test name
Test status
Simulation time 22426169 ps
CPU time 1.2 seconds
Started Jul 29 07:12:10 PM PDT 24
Finished Jul 29 07:12:12 PM PDT 24
Peak memory 223112 kb
Host smart-605e54de-7558-4044-ae49-ed3d0fca471c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96964313 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.96964313
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2763857033
Short name T250
Test name
Test status
Simulation time 44519113 ps
CPU time 0.83 seconds
Started Jul 29 07:11:56 PM PDT 24
Finished Jul 29 07:11:57 PM PDT 24
Peak memory 206540 kb
Host smart-698d6a52-ffe6-4976-b098-079a5de89ec1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763857033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2763857033
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2467500051
Short name T1107
Test name
Test status
Simulation time 21828788 ps
CPU time 0.86 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 206596 kb
Host smart-b8088b1c-cbe2-466d-83f1-d834eadc8b4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467500051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2467500051
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3078006779
Short name T264
Test name
Test status
Simulation time 42356683 ps
CPU time 0.99 seconds
Started Jul 29 07:12:01 PM PDT 24
Finished Jul 29 07:12:02 PM PDT 24
Peak memory 206680 kb
Host smart-b91b8a36-d92d-4d96-a2e5-cf85ceb57858
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078006779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3078006779
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.674948811
Short name T1124
Test name
Test status
Simulation time 65938701 ps
CPU time 2.56 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:12:00 PM PDT 24
Peak memory 215192 kb
Host smart-c61d1378-7d3c-41b9-8a21-a9c41a286c95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674948811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.674948811
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3172785309
Short name T273
Test name
Test status
Simulation time 303273119 ps
CPU time 2.42 seconds
Started Jul 29 07:12:01 PM PDT 24
Finished Jul 29 07:12:03 PM PDT 24
Peak memory 206712 kb
Host smart-3dbad7ee-e1b8-4839-a493-28c5b23e06cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172785309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3172785309
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1697042522
Short name T1001
Test name
Test status
Simulation time 280799585 ps
CPU time 1.5 seconds
Started Jul 29 07:12:05 PM PDT 24
Finished Jul 29 07:12:07 PM PDT 24
Peak memory 218800 kb
Host smart-e0ff7c2d-492d-42dd-ae11-07781b9d5467
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697042522 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1697042522
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1952820718
Short name T1013
Test name
Test status
Simulation time 18956214 ps
CPU time 0.94 seconds
Started Jul 29 07:12:02 PM PDT 24
Finished Jul 29 07:12:03 PM PDT 24
Peak memory 206540 kb
Host smart-658d9db6-e51e-46f5-9b70-aec1e5630f09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952820718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1952820718
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.191795715
Short name T1091
Test name
Test status
Simulation time 50285691 ps
CPU time 0.84 seconds
Started Jul 29 07:12:03 PM PDT 24
Finished Jul 29 07:12:04 PM PDT 24
Peak memory 206368 kb
Host smart-a3725ff6-22a7-422c-b4d8-3a24ae8a47ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191795715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.191795715
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1035547789
Short name T1043
Test name
Test status
Simulation time 60998897 ps
CPU time 1.1 seconds
Started Jul 29 07:12:07 PM PDT 24
Finished Jul 29 07:12:08 PM PDT 24
Peak memory 206644 kb
Host smart-5a2f0d70-401c-4f27-921e-a4cdea04d00d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035547789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1035547789
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1558047925
Short name T1067
Test name
Test status
Simulation time 38468484 ps
CPU time 2.55 seconds
Started Jul 29 07:12:07 PM PDT 24
Finished Jul 29 07:12:10 PM PDT 24
Peak memory 214992 kb
Host smart-339bfc75-3cd2-4418-ab67-71e29d9d8dcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558047925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1558047925
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.955502398
Short name T1024
Test name
Test status
Simulation time 92042486 ps
CPU time 2.67 seconds
Started Jul 29 07:11:58 PM PDT 24
Finished Jul 29 07:12:01 PM PDT 24
Peak memory 206752 kb
Host smart-8779e00d-2f3c-4e31-81cd-d2237b7dc438
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955502398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.955502398
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.841370737
Short name T1017
Test name
Test status
Simulation time 102301688 ps
CPU time 1.36 seconds
Started Jul 29 07:12:06 PM PDT 24
Finished Jul 29 07:12:08 PM PDT 24
Peak memory 214996 kb
Host smart-f4a3509a-4996-430a-94c8-97bcc099c32e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841370737 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.841370737
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1413531668
Short name T1077
Test name
Test status
Simulation time 32447077 ps
CPU time 0.95 seconds
Started Jul 29 07:12:08 PM PDT 24
Finished Jul 29 07:12:09 PM PDT 24
Peak memory 206576 kb
Host smart-2571ad0a-a33f-4cb3-beb4-f527159229d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413531668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1413531668
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1489579307
Short name T1063
Test name
Test status
Simulation time 122386772 ps
CPU time 0.85 seconds
Started Jul 29 07:12:07 PM PDT 24
Finished Jul 29 07:12:08 PM PDT 24
Peak memory 206340 kb
Host smart-52e444dc-dcc7-491f-b4cd-19a2e1983821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489579307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1489579307
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3950877294
Short name T1122
Test name
Test status
Simulation time 31618900 ps
CPU time 1.21 seconds
Started Jul 29 07:12:05 PM PDT 24
Finished Jul 29 07:12:06 PM PDT 24
Peak memory 206728 kb
Host smart-2697e240-a221-4937-9c99-219610f1c246
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950877294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3950877294
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.4294229262
Short name T1074
Test name
Test status
Simulation time 462276088 ps
CPU time 4.49 seconds
Started Jul 29 07:12:08 PM PDT 24
Finished Jul 29 07:12:12 PM PDT 24
Peak memory 214972 kb
Host smart-92e2a85d-6016-48e9-93f6-b4a051560269
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294229262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.4294229262
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3288557114
Short name T1102
Test name
Test status
Simulation time 186244144 ps
CPU time 1.68 seconds
Started Jul 29 07:12:02 PM PDT 24
Finished Jul 29 07:12:04 PM PDT 24
Peak memory 206876 kb
Host smart-478b87d4-e1fa-4011-9252-02d12fb4606f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288557114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3288557114
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.136830835
Short name T998
Test name
Test status
Simulation time 16555601 ps
CPU time 1.06 seconds
Started Jul 29 07:12:09 PM PDT 24
Finished Jul 29 07:12:10 PM PDT 24
Peak memory 206764 kb
Host smart-034277c9-baa5-4501-a7d3-b01ebd67bbbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136830835 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.136830835
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3129757459
Short name T1101
Test name
Test status
Simulation time 13408874 ps
CPU time 0.92 seconds
Started Jul 29 07:12:04 PM PDT 24
Finished Jul 29 07:12:05 PM PDT 24
Peak memory 206604 kb
Host smart-40f4e91d-72a8-4e39-bf61-05979a6ea8f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129757459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3129757459
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1523552650
Short name T1038
Test name
Test status
Simulation time 23705093 ps
CPU time 0.85 seconds
Started Jul 29 07:12:07 PM PDT 24
Finished Jul 29 07:12:08 PM PDT 24
Peak memory 206580 kb
Host smart-d49aad04-1b7a-4603-81f6-c1284e2d33e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523552650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1523552650
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4195219672
Short name T1121
Test name
Test status
Simulation time 45793457 ps
CPU time 1.4 seconds
Started Jul 29 07:12:09 PM PDT 24
Finished Jul 29 07:12:11 PM PDT 24
Peak memory 206676 kb
Host smart-4a7c5775-a7d3-473b-8a64-b84cf1dfa5e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195219672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.4195219672
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2811878981
Short name T1119
Test name
Test status
Simulation time 372026107 ps
CPU time 4.07 seconds
Started Jul 29 07:12:10 PM PDT 24
Finished Jul 29 07:12:15 PM PDT 24
Peak memory 214976 kb
Host smart-c09d6eb9-70e2-4496-91fa-f4904fae59ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811878981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2811878981
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3479516691
Short name T1058
Test name
Test status
Simulation time 722953335 ps
CPU time 3.95 seconds
Started Jul 29 07:12:10 PM PDT 24
Finished Jul 29 07:12:14 PM PDT 24
Peak memory 206640 kb
Host smart-f2dcd871-a1c0-4319-afd0-0d3438235d97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479516691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3479516691
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1553403327
Short name T1075
Test name
Test status
Simulation time 22264847 ps
CPU time 1.15 seconds
Started Jul 29 07:12:07 PM PDT 24
Finished Jul 29 07:12:08 PM PDT 24
Peak memory 216632 kb
Host smart-44cebc57-74e5-4b29-852d-75ceb9cd5b0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553403327 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1553403327
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3679123561
Short name T1065
Test name
Test status
Simulation time 15450777 ps
CPU time 0.9 seconds
Started Jul 29 07:12:07 PM PDT 24
Finished Jul 29 07:12:08 PM PDT 24
Peak memory 206576 kb
Host smart-1baf2327-8295-4f10-8a57-12a494e3eec4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679123561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3679123561
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1382369881
Short name T1092
Test name
Test status
Simulation time 17441667 ps
CPU time 0.9 seconds
Started Jul 29 07:12:02 PM PDT 24
Finished Jul 29 07:12:03 PM PDT 24
Peak memory 206560 kb
Host smart-264e530e-6823-4067-8fdc-485e5dec6754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382369881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1382369881
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1060701189
Short name T263
Test name
Test status
Simulation time 20604333 ps
CPU time 1.15 seconds
Started Jul 29 07:12:01 PM PDT 24
Finished Jul 29 07:12:02 PM PDT 24
Peak memory 206752 kb
Host smart-390c8db1-2aa4-464d-908e-0e01bd4ee220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060701189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1060701189
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1013239299
Short name T1113
Test name
Test status
Simulation time 40826093 ps
CPU time 2.78 seconds
Started Jul 29 07:12:03 PM PDT 24
Finished Jul 29 07:12:06 PM PDT 24
Peak memory 214952 kb
Host smart-a5c38eca-d5fa-4cdd-a862-238af1c9b05c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013239299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1013239299
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4068075511
Short name T1000
Test name
Test status
Simulation time 63893681 ps
CPU time 1.27 seconds
Started Jul 29 07:12:06 PM PDT 24
Finished Jul 29 07:12:07 PM PDT 24
Peak memory 214436 kb
Host smart-59b509f8-9356-4144-b543-0ff5118a7383
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068075511 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.4068075511
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3644325370
Short name T1036
Test name
Test status
Simulation time 48657700 ps
CPU time 0.91 seconds
Started Jul 29 07:12:07 PM PDT 24
Finished Jul 29 07:12:08 PM PDT 24
Peak memory 206596 kb
Host smart-b9b911d2-44b1-4b37-9109-19e2f83a60c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644325370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3644325370
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.743438606
Short name T1009
Test name
Test status
Simulation time 25955806 ps
CPU time 0.89 seconds
Started Jul 29 07:12:09 PM PDT 24
Finished Jul 29 07:12:10 PM PDT 24
Peak memory 206568 kb
Host smart-b02ab13d-e78e-4a3c-abe6-ad6737bdeffc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743438606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.743438606
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2419380896
Short name T1061
Test name
Test status
Simulation time 24085964 ps
CPU time 1.18 seconds
Started Jul 29 07:12:07 PM PDT 24
Finished Jul 29 07:12:09 PM PDT 24
Peak memory 206708 kb
Host smart-5691f11c-7535-4ac9-bbef-5d0966bbe890
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419380896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2419380896
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.4226745739
Short name T1040
Test name
Test status
Simulation time 141794821 ps
CPU time 4.67 seconds
Started Jul 29 07:12:03 PM PDT 24
Finished Jul 29 07:12:08 PM PDT 24
Peak memory 223156 kb
Host smart-1af463b7-0f44-4df3-940f-d36038f51ccb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226745739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.4226745739
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4031492041
Short name T217
Test name
Test status
Simulation time 224245970 ps
CPU time 1.79 seconds
Started Jul 29 07:12:10 PM PDT 24
Finished Jul 29 07:12:12 PM PDT 24
Peak memory 206712 kb
Host smart-70fcbeb2-72e8-44e7-850c-95f474f2812a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031492041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4031492041
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3238617851
Short name T1109
Test name
Test status
Simulation time 54066391 ps
CPU time 1.12 seconds
Started Jul 29 07:12:10 PM PDT 24
Finished Jul 29 07:12:11 PM PDT 24
Peak memory 214900 kb
Host smart-8554ed5a-d99f-4705-9f63-0fb2f9516278
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238617851 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3238617851
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.500704700
Short name T1088
Test name
Test status
Simulation time 47661954 ps
CPU time 0.83 seconds
Started Jul 29 07:12:05 PM PDT 24
Finished Jul 29 07:12:07 PM PDT 24
Peak memory 206412 kb
Host smart-281fbba4-bbf2-4fd4-b6fe-a0a4e659e9ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500704700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.500704700
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1545414131
Short name T1084
Test name
Test status
Simulation time 44326415 ps
CPU time 0.88 seconds
Started Jul 29 07:12:09 PM PDT 24
Finished Jul 29 07:12:10 PM PDT 24
Peak memory 206568 kb
Host smart-8f2f5e13-f7ca-4507-8a64-52cb67eff95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545414131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1545414131
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2364189932
Short name T1104
Test name
Test status
Simulation time 69220414 ps
CPU time 1.1 seconds
Started Jul 29 07:12:06 PM PDT 24
Finished Jul 29 07:12:07 PM PDT 24
Peak memory 206156 kb
Host smart-023a52de-4652-4525-a260-3799ff94e4ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364189932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2364189932
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1702028633
Short name T1007
Test name
Test status
Simulation time 334678863 ps
CPU time 4.57 seconds
Started Jul 29 07:12:09 PM PDT 24
Finished Jul 29 07:12:14 PM PDT 24
Peak memory 215016 kb
Host smart-8f9cb36d-bdb4-408d-b826-ebc4309cb144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702028633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1702028633
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1572843616
Short name T1078
Test name
Test status
Simulation time 60522042 ps
CPU time 1.82 seconds
Started Jul 29 07:12:06 PM PDT 24
Finished Jul 29 07:12:08 PM PDT 24
Peak memory 207296 kb
Host smart-32a18516-bcf1-4473-9b60-53ecedb812c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572843616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1572843616
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3073627691
Short name T994
Test name
Test status
Simulation time 260446290 ps
CPU time 2.96 seconds
Started Jul 29 07:11:40 PM PDT 24
Finished Jul 29 07:11:43 PM PDT 24
Peak memory 206592 kb
Host smart-c358fa83-6460-4005-85b2-75cfbeaa56d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073627691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3073627691
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.266909107
Short name T1069
Test name
Test status
Simulation time 19209801 ps
CPU time 0.98 seconds
Started Jul 29 07:11:38 PM PDT 24
Finished Jul 29 07:11:39 PM PDT 24
Peak memory 206524 kb
Host smart-58aaf731-e3b1-4e71-9dc5-f8f4397dafa8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266909107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.266909107
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3538245243
Short name T1030
Test name
Test status
Simulation time 88422517 ps
CPU time 1.63 seconds
Started Jul 29 07:11:38 PM PDT 24
Finished Jul 29 07:11:40 PM PDT 24
Peak memory 215004 kb
Host smart-2751b24c-f71b-4735-8dd6-5f8b45e6f6ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538245243 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3538245243
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2988325950
Short name T249
Test name
Test status
Simulation time 43910018 ps
CPU time 0.92 seconds
Started Jul 29 07:11:38 PM PDT 24
Finished Jul 29 07:11:40 PM PDT 24
Peak memory 206532 kb
Host smart-ed354bff-6ee0-4897-8ae8-66d9188e3b90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988325950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2988325950
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1907490886
Short name T1097
Test name
Test status
Simulation time 42991429 ps
CPU time 0.9 seconds
Started Jul 29 07:11:39 PM PDT 24
Finished Jul 29 07:11:40 PM PDT 24
Peak memory 206544 kb
Host smart-d80cc46b-6b2a-4823-bdbf-50b07ec20e31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907490886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1907490886
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2833200705
Short name T258
Test name
Test status
Simulation time 30026994 ps
CPU time 1.05 seconds
Started Jul 29 07:11:36 PM PDT 24
Finished Jul 29 07:11:37 PM PDT 24
Peak memory 206748 kb
Host smart-e198f488-00e4-42a0-b158-bc30f552bf9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833200705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2833200705
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.509687002
Short name T1056
Test name
Test status
Simulation time 43697357 ps
CPU time 2.8 seconds
Started Jul 29 07:11:37 PM PDT 24
Finished Jul 29 07:11:40 PM PDT 24
Peak memory 214992 kb
Host smart-729d72ce-d38e-4bc1-b3e5-273b923ebaba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509687002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.509687002
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.777479730
Short name T1100
Test name
Test status
Simulation time 50956521 ps
CPU time 1.79 seconds
Started Jul 29 07:11:38 PM PDT 24
Finished Jul 29 07:11:40 PM PDT 24
Peak memory 206952 kb
Host smart-cdbdd041-3320-4160-bcbb-788e9a61629d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777479730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.777479730
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.9153754
Short name T1029
Test name
Test status
Simulation time 18038174 ps
CPU time 0.93 seconds
Started Jul 29 07:12:09 PM PDT 24
Finished Jul 29 07:12:10 PM PDT 24
Peak memory 206560 kb
Host smart-9143ef91-da3e-43b2-b59d-db35203ad405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9153754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.9153754
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3802386810
Short name T1021
Test name
Test status
Simulation time 17516932 ps
CPU time 0.94 seconds
Started Jul 29 07:12:05 PM PDT 24
Finished Jul 29 07:12:06 PM PDT 24
Peak memory 206616 kb
Host smart-fd88f8e5-6fb0-43d7-a41f-727fb67f8d1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802386810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3802386810
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.911332957
Short name T1095
Test name
Test status
Simulation time 14077957 ps
CPU time 0.93 seconds
Started Jul 29 07:12:07 PM PDT 24
Finished Jul 29 07:12:09 PM PDT 24
Peak memory 206604 kb
Host smart-f439d880-dbb9-4a4d-a110-52cacb2520b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911332957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.911332957
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2537769314
Short name T1060
Test name
Test status
Simulation time 137772756 ps
CPU time 0.81 seconds
Started Jul 29 07:12:06 PM PDT 24
Finished Jul 29 07:12:07 PM PDT 24
Peak memory 206584 kb
Host smart-284c73cc-2716-449e-b194-781867c373c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537769314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2537769314
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.901525066
Short name T1123
Test name
Test status
Simulation time 11654361 ps
CPU time 0.82 seconds
Started Jul 29 07:12:06 PM PDT 24
Finished Jul 29 07:12:07 PM PDT 24
Peak memory 206544 kb
Host smart-59f69da0-5bc4-4885-9ac6-5e585ff33725
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901525066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.901525066
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1865660094
Short name T1052
Test name
Test status
Simulation time 41775984 ps
CPU time 0.83 seconds
Started Jul 29 07:12:07 PM PDT 24
Finished Jul 29 07:12:08 PM PDT 24
Peak memory 206416 kb
Host smart-87eaae66-0daa-42f2-a4f3-cd6542c0bd48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865660094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1865660094
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3634588148
Short name T1044
Test name
Test status
Simulation time 41438675 ps
CPU time 0.88 seconds
Started Jul 29 07:12:07 PM PDT 24
Finished Jul 29 07:12:08 PM PDT 24
Peak memory 206584 kb
Host smart-b47033a1-7245-49a4-84c4-0ed696391acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634588148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3634588148
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1416100727
Short name T996
Test name
Test status
Simulation time 21642384 ps
CPU time 0.91 seconds
Started Jul 29 07:12:08 PM PDT 24
Finished Jul 29 07:12:09 PM PDT 24
Peak memory 206584 kb
Host smart-574f4bf3-e71f-442c-97d6-e9b3030d4a55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416100727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1416100727
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2035232271
Short name T991
Test name
Test status
Simulation time 12816162 ps
CPU time 0.86 seconds
Started Jul 29 07:12:05 PM PDT 24
Finished Jul 29 07:12:06 PM PDT 24
Peak memory 206616 kb
Host smart-27a46216-084b-4378-a8d1-d9a7bb05390e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035232271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2035232271
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1521209212
Short name T1086
Test name
Test status
Simulation time 18069756 ps
CPU time 0.78 seconds
Started Jul 29 07:12:06 PM PDT 24
Finished Jul 29 07:12:07 PM PDT 24
Peak memory 206412 kb
Host smart-187e0a21-ecfc-4eae-93f0-6a1ca5c1d7b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521209212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1521209212
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1797069166
Short name T248
Test name
Test status
Simulation time 102552630 ps
CPU time 1.28 seconds
Started Jul 29 07:11:40 PM PDT 24
Finished Jul 29 07:11:42 PM PDT 24
Peak memory 206664 kb
Host smart-4fdf51f8-0d4d-43c6-b866-83bae0116b1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797069166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1797069166
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3142208001
Short name T1062
Test name
Test status
Simulation time 36551339 ps
CPU time 2.04 seconds
Started Jul 29 07:11:37 PM PDT 24
Finished Jul 29 07:11:39 PM PDT 24
Peak memory 206680 kb
Host smart-a8c99d78-1c2c-419a-b323-6af95d933976
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142208001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3142208001
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2980491893
Short name T251
Test name
Test status
Simulation time 25669922 ps
CPU time 0.89 seconds
Started Jul 29 07:11:39 PM PDT 24
Finished Jul 29 07:11:40 PM PDT 24
Peak memory 206588 kb
Host smart-1b6a5e87-a8e3-418f-b579-5f6a0a8ee5b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980491893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2980491893
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.152623257
Short name T1053
Test name
Test status
Simulation time 31420487 ps
CPU time 1.52 seconds
Started Jul 29 07:11:31 PM PDT 24
Finished Jul 29 07:11:32 PM PDT 24
Peak memory 215072 kb
Host smart-56f6ff66-b23d-45c1-bbb3-1f236420cdc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152623257 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.152623257
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1304425507
Short name T1072
Test name
Test status
Simulation time 111983258 ps
CPU time 0.86 seconds
Started Jul 29 07:11:42 PM PDT 24
Finished Jul 29 07:11:43 PM PDT 24
Peak memory 206580 kb
Host smart-41b908bf-cda0-4473-be1e-47431a1ec45b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304425507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1304425507
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3599264529
Short name T1032
Test name
Test status
Simulation time 20046777 ps
CPU time 0.81 seconds
Started Jul 29 07:11:40 PM PDT 24
Finished Jul 29 07:11:42 PM PDT 24
Peak memory 206404 kb
Host smart-d95f00d1-9c0b-44e8-98fc-64515b0a530c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599264529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3599264529
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1556431855
Short name T1066
Test name
Test status
Simulation time 19899586 ps
CPU time 1.02 seconds
Started Jul 29 07:11:42 PM PDT 24
Finished Jul 29 07:11:43 PM PDT 24
Peak memory 206788 kb
Host smart-7ec469d9-fd08-432b-b0c8-a63051f1e001
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556431855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1556431855
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2533801607
Short name T1006
Test name
Test status
Simulation time 89868988 ps
CPU time 1.8 seconds
Started Jul 29 07:11:38 PM PDT 24
Finished Jul 29 07:11:41 PM PDT 24
Peak memory 218952 kb
Host smart-e8d55510-d24a-40b1-b6d1-8dfb7d1df595
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533801607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2533801607
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2151852298
Short name T218
Test name
Test status
Simulation time 43168896 ps
CPU time 1.56 seconds
Started Jul 29 07:11:39 PM PDT 24
Finished Jul 29 07:11:41 PM PDT 24
Peak memory 206716 kb
Host smart-04fa8757-34c8-44a6-bbf9-a5f627b08457
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151852298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2151852298
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2096078391
Short name T997
Test name
Test status
Simulation time 15307751 ps
CPU time 0.92 seconds
Started Jul 29 07:12:10 PM PDT 24
Finished Jul 29 07:12:11 PM PDT 24
Peak memory 206652 kb
Host smart-0a336562-8ad4-4958-a991-a8a48c4b515f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096078391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2096078391
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.4212713591
Short name T1115
Test name
Test status
Simulation time 19314829 ps
CPU time 0.86 seconds
Started Jul 29 07:12:07 PM PDT 24
Finished Jul 29 07:12:08 PM PDT 24
Peak memory 206612 kb
Host smart-8a544a7d-e3e0-457c-a42e-57d5e9f6f04a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212713591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.4212713591
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.128198986
Short name T1031
Test name
Test status
Simulation time 25848427 ps
CPU time 0.88 seconds
Started Jul 29 07:12:08 PM PDT 24
Finished Jul 29 07:12:09 PM PDT 24
Peak memory 206616 kb
Host smart-c8a5383a-e6cc-4d17-a938-30a80c1a6e49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128198986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.128198986
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.218048806
Short name T1020
Test name
Test status
Simulation time 44438023 ps
CPU time 0.84 seconds
Started Jul 29 07:12:12 PM PDT 24
Finished Jul 29 07:12:13 PM PDT 24
Peak memory 206540 kb
Host smart-d89faf15-7437-4bb8-b1af-adcd7640bbe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218048806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.218048806
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.4106377609
Short name T1025
Test name
Test status
Simulation time 42452998 ps
CPU time 0.85 seconds
Started Jul 29 07:12:12 PM PDT 24
Finished Jul 29 07:12:13 PM PDT 24
Peak memory 206540 kb
Host smart-6f4e4b3d-c8a6-43b3-af98-de3d2b96f0dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106377609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.4106377609
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2793843557
Short name T1027
Test name
Test status
Simulation time 18522384 ps
CPU time 0.76 seconds
Started Jul 29 07:12:08 PM PDT 24
Finished Jul 29 07:12:09 PM PDT 24
Peak memory 206388 kb
Host smart-a0422d21-d6c1-4afe-8aee-7abc109cd861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793843557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2793843557
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1011418790
Short name T1096
Test name
Test status
Simulation time 13456219 ps
CPU time 0.93 seconds
Started Jul 29 07:12:12 PM PDT 24
Finished Jul 29 07:12:13 PM PDT 24
Peak memory 206776 kb
Host smart-b2e04dbc-2034-4124-9c10-a22a38f7ea22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011418790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1011418790
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2893267890
Short name T1087
Test name
Test status
Simulation time 21681290 ps
CPU time 0.88 seconds
Started Jul 29 07:12:14 PM PDT 24
Finished Jul 29 07:12:15 PM PDT 24
Peak memory 206544 kb
Host smart-3008350d-3d83-422f-9410-02b4f0e3278f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893267890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2893267890
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1680206603
Short name T1015
Test name
Test status
Simulation time 14634505 ps
CPU time 0.89 seconds
Started Jul 29 07:12:18 PM PDT 24
Finished Jul 29 07:12:19 PM PDT 24
Peak memory 206564 kb
Host smart-b75d5be9-1f07-4711-96bd-6bdb218b7342
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680206603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1680206603
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1015927136
Short name T990
Test name
Test status
Simulation time 13594249 ps
CPU time 0.87 seconds
Started Jul 29 07:12:19 PM PDT 24
Finished Jul 29 07:12:20 PM PDT 24
Peak memory 206564 kb
Host smart-064603a8-e08e-46d2-a91b-ee503e0dbfbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015927136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1015927136
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3538645450
Short name T1019
Test name
Test status
Simulation time 34787199 ps
CPU time 1.25 seconds
Started Jul 29 07:11:42 PM PDT 24
Finished Jul 29 07:11:44 PM PDT 24
Peak memory 206592 kb
Host smart-48933f6d-2588-41b2-9232-0cdd97d8567f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538645450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3538645450
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.988268245
Short name T999
Test name
Test status
Simulation time 523008314 ps
CPU time 6.91 seconds
Started Jul 29 07:11:39 PM PDT 24
Finished Jul 29 07:11:46 PM PDT 24
Peak memory 206664 kb
Host smart-ded339d9-4a52-416b-9af2-c1924dd457d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988268245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.988268245
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1035463001
Short name T254
Test name
Test status
Simulation time 18881605 ps
CPU time 0.78 seconds
Started Jul 29 07:11:40 PM PDT 24
Finished Jul 29 07:11:41 PM PDT 24
Peak memory 206364 kb
Host smart-f2a24353-8958-4a31-8094-22e798d62c7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035463001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1035463001
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3371307746
Short name T1068
Test name
Test status
Simulation time 279277953 ps
CPU time 1.46 seconds
Started Jul 29 07:11:37 PM PDT 24
Finished Jul 29 07:11:39 PM PDT 24
Peak memory 214972 kb
Host smart-a1a6cb74-87a9-49a6-932b-f6fde011581f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371307746 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3371307746
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.4195243116
Short name T1055
Test name
Test status
Simulation time 37780550 ps
CPU time 0.88 seconds
Started Jul 29 07:11:42 PM PDT 24
Finished Jul 29 07:11:43 PM PDT 24
Peak memory 206488 kb
Host smart-717059fd-f065-451a-a647-9e800550629b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195243116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.4195243116
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2137311466
Short name T989
Test name
Test status
Simulation time 15577068 ps
CPU time 0.93 seconds
Started Jul 29 07:11:40 PM PDT 24
Finished Jul 29 07:11:41 PM PDT 24
Peak memory 206608 kb
Host smart-be04eaad-e880-4739-b44e-e0e16b0d5870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137311466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2137311466
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1514439308
Short name T257
Test name
Test status
Simulation time 29087379 ps
CPU time 1.32 seconds
Started Jul 29 07:11:43 PM PDT 24
Finished Jul 29 07:11:44 PM PDT 24
Peak memory 206752 kb
Host smart-da9d1b77-b477-4fd5-b321-83c522a81291
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514439308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1514439308
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1977040915
Short name T1118
Test name
Test status
Simulation time 346470345 ps
CPU time 3.51 seconds
Started Jul 29 07:11:42 PM PDT 24
Finished Jul 29 07:11:46 PM PDT 24
Peak memory 215076 kb
Host smart-ba00b2d4-98d7-4d56-8100-02684b9c73e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977040915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1977040915
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3241963583
Short name T1070
Test name
Test status
Simulation time 52487623 ps
CPU time 1.53 seconds
Started Jul 29 07:11:42 PM PDT 24
Finished Jul 29 07:11:44 PM PDT 24
Peak memory 206888 kb
Host smart-0933c9ef-c4ab-4797-8b30-92e3873f07b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241963583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3241963583
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2644782694
Short name T1008
Test name
Test status
Simulation time 24302824 ps
CPU time 0.86 seconds
Started Jul 29 07:12:09 PM PDT 24
Finished Jul 29 07:12:10 PM PDT 24
Peak memory 206700 kb
Host smart-2202d41b-4a62-4677-b5e5-d826de550636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644782694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2644782694
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2847989255
Short name T995
Test name
Test status
Simulation time 15545484 ps
CPU time 0.93 seconds
Started Jul 29 07:12:10 PM PDT 24
Finished Jul 29 07:12:11 PM PDT 24
Peak memory 206692 kb
Host smart-57bae16e-f8d2-4989-8fc4-a96623c9142b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847989255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2847989255
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2896371417
Short name T1045
Test name
Test status
Simulation time 80495937 ps
CPU time 0.81 seconds
Started Jul 29 07:12:18 PM PDT 24
Finished Jul 29 07:12:20 PM PDT 24
Peak memory 206376 kb
Host smart-e8371a90-521c-476f-a580-7c15447a7519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896371417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2896371417
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1938510569
Short name T1057
Test name
Test status
Simulation time 45053842 ps
CPU time 0.86 seconds
Started Jul 29 07:12:16 PM PDT 24
Finished Jul 29 07:12:17 PM PDT 24
Peak memory 206604 kb
Host smart-5e12d992-e39c-41f9-a66b-17dd9f9b8069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938510569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1938510569
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.791487784
Short name T1050
Test name
Test status
Simulation time 15210608 ps
CPU time 0.9 seconds
Started Jul 29 07:12:18 PM PDT 24
Finished Jul 29 07:12:19 PM PDT 24
Peak memory 206564 kb
Host smart-4981ac7d-ad22-48dc-8b00-8f877bc7cc03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791487784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.791487784
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2265742647
Short name T1037
Test name
Test status
Simulation time 68488945 ps
CPU time 0.76 seconds
Started Jul 29 07:12:17 PM PDT 24
Finished Jul 29 07:12:18 PM PDT 24
Peak memory 206428 kb
Host smart-b8e6a706-3a10-4800-8698-39f686f20d55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265742647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2265742647
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2411220711
Short name T1010
Test name
Test status
Simulation time 39742260 ps
CPU time 0.84 seconds
Started Jul 29 07:12:18 PM PDT 24
Finished Jul 29 07:12:20 PM PDT 24
Peak memory 206376 kb
Host smart-477a9e58-0f12-4a18-858b-ca331dedfb92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411220711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2411220711
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2997134725
Short name T1003
Test name
Test status
Simulation time 28007386 ps
CPU time 0.88 seconds
Started Jul 29 07:12:18 PM PDT 24
Finished Jul 29 07:12:19 PM PDT 24
Peak memory 206564 kb
Host smart-cf73b999-71ea-4605-b68c-30e32f7e9abb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997134725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2997134725
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1285275409
Short name T1005
Test name
Test status
Simulation time 11620171 ps
CPU time 0.92 seconds
Started Jul 29 07:12:18 PM PDT 24
Finished Jul 29 07:12:19 PM PDT 24
Peak memory 206564 kb
Host smart-4936ca84-eb4d-457c-9c00-1e7f49f4304b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285275409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1285275409
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1092162111
Short name T1093
Test name
Test status
Simulation time 29186651 ps
CPU time 0.76 seconds
Started Jul 29 07:12:12 PM PDT 24
Finished Jul 29 07:12:13 PM PDT 24
Peak memory 206428 kb
Host smart-9b946901-2f6a-48e3-9ef1-233d1ff1d9f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092162111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1092162111
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.545565805
Short name T1111
Test name
Test status
Simulation time 29072810 ps
CPU time 1.43 seconds
Started Jul 29 07:11:41 PM PDT 24
Finished Jul 29 07:11:43 PM PDT 24
Peak memory 217520 kb
Host smart-1f74328a-d9b7-4536-9e9e-32bb2695ef2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545565805 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.545565805
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1469753648
Short name T992
Test name
Test status
Simulation time 16773415 ps
CPU time 0.89 seconds
Started Jul 29 07:11:41 PM PDT 24
Finished Jul 29 07:11:42 PM PDT 24
Peak memory 206764 kb
Host smart-9ea7ef49-ac66-48af-874b-853af7c2262b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469753648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1469753648
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2174097886
Short name T1051
Test name
Test status
Simulation time 18299046 ps
CPU time 0.95 seconds
Started Jul 29 07:11:40 PM PDT 24
Finished Jul 29 07:11:42 PM PDT 24
Peak memory 206604 kb
Host smart-4ff9abf0-141e-4526-ade4-38cf6252a87b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174097886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2174097886
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2336587592
Short name T1125
Test name
Test status
Simulation time 36162247 ps
CPU time 1.27 seconds
Started Jul 29 07:11:41 PM PDT 24
Finished Jul 29 07:11:43 PM PDT 24
Peak memory 206872 kb
Host smart-3dbc45cf-1700-42bd-b58e-5b81adbf5207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336587592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2336587592
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2106279815
Short name T1079
Test name
Test status
Simulation time 128217833 ps
CPU time 2.53 seconds
Started Jul 29 07:11:42 PM PDT 24
Finished Jul 29 07:11:45 PM PDT 24
Peak memory 215040 kb
Host smart-15cb71f4-5cc4-4040-8d77-6a43712076cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106279815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2106279815
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3352924389
Short name T1117
Test name
Test status
Simulation time 204385790 ps
CPU time 2.73 seconds
Started Jul 29 07:11:41 PM PDT 24
Finished Jul 29 07:11:44 PM PDT 24
Peak memory 206780 kb
Host smart-dff42c0d-6bc3-48d2-9243-a69146d5e7a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352924389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3352924389
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3228024821
Short name T1033
Test name
Test status
Simulation time 69833176 ps
CPU time 1.35 seconds
Started Jul 29 07:11:54 PM PDT 24
Finished Jul 29 07:11:55 PM PDT 24
Peak memory 215220 kb
Host smart-aa6548a2-0525-48f0-b081-f15d9dc6e277
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228024821 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3228024821
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2973752579
Short name T1048
Test name
Test status
Simulation time 13288993 ps
CPU time 0.87 seconds
Started Jul 29 07:11:53 PM PDT 24
Finished Jul 29 07:11:54 PM PDT 24
Peak memory 206496 kb
Host smart-f2b38eab-ae44-4daf-932e-f6122f66ece8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973752579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2973752579
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.352194196
Short name T1049
Test name
Test status
Simulation time 72717746 ps
CPU time 0.85 seconds
Started Jul 29 07:11:53 PM PDT 24
Finished Jul 29 07:11:54 PM PDT 24
Peak memory 206584 kb
Host smart-41876d82-4d8e-4776-8f09-5ce78a2649d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352194196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.352194196
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4005071273
Short name T262
Test name
Test status
Simulation time 50814299 ps
CPU time 0.95 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 206496 kb
Host smart-50072667-0a97-4e39-9480-fbe0980a95ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005071273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.4005071273
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3152125694
Short name T1073
Test name
Test status
Simulation time 137079830 ps
CPU time 2.24 seconds
Started Jul 29 07:11:56 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 214892 kb
Host smart-f74926c0-b6c0-4203-ae58-dc9a29f37d34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152125694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3152125694
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2064595251
Short name T278
Test name
Test status
Simulation time 57150871 ps
CPU time 1.83 seconds
Started Jul 29 07:11:56 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 206788 kb
Host smart-c360741b-f0ad-485a-81f8-653145448921
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064595251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2064595251
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2293721753
Short name T1120
Test name
Test status
Simulation time 28411104 ps
CPU time 1 seconds
Started Jul 29 07:11:56 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 206804 kb
Host smart-7b56fdd4-3853-4a99-9726-fe0aec4e174c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293721753 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2293721753
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3759588273
Short name T261
Test name
Test status
Simulation time 15620852 ps
CPU time 0.92 seconds
Started Jul 29 07:11:55 PM PDT 24
Finished Jul 29 07:11:56 PM PDT 24
Peak memory 206592 kb
Host smart-a257e745-5a13-4a4f-ab87-f16cd369e17f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759588273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3759588273
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3223189854
Short name T987
Test name
Test status
Simulation time 26321623 ps
CPU time 0.89 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 206628 kb
Host smart-2604d5ab-b490-4c50-8f06-47ae866c0d6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223189854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3223189854
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.777649597
Short name T259
Test name
Test status
Simulation time 41763189 ps
CPU time 1.17 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 206528 kb
Host smart-cd8e5065-4a00-46e3-9371-e5411b9bc2d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777649597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.777649597
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.771598067
Short name T1011
Test name
Test status
Simulation time 115199886 ps
CPU time 1.72 seconds
Started Jul 29 07:11:55 PM PDT 24
Finished Jul 29 07:11:57 PM PDT 24
Peak memory 223128 kb
Host smart-82d96c59-a0e6-48ba-9827-4b37e29eb827
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771598067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.771598067
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1911264138
Short name T1083
Test name
Test status
Simulation time 310335299 ps
CPU time 2.41 seconds
Started Jul 29 07:11:56 PM PDT 24
Finished Jul 29 07:11:59 PM PDT 24
Peak memory 214936 kb
Host smart-d986e367-2721-4ef8-9d8c-559c914f3754
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911264138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1911264138
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1477559443
Short name T1014
Test name
Test status
Simulation time 13987599 ps
CPU time 0.97 seconds
Started Jul 29 07:11:56 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 206732 kb
Host smart-61c8904c-b1fc-429f-a9cc-f7a87da9513d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477559443 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1477559443
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3582016339
Short name T1064
Test name
Test status
Simulation time 38182472 ps
CPU time 0.85 seconds
Started Jul 29 07:11:54 PM PDT 24
Finished Jul 29 07:11:55 PM PDT 24
Peak memory 206580 kb
Host smart-1f73ea35-a194-42fd-99d1-c1b8c558d94b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582016339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3582016339
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.4158733972
Short name T988
Test name
Test status
Simulation time 27625119 ps
CPU time 0.85 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 206628 kb
Host smart-1b4df607-9c31-404f-8b6e-536777167849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158733972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.4158733972
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1084585595
Short name T260
Test name
Test status
Simulation time 65746263 ps
CPU time 1.04 seconds
Started Jul 29 07:11:52 PM PDT 24
Finished Jul 29 07:11:53 PM PDT 24
Peak memory 206688 kb
Host smart-a8925a87-c619-4e00-98d8-d072b221a6d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084585595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1084585595
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3218334429
Short name T1085
Test name
Test status
Simulation time 435940562 ps
CPU time 3.7 seconds
Started Jul 29 07:11:54 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 215012 kb
Host smart-8e29a1c0-fa2a-4648-b9d8-e7eebeecfa75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218334429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3218334429
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3272395999
Short name T1076
Test name
Test status
Simulation time 183970183 ps
CPU time 2.32 seconds
Started Jul 29 07:11:56 PM PDT 24
Finished Jul 29 07:11:59 PM PDT 24
Peak memory 206924 kb
Host smart-cea56ed5-3531-462e-89b6-6c1d521302ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272395999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3272395999
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2251111379
Short name T1081
Test name
Test status
Simulation time 57503882 ps
CPU time 1.1 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 215052 kb
Host smart-429df893-68b0-44d6-89b9-8ba04656b732
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251111379 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2251111379
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3136031786
Short name T1114
Test name
Test status
Simulation time 12067596 ps
CPU time 0.92 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:11:58 PM PDT 24
Peak memory 206596 kb
Host smart-c0839403-eb4f-4f10-8001-a0ab453f46d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136031786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3136031786
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.691672516
Short name T1105
Test name
Test status
Simulation time 23987853 ps
CPU time 0.86 seconds
Started Jul 29 07:11:56 PM PDT 24
Finished Jul 29 07:11:57 PM PDT 24
Peak memory 206600 kb
Host smart-62b77e78-2c26-4b71-9e8b-020731d9c4e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691672516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.691672516
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1797726451
Short name T1082
Test name
Test status
Simulation time 102708128 ps
CPU time 1.33 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:11:59 PM PDT 24
Peak memory 206776 kb
Host smart-4b3296a0-80d7-4572-8397-f5814178779d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797726451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1797726451
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1446498871
Short name T1047
Test name
Test status
Simulation time 31689909 ps
CPU time 2.34 seconds
Started Jul 29 07:11:57 PM PDT 24
Finished Jul 29 07:11:59 PM PDT 24
Peak memory 215020 kb
Host smart-8f9e3b32-1c92-4c22-8f46-3b14f4a9fcc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446498871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1446498871
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1215405670
Short name T1071
Test name
Test status
Simulation time 263249083 ps
CPU time 1.47 seconds
Started Jul 29 07:11:55 PM PDT 24
Finished Jul 29 07:11:57 PM PDT 24
Peak memory 206792 kb
Host smart-2d7bb551-61cf-4422-be7d-8ecf2d03a6a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215405670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1215405670
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_disable.267865691
Short name T97
Test name
Test status
Simulation time 37061102 ps
CPU time 0.85 seconds
Started Jul 29 06:20:59 PM PDT 24
Finished Jul 29 06:21:00 PM PDT 24
Peak memory 216188 kb
Host smart-2a3a311a-3ccb-46f2-bed5-c2d7bda0dfc3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267865691 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.267865691
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3960606806
Short name T500
Test name
Test status
Simulation time 60595982 ps
CPU time 1.17 seconds
Started Jul 29 06:21:02 PM PDT 24
Finished Jul 29 06:21:03 PM PDT 24
Peak memory 216976 kb
Host smart-62776424-bc86-455a-abab-d118bfe17c5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960606806 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3960606806
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1549789189
Short name T943
Test name
Test status
Simulation time 23660619 ps
CPU time 1.03 seconds
Started Jul 29 06:20:59 PM PDT 24
Finished Jul 29 06:21:00 PM PDT 24
Peak memory 224012 kb
Host smart-d2501e61-3637-4bee-b340-d0026bfa2ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549789189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1549789189
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2492000897
Short name T671
Test name
Test status
Simulation time 89547922 ps
CPU time 2.75 seconds
Started Jul 29 06:20:56 PM PDT 24
Finished Jul 29 06:21:00 PM PDT 24
Peak memory 219888 kb
Host smart-62e5c30d-31c2-4803-aeb0-6d045bbf80f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492000897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2492000897
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.568264193
Short name T798
Test name
Test status
Simulation time 28212634 ps
CPU time 0.96 seconds
Started Jul 29 06:21:00 PM PDT 24
Finished Jul 29 06:21:01 PM PDT 24
Peak memory 215484 kb
Host smart-605267c7-8943-400d-9e0c-9fc2f3e41ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568264193 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.568264193
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1103023392
Short name T605
Test name
Test status
Simulation time 16635446 ps
CPU time 0.97 seconds
Started Jul 29 06:20:52 PM PDT 24
Finished Jul 29 06:20:54 PM PDT 24
Peak memory 207060 kb
Host smart-6ad38176-aa46-4a59-bcd2-8237a00e0e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103023392 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1103023392
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.598619763
Short name T839
Test name
Test status
Simulation time 33448573 ps
CPU time 0.9 seconds
Started Jul 29 06:20:59 PM PDT 24
Finished Jul 29 06:21:01 PM PDT 24
Peak memory 215308 kb
Host smart-9ae7ee08-84fa-4ebf-8778-7ccfdd009750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598619763 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.598619763
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.470204409
Short name T339
Test name
Test status
Simulation time 1168856470 ps
CPU time 4.78 seconds
Started Jul 29 06:20:56 PM PDT 24
Finished Jul 29 06:21:01 PM PDT 24
Peak memory 215300 kb
Host smart-6b3442a9-cbfa-4ad2-815d-986116a21c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470204409 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.470204409
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.62584236
Short name T830
Test name
Test status
Simulation time 69971161937 ps
CPU time 865.02 seconds
Started Jul 29 06:20:59 PM PDT 24
Finished Jul 29 06:35:25 PM PDT 24
Peak memory 223772 kb
Host smart-76aea16e-5470-480c-900d-4fb0f02f064a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62584236 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.62584236
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.148921365
Short name T841
Test name
Test status
Simulation time 89930781 ps
CPU time 1.19 seconds
Started Jul 29 06:20:52 PM PDT 24
Finished Jul 29 06:20:54 PM PDT 24
Peak memory 220084 kb
Host smart-b59e8251-1062-49b6-b224-18c2834a35ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148921365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.148921365
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.690752671
Short name T101
Test name
Test status
Simulation time 28986895 ps
CPU time 0.94 seconds
Started Jul 29 06:21:02 PM PDT 24
Finished Jul 29 06:21:03 PM PDT 24
Peak memory 206676 kb
Host smart-4d4be923-df44-4918-b856-9384250b31ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690752671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.690752671
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.480537702
Short name T629
Test name
Test status
Simulation time 16597195 ps
CPU time 0.88 seconds
Started Jul 29 06:21:01 PM PDT 24
Finished Jul 29 06:21:02 PM PDT 24
Peak memory 216188 kb
Host smart-0379f04f-621b-4090-832c-39f0cadadd35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480537702 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.480537702
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.748068787
Short name T491
Test name
Test status
Simulation time 50044788 ps
CPU time 1.05 seconds
Started Jul 29 06:20:58 PM PDT 24
Finished Jul 29 06:21:00 PM PDT 24
Peak memory 218460 kb
Host smart-b41e8151-2fb4-463b-95dc-0f054fe975fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748068787 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.748068787
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.85235802
Short name T929
Test name
Test status
Simulation time 47039124 ps
CPU time 0.96 seconds
Started Jul 29 06:20:52 PM PDT 24
Finished Jul 29 06:20:54 PM PDT 24
Peak memory 219772 kb
Host smart-3ecf2586-ef0b-49f3-9ab9-062c7c94e1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85235802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.85235802
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2550526722
Short name T894
Test name
Test status
Simulation time 132069371 ps
CPU time 1.15 seconds
Started Jul 29 06:21:07 PM PDT 24
Finished Jul 29 06:21:08 PM PDT 24
Peak memory 217432 kb
Host smart-ae441861-9e40-476e-97be-c1bc968c9cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550526722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2550526722
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.3854944545
Short name T915
Test name
Test status
Simulation time 18251682 ps
CPU time 1.01 seconds
Started Jul 29 06:21:02 PM PDT 24
Finished Jul 29 06:21:03 PM PDT 24
Peak memory 207148 kb
Host smart-e249e615-a82e-4f6c-8474-864dbd2b8ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854944545 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3854944545
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.1755220199
Short name T396
Test name
Test status
Simulation time 25569404 ps
CPU time 0.9 seconds
Started Jul 29 06:21:02 PM PDT 24
Finished Jul 29 06:21:03 PM PDT 24
Peak memory 215140 kb
Host smart-16df4aa6-ccf3-411b-8f45-8295a455ed5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755220199 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1755220199
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3481234028
Short name T864
Test name
Test status
Simulation time 556769628 ps
CPU time 3.27 seconds
Started Jul 29 06:20:55 PM PDT 24
Finished Jul 29 06:20:58 PM PDT 24
Peak memory 217256 kb
Host smart-9bdc896e-dad1-42e2-b789-575095c904d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481234028 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3481234028
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.741696989
Short name T911
Test name
Test status
Simulation time 30451360689 ps
CPU time 203.8 seconds
Started Jul 29 06:20:58 PM PDT 24
Finished Jul 29 06:24:22 PM PDT 24
Peak memory 217744 kb
Host smart-fe423b95-3ef4-454b-9cf0-1beac5583942
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741696989 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.741696989
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.778413875
Short name T754
Test name
Test status
Simulation time 24500753 ps
CPU time 1.13 seconds
Started Jul 29 06:21:18 PM PDT 24
Finished Jul 29 06:21:19 PM PDT 24
Peak memory 219572 kb
Host smart-0479826a-b6ec-4994-b308-e7d5e638b468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778413875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.778413875
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3342678428
Short name T383
Test name
Test status
Simulation time 165909978 ps
CPU time 0.94 seconds
Started Jul 29 06:21:31 PM PDT 24
Finished Jul 29 06:21:32 PM PDT 24
Peak memory 214852 kb
Host smart-43d42f90-534b-444f-87f9-728e0edc5621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342678428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3342678428
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.3066510745
Short name T806
Test name
Test status
Simulation time 24884734 ps
CPU time 0.83 seconds
Started Jul 29 06:21:18 PM PDT 24
Finished Jul 29 06:21:18 PM PDT 24
Peak memory 216220 kb
Host smart-e7c0b7f8-9eef-4da6-b34b-10785cf2dc48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066510745 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3066510745
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2576978055
Short name T531
Test name
Test status
Simulation time 115319740 ps
CPU time 1.13 seconds
Started Jul 29 06:21:17 PM PDT 24
Finished Jul 29 06:21:18 PM PDT 24
Peak memory 216844 kb
Host smart-a265692f-540f-472c-a3c5-dc87b03635fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576978055 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2576978055
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2927563909
Short name T779
Test name
Test status
Simulation time 58926813 ps
CPU time 0.86 seconds
Started Jul 29 06:21:34 PM PDT 24
Finished Jul 29 06:21:35 PM PDT 24
Peak memory 218224 kb
Host smart-48fd7ef6-31c9-4eac-9cf6-8ae461be8c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927563909 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2927563909
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1940054560
Short name T463
Test name
Test status
Simulation time 167826001 ps
CPU time 1.43 seconds
Started Jul 29 06:21:19 PM PDT 24
Finished Jul 29 06:21:21 PM PDT 24
Peak memory 220184 kb
Host smart-d9821304-5575-4769-ad42-6e5da9adf1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940054560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1940054560
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.4258465642
Short name T63
Test name
Test status
Simulation time 24358361 ps
CPU time 1.11 seconds
Started Jul 29 06:21:39 PM PDT 24
Finished Jul 29 06:21:40 PM PDT 24
Peak memory 215976 kb
Host smart-9a6cb1ce-fd5e-4e68-af1c-b706b17686d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258465642 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.4258465642
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.117065884
Short name T576
Test name
Test status
Simulation time 32302524 ps
CPU time 1 seconds
Started Jul 29 06:21:28 PM PDT 24
Finished Jul 29 06:21:29 PM PDT 24
Peak memory 215256 kb
Host smart-94b9f1f3-0e7e-4e52-8037-6750b1e9b00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117065884 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.117065884
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2066513022
Short name T363
Test name
Test status
Simulation time 17603843 ps
CPU time 0.97 seconds
Started Jul 29 06:21:15 PM PDT 24
Finished Jul 29 06:21:16 PM PDT 24
Peak memory 206404 kb
Host smart-2583032b-2e73-4310-b50b-23479135db19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066513022 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2066513022
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3375186171
Short name T825
Test name
Test status
Simulation time 50629241636 ps
CPU time 1096.14 seconds
Started Jul 29 06:21:14 PM PDT 24
Finished Jul 29 06:39:30 PM PDT 24
Peak memory 223584 kb
Host smart-e1668612-e4fe-4eb1-b676-720896eb2915
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375186171 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3375186171
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.923578995
Short name T674
Test name
Test status
Simulation time 57986062 ps
CPU time 1.21 seconds
Started Jul 29 06:22:33 PM PDT 24
Finished Jul 29 06:22:34 PM PDT 24
Peak memory 219728 kb
Host smart-6e5e436a-5281-4c0c-96ab-e4ee43af745f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923578995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.923578995
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.4189153859
Short name T408
Test name
Test status
Simulation time 269462876 ps
CPU time 3.32 seconds
Started Jul 29 06:22:39 PM PDT 24
Finished Jul 29 06:22:42 PM PDT 24
Peak memory 220216 kb
Host smart-757af33b-7fde-4c52-8dd3-1f45a5a57735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189153859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.4189153859
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.1260698518
Short name T410
Test name
Test status
Simulation time 54603775 ps
CPU time 1.32 seconds
Started Jul 29 06:23:00 PM PDT 24
Finished Jul 29 06:23:02 PM PDT 24
Peak memory 217308 kb
Host smart-e852935d-abd0-43a3-83e4-a5cbc9df93e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260698518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1260698518
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.139636812
Short name T204
Test name
Test status
Simulation time 49595713 ps
CPU time 1.15 seconds
Started Jul 29 06:22:28 PM PDT 24
Finished Jul 29 06:22:30 PM PDT 24
Peak memory 215672 kb
Host smart-c8d8806c-8442-422b-b744-3e57298c17d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139636812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.139636812
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.226230256
Short name T294
Test name
Test status
Simulation time 46137836 ps
CPU time 1.64 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 218824 kb
Host smart-53a403d7-690b-4cae-b526-ed9db8d21c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226230256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.226230256
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.3762758237
Short name T458
Test name
Test status
Simulation time 252518650 ps
CPU time 1.36 seconds
Started Jul 29 06:22:28 PM PDT 24
Finished Jul 29 06:22:30 PM PDT 24
Peak memory 220424 kb
Host smart-86d8a8cd-ea97-4cc9-92d4-2f078a234a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762758237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.3762758237
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.4288141059
Short name T712
Test name
Test status
Simulation time 95093239 ps
CPU time 2.2 seconds
Started Jul 29 06:22:33 PM PDT 24
Finished Jul 29 06:22:35 PM PDT 24
Peak memory 220232 kb
Host smart-f5c51e9d-6641-42c1-807a-28d8f4eb9897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288141059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.4288141059
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.4003007647
Short name T866
Test name
Test status
Simulation time 97290069 ps
CPU time 1.22 seconds
Started Jul 29 06:22:43 PM PDT 24
Finished Jul 29 06:22:45 PM PDT 24
Peak memory 218632 kb
Host smart-79392bd7-4594-4e56-ba51-bde1e53e7225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003007647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.4003007647
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.286287355
Short name T270
Test name
Test status
Simulation time 114122415 ps
CPU time 2.55 seconds
Started Jul 29 06:22:28 PM PDT 24
Finished Jul 29 06:22:30 PM PDT 24
Peak memory 218524 kb
Host smart-7a70fc4f-9260-4e90-b98f-634a65c85a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286287355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.286287355
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2025441422
Short name T461
Test name
Test status
Simulation time 62853727 ps
CPU time 1.1 seconds
Started Jul 29 06:22:42 PM PDT 24
Finished Jul 29 06:22:43 PM PDT 24
Peak memory 219412 kb
Host smart-2a01d6d9-f8d2-421e-b1f5-cd277d6efa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025441422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2025441422
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.1976006674
Short name T588
Test name
Test status
Simulation time 49985093 ps
CPU time 1.38 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:37 PM PDT 24
Peak memory 219480 kb
Host smart-6d0e8907-b778-4c18-a5e1-31f6c11bf21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976006674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1976006674
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.3345965835
Short name T245
Test name
Test status
Simulation time 31120404 ps
CPU time 1.32 seconds
Started Jul 29 06:22:31 PM PDT 24
Finished Jul 29 06:22:32 PM PDT 24
Peak memory 215684 kb
Host smart-269a44f1-41f9-4171-abbd-9b7eb8c65246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345965835 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3345965835
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.1068420474
Short name T35
Test name
Test status
Simulation time 39894824 ps
CPU time 1.47 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 220176 kb
Host smart-f603fdd8-8401-4401-8d78-8de83a10218a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068420474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1068420474
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.2765117992
Short name T765
Test name
Test status
Simulation time 35574109 ps
CPU time 1.2 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 218576 kb
Host smart-a166afff-be71-4f75-92b8-83da77368b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765117992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.2765117992
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.712716356
Short name T705
Test name
Test status
Simulation time 47357180 ps
CPU time 1.38 seconds
Started Jul 29 06:22:32 PM PDT 24
Finished Jul 29 06:22:33 PM PDT 24
Peak memory 218460 kb
Host smart-4c0222ed-461c-4f88-acb6-fb681797d418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712716356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.712716356
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1794768308
Short name T165
Test name
Test status
Simulation time 61157739 ps
CPU time 1.3 seconds
Started Jul 29 06:21:30 PM PDT 24
Finished Jul 29 06:21:31 PM PDT 24
Peak memory 215824 kb
Host smart-c1dcd2d0-6b4e-4f93-8de4-6ab089ff02ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794768308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1794768308
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3460611197
Short name T891
Test name
Test status
Simulation time 34694172 ps
CPU time 0.96 seconds
Started Jul 29 06:21:30 PM PDT 24
Finished Jul 29 06:21:31 PM PDT 24
Peak memory 206748 kb
Host smart-015e5f4f-55e5-4a3c-948c-c30aa6170105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460611197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3460611197
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1321436086
Short name T833
Test name
Test status
Simulation time 69145686 ps
CPU time 1.27 seconds
Started Jul 29 06:21:19 PM PDT 24
Finished Jul 29 06:21:20 PM PDT 24
Peak memory 217012 kb
Host smart-5745602d-ea5a-4d48-85ae-ec99da9fdebf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321436086 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1321436086
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2787072677
Short name T186
Test name
Test status
Simulation time 24760468 ps
CPU time 0.98 seconds
Started Jul 29 06:21:34 PM PDT 24
Finished Jul 29 06:21:35 PM PDT 24
Peak memory 218276 kb
Host smart-4ca6fb2d-ae45-4e4e-8386-571583f6f8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787072677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2787072677
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.4047558646
Short name T239
Test name
Test status
Simulation time 28057204 ps
CPU time 1.19 seconds
Started Jul 29 06:21:32 PM PDT 24
Finished Jul 29 06:21:33 PM PDT 24
Peak memory 220104 kb
Host smart-717d9403-4f26-4e5a-89b6-b179331457fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047558646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.4047558646
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.4191466303
Short name T902
Test name
Test status
Simulation time 45300448 ps
CPU time 0.88 seconds
Started Jul 29 06:21:20 PM PDT 24
Finished Jul 29 06:21:21 PM PDT 24
Peak memory 215700 kb
Host smart-bd60be67-ca2b-4aa7-92f1-b83f37a8a68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191466303 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.4191466303
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.4013781212
Short name T507
Test name
Test status
Simulation time 25305925 ps
CPU time 0.92 seconds
Started Jul 29 06:21:26 PM PDT 24
Finished Jul 29 06:21:27 PM PDT 24
Peak memory 215272 kb
Host smart-918f8132-4925-4764-9018-a5dcde577b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013781212 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4013781212
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1422090332
Short name T391
Test name
Test status
Simulation time 100165095 ps
CPU time 2.37 seconds
Started Jul 29 06:21:31 PM PDT 24
Finished Jul 29 06:21:33 PM PDT 24
Peak memory 215328 kb
Host smart-58120db3-1835-427f-bb89-c006ac32df47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422090332 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1422090332
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1245598672
Short name T639
Test name
Test status
Simulation time 120643348388 ps
CPU time 1045.46 seconds
Started Jul 29 06:21:24 PM PDT 24
Finished Jul 29 06:38:49 PM PDT 24
Peak memory 221752 kb
Host smart-5fdc3b23-68cd-40e8-8df1-d66e53800d65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245598672 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1245598672
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.273951918
Short name T826
Test name
Test status
Simulation time 26077130 ps
CPU time 1.2 seconds
Started Jul 29 06:22:29 PM PDT 24
Finished Jul 29 06:22:31 PM PDT 24
Peak memory 218680 kb
Host smart-b06086a8-9355-4106-b332-12ef93d22d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273951918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.273951918
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.2716720147
Short name T310
Test name
Test status
Simulation time 68141210 ps
CPU time 1.51 seconds
Started Jul 29 06:22:51 PM PDT 24
Finished Jul 29 06:22:53 PM PDT 24
Peak memory 219892 kb
Host smart-0546899f-ad06-477a-8512-9463c02dc4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716720147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2716720147
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.1050452101
Short name T287
Test name
Test status
Simulation time 52698164 ps
CPU time 1.27 seconds
Started Jul 29 06:22:30 PM PDT 24
Finished Jul 29 06:22:32 PM PDT 24
Peak memory 215660 kb
Host smart-7991fbe3-df60-4554-96c9-aafb8c3c8e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050452101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.1050452101
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.283437444
Short name T603
Test name
Test status
Simulation time 48676377 ps
CPU time 1.38 seconds
Started Jul 29 06:22:30 PM PDT 24
Finished Jul 29 06:22:32 PM PDT 24
Peak memory 217548 kb
Host smart-6df881a3-4e31-4c3d-a9e4-efced9bc0ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283437444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.283437444
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.2730857828
Short name T788
Test name
Test status
Simulation time 39746384 ps
CPU time 1.17 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:40 PM PDT 24
Peak memory 219684 kb
Host smart-ab33f9fc-cc29-4660-8f96-5ac1e42abfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730857828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2730857828
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.770690051
Short name T939
Test name
Test status
Simulation time 212195239 ps
CPU time 1.41 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:40 PM PDT 24
Peak memory 218608 kb
Host smart-df618dc3-c877-4673-9ff2-89e8824d50a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770690051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.770690051
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2175558167
Short name T853
Test name
Test status
Simulation time 38809966 ps
CPU time 1.07 seconds
Started Jul 29 06:22:31 PM PDT 24
Finished Jul 29 06:22:32 PM PDT 24
Peak memory 218776 kb
Host smart-abf77b1b-53e3-4185-b1ed-04e95e655fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175558167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2175558167
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.41677772
Short name T400
Test name
Test status
Simulation time 99751041 ps
CPU time 1.3 seconds
Started Jul 29 06:22:30 PM PDT 24
Finished Jul 29 06:22:32 PM PDT 24
Peak memory 217660 kb
Host smart-0576d4a4-8097-4018-8c1f-a64ab88009c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41677772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.41677772
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.158097356
Short name T898
Test name
Test status
Simulation time 135136349 ps
CPU time 1.18 seconds
Started Jul 29 06:22:31 PM PDT 24
Finished Jul 29 06:22:32 PM PDT 24
Peak memory 218268 kb
Host smart-b7924eb9-28d6-4bb4-9f91-92b66eef9fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158097356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.158097356
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.2899564495
Short name T30
Test name
Test status
Simulation time 142072812 ps
CPU time 3.17 seconds
Started Jul 29 06:22:43 PM PDT 24
Finished Jul 29 06:22:47 PM PDT 24
Peak memory 219176 kb
Host smart-34ca8867-bea2-4669-837e-da265c64dafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899564495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2899564495
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.4216419317
Short name T658
Test name
Test status
Simulation time 23567072 ps
CPU time 1.17 seconds
Started Jul 29 06:22:34 PM PDT 24
Finished Jul 29 06:22:35 PM PDT 24
Peak memory 219848 kb
Host smart-0302ee61-481e-457f-964c-f2f33be167d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216419317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.4216419317
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.518694493
Short name T909
Test name
Test status
Simulation time 61547311 ps
CPU time 1.04 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:37 PM PDT 24
Peak memory 217276 kb
Host smart-f9bc8d38-479f-4209-8bf6-2bb20ae2f8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518694493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.518694493
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1416693716
Short name T216
Test name
Test status
Simulation time 26976660 ps
CPU time 1.19 seconds
Started Jul 29 06:22:42 PM PDT 24
Finished Jul 29 06:22:43 PM PDT 24
Peak memory 219852 kb
Host smart-4ce12800-2fda-4849-a248-0215bf09b17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416693716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1416693716
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/117.edn_alert.2137631163
Short name T23
Test name
Test status
Simulation time 39373384 ps
CPU time 1.12 seconds
Started Jul 29 06:22:45 PM PDT 24
Finished Jul 29 06:22:47 PM PDT 24
Peak memory 219980 kb
Host smart-00ed69dd-a48b-4cdd-b280-f241718f66d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137631163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.2137631163
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.754658070
Short name T604
Test name
Test status
Simulation time 70544300 ps
CPU time 1.22 seconds
Started Jul 29 06:22:39 PM PDT 24
Finished Jul 29 06:22:40 PM PDT 24
Peak memory 217260 kb
Host smart-b99ff350-7bdb-43a8-b2c1-e6710bc438ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754658070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.754658070
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.4053158363
Short name T770
Test name
Test status
Simulation time 50176138 ps
CPU time 1.19 seconds
Started Jul 29 06:22:39 PM PDT 24
Finished Jul 29 06:22:40 PM PDT 24
Peak memory 220060 kb
Host smart-7f5718b3-b3f7-4896-9cd0-d986dcfa0bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053158363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.4053158363
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.1670259839
Short name T86
Test name
Test status
Simulation time 36234107 ps
CPU time 1.4 seconds
Started Jul 29 06:22:44 PM PDT 24
Finished Jul 29 06:22:45 PM PDT 24
Peak memory 219756 kb
Host smart-b451e416-5a8d-448d-b119-92ce5a6dd542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670259839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1670259839
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1817213255
Short name T596
Test name
Test status
Simulation time 60228227 ps
CPU time 1.08 seconds
Started Jul 29 06:22:39 PM PDT 24
Finished Jul 29 06:22:40 PM PDT 24
Peak memory 215648 kb
Host smart-72b76ff4-5fc2-4d5b-b33e-466fbe064492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817213255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1817213255
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.1447604613
Short name T10
Test name
Test status
Simulation time 39446823 ps
CPU time 1.38 seconds
Started Jul 29 06:22:44 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 220028 kb
Host smart-c3608f8f-bf75-4e4a-ac85-629806571175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447604613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1447604613
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.327181788
Short name T586
Test name
Test status
Simulation time 29401349 ps
CPU time 1.31 seconds
Started Jul 29 06:21:21 PM PDT 24
Finished Jul 29 06:21:22 PM PDT 24
Peak memory 218580 kb
Host smart-84a08d98-be8f-4b45-9694-8ae53b2248de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327181788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.327181788
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.55786919
Short name T666
Test name
Test status
Simulation time 27299908 ps
CPU time 0.94 seconds
Started Jul 29 06:21:32 PM PDT 24
Finished Jul 29 06:21:33 PM PDT 24
Peak memory 214820 kb
Host smart-32e12a96-f09c-4939-94eb-92599ebef2ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55786919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.55786919
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.880608270
Short name T437
Test name
Test status
Simulation time 32960922 ps
CPU time 0.83 seconds
Started Jul 29 06:21:18 PM PDT 24
Finished Jul 29 06:21:19 PM PDT 24
Peak memory 216072 kb
Host smart-4665966d-dc31-47ea-87b7-27beb76d6463
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880608270 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.880608270
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1823314171
Short name T769
Test name
Test status
Simulation time 47166304 ps
CPU time 1.06 seconds
Started Jul 29 06:21:19 PM PDT 24
Finished Jul 29 06:21:20 PM PDT 24
Peak memory 218496 kb
Host smart-37928448-83b1-46e6-9931-870c38f2df3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823314171 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1823314171
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2221251570
Short name T130
Test name
Test status
Simulation time 33222280 ps
CPU time 0.88 seconds
Started Jul 29 06:21:26 PM PDT 24
Finished Jul 29 06:21:27 PM PDT 24
Peak memory 218324 kb
Host smart-cab5beca-1404-44e8-967e-f51ced7a17a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221251570 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2221251570
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1115643119
Short name T12
Test name
Test status
Simulation time 137723603 ps
CPU time 1.38 seconds
Started Jul 29 06:21:23 PM PDT 24
Finished Jul 29 06:21:25 PM PDT 24
Peak memory 218672 kb
Host smart-1a20e9a5-cee6-457d-a898-3f6f4c43eb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115643119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1115643119
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2165806587
Short name T702
Test name
Test status
Simulation time 36690708 ps
CPU time 0.96 seconds
Started Jul 29 06:21:14 PM PDT 24
Finished Jul 29 06:21:15 PM PDT 24
Peak memory 223852 kb
Host smart-18e64130-d45a-4be8-8c95-85db7229fccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165806587 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2165806587
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.4292835232
Short name T237
Test name
Test status
Simulation time 48961069 ps
CPU time 0.89 seconds
Started Jul 29 06:21:19 PM PDT 24
Finished Jul 29 06:21:20 PM PDT 24
Peak memory 215268 kb
Host smart-6e8f5300-f56b-4fcc-8105-a36169dc8e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292835232 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.4292835232
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1246299538
Short name T527
Test name
Test status
Simulation time 308051895 ps
CPU time 2.09 seconds
Started Jul 29 06:21:29 PM PDT 24
Finished Jul 29 06:21:31 PM PDT 24
Peak memory 217204 kb
Host smart-8dae634b-c8b8-4aa8-bdae-81cf85bc2cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246299538 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1246299538
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1671128057
Short name T493
Test name
Test status
Simulation time 399071425864 ps
CPU time 2248.76 seconds
Started Jul 29 06:21:29 PM PDT 24
Finished Jul 29 06:58:58 PM PDT 24
Peak memory 227140 kb
Host smart-ff282088-f7eb-470b-8457-86bd87efcfb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671128057 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1671128057
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.3014203079
Short name T266
Test name
Test status
Simulation time 88748791 ps
CPU time 0.99 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 218344 kb
Host smart-f6df6010-e574-4c3a-a69f-3994338a5a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014203079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.3014203079
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.985419476
Short name T512
Test name
Test status
Simulation time 30111862 ps
CPU time 1.4 seconds
Started Jul 29 06:22:50 PM PDT 24
Finished Jul 29 06:22:52 PM PDT 24
Peak memory 219936 kb
Host smart-02e202c3-8858-480c-ae29-f48073508d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985419476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.985419476
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.893519506
Short name T740
Test name
Test status
Simulation time 79316588 ps
CPU time 1.2 seconds
Started Jul 29 06:22:45 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 219224 kb
Host smart-a7cd359e-a64e-425c-84f0-2ef39eda492b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893519506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.893519506
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.3665054572
Short name T382
Test name
Test status
Simulation time 52053873 ps
CPU time 1.76 seconds
Started Jul 29 06:22:46 PM PDT 24
Finished Jul 29 06:22:48 PM PDT 24
Peak memory 218484 kb
Host smart-7565f252-ddaa-44eb-b474-993547e15b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665054572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3665054572
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.3260925923
Short name T570
Test name
Test status
Simulation time 98187796 ps
CPU time 1.18 seconds
Started Jul 29 06:22:39 PM PDT 24
Finished Jul 29 06:22:40 PM PDT 24
Peak memory 219504 kb
Host smart-54411f28-2d8e-4a97-a74b-2f60b93558cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260925923 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3260925923
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.2097406026
Short name T637
Test name
Test status
Simulation time 60084051 ps
CPU time 1.41 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 218916 kb
Host smart-b9192403-5ef5-486b-b578-96747fb583a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097406026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2097406026
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.315962901
Short name T776
Test name
Test status
Simulation time 90292899 ps
CPU time 1.19 seconds
Started Jul 29 06:23:10 PM PDT 24
Finished Jul 29 06:23:11 PM PDT 24
Peak memory 220220 kb
Host smart-f84685cc-d700-46de-9217-6fb9d7ec1041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315962901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.315962901
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.3422394821
Short name T868
Test name
Test status
Simulation time 47966744 ps
CPU time 1.54 seconds
Started Jul 29 06:22:41 PM PDT 24
Finished Jul 29 06:22:42 PM PDT 24
Peak memory 220052 kb
Host smart-c2d6c87a-4be7-426e-bf56-33bfeeb36455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422394821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3422394821
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.674811680
Short name T70
Test name
Test status
Simulation time 96839607 ps
CPU time 1.26 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 218372 kb
Host smart-195a2ea4-dd63-45f8-8c67-daab8d2b82c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674811680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.674811680
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.2154288263
Short name T640
Test name
Test status
Simulation time 34890870 ps
CPU time 1.41 seconds
Started Jul 29 06:22:45 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 215248 kb
Host smart-8b8e775a-7329-4843-8380-708cdaef42c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154288263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2154288263
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.3878184246
Short name T661
Test name
Test status
Simulation time 27409285 ps
CPU time 1.15 seconds
Started Jul 29 06:22:46 PM PDT 24
Finished Jul 29 06:22:47 PM PDT 24
Peak memory 218848 kb
Host smart-02ef5db8-fb2c-40f3-b09e-5d0d1d4ba260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878184246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3878184246
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/127.edn_alert.2825175288
Short name T99
Test name
Test status
Simulation time 70489223 ps
CPU time 1.08 seconds
Started Jul 29 06:22:47 PM PDT 24
Finished Jul 29 06:22:48 PM PDT 24
Peak memory 218428 kb
Host smart-e9bb0e2e-62bb-4a56-b6db-7960c157c816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825175288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.2825175288
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.3028298395
Short name T534
Test name
Test status
Simulation time 49518363 ps
CPU time 1.49 seconds
Started Jul 29 06:22:34 PM PDT 24
Finished Jul 29 06:22:36 PM PDT 24
Peak memory 218512 kb
Host smart-8d1f847e-4fcd-4400-94da-f7d369066cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028298395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3028298395
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2835976168
Short name T286
Test name
Test status
Simulation time 255732340 ps
CPU time 1.43 seconds
Started Jul 29 06:22:53 PM PDT 24
Finished Jul 29 06:22:55 PM PDT 24
Peak memory 219164 kb
Host smart-31c2fff3-0c24-41cc-98ad-2a93dba764de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835976168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2835976168
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.2736543196
Short name T427
Test name
Test status
Simulation time 128400537 ps
CPU time 1.6 seconds
Started Jul 29 06:22:47 PM PDT 24
Finished Jul 29 06:22:48 PM PDT 24
Peak memory 218820 kb
Host smart-0c0f17dd-d499-4ee7-bc60-b310f81326d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736543196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2736543196
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.1467020970
Short name T783
Test name
Test status
Simulation time 30080206 ps
CPU time 1.25 seconds
Started Jul 29 06:22:44 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 215640 kb
Host smart-8e8bec64-8e38-4d2e-aaf1-1c7ab6aa0564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467020970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.1467020970
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.1427843155
Short name T632
Test name
Test status
Simulation time 18775485 ps
CPU time 1.05 seconds
Started Jul 29 06:22:33 PM PDT 24
Finished Jul 29 06:22:34 PM PDT 24
Peak memory 218464 kb
Host smart-3bdf41c2-fa00-4f0e-b95c-36051fc7d995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427843155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1427843155
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1272896890
Short name T892
Test name
Test status
Simulation time 24533974 ps
CPU time 1.22 seconds
Started Jul 29 06:21:30 PM PDT 24
Finished Jul 29 06:21:31 PM PDT 24
Peak memory 220544 kb
Host smart-27a4a161-e243-4cc4-8603-4bbfb3daec19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272896890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1272896890
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.767086432
Short name T469
Test name
Test status
Simulation time 18718587 ps
CPU time 0.98 seconds
Started Jul 29 06:21:34 PM PDT 24
Finished Jul 29 06:21:35 PM PDT 24
Peak memory 206688 kb
Host smart-4ebba334-af8b-4cce-bded-2348cb2f95ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767086432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.767086432
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.945178208
Short name T434
Test name
Test status
Simulation time 21281370 ps
CPU time 0.89 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:21:43 PM PDT 24
Peak memory 216204 kb
Host smart-d2afd1f2-2189-4285-b273-869d2f7dd03e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945178208 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.945178208
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3091886888
Short name T128
Test name
Test status
Simulation time 38395871 ps
CPU time 1.05 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 217000 kb
Host smart-c4791f3c-b01e-43c1-bc55-a47e1535d7f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091886888 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3091886888
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2780593166
Short name T179
Test name
Test status
Simulation time 19708164 ps
CPU time 1.06 seconds
Started Jul 29 06:21:45 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 218508 kb
Host smart-12327796-e55b-4bef-b1c9-d4cc6a89f702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780593166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2780593166
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1960191660
Short name T322
Test name
Test status
Simulation time 72162677 ps
CPU time 2.76 seconds
Started Jul 29 06:21:18 PM PDT 24
Finished Jul 29 06:21:21 PM PDT 24
Peak memory 220080 kb
Host smart-84c08075-c3fb-4116-94ba-7977bb0395a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960191660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1960191660
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3425133866
Short name T567
Test name
Test status
Simulation time 37659275 ps
CPU time 1.02 seconds
Started Jul 29 06:21:39 PM PDT 24
Finished Jul 29 06:21:40 PM PDT 24
Peak memory 224016 kb
Host smart-465860ff-c6c2-4233-836a-8db0effff73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425133866 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3425133866
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.4155419859
Short name T332
Test name
Test status
Simulation time 18040948 ps
CPU time 0.96 seconds
Started Jul 29 06:21:34 PM PDT 24
Finished Jul 29 06:21:35 PM PDT 24
Peak memory 215252 kb
Host smart-f6f24996-a340-4f3a-8be2-a2b0a2740bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155419859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.4155419859
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1449566434
Short name T764
Test name
Test status
Simulation time 401077000 ps
CPU time 4.11 seconds
Started Jul 29 06:21:19 PM PDT 24
Finished Jul 29 06:21:23 PM PDT 24
Peak memory 218524 kb
Host smart-f18fd3fd-9862-49a7-93c6-fb6dffacf4e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449566434 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1449566434
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2464439768
Short name T221
Test name
Test status
Simulation time 35030052327 ps
CPU time 462.89 seconds
Started Jul 29 06:21:39 PM PDT 24
Finished Jul 29 06:29:22 PM PDT 24
Peak memory 218432 kb
Host smart-25a9ed00-6f4c-4664-86f8-75ef338d8897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464439768 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2464439768
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.3179167111
Short name T100
Test name
Test status
Simulation time 259995696 ps
CPU time 1.11 seconds
Started Jul 29 06:22:59 PM PDT 24
Finished Jul 29 06:23:00 PM PDT 24
Peak memory 218588 kb
Host smart-0c62c1d2-59d0-4f81-946a-00e3bdbd630e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179167111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3179167111
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.631390938
Short name T741
Test name
Test status
Simulation time 95414141 ps
CPU time 1.25 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 217208 kb
Host smart-2f3f0b7a-7717-4918-86cb-4a30c3f35b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631390938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.631390938
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.3320136005
Short name T599
Test name
Test status
Simulation time 86052187 ps
CPU time 1.18 seconds
Started Jul 29 06:22:44 PM PDT 24
Finished Jul 29 06:22:45 PM PDT 24
Peak memory 215688 kb
Host smart-3998fff5-9100-430b-a1b9-457a34129453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320136005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3320136005
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.359561863
Short name T908
Test name
Test status
Simulation time 72133845 ps
CPU time 1.35 seconds
Started Jul 29 06:22:47 PM PDT 24
Finished Jul 29 06:22:48 PM PDT 24
Peak memory 219072 kb
Host smart-7e4f93d4-458f-4ee6-8000-31cc809b8ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359561863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.359561863
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.2034100359
Short name T647
Test name
Test status
Simulation time 84709684 ps
CPU time 1.13 seconds
Started Jul 29 06:23:00 PM PDT 24
Finished Jul 29 06:23:01 PM PDT 24
Peak memory 219720 kb
Host smart-2be8ffe7-901a-4010-9d55-f2475fef34e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034100359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.2034100359
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.402620217
Short name T880
Test name
Test status
Simulation time 48597159 ps
CPU time 1.82 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 218660 kb
Host smart-7d76210e-0430-455f-a4a0-9aa0e663759c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402620217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.402620217
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.3750382772
Short name T473
Test name
Test status
Simulation time 42848460 ps
CPU time 1.13 seconds
Started Jul 29 06:22:46 PM PDT 24
Finished Jul 29 06:22:47 PM PDT 24
Peak memory 219824 kb
Host smart-050f7d87-5b63-4cb4-a191-316f300c77a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750382772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.3750382772
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.1309983747
Short name T574
Test name
Test status
Simulation time 154653587 ps
CPU time 3.31 seconds
Started Jul 29 06:22:45 PM PDT 24
Finished Jul 29 06:22:49 PM PDT 24
Peak memory 220092 kb
Host smart-ded6aae6-c8e8-4229-b213-607afa28018d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309983747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1309983747
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.995471079
Short name T801
Test name
Test status
Simulation time 138252681 ps
CPU time 1.23 seconds
Started Jul 29 06:22:46 PM PDT 24
Finished Jul 29 06:22:47 PM PDT 24
Peak memory 219544 kb
Host smart-184b14ff-ba6b-44ad-ab8c-e4652404d125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995471079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.995471079
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.824331148
Short name T462
Test name
Test status
Simulation time 30749432 ps
CPU time 1.22 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:37 PM PDT 24
Peak memory 217264 kb
Host smart-44d1040d-2e62-4185-8be9-7b250ef1fdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824331148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.824331148
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.2262274191
Short name T520
Test name
Test status
Simulation time 354280974 ps
CPU time 1.32 seconds
Started Jul 29 06:22:44 PM PDT 24
Finished Jul 29 06:22:45 PM PDT 24
Peak memory 215640 kb
Host smart-7147bcf9-4e6b-4743-aa6c-130edd3885d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262274191 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.2262274191
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.1490217962
Short name T945
Test name
Test status
Simulation time 36861224 ps
CPU time 1.38 seconds
Started Jul 29 06:22:59 PM PDT 24
Finished Jul 29 06:23:00 PM PDT 24
Peak memory 219948 kb
Host smart-35b9b183-514e-4676-a8fb-7301185b9695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490217962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1490217962
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.1305914709
Short name T154
Test name
Test status
Simulation time 56002902 ps
CPU time 1.23 seconds
Started Jul 29 06:22:50 PM PDT 24
Finished Jul 29 06:22:51 PM PDT 24
Peak memory 218400 kb
Host smart-601795f9-f1a7-4804-952d-49c1de228a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305914709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1305914709
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.1600525533
Short name T556
Test name
Test status
Simulation time 73916628 ps
CPU time 2.23 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 218580 kb
Host smart-39ee2a44-032d-4233-b873-1df563c035be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600525533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1600525533
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.3852668918
Short name T525
Test name
Test status
Simulation time 58365473 ps
CPU time 1.22 seconds
Started Jul 29 06:22:58 PM PDT 24
Finished Jul 29 06:22:59 PM PDT 24
Peak memory 217244 kb
Host smart-a4218f48-13f9-4daf-ac2c-63e2caf60d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852668918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3852668918
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3568779535
Short name T559
Test name
Test status
Simulation time 156016570 ps
CPU time 1.96 seconds
Started Jul 29 06:22:40 PM PDT 24
Finished Jul 29 06:22:43 PM PDT 24
Peak memory 220228 kb
Host smart-f99ca91c-1b50-4206-88bd-c788817cd033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568779535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3568779535
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3053196989
Short name T105
Test name
Test status
Simulation time 31649998 ps
CPU time 1.3 seconds
Started Jul 29 06:21:33 PM PDT 24
Finished Jul 29 06:21:35 PM PDT 24
Peak memory 219436 kb
Host smart-08e36690-fde7-4944-a8f7-94a6cdb7a92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053196989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3053196989
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1380852713
Short name T585
Test name
Test status
Simulation time 53287098 ps
CPU time 0.83 seconds
Started Jul 29 06:21:45 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 206760 kb
Host smart-d253f271-c987-4e81-a06c-56aabb0417d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380852713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1380852713
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.786838138
Short name T743
Test name
Test status
Simulation time 100728724 ps
CPU time 1.14 seconds
Started Jul 29 06:21:35 PM PDT 24
Finished Jul 29 06:21:36 PM PDT 24
Peak memory 218708 kb
Host smart-c8d292ae-13fc-472f-96bb-37d3d4e6d236
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786838138 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.786838138
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1444583280
Short name T707
Test name
Test status
Simulation time 36618981 ps
CPU time 0.97 seconds
Started Jul 29 06:21:40 PM PDT 24
Finished Jul 29 06:21:41 PM PDT 24
Peak memory 223856 kb
Host smart-d0f9d4c7-b507-4318-9cae-0cc1d59f0988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444583280 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1444583280
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_smoke.3809604443
Short name T424
Test name
Test status
Simulation time 61949270 ps
CPU time 0.94 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:21:42 PM PDT 24
Peak memory 215288 kb
Host smart-973ff311-dd4a-4aae-8e9b-ebae0b975aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809604443 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3809604443
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1131454094
Short name T4
Test name
Test status
Simulation time 1063388072 ps
CPU time 2.75 seconds
Started Jul 29 06:21:32 PM PDT 24
Finished Jul 29 06:21:35 PM PDT 24
Peak memory 215296 kb
Host smart-10424aae-ad1e-407e-96b7-bfcb12994685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131454094 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1131454094
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.943097827
Short name T759
Test name
Test status
Simulation time 343526372418 ps
CPU time 1068.21 seconds
Started Jul 29 06:21:34 PM PDT 24
Finished Jul 29 06:39:22 PM PDT 24
Peak memory 224240 kb
Host smart-65d2d894-7896-4d9e-b86b-e809f46da24d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943097827 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.943097827
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.2016875414
Short name T713
Test name
Test status
Simulation time 34133983 ps
CPU time 1 seconds
Started Jul 29 06:22:39 PM PDT 24
Finished Jul 29 06:22:40 PM PDT 24
Peak memory 219544 kb
Host smart-ce3dbc2a-5540-4ae1-bfcc-06dfc7af10b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016875414 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.2016875414
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.80608608
Short name T558
Test name
Test status
Simulation time 58626605 ps
CPU time 1.38 seconds
Started Jul 29 06:22:54 PM PDT 24
Finished Jul 29 06:22:56 PM PDT 24
Peak memory 218960 kb
Host smart-fbd76547-42b9-424b-bec1-6daa5e513176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80608608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.80608608
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3881857986
Short name T2
Test name
Test status
Simulation time 70811052 ps
CPU time 2.37 seconds
Started Jul 29 06:22:47 PM PDT 24
Finished Jul 29 06:22:49 PM PDT 24
Peak memory 219596 kb
Host smart-09fefce7-93d3-40fd-8901-20877291ae15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881857986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3881857986
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3174994932
Short name T621
Test name
Test status
Simulation time 97786362 ps
CPU time 1.23 seconds
Started Jul 29 06:23:07 PM PDT 24
Finished Jul 29 06:23:08 PM PDT 24
Peak memory 220196 kb
Host smart-c0c34a1d-7587-4ed7-af26-fa795362d525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174994932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3174994932
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.3340476528
Short name T857
Test name
Test status
Simulation time 67945554 ps
CPU time 1.12 seconds
Started Jul 29 06:22:40 PM PDT 24
Finished Jul 29 06:22:41 PM PDT 24
Peak memory 217412 kb
Host smart-9691d72d-b33b-4be4-88f2-c21129a48336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340476528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3340476528
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.2978666150
Short name T148
Test name
Test status
Simulation time 31667136 ps
CPU time 1.32 seconds
Started Jul 29 06:22:50 PM PDT 24
Finished Jul 29 06:22:51 PM PDT 24
Peak memory 215688 kb
Host smart-8d6f1b6b-29cb-4102-874e-6e97b0ac4a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978666150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.2978666150
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.2170438152
Short name T489
Test name
Test status
Simulation time 38122720 ps
CPU time 1.62 seconds
Started Jul 29 06:22:52 PM PDT 24
Finished Jul 29 06:22:54 PM PDT 24
Peak memory 218360 kb
Host smart-52a6112e-f721-426e-972e-9ce27215f1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170438152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2170438152
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.2072213170
Short name T560
Test name
Test status
Simulation time 40344738 ps
CPU time 1.19 seconds
Started Jul 29 06:22:43 PM PDT 24
Finished Jul 29 06:22:45 PM PDT 24
Peak memory 219064 kb
Host smart-a5e2b989-9655-4984-bf25-2e98ceb0c440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072213170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.2072213170
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.2430980112
Short name T456
Test name
Test status
Simulation time 34874543 ps
CPU time 1.39 seconds
Started Jul 29 06:22:50 PM PDT 24
Finished Jul 29 06:22:51 PM PDT 24
Peak memory 219508 kb
Host smart-b519aabd-0c6d-4704-9b0a-1ec3850e1341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430980112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2430980112
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.3428825893
Short name T282
Test name
Test status
Simulation time 29479841 ps
CPU time 1.31 seconds
Started Jul 29 06:22:56 PM PDT 24
Finished Jul 29 06:22:57 PM PDT 24
Peak memory 220140 kb
Host smart-a4e59be9-2f7d-44d7-a833-67d91e7f550e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428825893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3428825893
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.2343786781
Short name T934
Test name
Test status
Simulation time 41326280 ps
CPU time 1.45 seconds
Started Jul 29 06:22:44 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 219780 kb
Host smart-c0b84f0b-7a07-4cda-ab38-258d92b1abb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343786781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2343786781
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.1472707188
Short name T265
Test name
Test status
Simulation time 26376484 ps
CPU time 1.19 seconds
Started Jul 29 06:22:41 PM PDT 24
Finished Jul 29 06:22:42 PM PDT 24
Peak memory 219584 kb
Host smart-75f5f24d-6d03-4c79-8f0b-ead4dc4664ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472707188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.1472707188
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.3991210316
Short name T404
Test name
Test status
Simulation time 79864674 ps
CPU time 1.62 seconds
Started Jul 29 06:22:46 PM PDT 24
Finished Jul 29 06:22:48 PM PDT 24
Peak memory 218584 kb
Host smart-6b93a78d-3d7a-4bd3-97ec-9eff96382fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991210316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3991210316
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.4049253369
Short name T450
Test name
Test status
Simulation time 29873034 ps
CPU time 1.05 seconds
Started Jul 29 06:22:44 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 217188 kb
Host smart-12734370-88d6-4749-a4d1-e8dbf4366c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049253369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.4049253369
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.3784448787
Short name T191
Test name
Test status
Simulation time 23952325 ps
CPU time 1.16 seconds
Started Jul 29 06:22:52 PM PDT 24
Finished Jul 29 06:22:53 PM PDT 24
Peak memory 218440 kb
Host smart-b7e376f6-21bd-4a64-ab03-07f21fd9da8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784448787 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.3784448787
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.2607029124
Short name T18
Test name
Test status
Simulation time 34194959 ps
CPU time 1.56 seconds
Started Jul 29 06:23:00 PM PDT 24
Finished Jul 29 06:23:02 PM PDT 24
Peak memory 219960 kb
Host smart-5fe13504-c869-407e-bc8d-fcf2d63deeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607029124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2607029124
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2498777779
Short name T654
Test name
Test status
Simulation time 29267707 ps
CPU time 1.2 seconds
Started Jul 29 06:22:44 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 217168 kb
Host smart-3486e47e-ff5c-4d0a-b6b3-13eead4b67aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498777779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2498777779
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1551347622
Short name T74
Test name
Test status
Simulation time 47365483 ps
CPU time 1.27 seconds
Started Jul 29 06:21:29 PM PDT 24
Finished Jul 29 06:21:30 PM PDT 24
Peak memory 220132 kb
Host smart-08029805-7d0a-4fae-86db-656b54e08285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551347622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1551347622
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.900650706
Short name T241
Test name
Test status
Simulation time 74973858 ps
CPU time 0.84 seconds
Started Jul 29 06:21:31 PM PDT 24
Finished Jul 29 06:21:32 PM PDT 24
Peak memory 206544 kb
Host smart-440ffeea-d753-44ea-839f-cf18b75248be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900650706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.900650706
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.358867012
Short name T933
Test name
Test status
Simulation time 12004951 ps
CPU time 0.9 seconds
Started Jul 29 06:21:31 PM PDT 24
Finished Jul 29 06:21:32 PM PDT 24
Peak memory 216284 kb
Host smart-13626890-00c8-469a-a710-55362f733349
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358867012 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.358867012
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.1517102986
Short name T141
Test name
Test status
Simulation time 53712651 ps
CPU time 0.84 seconds
Started Jul 29 06:21:38 PM PDT 24
Finished Jul 29 06:21:39 PM PDT 24
Peak memory 219196 kb
Host smart-b6d24e43-8c3d-480f-9dd5-b2b20ca93d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517102986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1517102986
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3504962519
Short name T553
Test name
Test status
Simulation time 69217016 ps
CPU time 1.1 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:21:42 PM PDT 24
Peak memory 217288 kb
Host smart-bafd20c9-5d8c-4683-88fe-ee265c289d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504962519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3504962519
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1337733316
Short name T88
Test name
Test status
Simulation time 22621157 ps
CPU time 0.94 seconds
Started Jul 29 06:21:38 PM PDT 24
Finished Jul 29 06:21:39 PM PDT 24
Peak memory 215816 kb
Host smart-b9fea762-77b4-4ce1-9e37-10a37c671e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337733316 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1337733316
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1490134304
Short name T876
Test name
Test status
Simulation time 25331436 ps
CPU time 0.95 seconds
Started Jul 29 06:21:30 PM PDT 24
Finished Jul 29 06:21:31 PM PDT 24
Peak memory 215248 kb
Host smart-bb168167-b8a9-454a-9a3e-cc77ea03e719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490134304 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1490134304
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.663787209
Short name T859
Test name
Test status
Simulation time 762925790 ps
CPU time 3.71 seconds
Started Jul 29 06:21:35 PM PDT 24
Finished Jul 29 06:21:39 PM PDT 24
Peak memory 215264 kb
Host smart-419e69a0-bfb2-4515-a713-29d0584a714c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663787209 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.663787209
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3857898641
Short name T356
Test name
Test status
Simulation time 39422745074 ps
CPU time 252.72 seconds
Started Jul 29 06:21:31 PM PDT 24
Finished Jul 29 06:25:44 PM PDT 24
Peak memory 218476 kb
Host smart-20684d7e-d039-4fec-9871-de37900d9bf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857898641 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3857898641
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2880687863
Short name T289
Test name
Test status
Simulation time 25136016 ps
CPU time 1.24 seconds
Started Jul 29 06:22:56 PM PDT 24
Finished Jul 29 06:22:57 PM PDT 24
Peak memory 219864 kb
Host smart-d2054e1c-e75e-4d99-ba79-c1508e38e71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880687863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2880687863
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.3201341518
Short name T925
Test name
Test status
Simulation time 51001888 ps
CPU time 1.74 seconds
Started Jul 29 06:22:47 PM PDT 24
Finished Jul 29 06:22:49 PM PDT 24
Peak memory 218552 kb
Host smart-c53a84f5-8fd5-4fed-95fe-850d3a579a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201341518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3201341518
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.532004770
Short name T748
Test name
Test status
Simulation time 379622501 ps
CPU time 1.41 seconds
Started Jul 29 06:22:45 PM PDT 24
Finished Jul 29 06:22:47 PM PDT 24
Peak memory 218376 kb
Host smart-e5257e4c-6300-45ec-a6cf-e2923e0abe0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532004770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.532004770
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.2953682691
Short name T847
Test name
Test status
Simulation time 52119318 ps
CPU time 1.21 seconds
Started Jul 29 06:22:46 PM PDT 24
Finished Jul 29 06:22:48 PM PDT 24
Peak memory 218760 kb
Host smart-3a3c241d-a54c-4492-a2ae-22ba9ec935c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953682691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2953682691
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.2676073691
Short name T104
Test name
Test status
Simulation time 53660583 ps
CPU time 1.24 seconds
Started Jul 29 06:23:08 PM PDT 24
Finished Jul 29 06:23:09 PM PDT 24
Peak memory 218656 kb
Host smart-fa5c3714-d0c7-4ae2-a8f7-228b4f6616c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676073691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2676073691
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.3701674346
Short name T308
Test name
Test status
Simulation time 53950328 ps
CPU time 1.43 seconds
Started Jul 29 06:23:12 PM PDT 24
Finished Jul 29 06:23:13 PM PDT 24
Peak memory 218796 kb
Host smart-bb481a91-3562-4611-bb93-a066de37d5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701674346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3701674346
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.3489404272
Short name T476
Test name
Test status
Simulation time 71760360 ps
CPU time 1.12 seconds
Started Jul 29 06:22:49 PM PDT 24
Finished Jul 29 06:22:50 PM PDT 24
Peak memory 220296 kb
Host smart-7de98cb3-ddeb-4d02-8698-503d8202e34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489404272 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3489404272
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3458777594
Short name T863
Test name
Test status
Simulation time 298728551 ps
CPU time 1.44 seconds
Started Jul 29 06:22:45 PM PDT 24
Finished Jul 29 06:22:47 PM PDT 24
Peak memory 220356 kb
Host smart-3e8bd8ee-f9fd-4650-a35e-b877ef41e383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458777594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3458777594
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1401488238
Short name T474
Test name
Test status
Simulation time 77840127 ps
CPU time 1.11 seconds
Started Jul 29 06:22:45 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 217172 kb
Host smart-7530d4d9-5aff-4ac2-b5a4-5ee99ff87878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401488238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1401488238
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3789008609
Short name T234
Test name
Test status
Simulation time 145184776 ps
CPU time 1.25 seconds
Started Jul 29 06:22:47 PM PDT 24
Finished Jul 29 06:22:49 PM PDT 24
Peak memory 219932 kb
Host smart-acf4ce5f-fc5f-4515-a135-ab60cfa30513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789008609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3789008609
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.697822557
Short name T899
Test name
Test status
Simulation time 79189733 ps
CPU time 1.47 seconds
Started Jul 29 06:22:44 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 218672 kb
Host smart-b04e2d49-5ce9-43c2-a4b9-ee54eedffe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697822557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.697822557
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.4048867853
Short name T762
Test name
Test status
Simulation time 144754991 ps
CPU time 1.12 seconds
Started Jul 29 06:22:54 PM PDT 24
Finished Jul 29 06:22:55 PM PDT 24
Peak memory 215692 kb
Host smart-06cf6af5-9d35-4cd5-844c-c42ccf8a5dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048867853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.4048867853
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.1029353624
Short name T641
Test name
Test status
Simulation time 165268225 ps
CPU time 1.34 seconds
Started Jul 29 06:22:48 PM PDT 24
Finished Jul 29 06:22:50 PM PDT 24
Peak memory 219536 kb
Host smart-ce40d359-20f9-4826-adb1-4f4592ce018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029353624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1029353624
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.3767832725
Short name T351
Test name
Test status
Simulation time 201637785 ps
CPU time 1.22 seconds
Started Jul 29 06:22:43 PM PDT 24
Finished Jul 29 06:22:44 PM PDT 24
Peak memory 220664 kb
Host smart-8ed637e5-cd10-4ec6-8a13-ec032101a6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767832725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3767832725
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.3051906299
Short name T961
Test name
Test status
Simulation time 267268599 ps
CPU time 1.47 seconds
Started Jul 29 06:22:51 PM PDT 24
Finished Jul 29 06:22:53 PM PDT 24
Peak memory 219056 kb
Host smart-a3f96bb7-9de2-4999-8035-807882b277b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051906299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3051906299
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.486531170
Short name T542
Test name
Test status
Simulation time 23070135 ps
CPU time 1.19 seconds
Started Jul 29 06:22:50 PM PDT 24
Finished Jul 29 06:22:52 PM PDT 24
Peak memory 219652 kb
Host smart-16c5a19e-593e-4753-a775-687ba202ac1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486531170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.486531170
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.4049344725
Short name T937
Test name
Test status
Simulation time 38103450 ps
CPU time 1.5 seconds
Started Jul 29 06:22:49 PM PDT 24
Finished Jul 29 06:22:51 PM PDT 24
Peak memory 218532 kb
Host smart-e35e1c29-7c2e-4575-8003-938e983b67be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049344725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.4049344725
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.1458909127
Short name T919
Test name
Test status
Simulation time 28248491 ps
CPU time 1.28 seconds
Started Jul 29 06:23:12 PM PDT 24
Finished Jul 29 06:23:14 PM PDT 24
Peak memory 220696 kb
Host smart-481f1a4a-844c-454d-a490-084a51e0f463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458909127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.1458909127
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1856179699
Short name T503
Test name
Test status
Simulation time 63911044 ps
CPU time 1.12 seconds
Started Jul 29 06:22:44 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 218984 kb
Host smart-cdbe273e-55c2-4ca4-ae06-6e69671163b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856179699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1856179699
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2096533261
Short name T192
Test name
Test status
Simulation time 75240549 ps
CPU time 1.16 seconds
Started Jul 29 06:21:28 PM PDT 24
Finished Jul 29 06:21:29 PM PDT 24
Peak memory 218628 kb
Host smart-6f911bc9-cbd4-4f1b-83bb-a897ccf1bbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096533261 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2096533261
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1676849958
Short name T344
Test name
Test status
Simulation time 45723669 ps
CPU time 0.83 seconds
Started Jul 29 06:21:35 PM PDT 24
Finished Jul 29 06:21:35 PM PDT 24
Peak memory 214624 kb
Host smart-38e1c99f-40f5-4b07-bf13-ee19d4339d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676849958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1676849958
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_genbits.1270596514
Short name T373
Test name
Test status
Simulation time 47364820 ps
CPU time 1.1 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 217220 kb
Host smart-d51d9bfe-4a55-4284-a977-8028330bb579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270596514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1270596514
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1667205200
Short name T59
Test name
Test status
Simulation time 59289285 ps
CPU time 0.89 seconds
Started Jul 29 06:21:32 PM PDT 24
Finished Jul 29 06:21:33 PM PDT 24
Peak memory 215320 kb
Host smart-9514c89f-afad-4190-907a-d33907548ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667205200 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1667205200
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1165457949
Short name T323
Test name
Test status
Simulation time 67180152 ps
CPU time 0.88 seconds
Started Jul 29 06:21:31 PM PDT 24
Finished Jul 29 06:21:32 PM PDT 24
Peak memory 215264 kb
Host smart-21bf8deb-bb94-4d4a-a37b-9b53ab8c4056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165457949 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1165457949
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.4099075878
Short name T372
Test name
Test status
Simulation time 132178774 ps
CPU time 3.05 seconds
Started Jul 29 06:21:20 PM PDT 24
Finished Jul 29 06:21:28 PM PDT 24
Peak memory 217160 kb
Host smart-dfe71218-5c54-4fee-9a7b-05c1555b22a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099075878 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.4099075878
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_alert.1998218589
Short name T877
Test name
Test status
Simulation time 61822195 ps
CPU time 1.26 seconds
Started Jul 29 06:22:45 PM PDT 24
Finished Jul 29 06:22:47 PM PDT 24
Peak memory 218720 kb
Host smart-b12a182e-bf73-4035-ae4f-40ef2d4896aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998218589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.1998218589
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1748260994
Short name T399
Test name
Test status
Simulation time 48443751 ps
CPU time 1.6 seconds
Started Jul 29 06:22:45 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 219136 kb
Host smart-556cd665-7f3d-48be-8ed5-b673fc1034b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748260994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1748260994
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.3970293262
Short name T147
Test name
Test status
Simulation time 321887133 ps
CPU time 1.4 seconds
Started Jul 29 06:23:05 PM PDT 24
Finished Jul 29 06:23:07 PM PDT 24
Peak memory 219644 kb
Host smart-a69339d8-1072-4e83-9f7b-fe3fc5aa26be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970293262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3970293262
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.2774764778
Short name T440
Test name
Test status
Simulation time 31866973 ps
CPU time 1.3 seconds
Started Jul 29 06:22:46 PM PDT 24
Finished Jul 29 06:22:47 PM PDT 24
Peak memory 217208 kb
Host smart-56124e2d-331a-408e-880e-ffd41ef4386c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774764778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2774764778
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.2584183883
Short name T618
Test name
Test status
Simulation time 176573149 ps
CPU time 1.21 seconds
Started Jul 29 06:23:03 PM PDT 24
Finished Jul 29 06:23:05 PM PDT 24
Peak memory 218712 kb
Host smart-5dd38b77-ab62-4eac-a8c7-cb880fa28909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584183883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.2584183883
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.2510149638
Short name T467
Test name
Test status
Simulation time 70643704 ps
CPU time 1.31 seconds
Started Jul 29 06:23:07 PM PDT 24
Finished Jul 29 06:23:08 PM PDT 24
Peak memory 217376 kb
Host smart-79a56ae8-5c7f-4a1e-8cae-05bf0b102da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510149638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2510149638
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.4068804507
Short name T108
Test name
Test status
Simulation time 90762355 ps
CPU time 1.2 seconds
Started Jul 29 06:22:50 PM PDT 24
Finished Jul 29 06:22:51 PM PDT 24
Peak memory 218524 kb
Host smart-ce4fb69c-be6a-4259-ac42-f292b27e93f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068804507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.4068804507
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.3996116314
Short name T519
Test name
Test status
Simulation time 34604956 ps
CPU time 1.5 seconds
Started Jul 29 06:22:50 PM PDT 24
Finished Jul 29 06:22:52 PM PDT 24
Peak memory 218692 kb
Host smart-6618274e-1e19-470c-9bf9-925bb3e7a3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996116314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3996116314
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.3731796964
Short name T203
Test name
Test status
Simulation time 23142853 ps
CPU time 1.11 seconds
Started Jul 29 06:23:08 PM PDT 24
Finished Jul 29 06:23:09 PM PDT 24
Peak memory 218824 kb
Host smart-5d6d739c-5e2f-40b3-8fcc-e863930a43a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731796964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3731796964
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/165.edn_alert.442906913
Short name T243
Test name
Test status
Simulation time 94576400 ps
CPU time 1.13 seconds
Started Jul 29 06:23:09 PM PDT 24
Finished Jul 29 06:23:10 PM PDT 24
Peak memory 218312 kb
Host smart-8ef26bd7-ab99-4996-8e35-b8a3faa8dc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442906913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.442906913
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.2848395771
Short name T272
Test name
Test status
Simulation time 61295112 ps
CPU time 2.34 seconds
Started Jul 29 06:22:47 PM PDT 24
Finished Jul 29 06:22:50 PM PDT 24
Peak memory 220088 kb
Host smart-bf3bffef-1680-423a-82c8-290da7536327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848395771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2848395771
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3020080450
Short name T913
Test name
Test status
Simulation time 97488922 ps
CPU time 1.28 seconds
Started Jul 29 06:22:50 PM PDT 24
Finished Jul 29 06:22:51 PM PDT 24
Peak memory 219804 kb
Host smart-ecd93443-c58f-4f9d-a281-34a742afdc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020080450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3020080450
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.3493439983
Short name T306
Test name
Test status
Simulation time 37850795 ps
CPU time 1.37 seconds
Started Jul 29 06:23:10 PM PDT 24
Finished Jul 29 06:23:11 PM PDT 24
Peak memory 217088 kb
Host smart-34d93136-a205-41e2-bd36-0aad4f851b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493439983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3493439983
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.3979819360
Short name T66
Test name
Test status
Simulation time 129713906 ps
CPU time 1.28 seconds
Started Jul 29 06:22:51 PM PDT 24
Finished Jul 29 06:22:52 PM PDT 24
Peak memory 218700 kb
Host smart-2e75ae9d-fe48-4a0a-bb67-d389b9936511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979819360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.3979819360
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2776857119
Short name T767
Test name
Test status
Simulation time 20704732 ps
CPU time 1.05 seconds
Started Jul 29 06:22:56 PM PDT 24
Finished Jul 29 06:22:57 PM PDT 24
Peak memory 217448 kb
Host smart-182185e2-9a52-4560-a607-5c86629b9939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776857119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2776857119
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.1553517160
Short name T694
Test name
Test status
Simulation time 46498814 ps
CPU time 1.28 seconds
Started Jul 29 06:22:49 PM PDT 24
Finished Jul 29 06:22:51 PM PDT 24
Peak memory 219376 kb
Host smart-b2eaea78-cab0-4219-8a98-07658ec1e07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553517160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1553517160
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.2332236196
Short name T886
Test name
Test status
Simulation time 449968884 ps
CPU time 4.26 seconds
Started Jul 29 06:22:50 PM PDT 24
Finished Jul 29 06:22:54 PM PDT 24
Peak memory 220116 kb
Host smart-22ace967-af3c-4a84-8bdd-2003f31eaf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332236196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2332236196
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2278997186
Short name T53
Test name
Test status
Simulation time 91393157 ps
CPU time 1.21 seconds
Started Jul 29 06:22:49 PM PDT 24
Finished Jul 29 06:22:51 PM PDT 24
Peak memory 215968 kb
Host smart-af9ffb8e-6e6b-4185-9884-43a4e1bbae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278997186 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2278997186
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.2761261006
Short name T728
Test name
Test status
Simulation time 65464190 ps
CPU time 1.53 seconds
Started Jul 29 06:22:51 PM PDT 24
Finished Jul 29 06:22:52 PM PDT 24
Peak memory 218860 kb
Host smart-e28e74ab-cbf4-43c3-b904-01eed619a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761261006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2761261006
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.511915121
Short name T167
Test name
Test status
Simulation time 26477588 ps
CPU time 1.22 seconds
Started Jul 29 06:21:26 PM PDT 24
Finished Jul 29 06:21:27 PM PDT 24
Peak memory 219736 kb
Host smart-73dc91f5-4828-41c3-bab0-3949983032fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511915121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.511915121
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3648629008
Short name T413
Test name
Test status
Simulation time 61512431 ps
CPU time 0.82 seconds
Started Jul 29 06:21:30 PM PDT 24
Finished Jul 29 06:21:31 PM PDT 24
Peak memory 206496 kb
Host smart-c7c2ba7e-9d8b-4290-a21d-348595a4e1cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648629008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3648629008
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3413192536
Short name T139
Test name
Test status
Simulation time 16884718 ps
CPU time 0.84 seconds
Started Jul 29 06:21:21 PM PDT 24
Finished Jul 29 06:21:22 PM PDT 24
Peak memory 216196 kb
Host smart-f46fc623-adc2-4d2c-ad12-be2a59a961fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413192536 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3413192536
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.634444975
Short name T442
Test name
Test status
Simulation time 54608358 ps
CPU time 1.13 seconds
Started Jul 29 06:21:34 PM PDT 24
Finished Jul 29 06:21:35 PM PDT 24
Peak memory 216748 kb
Host smart-ebada0c9-319d-43e1-9c1b-c64ff1a4b9e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634444975 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.634444975
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.2619292041
Short name T620
Test name
Test status
Simulation time 30773396 ps
CPU time 0.88 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 218240 kb
Host smart-9a196a2f-bd1f-46a9-8939-5b6aeadcec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619292041 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2619292041
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1223589278
Short name T692
Test name
Test status
Simulation time 96274478 ps
CPU time 1.22 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 218468 kb
Host smart-68d1779d-6092-44d3-aad7-e5074bd8bcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223589278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1223589278
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.542996713
Short name T644
Test name
Test status
Simulation time 38286357 ps
CPU time 1.05 seconds
Started Jul 29 06:21:21 PM PDT 24
Finished Jul 29 06:21:22 PM PDT 24
Peak memory 224064 kb
Host smart-6c8af70a-700d-4339-b707-d188de5e9e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542996713 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.542996713
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2543063120
Short name T482
Test name
Test status
Simulation time 23904466 ps
CPU time 0.91 seconds
Started Jul 29 06:21:31 PM PDT 24
Finished Jul 29 06:21:32 PM PDT 24
Peak memory 215316 kb
Host smart-6424c4ef-9379-446c-aa1e-615dff9311c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543063120 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2543063120
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1278763961
Short name T966
Test name
Test status
Simulation time 185960273 ps
CPU time 1.54 seconds
Started Jul 29 06:21:45 PM PDT 24
Finished Jul 29 06:21:47 PM PDT 24
Peak memory 217500 kb
Host smart-2107c91e-b182-4762-83e4-58e182c1197c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278763961 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1278763961
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3907750800
Short name T466
Test name
Test status
Simulation time 45352518256 ps
CPU time 266.17 seconds
Started Jul 29 06:21:34 PM PDT 24
Finished Jul 29 06:26:00 PM PDT 24
Peak memory 218028 kb
Host smart-5342da05-6121-44d8-84d9-0dc318069eed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907750800 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3907750800
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.3115059507
Short name T646
Test name
Test status
Simulation time 89387861 ps
CPU time 1.2 seconds
Started Jul 29 06:22:54 PM PDT 24
Finished Jul 29 06:22:55 PM PDT 24
Peak memory 220136 kb
Host smart-29074bb9-cad4-4dbb-b8a0-a1eade0c516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115059507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.3115059507
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.3071372668
Short name T31
Test name
Test status
Simulation time 41241196 ps
CPU time 1.4 seconds
Started Jul 29 06:22:49 PM PDT 24
Finished Jul 29 06:22:51 PM PDT 24
Peak memory 217152 kb
Host smart-d457901e-23b4-4d52-8c9a-1896c3b5bfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071372668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3071372668
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.2882945643
Short name T171
Test name
Test status
Simulation time 31025726 ps
CPU time 1.32 seconds
Started Jul 29 06:22:46 PM PDT 24
Finished Jul 29 06:22:47 PM PDT 24
Peak memory 219152 kb
Host smart-83bc71c2-d7f2-44e7-80af-a8512a6403cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882945643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2882945643
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.1526422669
Short name T775
Test name
Test status
Simulation time 33014610 ps
CPU time 1.24 seconds
Started Jul 29 06:22:47 PM PDT 24
Finished Jul 29 06:22:49 PM PDT 24
Peak memory 217216 kb
Host smart-4b52a4a1-e199-4ac2-ab2e-614668576b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526422669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1526422669
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.2195978670
Short name T715
Test name
Test status
Simulation time 63671272 ps
CPU time 1.08 seconds
Started Jul 29 06:22:44 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 219744 kb
Host smart-a54761ed-98f2-4ac6-8a96-e01475c0584a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195978670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.2195978670
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.1680571292
Short name T968
Test name
Test status
Simulation time 58513820 ps
CPU time 1.63 seconds
Started Jul 29 06:22:46 PM PDT 24
Finished Jul 29 06:22:48 PM PDT 24
Peak memory 219940 kb
Host smart-dc1adead-7735-4178-8dc3-c6a383885b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680571292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1680571292
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.1464933963
Short name T869
Test name
Test status
Simulation time 79527361 ps
CPU time 1.08 seconds
Started Jul 29 06:22:55 PM PDT 24
Finished Jul 29 06:22:56 PM PDT 24
Peak memory 220020 kb
Host smart-1504da82-43a9-466b-907e-553d5592e18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464933963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.1464933963
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.188782661
Short name T271
Test name
Test status
Simulation time 68593740 ps
CPU time 1.2 seconds
Started Jul 29 06:22:53 PM PDT 24
Finished Jul 29 06:22:54 PM PDT 24
Peak memory 217220 kb
Host smart-555475aa-c6bc-424d-aa99-a1e6616aec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188782661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.188782661
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.3607279112
Short name T932
Test name
Test status
Simulation time 103522013 ps
CPU time 1.1 seconds
Started Jul 29 06:23:00 PM PDT 24
Finished Jul 29 06:23:02 PM PDT 24
Peak memory 220128 kb
Host smart-589b82aa-2fcc-4c0a-8a1e-2b8bccaeb229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607279112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3607279112
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.1983086123
Short name T691
Test name
Test status
Simulation time 188813798 ps
CPU time 1.06 seconds
Started Jul 29 06:23:02 PM PDT 24
Finished Jul 29 06:23:03 PM PDT 24
Peak memory 219820 kb
Host smart-1778e55b-0ba7-4794-a529-6ccc1e6303a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983086123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1983086123
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.68846583
Short name T781
Test name
Test status
Simulation time 88723099 ps
CPU time 1.22 seconds
Started Jul 29 06:23:01 PM PDT 24
Finished Jul 29 06:23:02 PM PDT 24
Peak memory 218572 kb
Host smart-8348338f-e294-47b9-bf46-a3f11df10e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68846583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.68846583
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.2125112912
Short name T595
Test name
Test status
Simulation time 96010135 ps
CPU time 1.51 seconds
Started Jul 29 06:22:51 PM PDT 24
Finished Jul 29 06:22:53 PM PDT 24
Peak memory 218932 kb
Host smart-ffb4709b-23d3-44a3-89d8-6cf17880f74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125112912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2125112912
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2693426639
Short name T65
Test name
Test status
Simulation time 54042946 ps
CPU time 1.35 seconds
Started Jul 29 06:22:53 PM PDT 24
Finished Jul 29 06:22:54 PM PDT 24
Peak memory 219032 kb
Host smart-b37ba75d-a322-4998-b0d7-48695012425b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693426639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2693426639
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.500227673
Short name T944
Test name
Test status
Simulation time 244774479 ps
CPU time 1.29 seconds
Started Jul 29 06:23:09 PM PDT 24
Finished Jul 29 06:23:10 PM PDT 24
Peak memory 217244 kb
Host smart-8dc8c642-7d1e-4a75-a029-0b5b60189b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500227673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.500227673
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2903391092
Short name T172
Test name
Test status
Simulation time 24925741 ps
CPU time 1.22 seconds
Started Jul 29 06:22:54 PM PDT 24
Finished Jul 29 06:22:56 PM PDT 24
Peak memory 219772 kb
Host smart-b1fc17fb-05c6-4936-9261-70da608ed55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903391092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2903391092
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.1493099718
Short name T969
Test name
Test status
Simulation time 141820585 ps
CPU time 1.8 seconds
Started Jul 29 06:22:50 PM PDT 24
Finished Jul 29 06:22:52 PM PDT 24
Peak memory 218880 kb
Host smart-528dfc3a-49fa-4c61-9c46-fd431915c96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493099718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1493099718
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.747154956
Short name T544
Test name
Test status
Simulation time 26927487 ps
CPU time 1.21 seconds
Started Jul 29 06:22:55 PM PDT 24
Finished Jul 29 06:22:56 PM PDT 24
Peak memory 219244 kb
Host smart-9dcf9db1-e43e-47e5-8cd0-f91547fb11ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747154956 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.747154956
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.4231575801
Short name T910
Test name
Test status
Simulation time 48908435 ps
CPU time 1.91 seconds
Started Jul 29 06:22:50 PM PDT 24
Finished Jul 29 06:22:52 PM PDT 24
Peak memory 220060 kb
Host smart-43f0e855-23dd-4b23-ad97-389de0cdd230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231575801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.4231575801
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.585609551
Short name T928
Test name
Test status
Simulation time 126907582 ps
CPU time 1.2 seconds
Started Jul 29 06:22:51 PM PDT 24
Finished Jul 29 06:22:53 PM PDT 24
Peak memory 221160 kb
Host smart-5c462e45-c6bc-43bc-bcf4-81361350c6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585609551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.585609551
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.11343919
Short name T672
Test name
Test status
Simulation time 53562649 ps
CPU time 1.64 seconds
Started Jul 29 06:23:03 PM PDT 24
Finished Jul 29 06:23:04 PM PDT 24
Peak memory 218696 kb
Host smart-efbdffa3-38f2-4f0a-a147-94830bf68fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11343919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.11343919
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.419604085
Short name T860
Test name
Test status
Simulation time 49476121 ps
CPU time 1.29 seconds
Started Jul 29 06:21:31 PM PDT 24
Finished Jul 29 06:21:32 PM PDT 24
Peak memory 215700 kb
Host smart-e4640769-3841-4764-9eb2-f954391f40bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419604085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.419604085
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.724905605
Short name T787
Test name
Test status
Simulation time 70063237 ps
CPU time 0.97 seconds
Started Jul 29 06:21:31 PM PDT 24
Finished Jul 29 06:21:32 PM PDT 24
Peak memory 214900 kb
Host smart-29c2771b-113a-4652-9cda-049ea62f9852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724905605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.724905605
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_err.569554947
Short name T485
Test name
Test status
Simulation time 81362438 ps
CPU time 0.82 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 218356 kb
Host smart-d3154e42-92e6-4b25-a9a5-7701a2cf1392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569554947 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.569554947
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3385950738
Short name T390
Test name
Test status
Simulation time 41676715 ps
CPU time 1.44 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 218724 kb
Host smart-f802d61a-d09c-4d91-a03e-b3a32b3c89f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385950738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3385950738
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2165095401
Short name T94
Test name
Test status
Simulation time 28558448 ps
CPU time 0.9 seconds
Started Jul 29 06:21:49 PM PDT 24
Finished Jul 29 06:21:50 PM PDT 24
Peak memory 215976 kb
Host smart-5d51fabc-8621-400e-ad38-3c813cf4d935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165095401 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2165095401
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.413389661
Short name T464
Test name
Test status
Simulation time 25993679 ps
CPU time 0.96 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:21:42 PM PDT 24
Peak memory 215268 kb
Host smart-f084e181-ba4a-4e20-8507-422b16acc0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413389661 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.413389661
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2843856952
Short name T71
Test name
Test status
Simulation time 114842601 ps
CPU time 1.64 seconds
Started Jul 29 06:21:32 PM PDT 24
Finished Jul 29 06:21:34 PM PDT 24
Peak memory 218880 kb
Host smart-65c3f6e7-ade8-42fa-97b1-c0104be336a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843856952 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2843856952
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3549405148
Short name T608
Test name
Test status
Simulation time 40573305048 ps
CPU time 452.16 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:29:14 PM PDT 24
Peak memory 217916 kb
Host smart-9d61bc43-1365-46cc-a063-c6aef96adfc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549405148 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3549405148
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.3149772589
Short name T802
Test name
Test status
Simulation time 41715485 ps
CPU time 1.13 seconds
Started Jul 29 06:22:52 PM PDT 24
Finished Jul 29 06:22:54 PM PDT 24
Peak memory 218816 kb
Host smart-138698d5-8644-4f09-bc54-97b9b7385562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149772589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.3149772589
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3148279470
Short name T617
Test name
Test status
Simulation time 122495221 ps
CPU time 1.16 seconds
Started Jul 29 06:23:05 PM PDT 24
Finished Jul 29 06:23:06 PM PDT 24
Peak memory 217228 kb
Host smart-02045c17-3bd6-465d-911c-e53c037e78c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148279470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3148279470
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.4212762428
Short name T942
Test name
Test status
Simulation time 34185709 ps
CPU time 1.32 seconds
Started Jul 29 06:23:12 PM PDT 24
Finished Jul 29 06:23:13 PM PDT 24
Peak memory 221776 kb
Host smart-bc9cfd3c-debb-492f-9db6-d54a6e0ee208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212762428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.4212762428
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.709836223
Short name T698
Test name
Test status
Simulation time 45835503 ps
CPU time 1.5 seconds
Started Jul 29 06:22:54 PM PDT 24
Finished Jul 29 06:22:55 PM PDT 24
Peak memory 217260 kb
Host smart-c0528c8e-b5b5-4e68-ad37-1e2f74c759e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709836223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.709836223
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.214320347
Short name T823
Test name
Test status
Simulation time 65294039 ps
CPU time 1.26 seconds
Started Jul 29 06:22:50 PM PDT 24
Finished Jul 29 06:22:52 PM PDT 24
Peak memory 220296 kb
Host smart-e4fc9d16-273a-4580-8b57-76638f09969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214320347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.214320347
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.1352543905
Short name T631
Test name
Test status
Simulation time 36020552 ps
CPU time 1.58 seconds
Started Jul 29 06:22:51 PM PDT 24
Finished Jul 29 06:22:53 PM PDT 24
Peak memory 218736 kb
Host smart-e4d646d9-1abc-4158-8b80-4b337302fdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352543905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1352543905
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.2119094238
Short name T1
Test name
Test status
Simulation time 85460427 ps
CPU time 1.21 seconds
Started Jul 29 06:22:59 PM PDT 24
Finished Jul 29 06:23:00 PM PDT 24
Peak memory 220204 kb
Host smart-d72f7c4f-bb33-4dac-94ec-0b9080562c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119094238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.2119094238
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.151765961
Short name T800
Test name
Test status
Simulation time 318809609 ps
CPU time 3.83 seconds
Started Jul 29 06:22:58 PM PDT 24
Finished Jul 29 06:23:02 PM PDT 24
Peak memory 218744 kb
Host smart-02fbfefe-df83-4d5a-bf3a-a272b4027814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151765961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.151765961
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.3652816243
Short name T495
Test name
Test status
Simulation time 99406144 ps
CPU time 1.12 seconds
Started Jul 29 06:23:10 PM PDT 24
Finished Jul 29 06:23:11 PM PDT 24
Peak memory 218308 kb
Host smart-d825bbe4-7df8-4005-8471-a3eeeeed9988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652816243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3652816243
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.10539580
Short name T541
Test name
Test status
Simulation time 40804608 ps
CPU time 1.59 seconds
Started Jul 29 06:22:53 PM PDT 24
Finished Jul 29 06:22:54 PM PDT 24
Peak memory 218468 kb
Host smart-d8188e97-0bf7-4ab0-9e91-c8358f7562da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10539580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.10539580
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.2856384333
Short name T163
Test name
Test status
Simulation time 29412899 ps
CPU time 1.32 seconds
Started Jul 29 06:23:28 PM PDT 24
Finished Jul 29 06:23:29 PM PDT 24
Peak memory 215644 kb
Host smart-b166b5e6-d55e-46ac-991d-16bd301b7e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856384333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2856384333
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.3234603554
Short name T610
Test name
Test status
Simulation time 49534764 ps
CPU time 1.94 seconds
Started Jul 29 06:22:54 PM PDT 24
Finished Jul 29 06:22:56 PM PDT 24
Peak memory 218400 kb
Host smart-7bf3e2f9-9872-47ff-9bc3-1c82e5154116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234603554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3234603554
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2007353486
Short name T279
Test name
Test status
Simulation time 28029462 ps
CPU time 1.27 seconds
Started Jul 29 06:22:55 PM PDT 24
Finished Jul 29 06:22:56 PM PDT 24
Peak memory 220832 kb
Host smart-a4246327-a29c-496d-b487-6fcba3bb53b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007353486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2007353486
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/187.edn_alert.1802342035
Short name T793
Test name
Test status
Simulation time 25984813 ps
CPU time 1.21 seconds
Started Jul 29 06:23:19 PM PDT 24
Finished Jul 29 06:23:21 PM PDT 24
Peak memory 219620 kb
Host smart-0078db98-4e57-4516-9d19-dabbd30805e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802342035 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1802342035
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.3641280995
Short name T414
Test name
Test status
Simulation time 43614706 ps
CPU time 1.19 seconds
Started Jul 29 06:23:06 PM PDT 24
Finished Jul 29 06:23:07 PM PDT 24
Peak memory 217784 kb
Host smart-c304f7f7-74f4-400a-bfef-e75043d476bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641280995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3641280995
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.4177327028
Short name T721
Test name
Test status
Simulation time 89135453 ps
CPU time 1.14 seconds
Started Jul 29 06:23:02 PM PDT 24
Finished Jul 29 06:23:04 PM PDT 24
Peak memory 219752 kb
Host smart-f34fea3b-7bf2-4c92-8b5c-65730547431a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177327028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.4177327028
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.1219078132
Short name T731
Test name
Test status
Simulation time 125904857 ps
CPU time 1.41 seconds
Started Jul 29 06:23:06 PM PDT 24
Finished Jul 29 06:23:08 PM PDT 24
Peak memory 219868 kb
Host smart-bfadb62b-3c54-44df-b8c3-bb7a19e3a1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219078132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1219078132
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.4177947499
Short name T642
Test name
Test status
Simulation time 83903291 ps
CPU time 1.1 seconds
Started Jul 29 06:23:12 PM PDT 24
Finished Jul 29 06:23:13 PM PDT 24
Peak memory 219612 kb
Host smart-4eb91d4e-3ad0-4764-92b2-565770230588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177947499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.4177947499
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.3812971165
Short name T307
Test name
Test status
Simulation time 73969088 ps
CPU time 1.33 seconds
Started Jul 29 06:23:06 PM PDT 24
Finished Jul 29 06:23:08 PM PDT 24
Peak memory 218608 kb
Host smart-c945c97e-618a-4605-b98f-334a460fbf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812971165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3812971165
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1651304456
Short name T465
Test name
Test status
Simulation time 36439967 ps
CPU time 1.15 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:21:42 PM PDT 24
Peak memory 219760 kb
Host smart-06f8181a-2896-4d2f-8efb-5946d01a323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651304456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1651304456
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1508343465
Short name T704
Test name
Test status
Simulation time 73940601 ps
CPU time 1.01 seconds
Started Jul 29 06:21:35 PM PDT 24
Finished Jul 29 06:21:36 PM PDT 24
Peak memory 214904 kb
Host smart-21527ebe-349c-48c6-abe2-e3709e50f867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508343465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1508343465
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3363249990
Short name T526
Test name
Test status
Simulation time 22080453 ps
CPU time 0.88 seconds
Started Jul 29 06:21:30 PM PDT 24
Finished Jul 29 06:21:31 PM PDT 24
Peak memory 216060 kb
Host smart-02f0cdf8-8211-4d1d-92d3-d05125b90842
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363249990 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3363249990
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1439733532
Short name T778
Test name
Test status
Simulation time 31592182 ps
CPU time 1.15 seconds
Started Jul 29 06:21:35 PM PDT 24
Finished Jul 29 06:21:36 PM PDT 24
Peak memory 217096 kb
Host smart-aecc2431-f894-4013-949b-ff757057c0ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439733532 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1439733532
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.952518941
Short name T121
Test name
Test status
Simulation time 39612077 ps
CPU time 0.9 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 219584 kb
Host smart-a6d8c864-6faa-4e1c-b57f-d635d33cd50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952518941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.952518941
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1011450068
Short name T668
Test name
Test status
Simulation time 75011580 ps
CPU time 1.13 seconds
Started Jul 29 06:21:33 PM PDT 24
Finished Jul 29 06:21:34 PM PDT 24
Peak memory 217480 kb
Host smart-5ddc74fc-69f6-4edd-8365-706d9b436c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011450068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1011450068
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.4191225641
Short name T477
Test name
Test status
Simulation time 68524517 ps
CPU time 0.93 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 215228 kb
Host smart-b55017fa-a657-4bc9-bb4e-56c01becacf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191225641 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.4191225641
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.837238910
Short name T421
Test name
Test status
Simulation time 200594767 ps
CPU time 0.97 seconds
Started Jul 29 06:21:40 PM PDT 24
Finished Jul 29 06:21:41 PM PDT 24
Peak memory 215352 kb
Host smart-08347810-3125-450c-ba6a-3e3af7879c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837238910 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.837238910
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2608595054
Short name T96
Test name
Test status
Simulation time 455762614 ps
CPU time 4.84 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:49 PM PDT 24
Peak memory 215308 kb
Host smart-05b87c8d-263d-4084-8aa9-e34b89404aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608595054 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2608595054
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/190.edn_genbits.2121327016
Short name T533
Test name
Test status
Simulation time 87570382 ps
CPU time 1.41 seconds
Started Jul 29 06:22:58 PM PDT 24
Finished Jul 29 06:23:00 PM PDT 24
Peak memory 218976 kb
Host smart-955720be-0ba5-428a-9bf0-ee75e90c35f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121327016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2121327016
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.632261969
Short name T737
Test name
Test status
Simulation time 79921179 ps
CPU time 1.14 seconds
Started Jul 29 06:23:02 PM PDT 24
Finished Jul 29 06:23:03 PM PDT 24
Peak memory 220876 kb
Host smart-0bce18ca-74d3-4920-a41b-9c199f11756d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632261969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.632261969
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.2502458917
Short name T975
Test name
Test status
Simulation time 51637908 ps
CPU time 1.36 seconds
Started Jul 29 06:23:23 PM PDT 24
Finished Jul 29 06:23:25 PM PDT 24
Peak memory 219932 kb
Host smart-983cb45f-06c0-42cb-857d-844d8dd65ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502458917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2502458917
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.1925330829
Short name T843
Test name
Test status
Simulation time 28917107 ps
CPU time 1.34 seconds
Started Jul 29 06:23:02 PM PDT 24
Finished Jul 29 06:23:03 PM PDT 24
Peak memory 215816 kb
Host smart-3977d076-22e1-4b5f-b6ed-387901410d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925330829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.1925330829
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.539237494
Short name T316
Test name
Test status
Simulation time 28457781 ps
CPU time 1.25 seconds
Started Jul 29 06:23:12 PM PDT 24
Finished Jul 29 06:23:13 PM PDT 24
Peak memory 217488 kb
Host smart-3a1ec288-3f9c-4a61-8f61-9701ea48d16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539237494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.539237494
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.2048715641
Short name T813
Test name
Test status
Simulation time 80005851 ps
CPU time 1.24 seconds
Started Jul 29 06:23:01 PM PDT 24
Finished Jul 29 06:23:02 PM PDT 24
Peak memory 219508 kb
Host smart-f6ff9c9c-badb-45ba-939d-b454183cc76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048715641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2048715641
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.2353253595
Short name T849
Test name
Test status
Simulation time 32159762 ps
CPU time 1.23 seconds
Started Jul 29 06:23:22 PM PDT 24
Finished Jul 29 06:23:24 PM PDT 24
Peak memory 217360 kb
Host smart-037a2f4f-4827-4f9e-82a2-06cb1635c7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353253595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2353253595
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.237467151
Short name T194
Test name
Test status
Simulation time 81554485 ps
CPU time 1.19 seconds
Started Jul 29 06:22:59 PM PDT 24
Finished Jul 29 06:23:01 PM PDT 24
Peak memory 219604 kb
Host smart-157dd916-1133-4b1a-b4d0-2e8712086509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237467151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.237467151
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.230550985
Short name T62
Test name
Test status
Simulation time 66718910 ps
CPU time 1.16 seconds
Started Jul 29 06:23:08 PM PDT 24
Finished Jul 29 06:23:10 PM PDT 24
Peak memory 215272 kb
Host smart-6530421c-fce0-41b4-9ccf-fdf065c11dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230550985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.230550985
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.1420626640
Short name T675
Test name
Test status
Simulation time 63029261 ps
CPU time 1.26 seconds
Started Jul 29 06:23:27 PM PDT 24
Finished Jul 29 06:23:28 PM PDT 24
Peak memory 217320 kb
Host smart-eaa1c194-eee3-436f-83cc-97000fab986b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420626640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1420626640
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.2605348710
Short name T872
Test name
Test status
Simulation time 43902548 ps
CPU time 1.22 seconds
Started Jul 29 06:22:59 PM PDT 24
Finished Jul 29 06:23:01 PM PDT 24
Peak memory 218636 kb
Host smart-8b90234b-8ac1-4cbd-acc7-8bf08e4cd488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605348710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.2605348710
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.2275393123
Short name T842
Test name
Test status
Simulation time 57435665 ps
CPU time 1.79 seconds
Started Jul 29 06:23:02 PM PDT 24
Finished Jul 29 06:23:04 PM PDT 24
Peak memory 218616 kb
Host smart-0381321f-13f1-4310-a506-407f9d78a7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275393123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2275393123
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.66101871
Short name T478
Test name
Test status
Simulation time 80739287 ps
CPU time 1.36 seconds
Started Jul 29 06:23:26 PM PDT 24
Finished Jul 29 06:23:28 PM PDT 24
Peak memory 220076 kb
Host smart-8bbf996a-3b68-4ab4-8f4a-7b2ea0565379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66101871 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.66101871
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.2437313099
Short name T11
Test name
Test status
Simulation time 30904548 ps
CPU time 1.35 seconds
Started Jul 29 06:23:26 PM PDT 24
Finished Jul 29 06:23:27 PM PDT 24
Peak memory 220100 kb
Host smart-c776aac8-e7ba-417c-960d-ca32ee58b069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437313099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2437313099
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.1056905259
Short name T648
Test name
Test status
Simulation time 48477036 ps
CPU time 1.28 seconds
Started Jul 29 06:23:20 PM PDT 24
Finished Jul 29 06:23:21 PM PDT 24
Peak memory 219840 kb
Host smart-0c81011e-678b-45c4-8118-d502842115f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056905259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.1056905259
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.382581928
Short name T513
Test name
Test status
Simulation time 80549229 ps
CPU time 1.4 seconds
Started Jul 29 06:23:01 PM PDT 24
Finished Jul 29 06:23:03 PM PDT 24
Peak memory 218688 kb
Host smart-529053b5-47bd-42bb-9f5a-56c06d34bcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382581928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.382581928
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1855018176
Short name T190
Test name
Test status
Simulation time 41953041 ps
CPU time 1.1 seconds
Started Jul 29 06:23:16 PM PDT 24
Finished Jul 29 06:23:17 PM PDT 24
Peak memory 218632 kb
Host smart-035b020c-7b61-4b4b-bec3-ec4b5861159f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855018176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1855018176
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2947967933
Short name T335
Test name
Test status
Simulation time 150739134 ps
CPU time 2.7 seconds
Started Jul 29 06:23:27 PM PDT 24
Finished Jul 29 06:23:30 PM PDT 24
Peak memory 220304 kb
Host smart-ed12150d-942e-4870-99da-c73178035c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947967933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2947967933
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2084496186
Short name T579
Test name
Test status
Simulation time 26086768 ps
CPU time 1.3 seconds
Started Jul 29 06:20:50 PM PDT 24
Finished Jul 29 06:20:51 PM PDT 24
Peak memory 218424 kb
Host smart-329db5aa-de51-485a-8874-14b408ebb347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084496186 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2084496186
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3148155619
Short name T848
Test name
Test status
Simulation time 24198190 ps
CPU time 0.93 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:05 PM PDT 24
Peak memory 215156 kb
Host smart-b97770a7-4ad4-40b7-b323-fe00283a77c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148155619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3148155619
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.553801622
Short name T188
Test name
Test status
Simulation time 21565236 ps
CPU time 0.89 seconds
Started Jul 29 06:21:11 PM PDT 24
Finished Jul 29 06:21:12 PM PDT 24
Peak memory 216348 kb
Host smart-cab87aaa-8076-4f2f-8d67-6be007f48dec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553801622 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.553801622
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2711292185
Short name T366
Test name
Test status
Simulation time 27022770 ps
CPU time 1.03 seconds
Started Jul 29 06:21:06 PM PDT 24
Finished Jul 29 06:21:07 PM PDT 24
Peak memory 216860 kb
Host smart-9fca5b3e-8530-4c19-a5b4-a1959a3eadc4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711292185 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2711292185
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2663763804
Short name T628
Test name
Test status
Simulation time 18144528 ps
CPU time 1.01 seconds
Started Jul 29 06:21:00 PM PDT 24
Finished Jul 29 06:21:01 PM PDT 24
Peak memory 218172 kb
Host smart-ebe11eb1-60e6-4115-8ba8-3fdd303c9cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663763804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2663763804
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3324320517
Short name T304
Test name
Test status
Simulation time 496735950 ps
CPU time 4.12 seconds
Started Jul 29 06:20:55 PM PDT 24
Finished Jul 29 06:21:00 PM PDT 24
Peak memory 219388 kb
Host smart-10213e64-7d00-4455-b32c-406650a68fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324320517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3324320517
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3537450159
Short name T80
Test name
Test status
Simulation time 119140547 ps
CPU time 0.79 seconds
Started Jul 29 06:21:04 PM PDT 24
Finished Jul 29 06:21:05 PM PDT 24
Peak memory 215404 kb
Host smart-b9fe6fee-9b46-40e3-95ed-ca1b21d690a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537450159 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3537450159
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2560739087
Short name T76
Test name
Test status
Simulation time 19162068 ps
CPU time 1.02 seconds
Started Jul 29 06:20:59 PM PDT 24
Finished Jul 29 06:21:00 PM PDT 24
Peak memory 207108 kb
Host smart-bf968b8d-5544-4bc0-bc83-bc382a19deea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560739087 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2560739087
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.1175716915
Short name T343
Test name
Test status
Simulation time 18438078 ps
CPU time 0.98 seconds
Started Jul 29 06:20:58 PM PDT 24
Finished Jul 29 06:20:59 PM PDT 24
Peak memory 215228 kb
Host smart-4d5a7809-67ae-4c8b-b735-1a8f9f9dc751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175716915 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1175716915
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.902470597
Short name T535
Test name
Test status
Simulation time 565992556 ps
CPU time 4.18 seconds
Started Jul 29 06:20:53 PM PDT 24
Finished Jul 29 06:20:57 PM PDT 24
Peak memory 215268 kb
Host smart-34de4c0d-8ce0-4c9c-b3e7-4c0623754b1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902470597 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.902470597
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.4202767825
Short name T226
Test name
Test status
Simulation time 59082889186 ps
CPU time 652.29 seconds
Started Jul 29 06:20:53 PM PDT 24
Finished Jul 29 06:31:46 PM PDT 24
Peak memory 223552 kb
Host smart-75161dff-86cc-4035-9820-0927520ac836
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202767825 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.4202767825
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.977215656
Short name T804
Test name
Test status
Simulation time 89453305 ps
CPU time 1.29 seconds
Started Jul 29 06:21:40 PM PDT 24
Finished Jul 29 06:21:41 PM PDT 24
Peak memory 220744 kb
Host smart-15e21a87-ebb8-4e9e-ae24-fa13634f78f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977215656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.977215656
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2436127710
Short name T102
Test name
Test status
Simulation time 188970470 ps
CPU time 0.98 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 206628 kb
Host smart-85564f9c-7711-47a3-8932-4546105cad07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436127710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2436127710
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.638265492
Short name T561
Test name
Test status
Simulation time 102635131 ps
CPU time 0.86 seconds
Started Jul 29 06:21:46 PM PDT 24
Finished Jul 29 06:21:47 PM PDT 24
Peak memory 215988 kb
Host smart-0d2fe9bb-6e02-49c6-8064-aee74fd11a46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638265492 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.638265492
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.4262924522
Short name T173
Test name
Test status
Simulation time 47556781 ps
CPU time 1.11 seconds
Started Jul 29 06:21:31 PM PDT 24
Finished Jul 29 06:21:33 PM PDT 24
Peak memory 219660 kb
Host smart-07f9e47a-9dca-4f1f-bb6f-8255ce5a6266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262924522 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.4262924522
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.523270259
Short name T432
Test name
Test status
Simulation time 31384284 ps
CPU time 1.27 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 218528 kb
Host smart-8b182882-1ac5-4ee8-a29e-f11336cdff3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523270259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.523270259
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_smoke.2866043162
Short name T483
Test name
Test status
Simulation time 40266821 ps
CPU time 0.89 seconds
Started Jul 29 06:21:48 PM PDT 24
Finished Jul 29 06:21:49 PM PDT 24
Peak memory 215224 kb
Host smart-65ffb566-2a16-488b-92cb-ebc55bced13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866043162 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2866043162
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2777607463
Short name T428
Test name
Test status
Simulation time 183263792 ps
CPU time 4.06 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:21:47 PM PDT 24
Peak memory 215296 kb
Host smart-87616d9d-2eb8-473c-b480-90723a3104c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777607463 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2777607463
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.154385587
Short name T232
Test name
Test status
Simulation time 109457433911 ps
CPU time 611.82 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:31:56 PM PDT 24
Peak memory 223696 kb
Host smart-1937127e-3a05-4330-8523-3412916c62da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154385587 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.154385587
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2725807351
Short name T601
Test name
Test status
Simulation time 46942856 ps
CPU time 1.61 seconds
Started Jul 29 06:23:28 PM PDT 24
Finished Jul 29 06:23:30 PM PDT 24
Peak memory 218612 kb
Host smart-47e9c79d-e3da-4169-acb7-84bccad08145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725807351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2725807351
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.744731699
Short name T696
Test name
Test status
Simulation time 43980926 ps
CPU time 1.65 seconds
Started Jul 29 06:23:24 PM PDT 24
Finished Jul 29 06:23:26 PM PDT 24
Peak memory 218548 kb
Host smart-f4090c7b-6e5d-4b7c-9bcc-37665a0b30bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744731699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.744731699
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1132126803
Short name T523
Test name
Test status
Simulation time 273149602 ps
CPU time 1.54 seconds
Started Jul 29 06:23:08 PM PDT 24
Finished Jul 29 06:23:10 PM PDT 24
Peak memory 217332 kb
Host smart-db135599-a891-494d-b8d4-e66b2ebb8a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132126803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1132126803
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2040344085
Short name T472
Test name
Test status
Simulation time 524942347 ps
CPU time 3.23 seconds
Started Jul 29 06:23:27 PM PDT 24
Finished Jul 29 06:23:31 PM PDT 24
Peak memory 220288 kb
Host smart-701117a4-b99b-429e-9a23-2ff29d7e4a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040344085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2040344085
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1020399667
Short name T606
Test name
Test status
Simulation time 35906374 ps
CPU time 1.37 seconds
Started Jul 29 06:23:22 PM PDT 24
Finished Jul 29 06:23:29 PM PDT 24
Peak memory 215304 kb
Host smart-4be6e7e9-a1be-46c6-a7e1-9f19bce059e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020399667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1020399667
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3356214494
Short name T963
Test name
Test status
Simulation time 67112840 ps
CPU time 1.57 seconds
Started Jul 29 06:23:01 PM PDT 24
Finished Jul 29 06:23:03 PM PDT 24
Peak memory 218764 kb
Host smart-2fb755de-744f-4872-8823-f1f0daefb6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356214494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3356214494
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.648199459
Short name T370
Test name
Test status
Simulation time 129444894 ps
CPU time 1.25 seconds
Started Jul 29 06:23:26 PM PDT 24
Finished Jul 29 06:23:27 PM PDT 24
Peak memory 218908 kb
Host smart-51ad8ee4-8a1b-4ee8-a10b-3fe9cbb6dae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648199459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.648199459
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.476683878
Short name T611
Test name
Test status
Simulation time 47944296 ps
CPU time 1.26 seconds
Started Jul 29 06:23:08 PM PDT 24
Finished Jul 29 06:23:10 PM PDT 24
Peak memory 217336 kb
Host smart-fbcc70d9-edc7-43e0-839b-c18cb9ef1915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476683878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.476683878
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.4291621166
Short name T626
Test name
Test status
Simulation time 203610364 ps
CPU time 1.21 seconds
Started Jul 29 06:23:27 PM PDT 24
Finished Jul 29 06:23:29 PM PDT 24
Peak memory 217580 kb
Host smart-86291b0b-de63-4ea5-9c38-d87ac61519a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291621166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.4291621166
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3896478113
Short name T980
Test name
Test status
Simulation time 173209082 ps
CPU time 1.29 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 218576 kb
Host smart-2cfcc12f-ce93-44d6-8b48-55990a15ce2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896478113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3896478113
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.975583774
Short name T922
Test name
Test status
Simulation time 56791227 ps
CPU time 0.96 seconds
Started Jul 29 06:21:34 PM PDT 24
Finished Jul 29 06:21:35 PM PDT 24
Peak memory 215096 kb
Host smart-85d6d206-3ac2-49e8-bc7c-6d638a50da74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975583774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.975583774
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3140934602
Short name T739
Test name
Test status
Simulation time 26757866 ps
CPU time 0.84 seconds
Started Jul 29 06:21:34 PM PDT 24
Finished Jul 29 06:21:35 PM PDT 24
Peak memory 215928 kb
Host smart-d4ac9da5-1c56-45ce-8ee4-e4abf40688d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140934602 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3140934602
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2880941173
Short name T73
Test name
Test status
Simulation time 49027695 ps
CPU time 1.06 seconds
Started Jul 29 06:21:39 PM PDT 24
Finished Jul 29 06:21:40 PM PDT 24
Peak memory 218600 kb
Host smart-f45e7dec-d353-4781-a904-78b5c0c5d3c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880941173 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2880941173
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.4230139873
Short name T816
Test name
Test status
Simulation time 19663596 ps
CPU time 1.04 seconds
Started Jul 29 06:21:39 PM PDT 24
Finished Jul 29 06:21:40 PM PDT 24
Peak memory 219760 kb
Host smart-87528b9f-7c08-43ab-b901-0f32a5442894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230139873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.4230139873
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3181406604
Short name T365
Test name
Test status
Simulation time 25527225 ps
CPU time 1.17 seconds
Started Jul 29 06:21:48 PM PDT 24
Finished Jul 29 06:21:49 PM PDT 24
Peak memory 218708 kb
Host smart-3c4063af-5ab7-47d5-b6fe-62c7551d7d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181406604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3181406604
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2439108928
Short name T401
Test name
Test status
Simulation time 84996034 ps
CPU time 0.81 seconds
Started Jul 29 06:21:35 PM PDT 24
Finished Jul 29 06:21:36 PM PDT 24
Peak memory 215172 kb
Host smart-e2f54c6c-f692-46b3-86a0-bf78d443180d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439108928 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2439108928
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3139954275
Short name T54
Test name
Test status
Simulation time 29881042 ps
CPU time 0.93 seconds
Started Jul 29 06:21:38 PM PDT 24
Finished Jul 29 06:21:43 PM PDT 24
Peak memory 215260 kb
Host smart-ead00ae8-4051-495a-8bd9-c07d9625c2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139954275 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3139954275
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3957475037
Short name T433
Test name
Test status
Simulation time 542415145 ps
CPU time 5.19 seconds
Started Jul 29 06:21:40 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 215300 kb
Host smart-b42b9cff-cd55-415e-bcfe-738b957341d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957475037 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3957475037
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3703718735
Short name T669
Test name
Test status
Simulation time 87689211219 ps
CPU time 1278.91 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:43:04 PM PDT 24
Peak memory 222800 kb
Host smart-86fdc9e9-3614-4515-9355-f2f1d4bb4595
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703718735 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3703718735
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.425544807
Short name T591
Test name
Test status
Simulation time 52205842 ps
CPU time 0.94 seconds
Started Jul 29 06:22:59 PM PDT 24
Finished Jul 29 06:23:00 PM PDT 24
Peak memory 217540 kb
Host smart-e458e39a-26e4-4fd5-bb10-70ffd43cfe57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425544807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.425544807
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.4221893931
Short name T900
Test name
Test status
Simulation time 68818771 ps
CPU time 1.26 seconds
Started Jul 29 06:23:16 PM PDT 24
Finished Jul 29 06:23:18 PM PDT 24
Peak memory 217488 kb
Host smart-0ab88bf5-c79d-480d-8c73-9bf467455dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221893931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.4221893931
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1297847598
Short name T965
Test name
Test status
Simulation time 57581002 ps
CPU time 1.41 seconds
Started Jul 29 06:23:14 PM PDT 24
Finished Jul 29 06:23:15 PM PDT 24
Peak memory 218480 kb
Host smart-935f137a-3aae-4303-8240-2323e6bbd65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297847598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1297847598
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3544683049
Short name T914
Test name
Test status
Simulation time 95262220 ps
CPU time 1.52 seconds
Started Jul 29 06:23:08 PM PDT 24
Finished Jul 29 06:23:10 PM PDT 24
Peak memory 220092 kb
Host smart-f05abf5f-ece3-491d-9d8f-2f0a72da4060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544683049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3544683049
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2679207643
Short name T751
Test name
Test status
Simulation time 191609224 ps
CPU time 1.21 seconds
Started Jul 29 06:23:26 PM PDT 24
Finished Jul 29 06:23:27 PM PDT 24
Peak memory 217200 kb
Host smart-9ccc09d9-693c-4dff-b45f-8712c4314db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679207643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2679207643
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3222924277
Short name T679
Test name
Test status
Simulation time 44394152 ps
CPU time 1.46 seconds
Started Jul 29 06:23:14 PM PDT 24
Finished Jul 29 06:23:16 PM PDT 24
Peak memory 218580 kb
Host smart-66a10757-ccb8-4c86-8032-e5dd88c22b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222924277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3222924277
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2428629234
Short name T950
Test name
Test status
Simulation time 77413600 ps
CPU time 1.22 seconds
Started Jul 29 06:23:19 PM PDT 24
Finished Jul 29 06:23:21 PM PDT 24
Peak memory 218844 kb
Host smart-ceb8fcda-5bb1-46fc-804e-975ff34e6bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428629234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2428629234
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3473705987
Short name T720
Test name
Test status
Simulation time 57825949 ps
CPU time 1.09 seconds
Started Jul 29 06:23:18 PM PDT 24
Finished Jul 29 06:23:19 PM PDT 24
Peak memory 217420 kb
Host smart-4824261e-fab6-4e69-99d1-76fcfa7946d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473705987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3473705987
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2800026827
Short name T887
Test name
Test status
Simulation time 43420636 ps
CPU time 1.35 seconds
Started Jul 29 06:22:59 PM PDT 24
Finished Jul 29 06:23:01 PM PDT 24
Peak memory 218616 kb
Host smart-87d3525e-971c-4237-890d-0e7d2f12ed49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800026827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2800026827
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3561844998
Short name T870
Test name
Test status
Simulation time 19633237 ps
CPU time 1.07 seconds
Started Jul 29 06:23:08 PM PDT 24
Finished Jul 29 06:23:09 PM PDT 24
Peak memory 219684 kb
Host smart-738bfe55-3fbb-485c-a4e7-be55795f0299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561844998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3561844998
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.638693587
Short name T406
Test name
Test status
Simulation time 27286539 ps
CPU time 1.27 seconds
Started Jul 29 06:21:39 PM PDT 24
Finished Jul 29 06:21:41 PM PDT 24
Peak memory 218680 kb
Host smart-1736e4a4-10b6-486c-9f16-9b398afe8e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638693587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.638693587
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1773300442
Short name T371
Test name
Test status
Simulation time 25704562 ps
CPU time 0.92 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:21:43 PM PDT 24
Peak memory 215064 kb
Host smart-e650008b-3e0d-4b19-b860-5c8d99024ea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773300442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1773300442
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3603780413
Short name T547
Test name
Test status
Simulation time 11232852 ps
CPU time 0.88 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 215912 kb
Host smart-baeeb3da-32e7-4d46-82cb-85b19a72440d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603780413 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3603780413
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.3316260776
Short name T729
Test name
Test status
Simulation time 33441470 ps
CPU time 1.06 seconds
Started Jul 29 06:21:45 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 218432 kb
Host smart-fa7cf911-98ad-4531-a60f-0e79b0b3a2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316260776 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3316260776
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3112037910
Short name T562
Test name
Test status
Simulation time 32993049 ps
CPU time 1.28 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 219960 kb
Host smart-7f0bbf9c-4ba0-42d9-a7b4-da3d76098283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112037910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3112037910
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2834212874
Short name T61
Test name
Test status
Simulation time 26601868 ps
CPU time 0.94 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 215400 kb
Host smart-0785cb5b-822a-4c5f-b9a1-0148dc69a456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834212874 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2834212874
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3005031119
Short name T716
Test name
Test status
Simulation time 17044385 ps
CPU time 1.01 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 207072 kb
Host smart-4324bcef-6644-4956-8f0c-443c4218b355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005031119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3005031119
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3110657642
Short name T978
Test name
Test status
Simulation time 210594293 ps
CPU time 4.51 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:21:47 PM PDT 24
Peak memory 215464 kb
Host smart-2b7eb687-45b2-4dad-a564-704d72fcedf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110657642 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3110657642
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3019720508
Short name T846
Test name
Test status
Simulation time 48684372952 ps
CPU time 190.51 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:24:51 PM PDT 24
Peak memory 223620 kb
Host smart-08ccf69e-66d5-41c3-9331-ecb785fb90da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019720508 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3019720508
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1662759790
Short name T411
Test name
Test status
Simulation time 39493763 ps
CPU time 1.51 seconds
Started Jul 29 06:23:29 PM PDT 24
Finished Jul 29 06:23:31 PM PDT 24
Peak memory 218324 kb
Host smart-ff2ca2ac-4ec7-4b8c-865a-7a8bd13c1d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662759790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1662759790
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3914622465
Short name T724
Test name
Test status
Simulation time 68767779 ps
CPU time 1.15 seconds
Started Jul 29 06:23:27 PM PDT 24
Finished Jul 29 06:23:28 PM PDT 24
Peak memory 217424 kb
Host smart-bba7ecfe-8755-4d4f-8d20-ed4ca6754b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914622465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3914622465
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2853864602
Short name T242
Test name
Test status
Simulation time 311668211 ps
CPU time 3.9 seconds
Started Jul 29 06:23:14 PM PDT 24
Finished Jul 29 06:23:18 PM PDT 24
Peak memory 220088 kb
Host smart-7f393f14-e3aa-464f-a266-40aa2c0ee2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853864602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2853864602
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2147162780
Short name T269
Test name
Test status
Simulation time 35269090 ps
CPU time 1.04 seconds
Started Jul 29 06:23:27 PM PDT 24
Finished Jul 29 06:23:28 PM PDT 24
Peak memory 217644 kb
Host smart-c3f21fcb-1072-45eb-a9a3-77df0ca55289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147162780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2147162780
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.4158929820
Short name T548
Test name
Test status
Simulation time 426678489 ps
CPU time 3.11 seconds
Started Jul 29 06:23:28 PM PDT 24
Finished Jul 29 06:23:31 PM PDT 24
Peak memory 219828 kb
Host smart-8c142a25-8c13-41e9-b870-bdb6519754ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158929820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.4158929820
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.819748889
Short name T815
Test name
Test status
Simulation time 65111884 ps
CPU time 1.46 seconds
Started Jul 29 06:23:31 PM PDT 24
Finished Jul 29 06:23:33 PM PDT 24
Peak memory 218620 kb
Host smart-e5afa825-34a6-43ab-88de-5858ded25f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819748889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.819748889
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2552268742
Short name T409
Test name
Test status
Simulation time 102829481 ps
CPU time 1.14 seconds
Started Jul 29 06:23:26 PM PDT 24
Finished Jul 29 06:23:27 PM PDT 24
Peak memory 217408 kb
Host smart-8da39161-5390-41dd-9439-c024d5f91236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552268742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2552268742
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.4235020877
Short name T320
Test name
Test status
Simulation time 65151233 ps
CPU time 1.53 seconds
Started Jul 29 06:23:30 PM PDT 24
Finished Jul 29 06:23:32 PM PDT 24
Peak memory 218740 kb
Host smart-c608957e-09c7-4da7-85ee-d20fd22b98a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235020877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.4235020877
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2479883708
Short name T417
Test name
Test status
Simulation time 83248445 ps
CPU time 1.29 seconds
Started Jul 29 06:23:07 PM PDT 24
Finished Jul 29 06:23:09 PM PDT 24
Peak memory 217448 kb
Host smart-f66a0020-a585-449c-9cb6-e1e86954a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479883708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2479883708
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.774733023
Short name T789
Test name
Test status
Simulation time 49007543 ps
CPU time 1.47 seconds
Started Jul 29 06:23:25 PM PDT 24
Finished Jul 29 06:23:27 PM PDT 24
Peak memory 220156 kb
Host smart-0bf1c3c8-dded-44bd-b186-71ccd8f98ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774733023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.774733023
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.305234477
Short name T268
Test name
Test status
Simulation time 25616282 ps
CPU time 1.22 seconds
Started Jul 29 06:21:36 PM PDT 24
Finished Jul 29 06:21:37 PM PDT 24
Peak memory 218696 kb
Host smart-a7b847fe-7824-4179-b59d-3f5f7add48f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305234477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.305234477
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2736609624
Short name T447
Test name
Test status
Simulation time 27498997 ps
CPU time 0.95 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 206764 kb
Host smart-dc56f2d2-45d2-4a71-bb2d-4d67a415f04e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736609624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2736609624
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.4209870155
Short name T974
Test name
Test status
Simulation time 75844377 ps
CPU time 0.9 seconds
Started Jul 29 06:21:35 PM PDT 24
Finished Jul 29 06:21:36 PM PDT 24
Peak memory 216204 kb
Host smart-a752be34-de84-4602-81b7-54e0201b9fba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209870155 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.4209870155
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3626931657
Short name T136
Test name
Test status
Simulation time 59971837 ps
CPU time 1.16 seconds
Started Jul 29 06:21:49 PM PDT 24
Finished Jul 29 06:21:50 PM PDT 24
Peak memory 216636 kb
Host smart-99a131c0-2d3e-4f29-92b8-dec33580a54a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626931657 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3626931657
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3904299890
Short name T673
Test name
Test status
Simulation time 18436261 ps
CPU time 1.02 seconds
Started Jul 29 06:21:45 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 218620 kb
Host smart-cd4d27fd-86ea-48a0-a238-d714554bc5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904299890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3904299890
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1806808406
Short name T33
Test name
Test status
Simulation time 81941721 ps
CPU time 1.53 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:21:43 PM PDT 24
Peak memory 218760 kb
Host smart-26b13c9a-4296-474a-bc29-73f8df8491b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806808406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1806808406
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3313098864
Short name T651
Test name
Test status
Simulation time 21876352 ps
CPU time 1.04 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:21:42 PM PDT 24
Peak memory 215236 kb
Host smart-c24110c7-5951-4a8e-93eb-f26a393e8b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313098864 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3313098864
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3443738738
Short name T971
Test name
Test status
Simulation time 44276519 ps
CPU time 0.93 seconds
Started Jul 29 06:21:35 PM PDT 24
Finished Jul 29 06:21:37 PM PDT 24
Peak memory 215288 kb
Host smart-ba140944-71c8-4cb6-8aab-d2104b7dd1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443738738 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3443738738
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3098471802
Short name T338
Test name
Test status
Simulation time 107982476 ps
CPU time 1.6 seconds
Started Jul 29 06:21:30 PM PDT 24
Finished Jul 29 06:21:32 PM PDT 24
Peak memory 217504 kb
Host smart-8b50f78f-5ad3-4bcc-b3a4-635af30f0bd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098471802 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3098471802
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.741385186
Short name T422
Test name
Test status
Simulation time 181893605918 ps
CPU time 1165.49 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:41:09 PM PDT 24
Peak memory 223528 kb
Host smart-b9dd3901-f02a-41cb-adad-8ed9ab3057a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741385186 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.741385186
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2404822567
Short name T314
Test name
Test status
Simulation time 248433443 ps
CPU time 1.88 seconds
Started Jul 29 06:23:06 PM PDT 24
Finished Jul 29 06:23:07 PM PDT 24
Peak memory 218764 kb
Host smart-7df2cd42-bffd-4f4a-bf14-2a4d9e4dccf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404822567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2404822567
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2325030071
Short name T321
Test name
Test status
Simulation time 38817441 ps
CPU time 1.38 seconds
Started Jul 29 06:23:31 PM PDT 24
Finished Jul 29 06:23:33 PM PDT 24
Peak memory 218632 kb
Host smart-d0fc9a05-ae79-4591-b6c9-61d6bc5cb49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325030071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2325030071
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.910392550
Short name T420
Test name
Test status
Simulation time 59824516 ps
CPU time 1.32 seconds
Started Jul 29 06:23:09 PM PDT 24
Finished Jul 29 06:23:10 PM PDT 24
Peak memory 217320 kb
Host smart-df7e031f-5b8c-4220-81fc-b41b263f90cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910392550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.910392550
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3395732707
Short name T345
Test name
Test status
Simulation time 43014371 ps
CPU time 1.46 seconds
Started Jul 29 06:23:21 PM PDT 24
Finished Jul 29 06:23:23 PM PDT 24
Peak memory 218464 kb
Host smart-353f9563-ab3f-45bc-8865-9f3224a51a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395732707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3395732707
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3085713076
Short name T41
Test name
Test status
Simulation time 54631303 ps
CPU time 1.11 seconds
Started Jul 29 06:23:14 PM PDT 24
Finished Jul 29 06:23:15 PM PDT 24
Peak memory 215312 kb
Host smart-edbf42e8-650f-47d8-ab43-895b78e7cacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085713076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3085713076
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2185601421
Short name T334
Test name
Test status
Simulation time 101725379 ps
CPU time 0.98 seconds
Started Jul 29 06:23:19 PM PDT 24
Finished Jul 29 06:23:20 PM PDT 24
Peak memory 217424 kb
Host smart-94f320d1-935b-4511-80da-c437b4901781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185601421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2185601421
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3310004241
Short name T313
Test name
Test status
Simulation time 44631735 ps
CPU time 1.54 seconds
Started Jul 29 06:23:27 PM PDT 24
Finished Jul 29 06:23:29 PM PDT 24
Peak memory 218688 kb
Host smart-61b85b6c-8e59-4930-88cc-d80801a66cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310004241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3310004241
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3335706456
Short name T840
Test name
Test status
Simulation time 47342097 ps
CPU time 1.83 seconds
Started Jul 29 06:23:30 PM PDT 24
Finished Jul 29 06:23:32 PM PDT 24
Peak memory 218808 kb
Host smart-382dc60b-2eff-4177-8684-3aba0f6e94d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335706456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3335706456
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1316270742
Short name T687
Test name
Test status
Simulation time 55871030 ps
CPU time 1.9 seconds
Started Jul 29 06:23:30 PM PDT 24
Finished Jul 29 06:23:32 PM PDT 24
Peak memory 219576 kb
Host smart-7edea8c6-087b-42e2-97f7-b9e333260123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316270742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1316270742
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3665080595
Short name T630
Test name
Test status
Simulation time 61432243 ps
CPU time 1.15 seconds
Started Jul 29 06:23:35 PM PDT 24
Finished Jul 29 06:23:36 PM PDT 24
Peak memory 217304 kb
Host smart-4eadc298-5c77-46d0-b510-bc072b3cd3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665080595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3665080595
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.826954017
Short name T405
Test name
Test status
Simulation time 37510385 ps
CPU time 1.34 seconds
Started Jul 29 06:21:36 PM PDT 24
Finished Jul 29 06:21:37 PM PDT 24
Peak memory 219672 kb
Host smart-58d5be00-e7ed-4a0b-bc29-351468d298c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826954017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.826954017
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3259254656
Short name T515
Test name
Test status
Simulation time 40528323 ps
CPU time 0.98 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:21:43 PM PDT 24
Peak memory 214928 kb
Host smart-2f0f6315-c149-4688-a24d-b4f9925c0c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259254656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3259254656
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2392964662
Short name T215
Test name
Test status
Simulation time 13855455 ps
CPU time 0.92 seconds
Started Jul 29 06:21:31 PM PDT 24
Finished Jul 29 06:21:32 PM PDT 24
Peak memory 216460 kb
Host smart-ddc7a9d7-ec03-4582-a529-2b84fc29a42c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392964662 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2392964662
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1374261303
Short name T166
Test name
Test status
Simulation time 44766628 ps
CPU time 1.38 seconds
Started Jul 29 06:21:46 PM PDT 24
Finished Jul 29 06:21:48 PM PDT 24
Peak memory 215608 kb
Host smart-3f6ec8b7-5750-4f5e-9a6c-749a3f6e2fd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374261303 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1374261303
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.4291545222
Short name T156
Test name
Test status
Simulation time 77042854 ps
CPU time 1.04 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:21:43 PM PDT 24
Peak memory 229372 kb
Host smart-ad86313e-e7e7-4b0b-ad7d-eae840ef8410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291545222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.4291545222
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.603567890
Short name T622
Test name
Test status
Simulation time 86090084 ps
CPU time 1.88 seconds
Started Jul 29 06:21:36 PM PDT 24
Finished Jul 29 06:21:38 PM PDT 24
Peak memory 218952 kb
Host smart-80e6eae7-c483-4480-aa04-a92853cd04a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603567890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.603567890
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2900573042
Short name T888
Test name
Test status
Simulation time 37130356 ps
CPU time 1.04 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 224204 kb
Host smart-ce867c38-84db-4fff-93aa-ec907349e59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900573042 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2900573042
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.4239123259
Short name T917
Test name
Test status
Simulation time 17600155 ps
CPU time 1 seconds
Started Jul 29 06:21:38 PM PDT 24
Finished Jul 29 06:21:39 PM PDT 24
Peak memory 215236 kb
Host smart-02618c63-3b6c-467d-9dbc-9eb05ed2fedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239123259 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.4239123259
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.561462765
Short name T5
Test name
Test status
Simulation time 77806116 ps
CPU time 1.27 seconds
Started Jul 29 06:21:37 PM PDT 24
Finished Jul 29 06:21:38 PM PDT 24
Peak memory 207236 kb
Host smart-b774c293-6249-4829-80e0-c7d5decf48b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561462765 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.561462765
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/242.edn_genbits.3799040117
Short name T746
Test name
Test status
Simulation time 67981263 ps
CPU time 1.13 seconds
Started Jul 29 06:23:20 PM PDT 24
Finished Jul 29 06:23:21 PM PDT 24
Peak memory 217380 kb
Host smart-cd8c289d-8724-4e26-9de9-d15806671522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799040117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3799040117
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3147429160
Short name T44
Test name
Test status
Simulation time 60280813 ps
CPU time 1.45 seconds
Started Jul 29 06:23:14 PM PDT 24
Finished Jul 29 06:23:16 PM PDT 24
Peak memory 217388 kb
Host smart-2c6a6272-2f83-4bb0-bbcf-064e6a87209e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147429160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3147429160
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2268222407
Short name T821
Test name
Test status
Simulation time 80280039 ps
CPU time 2.54 seconds
Started Jul 29 06:23:25 PM PDT 24
Finished Jul 29 06:23:28 PM PDT 24
Peak memory 219932 kb
Host smart-a8c02ecf-e232-441b-8743-763f355794dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268222407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2268222407
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1737352416
Short name T662
Test name
Test status
Simulation time 245958716 ps
CPU time 1.09 seconds
Started Jul 29 06:23:28 PM PDT 24
Finished Jul 29 06:23:29 PM PDT 24
Peak memory 217332 kb
Host smart-899630d6-d0f4-4069-9f77-fc6e710fe6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737352416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1737352416
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3476539002
Short name T380
Test name
Test status
Simulation time 93459022 ps
CPU time 1.34 seconds
Started Jul 29 06:23:14 PM PDT 24
Finished Jul 29 06:23:16 PM PDT 24
Peak memory 219096 kb
Host smart-b10def19-5a27-45e7-9581-e1678430e223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476539002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3476539002
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3532563151
Short name T350
Test name
Test status
Simulation time 75254200 ps
CPU time 1.12 seconds
Started Jul 29 06:23:28 PM PDT 24
Finished Jul 29 06:23:30 PM PDT 24
Peak memory 217172 kb
Host smart-b84b159f-567b-4558-8a6c-31606ebd7346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532563151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3532563151
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2314585899
Short name T865
Test name
Test status
Simulation time 50546960 ps
CPU time 1.26 seconds
Started Jul 29 06:23:07 PM PDT 24
Finished Jul 29 06:23:08 PM PDT 24
Peak memory 218508 kb
Host smart-561a7693-fc65-4503-8826-4143420ad4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314585899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2314585899
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3447885522
Short name T921
Test name
Test status
Simulation time 64514962 ps
CPU time 1.18 seconds
Started Jul 29 06:21:35 PM PDT 24
Finished Jul 29 06:21:36 PM PDT 24
Peak memory 220432 kb
Host smart-fe237eba-dc74-4efd-9c0f-4604fbf16c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447885522 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3447885522
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.153605336
Short name T402
Test name
Test status
Simulation time 19738747 ps
CPU time 1 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:21:43 PM PDT 24
Peak memory 206748 kb
Host smart-2a4ff813-0bf3-4599-b7c5-4effdbe56408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153605336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.153605336
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2427255058
Short name T670
Test name
Test status
Simulation time 39078801 ps
CPU time 0.88 seconds
Started Jul 29 06:21:37 PM PDT 24
Finished Jul 29 06:21:43 PM PDT 24
Peak memory 215332 kb
Host smart-d8c1c8f4-17e3-4434-bdaf-68290c952808
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427255058 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2427255058
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1429199142
Short name T280
Test name
Test status
Simulation time 73112934 ps
CPU time 1.06 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 218200 kb
Host smart-1e6b8717-24b1-4b8f-bf1f-59b72b4cede8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429199142 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1429199142
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2642253809
Short name T820
Test name
Test status
Simulation time 24622842 ps
CPU time 0.92 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 218324 kb
Host smart-4ac11643-5bd2-42f0-97a2-f87a604aef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642253809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2642253809
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.390079722
Short name T415
Test name
Test status
Simulation time 45898128 ps
CPU time 1.96 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:21:43 PM PDT 24
Peak memory 220316 kb
Host smart-f97fd069-6a82-41dc-aee4-27449600eaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390079722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.390079722
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_smoke.3301592624
Short name T436
Test name
Test status
Simulation time 21870748 ps
CPU time 0.98 seconds
Started Jul 29 06:21:52 PM PDT 24
Finished Jul 29 06:21:53 PM PDT 24
Peak memory 215276 kb
Host smart-ae342df5-4cc0-4e73-a573-7adcc3c04d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301592624 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3301592624
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.4028791138
Short name T948
Test name
Test status
Simulation time 366083762 ps
CPU time 2.65 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 217196 kb
Host smart-9bdcba23-3b9c-438a-adbb-b4672e6e49de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028791138 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.4028791138
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3337558443
Short name T511
Test name
Test status
Simulation time 57457580259 ps
CPU time 1293.15 seconds
Started Jul 29 06:21:45 PM PDT 24
Finished Jul 29 06:43:18 PM PDT 24
Peak memory 220872 kb
Host smart-c5adf509-9a92-4ec0-8fa5-e343d79463c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337558443 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3337558443
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2888065293
Short name T602
Test name
Test status
Simulation time 64544234 ps
CPU time 1.13 seconds
Started Jul 29 06:23:31 PM PDT 24
Finished Jul 29 06:23:32 PM PDT 24
Peak memory 217196 kb
Host smart-4a7b7156-1331-41ee-b0fa-8c697a9558a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888065293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2888065293
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2066699693
Short name T985
Test name
Test status
Simulation time 56839758 ps
CPU time 2.06 seconds
Started Jul 29 06:23:23 PM PDT 24
Finished Jul 29 06:23:26 PM PDT 24
Peak memory 218412 kb
Host smart-fd93c0d3-606f-4dcd-91fd-84c92b86334e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066699693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2066699693
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.386343961
Short name T862
Test name
Test status
Simulation time 33049538 ps
CPU time 1.41 seconds
Started Jul 29 06:23:21 PM PDT 24
Finished Jul 29 06:23:23 PM PDT 24
Peak memory 217644 kb
Host smart-09b10d14-d99a-42af-aaf7-bd38252646fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386343961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.386343961
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.212147101
Short name T906
Test name
Test status
Simulation time 52096683 ps
CPU time 1.59 seconds
Started Jul 29 06:23:14 PM PDT 24
Finished Jul 29 06:23:16 PM PDT 24
Peak memory 217432 kb
Host smart-70c7ff5b-ac05-4937-87d6-ac3899a80ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212147101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.212147101
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2213819324
Short name T386
Test name
Test status
Simulation time 35108325 ps
CPU time 1.47 seconds
Started Jul 29 06:23:06 PM PDT 24
Finished Jul 29 06:23:08 PM PDT 24
Peak memory 217584 kb
Host smart-26785a00-6874-422e-beae-c2be9ed83a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213819324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2213819324
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.4081388383
Short name T752
Test name
Test status
Simulation time 75251411 ps
CPU time 1.61 seconds
Started Jul 29 06:23:21 PM PDT 24
Finished Jul 29 06:23:23 PM PDT 24
Peak memory 218704 kb
Host smart-36550893-fd0a-450e-8599-dc17a8bb4b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081388383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.4081388383
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1035164217
Short name T699
Test name
Test status
Simulation time 34221648 ps
CPU time 1.34 seconds
Started Jul 29 06:23:18 PM PDT 24
Finished Jul 29 06:23:19 PM PDT 24
Peak memory 219956 kb
Host smart-0b942e70-e754-4c11-9cd8-fe63e3ce4c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035164217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1035164217
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2319235079
Short name T983
Test name
Test status
Simulation time 40717859 ps
CPU time 1.4 seconds
Started Jul 29 06:23:23 PM PDT 24
Finished Jul 29 06:23:24 PM PDT 24
Peak memory 218552 kb
Host smart-2c79abef-e738-4ad8-89cc-92e0fa3ee566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319235079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2319235079
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.378036797
Short name T723
Test name
Test status
Simulation time 260735838 ps
CPU time 1.24 seconds
Started Jul 29 06:23:21 PM PDT 24
Finished Jul 29 06:23:22 PM PDT 24
Peak memory 217472 kb
Host smart-e3507570-f8e7-498c-92bd-96eb24a34f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378036797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.378036797
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1742340998
Short name T346
Test name
Test status
Simulation time 45410461 ps
CPU time 1.68 seconds
Started Jul 29 06:23:29 PM PDT 24
Finished Jul 29 06:23:31 PM PDT 24
Peak memory 218248 kb
Host smart-5aa71152-d2e3-4c51-98f9-b1408a52760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742340998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1742340998
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3659366976
Short name T42
Test name
Test status
Simulation time 66034335 ps
CPU time 1.19 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:21:43 PM PDT 24
Peak memory 220380 kb
Host smart-efc28f07-cbd3-47dc-9b98-5d56b30942b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659366976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3659366976
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2601564072
Short name T635
Test name
Test status
Simulation time 79221756 ps
CPU time 1 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 206900 kb
Host smart-69027fde-da96-4f1f-a338-7b8636a3767f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601564072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2601564072
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2357321204
Short name T123
Test name
Test status
Simulation time 170493714 ps
CPU time 0.85 seconds
Started Jul 29 06:21:38 PM PDT 24
Finished Jul 29 06:21:39 PM PDT 24
Peak memory 216216 kb
Host smart-c04e1381-0054-46a4-90b4-2e0e7b6e1d88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357321204 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2357321204
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.4046613105
Short name T517
Test name
Test status
Simulation time 32907849 ps
CPU time 0.99 seconds
Started Jul 29 06:21:37 PM PDT 24
Finished Jul 29 06:21:38 PM PDT 24
Peak memory 216880 kb
Host smart-492208ee-c539-4f38-895c-c466b3bdab76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046613105 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.4046613105
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3451630550
Short name T206
Test name
Test status
Simulation time 23924264 ps
CPU time 1.1 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 229596 kb
Host smart-a83d0c8c-3517-47fb-8e65-b15e2d45c8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451630550 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3451630550
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3201745274
Short name T818
Test name
Test status
Simulation time 36811442 ps
CPU time 1.38 seconds
Started Jul 29 06:21:45 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 219892 kb
Host smart-503fe908-1f28-4f79-93dc-4f1f681cf9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201745274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3201745274
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1285535903
Short name T807
Test name
Test status
Simulation time 48029997 ps
CPU time 0.87 seconds
Started Jul 29 06:21:35 PM PDT 24
Finished Jul 29 06:21:36 PM PDT 24
Peak memory 215088 kb
Host smart-de2957be-c4e8-4e47-bbd6-530f27e79ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285535903 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1285535903
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2486032659
Short name T714
Test name
Test status
Simulation time 17171125 ps
CPU time 1.01 seconds
Started Jul 29 06:21:40 PM PDT 24
Finished Jul 29 06:21:41 PM PDT 24
Peak memory 215228 kb
Host smart-f649662b-f2b6-4fd5-abe5-a2e1c0a65e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486032659 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2486032659
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2621292871
Short name T941
Test name
Test status
Simulation time 283945494 ps
CPU time 5.62 seconds
Started Jul 29 06:21:54 PM PDT 24
Finished Jul 29 06:21:59 PM PDT 24
Peak memory 217012 kb
Host smart-88d4c9d8-b9fd-4d8b-80ae-53844883535e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621292871 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2621292871
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1067313758
Short name T222
Test name
Test status
Simulation time 220410775416 ps
CPU time 2582.86 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 07:04:45 PM PDT 24
Peak memory 227524 kb
Host smart-7e52b65c-d556-4d5d-ae76-c9aa44e77cae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067313758 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1067313758
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1742130046
Short name T504
Test name
Test status
Simulation time 83276855 ps
CPU time 1.13 seconds
Started Jul 29 06:23:19 PM PDT 24
Finished Jul 29 06:23:20 PM PDT 24
Peak memory 219876 kb
Host smart-e0cf0c20-8b1e-46e8-a19b-b77464a41e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742130046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1742130046
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3443738879
Short name T786
Test name
Test status
Simulation time 245114887 ps
CPU time 1.91 seconds
Started Jul 29 06:23:28 PM PDT 24
Finished Jul 29 06:23:30 PM PDT 24
Peak memory 220624 kb
Host smart-a195d7cd-1fc8-46bd-aca3-ce272dff4ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443738879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3443738879
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1566665596
Short name T358
Test name
Test status
Simulation time 46379158 ps
CPU time 1.54 seconds
Started Jul 29 06:23:21 PM PDT 24
Finished Jul 29 06:23:23 PM PDT 24
Peak memory 217432 kb
Host smart-14dd1fc7-618c-40d3-bb7f-9768925a0130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566665596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1566665596
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.883933023
Short name T757
Test name
Test status
Simulation time 192461745 ps
CPU time 2.45 seconds
Started Jul 29 06:23:36 PM PDT 24
Finished Jul 29 06:23:39 PM PDT 24
Peak memory 219520 kb
Host smart-66bd6a7f-b9c1-413c-932b-84c1550b9e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883933023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.883933023
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2211132602
Short name T28
Test name
Test status
Simulation time 83680516 ps
CPU time 1.37 seconds
Started Jul 29 06:23:21 PM PDT 24
Finished Jul 29 06:23:22 PM PDT 24
Peak memory 217544 kb
Host smart-645ed714-17c3-4291-9a7d-898a8bf5512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211132602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2211132602
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2411389953
Short name T951
Test name
Test status
Simulation time 98945593 ps
CPU time 1.16 seconds
Started Jul 29 06:23:29 PM PDT 24
Finished Jul 29 06:23:30 PM PDT 24
Peak memory 217208 kb
Host smart-046fa29c-b16e-4d99-b23d-c8e515631d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411389953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2411389953
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1112923265
Short name T315
Test name
Test status
Simulation time 89572283 ps
CPU time 2.2 seconds
Started Jul 29 06:23:21 PM PDT 24
Finished Jul 29 06:23:23 PM PDT 24
Peak memory 220264 kb
Host smart-fa78314f-10ab-4fe7-b9ea-3f0655c614b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112923265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1112923265
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1577809380
Short name T689
Test name
Test status
Simulation time 128963532 ps
CPU time 2.99 seconds
Started Jul 29 06:23:18 PM PDT 24
Finished Jul 29 06:23:21 PM PDT 24
Peak memory 218604 kb
Host smart-97ce05ab-92f9-4d2a-bdda-1aeac5beb2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577809380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1577809380
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.636912035
Short name T342
Test name
Test status
Simulation time 42002856 ps
CPU time 1.65 seconds
Started Jul 29 06:23:22 PM PDT 24
Finished Jul 29 06:23:24 PM PDT 24
Peak memory 218468 kb
Host smart-af4b3d4b-f843-46b9-9e08-150c0f8262e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636912035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.636912035
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2165174875
Short name T659
Test name
Test status
Simulation time 364919120 ps
CPU time 2.04 seconds
Started Jul 29 06:23:30 PM PDT 24
Finished Jul 29 06:23:33 PM PDT 24
Peak memory 219636 kb
Host smart-81333305-c0e1-4426-8e4f-79aa9d11974d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165174875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2165174875
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.192871612
Short name T795
Test name
Test status
Simulation time 54975039 ps
CPU time 1.24 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:21:43 PM PDT 24
Peak memory 215744 kb
Host smart-7ea42fd5-7aff-4cce-99a0-6c00cf9e8c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192871612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.192871612
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1834044624
Short name T827
Test name
Test status
Simulation time 18439263 ps
CPU time 0.98 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 214852 kb
Host smart-107b7423-9ca6-415b-9cb5-b1d4c7f6b66d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834044624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1834044624
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2438598938
Short name T904
Test name
Test status
Simulation time 18117162 ps
CPU time 0.83 seconds
Started Jul 29 06:21:55 PM PDT 24
Finished Jul 29 06:21:56 PM PDT 24
Peak memory 216172 kb
Host smart-678020ad-918d-4fe6-980a-8e27a29e5306
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438598938 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2438598938
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2294883743
Short name T25
Test name
Test status
Simulation time 55693372 ps
CPU time 1.11 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 216808 kb
Host smart-e2db92f3-cff1-46fa-9e83-91ffeeab4d4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294883743 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2294883743
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3141088052
Short name T653
Test name
Test status
Simulation time 21663831 ps
CPU time 1.07 seconds
Started Jul 29 06:21:32 PM PDT 24
Finished Jul 29 06:21:33 PM PDT 24
Peak memory 224072 kb
Host smart-31d4a693-20f1-4670-ba37-d3ebbb91c39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141088052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3141088052
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.126893472
Short name T389
Test name
Test status
Simulation time 238866299 ps
CPU time 1.45 seconds
Started Jul 29 06:21:38 PM PDT 24
Finished Jul 29 06:21:40 PM PDT 24
Peak memory 218736 kb
Host smart-beab36be-1bc4-4c65-baab-0695a373614e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126893472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.126893472
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3544366626
Short name T803
Test name
Test status
Simulation time 27201789 ps
CPU time 0.92 seconds
Started Jul 29 06:21:51 PM PDT 24
Finished Jul 29 06:21:52 PM PDT 24
Peak memory 215328 kb
Host smart-79ef2822-7730-4b9e-b048-be43f7118b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544366626 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3544366626
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.4162022730
Short name T224
Test name
Test status
Simulation time 54423544 ps
CPU time 0.92 seconds
Started Jul 29 06:21:34 PM PDT 24
Finished Jul 29 06:21:35 PM PDT 24
Peak memory 215280 kb
Host smart-ba414c39-e574-412a-85d8-48c4e8f97de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162022730 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.4162022730
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.914390177
Short name T938
Test name
Test status
Simulation time 2227793364 ps
CPU time 3.26 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 217244 kb
Host smart-feaf140e-a04f-4296-bc2c-b84ff37ae5af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914390177 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.914390177
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1881209227
Short name T844
Test name
Test status
Simulation time 269553718533 ps
CPU time 1558.48 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:47:42 PM PDT 24
Peak memory 224156 kb
Host smart-936e9ca0-692b-4bb1-977b-c3f1195519d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881209227 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1881209227
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2215424133
Short name T318
Test name
Test status
Simulation time 107991496 ps
CPU time 2.5 seconds
Started Jul 29 06:23:29 PM PDT 24
Finished Jul 29 06:23:32 PM PDT 24
Peak memory 219892 kb
Host smart-34822fc4-2687-4ab7-9325-b6d347bdac1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215424133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2215424133
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2787468271
Short name T824
Test name
Test status
Simulation time 287631734 ps
CPU time 3.39 seconds
Started Jul 29 06:23:17 PM PDT 24
Finished Jul 29 06:23:21 PM PDT 24
Peak memory 220120 kb
Host smart-caea8527-f538-405b-b895-10e4ccf0c530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787468271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2787468271
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2531326298
Short name T745
Test name
Test status
Simulation time 39106764 ps
CPU time 1.1 seconds
Started Jul 29 06:23:28 PM PDT 24
Finished Jul 29 06:23:29 PM PDT 24
Peak memory 217376 kb
Host smart-5e99a7c1-5411-4574-aeb0-7aeb0f7d6d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531326298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2531326298
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3382954598
Short name T755
Test name
Test status
Simulation time 42803108 ps
CPU time 1.14 seconds
Started Jul 29 06:23:29 PM PDT 24
Finished Jul 29 06:23:30 PM PDT 24
Peak memory 217428 kb
Host smart-67cb81d3-d1e6-45d1-97ed-cf50db7e35d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382954598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3382954598
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.587146302
Short name T34
Test name
Test status
Simulation time 43574587 ps
CPU time 1.74 seconds
Started Jul 29 06:23:30 PM PDT 24
Finished Jul 29 06:23:32 PM PDT 24
Peak memory 218464 kb
Host smart-f1046fce-ae91-4db5-9903-8d888b158cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587146302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.587146302
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1919277792
Short name T301
Test name
Test status
Simulation time 206787994 ps
CPU time 3.36 seconds
Started Jul 29 06:23:28 PM PDT 24
Finished Jul 29 06:23:31 PM PDT 24
Peak memory 217608 kb
Host smart-aeb0a6db-4f8f-41b0-baa9-3bb7e40f05d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919277792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1919277792
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2078195824
Short name T861
Test name
Test status
Simulation time 181901933 ps
CPU time 1.25 seconds
Started Jul 29 06:23:36 PM PDT 24
Finished Jul 29 06:23:37 PM PDT 24
Peak memory 217304 kb
Host smart-4ff0428c-48eb-496b-b690-4abe8ba85283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078195824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2078195824
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.4245120104
Short name T490
Test name
Test status
Simulation time 25624883 ps
CPU time 1.16 seconds
Started Jul 29 06:23:28 PM PDT 24
Finished Jul 29 06:23:30 PM PDT 24
Peak memory 217356 kb
Host smart-6093f978-da39-47df-9567-f2c4c2dac093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245120104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.4245120104
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.595135382
Short name T581
Test name
Test status
Simulation time 40771540 ps
CPU time 1.59 seconds
Started Jul 29 06:23:30 PM PDT 24
Finished Jul 29 06:23:32 PM PDT 24
Peak memory 218708 kb
Host smart-93c7fccb-cb0a-4568-b578-d350d7b6468f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595135382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.595135382
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1556637307
Short name T750
Test name
Test status
Simulation time 66745007 ps
CPU time 1.02 seconds
Started Jul 29 06:21:56 PM PDT 24
Finished Jul 29 06:21:57 PM PDT 24
Peak memory 219748 kb
Host smart-d01bcff5-9bcc-426e-9fda-12d0b27820ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556637307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1556637307
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2448593788
Short name T379
Test name
Test status
Simulation time 130945992 ps
CPU time 0.86 seconds
Started Jul 29 06:21:37 PM PDT 24
Finished Jul 29 06:21:38 PM PDT 24
Peak memory 215116 kb
Host smart-6de2db19-1483-43ff-911f-653ed5091abe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448593788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2448593788
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.342880177
Short name T180
Test name
Test status
Simulation time 11084786 ps
CPU time 0.87 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:21:43 PM PDT 24
Peak memory 216284 kb
Host smart-67433dc1-dfbc-4eef-806e-8e834bf9c8a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342880177 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.342880177
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.276586009
Short name T170
Test name
Test status
Simulation time 44165395 ps
CPU time 0.97 seconds
Started Jul 29 06:21:54 PM PDT 24
Finished Jul 29 06:21:55 PM PDT 24
Peak memory 216680 kb
Host smart-54afefa7-6bbf-4fa9-805f-9c7865e8ed7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276586009 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.276586009
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.608499986
Short name T51
Test name
Test status
Simulation time 20136210 ps
CPU time 1.11 seconds
Started Jul 29 06:21:49 PM PDT 24
Finished Jul 29 06:21:55 PM PDT 24
Peak memory 223708 kb
Host smart-75f9a705-c8b6-4f10-ba38-9152cbcb69c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608499986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.608499986
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3662228652
Short name T471
Test name
Test status
Simulation time 33087289 ps
CPU time 1.29 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 218588 kb
Host smart-a07fa695-38d6-4832-b519-699e697ac192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662228652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3662228652
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.725674058
Short name T79
Test name
Test status
Simulation time 21667252 ps
CPU time 1.18 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 215796 kb
Host smart-964b732f-77e6-40d3-aae0-1f8ea4cfd0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725674058 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.725674058
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1181858349
Short name T749
Test name
Test status
Simulation time 55421736 ps
CPU time 0.92 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 215244 kb
Host smart-ceab0c40-f803-4af3-978f-af697d602cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181858349 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1181858349
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3788384898
Short name T516
Test name
Test status
Simulation time 184290808 ps
CPU time 2.62 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:47 PM PDT 24
Peak memory 215384 kb
Host smart-8a364944-e8d6-4a18-9e7e-dca244b7c4ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788384898 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3788384898
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.138864561
Short name T799
Test name
Test status
Simulation time 48216660303 ps
CPU time 1054.1 seconds
Started Jul 29 06:21:49 PM PDT 24
Finished Jul 29 06:39:23 PM PDT 24
Peak memory 223616 kb
Host smart-41b54434-9117-444b-9e41-84c2a7c1695a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138864561 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.138864561
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3380042440
Short name T238
Test name
Test status
Simulation time 100652899 ps
CPU time 1.27 seconds
Started Jul 29 06:23:30 PM PDT 24
Finished Jul 29 06:23:32 PM PDT 24
Peak memory 219140 kb
Host smart-e5777185-281f-4176-a83f-d4b17ed031ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380042440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3380042440
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3190760007
Short name T557
Test name
Test status
Simulation time 31085907 ps
CPU time 1.24 seconds
Started Jul 29 06:23:21 PM PDT 24
Finished Jul 29 06:23:23 PM PDT 24
Peak memory 217400 kb
Host smart-37b408bb-c98c-4c5e-937f-0995442504fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190760007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3190760007
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3020745266
Short name T446
Test name
Test status
Simulation time 43611588 ps
CPU time 1.46 seconds
Started Jul 29 06:23:19 PM PDT 24
Finished Jul 29 06:23:20 PM PDT 24
Peak memory 218440 kb
Host smart-55386257-1b70-4bfa-9253-5ae880ab4e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020745266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3020745266
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.700995782
Short name T555
Test name
Test status
Simulation time 45518323 ps
CPU time 1.41 seconds
Started Jul 29 06:23:20 PM PDT 24
Finished Jul 29 06:23:21 PM PDT 24
Peak memory 219976 kb
Host smart-42b60408-ae84-4b81-8b36-46523992a584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700995782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.700995782
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.423346590
Short name T55
Test name
Test status
Simulation time 49734262 ps
CPU time 1.18 seconds
Started Jul 29 06:23:18 PM PDT 24
Finished Jul 29 06:23:19 PM PDT 24
Peak memory 217364 kb
Host smart-f5a7d5ba-0317-4c31-a27c-4a2cb5df16b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423346590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.423346590
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2795785557
Short name T429
Test name
Test status
Simulation time 27698205 ps
CPU time 1.35 seconds
Started Jul 29 06:23:31 PM PDT 24
Finished Jul 29 06:23:33 PM PDT 24
Peak memory 217280 kb
Host smart-7d04d493-644b-4f3d-976c-ff18d8c104c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795785557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2795785557
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2864149283
Short name T946
Test name
Test status
Simulation time 64958039 ps
CPU time 1.53 seconds
Started Jul 29 06:23:41 PM PDT 24
Finished Jul 29 06:23:43 PM PDT 24
Peak memory 219832 kb
Host smart-56af9842-b1bf-49ab-b6d8-d832ac52233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864149283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2864149283
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1730968032
Short name T977
Test name
Test status
Simulation time 118318066 ps
CPU time 1.44 seconds
Started Jul 29 06:23:22 PM PDT 24
Finished Jul 29 06:23:24 PM PDT 24
Peak memory 217224 kb
Host smart-433c18c6-b363-4baa-99d9-b59539ad869c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730968032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1730968032
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3565527934
Short name T529
Test name
Test status
Simulation time 53011834 ps
CPU time 1.51 seconds
Started Jul 29 06:23:21 PM PDT 24
Finished Jul 29 06:23:23 PM PDT 24
Peak memory 218584 kb
Host smart-b2b1436b-9393-48e0-ae98-45fe14c302a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565527934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3565527934
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.4125229359
Short name T395
Test name
Test status
Simulation time 54545473 ps
CPU time 1.18 seconds
Started Jul 29 06:23:28 PM PDT 24
Finished Jul 29 06:23:34 PM PDT 24
Peak memory 217288 kb
Host smart-016b5e8f-0c86-47bb-aeb6-b305619a031d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125229359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.4125229359
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.325046651
Short name T593
Test name
Test status
Simulation time 79728100 ps
CPU time 1.13 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 218704 kb
Host smart-e124214b-2c5d-4864-ad2c-086f6647f399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325046651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.325046651
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.192890314
Short name T656
Test name
Test status
Simulation time 13947300 ps
CPU time 0.97 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 206664 kb
Host smart-8574ed11-e915-40fc-b1ae-452cfebadd8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192890314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.192890314
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1416359395
Short name T598
Test name
Test status
Simulation time 44533540 ps
CPU time 0.83 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 215404 kb
Host smart-f0b5544d-d150-4899-9da5-b093592f17a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416359395 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1416359395
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.563375502
Short name T162
Test name
Test status
Simulation time 110755513 ps
CPU time 0.98 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:21:42 PM PDT 24
Peak memory 216828 kb
Host smart-ccd5bf06-d12b-46ab-b3bf-3680a64f9e60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563375502 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.563375502
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.4080475731
Short name T624
Test name
Test status
Simulation time 43881721 ps
CPU time 1.12 seconds
Started Jul 29 06:21:50 PM PDT 24
Finished Jul 29 06:21:52 PM PDT 24
Peak memory 219572 kb
Host smart-5d8c385c-7fa6-4b92-b718-42a719862aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080475731 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.4080475731
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3144420426
Short name T643
Test name
Test status
Simulation time 37979630 ps
CPU time 1.42 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 215252 kb
Host smart-4c78e257-ac58-4f36-b0f8-05bbf6e83a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144420426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3144420426
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3923204635
Short name T90
Test name
Test status
Simulation time 58688580 ps
CPU time 0.79 seconds
Started Jul 29 06:21:49 PM PDT 24
Finished Jul 29 06:21:50 PM PDT 24
Peak memory 215156 kb
Host smart-c0c4daa9-8f78-43f1-97d1-d5b91aee087c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923204635 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3923204635
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.390114202
Short name T935
Test name
Test status
Simulation time 32450787 ps
CPU time 0.89 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 215288 kb
Host smart-e3833d34-de77-4110-a8df-fd098c41d3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390114202 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.390114202
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.445913539
Short name T111
Test name
Test status
Simulation time 542653003 ps
CPU time 3.11 seconds
Started Jul 29 06:21:53 PM PDT 24
Finished Jul 29 06:21:57 PM PDT 24
Peak memory 215372 kb
Host smart-2702a784-df9f-49a0-9e9f-4ac1ec84ab96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445913539 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.445913539
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.61184060
Short name T797
Test name
Test status
Simulation time 695002683584 ps
CPU time 1459.69 seconds
Started Jul 29 06:21:50 PM PDT 24
Finished Jul 29 06:46:10 PM PDT 24
Peak memory 223408 kb
Host smart-28b40270-a112-40fe-98ce-fc7cb7a956d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61184060 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.61184060
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2645304896
Short name T480
Test name
Test status
Simulation time 42529799 ps
CPU time 1.48 seconds
Started Jul 29 06:23:18 PM PDT 24
Finished Jul 29 06:23:20 PM PDT 24
Peak memory 218424 kb
Host smart-54f8b353-737c-4458-bf50-a0defa914b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645304896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2645304896
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.216553628
Short name T29
Test name
Test status
Simulation time 47735617 ps
CPU time 1.57 seconds
Started Jul 29 06:23:30 PM PDT 24
Finished Jul 29 06:23:32 PM PDT 24
Peak memory 217140 kb
Host smart-e5d724a3-da24-4f8c-bbdd-8aec18880f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216553628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.216553628
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2456501077
Short name T337
Test name
Test status
Simulation time 46700653 ps
CPU time 1.54 seconds
Started Jul 29 06:23:20 PM PDT 24
Finished Jul 29 06:23:22 PM PDT 24
Peak memory 220036 kb
Host smart-6a11d008-fd86-4a74-8fea-5d324b937585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456501077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2456501077
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.771338974
Short name T303
Test name
Test status
Simulation time 68088499 ps
CPU time 2.4 seconds
Started Jul 29 06:23:29 PM PDT 24
Finished Jul 29 06:23:32 PM PDT 24
Peak memory 220124 kb
Host smart-a3434a43-469e-4454-ab77-46b340d485ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771338974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.771338974
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3635854022
Short name T545
Test name
Test status
Simulation time 41590890 ps
CPU time 1.66 seconds
Started Jul 29 06:23:30 PM PDT 24
Finished Jul 29 06:23:32 PM PDT 24
Peak memory 220004 kb
Host smart-e3fb411e-9a8d-480e-b777-7b6ac8062648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635854022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3635854022
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3958726704
Short name T235
Test name
Test status
Simulation time 126661370 ps
CPU time 1.37 seconds
Started Jul 29 06:23:18 PM PDT 24
Finished Jul 29 06:23:20 PM PDT 24
Peak memory 218720 kb
Host smart-17af6cda-a785-4f0d-bb84-140a1a8aa9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958726704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3958726704
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.28993625
Short name T443
Test name
Test status
Simulation time 142317223 ps
CPU time 1.38 seconds
Started Jul 29 06:23:15 PM PDT 24
Finished Jul 29 06:23:16 PM PDT 24
Peak memory 218760 kb
Host smart-010c029a-ba89-4ec7-a7ab-b26a49bee697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28993625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.28993625
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2667320822
Short name T955
Test name
Test status
Simulation time 45105099 ps
CPU time 1.35 seconds
Started Jul 29 06:23:19 PM PDT 24
Finished Jul 29 06:23:21 PM PDT 24
Peak memory 218832 kb
Host smart-38e7490a-3cc1-40f3-b7e0-72613c670682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667320822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2667320822
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2570241778
Short name T663
Test name
Test status
Simulation time 106769735 ps
CPU time 1.24 seconds
Started Jul 29 06:23:30 PM PDT 24
Finished Jul 29 06:23:31 PM PDT 24
Peak memory 217136 kb
Host smart-b472c0c7-fdef-4f89-926c-8c2e29fccc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570241778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2570241778
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1539531481
Short name T398
Test name
Test status
Simulation time 37034431 ps
CPU time 1.35 seconds
Started Jul 29 06:23:28 PM PDT 24
Finished Jul 29 06:23:29 PM PDT 24
Peak memory 217112 kb
Host smart-858c53ec-e330-4360-bfa9-737e844e1505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539531481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1539531481
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2725146400
Short name T633
Test name
Test status
Simulation time 86087146 ps
CPU time 1.19 seconds
Started Jul 29 06:21:07 PM PDT 24
Finished Jul 29 06:21:08 PM PDT 24
Peak memory 218432 kb
Host smart-21195639-fa72-4617-b2ad-dfad70cecd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725146400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2725146400
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1062384055
Short name T791
Test name
Test status
Simulation time 30542540 ps
CPU time 1.02 seconds
Started Jul 29 06:21:02 PM PDT 24
Finished Jul 29 06:21:03 PM PDT 24
Peak memory 215160 kb
Host smart-f90866e9-d7e8-4682-9ed3-13a105c17876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062384055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1062384055
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.4014595501
Short name T175
Test name
Test status
Simulation time 24441120 ps
CPU time 0.83 seconds
Started Jul 29 06:21:00 PM PDT 24
Finished Jul 29 06:21:01 PM PDT 24
Peak memory 215348 kb
Host smart-272f616a-b29b-40f5-ab4b-40dae17d9dcd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014595501 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.4014595501
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.143843727
Short name T457
Test name
Test status
Simulation time 85916011 ps
CPU time 1.13 seconds
Started Jul 29 06:21:00 PM PDT 24
Finished Jul 29 06:21:02 PM PDT 24
Peak memory 218664 kb
Host smart-e69a52e2-dce8-43df-af5c-d545748bb69f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143843727 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.143843727
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3383431174
Short name T695
Test name
Test status
Simulation time 18049412 ps
CPU time 1.07 seconds
Started Jul 29 06:21:02 PM PDT 24
Finished Jul 29 06:21:04 PM PDT 24
Peak memory 218400 kb
Host smart-395acc42-f3e6-4b64-88a3-f04edbc49e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383431174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3383431174
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3682810041
Short name T809
Test name
Test status
Simulation time 95917962 ps
CPU time 1.27 seconds
Started Jul 29 06:21:01 PM PDT 24
Finished Jul 29 06:21:03 PM PDT 24
Peak memory 219220 kb
Host smart-1587d3ca-8409-453b-be19-4248d6833104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682810041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3682810041
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2896283097
Short name T667
Test name
Test status
Simulation time 24302113 ps
CPU time 0.95 seconds
Started Jul 29 06:21:04 PM PDT 24
Finished Jul 29 06:21:05 PM PDT 24
Peak memory 215524 kb
Host smart-abff9bb0-276c-45ff-b105-94e2092fe213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896283097 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2896283097
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_smoke.3989601596
Short name T325
Test name
Test status
Simulation time 25887530 ps
CPU time 0.96 seconds
Started Jul 29 06:21:01 PM PDT 24
Finished Jul 29 06:21:02 PM PDT 24
Peak memory 215296 kb
Host smart-ad9a8abc-6b05-4896-8f07-f2440f0cd304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989601596 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3989601596
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2035511674
Short name T362
Test name
Test status
Simulation time 227775967 ps
CPU time 2.8 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:06 PM PDT 24
Peak memory 217420 kb
Host smart-8bd0dc07-29fb-462c-aec1-233033e5ddc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035511674 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2035511674
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1972424900
Short name T426
Test name
Test status
Simulation time 39683058334 ps
CPU time 330.36 seconds
Started Jul 29 06:21:05 PM PDT 24
Finished Jul 29 06:26:35 PM PDT 24
Peak memory 219204 kb
Host smart-6e5d229c-b2d9-4e5a-bc53-7bfb0ce02859
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972424900 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1972424900
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.386244343
Short name T981
Test name
Test status
Simulation time 27096139 ps
CPU time 1.26 seconds
Started Jul 29 06:21:47 PM PDT 24
Finished Jul 29 06:21:49 PM PDT 24
Peak memory 219708 kb
Host smart-f5ea3f23-42ac-4776-b491-8263bc9c9f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386244343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.386244343
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3508096988
Short name T638
Test name
Test status
Simulation time 23841312 ps
CPU time 0.83 seconds
Started Jul 29 06:21:49 PM PDT 24
Finished Jul 29 06:21:50 PM PDT 24
Peak memory 206636 kb
Host smart-0a4cca76-eba8-4d55-b265-b9f4a4a20780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508096988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3508096988
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2427189923
Short name T583
Test name
Test status
Simulation time 17739335 ps
CPU time 0.82 seconds
Started Jul 29 06:21:49 PM PDT 24
Finished Jul 29 06:21:50 PM PDT 24
Peak memory 216176 kb
Host smart-a5fb41f4-3203-444b-b128-c0b70620ee46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427189923 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2427189923
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2382417223
Short name T878
Test name
Test status
Simulation time 38231005 ps
CPU time 1.35 seconds
Started Jul 29 06:21:50 PM PDT 24
Finished Jul 29 06:21:51 PM PDT 24
Peak memory 216756 kb
Host smart-1ade4923-2489-4251-88b0-ed3b5ca616da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382417223 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2382417223
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.417304745
Short name T771
Test name
Test status
Simulation time 20047418 ps
CPU time 1.07 seconds
Started Jul 29 06:21:36 PM PDT 24
Finished Jul 29 06:21:37 PM PDT 24
Peak memory 219600 kb
Host smart-6f212324-31d1-46da-86ad-10587f8cafe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417304745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.417304745
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.374234607
Short name T812
Test name
Test status
Simulation time 63988597 ps
CPU time 1.23 seconds
Started Jul 29 06:21:49 PM PDT 24
Finished Jul 29 06:21:50 PM PDT 24
Peak memory 218500 kb
Host smart-9d0cbfaa-bdbf-4028-bb32-d6f30ca17c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374234607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.374234607
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.674953730
Short name T89
Test name
Test status
Simulation time 24925831 ps
CPU time 0.94 seconds
Started Jul 29 06:21:49 PM PDT 24
Finished Jul 29 06:21:50 PM PDT 24
Peak memory 215772 kb
Host smart-77d3d5e4-f039-4558-8647-b9fedb38df53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674953730 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.674953730
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3749049942
Short name T326
Test name
Test status
Simulation time 25811296 ps
CPU time 0.92 seconds
Started Jul 29 06:21:51 PM PDT 24
Finished Jul 29 06:21:52 PM PDT 24
Peak memory 215260 kb
Host smart-70bc61c5-e0d8-413f-a7e6-9615bca96dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749049942 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3749049942
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1722050450
Short name T889
Test name
Test status
Simulation time 341824000 ps
CPU time 3.65 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 220032 kb
Host smart-27dfad9d-6076-4f8e-bc74-c5b6b6f24e52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722050450 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1722050450
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2374534696
Short name T703
Test name
Test status
Simulation time 23862524581 ps
CPU time 615.17 seconds
Started Jul 29 06:21:53 PM PDT 24
Finished Jul 29 06:32:08 PM PDT 24
Peak memory 223612 kb
Host smart-9ef164c9-239d-41c4-87f4-81706e203f85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374534696 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2374534696
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.980082816
Short name T566
Test name
Test status
Simulation time 28599940 ps
CPU time 1.26 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:21:59 PM PDT 24
Peak memory 219592 kb
Host smart-c11a0b4f-11c6-4dba-a9a8-9b09a8ea7560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980082816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.980082816
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3288133529
Short name T393
Test name
Test status
Simulation time 22966780 ps
CPU time 0.88 seconds
Started Jul 29 06:21:52 PM PDT 24
Finished Jul 29 06:21:53 PM PDT 24
Peak memory 214876 kb
Host smart-a1de64e5-dc4e-4c58-b959-718351a88a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288133529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3288133529
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3784234591
Short name T907
Test name
Test status
Simulation time 12093306 ps
CPU time 0.88 seconds
Started Jul 29 06:21:52 PM PDT 24
Finished Jul 29 06:21:53 PM PDT 24
Peak memory 216080 kb
Host smart-6e5e8ff3-f8ea-4589-96fe-4f19a7ca2b1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784234591 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3784234591
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3502286479
Short name T445
Test name
Test status
Simulation time 204554735 ps
CPU time 1.13 seconds
Started Jul 29 06:21:49 PM PDT 24
Finished Jul 29 06:21:50 PM PDT 24
Peak memory 218616 kb
Host smart-6379198d-09b4-49b8-970b-e18947f0aab2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502286479 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3502286479
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1083479319
Short name T718
Test name
Test status
Simulation time 28721063 ps
CPU time 0.87 seconds
Started Jul 29 06:21:52 PM PDT 24
Finished Jul 29 06:21:53 PM PDT 24
Peak memory 218160 kb
Host smart-25c1faac-29a4-48c8-95ac-e3f85dd996c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083479319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1083479319
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.44051074
Short name T453
Test name
Test status
Simulation time 114018209 ps
CPU time 1.27 seconds
Started Jul 29 06:21:50 PM PDT 24
Finished Jul 29 06:21:52 PM PDT 24
Peak memory 218988 kb
Host smart-38cf6be8-cca7-4df5-b431-73a5a76f575d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44051074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.44051074
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3583695499
Short name T683
Test name
Test status
Simulation time 23571529 ps
CPU time 1.25 seconds
Started Jul 29 06:21:48 PM PDT 24
Finished Jul 29 06:21:49 PM PDT 24
Peak memory 224120 kb
Host smart-00737f38-4036-48e2-8488-46a57681ba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583695499 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3583695499
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1644736576
Short name T324
Test name
Test status
Simulation time 105686966 ps
CPU time 0.85 seconds
Started Jul 29 06:21:46 PM PDT 24
Finished Jul 29 06:21:47 PM PDT 24
Peak memory 215136 kb
Host smart-baf0013a-13e6-405c-ad32-cb587ee07be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644736576 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1644736576
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3363224913
Short name T600
Test name
Test status
Simulation time 281075273 ps
CPU time 4.15 seconds
Started Jul 29 06:22:10 PM PDT 24
Finished Jul 29 06:22:15 PM PDT 24
Peak memory 220304 kb
Host smart-a14c7869-8be1-4ba8-85e6-8c7348089a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363224913 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3363224913
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.4101355739
Short name T233
Test name
Test status
Simulation time 580543804707 ps
CPU time 1895.02 seconds
Started Jul 29 06:21:48 PM PDT 24
Finished Jul 29 06:53:23 PM PDT 24
Peak memory 223836 kb
Host smart-ad296c8f-af8d-46ba-a065-de811479ac13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101355739 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.4101355739
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.665371824
Short name T634
Test name
Test status
Simulation time 27999935 ps
CPU time 1.2 seconds
Started Jul 29 06:22:00 PM PDT 24
Finished Jul 29 06:22:01 PM PDT 24
Peak memory 215684 kb
Host smart-50f2c074-fc59-4553-9b81-875a9abdacc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665371824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.665371824
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1932282430
Short name T678
Test name
Test status
Simulation time 75931684 ps
CPU time 1.44 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 214948 kb
Host smart-88f9f7ca-c92e-47f3-ad02-3386d6bf0ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932282430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1932282430
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3099602383
Short name T214
Test name
Test status
Simulation time 45414246 ps
CPU time 0.83 seconds
Started Jul 29 06:21:51 PM PDT 24
Finished Jul 29 06:21:52 PM PDT 24
Peak memory 216216 kb
Host smart-1c87c855-cdb8-4d83-9878-9f46fe248022
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099602383 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3099602383
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1848982981
Short name T657
Test name
Test status
Simulation time 47536442 ps
CPU time 1.05 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:21:59 PM PDT 24
Peak memory 218408 kb
Host smart-128e30da-e360-4fe8-abfb-570fb09bb238
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848982981 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1848982981
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3697144269
Short name T810
Test name
Test status
Simulation time 19435660 ps
CPU time 1.06 seconds
Started Jul 29 06:21:48 PM PDT 24
Finished Jul 29 06:21:50 PM PDT 24
Peak memory 219416 kb
Host smart-2eefc29a-f7d1-46bb-b1b7-a6fd64d20807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697144269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3697144269
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2464387004
Short name T296
Test name
Test status
Simulation time 98567483 ps
CPU time 1.18 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:21:59 PM PDT 24
Peak memory 217412 kb
Host smart-6f193ab7-5f4f-4dec-86a3-5f88ce12c44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464387004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2464387004
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3572949426
Short name T341
Test name
Test status
Simulation time 51949311 ps
CPU time 0.82 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 215132 kb
Host smart-9dce7b10-f849-40c4-b494-bd8ce3b75d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572949426 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3572949426
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3894428454
Short name T510
Test name
Test status
Simulation time 24806033 ps
CPU time 0.95 seconds
Started Jul 29 06:21:50 PM PDT 24
Finished Jul 29 06:21:51 PM PDT 24
Peak memory 215268 kb
Host smart-3a70016c-b08b-4454-b637-74b5778d37e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894428454 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3894428454
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2218990226
Short name T367
Test name
Test status
Simulation time 633550364 ps
CPU time 6.44 seconds
Started Jul 29 06:21:47 PM PDT 24
Finished Jul 29 06:21:54 PM PDT 24
Peak memory 215308 kb
Host smart-ca387b42-7f96-40c2-92e9-3b9f21d33659
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218990226 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2218990226
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2775514007
Short name T926
Test name
Test status
Simulation time 1247005969442 ps
CPU time 2185.08 seconds
Started Jul 29 06:22:03 PM PDT 24
Finished Jul 29 06:58:28 PM PDT 24
Peak memory 228124 kb
Host smart-f1cad1b3-aad2-4072-a1c5-3f33e1985ef6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775514007 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2775514007
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.893546858
Short name T211
Test name
Test status
Simulation time 102983590 ps
CPU time 1.15 seconds
Started Jul 29 06:21:47 PM PDT 24
Finished Jul 29 06:21:49 PM PDT 24
Peak memory 219128 kb
Host smart-7d3cb160-f992-49bd-83ec-5fb50b20d3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893546858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.893546858
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.958283821
Short name T901
Test name
Test status
Simulation time 17083562 ps
CPU time 0.95 seconds
Started Jul 29 06:21:55 PM PDT 24
Finished Jul 29 06:21:57 PM PDT 24
Peak memory 206528 kb
Host smart-564f8ec4-195b-4088-9ca9-2567f2b96348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958283821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.958283821
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.656459283
Short name T125
Test name
Test status
Simulation time 12071318 ps
CPU time 0.89 seconds
Started Jul 29 06:22:11 PM PDT 24
Finished Jul 29 06:22:12 PM PDT 24
Peak memory 216524 kb
Host smart-99555b65-3acc-4a6a-9ae9-670bdf68cfc4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656459283 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.656459283
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2427007172
Short name T479
Test name
Test status
Simulation time 36373174 ps
CPU time 1.26 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:46 PM PDT 24
Peak memory 218408 kb
Host smart-854c27c1-b2ea-498d-b54b-17fa1a8c39c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427007172 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2427007172
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.226790869
Short name T958
Test name
Test status
Simulation time 25018363 ps
CPU time 0.94 seconds
Started Jul 29 06:21:52 PM PDT 24
Finished Jul 29 06:21:53 PM PDT 24
Peak memory 219444 kb
Host smart-8252918d-9cc8-443a-9234-14252736ed93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226790869 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.226790869
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2292836625
Short name T537
Test name
Test status
Simulation time 68623229 ps
CPU time 1.11 seconds
Started Jul 29 06:21:53 PM PDT 24
Finished Jul 29 06:21:54 PM PDT 24
Peak memory 217224 kb
Host smart-7350d3e8-ebfe-43e6-9ae1-2761ea5669a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292836625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2292836625
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2600437806
Short name T551
Test name
Test status
Simulation time 21944365 ps
CPU time 1.19 seconds
Started Jul 29 06:22:10 PM PDT 24
Finished Jul 29 06:22:11 PM PDT 24
Peak memory 224028 kb
Host smart-59873609-45cf-457c-86ea-f01497b1b9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600437806 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2600437806
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2970414171
Short name T717
Test name
Test status
Simulation time 20035531 ps
CPU time 1.1 seconds
Started Jul 29 06:21:54 PM PDT 24
Finished Jul 29 06:21:56 PM PDT 24
Peak memory 215284 kb
Host smart-dc488bc1-ca53-4e61-9ffe-ead46d77448d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970414171 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2970414171
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.87347929
Short name T359
Test name
Test status
Simulation time 77824932 ps
CPU time 1.98 seconds
Started Jul 29 06:21:53 PM PDT 24
Finished Jul 29 06:21:55 PM PDT 24
Peak memory 217020 kb
Host smart-d0c4b8cb-a714-4baa-92a5-1599b588eaf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87347929 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.87347929
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.4266533046
Short name T700
Test name
Test status
Simulation time 186333762787 ps
CPU time 734.9 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:33:58 PM PDT 24
Peak memory 223760 kb
Host smart-b781c1d1-1458-441d-9c9e-e93ee66570a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266533046 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.4266533046
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1245457799
Short name T682
Test name
Test status
Simulation time 34418738 ps
CPU time 1.3 seconds
Started Jul 29 06:21:48 PM PDT 24
Finished Jul 29 06:21:49 PM PDT 24
Peak memory 219912 kb
Host smart-22ce2a5d-ecea-4824-a403-33490c65d89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245457799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1245457799
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.818184853
Short name T357
Test name
Test status
Simulation time 119481159 ps
CPU time 0.93 seconds
Started Jul 29 06:21:37 PM PDT 24
Finished Jul 29 06:21:38 PM PDT 24
Peak memory 214892 kb
Host smart-c8109a5c-19b9-4cdb-b4eb-4a4aa6e352a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818184853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.818184853
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2495491774
Short name T197
Test name
Test status
Simulation time 10603070 ps
CPU time 0.88 seconds
Started Jul 29 06:21:51 PM PDT 24
Finished Jul 29 06:21:52 PM PDT 24
Peak memory 216288 kb
Host smart-ed2eb40f-6d6b-48f6-9674-05550e87911a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495491774 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2495491774
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3801976001
Short name T676
Test name
Test status
Simulation time 69817875 ps
CPU time 1.12 seconds
Started Jul 29 06:21:53 PM PDT 24
Finished Jul 29 06:21:54 PM PDT 24
Peak memory 218456 kb
Host smart-73fd7fd4-a5e1-47ed-a7b5-759956882215
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801976001 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3801976001
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2229537485
Short name T117
Test name
Test status
Simulation time 81296381 ps
CPU time 1.03 seconds
Started Jul 29 06:21:56 PM PDT 24
Finished Jul 29 06:22:02 PM PDT 24
Peak memory 219672 kb
Host smart-a462d993-beb0-4491-9fa9-97400169e954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229537485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2229537485
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3779325089
Short name T300
Test name
Test status
Simulation time 119860525 ps
CPU time 1.17 seconds
Started Jul 29 06:22:02 PM PDT 24
Finished Jul 29 06:22:03 PM PDT 24
Peak memory 219900 kb
Host smart-59529497-3f2f-40ab-8760-6894c2367d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779325089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3779325089
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.4123392956
Short name T481
Test name
Test status
Simulation time 49844986 ps
CPU time 0.84 seconds
Started Jul 29 06:22:01 PM PDT 24
Finished Jul 29 06:22:02 PM PDT 24
Peak memory 215636 kb
Host smart-1a3f02d8-1b69-4e85-a585-c5ed9426ce1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123392956 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.4123392956
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.4158431112
Short name T419
Test name
Test status
Simulation time 40660968 ps
CPU time 0.87 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 215244 kb
Host smart-ecf03ba4-ab8a-48d8-8ef1-7cb6dc60e53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158431112 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.4158431112
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1020513811
Short name T454
Test name
Test status
Simulation time 1260453838 ps
CPU time 3.21 seconds
Started Jul 29 06:21:53 PM PDT 24
Finished Jul 29 06:21:56 PM PDT 24
Peak memory 220584 kb
Host smart-3cb95898-0676-4077-9ea2-ef4d7345df38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020513811 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1020513811
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.723668763
Short name T530
Test name
Test status
Simulation time 16025583430 ps
CPU time 329.02 seconds
Started Jul 29 06:21:51 PM PDT 24
Finished Jul 29 06:27:20 PM PDT 24
Peak memory 220308 kb
Host smart-13f71f07-7bc8-4591-b243-79ea6d83024c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723668763 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.723668763
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.441991489
Short name T851
Test name
Test status
Simulation time 60771752 ps
CPU time 1.27 seconds
Started Jul 29 06:21:46 PM PDT 24
Finished Jul 29 06:21:47 PM PDT 24
Peak memory 215672 kb
Host smart-3cfb31f4-c40c-4bc5-b42c-a601222381c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441991489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.441991489
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.4121162738
Short name T822
Test name
Test status
Simulation time 28137467 ps
CPU time 0.93 seconds
Started Jul 29 06:21:48 PM PDT 24
Finished Jul 29 06:21:50 PM PDT 24
Peak memory 206736 kb
Host smart-a564f114-f642-4317-bc75-d1ddffc50a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121162738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.4121162738
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.4050556931
Short name T127
Test name
Test status
Simulation time 12353031 ps
CPU time 0.86 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:21:58 PM PDT 24
Peak memory 216428 kb
Host smart-3e9e40f0-faeb-4b0c-bfa8-beb040beead2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050556931 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.4050556931
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.941461080
Short name T763
Test name
Test status
Simulation time 414244637 ps
CPU time 1.1 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:21:58 PM PDT 24
Peak memory 219552 kb
Host smart-989e9b5d-2ba1-4734-ae1f-ba75295e973b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941461080 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.941461080
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2475412767
Short name T8
Test name
Test status
Simulation time 24053679 ps
CPU time 1.14 seconds
Started Jul 29 06:22:06 PM PDT 24
Finished Jul 29 06:22:08 PM PDT 24
Peak memory 218496 kb
Host smart-af4f0731-2c1d-4acd-b481-a151f0a0a36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475412767 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2475412767
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3708738508
Short name T623
Test name
Test status
Simulation time 54032740 ps
CPU time 1.88 seconds
Started Jul 29 06:21:50 PM PDT 24
Finished Jul 29 06:21:52 PM PDT 24
Peak memory 218500 kb
Host smart-612758f3-9dc6-4d48-a20d-dbd5f7bab581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708738508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3708738508
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.519187165
Short name T524
Test name
Test status
Simulation time 25124432 ps
CPU time 0.95 seconds
Started Jul 29 06:21:36 PM PDT 24
Finished Jul 29 06:21:37 PM PDT 24
Peak memory 216088 kb
Host smart-0e4dc0f7-9a95-450d-9aed-892f8d2c6722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519187165 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.519187165
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3881580898
Short name T336
Test name
Test status
Simulation time 31112972 ps
CPU time 0.95 seconds
Started Jul 29 06:21:41 PM PDT 24
Finished Jul 29 06:21:43 PM PDT 24
Peak memory 215312 kb
Host smart-a822dc99-a0cc-40f8-b06c-9e0d3ee20cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881580898 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3881580898
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.769814900
Short name T766
Test name
Test status
Simulation time 583037105 ps
CPU time 4.45 seconds
Started Jul 29 06:21:59 PM PDT 24
Finished Jul 29 06:22:04 PM PDT 24
Peak memory 220660 kb
Host smart-9c313f1d-ba19-4910-b685-941bed745d78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769814900 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.769814900
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2333813925
Short name T95
Test name
Test status
Simulation time 24825901420 ps
CPU time 607.5 seconds
Started Jul 29 06:21:51 PM PDT 24
Finished Jul 29 06:31:58 PM PDT 24
Peak memory 218372 kb
Host smart-9c76ad90-a2a5-45bb-bee2-0d5f0ed42360
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333813925 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2333813925
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert_test.544148796
Short name T875
Test name
Test status
Simulation time 25927357 ps
CPU time 0.91 seconds
Started Jul 29 06:22:07 PM PDT 24
Finished Jul 29 06:22:08 PM PDT 24
Peak memory 206668 kb
Host smart-e3811f7c-3754-4fe1-ab1d-1890355a75e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544148796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.544148796
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1407215497
Short name T956
Test name
Test status
Simulation time 27248553 ps
CPU time 0.81 seconds
Started Jul 29 06:21:53 PM PDT 24
Finished Jul 29 06:21:54 PM PDT 24
Peak memory 215864 kb
Host smart-1a6fc102-c765-4c1b-a84a-deecbe2974c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407215497 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1407215497
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2729811367
Short name T113
Test name
Test status
Simulation time 40130535 ps
CPU time 0.98 seconds
Started Jul 29 06:22:04 PM PDT 24
Finished Jul 29 06:22:06 PM PDT 24
Peak memory 218504 kb
Host smart-7965dc08-26f7-4877-941f-c1819336bb92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729811367 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2729811367
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.4152457024
Short name T133
Test name
Test status
Simulation time 20428241 ps
CPU time 1.09 seconds
Started Jul 29 06:22:05 PM PDT 24
Finished Jul 29 06:22:06 PM PDT 24
Peak memory 219568 kb
Host smart-57242126-bf50-4edf-adc1-95a09d257225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152457024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.4152457024
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.567749341
Short name T726
Test name
Test status
Simulation time 34036507 ps
CPU time 1.12 seconds
Started Jul 29 06:22:03 PM PDT 24
Finished Jul 29 06:22:04 PM PDT 24
Peak memory 218556 kb
Host smart-0b3ea3d4-442c-4148-b126-c67815e53ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567749341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.567749341
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3316505004
Short name T563
Test name
Test status
Simulation time 38006289 ps
CPU time 0.98 seconds
Started Jul 29 06:21:55 PM PDT 24
Finished Jul 29 06:21:56 PM PDT 24
Peak memory 215360 kb
Host smart-c58a5d45-0334-4a56-bac2-59a638017068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316505004 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3316505004
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3206083103
Short name T353
Test name
Test status
Simulation time 32302235 ps
CPU time 0.97 seconds
Started Jul 29 06:21:52 PM PDT 24
Finished Jul 29 06:21:53 PM PDT 24
Peak memory 215288 kb
Host smart-dc135c34-c076-4ea4-a865-6938aac5f24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206083103 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3206083103
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.818567238
Short name T918
Test name
Test status
Simulation time 51606596 ps
CPU time 1.51 seconds
Started Jul 29 06:21:42 PM PDT 24
Finished Jul 29 06:21:44 PM PDT 24
Peak memory 218388 kb
Host smart-3b7ff32d-046c-46ad-af72-32cf7046a143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818567238 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.818567238
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3652003843
Short name T220
Test name
Test status
Simulation time 220229964022 ps
CPU time 1420.71 seconds
Started Jul 29 06:21:48 PM PDT 24
Finished Jul 29 06:45:29 PM PDT 24
Peak memory 224856 kb
Host smart-838d1944-7333-4a45-b4e4-fe73bf3ecdfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652003843 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3652003843
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1497526389
Short name T614
Test name
Test status
Simulation time 30187030 ps
CPU time 1.32 seconds
Started Jul 29 06:21:43 PM PDT 24
Finished Jul 29 06:21:45 PM PDT 24
Peak memory 215632 kb
Host smart-534189e0-eab8-4046-8fb5-b9df070dc228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497526389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1497526389
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.763664674
Short name T347
Test name
Test status
Simulation time 36292408 ps
CPU time 0.82 seconds
Started Jul 29 06:21:51 PM PDT 24
Finished Jul 29 06:21:52 PM PDT 24
Peak memory 206492 kb
Host smart-c2345575-c34e-40d6-aca4-3004ce2c10e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763664674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.763664674
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.29836517
Short name T213
Test name
Test status
Simulation time 222734762 ps
CPU time 1.09 seconds
Started Jul 29 06:22:01 PM PDT 24
Finished Jul 29 06:22:02 PM PDT 24
Peak memory 219820 kb
Host smart-fa4c41dc-6009-4770-b0c4-ace05cf8df8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29836517 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_dis
able_auto_req_mode.29836517
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.186580632
Short name T719
Test name
Test status
Simulation time 37626306 ps
CPU time 0.85 seconds
Started Jul 29 06:21:49 PM PDT 24
Finished Jul 29 06:21:50 PM PDT 24
Peak memory 218472 kb
Host smart-d6ed795a-6d6f-4b47-93d1-269ca99a4fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186580632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.186580632
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.4230943561
Short name T508
Test name
Test status
Simulation time 82930280 ps
CPU time 1.21 seconds
Started Jul 29 06:22:09 PM PDT 24
Finished Jul 29 06:22:10 PM PDT 24
Peak memory 217228 kb
Host smart-7ea2c10d-fd42-4192-8dcd-e9851a7913d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230943561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.4230943561
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2078755997
Short name T577
Test name
Test status
Simulation time 22167912 ps
CPU time 1.17 seconds
Started Jul 29 06:22:05 PM PDT 24
Finished Jul 29 06:22:06 PM PDT 24
Peak memory 224016 kb
Host smart-9de2f922-1b1c-4a41-a9f2-c6196a9169c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078755997 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2078755997
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2704902803
Short name T425
Test name
Test status
Simulation time 22086350 ps
CPU time 0.85 seconds
Started Jul 29 06:21:58 PM PDT 24
Finished Jul 29 06:21:59 PM PDT 24
Peak memory 215284 kb
Host smart-b6dc93d0-a283-4b94-9cd3-4d1235049064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704902803 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2704902803
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.322019605
Short name T768
Test name
Test status
Simulation time 394994993 ps
CPU time 4.74 seconds
Started Jul 29 06:21:44 PM PDT 24
Finished Jul 29 06:21:49 PM PDT 24
Peak memory 217244 kb
Host smart-32879bc6-22ad-436b-905f-c4722c5bfb72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322019605 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.322019605
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1405997072
Short name T228
Test name
Test status
Simulation time 126275655964 ps
CPU time 1436.63 seconds
Started Jul 29 06:22:02 PM PDT 24
Finished Jul 29 06:45:59 PM PDT 24
Peak memory 222656 kb
Host smart-4e805862-20eb-419d-af96-cd03be283004
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405997072 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1405997072
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1744663174
Short name T288
Test name
Test status
Simulation time 45889280 ps
CPU time 1.22 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:21:59 PM PDT 24
Peak memory 219132 kb
Host smart-db427671-aa46-4de4-b28e-2477d6f97e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744663174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1744663174
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.817329922
Short name T744
Test name
Test status
Simulation time 13551544 ps
CPU time 0.92 seconds
Started Jul 29 06:21:54 PM PDT 24
Finished Jul 29 06:21:55 PM PDT 24
Peak memory 206648 kb
Host smart-724ad886-7726-4a9b-8890-a3fce1a53d33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817329922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.817329922
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2070827609
Short name T758
Test name
Test status
Simulation time 71464318 ps
CPU time 0.87 seconds
Started Jul 29 06:21:51 PM PDT 24
Finished Jul 29 06:21:52 PM PDT 24
Peak memory 216240 kb
Host smart-24515fde-7acc-425f-9f7f-33f44fbfe71b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070827609 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2070827609
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3133362027
Short name T448
Test name
Test status
Simulation time 116705434 ps
CPU time 1.06 seconds
Started Jul 29 06:21:53 PM PDT 24
Finished Jul 29 06:21:54 PM PDT 24
Peak memory 218632 kb
Host smart-9c1b6755-139a-47e4-94d7-8a190922d1fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133362027 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3133362027
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2346889009
Short name T196
Test name
Test status
Simulation time 20526542 ps
CPU time 1.09 seconds
Started Jul 29 06:21:55 PM PDT 24
Finished Jul 29 06:21:56 PM PDT 24
Peak memory 218312 kb
Host smart-49a92f87-b767-42b8-8451-39c814b44b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346889009 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2346889009
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.227481523
Short name T967
Test name
Test status
Simulation time 72407612 ps
CPU time 1.2 seconds
Started Jul 29 06:21:46 PM PDT 24
Finished Jul 29 06:21:48 PM PDT 24
Peak memory 219932 kb
Host smart-407a5ab0-219f-4059-b036-780f4f3ee163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227481523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.227481523
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3610903841
Short name T85
Test name
Test status
Simulation time 20728086 ps
CPU time 1.11 seconds
Started Jul 29 06:22:11 PM PDT 24
Finished Jul 29 06:22:13 PM PDT 24
Peak memory 215836 kb
Host smart-8a9d85c8-fe62-4882-a995-b50e3969eb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610903841 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3610903841
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3920680612
Short name T828
Test name
Test status
Simulation time 28585114 ps
CPU time 0.94 seconds
Started Jul 29 06:21:55 PM PDT 24
Finished Jul 29 06:22:02 PM PDT 24
Peak memory 207108 kb
Host smart-c410633e-165e-457e-ac9a-0c6d7c095bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920680612 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3920680612
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3777128221
Short name T613
Test name
Test status
Simulation time 315486785 ps
CPU time 2.71 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:22:00 PM PDT 24
Peak memory 215284 kb
Host smart-6c5afb34-964e-4668-a64c-e6460ef64256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777128221 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3777128221
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3329712191
Short name T58
Test name
Test status
Simulation time 40796983033 ps
CPU time 645.64 seconds
Started Jul 29 06:21:53 PM PDT 24
Finished Jul 29 06:32:39 PM PDT 24
Peak memory 218984 kb
Host smart-3c5ddbe6-e639-42a0-a720-7b64cd4b2d6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329712191 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3329712191
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3617180915
Short name T509
Test name
Test status
Simulation time 39030204 ps
CPU time 1.3 seconds
Started Jul 29 06:21:49 PM PDT 24
Finished Jul 29 06:21:51 PM PDT 24
Peak memory 218600 kb
Host smart-2805a45c-3aaf-4241-b5ae-aecd7021f1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617180915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3617180915
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1845262347
Short name T735
Test name
Test status
Simulation time 28560386 ps
CPU time 0.8 seconds
Started Jul 29 06:21:51 PM PDT 24
Finished Jul 29 06:21:52 PM PDT 24
Peak memory 206740 kb
Host smart-89d8351e-fe0c-4099-b975-15606076057d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845262347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1845262347
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.569736070
Short name T15
Test name
Test status
Simulation time 28891204 ps
CPU time 1.18 seconds
Started Jul 29 06:22:13 PM PDT 24
Finished Jul 29 06:22:14 PM PDT 24
Peak memory 217100 kb
Host smart-c36713cd-6ca3-42a0-87a1-d3c0c512e54d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569736070 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.569736070
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2895930659
Short name T538
Test name
Test status
Simulation time 46612005 ps
CPU time 1 seconds
Started Jul 29 06:21:46 PM PDT 24
Finished Jul 29 06:21:47 PM PDT 24
Peak memory 218620 kb
Host smart-3570c37d-894e-4fda-a1f6-58c16592638d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895930659 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2895930659
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1620786189
Short name T792
Test name
Test status
Simulation time 65280446 ps
CPU time 1.52 seconds
Started Jul 29 06:22:00 PM PDT 24
Finished Jul 29 06:22:01 PM PDT 24
Peak memory 217436 kb
Host smart-de47b959-75e5-43e6-a87d-8fed60466ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620786189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1620786189
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2353965282
Short name T82
Test name
Test status
Simulation time 21475701 ps
CPU time 1.05 seconds
Started Jul 29 06:21:55 PM PDT 24
Finished Jul 29 06:21:56 PM PDT 24
Peak memory 216764 kb
Host smart-d21d1fde-2f50-4277-b5af-f766b53a8226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353965282 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2353965282
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1613069516
Short name T407
Test name
Test status
Simulation time 15672213 ps
CPU time 0.93 seconds
Started Jul 29 06:21:50 PM PDT 24
Finished Jul 29 06:21:52 PM PDT 24
Peak memory 215292 kb
Host smart-85bf503e-e061-416b-b52e-b174069b2343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613069516 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1613069516
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1554121791
Short name T305
Test name
Test status
Simulation time 272748256 ps
CPU time 5.66 seconds
Started Jul 29 06:22:00 PM PDT 24
Finished Jul 29 06:22:06 PM PDT 24
Peak memory 220220 kb
Host smart-fa4da2dc-348b-430d-b6e4-5e375d2cd591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554121791 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1554121791
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1933000194
Short name T612
Test name
Test status
Simulation time 77986491346 ps
CPU time 379.14 seconds
Started Jul 29 06:21:50 PM PDT 24
Finished Jul 29 06:28:10 PM PDT 24
Peak memory 218728 kb
Host smart-9ee314c0-4299-497e-8ad8-c7e0146b805c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933000194 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1933000194
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1110088235
Short name T37
Test name
Test status
Simulation time 80903342 ps
CPU time 1.12 seconds
Started Jul 29 06:21:00 PM PDT 24
Finished Jul 29 06:21:02 PM PDT 24
Peak memory 218768 kb
Host smart-40dd4259-dd04-43c1-a8b3-7a2acbbba861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110088235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1110088235
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2727780634
Short name T782
Test name
Test status
Simulation time 97455265 ps
CPU time 0.83 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:04 PM PDT 24
Peak memory 206520 kb
Host smart-f9e1af2a-2e3e-4c1a-b60c-a452e957fb6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727780634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2727780634
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1859458967
Short name T565
Test name
Test status
Simulation time 29154328 ps
CPU time 0.83 seconds
Started Jul 29 06:21:00 PM PDT 24
Finished Jul 29 06:21:01 PM PDT 24
Peak memory 215896 kb
Host smart-a297feb7-b45b-44b4-b5cf-086549e592df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859458967 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1859458967
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1515224289
Short name T135
Test name
Test status
Simulation time 65914565 ps
CPU time 0.98 seconds
Started Jul 29 06:21:06 PM PDT 24
Finished Jul 29 06:21:07 PM PDT 24
Peak memory 216760 kb
Host smart-354a0890-8abe-4774-9739-815c20e4c5ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515224289 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1515224289
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3875757751
Short name T460
Test name
Test status
Simulation time 18195678 ps
CPU time 1.19 seconds
Started Jul 29 06:21:04 PM PDT 24
Finished Jul 29 06:21:05 PM PDT 24
Peak memory 224020 kb
Host smart-38d10780-59bf-47a6-bdb1-9cce424e36e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875757751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3875757751
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.633162327
Short name T331
Test name
Test status
Simulation time 62840368 ps
CPU time 1.28 seconds
Started Jul 29 06:20:57 PM PDT 24
Finished Jul 29 06:20:59 PM PDT 24
Peak memory 218376 kb
Host smart-1f9c1aff-b897-4759-a16d-3187934cefe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633162327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.633162327
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2917906028
Short name T403
Test name
Test status
Simulation time 20926916 ps
CPU time 1.07 seconds
Started Jul 29 06:21:11 PM PDT 24
Finished Jul 29 06:21:12 PM PDT 24
Peak memory 215444 kb
Host smart-6e32bcac-862c-4b62-8837-66ff9a430aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917906028 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2917906028
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2712301439
Short name T655
Test name
Test status
Simulation time 40154589 ps
CPU time 0.92 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:04 PM PDT 24
Peak memory 207100 kb
Host smart-0d194479-b507-43ff-94f6-3abe2852b7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712301439 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2712301439
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.734806243
Short name T497
Test name
Test status
Simulation time 18633808 ps
CPU time 1.01 seconds
Started Jul 29 06:21:05 PM PDT 24
Finished Jul 29 06:21:06 PM PDT 24
Peak memory 215248 kb
Host smart-6d0f7aa6-840b-4bc3-a3b9-720fc92ebccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734806243 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.734806243
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1700810376
Short name T760
Test name
Test status
Simulation time 140089901 ps
CPU time 3.12 seconds
Started Jul 29 06:21:04 PM PDT 24
Finished Jul 29 06:21:08 PM PDT 24
Peak memory 218628 kb
Host smart-58e1410c-3075-4dce-a72e-9368f19fdcf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700810376 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1700810376
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.4214067178
Short name T636
Test name
Test status
Simulation time 114572182559 ps
CPU time 681.14 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:32:24 PM PDT 24
Peak memory 220044 kb
Host smart-c3886955-dd79-4743-a36a-894cbfc42a99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214067178 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.4214067178
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2900527142
Short name T684
Test name
Test status
Simulation time 70037926 ps
CPU time 1.11 seconds
Started Jul 29 06:22:24 PM PDT 24
Finished Jul 29 06:22:25 PM PDT 24
Peak memory 219912 kb
Host smart-dd429148-826d-4669-a70b-ba6bf71fb032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900527142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2900527142
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1224797822
Short name T377
Test name
Test status
Simulation time 24143706 ps
CPU time 0.89 seconds
Started Jul 29 06:21:47 PM PDT 24
Finished Jul 29 06:21:48 PM PDT 24
Peak memory 206668 kb
Host smart-9df5cf2e-40d0-4591-ab50-da721c5bebec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224797822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1224797822
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.4026302858
Short name T597
Test name
Test status
Simulation time 10465695 ps
CPU time 0.86 seconds
Started Jul 29 06:22:01 PM PDT 24
Finished Jul 29 06:22:02 PM PDT 24
Peak memory 216084 kb
Host smart-c7e8b6fe-643a-4cfd-a918-299a5016b346
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026302858 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.4026302858
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3099805888
Short name T494
Test name
Test status
Simulation time 33242080 ps
CPU time 0.97 seconds
Started Jul 29 06:21:53 PM PDT 24
Finished Jul 29 06:21:55 PM PDT 24
Peak memory 218584 kb
Host smart-b79e72c7-7a6d-4cda-9d0b-78e763452d2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099805888 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3099805888
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1224062485
Short name T52
Test name
Test status
Simulation time 19594243 ps
CPU time 1.15 seconds
Started Jul 29 06:21:48 PM PDT 24
Finished Jul 29 06:21:50 PM PDT 24
Peak memory 224060 kb
Host smart-f258db03-17e0-4e2d-a1ff-e1ae42bc0ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224062485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1224062485
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.722355477
Short name T774
Test name
Test status
Simulation time 96842242 ps
CPU time 1.15 seconds
Started Jul 29 06:21:48 PM PDT 24
Finished Jul 29 06:21:50 PM PDT 24
Peak memory 218612 kb
Host smart-6b856224-4fcb-4453-a163-77d654a412d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722355477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.722355477
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1853652392
Short name T361
Test name
Test status
Simulation time 23790190 ps
CPU time 1.02 seconds
Started Jul 29 06:22:10 PM PDT 24
Finished Jul 29 06:22:12 PM PDT 24
Peak memory 215348 kb
Host smart-b2dcbd45-bdf1-4492-a92e-a61a255e10c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853652392 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1853652392
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1724319361
Short name T340
Test name
Test status
Simulation time 18264696 ps
CPU time 1.02 seconds
Started Jul 29 06:21:51 PM PDT 24
Finished Jul 29 06:21:52 PM PDT 24
Peak memory 215300 kb
Host smart-9cf832b0-0972-4648-8543-ebcafb001473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724319361 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1724319361
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2981848757
Short name T564
Test name
Test status
Simulation time 141867087 ps
CPU time 3.22 seconds
Started Jul 29 06:21:54 PM PDT 24
Finished Jul 29 06:21:57 PM PDT 24
Peak memory 217324 kb
Host smart-1103caa1-6e5a-443d-838b-81f7a585d82b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981848757 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2981848757
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.551442380
Short name T223
Test name
Test status
Simulation time 16250771113 ps
CPU time 149.78 seconds
Started Jul 29 06:21:52 PM PDT 24
Finished Jul 29 06:24:22 PM PDT 24
Peak memory 221204 kb
Host smart-f937c98a-b7a5-48b9-b799-f0cc84189943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551442380 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.551442380
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert_test.2100837489
Short name T905
Test name
Test status
Simulation time 31747369 ps
CPU time 0.98 seconds
Started Jul 29 06:21:54 PM PDT 24
Finished Jul 29 06:21:55 PM PDT 24
Peak memory 206608 kb
Host smart-ee89fd12-7979-4fbb-9877-df467b7c26ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100837489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2100837489
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3667610002
Short name T120
Test name
Test status
Simulation time 64510436 ps
CPU time 0.83 seconds
Started Jul 29 06:22:07 PM PDT 24
Finished Jul 29 06:22:08 PM PDT 24
Peak memory 216240 kb
Host smart-9ec10d91-c342-4a0e-a041-94fbb8cc3ccb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667610002 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3667610002
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.496446588
Short name T153
Test name
Test status
Simulation time 63375277 ps
CPU time 1.14 seconds
Started Jul 29 06:21:55 PM PDT 24
Finished Jul 29 06:21:56 PM PDT 24
Peak memory 216884 kb
Host smart-d78b516f-e3eb-476a-a879-394062ac024f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496446588 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.496446588
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.118576619
Short name T528
Test name
Test status
Simulation time 19367300 ps
CPU time 1.18 seconds
Started Jul 29 06:21:55 PM PDT 24
Finished Jul 29 06:21:57 PM PDT 24
Peak memory 224044 kb
Host smart-9618451c-1b01-42ad-8526-6e9158f3ed0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118576619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.118576619
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2980747359
Short name T607
Test name
Test status
Simulation time 60609458 ps
CPU time 1.13 seconds
Started Jul 29 06:22:04 PM PDT 24
Finished Jul 29 06:22:05 PM PDT 24
Peak memory 218624 kb
Host smart-1e61e556-2286-41aa-9e2b-da158f14acd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980747359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2980747359
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2239163045
Short name T518
Test name
Test status
Simulation time 35679844 ps
CPU time 0.93 seconds
Started Jul 29 06:21:55 PM PDT 24
Finished Jul 29 06:21:56 PM PDT 24
Peak memory 215272 kb
Host smart-c9561778-6b48-4e7d-8987-f9c273692448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239163045 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2239163045
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.403855297
Short name T693
Test name
Test status
Simulation time 62200818 ps
CPU time 0.88 seconds
Started Jul 29 06:21:55 PM PDT 24
Finished Jul 29 06:21:56 PM PDT 24
Peak memory 215328 kb
Host smart-067b7ed6-1031-43cc-b389-c5fa95deb384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403855297 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.403855297
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3043928114
Short name T354
Test name
Test status
Simulation time 520084740 ps
CPU time 3.6 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:22:01 PM PDT 24
Peak memory 218472 kb
Host smart-e830b98c-b141-40a9-9d00-82971066ba0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043928114 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3043928114
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3698147542
Short name T311
Test name
Test status
Simulation time 84829456923 ps
CPU time 1955.76 seconds
Started Jul 29 06:21:48 PM PDT 24
Finished Jul 29 06:54:24 PM PDT 24
Peak memory 226096 kb
Host smart-87ec111e-89fa-4d00-b6e1-ddbf4203c6ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698147542 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3698147542
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3998350184
Short name T193
Test name
Test status
Simulation time 50116838 ps
CPU time 1.19 seconds
Started Jul 29 06:21:56 PM PDT 24
Finished Jul 29 06:21:58 PM PDT 24
Peak memory 218536 kb
Host smart-d16c2569-f2e5-483f-b5de-c937707a1fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998350184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3998350184
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.953545120
Short name T45
Test name
Test status
Simulation time 25496039 ps
CPU time 0.92 seconds
Started Jul 29 06:22:11 PM PDT 24
Finished Jul 29 06:22:12 PM PDT 24
Peak memory 206664 kb
Host smart-8ea83b6c-6408-48ed-834a-4aa1c31ee07a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953545120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.953545120
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2709601023
Short name T706
Test name
Test status
Simulation time 13681539 ps
CPU time 0.91 seconds
Started Jul 29 06:21:54 PM PDT 24
Finished Jul 29 06:21:55 PM PDT 24
Peak memory 215596 kb
Host smart-7a2fc15c-b22e-4336-85d0-42a168868276
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709601023 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2709601023
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1458685875
Short name T138
Test name
Test status
Simulation time 96236081 ps
CPU time 1.16 seconds
Started Jul 29 06:21:59 PM PDT 24
Finished Jul 29 06:22:01 PM PDT 24
Peak memory 216908 kb
Host smart-9f98bda9-32c4-4519-a8ca-5135b9748057
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458685875 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1458685875
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3264969723
Short name T590
Test name
Test status
Simulation time 35298269 ps
CPU time 1.16 seconds
Started Jul 29 06:21:58 PM PDT 24
Finished Jul 29 06:22:00 PM PDT 24
Peak memory 220792 kb
Host smart-224630b4-6a3d-4a45-a070-0920a5098342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264969723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3264969723
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1023620777
Short name T742
Test name
Test status
Simulation time 171571504 ps
CPU time 2.41 seconds
Started Jul 29 06:21:52 PM PDT 24
Finished Jul 29 06:21:55 PM PDT 24
Peak memory 220156 kb
Host smart-f8929de6-9d9e-4c90-b9c7-5fe713d0ba5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023620777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1023620777
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3629097318
Short name T627
Test name
Test status
Simulation time 51786678 ps
CPU time 0.85 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:21:58 PM PDT 24
Peak memory 215352 kb
Host smart-64673b84-6c01-4697-b1a1-2728907e81c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629097318 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3629097318
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.706252047
Short name T814
Test name
Test status
Simulation time 48322028 ps
CPU time 0.96 seconds
Started Jul 29 06:22:00 PM PDT 24
Finished Jul 29 06:22:01 PM PDT 24
Peak memory 215324 kb
Host smart-c68e842f-3e7b-46b9-b0d0-78f9e386bcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706252047 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.706252047
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3050108341
Short name T688
Test name
Test status
Simulation time 127593546 ps
CPU time 1.83 seconds
Started Jul 29 06:21:55 PM PDT 24
Finished Jul 29 06:21:56 PM PDT 24
Peak memory 215292 kb
Host smart-aee4da94-6123-4fa1-89b7-191047d23e74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050108341 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3050108341
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.764637815
Short name T438
Test name
Test status
Simulation time 42237638726 ps
CPU time 527.2 seconds
Started Jul 29 06:22:03 PM PDT 24
Finished Jul 29 06:30:51 PM PDT 24
Peak memory 217276 kb
Host smart-f4cc6baf-d3ab-46b6-b327-bb006f46fae4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764637815 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.764637815
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.71733546
Short name T146
Test name
Test status
Simulation time 40491183 ps
CPU time 1.17 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:21:59 PM PDT 24
Peak memory 219372 kb
Host smart-67345423-f7cc-4467-8876-bc6451237880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71733546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.71733546
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1265560716
Short name T773
Test name
Test status
Simulation time 18954077 ps
CPU time 0.83 seconds
Started Jul 29 06:22:09 PM PDT 24
Finished Jul 29 06:22:10 PM PDT 24
Peak memory 206776 kb
Host smart-d80aa9c1-72a2-4930-8e0c-572493547113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265560716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1265560716
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1584172437
Short name T733
Test name
Test status
Simulation time 33598936 ps
CPU time 1.14 seconds
Started Jul 29 06:22:19 PM PDT 24
Finished Jul 29 06:22:20 PM PDT 24
Peak memory 218380 kb
Host smart-eeb971b6-d3fd-4044-806e-b975e8ee8a3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584172437 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1584172437
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_genbits.3360285600
Short name T916
Test name
Test status
Simulation time 41021443 ps
CPU time 1.11 seconds
Started Jul 29 06:21:49 PM PDT 24
Finished Jul 29 06:21:50 PM PDT 24
Peak memory 218528 kb
Host smart-08e6e1ef-908d-4bbb-827d-e4f19aefab24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360285600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3360285600
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3702183061
Short name T87
Test name
Test status
Simulation time 37619103 ps
CPU time 0.88 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:21:58 PM PDT 24
Peak memory 215716 kb
Host smart-602d906d-9f10-4aac-b7a3-2f9b069f6a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702183061 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3702183061
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2470170253
Short name T327
Test name
Test status
Simulation time 52526830 ps
CPU time 0.93 seconds
Started Jul 29 06:21:59 PM PDT 24
Finished Jul 29 06:22:00 PM PDT 24
Peak memory 215288 kb
Host smart-669e457b-3a07-427d-a520-8a23a8a18e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470170253 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2470170253
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2021121921
Short name T333
Test name
Test status
Simulation time 68440112 ps
CPU time 1.8 seconds
Started Jul 29 06:22:08 PM PDT 24
Finished Jul 29 06:22:09 PM PDT 24
Peak memory 217196 kb
Host smart-08055591-0c7d-4a08-a9ff-f1ddc26e0990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021121921 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2021121921
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_alert.1153230330
Short name T212
Test name
Test status
Simulation time 238157157 ps
CPU time 1.34 seconds
Started Jul 29 06:21:54 PM PDT 24
Finished Jul 29 06:21:55 PM PDT 24
Peak memory 218332 kb
Host smart-f1cb9f2f-e2a0-4562-91b3-936e4c8871e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153230330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1153230330
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3289917367
Short name T838
Test name
Test status
Simulation time 164379186 ps
CPU time 0.91 seconds
Started Jul 29 06:22:03 PM PDT 24
Finished Jul 29 06:22:04 PM PDT 24
Peak memory 214844 kb
Host smart-f79b4b3e-6a35-4650-89a8-d839d6657331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289917367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3289917367
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1093784822
Short name T449
Test name
Test status
Simulation time 21480874 ps
CPU time 0.91 seconds
Started Jul 29 06:22:05 PM PDT 24
Finished Jul 29 06:22:06 PM PDT 24
Peak memory 215580 kb
Host smart-a62781f2-f3e3-4db9-93a6-d681a235b98c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093784822 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1093784822
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1790054845
Short name T973
Test name
Test status
Simulation time 57199700 ps
CPU time 1.16 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:21:59 PM PDT 24
Peak memory 216744 kb
Host smart-2f3ae790-548d-451d-9d1d-25edf2fe78c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790054845 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1790054845
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.184113607
Short name T575
Test name
Test status
Simulation time 23714913 ps
CPU time 1.23 seconds
Started Jul 29 06:22:05 PM PDT 24
Finished Jul 29 06:22:06 PM PDT 24
Peak memory 218280 kb
Host smart-e9171cd6-a576-42d3-af45-706a66b0046a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184113607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.184113607
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.22214630
Short name T444
Test name
Test status
Simulation time 23107876 ps
CPU time 1.19 seconds
Started Jul 29 06:22:03 PM PDT 24
Finished Jul 29 06:22:04 PM PDT 24
Peak memory 218476 kb
Host smart-dd91cb94-0751-48a4-90fa-ee1d7a381f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22214630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.22214630
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2308809225
Short name T582
Test name
Test status
Simulation time 38638124 ps
CPU time 0.91 seconds
Started Jul 29 06:22:09 PM PDT 24
Finished Jul 29 06:22:10 PM PDT 24
Peak memory 215420 kb
Host smart-8386ef19-fe5f-471f-a2c2-aa4b70842ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308809225 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2308809225
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1967020334
Short name T772
Test name
Test status
Simulation time 27432065 ps
CPU time 0.93 seconds
Started Jul 29 06:21:59 PM PDT 24
Finished Jul 29 06:22:00 PM PDT 24
Peak memory 215328 kb
Host smart-1e606283-49c2-4d95-8e59-bcad55d1df72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967020334 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1967020334
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2338610057
Short name T387
Test name
Test status
Simulation time 1673717562 ps
CPU time 4.41 seconds
Started Jul 29 06:22:07 PM PDT 24
Finished Jul 29 06:22:11 PM PDT 24
Peak memory 215300 kb
Host smart-bc429e4a-fb1a-4f03-9082-fb538b8e16ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338610057 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2338610057
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3759865908
Short name T230
Test name
Test status
Simulation time 2610492622 ps
CPU time 49.75 seconds
Started Jul 29 06:22:03 PM PDT 24
Finished Jul 29 06:22:53 PM PDT 24
Peak memory 219544 kb
Host smart-6d16c235-f002-48e6-925f-7ded43dc71b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759865908 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3759865908
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.295195132
Short name T267
Test name
Test status
Simulation time 71798801 ps
CPU time 1.29 seconds
Started Jul 29 06:22:06 PM PDT 24
Finished Jul 29 06:22:07 PM PDT 24
Peak memory 220360 kb
Host smart-3770366c-b595-45cd-a6de-5b81741165d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295195132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.295195132
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2694549609
Short name T552
Test name
Test status
Simulation time 59564053 ps
CPU time 0.93 seconds
Started Jul 29 06:22:00 PM PDT 24
Finished Jul 29 06:22:01 PM PDT 24
Peak memory 214804 kb
Host smart-4f704d75-9d98-4424-a880-6c37ff58c11b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694549609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2694549609
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2050798522
Short name T174
Test name
Test status
Simulation time 72667607 ps
CPU time 0.88 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:21:58 PM PDT 24
Peak memory 215396 kb
Host smart-d0137a82-d6e3-4f50-8a48-1dc52b57e41b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050798522 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2050798522
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1484009221
Short name T492
Test name
Test status
Simulation time 93661550 ps
CPU time 1.1 seconds
Started Jul 29 06:22:18 PM PDT 24
Finished Jul 29 06:22:19 PM PDT 24
Peak memory 217012 kb
Host smart-eeddf255-9185-4342-9d64-0affd9fed4e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484009221 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1484009221
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3111044225
Short name T118
Test name
Test status
Simulation time 75731522 ps
CPU time 0.97 seconds
Started Jul 29 06:21:55 PM PDT 24
Finished Jul 29 06:21:57 PM PDT 24
Peak memory 229452 kb
Host smart-33985a71-2cdd-4d1b-b1cc-3ab7c7988bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111044225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3111044225
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1847674
Short name T72
Test name
Test status
Simulation time 38063390 ps
CPU time 1.64 seconds
Started Jul 29 06:21:59 PM PDT 24
Finished Jul 29 06:22:01 PM PDT 24
Peak memory 218460 kb
Host smart-d4d720b1-f5b5-46e4-b931-37c04485f3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1847674
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2114346030
Short name T686
Test name
Test status
Simulation time 32977925 ps
CPU time 0.91 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:21:58 PM PDT 24
Peak memory 215336 kb
Host smart-633b719f-40eb-498e-9db5-13faa5b3032c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114346030 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2114346030
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.336215679
Short name T879
Test name
Test status
Simulation time 83452096 ps
CPU time 0.92 seconds
Started Jul 29 06:22:02 PM PDT 24
Finished Jul 29 06:22:03 PM PDT 24
Peak memory 215068 kb
Host smart-981f7d11-b99d-4106-b1a9-379b161a18c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336215679 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.336215679
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1882969827
Short name T777
Test name
Test status
Simulation time 142029178 ps
CPU time 3.36 seconds
Started Jul 29 06:22:03 PM PDT 24
Finished Jul 29 06:22:06 PM PDT 24
Peak memory 217180 kb
Host smart-7f09ee1c-af93-4d97-b64a-b203e4745231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882969827 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1882969827
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1495724670
Short name T584
Test name
Test status
Simulation time 103252693316 ps
CPU time 1140.01 seconds
Started Jul 29 06:22:11 PM PDT 24
Finished Jul 29 06:41:11 PM PDT 24
Peak memory 222528 kb
Host smart-2e98c110-f6b5-4b88-919b-c7530da4fd85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495724670 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1495724670
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2664619600
Short name T157
Test name
Test status
Simulation time 47221438 ps
CPU time 1.28 seconds
Started Jul 29 06:21:58 PM PDT 24
Finished Jul 29 06:22:00 PM PDT 24
Peak memory 215700 kb
Host smart-14ab1560-0942-4786-85f7-11cb5f5e5d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664619600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2664619600
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2980509648
Short name T475
Test name
Test status
Simulation time 25097048 ps
CPU time 0.8 seconds
Started Jul 29 06:22:09 PM PDT 24
Finished Jul 29 06:22:09 PM PDT 24
Peak memory 206296 kb
Host smart-3159a4f3-693f-4f41-8750-2b34d0380436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980509648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2980509648
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.215448511
Short name T199
Test name
Test status
Simulation time 25232370 ps
CPU time 0.96 seconds
Started Jul 29 06:22:09 PM PDT 24
Finished Jul 29 06:22:10 PM PDT 24
Peak memory 216208 kb
Host smart-904d449a-0827-406b-afaa-f4f462f60573
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215448511 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.215448511
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.4041119383
Short name T115
Test name
Test status
Simulation time 48460005 ps
CPU time 1.41 seconds
Started Jul 29 06:22:03 PM PDT 24
Finished Jul 29 06:22:05 PM PDT 24
Peak memory 219388 kb
Host smart-3fc03a7b-a3df-4ff7-b60e-8fed7b8d9351
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041119383 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.4041119383
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2354764396
Short name T578
Test name
Test status
Simulation time 22362786 ps
CPU time 0.94 seconds
Started Jul 29 06:21:58 PM PDT 24
Finished Jul 29 06:21:59 PM PDT 24
Peak memory 218748 kb
Host smart-0c8af863-bc45-43f3-b4c8-ec6efe0affd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354764396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2354764396
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.236855344
Short name T64
Test name
Test status
Simulation time 121648386 ps
CPU time 1.17 seconds
Started Jul 29 06:21:59 PM PDT 24
Finished Jul 29 06:22:01 PM PDT 24
Peak memory 217424 kb
Host smart-f9140c53-f6e8-4266-884e-3710441c8bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236855344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.236855344
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1987293106
Short name T794
Test name
Test status
Simulation time 31434249 ps
CPU time 0.89 seconds
Started Jul 29 06:22:08 PM PDT 24
Finished Jul 29 06:22:09 PM PDT 24
Peak memory 215520 kb
Host smart-98f5c734-ecd5-4c54-81b3-843d2c540053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987293106 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1987293106
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3901147987
Short name T502
Test name
Test status
Simulation time 30188202 ps
CPU time 0.98 seconds
Started Jul 29 06:21:57 PM PDT 24
Finished Jul 29 06:21:59 PM PDT 24
Peak memory 215316 kb
Host smart-e203b53c-d6b9-442c-863b-72d2fb0f8959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901147987 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3901147987
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3894345320
Short name T850
Test name
Test status
Simulation time 854268909 ps
CPU time 5.33 seconds
Started Jul 29 06:22:16 PM PDT 24
Finished Jul 29 06:22:22 PM PDT 24
Peak memory 217404 kb
Host smart-8d25285e-d611-45b4-b1b8-e7bcedccd9d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894345320 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3894345320
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.767253217
Short name T388
Test name
Test status
Simulation time 99577364695 ps
CPU time 1345.91 seconds
Started Jul 29 06:21:59 PM PDT 24
Finished Jul 29 06:44:26 PM PDT 24
Peak memory 224468 kb
Host smart-4e8fb5fb-2408-4934-a279-6aac0bfc41bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767253217 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.767253217
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1609601232
Short name T236
Test name
Test status
Simulation time 56753856 ps
CPU time 1.2 seconds
Started Jul 29 06:22:06 PM PDT 24
Finished Jul 29 06:22:08 PM PDT 24
Peak memory 215680 kb
Host smart-649a7f67-f7d7-4e81-afbd-ecf9541f7797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609601232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1609601232
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1743640282
Short name T554
Test name
Test status
Simulation time 13756777 ps
CPU time 0.88 seconds
Started Jul 29 06:22:25 PM PDT 24
Finished Jul 29 06:22:26 PM PDT 24
Peak memory 206920 kb
Host smart-6731648e-3e5f-4adc-8769-658160d1b2ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743640282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1743640282
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2882285190
Short name T189
Test name
Test status
Simulation time 23750820 ps
CPU time 0.83 seconds
Started Jul 29 06:22:26 PM PDT 24
Finished Jul 29 06:22:27 PM PDT 24
Peak memory 216124 kb
Host smart-637d97eb-5dfc-4297-b596-7367ccea5a55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882285190 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2882285190
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3739365731
Short name T592
Test name
Test status
Simulation time 38486153 ps
CPU time 1.3 seconds
Started Jul 29 06:22:19 PM PDT 24
Finished Jul 29 06:22:20 PM PDT 24
Peak memory 216896 kb
Host smart-14c6b065-a5be-4aed-b93d-2bb1f584ec92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739365731 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3739365731
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3653221057
Short name T837
Test name
Test status
Simulation time 18766388 ps
CPU time 1.13 seconds
Started Jul 29 06:22:16 PM PDT 24
Finished Jul 29 06:22:17 PM PDT 24
Peak memory 218296 kb
Host smart-34b4f926-92eb-4577-9700-441412426e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653221057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3653221057
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2497860341
Short name T587
Test name
Test status
Simulation time 46338091 ps
CPU time 1.59 seconds
Started Jul 29 06:22:02 PM PDT 24
Finished Jul 29 06:22:03 PM PDT 24
Peak memory 220068 kb
Host smart-28d7c810-c3f9-49eb-a8a8-59304a09923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497860341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2497860341
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.59740893
Short name T352
Test name
Test status
Simulation time 21737662 ps
CPU time 1.08 seconds
Started Jul 29 06:22:05 PM PDT 24
Finished Jul 29 06:22:06 PM PDT 24
Peak memory 215812 kb
Host smart-fc39886b-bfcf-4421-a61f-d07b0ef9d2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59740893 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.59740893
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1364173397
Short name T615
Test name
Test status
Simulation time 31463906 ps
CPU time 1.02 seconds
Started Jul 29 06:22:08 PM PDT 24
Finished Jul 29 06:22:09 PM PDT 24
Peak memory 215340 kb
Host smart-ce2c4875-a082-4f44-9dce-13ca72c099cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364173397 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1364173397
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3623126785
Short name T240
Test name
Test status
Simulation time 254195807 ps
CPU time 1.74 seconds
Started Jul 29 06:22:07 PM PDT 24
Finished Jul 29 06:22:09 PM PDT 24
Peak memory 215284 kb
Host smart-2d130523-0edb-4eb0-adbc-1ea8b5a77f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623126785 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3623126785
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.266940528
Short name T732
Test name
Test status
Simulation time 260332666665 ps
CPU time 1561.57 seconds
Started Jul 29 06:22:03 PM PDT 24
Finished Jul 29 06:48:05 PM PDT 24
Peak memory 223888 kb
Host smart-e033e6c5-84ce-4993-9597-202f36b93101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266940528 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.266940528
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2210301658
Short name T609
Test name
Test status
Simulation time 49081732 ps
CPU time 1.22 seconds
Started Jul 29 06:22:33 PM PDT 24
Finished Jul 29 06:22:34 PM PDT 24
Peak memory 219776 kb
Host smart-7a040bd3-50a8-46f4-96b7-ace81759eafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210301658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2210301658
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.877791072
Short name T884
Test name
Test status
Simulation time 11942340 ps
CPU time 0.92 seconds
Started Jul 29 06:22:12 PM PDT 24
Finished Jul 29 06:22:13 PM PDT 24
Peak memory 206744 kb
Host smart-5263442f-5f6c-49eb-a330-5ebda48b2958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877791072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.877791072
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2395090250
Short name T374
Test name
Test status
Simulation time 13930235 ps
CPU time 0.92 seconds
Started Jul 29 06:22:33 PM PDT 24
Finished Jul 29 06:22:34 PM PDT 24
Peak memory 216072 kb
Host smart-2e6f4d54-8373-4a24-9243-be5a8efdc68e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395090250 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2395090250
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_err.3401393378
Short name T784
Test name
Test status
Simulation time 19425938 ps
CPU time 1.07 seconds
Started Jul 29 06:22:23 PM PDT 24
Finished Jul 29 06:22:24 PM PDT 24
Peak memory 218804 kb
Host smart-9987323e-93cb-43cb-9e35-03bd47344b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401393378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3401393378
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.806061117
Short name T381
Test name
Test status
Simulation time 135760255 ps
CPU time 1.35 seconds
Started Jul 29 06:22:24 PM PDT 24
Finished Jul 29 06:22:25 PM PDT 24
Peak memory 218832 kb
Host smart-5d2159ad-61d2-4ad6-8830-9e2dd470df40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806061117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.806061117
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1612118609
Short name T392
Test name
Test status
Simulation time 21965139 ps
CPU time 1.1 seconds
Started Jul 29 06:22:31 PM PDT 24
Finished Jul 29 06:22:32 PM PDT 24
Peak memory 215364 kb
Host smart-46307f61-4325-48c1-854e-df8a33795307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612118609 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1612118609
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3607970982
Short name T459
Test name
Test status
Simulation time 25016446 ps
CPU time 0.95 seconds
Started Jul 29 06:22:10 PM PDT 24
Finished Jul 29 06:22:11 PM PDT 24
Peak memory 215248 kb
Host smart-2f311859-3c47-4695-9a76-794795090327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607970982 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3607970982
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2501881497
Short name T451
Test name
Test status
Simulation time 298827608 ps
CPU time 3.48 seconds
Started Jul 29 06:22:31 PM PDT 24
Finished Jul 29 06:22:34 PM PDT 24
Peak memory 215268 kb
Host smart-1d4d2c4c-cea5-418c-8124-ccacc3a424c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501881497 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2501881497
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2071393758
Short name T785
Test name
Test status
Simulation time 61699422631 ps
CPU time 531.22 seconds
Started Jul 29 06:22:28 PM PDT 24
Finished Jul 29 06:31:20 PM PDT 24
Peak memory 218312 kb
Host smart-dffa1545-e9b8-4121-a106-db3bffd06029
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071393758 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2071393758
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.4243362621
Short name T487
Test name
Test status
Simulation time 30721364 ps
CPU time 1.35 seconds
Started Jul 29 06:22:23 PM PDT 24
Finished Jul 29 06:22:25 PM PDT 24
Peak memory 219720 kb
Host smart-9b17af43-448f-4ea8-bf82-61b81edb16ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243362621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.4243362621
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1191719784
Short name T885
Test name
Test status
Simulation time 53485775 ps
CPU time 1.01 seconds
Started Jul 29 06:22:17 PM PDT 24
Finished Jul 29 06:22:19 PM PDT 24
Peak memory 215112 kb
Host smart-53580c05-2337-4cac-8d38-4c6fd0e457df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191719784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1191719784
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3881760208
Short name T514
Test name
Test status
Simulation time 17321115 ps
CPU time 0.93 seconds
Started Jul 29 06:22:15 PM PDT 24
Finished Jul 29 06:22:16 PM PDT 24
Peak memory 215768 kb
Host smart-821e7d5b-7411-4afc-ba78-f9bebeb1b3de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881760208 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3881760208
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.4267877643
Short name T151
Test name
Test status
Simulation time 51479252 ps
CPU time 1.57 seconds
Started Jul 29 06:22:14 PM PDT 24
Finished Jul 29 06:22:16 PM PDT 24
Peak memory 219484 kb
Host smart-3a8c6593-c187-4a2b-8875-e7157908b7ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267877643 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.4267877643
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1287478037
Short name T867
Test name
Test status
Simulation time 20234202 ps
CPU time 1.07 seconds
Started Jul 29 06:22:20 PM PDT 24
Finished Jul 29 06:22:21 PM PDT 24
Peak memory 219380 kb
Host smart-d9ace772-e34b-4df3-8986-8fe2a1c0d9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287478037 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1287478037
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1298613184
Short name T295
Test name
Test status
Simulation time 42215670 ps
CPU time 1.24 seconds
Started Jul 29 06:22:09 PM PDT 24
Finished Jul 29 06:22:11 PM PDT 24
Peak memory 217160 kb
Host smart-0ab37355-864b-4fe6-8361-298bd8a2586d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298613184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1298613184
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2488998003
Short name T208
Test name
Test status
Simulation time 42962685 ps
CPU time 0.92 seconds
Started Jul 29 06:22:15 PM PDT 24
Finished Jul 29 06:22:16 PM PDT 24
Peak memory 215316 kb
Host smart-ca4d50af-53ee-4911-9201-578d51c32c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488998003 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2488998003
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.4256400055
Short name T330
Test name
Test status
Simulation time 17680581 ps
CPU time 0.98 seconds
Started Jul 29 06:22:22 PM PDT 24
Finished Jul 29 06:22:23 PM PDT 24
Peak memory 215312 kb
Host smart-6e946683-47aa-4b83-a9ac-bafde612e52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256400055 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.4256400055
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2513099631
Short name T680
Test name
Test status
Simulation time 1595190565 ps
CPU time 4.28 seconds
Started Jul 29 06:22:10 PM PDT 24
Finished Jul 29 06:22:14 PM PDT 24
Peak memory 215312 kb
Host smart-d107992d-5799-44bb-9585-536f94584601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513099631 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2513099631
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.788036290
Short name T22
Test name
Test status
Simulation time 26284901298 ps
CPU time 605.26 seconds
Started Jul 29 06:22:32 PM PDT 24
Finished Jul 29 06:32:37 PM PDT 24
Peak memory 218716 kb
Host smart-742ab2ed-c163-4070-ba26-e0c35da207df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788036290 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.788036290
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1802554686
Short name T285
Test name
Test status
Simulation time 26371832 ps
CPU time 1.22 seconds
Started Jul 29 06:21:20 PM PDT 24
Finished Jul 29 06:21:21 PM PDT 24
Peak memory 219804 kb
Host smart-e1eaaedb-cede-4fd3-b94d-01d5b93cb841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802554686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1802554686
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.4227598616
Short name T652
Test name
Test status
Simulation time 21236560 ps
CPU time 0.81 seconds
Started Jul 29 06:21:01 PM PDT 24
Finished Jul 29 06:21:02 PM PDT 24
Peak memory 206496 kb
Host smart-5531a179-e23f-4d8a-b0c4-809dfc64492d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227598616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.4227598616
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.4242130282
Short name T132
Test name
Test status
Simulation time 118031563 ps
CPU time 0.89 seconds
Started Jul 29 06:21:01 PM PDT 24
Finished Jul 29 06:21:02 PM PDT 24
Peak memory 216220 kb
Host smart-8ead7021-1816-49de-af20-07b9caf2fea4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242130282 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.4242130282
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.722387876
Short name T423
Test name
Test status
Simulation time 74243794 ps
CPU time 1 seconds
Started Jul 29 06:20:56 PM PDT 24
Finished Jul 29 06:20:57 PM PDT 24
Peak memory 216772 kb
Host smart-2832257c-76e6-4390-ae7d-3ba796471b88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722387876 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.722387876
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2800967143
Short name T488
Test name
Test status
Simulation time 23695429 ps
CPU time 0.99 seconds
Started Jul 29 06:21:00 PM PDT 24
Finished Jul 29 06:21:02 PM PDT 24
Peak memory 218848 kb
Host smart-97d7aeea-ac46-4271-8b32-f265736921fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800967143 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2800967143
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1090249276
Short name T281
Test name
Test status
Simulation time 48729413 ps
CPU time 1.17 seconds
Started Jul 29 06:21:17 PM PDT 24
Finished Jul 29 06:21:18 PM PDT 24
Peak memory 218680 kb
Host smart-2c4ccb83-529d-4f4b-b02f-79d41eaaae08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090249276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1090249276
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1387249105
Short name T209
Test name
Test status
Simulation time 33165690 ps
CPU time 0.88 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:04 PM PDT 24
Peak memory 215168 kb
Host smart-e313002c-18fe-48b1-a74c-b0bd564202c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387249105 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1387249105
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2994596141
Short name T923
Test name
Test status
Simulation time 20819604 ps
CPU time 0.95 seconds
Started Jul 29 06:21:04 PM PDT 24
Finished Jul 29 06:21:05 PM PDT 24
Peak memory 207032 kb
Host smart-4c52a05e-63a7-4874-a07c-4ffb1c4ce783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994596141 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2994596141
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1579904189
Short name T681
Test name
Test status
Simulation time 18376132 ps
CPU time 1 seconds
Started Jul 29 06:21:02 PM PDT 24
Finished Jul 29 06:21:03 PM PDT 24
Peak memory 215228 kb
Host smart-7befcfae-2b96-45f4-91ae-f8a168e17499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579904189 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1579904189
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3438395741
Short name T112
Test name
Test status
Simulation time 106857624 ps
CPU time 2.42 seconds
Started Jul 29 06:21:01 PM PDT 24
Finished Jul 29 06:21:04 PM PDT 24
Peak memory 218428 kb
Host smart-77d661bd-e51f-4c79-8863-12cee8275334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438395741 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3438395741
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2515146125
Short name T568
Test name
Test status
Simulation time 236860982295 ps
CPU time 1300.4 seconds
Started Jul 29 06:20:57 PM PDT 24
Finished Jul 29 06:42:37 PM PDT 24
Peak memory 223676 kb
Host smart-bd2404e6-d38e-4d4c-8b36-cbd2c84c805f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515146125 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2515146125
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.205401345
Short name T734
Test name
Test status
Simulation time 55075844 ps
CPU time 1.34 seconds
Started Jul 29 06:22:10 PM PDT 24
Finished Jul 29 06:22:11 PM PDT 24
Peak memory 215688 kb
Host smart-e36f2f20-260c-4bca-8853-17df52fd368b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205401345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.205401345
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1783862855
Short name T536
Test name
Test status
Simulation time 25649175 ps
CPU time 0.97 seconds
Started Jul 29 06:22:19 PM PDT 24
Finished Jul 29 06:22:20 PM PDT 24
Peak memory 218628 kb
Host smart-75fc35e4-467b-4da0-b814-04647a4f1f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783862855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1783862855
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2402111594
Short name T484
Test name
Test status
Simulation time 91996345 ps
CPU time 1.16 seconds
Started Jul 29 06:22:34 PM PDT 24
Finished Jul 29 06:22:35 PM PDT 24
Peak memory 217284 kb
Host smart-da73fb66-233c-4ab5-b3f2-35926074be46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402111594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2402111594
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1499398215
Short name T26
Test name
Test status
Simulation time 28226938 ps
CPU time 1.26 seconds
Started Jul 29 06:22:23 PM PDT 24
Finished Jul 29 06:22:25 PM PDT 24
Peak memory 219776 kb
Host smart-ac00a272-cdef-4f0e-8753-662310e05e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499398215 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1499398215
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.3732317635
Short name T182
Test name
Test status
Simulation time 25535181 ps
CPU time 0.98 seconds
Started Jul 29 06:22:21 PM PDT 24
Finished Jul 29 06:22:22 PM PDT 24
Peak memory 218492 kb
Host smart-d63cf37d-bc95-4d6b-a866-1bf9fc786866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732317635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3732317635
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4134175862
Short name T589
Test name
Test status
Simulation time 175561994 ps
CPU time 1.26 seconds
Started Jul 29 06:22:21 PM PDT 24
Finished Jul 29 06:22:22 PM PDT 24
Peak memory 218612 kb
Host smart-83d74e36-58e1-4eab-b752-fbf14c5fe7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134175862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4134175862
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.304955492
Short name T185
Test name
Test status
Simulation time 23404579 ps
CPU time 1.18 seconds
Started Jul 29 06:22:19 PM PDT 24
Finished Jul 29 06:22:20 PM PDT 24
Peak memory 219580 kb
Host smart-15c3404b-be13-412e-9bc7-77053bc0f86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304955492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.304955492
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.659242202
Short name T808
Test name
Test status
Simulation time 18665030 ps
CPU time 1.08 seconds
Started Jul 29 06:22:09 PM PDT 24
Finished Jul 29 06:22:10 PM PDT 24
Peak memory 218500 kb
Host smart-5d24f173-b9fa-4585-ac53-6e0a212f8530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659242202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.659242202
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/53.edn_alert.2589066
Short name T710
Test name
Test status
Simulation time 27207695 ps
CPU time 1.33 seconds
Started Jul 29 06:22:20 PM PDT 24
Finished Jul 29 06:22:22 PM PDT 24
Peak memory 219720 kb
Host smart-a2b23b57-03f7-4b5b-b54b-8f4e5fbcf4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2589066
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.3229879782
Short name T986
Test name
Test status
Simulation time 19443532 ps
CPU time 1.05 seconds
Started Jul 29 06:22:21 PM PDT 24
Finished Jul 29 06:22:23 PM PDT 24
Peak memory 218500 kb
Host smart-63d50dbc-d619-4d0c-9878-ede858e2f8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229879782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3229879782
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.960237499
Short name T498
Test name
Test status
Simulation time 72442624 ps
CPU time 1.03 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 217264 kb
Host smart-a9dad723-0274-4938-885d-2b7f7c98265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960237499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.960237499
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3778991008
Short name T431
Test name
Test status
Simulation time 52776087 ps
CPU time 1.32 seconds
Started Jul 29 06:22:15 PM PDT 24
Finished Jul 29 06:22:17 PM PDT 24
Peak memory 219968 kb
Host smart-d37bd2b6-0e54-4e2c-b246-802a56a8e459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778991008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3778991008
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.1186340669
Short name T142
Test name
Test status
Simulation time 32664770 ps
CPU time 0.99 seconds
Started Jul 29 06:22:30 PM PDT 24
Finished Jul 29 06:22:31 PM PDT 24
Peak memory 229748 kb
Host smart-7fae5958-e57f-45d6-8df5-1a10dc049c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186340669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1186340669
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3998526207
Short name T329
Test name
Test status
Simulation time 216231882 ps
CPU time 1.05 seconds
Started Jul 29 06:22:12 PM PDT 24
Finished Jul 29 06:22:13 PM PDT 24
Peak memory 217184 kb
Host smart-24e65caf-58e7-45b5-a8b1-0c9d9ac38789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998526207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3998526207
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.2689893117
Short name T177
Test name
Test status
Simulation time 131858376 ps
CPU time 1.34 seconds
Started Jul 29 06:22:34 PM PDT 24
Finished Jul 29 06:22:35 PM PDT 24
Peak memory 219096 kb
Host smart-1e57803c-a5da-422b-b579-fdce4d98d71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689893117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2689893117
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2168381218
Short name T164
Test name
Test status
Simulation time 26192440 ps
CPU time 1.14 seconds
Started Jul 29 06:22:33 PM PDT 24
Finished Jul 29 06:22:34 PM PDT 24
Peak memory 218348 kb
Host smart-1a3998d8-c75d-4c02-8e9b-7585e5860e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168381218 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2168381218
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.106431112
Short name T317
Test name
Test status
Simulation time 144238727 ps
CPU time 3.36 seconds
Started Jul 29 06:22:18 PM PDT 24
Finished Jul 29 06:22:22 PM PDT 24
Peak memory 219884 kb
Host smart-cde93a81-8952-4e69-9de9-46853cfdabcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106431112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.106431112
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.891355343
Short name T690
Test name
Test status
Simulation time 24808277 ps
CPU time 1.24 seconds
Started Jul 29 06:22:23 PM PDT 24
Finished Jul 29 06:22:24 PM PDT 24
Peak memory 218816 kb
Host smart-b8f1f6d0-a361-4ba3-918a-58861e89b696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891355343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.891355343
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.24923152
Short name T738
Test name
Test status
Simulation time 27601999 ps
CPU time 0.94 seconds
Started Jul 29 06:22:34 PM PDT 24
Finished Jul 29 06:22:35 PM PDT 24
Peak memory 223684 kb
Host smart-72d6f33b-e295-4e54-872d-74f686e0cb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24923152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.24923152
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3745755991
Short name T976
Test name
Test status
Simulation time 56405884 ps
CPU time 1.07 seconds
Started Jul 29 06:22:33 PM PDT 24
Finished Jul 29 06:22:34 PM PDT 24
Peak memory 217204 kb
Host smart-e485b8d6-c975-4107-ab70-ab25d4826ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745755991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3745755991
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.162710648
Short name T619
Test name
Test status
Simulation time 48396917 ps
CPU time 1.19 seconds
Started Jul 29 06:22:34 PM PDT 24
Finished Jul 29 06:22:35 PM PDT 24
Peak memory 219824 kb
Host smart-a87bd3b4-4f2d-4418-ab57-0505d3595893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162710648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.162710648
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.610313306
Short name T730
Test name
Test status
Simulation time 20931334 ps
CPU time 0.91 seconds
Started Jul 29 06:22:35 PM PDT 24
Finished Jul 29 06:22:36 PM PDT 24
Peak memory 218096 kb
Host smart-edc104ef-0c47-40ca-8262-5b166315aecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610313306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.610313306
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.683298265
Short name T811
Test name
Test status
Simulation time 40142762 ps
CPU time 1.48 seconds
Started Jul 29 06:22:31 PM PDT 24
Finished Jul 29 06:22:33 PM PDT 24
Peak memory 218588 kb
Host smart-2dd96cf2-167d-48c5-bda6-c155ae81395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683298265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.683298265
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.4134709822
Short name T920
Test name
Test status
Simulation time 26610944 ps
CPU time 1.15 seconds
Started Jul 29 06:22:23 PM PDT 24
Finished Jul 29 06:22:25 PM PDT 24
Peak memory 220728 kb
Host smart-47f15d20-d0b1-465e-8862-d0218d36eff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134709822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.4134709822
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.1403736519
Short name T149
Test name
Test status
Simulation time 35989820 ps
CPU time 0.92 seconds
Started Jul 29 06:22:43 PM PDT 24
Finished Jul 29 06:22:45 PM PDT 24
Peak memory 219464 kb
Host smart-b1274761-24f7-4318-93ea-608b72f620d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403736519 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1403736519
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2232376937
Short name T677
Test name
Test status
Simulation time 153083057 ps
CPU time 2.32 seconds
Started Jul 29 06:22:24 PM PDT 24
Finished Jul 29 06:22:26 PM PDT 24
Peak memory 220100 kb
Host smart-08675914-fb9c-4db2-b281-1f8d7b3e8b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232376937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2232376937
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.2003014721
Short name T761
Test name
Test status
Simulation time 81416594 ps
CPU time 1.18 seconds
Started Jul 29 06:22:32 PM PDT 24
Finished Jul 29 06:22:33 PM PDT 24
Peak memory 221576 kb
Host smart-34462242-6baa-4570-8d7b-48ac266a5da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003014721 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2003014721
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.3645771554
Short name T435
Test name
Test status
Simulation time 37614623 ps
CPU time 0.93 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:37 PM PDT 24
Peak memory 219728 kb
Host smart-b05054a3-ea95-4cca-bc7c-e4543775874a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645771554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3645771554
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.658271650
Short name T67
Test name
Test status
Simulation time 40807301 ps
CPU time 1.45 seconds
Started Jul 29 06:22:41 PM PDT 24
Finished Jul 29 06:22:42 PM PDT 24
Peak memory 219712 kb
Host smart-f53e5004-b3c1-4eb1-92ae-b080127a219b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658271650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.658271650
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert_test.4278678356
Short name T832
Test name
Test status
Simulation time 151475786 ps
CPU time 0.96 seconds
Started Jul 29 06:21:07 PM PDT 24
Finished Jul 29 06:21:08 PM PDT 24
Peak memory 206712 kb
Host smart-7da8a9f8-c38a-476e-ac32-1cf9f660b9f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278678356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.4278678356
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2979081650
Short name T499
Test name
Test status
Simulation time 21941080 ps
CPU time 0.92 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:05 PM PDT 24
Peak memory 216032 kb
Host smart-be20e6c8-5874-4941-a72f-7e539269701d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979081650 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2979081650
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.637773747
Short name T540
Test name
Test status
Simulation time 58415479 ps
CPU time 1.15 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:05 PM PDT 24
Peak memory 218368 kb
Host smart-75fd454b-fbd1-474a-9939-79297aaafb41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637773747 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.637773747
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1597190010
Short name T116
Test name
Test status
Simulation time 23924205 ps
CPU time 0.99 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:04 PM PDT 24
Peak memory 218452 kb
Host smart-63584a54-b052-453e-9e52-91980a702aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597190010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1597190010
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3216508763
Short name T836
Test name
Test status
Simulation time 62908627 ps
CPU time 2.18 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:05 PM PDT 24
Peak memory 219956 kb
Host smart-f3c662ea-b7df-4e48-876d-58a0f05ce544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216508763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3216508763
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.406988886
Short name T883
Test name
Test status
Simulation time 37882447 ps
CPU time 0.99 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:04 PM PDT 24
Peak memory 215352 kb
Host smart-7b702281-aa9a-4d78-98a8-2e166630b831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406988886 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.406988886
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1509574564
Short name T912
Test name
Test status
Simulation time 172996906 ps
CPU time 0.92 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:04 PM PDT 24
Peak memory 207100 kb
Host smart-e030a663-6ca0-46af-af48-274ab7b3576d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509574564 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1509574564
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3056608651
Short name T796
Test name
Test status
Simulation time 18776625 ps
CPU time 0.94 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:04 PM PDT 24
Peak memory 215320 kb
Host smart-07612768-b4e3-4588-ae91-4bf63ce0db4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056608651 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3056608651
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.104353509
Short name T756
Test name
Test status
Simulation time 383155006 ps
CPU time 2.61 seconds
Started Jul 29 06:21:05 PM PDT 24
Finished Jul 29 06:21:08 PM PDT 24
Peak memory 217024 kb
Host smart-e9fcb16e-0f37-4d48-a45b-642a0f4c7657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104353509 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.104353509
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1697442269
Short name T229
Test name
Test status
Simulation time 64343809394 ps
CPU time 1428.97 seconds
Started Jul 29 06:21:04 PM PDT 24
Finished Jul 29 06:44:54 PM PDT 24
Peak memory 223688 kb
Host smart-16845ca7-b753-4e6b-918a-ba64ef11b2b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697442269 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1697442269
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.619781745
Short name T829
Test name
Test status
Simulation time 40545365 ps
CPU time 1.15 seconds
Started Jul 29 06:22:23 PM PDT 24
Finished Jul 29 06:22:25 PM PDT 24
Peak memory 218604 kb
Host smart-e6c1ac38-cbfd-449f-8a46-ed4046ba2279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619781745 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.619781745
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1510580621
Short name T858
Test name
Test status
Simulation time 58382463 ps
CPU time 0.91 seconds
Started Jul 29 06:22:23 PM PDT 24
Finished Jul 29 06:22:24 PM PDT 24
Peak memory 219632 kb
Host smart-9a774f4d-d557-495c-be23-606d7d147948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510580621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1510580621
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.352482538
Short name T616
Test name
Test status
Simulation time 60742982 ps
CPU time 1.08 seconds
Started Jul 29 06:22:20 PM PDT 24
Finished Jul 29 06:22:21 PM PDT 24
Peak memory 217252 kb
Host smart-5ad41ec2-dcaa-4ace-9774-af41e262d945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352482538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.352482538
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1226477108
Short name T852
Test name
Test status
Simulation time 48980495 ps
CPU time 1.13 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 220604 kb
Host smart-b182076c-10d4-4ae8-a641-6e2b1a58c2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226477108 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1226477108
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.288804878
Short name T890
Test name
Test status
Simulation time 94630975 ps
CPU time 0.92 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:37 PM PDT 24
Peak memory 219584 kb
Host smart-cf9512a1-474b-4746-8988-a6049fa67f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288804878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.288804878
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2775391208
Short name T625
Test name
Test status
Simulation time 49596657 ps
CPU time 1.26 seconds
Started Jul 29 06:22:41 PM PDT 24
Finished Jul 29 06:22:42 PM PDT 24
Peak memory 219588 kb
Host smart-95ffa4ce-0381-47d6-97f6-bf32927c3ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775391208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2775391208
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.2212759551
Short name T201
Test name
Test status
Simulation time 28639955 ps
CPU time 1.27 seconds
Started Jul 29 06:22:32 PM PDT 24
Finished Jul 29 06:22:34 PM PDT 24
Peak memory 215628 kb
Host smart-5e6a5a7f-a066-4047-845e-329d8cdf9f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212759551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2212759551
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1400424568
Short name T385
Test name
Test status
Simulation time 23531455 ps
CPU time 0.92 seconds
Started Jul 29 06:22:41 PM PDT 24
Finished Jul 29 06:22:42 PM PDT 24
Peak memory 218416 kb
Host smart-795fde58-ddaa-43de-9345-f45af7b86225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400424568 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1400424568
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.864056844
Short name T17
Test name
Test status
Simulation time 46003740 ps
CPU time 1.21 seconds
Started Jul 29 06:22:26 PM PDT 24
Finished Jul 29 06:22:27 PM PDT 24
Peak memory 219964 kb
Host smart-4b3e27da-b2b7-4a27-8348-3610ae630a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864056844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.864056844
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.3221422277
Short name T247
Test name
Test status
Simulation time 28253447 ps
CPU time 1.3 seconds
Started Jul 29 06:22:24 PM PDT 24
Finished Jul 29 06:22:25 PM PDT 24
Peak memory 220516 kb
Host smart-75eea630-322e-4adb-92e4-973b8671ce2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221422277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3221422277
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.3746009828
Short name T940
Test name
Test status
Simulation time 28321965 ps
CPU time 1.17 seconds
Started Jul 29 06:22:35 PM PDT 24
Finished Jul 29 06:22:36 PM PDT 24
Peak memory 219756 kb
Host smart-b905f913-e899-4f23-89cb-3b02fd963fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746009828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3746009828
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2184478896
Short name T348
Test name
Test status
Simulation time 576835046 ps
CPU time 5.15 seconds
Started Jul 29 06:22:41 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 220204 kb
Host smart-62deaed4-9594-427e-9bd8-24fc47181075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184478896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2184478896
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.3859963750
Short name T412
Test name
Test status
Simulation time 51147222 ps
CPU time 1.21 seconds
Started Jul 29 06:22:41 PM PDT 24
Finished Jul 29 06:22:42 PM PDT 24
Peak memory 219760 kb
Host smart-ce61afd5-9795-4188-9bd2-24c967d7f1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859963750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.3859963750
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.4055290542
Short name T93
Test name
Test status
Simulation time 92567997 ps
CPU time 1.17 seconds
Started Jul 29 06:22:40 PM PDT 24
Finished Jul 29 06:22:41 PM PDT 24
Peak memory 219516 kb
Host smart-2bdaafd8-89b9-4a63-aba7-a82e45471f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055290542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.4055290542
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2302110354
Short name T722
Test name
Test status
Simulation time 59638119 ps
CPU time 1.41 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 217100 kb
Host smart-bc156c15-15c7-4e7e-ad26-613478e0269d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302110354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2302110354
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.718218906
Short name T416
Test name
Test status
Simulation time 48652682 ps
CPU time 1.22 seconds
Started Jul 29 06:22:20 PM PDT 24
Finished Jul 29 06:22:21 PM PDT 24
Peak memory 218744 kb
Host smart-01585101-2277-4282-b8fb-f2d99c46b6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718218906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.718218906
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.1305117795
Short name T60
Test name
Test status
Simulation time 20869368 ps
CPU time 0.99 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 218532 kb
Host smart-a41fadbe-d78e-424f-9e3c-4695ffc2ef9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305117795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1305117795
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3564551210
Short name T328
Test name
Test status
Simulation time 63242088 ps
CPU time 1.04 seconds
Started Jul 29 06:22:35 PM PDT 24
Finished Jul 29 06:22:36 PM PDT 24
Peak memory 217196 kb
Host smart-5ae08e28-a1aa-4b3d-840c-87c555121ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564551210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3564551210
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.270157363
Short name T927
Test name
Test status
Simulation time 24718825 ps
CPU time 1.21 seconds
Started Jul 29 06:22:41 PM PDT 24
Finished Jul 29 06:22:42 PM PDT 24
Peak memory 219532 kb
Host smart-689f38f2-83ff-4d85-94d5-9836dbf82a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270157363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.270157363
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2573293160
Short name T649
Test name
Test status
Simulation time 22406631 ps
CPU time 0.93 seconds
Started Jul 29 06:22:30 PM PDT 24
Finished Jul 29 06:22:31 PM PDT 24
Peak memory 218260 kb
Host smart-831e3529-003d-4a90-907f-c5cea9d14f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573293160 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2573293160
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3655688737
Short name T397
Test name
Test status
Simulation time 84256975 ps
CPU time 1.49 seconds
Started Jul 29 06:22:41 PM PDT 24
Finished Jul 29 06:22:43 PM PDT 24
Peak memory 218592 kb
Host smart-ea718052-e9d1-426e-8878-676ca3601a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655688737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3655688737
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.1568171944
Short name T394
Test name
Test status
Simulation time 136385922 ps
CPU time 1.22 seconds
Started Jul 29 06:22:28 PM PDT 24
Finished Jul 29 06:22:34 PM PDT 24
Peak memory 215628 kb
Host smart-15aadd4e-0a78-47ce-bc53-4afd2da45ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568171944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1568171944
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1695829283
Short name T572
Test name
Test status
Simulation time 21798773 ps
CPU time 0.93 seconds
Started Jul 29 06:22:27 PM PDT 24
Finished Jul 29 06:22:28 PM PDT 24
Peak memory 218240 kb
Host smart-9659dd5c-2eb1-44b1-ae1a-adcc9ed0f87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695829283 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1695829283
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.291317846
Short name T780
Test name
Test status
Simulation time 51479269 ps
CPU time 1.3 seconds
Started Jul 29 06:22:19 PM PDT 24
Finished Jul 29 06:22:20 PM PDT 24
Peak memory 218680 kb
Host smart-b065a914-15be-4f32-84fb-e0f8cdc2aa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291317846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.291317846
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.2531024573
Short name T468
Test name
Test status
Simulation time 46105353 ps
CPU time 1.17 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 218812 kb
Host smart-c77835ae-8a96-4abd-93f9-78f484e51888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531024573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.2531024573
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_genbits.4097995295
Short name T375
Test name
Test status
Simulation time 114447087 ps
CPU time 1.41 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:37 PM PDT 24
Peak memory 220220 kb
Host smart-cf3e2f27-027b-4c04-bebb-2826373d8a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097995295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.4097995295
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.561059493
Short name T184
Test name
Test status
Simulation time 78368453 ps
CPU time 1.08 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 219624 kb
Host smart-9adac7af-f2ff-4def-9fd5-caeef130bfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561059493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.561059493
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.4079183454
Short name T697
Test name
Test status
Simulation time 18161409 ps
CPU time 1.17 seconds
Started Jul 29 06:22:34 PM PDT 24
Finished Jul 29 06:22:36 PM PDT 24
Peak memory 223940 kb
Host smart-cb45dd1e-d62c-4719-a6d3-248545b99f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079183454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.4079183454
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.438048344
Short name T319
Test name
Test status
Simulation time 48052131 ps
CPU time 1.21 seconds
Started Jul 29 06:22:34 PM PDT 24
Finished Jul 29 06:22:36 PM PDT 24
Peak memory 220052 kb
Host smart-12e06eba-b363-4ab3-96c5-596332049366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438048344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.438048344
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.540645946
Short name T650
Test name
Test status
Simulation time 53924793 ps
CPU time 1.24 seconds
Started Jul 29 06:21:23 PM PDT 24
Finished Jul 29 06:21:25 PM PDT 24
Peak memory 219120 kb
Host smart-3703c0b7-ade1-409c-8bdd-f5d3fca33dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540645946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.540645946
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3221348194
Short name T964
Test name
Test status
Simulation time 24324306 ps
CPU time 0.85 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:04 PM PDT 24
Peak memory 206696 kb
Host smart-42c5042e-dc8a-496e-b6d9-10725f82c959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221348194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3221348194
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1746578128
Short name T893
Test name
Test status
Simulation time 13513468 ps
CPU time 0.94 seconds
Started Jul 29 06:21:04 PM PDT 24
Finished Jul 29 06:21:05 PM PDT 24
Peak memory 216224 kb
Host smart-2799fc40-974b-41b9-933e-57ca5ae7814b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746578128 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1746578128
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3581364187
Short name T119
Test name
Test status
Simulation time 35228666 ps
CPU time 1.37 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:05 PM PDT 24
Peak memory 219736 kb
Host smart-1d442af3-0d4c-4cca-b3cb-d53b865f68f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581364187 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3581364187
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2903427632
Short name T49
Test name
Test status
Simulation time 108206833 ps
CPU time 1.1 seconds
Started Jul 29 06:21:06 PM PDT 24
Finished Jul 29 06:21:07 PM PDT 24
Peak memory 229660 kb
Host smart-8bf3a9ee-703b-4499-9157-121dfa5feff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903427632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2903427632
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2413646813
Short name T831
Test name
Test status
Simulation time 67275933 ps
CPU time 1.09 seconds
Started Jul 29 06:21:04 PM PDT 24
Finished Jul 29 06:21:06 PM PDT 24
Peak memory 218744 kb
Host smart-4751189b-3f19-4f96-81c7-7f00c4aea60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413646813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2413646813
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2258619340
Short name T594
Test name
Test status
Simulation time 21484089 ps
CPU time 1.1 seconds
Started Jul 29 06:21:02 PM PDT 24
Finished Jul 29 06:21:03 PM PDT 24
Peak memory 215300 kb
Host smart-ed12e7c5-1595-4ae2-a2ed-cbc305e5252b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258619340 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2258619340
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.4206178764
Short name T962
Test name
Test status
Simulation time 17276568 ps
CPU time 1 seconds
Started Jul 29 06:21:04 PM PDT 24
Finished Jul 29 06:21:05 PM PDT 24
Peak memory 207160 kb
Host smart-5bcfbfeb-4e4f-4e66-81ed-b706c5aa367c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206178764 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.4206178764
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.513833141
Short name T496
Test name
Test status
Simulation time 65279572 ps
CPU time 0.9 seconds
Started Jul 29 06:21:05 PM PDT 24
Finished Jul 29 06:21:06 PM PDT 24
Peak memory 215268 kb
Host smart-93e707b5-6c36-466c-8a4a-cdf153cb00ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513833141 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.513833141
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1669904992
Short name T982
Test name
Test status
Simulation time 642415723 ps
CPU time 3.39 seconds
Started Jul 29 06:21:04 PM PDT 24
Finished Jul 29 06:21:08 PM PDT 24
Peak memory 215308 kb
Host smart-08513a6a-569c-4e8c-909b-b980d68828c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669904992 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1669904992
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.792729064
Short name T665
Test name
Test status
Simulation time 31186608211 ps
CPU time 452.91 seconds
Started Jul 29 06:21:07 PM PDT 24
Finished Jul 29 06:28:40 PM PDT 24
Peak memory 218344 kb
Host smart-60ff0b2d-5326-41c2-9441-d18337c01c31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792729064 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.792729064
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.1503213229
Short name T168
Test name
Test status
Simulation time 47000538 ps
CPU time 1.14 seconds
Started Jul 29 06:22:26 PM PDT 24
Finished Jul 29 06:22:28 PM PDT 24
Peak memory 219696 kb
Host smart-0af514db-16a7-4bd8-a8b1-4305288a2341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503213229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1503213229
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_genbits.713243313
Short name T68
Test name
Test status
Simulation time 38427908 ps
CPU time 1.36 seconds
Started Jul 29 06:22:30 PM PDT 24
Finished Jul 29 06:22:31 PM PDT 24
Peak memory 218728 kb
Host smart-5bf4a0d2-056c-4e37-acf1-d9e277a51212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713243313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.713243313
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.727314867
Short name T210
Test name
Test status
Simulation time 74425763 ps
CPU time 1.28 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 218708 kb
Host smart-39e068d1-6f23-4ae2-bd58-e947015bd64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727314867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.727314867
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2047080300
Short name T150
Test name
Test status
Simulation time 24681809 ps
CPU time 1.27 seconds
Started Jul 29 06:22:23 PM PDT 24
Finished Jul 29 06:22:25 PM PDT 24
Peak memory 220540 kb
Host smart-e8b65941-90c8-426f-a1c0-637d5398c6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047080300 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2047080300
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.4749267
Short name T953
Test name
Test status
Simulation time 49932805 ps
CPU time 1.48 seconds
Started Jul 29 06:22:27 PM PDT 24
Finished Jul 29 06:22:28 PM PDT 24
Peak memory 217364 kb
Host smart-d8c825b9-d35b-4ee2-a188-a784d4680e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4749267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.4749267
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1010609046
Short name T685
Test name
Test status
Simulation time 140406587 ps
CPU time 1.27 seconds
Started Jul 29 06:22:26 PM PDT 24
Finished Jul 29 06:22:27 PM PDT 24
Peak memory 219172 kb
Host smart-380f37bf-e1f4-4d3c-9622-547816452f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010609046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1010609046
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.1597602222
Short name T384
Test name
Test status
Simulation time 19977022 ps
CPU time 1.07 seconds
Started Jul 29 06:22:45 PM PDT 24
Finished Jul 29 06:22:46 PM PDT 24
Peak memory 219524 kb
Host smart-6ef925ce-4004-4afa-a6fe-dc3c6bbfef5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597602222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1597602222
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2384018933
Short name T441
Test name
Test status
Simulation time 39145035 ps
CPU time 1.29 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:37 PM PDT 24
Peak memory 218740 kb
Host smart-132b9ad4-e56c-4015-a557-47681ed35fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384018933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2384018933
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.443179469
Short name T896
Test name
Test status
Simulation time 39644866 ps
CPU time 1.18 seconds
Started Jul 29 06:22:27 PM PDT 24
Finished Jul 29 06:22:28 PM PDT 24
Peak memory 219152 kb
Host smart-5666e647-c3f5-4829-a726-50f12dec3bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443179469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.443179469
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3378989462
Short name T145
Test name
Test status
Simulation time 25989039 ps
CPU time 1.2 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 219764 kb
Host smart-7a1d297f-6c2e-46c3-a92c-7a2e9c3a8e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378989462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3378989462
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1013487769
Short name T855
Test name
Test status
Simulation time 62530909 ps
CPU time 1.51 seconds
Started Jul 29 06:22:25 PM PDT 24
Finished Jul 29 06:22:26 PM PDT 24
Peak memory 218684 kb
Host smart-e3698e3a-13d2-4467-abd6-8c3a6c1bbf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013487769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1013487769
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.881728624
Short name T109
Test name
Test status
Simulation time 67291208 ps
CPU time 1.15 seconds
Started Jul 29 06:22:25 PM PDT 24
Finished Jul 29 06:22:27 PM PDT 24
Peak memory 220020 kb
Host smart-d36d0037-fa94-4894-8036-5deaf631c23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881728624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.881728624
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.379619091
Short name T6
Test name
Test status
Simulation time 37435769 ps
CPU time 0.94 seconds
Started Jul 29 06:22:28 PM PDT 24
Finished Jul 29 06:22:29 PM PDT 24
Peak memory 219440 kb
Host smart-2d60b24f-8c32-4b4d-aec7-5d76ebc97773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379619091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.379619091
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/75.edn_alert.1847471713
Short name T984
Test name
Test status
Simulation time 161172868 ps
CPU time 1.27 seconds
Started Jul 29 06:22:42 PM PDT 24
Finished Jul 29 06:22:43 PM PDT 24
Peak memory 219556 kb
Host smart-55a6f6d5-7cdc-48e0-a50a-5bb4db5e4564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847471713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1847471713
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.1420206729
Short name T834
Test name
Test status
Simulation time 35136733 ps
CPU time 1.08 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:40 PM PDT 24
Peak memory 220832 kb
Host smart-1f0e504b-f8f7-487c-8e33-547e7cf23f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420206729 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1420206729
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.4072930317
Short name T378
Test name
Test status
Simulation time 70020193 ps
CPU time 1.47 seconds
Started Jul 29 06:22:25 PM PDT 24
Finished Jul 29 06:22:27 PM PDT 24
Peak memory 218724 kb
Host smart-364ec925-d217-4d35-ba6c-5442500d6f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072930317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.4072930317
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.1140877024
Short name T283
Test name
Test status
Simulation time 25142551 ps
CPU time 1.27 seconds
Started Jul 29 06:22:27 PM PDT 24
Finished Jul 29 06:22:28 PM PDT 24
Peak memory 219268 kb
Host smart-dc1e8a3a-d90c-4c50-aaa6-7e4006947aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140877024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1140877024
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.1611943808
Short name T144
Test name
Test status
Simulation time 85314127 ps
CPU time 0.94 seconds
Started Jul 29 06:22:28 PM PDT 24
Finished Jul 29 06:22:29 PM PDT 24
Peak memory 219652 kb
Host smart-382e2ca2-7013-4331-a52c-4e276069e3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611943808 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1611943808
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3070366489
Short name T660
Test name
Test status
Simulation time 84616968 ps
CPU time 1.14 seconds
Started Jul 29 06:22:33 PM PDT 24
Finished Jul 29 06:22:34 PM PDT 24
Peak memory 217328 kb
Host smart-e6cedbea-4989-4275-af7a-89cb901ae912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070366489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3070366489
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.3754908753
Short name T546
Test name
Test status
Simulation time 94303704 ps
CPU time 1.29 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 220524 kb
Host smart-5fabef7d-1479-44c0-ac20-25c46e2cb3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754908753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.3754908753
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.967071651
Short name T181
Test name
Test status
Simulation time 145994082 ps
CPU time 1.04 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 219552 kb
Host smart-135fb9dd-7136-4ff8-9724-0dd0f30373ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967071651 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.967071651
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1272552959
Short name T580
Test name
Test status
Simulation time 54243618 ps
CPU time 1.5 seconds
Started Jul 29 06:22:41 PM PDT 24
Finished Jul 29 06:22:42 PM PDT 24
Peak memory 218948 kb
Host smart-1da0a2a9-6c78-4121-b5f9-a7a1843267b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272552959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1272552959
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.22615340
Short name T505
Test name
Test status
Simulation time 50502159 ps
CPU time 1.21 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 215624 kb
Host smart-bbafc51a-210b-4d56-b0e2-e8d8e2389e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22615340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.22615340
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_genbits.388473282
Short name T970
Test name
Test status
Simulation time 34616696 ps
CPU time 1.04 seconds
Started Jul 29 06:22:27 PM PDT 24
Finished Jul 29 06:22:28 PM PDT 24
Peak memory 217388 kb
Host smart-a8d13f3e-58eb-486f-971c-aacd0751c6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388473282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.388473282
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.3214092384
Short name T954
Test name
Test status
Simulation time 84383371 ps
CPU time 1.05 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:37 PM PDT 24
Peak memory 218512 kb
Host smart-35aa091e-e08b-4c00-b9a0-80bcd5938ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214092384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.3214092384
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.2782017436
Short name T160
Test name
Test status
Simulation time 105801364 ps
CPU time 1.03 seconds
Started Jul 29 06:22:29 PM PDT 24
Finished Jul 29 06:22:30 PM PDT 24
Peak memory 219612 kb
Host smart-6075a3bc-29ae-4544-8569-3e36274017a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782017436 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2782017436
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3891894031
Short name T957
Test name
Test status
Simulation time 194151684 ps
CPU time 1.06 seconds
Started Jul 29 06:22:35 PM PDT 24
Finished Jul 29 06:22:36 PM PDT 24
Peak memory 217348 kb
Host smart-566f7733-6d0e-43f5-9599-510907894440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891894031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3891894031
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3572938321
Short name T9
Test name
Test status
Simulation time 24831007 ps
CPU time 1.23 seconds
Started Jul 29 06:21:31 PM PDT 24
Finished Jul 29 06:21:33 PM PDT 24
Peak memory 219524 kb
Host smart-4da5795c-f64d-40e4-8597-29305b93cb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572938321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3572938321
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1026190704
Short name T924
Test name
Test status
Simulation time 51507594 ps
CPU time 1.05 seconds
Started Jul 29 06:21:33 PM PDT 24
Finished Jul 29 06:21:34 PM PDT 24
Peak memory 206668 kb
Host smart-e3db5b97-6295-4116-b64f-a2147cb5f226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026190704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1026190704
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3012688265
Short name T522
Test name
Test status
Simulation time 25053436 ps
CPU time 0.79 seconds
Started Jul 29 06:21:30 PM PDT 24
Finished Jul 29 06:21:31 PM PDT 24
Peak memory 216164 kb
Host smart-a453959d-8db5-4ba6-9060-9e3b07d705d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012688265 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3012688265
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.4152886859
Short name T549
Test name
Test status
Simulation time 54674000 ps
CPU time 1.5 seconds
Started Jul 29 06:21:16 PM PDT 24
Finished Jul 29 06:21:17 PM PDT 24
Peak memory 216820 kb
Host smart-2637fee9-9c1a-48ff-bbfa-5d564540c314
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152886859 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.4152886859
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1830108259
Short name T140
Test name
Test status
Simulation time 28166446 ps
CPU time 0.88 seconds
Started Jul 29 06:21:18 PM PDT 24
Finished Jul 29 06:21:19 PM PDT 24
Peak memory 218380 kb
Host smart-8cfbf756-b400-44c2-9953-62c190bcc9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830108259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1830108259
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1595392008
Short name T664
Test name
Test status
Simulation time 32458527 ps
CPU time 1.04 seconds
Started Jul 29 06:21:02 PM PDT 24
Finished Jul 29 06:21:03 PM PDT 24
Peak memory 217252 kb
Host smart-2971eca0-baa4-4a0e-9655-20dfd9575e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595392008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1595392008
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_regwen.616329354
Short name T77
Test name
Test status
Simulation time 19672674 ps
CPU time 0.98 seconds
Started Jul 29 06:21:01 PM PDT 24
Finished Jul 29 06:21:02 PM PDT 24
Peak memory 207052 kb
Host smart-218451d1-b1a4-4cf0-8937-555534aecba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616329354 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.616329354
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3827710105
Short name T521
Test name
Test status
Simulation time 53370227 ps
CPU time 0.89 seconds
Started Jul 29 06:21:03 PM PDT 24
Finished Jul 29 06:21:04 PM PDT 24
Peak memory 215288 kb
Host smart-26dea1c5-bcd5-41e9-86d3-9e8a073f701d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827710105 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3827710105
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3065123980
Short name T701
Test name
Test status
Simulation time 243857935 ps
CPU time 4.62 seconds
Started Jul 29 06:21:08 PM PDT 24
Finished Jul 29 06:21:13 PM PDT 24
Peak memory 219564 kb
Host smart-c3367283-1566-4f49-abe5-b95c97e243c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065123980 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3065123980
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1123069452
Short name T231
Test name
Test status
Simulation time 835690943206 ps
CPU time 1293.65 seconds
Started Jul 29 06:21:05 PM PDT 24
Finished Jul 29 06:42:39 PM PDT 24
Peak memory 223764 kb
Host smart-0cdc1bd9-0962-49ea-88ee-db459906d286
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123069452 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1123069452
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1774987035
Short name T195
Test name
Test status
Simulation time 71052236 ps
CPU time 1.22 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:37 PM PDT 24
Peak memory 220584 kb
Host smart-9870c57f-6f5c-4887-88e7-5989564e9351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774987035 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1774987035
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.2191535876
Short name T711
Test name
Test status
Simulation time 35152063 ps
CPU time 0.92 seconds
Started Jul 29 06:22:28 PM PDT 24
Finished Jul 29 06:22:29 PM PDT 24
Peak memory 219844 kb
Host smart-6bc14b27-7492-4180-8fed-5cb1a2f1da1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191535876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2191535876
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2284545027
Short name T299
Test name
Test status
Simulation time 194166525 ps
CPU time 1.3 seconds
Started Jul 29 06:22:23 PM PDT 24
Finished Jul 29 06:22:24 PM PDT 24
Peak memory 218804 kb
Host smart-19f66403-c3e3-4148-8efa-dbc959b89ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284545027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2284545027
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1540502863
Short name T200
Test name
Test status
Simulation time 132884718 ps
CPU time 1.28 seconds
Started Jul 29 06:22:25 PM PDT 24
Finished Jul 29 06:22:26 PM PDT 24
Peak memory 219516 kb
Host smart-4dc8dc0f-b73a-49cf-bd37-955bd5080918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540502863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1540502863
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.322444462
Short name T50
Test name
Test status
Simulation time 59670507 ps
CPU time 1.07 seconds
Started Jul 29 06:22:52 PM PDT 24
Finished Jul 29 06:22:53 PM PDT 24
Peak memory 229744 kb
Host smart-ec7792cc-d1af-4c2c-904a-7304a981236f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322444462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.322444462
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3175764187
Short name T753
Test name
Test status
Simulation time 43411276 ps
CPU time 1.49 seconds
Started Jul 29 06:22:26 PM PDT 24
Finished Jul 29 06:22:28 PM PDT 24
Peak memory 217272 kb
Host smart-8ccd9ad4-c6b4-4165-963b-4725fdb89905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175764187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3175764187
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2257031811
Short name T290
Test name
Test status
Simulation time 128340092 ps
CPU time 1.19 seconds
Started Jul 29 06:22:27 PM PDT 24
Finished Jul 29 06:22:28 PM PDT 24
Peak memory 220436 kb
Host smart-008db8ed-fa29-47fd-827f-4370ae1168f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257031811 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2257031811
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.2049862826
Short name T486
Test name
Test status
Simulation time 30251007 ps
CPU time 0.93 seconds
Started Jul 29 06:22:27 PM PDT 24
Finished Jul 29 06:22:28 PM PDT 24
Peak memory 218568 kb
Host smart-9a0cde95-673a-45ed-89b3-ca8109bb7cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049862826 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2049862826
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3521321163
Short name T736
Test name
Test status
Simulation time 63224029 ps
CPU time 1.21 seconds
Started Jul 29 06:22:25 PM PDT 24
Finished Jul 29 06:22:26 PM PDT 24
Peak memory 219868 kb
Host smart-bcd7c19f-efb0-403c-b3a1-0b5e52b1d501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521321163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3521321163
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1939726317
Short name T539
Test name
Test status
Simulation time 84282664 ps
CPU time 1.18 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 219884 kb
Host smart-c7195766-2f56-41d0-bc3c-ecb08f813cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939726317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1939726317
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.1351092827
Short name T874
Test name
Test status
Simulation time 29462087 ps
CPU time 1.38 seconds
Started Jul 29 06:22:24 PM PDT 24
Finished Jul 29 06:22:26 PM PDT 24
Peak memory 225664 kb
Host smart-43aae8a8-6378-4f4e-b64d-b10d4095c10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351092827 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1351092827
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.4074446243
Short name T349
Test name
Test status
Simulation time 41732611 ps
CPU time 1.46 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 218460 kb
Host smart-420f36f9-baf6-4ce2-892f-715a3ef624c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074446243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.4074446243
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2485313599
Short name T871
Test name
Test status
Simulation time 24488228 ps
CPU time 1.19 seconds
Started Jul 29 06:22:34 PM PDT 24
Finished Jul 29 06:22:35 PM PDT 24
Peak memory 219436 kb
Host smart-747ef7b3-86b7-480b-91c2-875b0b7afd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485313599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2485313599
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.1631417729
Short name T46
Test name
Test status
Simulation time 22322609 ps
CPU time 1.07 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 223992 kb
Host smart-a15e6b71-01e4-4aab-abbb-3c69b6de3900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631417729 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1631417729
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2258893678
Short name T882
Test name
Test status
Simulation time 142025072 ps
CPU time 1.31 seconds
Started Jul 29 06:22:27 PM PDT 24
Finished Jul 29 06:22:29 PM PDT 24
Peak memory 219868 kb
Host smart-46d6a795-0a6f-4d44-84c6-a49d3d9e454b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258893678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2258893678
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.2953540284
Short name T936
Test name
Test status
Simulation time 48555679 ps
CPU time 1.22 seconds
Started Jul 29 06:22:27 PM PDT 24
Finished Jul 29 06:22:28 PM PDT 24
Peak memory 219660 kb
Host smart-920e3880-6430-4fec-a97d-53f0c1fb0499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953540284 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2953540284
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1490391086
Short name T47
Test name
Test status
Simulation time 22841058 ps
CPU time 1.08 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 224008 kb
Host smart-6cb8c5f8-423c-4ff3-82b0-3c9baa8e656f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490391086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1490391086
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.242805439
Short name T376
Test name
Test status
Simulation time 58263737 ps
CPU time 1.22 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 217352 kb
Host smart-cb793c5e-3a7e-418d-9752-8dc3d684a93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242805439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.242805439
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2825422025
Short name T569
Test name
Test status
Simulation time 24396867 ps
CPU time 1.23 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 219652 kb
Host smart-80183fde-f859-47d1-91ad-5f33d91c35ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825422025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2825422025
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2500203366
Short name T137
Test name
Test status
Simulation time 22686536 ps
CPU time 1.2 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 224052 kb
Host smart-af83541c-4386-4107-8f9a-2383a3c968d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500203366 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2500203366
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1370696342
Short name T709
Test name
Test status
Simulation time 66782882 ps
CPU time 1.49 seconds
Started Jul 29 06:22:27 PM PDT 24
Finished Jul 29 06:22:29 PM PDT 24
Peak memory 218756 kb
Host smart-8d6e8b91-0234-40a6-a904-47d266abac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370696342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1370696342
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.711975329
Short name T571
Test name
Test status
Simulation time 51062802 ps
CPU time 1.19 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 219536 kb
Host smart-dcf2e628-34bd-40fa-b304-bb33f599cc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711975329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.711975329
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_genbits.1364020999
Short name T543
Test name
Test status
Simulation time 203973941 ps
CPU time 2.44 seconds
Started Jul 29 06:22:28 PM PDT 24
Finished Jul 29 06:22:30 PM PDT 24
Peak memory 217720 kb
Host smart-3e05cd72-b73b-4be0-ba8b-eacdac2a0194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364020999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1364020999
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3743527155
Short name T360
Test name
Test status
Simulation time 37914087 ps
CPU time 1.08 seconds
Started Jul 29 06:22:26 PM PDT 24
Finished Jul 29 06:22:27 PM PDT 24
Peak memory 218552 kb
Host smart-2f9d882b-8a3f-47a0-8973-3b26a37e5b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743527155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3743527155
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.3806929779
Short name T881
Test name
Test status
Simulation time 18731814 ps
CPU time 1.03 seconds
Started Jul 29 06:22:35 PM PDT 24
Finished Jul 29 06:22:36 PM PDT 24
Peak memory 218564 kb
Host smart-f518e4f4-d76a-45be-8642-c6ecdfdfc852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806929779 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3806929779
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1037719357
Short name T364
Test name
Test status
Simulation time 76806455 ps
CPU time 1.68 seconds
Started Jul 29 06:22:40 PM PDT 24
Finished Jul 29 06:22:42 PM PDT 24
Peak memory 218748 kb
Host smart-d99c5319-e488-46e1-9791-8d0d638ea536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037719357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1037719357
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2115398013
Short name T418
Test name
Test status
Simulation time 30818377 ps
CPU time 1.31 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 220440 kb
Host smart-eb2191ec-9fc0-4991-97fd-8605d8dd2aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115398013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2115398013
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2831885327
Short name T169
Test name
Test status
Simulation time 35813393 ps
CPU time 0.95 seconds
Started Jul 29 06:22:27 PM PDT 24
Finished Jul 29 06:22:29 PM PDT 24
Peak memory 219660 kb
Host smart-6b8a17bf-ba69-44ae-a2c6-dfcb1d516a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831885327 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2831885327
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1507144625
Short name T972
Test name
Test status
Simulation time 55760899 ps
CPU time 1.3 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:40 PM PDT 24
Peak memory 218680 kb
Host smart-26c72173-3474-4d84-a7ff-d4a0f39fe8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507144625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1507144625
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.704691790
Short name T903
Test name
Test status
Simulation time 23618297 ps
CPU time 1.19 seconds
Started Jul 29 06:21:13 PM PDT 24
Finished Jul 29 06:21:15 PM PDT 24
Peak memory 219656 kb
Host smart-6fb803d2-be04-469c-9279-ab99ddcf9a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704691790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.704691790
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3847363701
Short name T931
Test name
Test status
Simulation time 60310329 ps
CPU time 1.08 seconds
Started Jul 29 06:21:09 PM PDT 24
Finished Jul 29 06:21:10 PM PDT 24
Peak memory 206620 kb
Host smart-7376bae3-4455-489e-a8a6-5afade6c7045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847363701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3847363701
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.159691374
Short name T439
Test name
Test status
Simulation time 14148842 ps
CPU time 0.99 seconds
Started Jul 29 06:21:19 PM PDT 24
Finished Jul 29 06:21:20 PM PDT 24
Peak memory 215604 kb
Host smart-fc1197f0-d21b-47d7-a186-c8020ed4e88a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159691374 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.159691374
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_err.14975389
Short name T207
Test name
Test status
Simulation time 26424483 ps
CPU time 1.14 seconds
Started Jul 29 06:21:21 PM PDT 24
Finished Jul 29 06:21:22 PM PDT 24
Peak memory 229540 kb
Host smart-6d62162b-b557-407c-837f-d1b270d79482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14975389 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.14975389
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3437302386
Short name T32
Test name
Test status
Simulation time 689658674 ps
CPU time 5.25 seconds
Started Jul 29 06:21:16 PM PDT 24
Finished Jul 29 06:21:21 PM PDT 24
Peak memory 219460 kb
Host smart-95f17763-5327-42be-8b5a-e4d008b02fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437302386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3437302386
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.415970525
Short name T727
Test name
Test status
Simulation time 21682938 ps
CPU time 1.11 seconds
Started Jul 29 06:21:07 PM PDT 24
Finished Jul 29 06:21:08 PM PDT 24
Peak memory 215372 kb
Host smart-f3e0c965-eb09-4fbc-a513-45079c4017df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415970525 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.415970525
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2341801304
Short name T550
Test name
Test status
Simulation time 15275609 ps
CPU time 0.96 seconds
Started Jul 29 06:21:27 PM PDT 24
Finished Jul 29 06:21:28 PM PDT 24
Peak memory 207112 kb
Host smart-d4e58bc2-3bb5-4734-bc2d-8a91844868e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341801304 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2341801304
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2246009483
Short name T369
Test name
Test status
Simulation time 28894805 ps
CPU time 1.02 seconds
Started Jul 29 06:21:15 PM PDT 24
Finished Jul 29 06:21:16 PM PDT 24
Peak memory 215452 kb
Host smart-7e96a75d-42b8-4591-9442-7fb8f2b491a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246009483 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2246009483
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2422031886
Short name T845
Test name
Test status
Simulation time 85215117 ps
CPU time 1.44 seconds
Started Jul 29 06:21:18 PM PDT 24
Finished Jul 29 06:21:19 PM PDT 24
Peak memory 215192 kb
Host smart-9796e7d9-71cf-4f0b-b813-6e49593f14e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422031886 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2422031886
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2098934834
Short name T227
Test name
Test status
Simulation time 20205761772 ps
CPU time 447.97 seconds
Started Jul 29 06:21:27 PM PDT 24
Finished Jul 29 06:28:55 PM PDT 24
Peak memory 223676 kb
Host smart-a04a3652-96b6-4053-b5ff-c6b481f1f229
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098934834 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2098934834
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.3948117055
Short name T708
Test name
Test status
Simulation time 81288086 ps
CPU time 1.2 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:38 PM PDT 24
Peak memory 219796 kb
Host smart-c8f1c008-58ae-4f64-8134-5d8213ac3f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948117055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.3948117055
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.4143370914
Short name T13
Test name
Test status
Simulation time 22397314 ps
CPU time 1.07 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 223944 kb
Host smart-d43a1f7f-7273-4e4b-b172-c78cae98d583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143370914 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.4143370914
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/91.edn_alert.285014305
Short name T947
Test name
Test status
Simulation time 41942431 ps
CPU time 1.01 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:37 PM PDT 24
Peak memory 218408 kb
Host smart-3b6a2022-cc2e-41fa-ac5c-7df9261758c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285014305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.285014305
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.1679556222
Short name T455
Test name
Test status
Simulation time 87969784 ps
CPU time 1.05 seconds
Started Jul 29 06:22:51 PM PDT 24
Finished Jul 29 06:22:52 PM PDT 24
Peak memory 220848 kb
Host smart-62a9c89b-c910-43cf-b260-13455fc8e542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679556222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1679556222
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2327762723
Short name T368
Test name
Test status
Simulation time 41864472 ps
CPU time 1.22 seconds
Started Jul 29 06:22:38 PM PDT 24
Finished Jul 29 06:22:40 PM PDT 24
Peak memory 220184 kb
Host smart-9e61913a-f163-48f3-9e03-bdd750a2420a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327762723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2327762723
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.554473387
Short name T645
Test name
Test status
Simulation time 37879692 ps
CPU time 1.1 seconds
Started Jul 29 06:22:32 PM PDT 24
Finished Jul 29 06:22:33 PM PDT 24
Peak memory 218664 kb
Host smart-fb499911-aa58-4426-93cc-3e4cf08407ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554473387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.554473387
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.255701715
Short name T501
Test name
Test status
Simulation time 59319876 ps
CPU time 1.09 seconds
Started Jul 29 06:22:35 PM PDT 24
Finished Jul 29 06:22:36 PM PDT 24
Peak memory 220572 kb
Host smart-f4923280-5e32-43c5-9d47-3a1b41d74cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255701715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.255701715
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3665842022
Short name T470
Test name
Test status
Simulation time 46204158 ps
CPU time 1.8 seconds
Started Jul 29 06:22:39 PM PDT 24
Finished Jul 29 06:22:41 PM PDT 24
Peak memory 218340 kb
Host smart-240857df-3683-4cb4-ad6a-d715dad60361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665842022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3665842022
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.3235313996
Short name T952
Test name
Test status
Simulation time 42869920 ps
CPU time 1.14 seconds
Started Jul 29 06:22:36 PM PDT 24
Finished Jul 29 06:22:37 PM PDT 24
Peak memory 215684 kb
Host smart-f78ec9bf-4132-4720-b321-3f024caa3826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235313996 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.3235313996
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.2314950246
Short name T873
Test name
Test status
Simulation time 20075548 ps
CPU time 0.91 seconds
Started Jul 29 06:22:42 PM PDT 24
Finished Jul 29 06:22:43 PM PDT 24
Peak memory 218532 kb
Host smart-281fb887-23eb-419e-aba3-510226596fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314950246 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2314950246
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2434648533
Short name T532
Test name
Test status
Simulation time 38212887 ps
CPU time 1.44 seconds
Started Jul 29 06:22:34 PM PDT 24
Finished Jul 29 06:22:35 PM PDT 24
Peak memory 215320 kb
Host smart-5a398844-842e-42fe-b4e2-233c03089c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434648533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2434648533
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1527645657
Short name T158
Test name
Test status
Simulation time 53911740 ps
CPU time 1.27 seconds
Started Jul 29 06:22:39 PM PDT 24
Finished Jul 29 06:22:41 PM PDT 24
Peak memory 215708 kb
Host smart-8c0f3199-1f7c-47c1-8b8f-9385004587d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527645657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1527645657
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1092656173
Short name T178
Test name
Test status
Simulation time 20633449 ps
CPU time 1.06 seconds
Started Jul 29 06:22:28 PM PDT 24
Finished Jul 29 06:22:29 PM PDT 24
Peak memory 218536 kb
Host smart-e193886b-b002-4816-a530-ffd234dec863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092656173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1092656173
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2729022267
Short name T573
Test name
Test status
Simulation time 24259837 ps
CPU time 1.1 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 217216 kb
Host smart-c32e6333-d991-4079-8375-660884370549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729022267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2729022267
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.4137101256
Short name T960
Test name
Test status
Simulation time 25927123 ps
CPU time 0.94 seconds
Started Jul 29 06:22:28 PM PDT 24
Finished Jul 29 06:22:29 PM PDT 24
Peak memory 218696 kb
Host smart-30940bee-a73e-454f-8a25-ec03168896c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137101256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4137101256
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.805904420
Short name T302
Test name
Test status
Simulation time 151717384 ps
CPU time 1.25 seconds
Started Jul 29 06:22:43 PM PDT 24
Finished Jul 29 06:22:45 PM PDT 24
Peak memory 218884 kb
Host smart-779b24c7-9e90-42ee-945f-f316b4089da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805904420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.805904420
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.2287212201
Short name T106
Test name
Test status
Simulation time 150526809 ps
CPU time 1.24 seconds
Started Jul 29 06:22:33 PM PDT 24
Finished Jul 29 06:22:34 PM PDT 24
Peak memory 218932 kb
Host smart-02700792-c60e-4eef-8f3b-8148332027ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287212201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.2287212201
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3377797577
Short name T747
Test name
Test status
Simulation time 35194903 ps
CPU time 0.86 seconds
Started Jul 29 06:22:44 PM PDT 24
Finished Jul 29 06:22:45 PM PDT 24
Peak memory 218468 kb
Host smart-1e4a9ae1-a624-4d30-8972-1a08d2a13f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377797577 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3377797577
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3593601834
Short name T817
Test name
Test status
Simulation time 63720753 ps
CPU time 1.46 seconds
Started Jul 29 06:22:34 PM PDT 24
Finished Jul 29 06:22:36 PM PDT 24
Peak memory 218768 kb
Host smart-cc5607ee-39db-4b64-a567-91679552ab6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593601834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3593601834
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3884756008
Short name T506
Test name
Test status
Simulation time 121900871 ps
CPU time 1.13 seconds
Started Jul 29 06:22:26 PM PDT 24
Finished Jul 29 06:22:27 PM PDT 24
Peak memory 219572 kb
Host smart-b0de646b-97c5-4969-809a-c17d623447ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884756008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3884756008
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.4283568541
Short name T790
Test name
Test status
Simulation time 24921389 ps
CPU time 1.11 seconds
Started Jul 29 06:22:33 PM PDT 24
Finished Jul 29 06:22:35 PM PDT 24
Peak memory 223952 kb
Host smart-f12fc992-3734-453b-ae92-61e6fa51c6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283568541 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.4283568541
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.999070551
Short name T895
Test name
Test status
Simulation time 355020977 ps
CPU time 1.34 seconds
Started Jul 29 06:22:34 PM PDT 24
Finished Jul 29 06:22:36 PM PDT 24
Peak memory 219996 kb
Host smart-6933cfc7-6674-417a-9a8c-1e9ad0074056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999070551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.999070551
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.3442409896
Short name T725
Test name
Test status
Simulation time 45866389 ps
CPU time 1.18 seconds
Started Jul 29 06:22:27 PM PDT 24
Finished Jul 29 06:22:29 PM PDT 24
Peak memory 218500 kb
Host smart-5513d506-dcec-4b76-8041-af8e4f72ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442409896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.3442409896
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1236717020
Short name T143
Test name
Test status
Simulation time 32018534 ps
CPU time 1.24 seconds
Started Jul 29 06:22:31 PM PDT 24
Finished Jul 29 06:22:33 PM PDT 24
Peak memory 229568 kb
Host smart-e93c6185-0ab2-413e-87fd-2498346a7872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236717020 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1236717020
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2845841925
Short name T835
Test name
Test status
Simulation time 52026014 ps
CPU time 1.51 seconds
Started Jul 29 06:22:49 PM PDT 24
Finished Jul 29 06:22:51 PM PDT 24
Peak memory 217512 kb
Host smart-b95c915f-226c-40fd-82d3-30e50955e5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845841925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2845841925
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.3976952070
Short name T103
Test name
Test status
Simulation time 26690269 ps
CPU time 1.15 seconds
Started Jul 29 06:22:37 PM PDT 24
Finished Jul 29 06:22:39 PM PDT 24
Peak memory 218576 kb
Host smart-a1b3ffbc-9a07-4945-9e70-d2e0b184d34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976952070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.3976952070
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.204193596
Short name T126
Test name
Test status
Simulation time 158453024 ps
CPU time 1.16 seconds
Started Jul 29 06:22:33 PM PDT 24
Finished Jul 29 06:22:34 PM PDT 24
Peak memory 225692 kb
Host smart-926eb927-2558-4593-8759-d35bfda55e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204193596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.204193596
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1396699640
Short name T805
Test name
Test status
Simulation time 51615480 ps
CPU time 1.69 seconds
Started Jul 29 06:22:29 PM PDT 24
Finished Jul 29 06:22:30 PM PDT 24
Peak memory 217168 kb
Host smart-f8b9ebe8-7280-4dd3-8bb4-73509f413e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396699640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1396699640
Directory /workspace/99.edn_genbits/latest
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