Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.38 98.25 93.25 91.10 86.63 95.50 96.83 92.08


Total test records in report: 1125
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T277 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3284126533 Jul 30 05:58:28 PM PDT 24 Jul 30 05:58:29 PM PDT 24 23176420 ps
T1017 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1173693654 Jul 30 05:58:36 PM PDT 24 Jul 30 05:58:37 PM PDT 24 29143773 ps
T1018 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.508536578 Jul 30 05:58:41 PM PDT 24 Jul 30 05:58:42 PM PDT 24 26388431 ps
T1019 /workspace/coverage/cover_reg_top/43.edn_intr_test.2587754108 Jul 30 05:59:00 PM PDT 24 Jul 30 05:59:01 PM PDT 24 19876164 ps
T1020 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2683703008 Jul 30 05:58:24 PM PDT 24 Jul 30 05:58:28 PM PDT 24 2004627590 ps
T1021 /workspace/coverage/cover_reg_top/2.edn_intr_test.2773782387 Jul 30 05:58:14 PM PDT 24 Jul 30 05:58:15 PM PDT 24 44107365 ps
T1022 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1550285468 Jul 30 05:58:47 PM PDT 24 Jul 30 05:58:49 PM PDT 24 73213260 ps
T1023 /workspace/coverage/cover_reg_top/9.edn_intr_test.2486187491 Jul 30 05:58:28 PM PDT 24 Jul 30 05:58:29 PM PDT 24 14323360 ps
T278 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2362592041 Jul 30 05:58:14 PM PDT 24 Jul 30 05:58:15 PM PDT 24 18245687 ps
T224 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.630981601 Jul 30 05:58:54 PM PDT 24 Jul 30 05:58:57 PM PDT 24 204171513 ps
T1024 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2530665949 Jul 30 05:58:22 PM PDT 24 Jul 30 05:58:24 PM PDT 24 154769638 ps
T1025 /workspace/coverage/cover_reg_top/6.edn_intr_test.3299954331 Jul 30 05:58:24 PM PDT 24 Jul 30 05:58:25 PM PDT 24 13739577 ps
T1026 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2770585330 Jul 30 05:58:10 PM PDT 24 Jul 30 05:58:11 PM PDT 24 24243637 ps
T1027 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2148525258 Jul 30 05:58:43 PM PDT 24 Jul 30 05:58:44 PM PDT 24 85540775 ps
T1028 /workspace/coverage/cover_reg_top/19.edn_intr_test.3230208733 Jul 30 05:58:49 PM PDT 24 Jul 30 05:58:50 PM PDT 24 14177082 ps
T1029 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1111006203 Jul 30 05:58:25 PM PDT 24 Jul 30 05:58:28 PM PDT 24 82862691 ps
T1030 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3631995674 Jul 30 05:58:33 PM PDT 24 Jul 30 05:58:34 PM PDT 24 14457759 ps
T1031 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2897254176 Jul 30 05:58:09 PM PDT 24 Jul 30 05:58:10 PM PDT 24 107462005 ps
T1032 /workspace/coverage/cover_reg_top/26.edn_intr_test.4156385639 Jul 30 05:59:06 PM PDT 24 Jul 30 05:59:06 PM PDT 24 77996649 ps
T1033 /workspace/coverage/cover_reg_top/14.edn_intr_test.2557596340 Jul 30 05:58:41 PM PDT 24 Jul 30 05:58:42 PM PDT 24 44352066 ps
T1034 /workspace/coverage/cover_reg_top/4.edn_intr_test.22186380 Jul 30 05:58:26 PM PDT 24 Jul 30 05:58:27 PM PDT 24 13201428 ps
T298 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2817844122 Jul 30 05:59:06 PM PDT 24 Jul 30 05:59:08 PM PDT 24 76539310 ps
T1035 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.222981540 Jul 30 05:58:05 PM PDT 24 Jul 30 05:58:07 PM PDT 24 41780592 ps
T1036 /workspace/coverage/cover_reg_top/1.edn_intr_test.1757090816 Jul 30 05:58:11 PM PDT 24 Jul 30 05:58:12 PM PDT 24 13214664 ps
T1037 /workspace/coverage/cover_reg_top/27.edn_intr_test.1555216474 Jul 30 05:58:53 PM PDT 24 Jul 30 05:58:54 PM PDT 24 50635317 ps
T1038 /workspace/coverage/cover_reg_top/30.edn_intr_test.210059712 Jul 30 05:58:52 PM PDT 24 Jul 30 05:58:53 PM PDT 24 11326701 ps
T1039 /workspace/coverage/cover_reg_top/8.edn_intr_test.1652459151 Jul 30 05:58:28 PM PDT 24 Jul 30 05:58:30 PM PDT 24 38376860 ps
T1040 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2802080963 Jul 30 05:59:05 PM PDT 24 Jul 30 05:59:06 PM PDT 24 96589418 ps
T1041 /workspace/coverage/cover_reg_top/40.edn_intr_test.1753538108 Jul 30 05:59:09 PM PDT 24 Jul 30 05:59:10 PM PDT 24 12086583 ps
T1042 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1267040456 Jul 30 05:58:42 PM PDT 24 Jul 30 05:58:44 PM PDT 24 265027750 ps
T1043 /workspace/coverage/cover_reg_top/33.edn_intr_test.2234273958 Jul 30 05:58:54 PM PDT 24 Jul 30 05:58:55 PM PDT 24 32370062 ps
T1044 /workspace/coverage/cover_reg_top/18.edn_tl_errors.367336940 Jul 30 05:59:02 PM PDT 24 Jul 30 05:59:06 PM PDT 24 187079542 ps
T1045 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2647469545 Jul 30 05:58:46 PM PDT 24 Jul 30 05:58:47 PM PDT 24 42797564 ps
T263 /workspace/coverage/cover_reg_top/12.edn_csr_rw.62955973 Jul 30 05:58:36 PM PDT 24 Jul 30 05:58:37 PM PDT 24 12239773 ps
T1046 /workspace/coverage/cover_reg_top/11.edn_intr_test.1683103531 Jul 30 05:58:41 PM PDT 24 Jul 30 05:58:42 PM PDT 24 89088335 ps
T264 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2898514439 Jul 30 05:58:09 PM PDT 24 Jul 30 05:58:10 PM PDT 24 109444987 ps
T1047 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3267830869 Jul 30 05:58:09 PM PDT 24 Jul 30 05:58:12 PM PDT 24 38846480 ps
T1048 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1885787501 Jul 30 05:58:50 PM PDT 24 Jul 30 05:58:51 PM PDT 24 15114515 ps
T299 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2768487095 Jul 30 05:58:42 PM PDT 24 Jul 30 05:58:44 PM PDT 24 597435203 ps
T1049 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.501743766 Jul 30 05:58:24 PM PDT 24 Jul 30 05:58:27 PM PDT 24 616769026 ps
T1050 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.249214801 Jul 30 05:58:41 PM PDT 24 Jul 30 05:58:42 PM PDT 24 126391074 ps
T1051 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1316866586 Jul 30 05:58:32 PM PDT 24 Jul 30 05:58:34 PM PDT 24 22907220 ps
T1052 /workspace/coverage/cover_reg_top/49.edn_intr_test.2669830740 Jul 30 05:59:01 PM PDT 24 Jul 30 05:59:02 PM PDT 24 15584401 ps
T265 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1614903004 Jul 30 05:58:07 PM PDT 24 Jul 30 05:58:08 PM PDT 24 14651852 ps
T1053 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.213381072 Jul 30 05:58:40 PM PDT 24 Jul 30 05:58:42 PM PDT 24 53302680 ps
T1054 /workspace/coverage/cover_reg_top/35.edn_intr_test.1112169876 Jul 30 05:58:54 PM PDT 24 Jul 30 05:58:55 PM PDT 24 17256770 ps
T1055 /workspace/coverage/cover_reg_top/10.edn_csr_rw.816887168 Jul 30 05:58:38 PM PDT 24 Jul 30 05:58:39 PM PDT 24 20954023 ps
T1056 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3199233204 Jul 30 05:59:04 PM PDT 24 Jul 30 05:59:05 PM PDT 24 22298971 ps
T1057 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3727357265 Jul 30 05:59:04 PM PDT 24 Jul 30 05:59:05 PM PDT 24 18465233 ps
T1058 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2314309631 Jul 30 05:58:22 PM PDT 24 Jul 30 05:58:23 PM PDT 24 17547221 ps
T1059 /workspace/coverage/cover_reg_top/12.edn_intr_test.2569786271 Jul 30 05:58:40 PM PDT 24 Jul 30 05:58:41 PM PDT 24 15196325 ps
T1060 /workspace/coverage/cover_reg_top/20.edn_intr_test.2925359028 Jul 30 05:58:51 PM PDT 24 Jul 30 05:58:52 PM PDT 24 29734180 ps
T1061 /workspace/coverage/cover_reg_top/4.edn_csr_rw.70608500 Jul 30 05:58:22 PM PDT 24 Jul 30 05:58:23 PM PDT 24 147968743 ps
T266 /workspace/coverage/cover_reg_top/7.edn_csr_rw.889585934 Jul 30 05:58:30 PM PDT 24 Jul 30 05:58:31 PM PDT 24 45710231 ps
T1062 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3364790491 Jul 30 05:58:37 PM PDT 24 Jul 30 05:58:39 PM PDT 24 31033128 ps
T1063 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2938125975 Jul 30 05:58:36 PM PDT 24 Jul 30 05:58:38 PM PDT 24 31216527 ps
T1064 /workspace/coverage/cover_reg_top/15.edn_intr_test.4065428893 Jul 30 05:58:38 PM PDT 24 Jul 30 05:58:39 PM PDT 24 43991731 ps
T1065 /workspace/coverage/cover_reg_top/16.edn_intr_test.3854758171 Jul 30 05:58:42 PM PDT 24 Jul 30 05:58:43 PM PDT 24 28854332 ps
T1066 /workspace/coverage/cover_reg_top/18.edn_intr_test.4193317304 Jul 30 05:58:52 PM PDT 24 Jul 30 05:58:53 PM PDT 24 11567574 ps
T1067 /workspace/coverage/cover_reg_top/8.edn_tl_errors.2342625120 Jul 30 05:58:31 PM PDT 24 Jul 30 05:58:33 PM PDT 24 29146182 ps
T302 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.344057165 Jul 30 05:58:29 PM PDT 24 Jul 30 05:58:31 PM PDT 24 306849210 ps
T1068 /workspace/coverage/cover_reg_top/46.edn_intr_test.1755983925 Jul 30 05:59:13 PM PDT 24 Jul 30 05:59:14 PM PDT 24 13847053 ps
T1069 /workspace/coverage/cover_reg_top/5.edn_intr_test.863906712 Jul 30 05:58:27 PM PDT 24 Jul 30 05:58:28 PM PDT 24 49660759 ps
T1070 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3206054880 Jul 30 05:58:14 PM PDT 24 Jul 30 05:58:15 PM PDT 24 33763408 ps
T1071 /workspace/coverage/cover_reg_top/39.edn_intr_test.241929554 Jul 30 05:59:01 PM PDT 24 Jul 30 05:59:02 PM PDT 24 46689919 ps
T1072 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1552680496 Jul 30 05:58:20 PM PDT 24 Jul 30 05:58:23 PM PDT 24 165240410 ps
T1073 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2172785419 Jul 30 05:58:28 PM PDT 24 Jul 30 05:58:29 PM PDT 24 39117975 ps
T1074 /workspace/coverage/cover_reg_top/28.edn_intr_test.3487655102 Jul 30 05:58:53 PM PDT 24 Jul 30 05:58:54 PM PDT 24 28509215 ps
T300 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3080656940 Jul 30 05:58:38 PM PDT 24 Jul 30 05:58:41 PM PDT 24 204447141 ps
T1075 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2621081511 Jul 30 05:58:12 PM PDT 24 Jul 30 05:58:14 PM PDT 24 189184140 ps
T1076 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.322973901 Jul 30 05:58:14 PM PDT 24 Jul 30 05:58:16 PM PDT 24 230106521 ps
T1077 /workspace/coverage/cover_reg_top/9.edn_tl_errors.664688362 Jul 30 05:58:29 PM PDT 24 Jul 30 05:58:31 PM PDT 24 170249714 ps
T1078 /workspace/coverage/cover_reg_top/14.edn_tl_errors.656997645 Jul 30 05:58:59 PM PDT 24 Jul 30 05:59:01 PM PDT 24 26408873 ps
T1079 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.534597866 Jul 30 05:58:45 PM PDT 24 Jul 30 05:58:46 PM PDT 24 54291592 ps
T1080 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3256245536 Jul 30 05:58:57 PM PDT 24 Jul 30 05:58:59 PM PDT 24 272000621 ps
T1081 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1267332990 Jul 30 05:58:29 PM PDT 24 Jul 30 05:58:30 PM PDT 24 73482696 ps
T1082 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2861443238 Jul 30 05:58:20 PM PDT 24 Jul 30 05:58:21 PM PDT 24 36777917 ps
T1083 /workspace/coverage/cover_reg_top/41.edn_intr_test.3941846578 Jul 30 05:58:56 PM PDT 24 Jul 30 05:58:57 PM PDT 24 40380609 ps
T1084 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.219166171 Jul 30 05:58:41 PM PDT 24 Jul 30 05:58:42 PM PDT 24 78114460 ps
T267 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1786054083 Jul 30 05:58:12 PM PDT 24 Jul 30 05:58:13 PM PDT 24 54200746 ps
T1085 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2667563664 Jul 30 05:58:40 PM PDT 24 Jul 30 05:58:41 PM PDT 24 29880639 ps
T1086 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4160770065 Jul 30 05:58:28 PM PDT 24 Jul 30 05:58:30 PM PDT 24 88945748 ps
T1087 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.757327222 Jul 30 05:58:18 PM PDT 24 Jul 30 05:58:23 PM PDT 24 708286145 ps
T1088 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.872305824 Jul 30 05:58:40 PM PDT 24 Jul 30 05:58:43 PM PDT 24 97909609 ps
T1089 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4048530005 Jul 30 05:58:49 PM PDT 24 Jul 30 05:58:50 PM PDT 24 23521786 ps
T1090 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1567435884 Jul 30 05:58:11 PM PDT 24 Jul 30 05:58:12 PM PDT 24 58406673 ps
T1091 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1369595620 Jul 30 05:58:13 PM PDT 24 Jul 30 05:58:15 PM PDT 24 62434660 ps
T1092 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.309427743 Jul 30 05:58:25 PM PDT 24 Jul 30 05:58:27 PM PDT 24 37447654 ps
T1093 /workspace/coverage/cover_reg_top/7.edn_intr_test.2516303691 Jul 30 05:58:29 PM PDT 24 Jul 30 05:58:30 PM PDT 24 23237010 ps
T1094 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3260079104 Jul 30 05:58:37 PM PDT 24 Jul 30 05:58:39 PM PDT 24 378218415 ps
T1095 /workspace/coverage/cover_reg_top/1.edn_tl_errors.349860781 Jul 30 05:58:09 PM PDT 24 Jul 30 05:58:11 PM PDT 24 21044513 ps
T1096 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2543778228 Jul 30 05:58:09 PM PDT 24 Jul 30 05:58:13 PM PDT 24 218445804 ps
T268 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.714078833 Jul 30 05:58:25 PM PDT 24 Jul 30 05:58:26 PM PDT 24 70818688 ps
T1097 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1974004131 Jul 30 05:58:19 PM PDT 24 Jul 30 05:58:20 PM PDT 24 35414967 ps
T1098 /workspace/coverage/cover_reg_top/10.edn_intr_test.2871512294 Jul 30 05:58:31 PM PDT 24 Jul 30 05:58:32 PM PDT 24 23229328 ps
T1099 /workspace/coverage/cover_reg_top/0.edn_intr_test.1168405737 Jul 30 05:58:08 PM PDT 24 Jul 30 05:58:09 PM PDT 24 13305489 ps
T1100 /workspace/coverage/cover_reg_top/17.edn_intr_test.1458013308 Jul 30 05:58:53 PM PDT 24 Jul 30 05:58:54 PM PDT 24 73515188 ps
T1101 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1031215944 Jul 30 05:58:19 PM PDT 24 Jul 30 05:58:23 PM PDT 24 271335123 ps
T1102 /workspace/coverage/cover_reg_top/47.edn_intr_test.2984313921 Jul 30 05:59:03 PM PDT 24 Jul 30 05:59:04 PM PDT 24 24313672 ps
T1103 /workspace/coverage/cover_reg_top/44.edn_intr_test.585820362 Jul 30 05:59:03 PM PDT 24 Jul 30 05:59:04 PM PDT 24 12998935 ps
T301 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3599988409 Jul 30 05:58:30 PM PDT 24 Jul 30 05:58:32 PM PDT 24 698135731 ps
T1104 /workspace/coverage/cover_reg_top/6.edn_tl_errors.975962967 Jul 30 05:58:23 PM PDT 24 Jul 30 05:58:28 PM PDT 24 1948675761 ps
T1105 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.812423743 Jul 30 05:58:29 PM PDT 24 Jul 30 05:58:30 PM PDT 24 44677993 ps
T1106 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.140542778 Jul 30 05:58:38 PM PDT 24 Jul 30 05:58:40 PM PDT 24 176994980 ps
T1107 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.516383872 Jul 30 05:58:14 PM PDT 24 Jul 30 05:58:20 PM PDT 24 1835278691 ps
T1108 /workspace/coverage/cover_reg_top/45.edn_intr_test.103471232 Jul 30 05:59:02 PM PDT 24 Jul 30 05:59:04 PM PDT 24 104872885 ps
T1109 /workspace/coverage/cover_reg_top/34.edn_intr_test.1758332978 Jul 30 05:58:54 PM PDT 24 Jul 30 05:58:55 PM PDT 24 11617818 ps
T1110 /workspace/coverage/cover_reg_top/24.edn_intr_test.3198837594 Jul 30 05:58:53 PM PDT 24 Jul 30 05:58:54 PM PDT 24 55991557 ps
T1111 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3552057538 Jul 30 05:58:47 PM PDT 24 Jul 30 05:58:48 PM PDT 24 16641378 ps
T1112 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1852415249 Jul 30 05:58:14 PM PDT 24 Jul 30 05:58:16 PM PDT 24 123786877 ps
T1113 /workspace/coverage/cover_reg_top/48.edn_intr_test.1815847466 Jul 30 05:59:13 PM PDT 24 Jul 30 05:59:14 PM PDT 24 17025117 ps
T1114 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.66011833 Jul 30 05:58:31 PM PDT 24 Jul 30 05:58:32 PM PDT 24 57870303 ps
T1115 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3732949996 Jul 30 05:58:16 PM PDT 24 Jul 30 05:58:19 PM PDT 24 349613765 ps
T1116 /workspace/coverage/cover_reg_top/25.edn_intr_test.1345062333 Jul 30 05:59:12 PM PDT 24 Jul 30 05:59:13 PM PDT 24 11867037 ps
T269 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2159439574 Jul 30 05:58:11 PM PDT 24 Jul 30 05:58:14 PM PDT 24 434115164 ps
T1117 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.512487372 Jul 30 05:58:28 PM PDT 24 Jul 30 05:58:30 PM PDT 24 50930153 ps
T1118 /workspace/coverage/cover_reg_top/38.edn_intr_test.2278013852 Jul 30 05:58:55 PM PDT 24 Jul 30 05:58:56 PM PDT 24 56651962 ps
T1119 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3688555621 Jul 30 05:58:39 PM PDT 24 Jul 30 05:58:41 PM PDT 24 25050635 ps
T1120 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3795267241 Jul 30 05:58:30 PM PDT 24 Jul 30 05:58:32 PM PDT 24 55000820 ps
T1121 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1337380578 Jul 30 05:58:42 PM PDT 24 Jul 30 05:58:43 PM PDT 24 30770555 ps
T1122 /workspace/coverage/cover_reg_top/19.edn_csr_rw.4007245650 Jul 30 05:58:48 PM PDT 24 Jul 30 05:58:49 PM PDT 24 76502585 ps
T1123 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.851866159 Jul 30 05:58:37 PM PDT 24 Jul 30 05:58:40 PM PDT 24 116572110 ps
T270 /workspace/coverage/cover_reg_top/2.edn_csr_rw.516716007 Jul 30 05:58:15 PM PDT 24 Jul 30 05:58:16 PM PDT 24 14184043 ps
T1124 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2059173819 Jul 30 05:59:05 PM PDT 24 Jul 30 05:59:09 PM PDT 24 101531234 ps
T1125 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1993638279 Jul 30 05:58:26 PM PDT 24 Jul 30 05:58:28 PM PDT 24 160302977 ps

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3007215221
Short name T9
Test name
Test status
Simulation time 43776398 ps
CPU time 1.4 seconds
Started Jul 30 06:44:52 PM PDT 24
Finished Jul 30 06:44:54 PM PDT 24
Peak memory 216940 kb
Host smart-8a1c0c30-0cfe-4beb-8985-0fb96c105b59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007215221 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3007215221
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1690570060
Short name T23
Test name
Test status
Simulation time 53833721804 ps
CPU time 1223.43 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 07:05:37 PM PDT 24
Peak memory 223776 kb
Host smart-768d7b5d-8ecd-413e-a2a6-15eff409ca55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690570060 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1690570060
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/223.edn_genbits.111916112
Short name T40
Test name
Test status
Simulation time 40154691 ps
CPU time 1.64 seconds
Started Jul 30 06:46:04 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 218540 kb
Host smart-efa71c35-311e-47b6-8edc-e384c32ff885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111916112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.111916112
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_err.1841245788
Short name T1
Test name
Test status
Simulation time 18944063 ps
CPU time 1.04 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 218592 kb
Host smart-d637b195-365b-4803-865f-34fa9cb3bfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841245788 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1841245788
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/118.edn_alert.3376808714
Short name T3
Test name
Test status
Simulation time 40527777 ps
CPU time 1.06 seconds
Started Jul 30 06:45:37 PM PDT 24
Finished Jul 30 06:45:38 PM PDT 24
Peak memory 220836 kb
Host smart-b95a0ea1-0d7c-4251-bad7-f0cab5468849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376808714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.3376808714
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/29.edn_err.3916991093
Short name T5
Test name
Test status
Simulation time 30673174 ps
CPU time 0.96 seconds
Started Jul 30 06:44:40 PM PDT 24
Finished Jul 30 06:44:41 PM PDT 24
Peak memory 223792 kb
Host smart-7e483d7b-fc2d-479f-8caf-f466e5fca161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916991093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3916991093
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.4237381547
Short name T32
Test name
Test status
Simulation time 98605587 ps
CPU time 1.4 seconds
Started Jul 30 06:45:10 PM PDT 24
Finished Jul 30 06:45:12 PM PDT 24
Peak memory 218628 kb
Host smart-77f8dfa8-76e2-4da5-8383-01ecbe74d5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237381547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.4237381547
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_disable.2618475382
Short name T194
Test name
Test status
Simulation time 15481231 ps
CPU time 0.98 seconds
Started Jul 30 06:44:44 PM PDT 24
Finished Jul 30 06:44:45 PM PDT 24
Peak memory 216496 kb
Host smart-270274a7-9557-453a-85b7-c4e6dcdee3a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618475382 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2618475382
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/122.edn_alert.578595895
Short name T33
Test name
Test status
Simulation time 97079420 ps
CPU time 1.33 seconds
Started Jul 30 06:45:49 PM PDT 24
Finished Jul 30 06:45:51 PM PDT 24
Peak memory 215660 kb
Host smart-764a819a-b6fe-4ab1-b8e4-2a254c22cab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578595895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.578595895
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/1.edn_genbits.2787607802
Short name T30
Test name
Test status
Simulation time 114495571 ps
CPU time 2.58 seconds
Started Jul 30 06:44:13 PM PDT 24
Finished Jul 30 06:44:15 PM PDT 24
Peak memory 220228 kb
Host smart-7f04c7b4-f86f-4cf6-98fc-6e2e0e0598c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787607802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2787607802
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2178450470
Short name T25
Test name
Test status
Simulation time 430307005478 ps
CPU time 659.23 seconds
Started Jul 30 06:44:47 PM PDT 24
Finished Jul 30 06:55:46 PM PDT 24
Peak memory 219968 kb
Host smart-5e2a897e-56aa-4189-8361-9dc1c5d9e52e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178450470 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2178450470
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.edn_alert.3659730946
Short name T142
Test name
Test status
Simulation time 89817885 ps
CPU time 1.15 seconds
Started Jul 30 06:45:28 PM PDT 24
Finished Jul 30 06:45:30 PM PDT 24
Peak memory 218848 kb
Host smart-b188db8e-11a7-44be-b130-86f7b8049220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659730946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3659730946
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/23.edn_intr.2768827848
Short name T89
Test name
Test status
Simulation time 41858144 ps
CPU time 0.87 seconds
Started Jul 30 06:44:39 PM PDT 24
Finished Jul 30 06:44:40 PM PDT 24
Peak memory 215680 kb
Host smart-15739f37-80ce-42c6-9995-76086605d396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768827848 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2768827848
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.224956288
Short name T307
Test name
Test status
Simulation time 26432007 ps
CPU time 0.91 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 207044 kb
Host smart-ad33f285-bb33-464e-8fe9-b29fcc1e9c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224956288 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.224956288
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2817844122
Short name T298
Test name
Test status
Simulation time 76539310 ps
CPU time 2.25 seconds
Started Jul 30 05:59:06 PM PDT 24
Finished Jul 30 05:59:08 PM PDT 24
Peak memory 206428 kb
Host smart-2237d518-7e46-46c4-9323-5cdc750f4565
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817844122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2817844122
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/default/80.edn_alert.3749233498
Short name T64
Test name
Test status
Simulation time 122543444 ps
CPU time 1.15 seconds
Started Jul 30 06:45:06 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 219832 kb
Host smart-ef73e500-5c72-4750-baa8-b44ec65aaf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749233498 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.3749233498
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3264862633
Short name T18
Test name
Test status
Simulation time 95268044 ps
CPU time 1.11 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 216876 kb
Host smart-3c64f962-cfff-4e5b-9c11-4ca2c8016246
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264862633 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3264862633
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3721682257
Short name T232
Test name
Test status
Simulation time 101852954074 ps
CPU time 1123.04 seconds
Started Jul 30 06:44:27 PM PDT 24
Finished Jul 30 07:03:11 PM PDT 24
Peak memory 223756 kb
Host smart-7fd9ab2f-9457-40af-b60f-17eaf5e35159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721682257 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3721682257
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2324525905
Short name T123
Test name
Test status
Simulation time 54786690 ps
CPU time 1.06 seconds
Started Jul 30 06:44:27 PM PDT 24
Finished Jul 30 06:44:29 PM PDT 24
Peak memory 216984 kb
Host smart-27efea2e-538f-4ccf-9c72-cc9dd3b32983
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324525905 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2324525905
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_disable.3299979361
Short name T97
Test name
Test status
Simulation time 28270584 ps
CPU time 0.86 seconds
Started Jul 30 06:44:14 PM PDT 24
Finished Jul 30 06:44:15 PM PDT 24
Peak memory 216236 kb
Host smart-17fefaba-be93-4543-b6a0-865c1d724e1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299979361 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3299979361
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/125.edn_alert.323844847
Short name T291
Test name
Test status
Simulation time 254275191 ps
CPU time 1.37 seconds
Started Jul 30 06:45:51 PM PDT 24
Finished Jul 30 06:45:52 PM PDT 24
Peak memory 219896 kb
Host smart-bdba3118-69bd-4a31-bbc9-eab91e5a2ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323844847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.323844847
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/33.edn_disable.917618608
Short name T96
Test name
Test status
Simulation time 36088357 ps
CPU time 0.86 seconds
Started Jul 30 06:45:03 PM PDT 24
Finished Jul 30 06:45:04 PM PDT 24
Peak memory 216148 kb
Host smart-d66ad65a-4e99-4d36-b012-c319a078286b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917618608 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.917618608
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable.3445816024
Short name T112
Test name
Test status
Simulation time 21122833 ps
CPU time 0.89 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 216200 kb
Host smart-82dfff3f-40fa-457e-8544-67e6d75b1f75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445816024 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3445816024
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.876896725
Short name T260
Test name
Test status
Simulation time 38393184 ps
CPU time 1.57 seconds
Started Jul 30 05:58:07 PM PDT 24
Finished Jul 30 05:58:08 PM PDT 24
Peak memory 206544 kb
Host smart-67309674-11aa-4062-9393-76f8c72fd29f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876896725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.876896725
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/29.edn_intr.458269524
Short name T93
Test name
Test status
Simulation time 32317033 ps
CPU time 0.86 seconds
Started Jul 30 06:44:52 PM PDT 24
Finished Jul 30 06:44:53 PM PDT 24
Peak memory 215616 kb
Host smart-2f92da9c-1c6f-4039-aace-343211908106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458269524 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.458269524
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/191.edn_alert.2895913760
Short name T283
Test name
Test status
Simulation time 118669456 ps
CPU time 1.08 seconds
Started Jul 30 06:46:04 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 218520 kb
Host smart-74f64326-c19a-46d6-afd0-4b871c24f7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895913760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.2895913760
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/103.edn_alert.580378737
Short name T135
Test name
Test status
Simulation time 46806356 ps
CPU time 1.18 seconds
Started Jul 30 06:45:35 PM PDT 24
Finished Jul 30 06:45:36 PM PDT 24
Peak memory 220412 kb
Host smart-dcb45dfc-f3ab-4cc1-98ed-74c9b14ca340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580378737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.580378737
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.3539068720
Short name T316
Test name
Test status
Simulation time 72130721 ps
CPU time 1.06 seconds
Started Jul 30 06:46:02 PM PDT 24
Finished Jul 30 06:46:03 PM PDT 24
Peak memory 217164 kb
Host smart-84ea9ba7-40d1-475a-8aad-45574b85c31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539068720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3539068720
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/220.edn_genbits.2257122304
Short name T555
Test name
Test status
Simulation time 55430778 ps
CPU time 1.88 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 215352 kb
Host smart-ac2cb8e5-48a9-48dd-9604-435dff9dc0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257122304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2257122304
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3847196468
Short name T173
Test name
Test status
Simulation time 76320353 ps
CPU time 1.18 seconds
Started Jul 30 06:45:50 PM PDT 24
Finished Jul 30 06:45:52 PM PDT 24
Peak memory 219008 kb
Host smart-495ee30b-13dc-45b0-9d38-af06291391e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847196468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3847196468
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/144.edn_alert.1111425394
Short name T219
Test name
Test status
Simulation time 31321764 ps
CPU time 1.23 seconds
Started Jul 30 06:45:56 PM PDT 24
Finished Jul 30 06:45:57 PM PDT 24
Peak memory 220960 kb
Host smart-14f45f91-e8ff-4404-bd6c-e85ad8277a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111425394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1111425394
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/153.edn_alert.1771939729
Short name T39
Test name
Test status
Simulation time 32334282 ps
CPU time 1.31 seconds
Started Jul 30 06:45:53 PM PDT 24
Finished Jul 30 06:45:55 PM PDT 24
Peak memory 219784 kb
Host smart-57a04664-8636-4452-8006-03e8a786e697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771939729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1771939729
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/192.edn_alert.2900685530
Short name T54
Test name
Test status
Simulation time 175333335 ps
CPU time 1.16 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 215680 kb
Host smart-8f9cdaf6-6a97-400a-899a-d15f5701e956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900685530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2900685530
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/21.edn_err.2707807255
Short name T110
Test name
Test status
Simulation time 20787805 ps
CPU time 1.05 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 218452 kb
Host smart-329c9e20-a747-4840-b825-22e089e5857d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707807255 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2707807255
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/146.edn_alert.2758697281
Short name T62
Test name
Test status
Simulation time 142388553 ps
CPU time 1.13 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 220048 kb
Host smart-5047e99d-079e-409e-972b-697a3144c110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758697281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2758697281
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert.2130596266
Short name T285
Test name
Test status
Simulation time 83715922 ps
CPU time 1.13 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 219736 kb
Host smart-56042816-7986-42b9-b231-5c8574db9b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130596266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2130596266
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_disable.1229116892
Short name T497
Test name
Test status
Simulation time 42001113 ps
CPU time 0.86 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 207084 kb
Host smart-893c9022-7d08-4488-a137-720890e66241
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229116892 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1229116892
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3383950794
Short name T294
Test name
Test status
Simulation time 148807499 ps
CPU time 1.13 seconds
Started Jul 30 06:45:04 PM PDT 24
Finished Jul 30 06:45:06 PM PDT 24
Peak memory 218624 kb
Host smart-c7ee86d2-24bb-4ac4-a21d-2a1096d2bbfd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383950794 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3383950794
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/56.edn_alert.116897675
Short name T909
Test name
Test status
Simulation time 27257358 ps
CPU time 1.21 seconds
Started Jul 30 06:45:11 PM PDT 24
Finished Jul 30 06:45:12 PM PDT 24
Peak memory 220440 kb
Host smart-0bd80dfe-c0e6-488a-b381-ace7d888e08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116897675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.116897675
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/5.edn_disable.4014737077
Short name T896
Test name
Test status
Simulation time 11186878 ps
CPU time 0.88 seconds
Started Jul 30 06:44:13 PM PDT 24
Finished Jul 30 06:44:14 PM PDT 24
Peak memory 216368 kb
Host smart-57cf4968-c2e4-4200-aa71-bcbd516dbc06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014737077 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.4014737077
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.4115631584
Short name T95
Test name
Test status
Simulation time 67988110 ps
CPU time 1.02 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 219628 kb
Host smart-3244cc52-e21e-4223-976b-0f6c3da28ad6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115631584 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.4115631584
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3750483539
Short name T535
Test name
Test status
Simulation time 54656476 ps
CPU time 1.14 seconds
Started Jul 30 06:44:12 PM PDT 24
Finished Jul 30 06:44:14 PM PDT 24
Peak memory 216808 kb
Host smart-313163b1-ec6a-45ad-ba95-bc7a1d29ffe8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750483539 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3750483539
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_alert.2383359014
Short name T208
Test name
Test status
Simulation time 29685413 ps
CPU time 1.22 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 219668 kb
Host smart-d494bcde-7563-4dcf-9f40-160ee809528b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383359014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2383359014
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/149.edn_alert.3132078690
Short name T197
Test name
Test status
Simulation time 83796479 ps
CPU time 1.13 seconds
Started Jul 30 06:46:04 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 218404 kb
Host smart-09e90f46-8db2-490c-ac9d-0cf655a6a480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132078690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3132078690
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/20.edn_disable.3198140484
Short name T107
Test name
Test status
Simulation time 29523888 ps
CPU time 0.79 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 216260 kb
Host smart-d5e6d1ed-6cd9-4997-bf95-120bc5bb2af5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198140484 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3198140484
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1587346718
Short name T129
Test name
Test status
Simulation time 42906405 ps
CPU time 1.26 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 216804 kb
Host smart-e55119bb-5c3f-4415-a921-4128dcc6c1e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587346718 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1587346718
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1254526006
Short name T210
Test name
Test status
Simulation time 23139034 ps
CPU time 1.04 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 229636 kb
Host smart-43a6645c-c3bb-4aa4-92ca-2d67ed40123e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254526006 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1254526006
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/10.edn_alert_test.3468578555
Short name T360
Test name
Test status
Simulation time 32351901 ps
CPU time 0.95 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 206728 kb
Host smart-9048b287-aabb-47d3-8364-1abc50589297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468578555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3468578555
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/117.edn_genbits.3742859598
Short name T341
Test name
Test status
Simulation time 79194883 ps
CPU time 2.77 seconds
Started Jul 30 06:45:58 PM PDT 24
Finished Jul 30 06:46:01 PM PDT 24
Peak memory 219516 kb
Host smart-c91e300a-bf7b-43e4-a180-164ad0703cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742859598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3742859598
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2597442390
Short name T56
Test name
Test status
Simulation time 67323245 ps
CPU time 1.07 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 217544 kb
Host smart-e88da94a-e234-4bac-9312-0590c9c021c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597442390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2597442390
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1303251010
Short name T88
Test name
Test status
Simulation time 27881912 ps
CPU time 0.86 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 215700 kb
Host smart-4f9aec2a-5409-4496-a59b-5750913af57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303251010 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1303251010
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/122.edn_genbits.1811565942
Short name T515
Test name
Test status
Simulation time 84345256 ps
CPU time 1.42 seconds
Started Jul 30 06:45:55 PM PDT 24
Finished Jul 30 06:45:56 PM PDT 24
Peak memory 219940 kb
Host smart-4551bca8-9cea-4ed0-bd79-1e1d81e88fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811565942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1811565942
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1668142112
Short name T275
Test name
Test status
Simulation time 202134209 ps
CPU time 1.04 seconds
Started Jul 30 05:58:13 PM PDT 24
Finished Jul 30 05:58:14 PM PDT 24
Peak memory 206744 kb
Host smart-d9ca0254-1000-4b19-8921-82a321b1cb62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668142112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1668142112
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.851866159
Short name T1123
Test name
Test status
Simulation time 116572110 ps
CPU time 2.78 seconds
Started Jul 30 05:58:37 PM PDT 24
Finished Jul 30 05:58:40 PM PDT 24
Peak memory 206772 kb
Host smart-b7907411-fa86-41ce-9023-bb0d0fd26c65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851866159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.851866159
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_regwen.95549532
Short name T80
Test name
Test status
Simulation time 28421630 ps
CPU time 0.97 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 207052 kb
Host smart-e12b7696-cb9f-41ea-9111-d60cdc936832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95549532 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.95549532
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/100.edn_genbits.1522581602
Short name T12
Test name
Test status
Simulation time 36620640 ps
CPU time 1.41 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:26 PM PDT 24
Peak memory 219944 kb
Host smart-ad88482a-6f45-4613-8de8-6b739818b511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522581602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1522581602
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3253589326
Short name T321
Test name
Test status
Simulation time 103303207 ps
CPU time 1.1 seconds
Started Jul 30 06:45:45 PM PDT 24
Finished Jul 30 06:45:46 PM PDT 24
Peak memory 219620 kb
Host smart-9a4f7c94-daa0-42d3-9637-0df8ea20bd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253589326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3253589326
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_genbits.879202399
Short name T383
Test name
Test status
Simulation time 77130927 ps
CPU time 1.45 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 219100 kb
Host smart-1c2a409e-9a85-45df-a1f3-90020f614fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879202399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.879202399
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.729413763
Short name T74
Test name
Test status
Simulation time 54915252 ps
CPU time 1.88 seconds
Started Jul 30 06:45:38 PM PDT 24
Finished Jul 30 06:45:40 PM PDT 24
Peak memory 215316 kb
Host smart-4bf58eef-c706-433d-84b2-13ff7dbf0b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729413763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.729413763
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1734953517
Short name T866
Test name
Test status
Simulation time 92189652 ps
CPU time 1.39 seconds
Started Jul 30 06:45:35 PM PDT 24
Finished Jul 30 06:45:37 PM PDT 24
Peak memory 218412 kb
Host smart-a2a0d7bd-fb90-4bc7-987b-ef58c37a405f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734953517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1734953517
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3069181807
Short name T330
Test name
Test status
Simulation time 128591160 ps
CPU time 2.95 seconds
Started Jul 30 06:45:56 PM PDT 24
Finished Jul 30 06:45:59 PM PDT 24
Peak memory 218512 kb
Host smart-0af7bb05-d806-4428-a087-69fd4570bbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069181807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3069181807
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2031016226
Short name T60
Test name
Test status
Simulation time 232100705 ps
CPU time 3.09 seconds
Started Jul 30 06:45:39 PM PDT 24
Finished Jul 30 06:45:43 PM PDT 24
Peak memory 218980 kb
Host smart-631b38b5-f892-4a86-a6dd-16505efa8a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031016226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2031016226
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.752433682
Short name T320
Test name
Test status
Simulation time 30889422 ps
CPU time 1.49 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:03 PM PDT 24
Peak memory 218336 kb
Host smart-3763ac0f-f5e7-4c5b-aef6-c73d1c8849fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752433682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.752433682
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1565541636
Short name T288
Test name
Test status
Simulation time 91193818 ps
CPU time 1.1 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 216944 kb
Host smart-8881a7c1-0dc0-48ee-b694-958aaf5ecce9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565541636 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1565541636
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_stress_all.2973095186
Short name T690
Test name
Test status
Simulation time 869654773 ps
CPU time 4 seconds
Started Jul 30 06:44:15 PM PDT 24
Finished Jul 30 06:44:19 PM PDT 24
Peak memory 217264 kb
Host smart-bf58e8ea-b154-4c34-94ca-4280d5bea565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973095186 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2973095186
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_genbits.379014422
Short name T319
Test name
Test status
Simulation time 47888718 ps
CPU time 1.56 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 218596 kb
Host smart-23d8be19-b88b-4036-8542-7e2d5c5f3463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379014422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.379014422
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2768123797
Short name T335
Test name
Test status
Simulation time 68139267 ps
CPU time 1.29 seconds
Started Jul 30 06:46:15 PM PDT 24
Finished Jul 30 06:46:16 PM PDT 24
Peak memory 219900 kb
Host smart-dc340c45-ea22-4b55-9dde-71d5ef5e37d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768123797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2768123797
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3053922503
Short name T328
Test name
Test status
Simulation time 42588228 ps
CPU time 1.75 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:12 PM PDT 24
Peak memory 218572 kb
Host smart-4f4eb871-b8f6-4b3b-ac65-22573c0acb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053922503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3053922503
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3994911509
Short name T229
Test name
Test status
Simulation time 72077296695 ps
CPU time 997.43 seconds
Started Jul 30 06:44:10 PM PDT 24
Finished Jul 30 07:00:48 PM PDT 24
Peak memory 221872 kb
Host smart-913e7e37-7844-4a41-83a3-c4af921f886c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994911509 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3994911509
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.edn_intr.639651887
Short name T83
Test name
Test status
Simulation time 21924406 ps
CPU time 1.04 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 215856 kb
Host smart-e26e9835-9633-41aa-81fa-2f2d3391574e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639651887 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.639651887
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/10.edn_disable.3420690406
Short name T207
Test name
Test status
Simulation time 30153964 ps
CPU time 0.87 seconds
Started Jul 30 06:44:16 PM PDT 24
Finished Jul 30 06:44:17 PM PDT 24
Peak memory 216304 kb
Host smart-a045c345-b9e0-47b2-a9fc-766ff9b2021d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420690406 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3420690406
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/129.edn_alert.3297419868
Short name T710
Test name
Test status
Simulation time 68456835 ps
CPU time 1.14 seconds
Started Jul 30 06:45:35 PM PDT 24
Finished Jul 30 06:45:36 PM PDT 24
Peak memory 220696 kb
Host smart-1ae1ab72-d83b-4113-950e-a2ee395ff573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297419868 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3297419868
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/96.edn_alert.1903264230
Short name T145
Test name
Test status
Simulation time 37852200 ps
CPU time 1.08 seconds
Started Jul 30 06:45:22 PM PDT 24
Finished Jul 30 06:45:24 PM PDT 24
Peak memory 219664 kb
Host smart-a947096c-b263-4122-aa20-9aff5d82e327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903264230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1903264230
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/10.edn_err.2321541475
Short name T8
Test name
Test status
Simulation time 25060800 ps
CPU time 1.22 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 217464 kb
Host smart-13008842-7b62-4e0b-9ef1-1219d60da2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321541475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2321541475
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.516383872
Short name T1107
Test name
Test status
Simulation time 1835278691 ps
CPU time 5.64 seconds
Started Jul 30 05:58:14 PM PDT 24
Finished Jul 30 05:58:20 PM PDT 24
Peak memory 206584 kb
Host smart-53e476fb-af3f-4271-a551-ea043b47def5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516383872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.516383872
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1614903004
Short name T265
Test name
Test status
Simulation time 14651852 ps
CPU time 0.93 seconds
Started Jul 30 05:58:07 PM PDT 24
Finished Jul 30 05:58:08 PM PDT 24
Peak memory 206572 kb
Host smart-302f9c71-9574-4b02-b153-d357c9afb1db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614903004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1614903004
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3206054880
Short name T1070
Test name
Test status
Simulation time 33763408 ps
CPU time 1.09 seconds
Started Jul 30 05:58:14 PM PDT 24
Finished Jul 30 05:58:15 PM PDT 24
Peak memory 223188 kb
Host smart-2637480c-712e-4cb2-a3d2-b5a6e5f13d29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206054880 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3206054880
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2898514439
Short name T264
Test name
Test status
Simulation time 109444987 ps
CPU time 0.78 seconds
Started Jul 30 05:58:09 PM PDT 24
Finished Jul 30 05:58:10 PM PDT 24
Peak memory 206436 kb
Host smart-600df18f-7073-4fc0-89c0-a07470fbb066
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898514439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2898514439
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1168405737
Short name T1099
Test name
Test status
Simulation time 13305489 ps
CPU time 0.86 seconds
Started Jul 30 05:58:08 PM PDT 24
Finished Jul 30 05:58:09 PM PDT 24
Peak memory 206624 kb
Host smart-fe241a14-6c90-40ae-a047-4c66775b4631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168405737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1168405737
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1852415249
Short name T1112
Test name
Test status
Simulation time 123786877 ps
CPU time 1.35 seconds
Started Jul 30 05:58:14 PM PDT 24
Finished Jul 30 05:58:16 PM PDT 24
Peak memory 206748 kb
Host smart-53a30d31-73d9-4c4d-a5f4-63fff0a7c156
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852415249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1852415249
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3267830869
Short name T1047
Test name
Test status
Simulation time 38846480 ps
CPU time 2.64 seconds
Started Jul 30 05:58:09 PM PDT 24
Finished Jul 30 05:58:12 PM PDT 24
Peak memory 215096 kb
Host smart-9af664ff-aeaa-42ed-8095-6660f470d61a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267830869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3267830869
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.222981540
Short name T1035
Test name
Test status
Simulation time 41780592 ps
CPU time 1.57 seconds
Started Jul 30 05:58:05 PM PDT 24
Finished Jul 30 05:58:07 PM PDT 24
Peak memory 206948 kb
Host smart-b4c040c8-c539-4d0d-88f0-2a4fd656eb0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222981540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.222981540
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1567435884
Short name T1090
Test name
Test status
Simulation time 58406673 ps
CPU time 1.24 seconds
Started Jul 30 05:58:11 PM PDT 24
Finished Jul 30 05:58:12 PM PDT 24
Peak memory 206632 kb
Host smart-f583d5ec-f056-4240-a9e0-9a57b2e6afec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567435884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1567435884
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2543778228
Short name T1096
Test name
Test status
Simulation time 218445804 ps
CPU time 3.25 seconds
Started Jul 30 05:58:09 PM PDT 24
Finished Jul 30 05:58:13 PM PDT 24
Peak memory 206656 kb
Host smart-104641fc-7819-4945-a8b4-278214ff799e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543778228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2543778228
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2897254176
Short name T1031
Test name
Test status
Simulation time 107462005 ps
CPU time 0.96 seconds
Started Jul 30 05:58:09 PM PDT 24
Finished Jul 30 05:58:10 PM PDT 24
Peak memory 206624 kb
Host smart-7adc01c2-5313-4e9f-8174-e92115d7dfa6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897254176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2897254176
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.490893608
Short name T1015
Test name
Test status
Simulation time 122789756 ps
CPU time 1.51 seconds
Started Jul 30 05:58:13 PM PDT 24
Finished Jul 30 05:58:14 PM PDT 24
Peak memory 215220 kb
Host smart-626e4ab6-00df-4e71-963a-0fda190a71fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490893608 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.490893608
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2770585330
Short name T1026
Test name
Test status
Simulation time 24243637 ps
CPU time 0.92 seconds
Started Jul 30 05:58:10 PM PDT 24
Finished Jul 30 05:58:11 PM PDT 24
Peak memory 206576 kb
Host smart-98fdb0cc-fb8a-49c6-83ee-c278952d5d67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770585330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2770585330
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1757090816
Short name T1036
Test name
Test status
Simulation time 13214664 ps
CPU time 0.9 seconds
Started Jul 30 05:58:11 PM PDT 24
Finished Jul 30 05:58:12 PM PDT 24
Peak memory 206628 kb
Host smart-9236ddf1-cee0-45d6-976a-3e115be205fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757090816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1757090816
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.349860781
Short name T1095
Test name
Test status
Simulation time 21044513 ps
CPU time 1.46 seconds
Started Jul 30 05:58:09 PM PDT 24
Finished Jul 30 05:58:11 PM PDT 24
Peak memory 214920 kb
Host smart-297a7196-c0d8-462a-a809-0c28e5495220
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349860781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.349860781
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2621081511
Short name T1075
Test name
Test status
Simulation time 189184140 ps
CPU time 1.69 seconds
Started Jul 30 05:58:12 PM PDT 24
Finished Jul 30 05:58:14 PM PDT 24
Peak memory 206956 kb
Host smart-40f676d7-6e5c-4031-9c38-2fbef1b2cc2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621081511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2621081511
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1173693654
Short name T1017
Test name
Test status
Simulation time 29143773 ps
CPU time 0.97 seconds
Started Jul 30 05:58:36 PM PDT 24
Finished Jul 30 05:58:37 PM PDT 24
Peak memory 206836 kb
Host smart-12fcdf58-2143-46b2-b173-489c12bce759
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173693654 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1173693654
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.816887168
Short name T1055
Test name
Test status
Simulation time 20954023 ps
CPU time 0.87 seconds
Started Jul 30 05:58:38 PM PDT 24
Finished Jul 30 05:58:39 PM PDT 24
Peak memory 206380 kb
Host smart-47f44bb8-e084-474d-866a-c95102986b7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816887168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.816887168
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2871512294
Short name T1098
Test name
Test status
Simulation time 23229328 ps
CPU time 0.89 seconds
Started Jul 30 05:58:31 PM PDT 24
Finished Jul 30 05:58:32 PM PDT 24
Peak memory 206592 kb
Host smart-5bb54ee1-c32c-4419-a814-66a44197ab3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871512294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2871512294
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.219166171
Short name T1084
Test name
Test status
Simulation time 78114460 ps
CPU time 0.97 seconds
Started Jul 30 05:58:41 PM PDT 24
Finished Jul 30 05:58:42 PM PDT 24
Peak memory 206824 kb
Host smart-a09e807f-77f3-4c78-b97e-d5d4cb2273f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219166171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.219166171
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2148525258
Short name T1027
Test name
Test status
Simulation time 85540775 ps
CPU time 1.73 seconds
Started Jul 30 05:58:43 PM PDT 24
Finished Jul 30 05:58:44 PM PDT 24
Peak memory 223200 kb
Host smart-38f569f0-f973-4ce1-b5ce-cc4ea5727e16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148525258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2148525258
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2938125975
Short name T1063
Test name
Test status
Simulation time 31216527 ps
CPU time 1.33 seconds
Started Jul 30 05:58:36 PM PDT 24
Finished Jul 30 05:58:38 PM PDT 24
Peak memory 217044 kb
Host smart-f82c654e-3428-47a8-86db-977ad525306c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938125975 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2938125975
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3631995674
Short name T1030
Test name
Test status
Simulation time 14457759 ps
CPU time 0.9 seconds
Started Jul 30 05:58:33 PM PDT 24
Finished Jul 30 05:58:34 PM PDT 24
Peak memory 206564 kb
Host smart-635a212c-2445-49ea-a473-81d0b708a759
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631995674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3631995674
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1683103531
Short name T1046
Test name
Test status
Simulation time 89088335 ps
CPU time 0.91 seconds
Started Jul 30 05:58:41 PM PDT 24
Finished Jul 30 05:58:42 PM PDT 24
Peak memory 206576 kb
Host smart-994b281b-71d0-4961-8647-5ffe8e196b51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683103531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1683103531
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3688555621
Short name T1119
Test name
Test status
Simulation time 25050635 ps
CPU time 1.26 seconds
Started Jul 30 05:58:39 PM PDT 24
Finished Jul 30 05:58:41 PM PDT 24
Peak memory 206736 kb
Host smart-9b52f472-2316-488c-be62-3da79e9b1301
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688555621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3688555621
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2910944242
Short name T1012
Test name
Test status
Simulation time 132163343 ps
CPU time 3.98 seconds
Started Jul 30 05:58:36 PM PDT 24
Finished Jul 30 05:58:40 PM PDT 24
Peak memory 215068 kb
Host smart-ff17ccde-ffda-48ff-b204-9944f4efd302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910944242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2910944242
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1694202500
Short name T222
Test name
Test status
Simulation time 61398191 ps
CPU time 1.8 seconds
Started Jul 30 05:58:43 PM PDT 24
Finished Jul 30 05:58:44 PM PDT 24
Peak memory 206716 kb
Host smart-496b0789-de2f-4483-8338-00281d854091
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694202500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1694202500
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.140542778
Short name T1106
Test name
Test status
Simulation time 176994980 ps
CPU time 1.51 seconds
Started Jul 30 05:58:38 PM PDT 24
Finished Jul 30 05:58:40 PM PDT 24
Peak memory 214988 kb
Host smart-96c72e25-9f39-43c8-a768-30a0c72dc04a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140542778 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.140542778
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.62955973
Short name T263
Test name
Test status
Simulation time 12239773 ps
CPU time 0.87 seconds
Started Jul 30 05:58:36 PM PDT 24
Finished Jul 30 05:58:37 PM PDT 24
Peak memory 206536 kb
Host smart-0cfa5ce3-4a0c-4a4b-9ecc-0b94edf24957
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62955973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.62955973
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2569786271
Short name T1059
Test name
Test status
Simulation time 15196325 ps
CPU time 0.94 seconds
Started Jul 30 05:58:40 PM PDT 24
Finished Jul 30 05:58:41 PM PDT 24
Peak memory 206772 kb
Host smart-00675255-1007-4848-b71e-9adf4573a00a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569786271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2569786271
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3364790491
Short name T1062
Test name
Test status
Simulation time 31033128 ps
CPU time 1.37 seconds
Started Jul 30 05:58:37 PM PDT 24
Finished Jul 30 05:58:39 PM PDT 24
Peak memory 206760 kb
Host smart-8cb867b0-91e3-448a-a696-d159da8dbfd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364790491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3364790491
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.231198627
Short name T991
Test name
Test status
Simulation time 217723403 ps
CPU time 2.14 seconds
Started Jul 30 05:58:36 PM PDT 24
Finished Jul 30 05:58:39 PM PDT 24
Peak memory 215000 kb
Host smart-793224de-913a-4a6a-87d1-4f04ae30bbc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231198627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.231198627
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3080656940
Short name T300
Test name
Test status
Simulation time 204447141 ps
CPU time 2.7 seconds
Started Jul 30 05:58:38 PM PDT 24
Finished Jul 30 05:58:41 PM PDT 24
Peak memory 214904 kb
Host smart-dff98507-4000-43c7-8f94-d81035a42ea0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080656940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3080656940
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1337380578
Short name T1121
Test name
Test status
Simulation time 30770555 ps
CPU time 1.24 seconds
Started Jul 30 05:58:42 PM PDT 24
Finished Jul 30 05:58:43 PM PDT 24
Peak memory 214996 kb
Host smart-dedbf8d8-6d7e-40a3-9eed-ffcb38398a0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337380578 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1337380578
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3552057538
Short name T1111
Test name
Test status
Simulation time 16641378 ps
CPU time 0.87 seconds
Started Jul 30 05:58:47 PM PDT 24
Finished Jul 30 05:58:48 PM PDT 24
Peak memory 206580 kb
Host smart-a073676a-83ec-4e71-8558-cfad4c35722c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552057538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3552057538
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3583774037
Short name T992
Test name
Test status
Simulation time 83673080 ps
CPU time 0.88 seconds
Started Jul 30 05:58:38 PM PDT 24
Finished Jul 30 05:58:39 PM PDT 24
Peak memory 206596 kb
Host smart-9306bf2b-de5b-4237-ab74-6eda54ed8df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583774037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3583774037
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.213381072
Short name T1053
Test name
Test status
Simulation time 53302680 ps
CPU time 1.36 seconds
Started Jul 30 05:58:40 PM PDT 24
Finished Jul 30 05:58:42 PM PDT 24
Peak memory 206712 kb
Host smart-f558024d-49f6-4504-84e9-1ba7dc29758e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213381072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.213381072
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1587800731
Short name T994
Test name
Test status
Simulation time 126490028 ps
CPU time 2.77 seconds
Started Jul 30 05:58:40 PM PDT 24
Finished Jul 30 05:58:43 PM PDT 24
Peak memory 215240 kb
Host smart-58557683-28a8-4432-9d51-96d6d8ca1246
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587800731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1587800731
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2768487095
Short name T299
Test name
Test status
Simulation time 597435203 ps
CPU time 2.1 seconds
Started Jul 30 05:58:42 PM PDT 24
Finished Jul 30 05:58:44 PM PDT 24
Peak memory 214880 kb
Host smart-794a35fa-e5e4-4e2e-8b3d-53b12d7e79ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768487095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2768487095
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2647469545
Short name T1045
Test name
Test status
Simulation time 42797564 ps
CPU time 0.98 seconds
Started Jul 30 05:58:46 PM PDT 24
Finished Jul 30 05:58:47 PM PDT 24
Peak memory 215032 kb
Host smart-30cff280-7467-4cdf-aa3a-e757b8d52eec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647469545 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2647469545
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.487838933
Short name T273
Test name
Test status
Simulation time 17698132 ps
CPU time 0.84 seconds
Started Jul 30 05:58:45 PM PDT 24
Finished Jul 30 05:58:46 PM PDT 24
Peak memory 206592 kb
Host smart-1f7d2ee3-ad65-45ab-9e77-3cef0a00c484
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487838933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.487838933
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2557596340
Short name T1033
Test name
Test status
Simulation time 44352066 ps
CPU time 0.85 seconds
Started Jul 30 05:58:41 PM PDT 24
Finished Jul 30 05:58:42 PM PDT 24
Peak memory 206600 kb
Host smart-d3d6132b-fff3-416b-9b30-0cc5c4dedbf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557596340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2557596340
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1247516573
Short name T259
Test name
Test status
Simulation time 37026096 ps
CPU time 1.13 seconds
Started Jul 30 05:58:39 PM PDT 24
Finished Jul 30 05:58:40 PM PDT 24
Peak memory 206752 kb
Host smart-477d33c6-f369-4bf3-8483-b6879de494f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247516573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1247516573
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.656997645
Short name T1078
Test name
Test status
Simulation time 26408873 ps
CPU time 1.74 seconds
Started Jul 30 05:58:59 PM PDT 24
Finished Jul 30 05:59:01 PM PDT 24
Peak memory 215056 kb
Host smart-cdf724da-7e88-44cc-9084-5975a12e7270
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656997645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.656997645
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.872305824
Short name T1088
Test name
Test status
Simulation time 97909609 ps
CPU time 2.82 seconds
Started Jul 30 05:58:40 PM PDT 24
Finished Jul 30 05:58:43 PM PDT 24
Peak memory 206752 kb
Host smart-259a5c57-abf0-49fc-ace2-ecf41982a14e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872305824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.872305824
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.508536578
Short name T1018
Test name
Test status
Simulation time 26388431 ps
CPU time 0.98 seconds
Started Jul 30 05:58:41 PM PDT 24
Finished Jul 30 05:58:42 PM PDT 24
Peak memory 206772 kb
Host smart-fccde0e3-d4a3-4ef3-a74c-6f4492303f6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508536578 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.508536578
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2667563664
Short name T1085
Test name
Test status
Simulation time 29880639 ps
CPU time 0.88 seconds
Started Jul 30 05:58:40 PM PDT 24
Finished Jul 30 05:58:41 PM PDT 24
Peak memory 206376 kb
Host smart-db20ef12-a12c-4f7d-b75f-32b21cc9ccfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667563664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2667563664
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.4065428893
Short name T1064
Test name
Test status
Simulation time 43991731 ps
CPU time 0.83 seconds
Started Jul 30 05:58:38 PM PDT 24
Finished Jul 30 05:58:39 PM PDT 24
Peak memory 206444 kb
Host smart-dd5258f1-bdb8-4fb5-9646-352d4cc03075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065428893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.4065428893
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.249214801
Short name T1050
Test name
Test status
Simulation time 126391074 ps
CPU time 1.48 seconds
Started Jul 30 05:58:41 PM PDT 24
Finished Jul 30 05:58:42 PM PDT 24
Peak memory 206772 kb
Host smart-fb8cfe91-9a66-4f22-bbbf-4175cc5242b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249214801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.249214801
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1550285468
Short name T1022
Test name
Test status
Simulation time 73213260 ps
CPU time 1.91 seconds
Started Jul 30 05:58:47 PM PDT 24
Finished Jul 30 05:58:49 PM PDT 24
Peak memory 223148 kb
Host smart-fb365049-9f4d-4ab6-b657-fd008ab970db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550285468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1550285468
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1267040456
Short name T1042
Test name
Test status
Simulation time 265027750 ps
CPU time 1.56 seconds
Started Jul 30 05:58:42 PM PDT 24
Finished Jul 30 05:58:44 PM PDT 24
Peak memory 206896 kb
Host smart-c18deac3-f4ab-465c-ad00-5cb3967e0932
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267040456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1267040456
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4048530005
Short name T1089
Test name
Test status
Simulation time 23521786 ps
CPU time 1.37 seconds
Started Jul 30 05:58:49 PM PDT 24
Finished Jul 30 05:58:50 PM PDT 24
Peak memory 214964 kb
Host smart-cc4402a4-0c88-4f9a-8941-f277943fb1e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048530005 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.4048530005
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1630160564
Short name T995
Test name
Test status
Simulation time 26776421 ps
CPU time 0.92 seconds
Started Jul 30 05:58:47 PM PDT 24
Finished Jul 30 05:58:48 PM PDT 24
Peak memory 206408 kb
Host smart-07e1a638-50da-428e-ab31-6b2633e33a72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630160564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1630160564
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3854758171
Short name T1065
Test name
Test status
Simulation time 28854332 ps
CPU time 0.91 seconds
Started Jul 30 05:58:42 PM PDT 24
Finished Jul 30 05:58:43 PM PDT 24
Peak memory 206636 kb
Host smart-60c4ed37-d43c-43be-8144-c7f221bc06c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854758171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3854758171
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.534597866
Short name T1079
Test name
Test status
Simulation time 54291592 ps
CPU time 1.16 seconds
Started Jul 30 05:58:45 PM PDT 24
Finished Jul 30 05:58:46 PM PDT 24
Peak memory 206652 kb
Host smart-89617031-1e35-4243-90e9-1a69cdb3bde0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534597866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_ou
tstanding.534597866
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2443346133
Short name T1004
Test name
Test status
Simulation time 150247633 ps
CPU time 4.68 seconds
Started Jul 30 05:58:45 PM PDT 24
Finished Jul 30 05:58:50 PM PDT 24
Peak memory 215032 kb
Host smart-78cccb93-e2c0-4044-86d5-24a5824f7f41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443346133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2443346133
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3256245536
Short name T1080
Test name
Test status
Simulation time 272000621 ps
CPU time 1.65 seconds
Started Jul 30 05:58:57 PM PDT 24
Finished Jul 30 05:58:59 PM PDT 24
Peak memory 206804 kb
Host smart-fd1373a2-dc68-451e-9f6a-4d0f1c3de5bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256245536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3256245536
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2465404074
Short name T1016
Test name
Test status
Simulation time 28251621 ps
CPU time 1.39 seconds
Started Jul 30 05:58:47 PM PDT 24
Finished Jul 30 05:58:48 PM PDT 24
Peak memory 215012 kb
Host smart-f679d5c8-45a4-4341-b214-b09b23b1e56e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465404074 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2465404074
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.4064551630
Short name T257
Test name
Test status
Simulation time 86776340 ps
CPU time 0.85 seconds
Started Jul 30 05:58:44 PM PDT 24
Finished Jul 30 05:58:45 PM PDT 24
Peak memory 206572 kb
Host smart-c9cdf7f3-53cb-42fd-8313-eaddcb85248a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064551630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.4064551630
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1458013308
Short name T1100
Test name
Test status
Simulation time 73515188 ps
CPU time 0.85 seconds
Started Jul 30 05:58:53 PM PDT 24
Finished Jul 30 05:58:54 PM PDT 24
Peak memory 206420 kb
Host smart-67f547ed-6fd0-41d0-8ff2-a501e8a00a2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458013308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1458013308
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3113633976
Short name T274
Test name
Test status
Simulation time 65103388 ps
CPU time 1.03 seconds
Started Jul 30 05:58:57 PM PDT 24
Finished Jul 30 05:58:58 PM PDT 24
Peak memory 206704 kb
Host smart-fbbde5df-46b1-4fea-97e8-c4580d5d18e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113633976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3113633976
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2059173819
Short name T1124
Test name
Test status
Simulation time 101531234 ps
CPU time 3.83 seconds
Started Jul 30 05:59:05 PM PDT 24
Finished Jul 30 05:59:09 PM PDT 24
Peak memory 215024 kb
Host smart-6660bbe2-f0ce-4510-9783-724b78369487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059173819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2059173819
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2802080963
Short name T1040
Test name
Test status
Simulation time 96589418 ps
CPU time 1.64 seconds
Started Jul 30 05:59:05 PM PDT 24
Finished Jul 30 05:59:06 PM PDT 24
Peak memory 206732 kb
Host smart-47f9554b-bfe4-414b-b7c0-9281d012de3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802080963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2802080963
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3727357265
Short name T1057
Test name
Test status
Simulation time 18465233 ps
CPU time 1.1 seconds
Started Jul 30 05:59:04 PM PDT 24
Finished Jul 30 05:59:05 PM PDT 24
Peak memory 206804 kb
Host smart-1618a75d-096a-4ffa-bc4f-00a795a239e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727357265 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3727357265
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3861081658
Short name T271
Test name
Test status
Simulation time 62139303 ps
CPU time 0.79 seconds
Started Jul 30 05:59:07 PM PDT 24
Finished Jul 30 05:59:07 PM PDT 24
Peak memory 206404 kb
Host smart-1648691a-5fcb-4b9e-b2f3-620b7c8b12a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861081658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3861081658
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.4193317304
Short name T1066
Test name
Test status
Simulation time 11567574 ps
CPU time 0.84 seconds
Started Jul 30 05:58:52 PM PDT 24
Finished Jul 30 05:58:53 PM PDT 24
Peak memory 206624 kb
Host smart-c52495a9-2825-47e1-b3cc-8ebd11d4c4ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193317304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.4193317304
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1885787501
Short name T1048
Test name
Test status
Simulation time 15114515 ps
CPU time 1.03 seconds
Started Jul 30 05:58:50 PM PDT 24
Finished Jul 30 05:58:51 PM PDT 24
Peak memory 206828 kb
Host smart-b8a7c39c-5e9e-4510-9eb7-0165fcc7845e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885787501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1885787501
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.367336940
Short name T1044
Test name
Test status
Simulation time 187079542 ps
CPU time 3.41 seconds
Started Jul 30 05:59:02 PM PDT 24
Finished Jul 30 05:59:06 PM PDT 24
Peak memory 215056 kb
Host smart-6c5756b2-1f5e-4ec0-a324-9ef50267d6a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367336940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.367336940
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3654865620
Short name T1009
Test name
Test status
Simulation time 18486518 ps
CPU time 1.15 seconds
Started Jul 30 05:58:57 PM PDT 24
Finished Jul 30 05:58:58 PM PDT 24
Peak memory 215088 kb
Host smart-0c2fd6cd-f6fe-4629-a311-023f4a01d77f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654865620 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3654865620
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.4007245650
Short name T1122
Test name
Test status
Simulation time 76502585 ps
CPU time 0.88 seconds
Started Jul 30 05:58:48 PM PDT 24
Finished Jul 30 05:58:49 PM PDT 24
Peak memory 206368 kb
Host smart-8ff52826-4a7f-4ec7-9517-be5eae5d4814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007245650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.4007245650
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3230208733
Short name T1028
Test name
Test status
Simulation time 14177082 ps
CPU time 0.92 seconds
Started Jul 30 05:58:49 PM PDT 24
Finished Jul 30 05:58:50 PM PDT 24
Peak memory 206584 kb
Host smart-f8a70416-11c8-4221-ad40-3dd8e60c61e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230208733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3230208733
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.882618600
Short name T276
Test name
Test status
Simulation time 56750962 ps
CPU time 1.14 seconds
Started Jul 30 05:59:04 PM PDT 24
Finished Jul 30 05:59:05 PM PDT 24
Peak memory 206692 kb
Host smart-1a9ecc55-b34a-466e-afeb-4117e8915cdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882618600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.882618600
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3199233204
Short name T1056
Test name
Test status
Simulation time 22298971 ps
CPU time 1.53 seconds
Started Jul 30 05:59:04 PM PDT 24
Finished Jul 30 05:59:05 PM PDT 24
Peak memory 215008 kb
Host smart-4f7ae7d4-38a6-4119-ac45-9ad6b953d59a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199233204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3199233204
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.630981601
Short name T224
Test name
Test status
Simulation time 204171513 ps
CPU time 2.47 seconds
Started Jul 30 05:58:54 PM PDT 24
Finished Jul 30 05:58:57 PM PDT 24
Peak memory 214844 kb
Host smart-19bab7cf-b868-4251-81d3-f80e6dfe4c04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630981601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.630981601
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2272546291
Short name T1010
Test name
Test status
Simulation time 56231092 ps
CPU time 1.06 seconds
Started Jul 30 05:58:14 PM PDT 24
Finished Jul 30 05:58:15 PM PDT 24
Peak memory 206580 kb
Host smart-e3ebaa17-ced6-4900-95c0-554ed2e8bd6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272546291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2272546291
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2159439574
Short name T269
Test name
Test status
Simulation time 434115164 ps
CPU time 3.25 seconds
Started Jul 30 05:58:11 PM PDT 24
Finished Jul 30 05:58:14 PM PDT 24
Peak memory 206560 kb
Host smart-2b415982-739f-4220-b36c-a47ef07f0409
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159439574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2159439574
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1786054083
Short name T267
Test name
Test status
Simulation time 54200746 ps
CPU time 0.94 seconds
Started Jul 30 05:58:12 PM PDT 24
Finished Jul 30 05:58:13 PM PDT 24
Peak memory 206556 kb
Host smart-00df6b7c-b96f-4b0f-bbaa-052b13b964ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786054083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1786054083
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1974004131
Short name T1097
Test name
Test status
Simulation time 35414967 ps
CPU time 1.53 seconds
Started Jul 30 05:58:19 PM PDT 24
Finished Jul 30 05:58:20 PM PDT 24
Peak memory 214952 kb
Host smart-eae9e65d-d3e5-47f2-af37-2c04d222193b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974004131 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1974004131
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.516716007
Short name T270
Test name
Test status
Simulation time 14184043 ps
CPU time 0.93 seconds
Started Jul 30 05:58:15 PM PDT 24
Finished Jul 30 05:58:16 PM PDT 24
Peak memory 206532 kb
Host smart-b8c4014b-9a0f-423c-a5c3-8c6d44572588
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516716007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.516716007
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2773782387
Short name T1021
Test name
Test status
Simulation time 44107365 ps
CPU time 0.86 seconds
Started Jul 30 05:58:14 PM PDT 24
Finished Jul 30 05:58:15 PM PDT 24
Peak memory 206588 kb
Host smart-9459de91-6a43-42d3-9eda-f2dbdb51b2d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773782387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2773782387
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2362592041
Short name T278
Test name
Test status
Simulation time 18245687 ps
CPU time 0.96 seconds
Started Jul 30 05:58:14 PM PDT 24
Finished Jul 30 05:58:15 PM PDT 24
Peak memory 206756 kb
Host smart-454e917d-de21-4484-a50d-eabc6f9caefc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362592041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2362592041
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1369595620
Short name T1091
Test name
Test status
Simulation time 62434660 ps
CPU time 2.44 seconds
Started Jul 30 05:58:13 PM PDT 24
Finished Jul 30 05:58:15 PM PDT 24
Peak memory 214992 kb
Host smart-d89a7959-9da6-4f7c-b1af-88287f24deb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369595620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1369595620
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.322973901
Short name T1076
Test name
Test status
Simulation time 230106521 ps
CPU time 2.46 seconds
Started Jul 30 05:58:14 PM PDT 24
Finished Jul 30 05:58:16 PM PDT 24
Peak memory 206728 kb
Host smart-141aa471-77cd-4d2b-82f5-cdf86adf9322
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322973901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.322973901
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2925359028
Short name T1060
Test name
Test status
Simulation time 29734180 ps
CPU time 0.93 seconds
Started Jul 30 05:58:51 PM PDT 24
Finished Jul 30 05:58:52 PM PDT 24
Peak memory 206572 kb
Host smart-95c9b9d7-4108-4195-aba1-afb80737c8e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925359028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2925359028
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.342601214
Short name T1003
Test name
Test status
Simulation time 16082457 ps
CPU time 0.93 seconds
Started Jul 30 05:59:04 PM PDT 24
Finished Jul 30 05:59:05 PM PDT 24
Peak memory 206576 kb
Host smart-f0e51c37-94a8-43af-ab67-fe5feda2c7b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342601214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.342601214
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2027038650
Short name T993
Test name
Test status
Simulation time 14591636 ps
CPU time 0.94 seconds
Started Jul 30 05:58:58 PM PDT 24
Finished Jul 30 05:58:59 PM PDT 24
Peak memory 206624 kb
Host smart-6c69e2fe-ed2f-4bdf-84b5-a727266463b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027038650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2027038650
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3379130890
Short name T1013
Test name
Test status
Simulation time 15919151 ps
CPU time 0.79 seconds
Started Jul 30 05:59:02 PM PDT 24
Finished Jul 30 05:59:03 PM PDT 24
Peak memory 206400 kb
Host smart-f1478715-bdfc-4e5c-bf4a-66921422f702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379130890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3379130890
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3198837594
Short name T1110
Test name
Test status
Simulation time 55991557 ps
CPU time 0.83 seconds
Started Jul 30 05:58:53 PM PDT 24
Finished Jul 30 05:58:54 PM PDT 24
Peak memory 206564 kb
Host smart-0dbdf38e-0595-4311-bf4b-af3fec7aeb57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198837594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3198837594
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1345062333
Short name T1116
Test name
Test status
Simulation time 11867037 ps
CPU time 0.82 seconds
Started Jul 30 05:59:12 PM PDT 24
Finished Jul 30 05:59:13 PM PDT 24
Peak memory 206552 kb
Host smart-9c629e97-4355-48c4-ade3-95260cccddd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345062333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1345062333
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4156385639
Short name T1032
Test name
Test status
Simulation time 77996649 ps
CPU time 0.88 seconds
Started Jul 30 05:59:06 PM PDT 24
Finished Jul 30 05:59:06 PM PDT 24
Peak memory 206396 kb
Host smart-2fd716bc-8dda-405e-830b-7cd969dc010c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156385639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4156385639
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1555216474
Short name T1037
Test name
Test status
Simulation time 50635317 ps
CPU time 0.88 seconds
Started Jul 30 05:58:53 PM PDT 24
Finished Jul 30 05:58:54 PM PDT 24
Peak memory 206608 kb
Host smart-5669c4dd-a4d5-4d5d-8afd-f0652208b27c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555216474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1555216474
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3487655102
Short name T1074
Test name
Test status
Simulation time 28509215 ps
CPU time 0.84 seconds
Started Jul 30 05:58:53 PM PDT 24
Finished Jul 30 05:58:54 PM PDT 24
Peak memory 206588 kb
Host smart-faf99417-3f70-4f82-b66f-4cb927843f34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487655102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3487655102
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1458675533
Short name T996
Test name
Test status
Simulation time 20998865 ps
CPU time 0.82 seconds
Started Jul 30 05:59:06 PM PDT 24
Finished Jul 30 05:59:07 PM PDT 24
Peak memory 206340 kb
Host smart-d71cedbf-a8ff-4cef-8aa0-297adbefd1b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458675533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1458675533
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.4189482754
Short name T262
Test name
Test status
Simulation time 61038908 ps
CPU time 1.23 seconds
Started Jul 30 05:58:17 PM PDT 24
Finished Jul 30 05:58:19 PM PDT 24
Peak memory 206644 kb
Host smart-6b90123e-6d7b-4a14-bdf7-236657f95212
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189482754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.4189482754
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.757327222
Short name T1087
Test name
Test status
Simulation time 708286145 ps
CPU time 4.93 seconds
Started Jul 30 05:58:18 PM PDT 24
Finished Jul 30 05:58:23 PM PDT 24
Peak memory 206444 kb
Host smart-500393b2-12fb-4541-a362-743c485e6f2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757327222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.757327222
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2832211850
Short name T258
Test name
Test status
Simulation time 18239023 ps
CPU time 0.97 seconds
Started Jul 30 05:58:18 PM PDT 24
Finished Jul 30 05:58:19 PM PDT 24
Peak memory 206576 kb
Host smart-7f62d94b-0179-4d9d-a2ad-ff40ff1c0ce5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832211850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2832211850
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.812423743
Short name T1105
Test name
Test status
Simulation time 44677993 ps
CPU time 1.05 seconds
Started Jul 30 05:58:29 PM PDT 24
Finished Jul 30 05:58:30 PM PDT 24
Peak memory 206788 kb
Host smart-95441f2b-cc2c-4475-be59-98356bc528f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812423743 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.812423743
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1984206982
Short name T1006
Test name
Test status
Simulation time 27769494 ps
CPU time 0.9 seconds
Started Jul 30 05:58:16 PM PDT 24
Finished Jul 30 05:58:17 PM PDT 24
Peak memory 206524 kb
Host smart-8e255eb6-f6df-450e-bfc4-8533252b7d54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984206982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1984206982
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.4134183468
Short name T1000
Test name
Test status
Simulation time 56338477 ps
CPU time 0.87 seconds
Started Jul 30 05:58:26 PM PDT 24
Finished Jul 30 05:58:27 PM PDT 24
Peak memory 206660 kb
Host smart-aff12716-305c-4ecd-a87b-675b4d50c545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134183468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.4134183468
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2530665949
Short name T1024
Test name
Test status
Simulation time 154769638 ps
CPU time 1.54 seconds
Started Jul 30 05:58:22 PM PDT 24
Finished Jul 30 05:58:24 PM PDT 24
Peak memory 206724 kb
Host smart-cec415b1-40c4-4731-a370-e1564104b092
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530665949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2530665949
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3732949996
Short name T1115
Test name
Test status
Simulation time 349613765 ps
CPU time 3.14 seconds
Started Jul 30 05:58:16 PM PDT 24
Finished Jul 30 05:58:19 PM PDT 24
Peak memory 214996 kb
Host smart-ee1c6592-9f90-45b5-9322-67804f21fca6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732949996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3732949996
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3583628423
Short name T223
Test name
Test status
Simulation time 244189652 ps
CPU time 1.69 seconds
Started Jul 30 05:58:16 PM PDT 24
Finished Jul 30 05:58:17 PM PDT 24
Peak memory 206896 kb
Host smart-6bfbc34c-962a-40a0-a76b-3a6b88bfa73e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583628423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3583628423
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.210059712
Short name T1038
Test name
Test status
Simulation time 11326701 ps
CPU time 0.84 seconds
Started Jul 30 05:58:52 PM PDT 24
Finished Jul 30 05:58:53 PM PDT 24
Peak memory 206584 kb
Host smart-88432f72-efc5-4302-bb60-8bf05736009a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210059712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.210059712
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2180810048
Short name T1001
Test name
Test status
Simulation time 14037124 ps
CPU time 0.92 seconds
Started Jul 30 05:58:51 PM PDT 24
Finished Jul 30 05:58:52 PM PDT 24
Peak memory 206612 kb
Host smart-d6e9bc31-f768-4efa-8e53-12eebf345d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180810048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2180810048
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2444782956
Short name T1005
Test name
Test status
Simulation time 17228901 ps
CPU time 0.95 seconds
Started Jul 30 05:59:03 PM PDT 24
Finished Jul 30 05:59:04 PM PDT 24
Peak memory 206600 kb
Host smart-287e624b-4e8f-4aa9-813f-c067e13935cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444782956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2444782956
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2234273958
Short name T1043
Test name
Test status
Simulation time 32370062 ps
CPU time 0.89 seconds
Started Jul 30 05:58:54 PM PDT 24
Finished Jul 30 05:58:55 PM PDT 24
Peak memory 206852 kb
Host smart-cd298199-46ed-493e-8e44-d3a27fca7c64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234273958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2234273958
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1758332978
Short name T1109
Test name
Test status
Simulation time 11617818 ps
CPU time 0.85 seconds
Started Jul 30 05:58:54 PM PDT 24
Finished Jul 30 05:58:55 PM PDT 24
Peak memory 206508 kb
Host smart-09005bb3-6811-4498-9672-3f877c1e6034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758332978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1758332978
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1112169876
Short name T1054
Test name
Test status
Simulation time 17256770 ps
CPU time 0.93 seconds
Started Jul 30 05:58:54 PM PDT 24
Finished Jul 30 05:58:55 PM PDT 24
Peak memory 206512 kb
Host smart-64d4eb98-76e4-4d07-bd18-29597b91419d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112169876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1112169876
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1428617866
Short name T1008
Test name
Test status
Simulation time 37885173 ps
CPU time 0.86 seconds
Started Jul 30 05:59:01 PM PDT 24
Finished Jul 30 05:59:02 PM PDT 24
Peak memory 206416 kb
Host smart-8858101a-9a35-407a-a3c4-66eec6a3b69f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428617866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1428617866
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3321293132
Short name T998
Test name
Test status
Simulation time 44239032 ps
CPU time 0.83 seconds
Started Jul 30 05:59:02 PM PDT 24
Finished Jul 30 05:59:03 PM PDT 24
Peak memory 206428 kb
Host smart-5a51095a-2287-4df9-89e6-6467f2556cf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321293132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3321293132
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2278013852
Short name T1118
Test name
Test status
Simulation time 56651962 ps
CPU time 0.87 seconds
Started Jul 30 05:58:55 PM PDT 24
Finished Jul 30 05:58:56 PM PDT 24
Peak memory 206456 kb
Host smart-460da12a-618c-4d90-a60e-764968b740e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278013852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2278013852
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.241929554
Short name T1071
Test name
Test status
Simulation time 46689919 ps
CPU time 0.88 seconds
Started Jul 30 05:59:01 PM PDT 24
Finished Jul 30 05:59:02 PM PDT 24
Peak memory 206584 kb
Host smart-6785e17a-41d3-4bbd-a9b5-a3137216e352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241929554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.241929554
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.714078833
Short name T268
Test name
Test status
Simulation time 70818688 ps
CPU time 1.2 seconds
Started Jul 30 05:58:25 PM PDT 24
Finished Jul 30 05:58:26 PM PDT 24
Peak memory 206572 kb
Host smart-41e02a6b-d52d-4835-b6d5-1c8ba155f8eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714078833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.714078833
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1031215944
Short name T1101
Test name
Test status
Simulation time 271335123 ps
CPU time 3.93 seconds
Started Jul 30 05:58:19 PM PDT 24
Finished Jul 30 05:58:23 PM PDT 24
Peak memory 206648 kb
Host smart-fe88de71-6df5-4cda-92c7-ecdc31f10949
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031215944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1031215944
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2861443238
Short name T1082
Test name
Test status
Simulation time 36777917 ps
CPU time 0.88 seconds
Started Jul 30 05:58:20 PM PDT 24
Finished Jul 30 05:58:21 PM PDT 24
Peak memory 206592 kb
Host smart-386cbac0-4db5-4d78-99d8-3202854556a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861443238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2861443238
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4160770065
Short name T1086
Test name
Test status
Simulation time 88945748 ps
CPU time 1.22 seconds
Started Jul 30 05:58:28 PM PDT 24
Finished Jul 30 05:58:30 PM PDT 24
Peak memory 215104 kb
Host smart-5855ffbb-f67e-4e9a-915a-bde80252e6ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160770065 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.4160770065
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.70608500
Short name T1061
Test name
Test status
Simulation time 147968743 ps
CPU time 0.81 seconds
Started Jul 30 05:58:22 PM PDT 24
Finished Jul 30 05:58:23 PM PDT 24
Peak memory 206424 kb
Host smart-3a1fc879-76f4-4964-bcfa-b78639247e55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70608500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.70608500
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.22186380
Short name T1034
Test name
Test status
Simulation time 13201428 ps
CPU time 0.91 seconds
Started Jul 30 05:58:26 PM PDT 24
Finished Jul 30 05:58:27 PM PDT 24
Peak memory 206648 kb
Host smart-1d0aae0a-862b-4c81-9549-abd3f89a7521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22186380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.22186380
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2314309631
Short name T1058
Test name
Test status
Simulation time 17547221 ps
CPU time 1.13 seconds
Started Jul 30 05:58:22 PM PDT 24
Finished Jul 30 05:58:23 PM PDT 24
Peak memory 206796 kb
Host smart-f159ebe8-0227-48f3-b6ec-c06c084f9fab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314309631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2314309631
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1552680496
Short name T1072
Test name
Test status
Simulation time 165240410 ps
CPU time 3.2 seconds
Started Jul 30 05:58:20 PM PDT 24
Finished Jul 30 05:58:23 PM PDT 24
Peak memory 214964 kb
Host smart-14ad5d38-87d8-481b-bef7-096e5a23ce08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552680496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1552680496
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.501743766
Short name T1049
Test name
Test status
Simulation time 616769026 ps
CPU time 2.2 seconds
Started Jul 30 05:58:24 PM PDT 24
Finished Jul 30 05:58:27 PM PDT 24
Peak memory 206912 kb
Host smart-dd0e82fe-2195-4acf-9e2a-add6f4714f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501743766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.501743766
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1753538108
Short name T1041
Test name
Test status
Simulation time 12086583 ps
CPU time 0.8 seconds
Started Jul 30 05:59:09 PM PDT 24
Finished Jul 30 05:59:10 PM PDT 24
Peak memory 206416 kb
Host smart-b8b0a0fb-6c6b-486a-965d-594d07f8cf91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753538108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1753538108
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3941846578
Short name T1083
Test name
Test status
Simulation time 40380609 ps
CPU time 0.81 seconds
Started Jul 30 05:58:56 PM PDT 24
Finished Jul 30 05:58:57 PM PDT 24
Peak memory 206392 kb
Host smart-9023597f-5f7f-4795-a150-1302eaeb6f18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941846578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3941846578
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2188387636
Short name T1011
Test name
Test status
Simulation time 11707528 ps
CPU time 0.81 seconds
Started Jul 30 05:58:56 PM PDT 24
Finished Jul 30 05:58:57 PM PDT 24
Peak memory 206396 kb
Host smart-f0c26aab-b134-4973-993a-924da67098d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188387636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2188387636
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2587754108
Short name T1019
Test name
Test status
Simulation time 19876164 ps
CPU time 0.82 seconds
Started Jul 30 05:59:00 PM PDT 24
Finished Jul 30 05:59:01 PM PDT 24
Peak memory 206572 kb
Host smart-1a3bf280-0c98-4fa7-9818-7dee58752354
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587754108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2587754108
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.585820362
Short name T1103
Test name
Test status
Simulation time 12998935 ps
CPU time 0.89 seconds
Started Jul 30 05:59:03 PM PDT 24
Finished Jul 30 05:59:04 PM PDT 24
Peak memory 206544 kb
Host smart-6d86dff8-0231-44b0-8690-80acfab93a0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585820362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.585820362
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.103471232
Short name T1108
Test name
Test status
Simulation time 104872885 ps
CPU time 1.04 seconds
Started Jul 30 05:59:02 PM PDT 24
Finished Jul 30 05:59:04 PM PDT 24
Peak memory 206444 kb
Host smart-39a8e4d8-c2b1-4a71-b1b1-97038c13cccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103471232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.103471232
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1755983925
Short name T1068
Test name
Test status
Simulation time 13847053 ps
CPU time 0.86 seconds
Started Jul 30 05:59:13 PM PDT 24
Finished Jul 30 05:59:14 PM PDT 24
Peak memory 206652 kb
Host smart-62c776d7-0748-4449-a1a9-c2589fc1ca27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755983925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1755983925
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2984313921
Short name T1102
Test name
Test status
Simulation time 24313672 ps
CPU time 0.86 seconds
Started Jul 30 05:59:03 PM PDT 24
Finished Jul 30 05:59:04 PM PDT 24
Peak memory 206492 kb
Host smart-d3082469-00c7-423e-b7ce-28b9de0c985f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984313921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2984313921
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1815847466
Short name T1113
Test name
Test status
Simulation time 17025117 ps
CPU time 0.91 seconds
Started Jul 30 05:59:13 PM PDT 24
Finished Jul 30 05:59:14 PM PDT 24
Peak memory 206580 kb
Host smart-1a844656-c980-48e8-bcde-852bae559c24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815847466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1815847466
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2669830740
Short name T1052
Test name
Test status
Simulation time 15584401 ps
CPU time 0.92 seconds
Started Jul 30 05:59:01 PM PDT 24
Finished Jul 30 05:59:02 PM PDT 24
Peak memory 206500 kb
Host smart-6ab8e19d-53fc-43cf-9c7b-ad14e117a9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669830740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2669830740
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3762064704
Short name T999
Test name
Test status
Simulation time 24989431 ps
CPU time 1.58 seconds
Started Jul 30 05:58:26 PM PDT 24
Finished Jul 30 05:58:27 PM PDT 24
Peak memory 215032 kb
Host smart-eab33b71-257c-4132-a6dd-c659f2503f57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762064704 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3762064704
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2679293801
Short name T997
Test name
Test status
Simulation time 15078244 ps
CPU time 0.96 seconds
Started Jul 30 05:58:26 PM PDT 24
Finished Jul 30 05:58:27 PM PDT 24
Peak memory 206556 kb
Host smart-7d283f02-ea27-4ba6-b601-419d7a42e0cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679293801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2679293801
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.863906712
Short name T1069
Test name
Test status
Simulation time 49660759 ps
CPU time 0.82 seconds
Started Jul 30 05:58:27 PM PDT 24
Finished Jul 30 05:58:28 PM PDT 24
Peak memory 206404 kb
Host smart-3ef7c4c4-0e10-4d9f-9e1b-738a87855cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863906712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.863906712
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1213971870
Short name T261
Test name
Test status
Simulation time 67794281 ps
CPU time 1.06 seconds
Started Jul 30 05:58:27 PM PDT 24
Finished Jul 30 05:58:28 PM PDT 24
Peak memory 206744 kb
Host smart-bbdc6beb-a667-4946-b9ba-09fa6ab9487f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213971870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1213971870
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2683703008
Short name T1020
Test name
Test status
Simulation time 2004627590 ps
CPU time 4.05 seconds
Started Jul 30 05:58:24 PM PDT 24
Finished Jul 30 05:58:28 PM PDT 24
Peak memory 214924 kb
Host smart-aff4fddd-11d5-49a0-ade2-2a7e90c6f644
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683703008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2683703008
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1993638279
Short name T1125
Test name
Test status
Simulation time 160302977 ps
CPU time 1.58 seconds
Started Jul 30 05:58:26 PM PDT 24
Finished Jul 30 05:58:28 PM PDT 24
Peak memory 206740 kb
Host smart-c985999a-09e3-40a1-9625-de5490610eaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993638279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1993638279
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.309427743
Short name T1092
Test name
Test status
Simulation time 37447654 ps
CPU time 1.25 seconds
Started Jul 30 05:58:25 PM PDT 24
Finished Jul 30 05:58:27 PM PDT 24
Peak memory 215024 kb
Host smart-c5cf397b-c3e3-4e74-897a-c13ae644a40d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309427743 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.309427743
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3843334793
Short name T1007
Test name
Test status
Simulation time 16319298 ps
CPU time 1 seconds
Started Jul 30 05:58:26 PM PDT 24
Finished Jul 30 05:58:27 PM PDT 24
Peak memory 206620 kb
Host smart-193ab598-5314-4d1a-819e-80cb878ffd72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843334793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3843334793
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3299954331
Short name T1025
Test name
Test status
Simulation time 13739577 ps
CPU time 0.91 seconds
Started Jul 30 05:58:24 PM PDT 24
Finished Jul 30 05:58:25 PM PDT 24
Peak memory 206596 kb
Host smart-87df0f8e-0902-4feb-9992-40887988386b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299954331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3299954331
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.66011833
Short name T1114
Test name
Test status
Simulation time 57870303 ps
CPU time 1.32 seconds
Started Jul 30 05:58:31 PM PDT 24
Finished Jul 30 05:58:32 PM PDT 24
Peak memory 206776 kb
Host smart-447b6b9b-b156-40d8-9fbc-b111af45847b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66011833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outs
tanding.66011833
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.975962967
Short name T1104
Test name
Test status
Simulation time 1948675761 ps
CPU time 4.84 seconds
Started Jul 30 05:58:23 PM PDT 24
Finished Jul 30 05:58:28 PM PDT 24
Peak memory 215020 kb
Host smart-9d1459da-9d08-4172-a815-eea11161d39b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975962967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.975962967
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.344057165
Short name T302
Test name
Test status
Simulation time 306849210 ps
CPU time 1.48 seconds
Started Jul 30 05:58:29 PM PDT 24
Finished Jul 30 05:58:31 PM PDT 24
Peak memory 206792 kb
Host smart-9e48dec6-4343-46fe-8c1b-4057743d1e1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344057165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.344057165
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2929759261
Short name T1002
Test name
Test status
Simulation time 172111892 ps
CPU time 1.66 seconds
Started Jul 30 05:58:29 PM PDT 24
Finished Jul 30 05:58:30 PM PDT 24
Peak memory 215076 kb
Host smart-8e19224c-7707-425f-98ef-78ec31c49fd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929759261 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2929759261
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.889585934
Short name T266
Test name
Test status
Simulation time 45710231 ps
CPU time 0.89 seconds
Started Jul 30 05:58:30 PM PDT 24
Finished Jul 30 05:58:31 PM PDT 24
Peak memory 206608 kb
Host smart-44b3e426-7030-4309-b473-d94179b07ab0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889585934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.889585934
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2516303691
Short name T1093
Test name
Test status
Simulation time 23237010 ps
CPU time 0.85 seconds
Started Jul 30 05:58:29 PM PDT 24
Finished Jul 30 05:58:30 PM PDT 24
Peak memory 206560 kb
Host smart-d62de572-8e66-41bd-9c22-2c230d6eab0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516303691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2516303691
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1330773782
Short name T272
Test name
Test status
Simulation time 30466997 ps
CPU time 1.35 seconds
Started Jul 30 05:58:30 PM PDT 24
Finished Jul 30 05:58:31 PM PDT 24
Peak memory 206744 kb
Host smart-3921c3e7-cdf3-4660-926b-3c02cf66b57d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330773782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1330773782
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1111006203
Short name T1029
Test name
Test status
Simulation time 82862691 ps
CPU time 3.08 seconds
Started Jul 30 05:58:25 PM PDT 24
Finished Jul 30 05:58:28 PM PDT 24
Peak memory 214960 kb
Host smart-d897927d-e269-49e4-a987-e4c86b9b72a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111006203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1111006203
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3260079104
Short name T1094
Test name
Test status
Simulation time 378218415 ps
CPU time 1.49 seconds
Started Jul 30 05:58:37 PM PDT 24
Finished Jul 30 05:58:39 PM PDT 24
Peak memory 206668 kb
Host smart-a8a49762-de5c-413f-8f03-f85364fbe929
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260079104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3260079104
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3778280146
Short name T1014
Test name
Test status
Simulation time 46611057 ps
CPU time 1.9 seconds
Started Jul 30 05:58:28 PM PDT 24
Finished Jul 30 05:58:30 PM PDT 24
Peak memory 219560 kb
Host smart-11bef167-58da-4794-9488-df50c12782fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778280146 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3778280146
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3284126533
Short name T277
Test name
Test status
Simulation time 23176420 ps
CPU time 0.87 seconds
Started Jul 30 05:58:28 PM PDT 24
Finished Jul 30 05:58:29 PM PDT 24
Peak memory 206560 kb
Host smart-cb92f3e1-4b7a-480b-afa0-ad482aede401
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284126533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3284126533
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1652459151
Short name T1039
Test name
Test status
Simulation time 38376860 ps
CPU time 0.82 seconds
Started Jul 30 05:58:28 PM PDT 24
Finished Jul 30 05:58:30 PM PDT 24
Peak memory 206396 kb
Host smart-8a6dd2fc-a52a-474f-bfc3-aa4f5a5d567f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652459151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1652459151
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1267332990
Short name T1081
Test name
Test status
Simulation time 73482696 ps
CPU time 1.07 seconds
Started Jul 30 05:58:29 PM PDT 24
Finished Jul 30 05:58:30 PM PDT 24
Peak memory 206784 kb
Host smart-e42b6425-91a6-48aa-a8f1-c064e8885304
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267332990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1267332990
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2342625120
Short name T1067
Test name
Test status
Simulation time 29146182 ps
CPU time 1.83 seconds
Started Jul 30 05:58:31 PM PDT 24
Finished Jul 30 05:58:33 PM PDT 24
Peak memory 214964 kb
Host smart-7de5705c-431e-46e4-a78e-f108ccf41bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342625120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2342625120
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3599988409
Short name T301
Test name
Test status
Simulation time 698135731 ps
CPU time 2.17 seconds
Started Jul 30 05:58:30 PM PDT 24
Finished Jul 30 05:58:32 PM PDT 24
Peak memory 214884 kb
Host smart-9c4aa553-30ff-42fb-a10d-e63c30f8344f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599988409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3599988409
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1316866586
Short name T1051
Test name
Test status
Simulation time 22907220 ps
CPU time 1.48 seconds
Started Jul 30 05:58:32 PM PDT 24
Finished Jul 30 05:58:34 PM PDT 24
Peak memory 214996 kb
Host smart-bef698b6-bfb7-4bbf-a3cd-aaaadbcbe5b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316866586 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1316866586
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2172785419
Short name T1073
Test name
Test status
Simulation time 39117975 ps
CPU time 0.91 seconds
Started Jul 30 05:58:28 PM PDT 24
Finished Jul 30 05:58:29 PM PDT 24
Peak memory 206584 kb
Host smart-a617f365-68fe-4bc4-a345-fc0909677208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172785419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2172785419
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2486187491
Short name T1023
Test name
Test status
Simulation time 14323360 ps
CPU time 0.86 seconds
Started Jul 30 05:58:28 PM PDT 24
Finished Jul 30 05:58:29 PM PDT 24
Peak memory 206604 kb
Host smart-c01efa64-d466-4b8b-be57-8c2aa4f26edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486187491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2486187491
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.512487372
Short name T1117
Test name
Test status
Simulation time 50930153 ps
CPU time 1.24 seconds
Started Jul 30 05:58:28 PM PDT 24
Finished Jul 30 05:58:30 PM PDT 24
Peak memory 206540 kb
Host smart-b4daef37-fb3c-42ae-9974-12a2f2bd93f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512487372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.512487372
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.664688362
Short name T1077
Test name
Test status
Simulation time 170249714 ps
CPU time 2.14 seconds
Started Jul 30 05:58:29 PM PDT 24
Finished Jul 30 05:58:31 PM PDT 24
Peak memory 215236 kb
Host smart-3e4f0056-9e3f-47d9-8f39-d3247734cded
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664688362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.664688362
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3795267241
Short name T1120
Test name
Test status
Simulation time 55000820 ps
CPU time 1.75 seconds
Started Jul 30 05:58:30 PM PDT 24
Finished Jul 30 05:58:32 PM PDT 24
Peak memory 214916 kb
Host smart-48b6facc-ad08-4ab9-8333-a42260412ff0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795267241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3795267241
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3688943739
Short name T310
Test name
Test status
Simulation time 25172455 ps
CPU time 1.12 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:20 PM PDT 24
Peak memory 218592 kb
Host smart-b973ab12-2bb6-4d85-9a0e-82bc6b8a4ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688943739 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3688943739
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2512561863
Short name T816
Test name
Test status
Simulation time 22702128 ps
CPU time 0.92 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 214848 kb
Host smart-80064b7e-b948-4676-a8be-6881558721a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512561863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2512561863
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.1186601008
Short name T125
Test name
Test status
Simulation time 39249340 ps
CPU time 0.89 seconds
Started Jul 30 06:44:13 PM PDT 24
Finished Jul 30 06:44:14 PM PDT 24
Peak memory 216212 kb
Host smart-5397d6ff-5449-4ad4-a07f-bbb3896c454c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186601008 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1186601008
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.1768077328
Short name T797
Test name
Test status
Simulation time 57096742 ps
CPU time 1 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 220404 kb
Host smart-d3d5eea4-2651-416a-9655-489b3b3f76cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768077328 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1768077328
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3460140348
Short name T548
Test name
Test status
Simulation time 48504084 ps
CPU time 1.14 seconds
Started Jul 30 06:44:16 PM PDT 24
Finished Jul 30 06:44:17 PM PDT 24
Peak memory 217364 kb
Host smart-1f4a88b1-e32b-4e52-bf63-fe0655cbdccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460140348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3460140348
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1530257064
Short name T613
Test name
Test status
Simulation time 23007718 ps
CPU time 1.12 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 215384 kb
Host smart-73ed7b64-d6a8-4717-997b-247448045e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530257064 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1530257064
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_smoke.2000535381
Short name T361
Test name
Test status
Simulation time 20212800 ps
CPU time 0.95 seconds
Started Jul 30 06:44:13 PM PDT 24
Finished Jul 30 06:44:15 PM PDT 24
Peak memory 215232 kb
Host smart-4a338100-e95a-4e95-8b86-291a899ede12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000535381 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2000535381
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1336461391
Short name T251
Test name
Test status
Simulation time 346050015 ps
CPU time 3.77 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:30 PM PDT 24
Peak memory 215300 kb
Host smart-bee4f870-4ebb-4470-8209-8779b7c2a4e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336461391 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1336461391
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.1817283500
Short name T159
Test name
Test status
Simulation time 23917543 ps
CPU time 1.17 seconds
Started Jul 30 06:44:15 PM PDT 24
Finished Jul 30 06:44:16 PM PDT 24
Peak memory 219468 kb
Host smart-f19df7e7-6b90-41a6-8967-af6b71c6b902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817283500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1817283500
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1095247951
Short name T625
Test name
Test status
Simulation time 29427091 ps
CPU time 0.91 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 206704 kb
Host smart-48f07a3e-1b37-44e5-b156-9a4775d12c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095247951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1095247951
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.3522144650
Short name T962
Test name
Test status
Simulation time 13167833 ps
CPU time 0.88 seconds
Started Jul 30 06:44:11 PM PDT 24
Finished Jul 30 06:44:12 PM PDT 24
Peak memory 216220 kb
Host smart-13198929-c3e8-4d60-b1ae-192d6c88f4e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522144650 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3522144650
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3228004287
Short name T153
Test name
Test status
Simulation time 107737443 ps
CPU time 1.1 seconds
Started Jul 30 06:44:18 PM PDT 24
Finished Jul 30 06:44:19 PM PDT 24
Peak memory 216936 kb
Host smart-dbdae7b0-5514-4121-899a-1e6de9a88047
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228004287 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3228004287
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2213744238
Short name T939
Test name
Test status
Simulation time 31869889 ps
CPU time 0.97 seconds
Started Jul 30 06:44:13 PM PDT 24
Finished Jul 30 06:44:14 PM PDT 24
Peak memory 223804 kb
Host smart-52c80e68-e349-4646-a6f2-d310847be468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213744238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2213744238
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_intr.3732025790
Short name T441
Test name
Test status
Simulation time 29317981 ps
CPU time 0.97 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 215320 kb
Host smart-a8b6d913-e8b9-40e2-a597-0972a09bee3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732025790 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3732025790
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_smoke.2841265740
Short name T424
Test name
Test status
Simulation time 45161653 ps
CPU time 0.9 seconds
Started Jul 30 06:44:17 PM PDT 24
Finished Jul 30 06:44:18 PM PDT 24
Peak memory 215288 kb
Host smart-9918b558-e265-4d76-896b-f8d293e0be60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841265740 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2841265740
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3035163000
Short name T850
Test name
Test status
Simulation time 2067164372 ps
CPU time 4.3 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 215264 kb
Host smart-4b44b968-0ffa-46da-8d54-e7a8d233cb75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035163000 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3035163000
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2888598659
Short name T860
Test name
Test status
Simulation time 53554648559 ps
CPU time 670.52 seconds
Started Jul 30 06:44:11 PM PDT 24
Finished Jul 30 06:55:22 PM PDT 24
Peak memory 218784 kb
Host smart-d88b3ca2-22e8-4388-9220-549fec06add6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888598659 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2888598659
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3894989482
Short name T546
Test name
Test status
Simulation time 53510769 ps
CPU time 1.18 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 220672 kb
Host smart-1a1ad352-e6be-4b00-9439-c55cccfd5aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894989482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3894989482
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_genbits.4104487037
Short name T737
Test name
Test status
Simulation time 145879578 ps
CPU time 1.55 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 219032 kb
Host smart-34363a31-f96a-4989-a6ce-fa0b55929548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104487037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.4104487037
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1742214243
Short name T938
Test name
Test status
Simulation time 26001193 ps
CPU time 1.02 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 224040 kb
Host smart-387ad749-0ea8-42a7-8033-4f2bde80a0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742214243 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1742214243
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.291912478
Short name T559
Test name
Test status
Simulation time 24621405 ps
CPU time 0.98 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 214204 kb
Host smart-1c464a79-8394-42d7-8dea-02c32398c6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291912478 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.291912478
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2319422087
Short name T788
Test name
Test status
Simulation time 2515847641 ps
CPU time 5.15 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 217076 kb
Host smart-7bacaeb6-7587-4056-b276-065db376fade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319422087 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2319422087
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2231648366
Short name T818
Test name
Test status
Simulation time 37122501403 ps
CPU time 811.92 seconds
Started Jul 30 06:44:15 PM PDT 24
Finished Jul 30 06:57:47 PM PDT 24
Peak memory 218360 kb
Host smart-251abd9a-cceb-4e4e-9055-9e5508227994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231648366 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2231648366
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.4051833605
Short name T843
Test name
Test status
Simulation time 49191832 ps
CPU time 1.13 seconds
Started Jul 30 06:45:21 PM PDT 24
Finished Jul 30 06:45:22 PM PDT 24
Peak memory 218828 kb
Host smart-03588352-1372-433a-9ddb-9fb903b3f2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051833605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.4051833605
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/101.edn_alert.655553244
Short name T75
Test name
Test status
Simulation time 50978140 ps
CPU time 1.33 seconds
Started Jul 30 06:45:30 PM PDT 24
Finished Jul 30 06:45:31 PM PDT 24
Peak memory 215632 kb
Host smart-0ba29983-4a65-436a-adfc-6b7ba4a020c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655553244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.655553244
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.2086239123
Short name T495
Test name
Test status
Simulation time 52650036 ps
CPU time 1.91 seconds
Started Jul 30 06:45:31 PM PDT 24
Finished Jul 30 06:45:33 PM PDT 24
Peak memory 218340 kb
Host smart-1d65e6c8-eed8-4000-b3f2-127a0c5f891a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086239123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2086239123
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.564615268
Short name T753
Test name
Test status
Simulation time 62458735 ps
CPU time 1.07 seconds
Started Jul 30 06:45:30 PM PDT 24
Finished Jul 30 06:45:31 PM PDT 24
Peak memory 219756 kb
Host smart-a52017f6-36fd-4ea6-a940-41bb47d138e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564615268 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.564615268
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2251514407
Short name T496
Test name
Test status
Simulation time 125041050 ps
CPU time 1.07 seconds
Started Jul 30 06:45:32 PM PDT 24
Finished Jul 30 06:45:33 PM PDT 24
Peak memory 217412 kb
Host smart-65f3f3a5-c573-4b52-88f6-4cbf151e96d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251514407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2251514407
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2599088815
Short name T945
Test name
Test status
Simulation time 99499464 ps
CPU time 1.34 seconds
Started Jul 30 06:45:29 PM PDT 24
Finished Jul 30 06:45:30 PM PDT 24
Peak memory 217556 kb
Host smart-65ce6649-620d-41bc-9ac5-47f755003b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599088815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2599088815
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.2987302479
Short name T174
Test name
Test status
Simulation time 103234440 ps
CPU time 1.18 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:28 PM PDT 24
Peak memory 218484 kb
Host smart-ed872cc1-28b0-4aab-adca-831fb8c2df53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987302479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2987302479
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.3475344373
Short name T869
Test name
Test status
Simulation time 38212638 ps
CPU time 1.33 seconds
Started Jul 30 06:45:21 PM PDT 24
Finished Jul 30 06:45:23 PM PDT 24
Peak memory 215292 kb
Host smart-33c682f1-1650-48b2-9e02-af8a17ead810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475344373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3475344373
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.496738333
Short name T21
Test name
Test status
Simulation time 31594842 ps
CPU time 1.42 seconds
Started Jul 30 06:45:31 PM PDT 24
Finished Jul 30 06:45:33 PM PDT 24
Peak memory 220272 kb
Host smart-f9f30ef4-66a3-49c6-a7b5-3613e46b6423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496738333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.496738333
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.2141353567
Short name T927
Test name
Test status
Simulation time 21825465 ps
CPU time 1.12 seconds
Started Jul 30 06:45:25 PM PDT 24
Finished Jul 30 06:45:28 PM PDT 24
Peak memory 217176 kb
Host smart-14072259-7c2e-42f3-b3d5-bba3393f2383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141353567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2141353567
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.3013577803
Short name T292
Test name
Test status
Simulation time 31672675 ps
CPU time 1.26 seconds
Started Jul 30 06:45:42 PM PDT 24
Finished Jul 30 06:45:44 PM PDT 24
Peak memory 219000 kb
Host smart-3f7694e7-6f38-4496-aecf-69e0657e2255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013577803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3013577803
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.267412292
Short name T828
Test name
Test status
Simulation time 76222020 ps
CPU time 1.18 seconds
Started Jul 30 06:45:37 PM PDT 24
Finished Jul 30 06:45:39 PM PDT 24
Peak memory 217272 kb
Host smart-5ae2fee2-0f09-4841-8815-8e9cac7b848d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267412292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.267412292
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.2603091458
Short name T209
Test name
Test status
Simulation time 28575027 ps
CPU time 1.26 seconds
Started Jul 30 06:45:34 PM PDT 24
Finished Jul 30 06:45:35 PM PDT 24
Peak memory 219684 kb
Host smart-c70d7fe1-0d40-48be-9034-5c116d7528cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603091458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2603091458
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.724242749
Short name T659
Test name
Test status
Simulation time 73710198 ps
CPU time 1.1 seconds
Started Jul 30 06:45:29 PM PDT 24
Finished Jul 30 06:45:31 PM PDT 24
Peak memory 217204 kb
Host smart-ce65ccad-ce62-4d8c-b0ec-2488d1c2a7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724242749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.724242749
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.3915315826
Short name T168
Test name
Test status
Simulation time 151934803 ps
CPU time 1.24 seconds
Started Jul 30 06:45:49 PM PDT 24
Finished Jul 30 06:45:50 PM PDT 24
Peak memory 218476 kb
Host smart-7cede63f-4d0f-46e2-9d39-87fbfaa50fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915315826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3915315826
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/109.edn_alert.4256038081
Short name T890
Test name
Test status
Simulation time 28467487 ps
CPU time 1.21 seconds
Started Jul 30 06:45:29 PM PDT 24
Finished Jul 30 06:45:30 PM PDT 24
Peak memory 218748 kb
Host smart-8b8c2b95-467e-48c1-bc95-38c624b736cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256038081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.4256038081
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3862051509
Short name T899
Test name
Test status
Simulation time 58972068 ps
CPU time 1.22 seconds
Started Jul 30 06:45:39 PM PDT 24
Finished Jul 30 06:45:41 PM PDT 24
Peak memory 217392 kb
Host smart-dc888f69-ccea-4a8d-8c7a-93e820a2f98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862051509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3862051509
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1525169168
Short name T183
Test name
Test status
Simulation time 77971396 ps
CPU time 1.23 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 218836 kb
Host smart-a6ae100d-e001-457d-b414-351f99bcabaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525169168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1525169168
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.4245054453
Short name T769
Test name
Test status
Simulation time 25273693 ps
CPU time 0.88 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 206860 kb
Host smart-b02ac7a2-18a2-4085-8682-bf7db9e810dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245054453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4245054453
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2102928211
Short name T181
Test name
Test status
Simulation time 30735023 ps
CPU time 0.8 seconds
Started Jul 30 06:44:28 PM PDT 24
Finished Jul 30 06:44:29 PM PDT 24
Peak memory 215348 kb
Host smart-114ceeb8-e889-4094-8cae-c3e6449f8c31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102928211 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2102928211
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.306053593
Short name T118
Test name
Test status
Simulation time 28376812 ps
CPU time 1.28 seconds
Started Jul 30 06:44:29 PM PDT 24
Finished Jul 30 06:44:30 PM PDT 24
Peak memory 229788 kb
Host smart-74f8583a-852d-4e5f-aa2d-54ea11e19940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306053593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.306053593
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.525901893
Short name T864
Test name
Test status
Simulation time 35123480 ps
CPU time 0.99 seconds
Started Jul 30 06:44:27 PM PDT 24
Finished Jul 30 06:44:29 PM PDT 24
Peak memory 224036 kb
Host smart-d0d3ebf2-ef0a-475c-a9f3-b3a620c9208a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525901893 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.525901893
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1627162444
Short name T372
Test name
Test status
Simulation time 25416942 ps
CPU time 0.9 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 215240 kb
Host smart-855614dd-d313-4ae8-af01-ed4225abcc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627162444 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1627162444
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.420459676
Short name T692
Test name
Test status
Simulation time 216749466 ps
CPU time 1.11 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 215256 kb
Host smart-b7b31cb0-59f5-4765-8ff4-54dd8b637e44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420459676 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.420459676
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2293340031
Short name T238
Test name
Test status
Simulation time 15256217042 ps
CPU time 332.41 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:49:56 PM PDT 24
Peak memory 218900 kb
Host smart-714240f5-3322-4d7d-888a-755c10dc516c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293340031 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2293340031
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.3781541796
Short name T798
Test name
Test status
Simulation time 31495141 ps
CPU time 1.22 seconds
Started Jul 30 06:45:37 PM PDT 24
Finished Jul 30 06:45:39 PM PDT 24
Peak memory 219716 kb
Host smart-08ebafbd-baca-411b-8f5f-f9d01ae691c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781541796 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.3781541796
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.2779080983
Short name T326
Test name
Test status
Simulation time 195441648 ps
CPU time 2.54 seconds
Started Jul 30 06:45:36 PM PDT 24
Finished Jul 30 06:45:39 PM PDT 24
Peak memory 219588 kb
Host smart-06e027f8-dc7c-4cde-8ee7-2d4dbeaf4d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779080983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2779080983
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.2398373761
Short name T200
Test name
Test status
Simulation time 37142890 ps
CPU time 1.09 seconds
Started Jul 30 06:45:35 PM PDT 24
Finished Jul 30 06:45:36 PM PDT 24
Peak memory 221280 kb
Host smart-b2ff824b-8d6b-44a6-9c09-bcc6e0b562c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398373761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2398373761
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/112.edn_alert.1726771735
Short name T293
Test name
Test status
Simulation time 29725513 ps
CPU time 1.36 seconds
Started Jul 30 06:45:42 PM PDT 24
Finished Jul 30 06:45:49 PM PDT 24
Peak memory 215716 kb
Host smart-34f97601-56ec-4b03-a252-b67c4a25b886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726771735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.1726771735
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.2795844491
Short name T877
Test name
Test status
Simulation time 109707781 ps
CPU time 1.26 seconds
Started Jul 30 06:45:30 PM PDT 24
Finished Jul 30 06:45:31 PM PDT 24
Peak memory 219568 kb
Host smart-7fe1876f-dbdb-4372-8e9d-47c878889edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795844491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2795844491
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.55295888
Short name T983
Test name
Test status
Simulation time 44780170 ps
CPU time 1.17 seconds
Started Jul 30 06:45:28 PM PDT 24
Finished Jul 30 06:45:29 PM PDT 24
Peak memory 218836 kb
Host smart-4d8c372c-452e-4395-9ba1-4a4bb7459c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55295888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.55295888
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.820589149
Short name T921
Test name
Test status
Simulation time 34349452 ps
CPU time 1.36 seconds
Started Jul 30 06:45:33 PM PDT 24
Finished Jul 30 06:45:35 PM PDT 24
Peak memory 219944 kb
Host smart-a64f5224-cea2-4f32-b292-a8d8719b5b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820589149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.820589149
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.2557651465
Short name T731
Test name
Test status
Simulation time 25526879 ps
CPU time 1.14 seconds
Started Jul 30 06:45:35 PM PDT 24
Finished Jul 30 06:45:36 PM PDT 24
Peak memory 218496 kb
Host smart-cf443734-972d-43b7-a8f0-efe1b9ed4f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557651465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.2557651465
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.194874506
Short name T785
Test name
Test status
Simulation time 124741560 ps
CPU time 1.37 seconds
Started Jul 30 06:45:44 PM PDT 24
Finished Jul 30 06:45:46 PM PDT 24
Peak memory 218920 kb
Host smart-8c1d8303-c653-4ace-be38-7823ee3c4e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194874506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.194874506
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.3623182570
Short name T560
Test name
Test status
Simulation time 117449443 ps
CPU time 2.81 seconds
Started Jul 30 06:45:49 PM PDT 24
Finished Jul 30 06:45:51 PM PDT 24
Peak memory 220196 kb
Host smart-6bfea24f-4664-4994-a7a4-d73e603720e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623182570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3623182570
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1787774517
Short name T598
Test name
Test status
Simulation time 30695609 ps
CPU time 1.24 seconds
Started Jul 30 06:45:49 PM PDT 24
Finished Jul 30 06:45:50 PM PDT 24
Peak memory 218620 kb
Host smart-8379113a-191b-4978-9303-ab4927fbe436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787774517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1787774517
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.1190789755
Short name T428
Test name
Test status
Simulation time 77113551 ps
CPU time 1.59 seconds
Started Jul 30 06:45:52 PM PDT 24
Finished Jul 30 06:45:53 PM PDT 24
Peak memory 218364 kb
Host smart-46e5c3f7-52b3-4f55-82bf-df7ce53bf515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190789755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1190789755
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.286623282
Short name T451
Test name
Test status
Simulation time 64289952 ps
CPU time 1.25 seconds
Started Jul 30 06:45:44 PM PDT 24
Finished Jul 30 06:45:45 PM PDT 24
Peak memory 219968 kb
Host smart-18e8cccc-a166-4fbf-9645-98d0fa9f8750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286623282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.286623282
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3281327980
Short name T542
Test name
Test status
Simulation time 46988450 ps
CPU time 1.53 seconds
Started Jul 30 06:45:49 PM PDT 24
Finished Jul 30 06:45:50 PM PDT 24
Peak memory 218464 kb
Host smart-d349d287-51f8-4b49-8f5e-78954dbb7e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281327980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3281327980
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.498526334
Short name T837
Test name
Test status
Simulation time 60648669 ps
CPU time 1.11 seconds
Started Jul 30 06:44:13 PM PDT 24
Finished Jul 30 06:44:14 PM PDT 24
Peak memory 214988 kb
Host smart-e7b5d553-78f2-4c59-923d-d29431edd682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498526334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.498526334
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2769782010
Short name T703
Test name
Test status
Simulation time 11334399 ps
CPU time 0.87 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 216376 kb
Host smart-1d428215-e530-4fa9-84d0-c272fbdf3dba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769782010 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2769782010
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3888034847
Short name T462
Test name
Test status
Simulation time 39219124 ps
CPU time 1.25 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 218644 kb
Host smart-8e7b6dde-a37e-4666-a4ae-82a7c4c4d55c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888034847 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3888034847
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1892640656
Short name T873
Test name
Test status
Simulation time 32993905 ps
CPU time 0.85 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:20 PM PDT 24
Peak memory 218392 kb
Host smart-d3a340fe-35db-4540-b1bb-e31064793952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892640656 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1892640656
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3592637220
Short name T677
Test name
Test status
Simulation time 24637408 ps
CPU time 1.16 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 217256 kb
Host smart-ccafe28d-01b5-431e-a26d-a88ff3455544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592637220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3592637220
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.234574553
Short name T629
Test name
Test status
Simulation time 28065086 ps
CPU time 0.96 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 215484 kb
Host smart-54a4a9b6-93b4-4ad5-ba17-2835501901d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234574553 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.234574553
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.318950885
Short name T541
Test name
Test status
Simulation time 23024927 ps
CPU time 0.89 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 215256 kb
Host smart-c8544a3b-76cc-434f-89cb-879cdc2b9fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318950885 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.318950885
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2314361214
Short name T422
Test name
Test status
Simulation time 410641918 ps
CPU time 2.78 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 217412 kb
Host smart-d46f168e-8dea-484f-ba63-3f1b9ab978b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314361214 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2314361214
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2782301988
Short name T235
Test name
Test status
Simulation time 379712187745 ps
CPU time 977.82 seconds
Started Jul 30 06:44:28 PM PDT 24
Finished Jul 30 07:00:46 PM PDT 24
Peak memory 222128 kb
Host smart-8efd14e4-5b9e-43fd-ae06-07539e653cc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782301988 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2782301988
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.1354899017
Short name T529
Test name
Test status
Simulation time 30127382 ps
CPU time 1.29 seconds
Started Jul 30 06:45:55 PM PDT 24
Finished Jul 30 06:45:56 PM PDT 24
Peak memory 219708 kb
Host smart-8a2f5bbb-e3bb-4f88-a987-411894eb4667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354899017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1354899017
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.2812529705
Short name T456
Test name
Test status
Simulation time 50331304 ps
CPU time 1.49 seconds
Started Jul 30 06:45:34 PM PDT 24
Finished Jul 30 06:45:35 PM PDT 24
Peak memory 217252 kb
Host smart-fd0dc483-7b58-4736-b696-df1c5c45b28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812529705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2812529705
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.198800276
Short name T306
Test name
Test status
Simulation time 29390209 ps
CPU time 1.18 seconds
Started Jul 30 06:45:53 PM PDT 24
Finished Jul 30 06:45:55 PM PDT 24
Peak memory 219692 kb
Host smart-7e757ec5-e79d-4032-aeaf-11b41261a878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198800276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.198800276
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.1789425212
Short name T567
Test name
Test status
Simulation time 28386955 ps
CPU time 1.25 seconds
Started Jul 30 06:45:56 PM PDT 24
Finished Jul 30 06:45:58 PM PDT 24
Peak memory 218384 kb
Host smart-7d2686c3-cafd-4808-bf13-d139aa7bbda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789425212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1789425212
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2621443615
Short name T597
Test name
Test status
Simulation time 34342620 ps
CPU time 1.09 seconds
Started Jul 30 06:45:36 PM PDT 24
Finished Jul 30 06:45:37 PM PDT 24
Peak memory 220664 kb
Host smart-25f4b703-1de9-4c8f-bfdc-69ed1853ebaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621443615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2621443615
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.3909813876
Short name T279
Test name
Test status
Simulation time 42997664 ps
CPU time 1.52 seconds
Started Jul 30 06:45:53 PM PDT 24
Finished Jul 30 06:45:54 PM PDT 24
Peak memory 219412 kb
Host smart-06f76f85-c4e5-4854-acdd-926ee3fd9c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909813876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3909813876
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.713819181
Short name T929
Test name
Test status
Simulation time 39724530 ps
CPU time 1.13 seconds
Started Jul 30 06:45:56 PM PDT 24
Finished Jul 30 06:45:58 PM PDT 24
Peak memory 219772 kb
Host smart-ed6fc4a9-a715-437b-9b6a-ef7da98d0f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713819181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.713819181
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.749415416
Short name T848
Test name
Test status
Simulation time 108557955 ps
CPU time 1.34 seconds
Started Jul 30 06:45:49 PM PDT 24
Finished Jul 30 06:45:51 PM PDT 24
Peak memory 218816 kb
Host smart-a84c708e-da94-48e6-a57a-e27ab9e7e129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749415416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.749415416
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.1022290553
Short name T931
Test name
Test status
Simulation time 67342598 ps
CPU time 1.16 seconds
Started Jul 30 06:45:51 PM PDT 24
Finished Jul 30 06:45:52 PM PDT 24
Peak memory 220084 kb
Host smart-16e0ab8a-5dce-43d6-98b9-2ddda10cef5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022290553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.1022290553
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.885708021
Short name T22
Test name
Test status
Simulation time 81935564 ps
CPU time 1.31 seconds
Started Jul 30 06:46:00 PM PDT 24
Finished Jul 30 06:46:02 PM PDT 24
Peak memory 218824 kb
Host smart-41d2c20e-3956-4e56-80cc-1667c98117f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885708021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.885708021
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.1095007704
Short name T611
Test name
Test status
Simulation time 66859603 ps
CPU time 1.07 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 218512 kb
Host smart-64fbd000-8a0e-4b20-abf5-cf5fc23c8594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095007704 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.1095007704
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/128.edn_alert.1839758589
Short name T467
Test name
Test status
Simulation time 31084389 ps
CPU time 1.32 seconds
Started Jul 30 06:45:35 PM PDT 24
Finished Jul 30 06:45:36 PM PDT 24
Peak memory 215652 kb
Host smart-378090f7-9ce9-4457-b457-15b8e44b81df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839758589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.1839758589
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.3077004271
Short name T867
Test name
Test status
Simulation time 45149039 ps
CPU time 1.18 seconds
Started Jul 30 06:45:50 PM PDT 24
Finished Jul 30 06:45:51 PM PDT 24
Peak memory 217292 kb
Host smart-42dd7eda-6952-415d-9d4c-c67b5cb32a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077004271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3077004271
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.812626203
Short name T732
Test name
Test status
Simulation time 49834807 ps
CPU time 1.27 seconds
Started Jul 30 06:45:50 PM PDT 24
Finished Jul 30 06:45:51 PM PDT 24
Peak memory 217404 kb
Host smart-df7634b6-741d-4a0c-9515-04b4dfaef8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812626203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.812626203
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1252313708
Short name T216
Test name
Test status
Simulation time 69543190 ps
CPU time 1.12 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 220264 kb
Host smart-005c9410-30b6-4309-a013-31035e2059c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252313708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1252313708
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2857435517
Short name T603
Test name
Test status
Simulation time 70384561 ps
CPU time 0.87 seconds
Started Jul 30 06:44:27 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 206664 kb
Host smart-488c24d7-3f77-4e5e-8847-83b423b4d4bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857435517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2857435517
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.192567450
Short name T616
Test name
Test status
Simulation time 12244107 ps
CPU time 0.92 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 216484 kb
Host smart-48f0e172-3631-47aa-b406-dd0909da9853
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192567450 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.192567450
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3977529261
Short name T974
Test name
Test status
Simulation time 90652831 ps
CPU time 1.1 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 216888 kb
Host smart-a2700533-9780-4859-b50c-293d63c8ddd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977529261 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3977529261
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3342081875
Short name T186
Test name
Test status
Simulation time 50956739 ps
CPU time 0.8 seconds
Started Jul 30 06:44:28 PM PDT 24
Finished Jul 30 06:44:29 PM PDT 24
Peak memory 218088 kb
Host smart-6033ece5-2133-4445-a623-50fe8ea40ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342081875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3342081875
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3857926230
Short name T953
Test name
Test status
Simulation time 39215685 ps
CPU time 1.34 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 218400 kb
Host smart-dca007e3-f42e-4c90-a8ba-758ec0c6db37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857926230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3857926230
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1221184514
Short name T400
Test name
Test status
Simulation time 27243446 ps
CPU time 0.98 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 215496 kb
Host smart-8e7864ab-5c04-4a8d-8e0d-8b99694c3854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221184514 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1221184514
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3684746256
Short name T595
Test name
Test status
Simulation time 17662294 ps
CPU time 1 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 215232 kb
Host smart-b6b68715-971d-4f58-9a81-ffb9a960189e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684746256 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3684746256
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.4227898961
Short name T98
Test name
Test status
Simulation time 277415139 ps
CPU time 2.02 seconds
Started Jul 30 06:44:23 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 215332 kb
Host smart-380df5b7-4721-40c7-8fcf-a2766bfcdf61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227898961 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.4227898961
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1547879235
Short name T656
Test name
Test status
Simulation time 90524754066 ps
CPU time 399.21 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:51:05 PM PDT 24
Peak memory 223636 kb
Host smart-3a137255-a5ce-40bd-a27a-45da50622a9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547879235 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1547879235
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.595757718
Short name T745
Test name
Test status
Simulation time 90369316 ps
CPU time 1.13 seconds
Started Jul 30 06:45:48 PM PDT 24
Finished Jul 30 06:45:50 PM PDT 24
Peak memory 218608 kb
Host smart-4203ae82-7792-4171-88be-cb242271a4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595757718 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.595757718
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2592798962
Short name T345
Test name
Test status
Simulation time 100703865 ps
CPU time 1.39 seconds
Started Jul 30 06:45:55 PM PDT 24
Finished Jul 30 06:45:57 PM PDT 24
Peak memory 218772 kb
Host smart-f4b35283-5e7c-4e0f-baa7-0ddfef361ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592798962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2592798962
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.2411373806
Short name T256
Test name
Test status
Simulation time 183840432 ps
CPU time 1.18 seconds
Started Jul 30 06:45:47 PM PDT 24
Finished Jul 30 06:45:48 PM PDT 24
Peak memory 219064 kb
Host smart-e16c1796-459b-4d42-a846-738e2578404b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411373806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.2411373806
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.2626005339
Short name T73
Test name
Test status
Simulation time 161753004 ps
CPU time 3.31 seconds
Started Jul 30 06:45:42 PM PDT 24
Finished Jul 30 06:45:45 PM PDT 24
Peak memory 219248 kb
Host smart-cce19b0b-81dc-4964-8346-caa9d448d471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626005339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2626005339
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.836345881
Short name T170
Test name
Test status
Simulation time 26938442 ps
CPU time 1.29 seconds
Started Jul 30 06:45:46 PM PDT 24
Finished Jul 30 06:45:47 PM PDT 24
Peak memory 220748 kb
Host smart-2f678973-66ef-433f-96af-71693f4f905c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836345881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.836345881
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.3633289961
Short name T751
Test name
Test status
Simulation time 46069901 ps
CPU time 1.17 seconds
Started Jul 30 06:45:59 PM PDT 24
Finished Jul 30 06:46:00 PM PDT 24
Peak memory 217324 kb
Host smart-0b92370a-69db-43b4-8786-12e4e293de24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633289961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3633289961
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.2971745262
Short name T566
Test name
Test status
Simulation time 77362834 ps
CPU time 1.26 seconds
Started Jul 30 06:45:48 PM PDT 24
Finished Jul 30 06:45:49 PM PDT 24
Peak memory 218776 kb
Host smart-46367c1e-ccf9-46db-ac91-fa81ba507c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971745262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2971745262
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.1962235361
Short name T94
Test name
Test status
Simulation time 62984208 ps
CPU time 1.48 seconds
Started Jul 30 06:45:59 PM PDT 24
Finished Jul 30 06:46:00 PM PDT 24
Peak memory 220264 kb
Host smart-27bac4f3-71ee-4e45-9d78-1c88cc9ea1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962235361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1962235361
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.3983657341
Short name T789
Test name
Test status
Simulation time 185701627 ps
CPU time 1.11 seconds
Started Jul 30 06:45:53 PM PDT 24
Finished Jul 30 06:45:54 PM PDT 24
Peak memory 221600 kb
Host smart-116be01d-95d0-4cb0-a075-e0cb00cde4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983657341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.3983657341
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.623070027
Short name T716
Test name
Test status
Simulation time 57594308 ps
CPU time 1.86 seconds
Started Jul 30 06:45:48 PM PDT 24
Finished Jul 30 06:45:50 PM PDT 24
Peak memory 220004 kb
Host smart-e165d963-b913-4402-af3d-c5218fd273e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623070027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.623070027
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.1210508379
Short name T530
Test name
Test status
Simulation time 26653001 ps
CPU time 1.28 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:03 PM PDT 24
Peak memory 220880 kb
Host smart-ec4bc3c6-4020-4235-b72d-d6aa79e7a4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210508379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.1210508379
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.461475149
Short name T461
Test name
Test status
Simulation time 51182715 ps
CPU time 1.9 seconds
Started Jul 30 06:45:43 PM PDT 24
Finished Jul 30 06:45:46 PM PDT 24
Peak memory 218460 kb
Host smart-10b3a276-5a4f-4165-9a29-4b15ef70959a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461475149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.461475149
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1524253035
Short name T892
Test name
Test status
Simulation time 27035761 ps
CPU time 1.19 seconds
Started Jul 30 06:45:47 PM PDT 24
Finished Jul 30 06:45:48 PM PDT 24
Peak memory 215688 kb
Host smart-01410708-de52-44fb-a79b-7256d5ab24fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524253035 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1524253035
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2621587137
Short name T448
Test name
Test status
Simulation time 125162728 ps
CPU time 1.11 seconds
Started Jul 30 06:45:53 PM PDT 24
Finished Jul 30 06:45:54 PM PDT 24
Peak memory 217256 kb
Host smart-478fbaca-d4a4-4242-b8ca-44ac8f191d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621587137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2621587137
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.727983989
Short name T779
Test name
Test status
Simulation time 24566694 ps
CPU time 1.18 seconds
Started Jul 30 06:46:00 PM PDT 24
Finished Jul 30 06:46:02 PM PDT 24
Peak memory 218708 kb
Host smart-8587a363-74b2-4dce-8561-6349f5e21589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727983989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.727983989
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.1317515616
Short name T212
Test name
Test status
Simulation time 58948309 ps
CPU time 1.59 seconds
Started Jul 30 06:46:00 PM PDT 24
Finished Jul 30 06:46:02 PM PDT 24
Peak memory 218820 kb
Host smart-670bc73a-1b6e-4f16-b992-06090b0ee56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317515616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1317515616
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.99858240
Short name T487
Test name
Test status
Simulation time 66638079 ps
CPU time 1.14 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 219652 kb
Host smart-08c1697b-6c96-4220-8a01-fb22f074d1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99858240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.99858240
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.3954544820
Short name T136
Test name
Test status
Simulation time 36352750 ps
CPU time 1.37 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 218464 kb
Host smart-82a624bf-80b3-4c7e-afc4-b842132481b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954544820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3954544820
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.3325691560
Short name T141
Test name
Test status
Simulation time 73083142 ps
CPU time 1.2 seconds
Started Jul 30 06:45:51 PM PDT 24
Finished Jul 30 06:45:52 PM PDT 24
Peak memory 215660 kb
Host smart-84de24cb-9f68-4c04-b31e-ff18303fb2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325691560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.3325691560
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.2262032942
Short name T13
Test name
Test status
Simulation time 156414505 ps
CPU time 1.69 seconds
Started Jul 30 06:45:51 PM PDT 24
Finished Jul 30 06:45:53 PM PDT 24
Peak memory 218576 kb
Host smart-d1fc79cd-8587-4754-a1ba-535dae3cad79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262032942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2262032942
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.680728913
Short name T2
Test name
Test status
Simulation time 29298828 ps
CPU time 1.17 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 219416 kb
Host smart-2421e04c-a8b0-40e0-b63c-a3ab97fd4196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680728913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.680728913
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3360981879
Short name T427
Test name
Test status
Simulation time 24297459 ps
CPU time 0.95 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 206672 kb
Host smart-fff89014-72d4-4e37-9ba9-2373d0b5126c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360981879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3360981879
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.4108189410
Short name T124
Test name
Test status
Simulation time 12051941 ps
CPU time 0.92 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 216384 kb
Host smart-6d942571-7550-4134-bf81-9f9a9c967668
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108189410 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.4108189410
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2923035098
Short name T17
Test name
Test status
Simulation time 38512192 ps
CPU time 1.06 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 219632 kb
Host smart-d5582b7f-2b50-4899-98ed-9b8d5e430246
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923035098 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2923035098
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3782630812
Short name T854
Test name
Test status
Simulation time 36643005 ps
CPU time 0.84 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 217268 kb
Host smart-259b351d-39a6-4c6d-8a43-7d2d885fd981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782630812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3782630812
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2158725220
Short name T746
Test name
Test status
Simulation time 71744999 ps
CPU time 1.27 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 217272 kb
Host smart-5c7a8564-b613-436a-9fd7-5be98212b707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158725220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2158725220
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2179249305
Short name T90
Test name
Test status
Simulation time 25362325 ps
CPU time 0.93 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 214840 kb
Host smart-0905d737-911c-499a-a7c6-87a576123fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179249305 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2179249305
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3607055998
Short name T254
Test name
Test status
Simulation time 61265315 ps
CPU time 0.89 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 215244 kb
Host smart-e8cc2d9f-242d-4a0a-bb49-5774928af613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607055998 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3607055998
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1807423130
Short name T359
Test name
Test status
Simulation time 330060665 ps
CPU time 3.93 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:31 PM PDT 24
Peak memory 217316 kb
Host smart-0075c0e5-38f8-4311-88eb-d83c79993155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807423130 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1807423130
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3567121296
Short name T771
Test name
Test status
Simulation time 64321474601 ps
CPU time 1407.99 seconds
Started Jul 30 06:44:27 PM PDT 24
Finished Jul 30 07:07:56 PM PDT 24
Peak memory 223732 kb
Host smart-7b36a20d-f5a2-4b5c-b5e5-4abbbcf2cfe3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567121296 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3567121296
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.1770501950
Short name T143
Test name
Test status
Simulation time 45187528 ps
CPU time 1.23 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:02 PM PDT 24
Peak memory 220068 kb
Host smart-35f023ff-f274-4023-83fc-c217dad60081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770501950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1770501950
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3887708789
Short name T707
Test name
Test status
Simulation time 60593919 ps
CPU time 0.96 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:02 PM PDT 24
Peak memory 217228 kb
Host smart-e8d75388-ac4e-4482-873e-305d89756dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887708789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3887708789
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.1975436141
Short name T861
Test name
Test status
Simulation time 72418067 ps
CPU time 1.08 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 219508 kb
Host smart-6732c573-fa80-4c69-8b4e-1f2c5aa8d56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975436141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1975436141
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.917381077
Short name T374
Test name
Test status
Simulation time 43435419 ps
CPU time 1.46 seconds
Started Jul 30 06:45:53 PM PDT 24
Finished Jul 30 06:45:54 PM PDT 24
Peak memory 218828 kb
Host smart-d7b395a2-3ae1-4e2b-8693-2b66afd4dd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917381077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.917381077
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3109982669
Short name T532
Test name
Test status
Simulation time 62842469 ps
CPU time 1.12 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:02 PM PDT 24
Peak memory 219552 kb
Host smart-a54f847b-a9d5-42f2-ac17-fbd756d827a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109982669 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3109982669
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.2715173553
Short name T809
Test name
Test status
Simulation time 76160671 ps
CPU time 1.11 seconds
Started Jul 30 06:45:50 PM PDT 24
Finished Jul 30 06:45:51 PM PDT 24
Peak memory 219816 kb
Host smart-ed813c53-aa9f-4494-b5bd-4b71e983edf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715173553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2715173553
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1671271423
Short name T308
Test name
Test status
Simulation time 38917609 ps
CPU time 1.09 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:04 PM PDT 24
Peak memory 218708 kb
Host smart-78210876-7a99-472d-9850-f2cba1035c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671271423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1671271423
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.3171065178
Short name T840
Test name
Test status
Simulation time 173712921 ps
CPU time 1.62 seconds
Started Jul 30 06:45:59 PM PDT 24
Finished Jul 30 06:46:01 PM PDT 24
Peak memory 218972 kb
Host smart-39cd76a9-2458-418f-810b-f689ccf90e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171065178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3171065178
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3587801742
Short name T547
Test name
Test status
Simulation time 37904480 ps
CPU time 1.46 seconds
Started Jul 30 06:45:54 PM PDT 24
Finished Jul 30 06:45:56 PM PDT 24
Peak memory 218532 kb
Host smart-899eb5ef-fd32-4eb1-92be-e64a64d94036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587801742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3587801742
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2295596791
Short name T282
Test name
Test status
Simulation time 46088449 ps
CPU time 1.14 seconds
Started Jul 30 06:45:58 PM PDT 24
Finished Jul 30 06:46:00 PM PDT 24
Peak memory 218512 kb
Host smart-f5c67b07-fc05-4a57-be32-520c1e703c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295596791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2295596791
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.492303052
Short name T827
Test name
Test status
Simulation time 124010710 ps
CPU time 1.01 seconds
Started Jul 30 06:45:50 PM PDT 24
Finished Jul 30 06:45:51 PM PDT 24
Peak memory 217104 kb
Host smart-8463759d-5526-4741-88b4-171545190003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492303052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.492303052
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.1321176762
Short name T893
Test name
Test status
Simulation time 27489799 ps
CPU time 1.23 seconds
Started Jul 30 06:45:59 PM PDT 24
Finished Jul 30 06:46:00 PM PDT 24
Peak memory 219604 kb
Host smart-170d40a4-e855-4a74-889d-854e61febfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321176762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1321176762
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.1018239185
Short name T908
Test name
Test status
Simulation time 64200918 ps
CPU time 2.18 seconds
Started Jul 30 06:46:02 PM PDT 24
Finished Jul 30 06:46:04 PM PDT 24
Peak memory 217612 kb
Host smart-0391f8ec-897c-411a-b13b-7123660f32a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018239185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1018239185
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.1595603092
Short name T480
Test name
Test status
Simulation time 41477013 ps
CPU time 1.08 seconds
Started Jul 30 06:46:00 PM PDT 24
Finished Jul 30 06:46:01 PM PDT 24
Peak memory 218700 kb
Host smart-74fe03be-68ed-412c-9e0b-0304e7b3700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595603092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1595603092
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.3001846204
Short name T431
Test name
Test status
Simulation time 47130985 ps
CPU time 1.56 seconds
Started Jul 30 06:45:59 PM PDT 24
Finished Jul 30 06:46:01 PM PDT 24
Peak memory 219924 kb
Host smart-9a4a74ab-295c-4cae-ac92-c0e5d37cea2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001846204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3001846204
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.255403562
Short name T766
Test name
Test status
Simulation time 55269817 ps
CPU time 1.32 seconds
Started Jul 30 06:45:58 PM PDT 24
Finished Jul 30 06:46:00 PM PDT 24
Peak memory 218500 kb
Host smart-c1e94671-acf3-41f2-b95c-dadfdcbfba36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255403562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.255403562
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.234160530
Short name T38
Test name
Test status
Simulation time 28558856 ps
CPU time 1.26 seconds
Started Jul 30 06:44:27 PM PDT 24
Finished Jul 30 06:44:29 PM PDT 24
Peak memory 219948 kb
Host smart-7120dcaf-18ec-470d-bbde-c3158e83f32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234160530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.234160530
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2710193487
Short name T842
Test name
Test status
Simulation time 55678276 ps
CPU time 0.93 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 206668 kb
Host smart-d4ae7602-ca4f-4823-afe4-3428453ea1f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710193487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2710193487
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2206677405
Short name T217
Test name
Test status
Simulation time 12029342 ps
CPU time 0.86 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 216356 kb
Host smart-966d8afd-aaeb-452f-972b-a17044395358
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206677405 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2206677405
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.271994714
Short name T833
Test name
Test status
Simulation time 61798875 ps
CPU time 1.21 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 216856 kb
Host smart-cfb6ebea-5f82-4b3c-9829-2c457c86b2cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271994714 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.271994714
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1521115564
Short name T847
Test name
Test status
Simulation time 18458254 ps
CPU time 1.09 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 218632 kb
Host smart-c72f945d-2858-485d-abcd-c225117ac9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521115564 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1521115564
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1078969034
Short name T371
Test name
Test status
Simulation time 97477469 ps
CPU time 1.64 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 218840 kb
Host smart-2546079e-f6c0-409e-a3c3-4275520d9c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078969034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1078969034
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.4273935134
Short name T663
Test name
Test status
Simulation time 22941408 ps
CPU time 1.1 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 215516 kb
Host smart-c1c02c95-c451-4b06-ad78-90b574596451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273935134 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.4273935134
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1587093952
Short name T765
Test name
Test status
Simulation time 105327616 ps
CPU time 0.93 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 207048 kb
Host smart-1ee9b8ab-f70c-4bdc-9760-3bfeb3c0841c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587093952 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1587093952
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2946475259
Short name T247
Test name
Test status
Simulation time 432126680 ps
CPU time 6.7 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 215288 kb
Host smart-cb2de8cb-a043-4f13-bd5a-7fc2829a6fb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946475259 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2946475259
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_alert.4238206103
Short name T905
Test name
Test status
Simulation time 43165716 ps
CPU time 1.21 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:04 PM PDT 24
Peak memory 218736 kb
Host smart-3429c7c4-dd98-4a82-afda-824458b940d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238206103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.4238206103
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.3332541162
Short name T865
Test name
Test status
Simulation time 58180083 ps
CPU time 1.27 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:03 PM PDT 24
Peak memory 218456 kb
Host smart-f46b6612-46b6-4a37-9392-d2dffd90fa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332541162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3332541162
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.889711767
Short name T912
Test name
Test status
Simulation time 70448969 ps
CPU time 1.15 seconds
Started Jul 30 06:46:04 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 219064 kb
Host smart-ea44b47d-1e44-402b-8ade-b594989a2fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889711767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.889711767
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.1444431762
Short name T318
Test name
Test status
Simulation time 41694169 ps
CPU time 1.48 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:02 PM PDT 24
Peak memory 217260 kb
Host smart-14b131e3-4fe9-4257-ad79-3019d1beee9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444431762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1444431762
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3510929153
Short name T218
Test name
Test status
Simulation time 22955103 ps
CPU time 1.16 seconds
Started Jul 30 06:45:48 PM PDT 24
Finished Jul 30 06:45:49 PM PDT 24
Peak memory 219300 kb
Host smart-73b16ffe-3336-4097-8259-2d344027c1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510929153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3510929153
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.2047538929
Short name T803
Test name
Test status
Simulation time 48186884 ps
CPU time 1.8 seconds
Started Jul 30 06:45:51 PM PDT 24
Finished Jul 30 06:45:53 PM PDT 24
Peak memory 217348 kb
Host smart-f4d87d42-ebab-4abf-ac13-d6d5c925b43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047538929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2047538929
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.1241043605
Short name T802
Test name
Test status
Simulation time 55582925 ps
CPU time 1.34 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 219800 kb
Host smart-1e729729-3e2e-4eb9-b39b-21c96597736c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241043605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1241043605
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.451662132
Short name T463
Test name
Test status
Simulation time 50588912 ps
CPU time 1.22 seconds
Started Jul 30 06:46:02 PM PDT 24
Finished Jul 30 06:46:03 PM PDT 24
Peak memory 219768 kb
Host smart-240f500d-a26c-444f-8a57-d8f375bb8946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451662132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.451662132
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1651385475
Short name T783
Test name
Test status
Simulation time 62633739 ps
CPU time 1.32 seconds
Started Jul 30 06:45:56 PM PDT 24
Finished Jul 30 06:45:58 PM PDT 24
Peak memory 218304 kb
Host smart-015002fd-6e12-4eee-8737-64dfaba51af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651385475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1651385475
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.406777285
Short name T697
Test name
Test status
Simulation time 29142165 ps
CPU time 1.31 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:03 PM PDT 24
Peak memory 219260 kb
Host smart-b172feea-ac7d-48c0-b843-c9f5b0deeb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406777285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.406777285
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.2998509154
Short name T416
Test name
Test status
Simulation time 69990247 ps
CPU time 1.24 seconds
Started Jul 30 06:45:54 PM PDT 24
Finished Jul 30 06:45:55 PM PDT 24
Peak memory 217420 kb
Host smart-7c79566d-213c-4377-8aa7-60f4d908b195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998509154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2998509154
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.2912427786
Short name T915
Test name
Test status
Simulation time 42545009 ps
CPU time 1.12 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 218940 kb
Host smart-e1d8ae9d-6db1-42eb-a652-54bb3d270ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912427786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.2912427786
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3439784797
Short name T438
Test name
Test status
Simulation time 89736104 ps
CPU time 1.3 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 218824 kb
Host smart-dff21ab9-8200-4844-9c2f-e99eabf2fa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439784797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3439784797
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.1117646049
Short name T309
Test name
Test status
Simulation time 297833142 ps
CPU time 1.17 seconds
Started Jul 30 06:45:58 PM PDT 24
Finished Jul 30 06:45:59 PM PDT 24
Peak memory 219720 kb
Host smart-892138b4-3525-44dd-b202-a9b7be1e78cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117646049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1117646049
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.1504656328
Short name T868
Test name
Test status
Simulation time 25792211 ps
CPU time 1.2 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 217324 kb
Host smart-eea71ee6-5a3e-4d8d-8a5c-184e5d7a970e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504656328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1504656328
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.395424596
Short name T149
Test name
Test status
Simulation time 33633369 ps
CPU time 1.33 seconds
Started Jul 30 06:45:57 PM PDT 24
Finished Jul 30 06:45:59 PM PDT 24
Peak memory 215684 kb
Host smart-168c6449-9e88-497a-b717-cdd699ef74cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395424596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.395424596
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.2889281197
Short name T297
Test name
Test status
Simulation time 51142310 ps
CPU time 1.6 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 218632 kb
Host smart-fa6ebda1-5361-49e1-814f-71983fa08258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889281197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2889281197
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.3409802192
Short name T965
Test name
Test status
Simulation time 23298453 ps
CPU time 1.16 seconds
Started Jul 30 06:45:58 PM PDT 24
Finished Jul 30 06:45:59 PM PDT 24
Peak memory 220824 kb
Host smart-2af29500-5632-4c96-8983-084537ad0680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409802192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.3409802192
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.4021428637
Short name T315
Test name
Test status
Simulation time 46692203 ps
CPU time 1.82 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 220148 kb
Host smart-2484a40d-6de1-4824-a3d3-ea7de8ea35e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021428637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.4021428637
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.4032550715
Short name T826
Test name
Test status
Simulation time 72738545 ps
CPU time 1.12 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 218700 kb
Host smart-9819cdd2-dfd3-46c0-a9e5-b9d176c72142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032550715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.4032550715
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3850534010
Short name T591
Test name
Test status
Simulation time 60536944 ps
CPU time 1.07 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 214928 kb
Host smart-af18a478-f524-4f3e-bb88-1c2ba615ed2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850534010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3850534010
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.1167078670
Short name T111
Test name
Test status
Simulation time 65414360 ps
CPU time 0.82 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 216252 kb
Host smart-c935d425-0f81-47e9-88ca-d0b6b34cc121
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167078670 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1167078670
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.2962417380
Short name T492
Test name
Test status
Simulation time 24934757 ps
CPU time 0.95 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 218656 kb
Host smart-f0e4d832-2519-4ed0-922c-5c66ccefdc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962417380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2962417380
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2694692015
Short name T353
Test name
Test status
Simulation time 25334188 ps
CPU time 1.11 seconds
Started Jul 30 06:44:18 PM PDT 24
Finished Jul 30 06:44:19 PM PDT 24
Peak memory 217368 kb
Host smart-25b4b8ff-efc9-4058-bb4c-ea5a295b76f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694692015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2694692015
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3543344001
Short name T364
Test name
Test status
Simulation time 35031417 ps
CPU time 0.88 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 215324 kb
Host smart-485d6cd0-6f13-4f4a-9589-e598a7956a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543344001 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3543344001
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.985778997
Short name T600
Test name
Test status
Simulation time 45691196 ps
CPU time 0.99 seconds
Started Jul 30 06:44:53 PM PDT 24
Finished Jul 30 06:44:54 PM PDT 24
Peak memory 215268 kb
Host smart-81964edb-80e7-40f7-a8df-2b506830f3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985778997 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.985778997
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3012491731
Short name T234
Test name
Test status
Simulation time 57747097013 ps
CPU time 814.29 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:58:01 PM PDT 24
Peak memory 223604 kb
Host smart-7aee2bc4-025f-43d8-af1c-39504283b36b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012491731 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3012491731
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3547372546
Short name T178
Test name
Test status
Simulation time 280450384 ps
CPU time 1.53 seconds
Started Jul 30 06:46:02 PM PDT 24
Finished Jul 30 06:46:04 PM PDT 24
Peak memory 218328 kb
Host smart-07c61791-493f-4c86-95d7-1d00d3d52808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547372546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3547372546
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1406568614
Short name T935
Test name
Test status
Simulation time 117074528 ps
CPU time 2.2 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 219872 kb
Host smart-3b6084eb-0365-454b-9eff-b9ec938a95b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406568614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1406568614
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.3373417895
Short name T887
Test name
Test status
Simulation time 28249221 ps
CPU time 1.24 seconds
Started Jul 30 06:45:51 PM PDT 24
Finished Jul 30 06:45:53 PM PDT 24
Peak memory 219456 kb
Host smart-9aab3078-9f8c-4fcc-9b5c-a128d92311a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373417895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3373417895
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.1295409396
Short name T16
Test name
Test status
Simulation time 86691894 ps
CPU time 1.2 seconds
Started Jul 30 06:46:04 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 220060 kb
Host smart-dbbd599b-4028-490d-8ead-ffcc5227fde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295409396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1295409396
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.3330408770
Short name T314
Test name
Test status
Simulation time 45037362 ps
CPU time 1.11 seconds
Started Jul 30 06:46:00 PM PDT 24
Finished Jul 30 06:46:01 PM PDT 24
Peak memory 218472 kb
Host smart-e4a51617-6e3e-4292-90d9-a0c7372d71ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330408770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.3330408770
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.311966685
Short name T722
Test name
Test status
Simulation time 220967180 ps
CPU time 1.79 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:14 PM PDT 24
Peak memory 219188 kb
Host smart-3fc5fb85-f605-475c-b1e5-9ae7b1bbde00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311966685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.311966685
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.2546677065
Short name T739
Test name
Test status
Simulation time 89327473 ps
CPU time 1.09 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 219296 kb
Host smart-113b6987-7c51-46cd-b8ca-a22259515364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546677065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.2546677065
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.2268788535
Short name T801
Test name
Test status
Simulation time 39571321 ps
CPU time 1.67 seconds
Started Jul 30 06:45:47 PM PDT 24
Finished Jul 30 06:45:49 PM PDT 24
Peak memory 218568 kb
Host smart-ae549ecb-c4b6-4edf-b824-6dd5865dfacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268788535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2268788535
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.3100871127
Short name T857
Test name
Test status
Simulation time 43033913 ps
CPU time 1.15 seconds
Started Jul 30 06:45:52 PM PDT 24
Finished Jul 30 06:45:53 PM PDT 24
Peak memory 220020 kb
Host smart-270e45b4-678b-4f65-b102-a136e0a9f420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100871127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3100871127
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3111393438
Short name T956
Test name
Test status
Simulation time 61674258 ps
CPU time 1.42 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:04 PM PDT 24
Peak memory 218708 kb
Host smart-533161d3-8bf1-4ec5-a7e5-f83f8a7194be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111393438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3111393438
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.4161946553
Short name T215
Test name
Test status
Simulation time 72184535 ps
CPU time 1.26 seconds
Started Jul 30 06:46:02 PM PDT 24
Finished Jul 30 06:46:03 PM PDT 24
Peak memory 219556 kb
Host smart-e1786b81-fcd2-4b0c-b469-d5e18c3deaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161946553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.4161946553
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1717234587
Short name T952
Test name
Test status
Simulation time 50093057 ps
CPU time 1.43 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 217400 kb
Host smart-85d74a6d-b94e-481d-add3-2beac0554159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717234587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1717234587
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.4015604178
Short name T713
Test name
Test status
Simulation time 82613697 ps
CPU time 1.22 seconds
Started Jul 30 06:46:02 PM PDT 24
Finished Jul 30 06:46:04 PM PDT 24
Peak memory 218532 kb
Host smart-ad293759-5569-4fd7-84ac-c452d86d0009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015604178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.4015604178
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.1509972741
Short name T352
Test name
Test status
Simulation time 58085117 ps
CPU time 1.27 seconds
Started Jul 30 06:45:50 PM PDT 24
Finished Jul 30 06:45:51 PM PDT 24
Peak memory 218648 kb
Host smart-8bf998ba-d56f-453b-8f15-789feef68dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509972741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1509972741
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.4144435817
Short name T627
Test name
Test status
Simulation time 70149316 ps
CPU time 1.13 seconds
Started Jul 30 06:45:58 PM PDT 24
Finished Jul 30 06:45:59 PM PDT 24
Peak memory 218576 kb
Host smart-22709109-48e8-41e2-8459-14a4453552fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144435817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.4144435817
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/168.edn_alert.1682584795
Short name T834
Test name
Test status
Simulation time 31189576 ps
CPU time 1.2 seconds
Started Jul 30 06:46:04 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 219536 kb
Host smart-32cd8ef7-b23b-49a6-9d2d-b196e3061bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682584795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1682584795
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.4234178210
Short name T920
Test name
Test status
Simulation time 116831321 ps
CPU time 1.4 seconds
Started Jul 30 06:46:02 PM PDT 24
Finished Jul 30 06:46:04 PM PDT 24
Peak memory 218680 kb
Host smart-a2a9105b-eca2-46ea-b3e7-d6fca9807680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234178210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.4234178210
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.1829160415
Short name T815
Test name
Test status
Simulation time 292191258 ps
CPU time 1.44 seconds
Started Jul 30 06:45:57 PM PDT 24
Finished Jul 30 06:45:58 PM PDT 24
Peak memory 218536 kb
Host smart-894af151-d90b-49f5-bdbf-856c5baa1bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829160415 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1829160415
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.3736936236
Short name T770
Test name
Test status
Simulation time 82977021 ps
CPU time 1.14 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:02 PM PDT 24
Peak memory 217716 kb
Host smart-bcfeba68-be5c-40d0-b771-205b5615b7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736936236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3736936236
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2106484244
Short name T878
Test name
Test status
Simulation time 33004854 ps
CPU time 1.18 seconds
Started Jul 30 06:44:42 PM PDT 24
Finished Jul 30 06:44:43 PM PDT 24
Peak memory 220000 kb
Host smart-702babed-a889-4b04-9738-d27caa75629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106484244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2106484244
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2403136968
Short name T50
Test name
Test status
Simulation time 33318847 ps
CPU time 0.92 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 214860 kb
Host smart-6b6487f5-7d66-4cd1-af6d-04631e0f3900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403136968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2403136968
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.4082541280
Short name T450
Test name
Test status
Simulation time 11434617 ps
CPU time 0.89 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 215872 kb
Host smart-8642d019-4506-4a8f-aac1-e7e017da88cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082541280 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.4082541280
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1813550939
Short name T493
Test name
Test status
Simulation time 31244025 ps
CPU time 1.19 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 218368 kb
Host smart-09e398cf-de15-47e8-bdf3-d862eca59680
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813550939 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1813550939
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1283522797
Short name T793
Test name
Test status
Simulation time 38230009 ps
CPU time 0.93 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 223872 kb
Host smart-06f5f15c-d6e1-4794-9d96-b60833e90ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283522797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1283522797
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1750375412
Short name T897
Test name
Test status
Simulation time 40792186 ps
CPU time 1.52 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 218508 kb
Host smart-f9c4521c-a59d-49fd-a962-54deaf98a4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750375412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1750375412
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1198945814
Short name T355
Test name
Test status
Simulation time 25698013 ps
CPU time 1.02 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 215476 kb
Host smart-1a6dbd42-f0e2-4fad-b77a-133a19ba0070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198945814 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1198945814
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3640722149
Short name T485
Test name
Test status
Simulation time 39213022 ps
CPU time 0.85 seconds
Started Jul 30 06:44:39 PM PDT 24
Finished Jul 30 06:44:40 PM PDT 24
Peak memory 215260 kb
Host smart-9f1b57d1-e519-48f7-a9ac-3fc1b2960c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640722149 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3640722149
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.382738965
Short name T780
Test name
Test status
Simulation time 107369779 ps
CPU time 1.49 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:29 PM PDT 24
Peak memory 217136 kb
Host smart-60fdeb8c-77a0-40c0-a41b-19fe7e8bdd80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382738965 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.382738965
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.963828674
Short name T440
Test name
Test status
Simulation time 53627887889 ps
CPU time 1410.13 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 07:07:54 PM PDT 24
Peak memory 222492 kb
Host smart-a85fcdf2-4b96-499a-8927-a74720f9073f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963828674 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.963828674
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1032192572
Short name T658
Test name
Test status
Simulation time 42917173 ps
CPU time 1.18 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 220804 kb
Host smart-3197f27c-6c64-4acc-917b-7c20a06cfa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032192572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1032192572
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.976165121
Short name T498
Test name
Test status
Simulation time 100646740 ps
CPU time 1.91 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 218632 kb
Host smart-9743e611-1fd4-4dc7-b841-a8ea57d4da10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976165121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.976165121
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1476551569
Short name T874
Test name
Test status
Simulation time 39324098 ps
CPU time 1.17 seconds
Started Jul 30 06:46:04 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 220856 kb
Host smart-96595fcf-a2f3-41d3-bc33-14de5112ebf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476551569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1476551569
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.1509896732
Short name T452
Test name
Test status
Simulation time 43489695 ps
CPU time 1.76 seconds
Started Jul 30 06:45:57 PM PDT 24
Finished Jul 30 06:45:59 PM PDT 24
Peak memory 218752 kb
Host smart-94194608-1b7a-4065-b578-f5e26202ee29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509896732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1509896732
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1377227748
Short name T679
Test name
Test status
Simulation time 64162187 ps
CPU time 1.16 seconds
Started Jul 30 06:46:14 PM PDT 24
Finished Jul 30 06:46:15 PM PDT 24
Peak memory 218788 kb
Host smart-f45ae98b-a2ed-4e5d-a061-b940b064075f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377227748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1377227748
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.801947222
Short name T453
Test name
Test status
Simulation time 32557128 ps
CPU time 1.34 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 217476 kb
Host smart-c76a0ca6-af3d-44fe-bcec-50ae6d7550cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801947222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.801947222
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.1056088484
Short name T686
Test name
Test status
Simulation time 50386455 ps
CPU time 1.16 seconds
Started Jul 30 06:46:02 PM PDT 24
Finished Jul 30 06:46:04 PM PDT 24
Peak memory 219680 kb
Host smart-2c990136-65ba-49e8-b706-0daa9605e0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056088484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.1056088484
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.2495545660
Short name T340
Test name
Test status
Simulation time 73299850 ps
CPU time 1.38 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 220120 kb
Host smart-e5dcca3f-92d0-45cd-9941-261f48cac496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495545660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2495545660
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.3884866827
Short name T680
Test name
Test status
Simulation time 24087191 ps
CPU time 1.16 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:02 PM PDT 24
Peak memory 218620 kb
Host smart-25aa6e1c-f086-4636-a0c7-75286eafaab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884866827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3884866827
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3373946908
Short name T417
Test name
Test status
Simulation time 59808684 ps
CPU time 1.49 seconds
Started Jul 30 06:45:57 PM PDT 24
Finished Jul 30 06:45:59 PM PDT 24
Peak memory 218600 kb
Host smart-fddad4ea-76b0-4731-9eba-457a0810901a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373946908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3373946908
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.1393218318
Short name T618
Test name
Test status
Simulation time 27975423 ps
CPU time 1.22 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 219468 kb
Host smart-b1221140-2366-457d-b636-9a6aaaff50c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393218318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1393218318
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.2236458856
Short name T957
Test name
Test status
Simulation time 38800056 ps
CPU time 1.24 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 217256 kb
Host smart-9700615a-f08a-4bb3-a476-0f659d778eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236458856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2236458856
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2142589855
Short name T476
Test name
Test status
Simulation time 28337309 ps
CPU time 1.2 seconds
Started Jul 30 06:45:58 PM PDT 24
Finished Jul 30 06:45:59 PM PDT 24
Peak memory 218612 kb
Host smart-ebe9106c-98c2-4229-a274-9152b76fd875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142589855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2142589855
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.2970903467
Short name T554
Test name
Test status
Simulation time 31817957 ps
CPU time 1.42 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 218560 kb
Host smart-67679dec-af7e-4597-8867-f57cabdc553a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970903467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2970903467
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.3178456908
Short name T852
Test name
Test status
Simulation time 43324671 ps
CPU time 1.24 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 219820 kb
Host smart-49fdfda2-b29b-4c60-9c96-9a9ed79106a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178456908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.3178456908
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.1205216086
Short name T767
Test name
Test status
Simulation time 45500709 ps
CPU time 1.18 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 218836 kb
Host smart-4b264e6c-89a3-4e6f-b4b1-0c7ee56f27bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205216086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1205216086
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.4219502562
Short name T853
Test name
Test status
Simulation time 37142001 ps
CPU time 1.18 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 218580 kb
Host smart-075e3a96-5fbb-4dfe-9fca-d9b3239b0431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219502562 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.4219502562
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.1131582307
Short name T459
Test name
Test status
Simulation time 42392520 ps
CPU time 1.11 seconds
Started Jul 30 06:45:58 PM PDT 24
Finished Jul 30 06:46:00 PM PDT 24
Peak memory 218504 kb
Host smart-6cfe696c-8712-4947-8bb2-2355fb012d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131582307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1131582307
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2082843956
Short name T654
Test name
Test status
Simulation time 142733332 ps
CPU time 1.04 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 218740 kb
Host smart-c9b8792b-088a-4aab-bb11-e98ce8d386f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082843956 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2082843956
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.4241709439
Short name T66
Test name
Test status
Simulation time 75141895 ps
CPU time 1.29 seconds
Started Jul 30 06:45:58 PM PDT 24
Finished Jul 30 06:45:59 PM PDT 24
Peak memory 219076 kb
Host smart-e7e9d731-b27e-4cdc-a3b8-0357977ff135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241709439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.4241709439
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.272216012
Short name T948
Test name
Test status
Simulation time 24452908 ps
CPU time 1.17 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 218604 kb
Host smart-fa65bf36-d87b-4b83-9f45-074476968d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272216012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.272216012
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3910459828
Short name T474
Test name
Test status
Simulation time 23518201 ps
CPU time 1.06 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 214956 kb
Host smart-6af389c7-7b47-47ee-b83d-136f81d1d28d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910459828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3910459828
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3205428982
Short name T942
Test name
Test status
Simulation time 13717422 ps
CPU time 0.89 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 216024 kb
Host smart-99b2f6d7-79d6-4e48-8f41-dfd40d7b0682
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205428982 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3205428982
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.367551087
Short name T718
Test name
Test status
Simulation time 54396537 ps
CPU time 1.16 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 216940 kb
Host smart-9aee59ee-d387-4490-b92b-c4b5e0aadbe5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367551087 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.367551087
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3213099288
Short name T777
Test name
Test status
Simulation time 24135283 ps
CPU time 1.14 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 218696 kb
Host smart-bb7f9765-48f8-4f9e-90a5-e555db2f2d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213099288 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3213099288
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2773386939
Short name T934
Test name
Test status
Simulation time 48917391 ps
CPU time 1.28 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 219708 kb
Host smart-e0d6cdef-6b42-4316-9fcd-ce833be18d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773386939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2773386939
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3566448611
Short name T933
Test name
Test status
Simulation time 23102881 ps
CPU time 1.17 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 215556 kb
Host smart-c0b0cccf-c4fe-4acc-a487-848c4739880b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566448611 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3566448611
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3499527545
Short name T240
Test name
Test status
Simulation time 25355764 ps
CPU time 0.94 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 215256 kb
Host smart-696694b2-c1ef-470a-a114-52988fb62fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499527545 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3499527545
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1475890540
Short name T454
Test name
Test status
Simulation time 154497239 ps
CPU time 3.44 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:31 PM PDT 24
Peak memory 219864 kb
Host smart-873f2ef0-076b-4e66-8112-5ebbc9af598d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475890540 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1475890540
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2227312081
Short name T513
Test name
Test status
Simulation time 218792833847 ps
CPU time 1117.72 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 07:03:04 PM PDT 24
Peak memory 223664 kb
Host smart-605261e9-1b0e-42ae-9a03-a13477683eae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227312081 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2227312081
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.3716226535
Short name T687
Test name
Test status
Simulation time 28289671 ps
CPU time 1.19 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 220844 kb
Host smart-f15f8590-ab86-482d-b0ee-d29f34753c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716226535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.3716226535
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.4283290756
Short name T414
Test name
Test status
Simulation time 250094707 ps
CPU time 1.67 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 218792 kb
Host smart-bb597862-44fd-49bd-a79f-1aaadd207005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283290756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.4283290756
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.963962091
Short name T478
Test name
Test status
Simulation time 56010545 ps
CPU time 1.3 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 215724 kb
Host smart-64b088a4-4d07-4627-962a-29b9db65beff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963962091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.963962091
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3858798503
Short name T408
Test name
Test status
Simulation time 53505342 ps
CPU time 0.99 seconds
Started Jul 30 06:46:02 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 217496 kb
Host smart-22339298-87a5-4dc8-a5b4-505a4c4284cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858798503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3858798503
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.1970040106
Short name T633
Test name
Test status
Simulation time 48781789 ps
CPU time 1.15 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 215684 kb
Host smart-1cd60d54-34f1-477d-9712-27ecc20b9ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970040106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.1970040106
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.1143465282
Short name T399
Test name
Test status
Simulation time 157401793 ps
CPU time 1.6 seconds
Started Jul 30 06:45:57 PM PDT 24
Finished Jul 30 06:45:59 PM PDT 24
Peak memory 218660 kb
Host smart-c91e5d2a-006e-4658-8d26-ec5c1d840b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143465282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1143465282
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1008760642
Short name T821
Test name
Test status
Simulation time 34368481 ps
CPU time 1.24 seconds
Started Jul 30 06:46:02 PM PDT 24
Finished Jul 30 06:46:03 PM PDT 24
Peak memory 219896 kb
Host smart-f698c4d0-7674-42ff-a0d4-a84c3c970d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008760642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1008760642
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.3841501557
Short name T571
Test name
Test status
Simulation time 63385388 ps
CPU time 0.99 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 217200 kb
Host smart-f618652c-3c9e-4456-a2f3-d8369ddc368c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841501557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3841501557
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.2324421544
Short name T139
Test name
Test status
Simulation time 35323167 ps
CPU time 1.11 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 219948 kb
Host smart-075fd501-51ef-4f0f-afe3-e442713705c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324421544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2324421544
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.2376712857
Short name T693
Test name
Test status
Simulation time 37185406 ps
CPU time 1.33 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:03 PM PDT 24
Peak memory 219436 kb
Host smart-a02649f2-9bbd-45dc-beb9-7aa3969625cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376712857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2376712857
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.643450731
Short name T311
Test name
Test status
Simulation time 26924517 ps
CPU time 1.2 seconds
Started Jul 30 06:45:59 PM PDT 24
Finished Jul 30 06:46:00 PM PDT 24
Peak memory 218544 kb
Host smart-1d902d1c-0a22-4860-92fa-c8c5e4b89aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643450731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.643450731
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.672241407
Short name T642
Test name
Test status
Simulation time 18406852 ps
CPU time 1.06 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 217260 kb
Host smart-f14eb249-b597-476c-8ea2-653ba035f6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672241407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.672241407
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2208678192
Short name T755
Test name
Test status
Simulation time 39228890 ps
CPU time 1.2 seconds
Started Jul 30 06:46:04 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 220516 kb
Host smart-627b0979-e6fd-448a-b999-8eb64868d6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208678192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2208678192
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.1552463353
Short name T475
Test name
Test status
Simulation time 51913556 ps
CPU time 1.25 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:16 PM PDT 24
Peak memory 219192 kb
Host smart-0275a3e2-d75a-469e-80e1-8fb3c8fe6118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552463353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1552463353
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1115813603
Short name T202
Test name
Test status
Simulation time 48187129 ps
CPU time 1.25 seconds
Started Jul 30 06:46:04 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 219044 kb
Host smart-b9c5caeb-b21f-49a9-a5d9-17c207315f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115813603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1115813603
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.3283961512
Short name T975
Test name
Test status
Simulation time 431991147 ps
CPU time 1.17 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 217300 kb
Host smart-a73760f7-88b0-4254-a2fa-425492479b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283961512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3283961512
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.3605928858
Short name T201
Test name
Test status
Simulation time 38135832 ps
CPU time 1.13 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:02 PM PDT 24
Peak memory 219160 kb
Host smart-97e3606e-c740-4228-aefc-d7543e808a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605928858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.3605928858
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.1838539139
Short name T960
Test name
Test status
Simulation time 94063068 ps
CPU time 1.22 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 217224 kb
Host smart-e800d518-cfff-4d3a-b288-d1f7194397a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838539139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1838539139
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3145229692
Short name T796
Test name
Test status
Simulation time 77712982 ps
CPU time 1.14 seconds
Started Jul 30 06:46:00 PM PDT 24
Finished Jul 30 06:46:02 PM PDT 24
Peak memory 219488 kb
Host smart-1cfa2458-a623-4f10-8f96-513cf0a3976b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145229692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3145229692
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2486591475
Short name T752
Test name
Test status
Simulation time 48142083 ps
CPU time 1.73 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 220020 kb
Host smart-c1572b86-a75b-4d41-850f-943242933ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486591475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2486591475
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3193393995
Short name T563
Test name
Test status
Simulation time 43981896 ps
CPU time 1.22 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 218612 kb
Host smart-5c403e51-9fbc-4358-86a1-6ffb85611464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193393995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3193393995
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2331009885
Short name T402
Test name
Test status
Simulation time 44567961 ps
CPU time 0.87 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 214936 kb
Host smart-29b472f6-5dd8-4513-b43f-6018576a8179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331009885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2331009885
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2184099992
Short name T71
Test name
Test status
Simulation time 13337669 ps
CPU time 0.88 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 216092 kb
Host smart-f53dddb1-cb13-4efb-9968-fad20f5b93a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184099992 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2184099992
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.391527126
Short name T152
Test name
Test status
Simulation time 59200145 ps
CPU time 0.97 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 216908 kb
Host smart-9dd9d3a2-6bd9-4b14-bc07-8da1ad372100
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391527126 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.391527126
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1086263067
Short name T986
Test name
Test status
Simulation time 33129698 ps
CPU time 1.1 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 219688 kb
Host smart-27d29b9a-363e-46f1-b824-4ca2095a1131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086263067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1086263067
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.4261828096
Short name T647
Test name
Test status
Simulation time 57788619 ps
CPU time 1.08 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 217156 kb
Host smart-7c3ce4f2-1f6c-4f57-9912-979755cebd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261828096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.4261828096
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.2638780832
Short name T958
Test name
Test status
Simulation time 29589620 ps
CPU time 1.02 seconds
Started Jul 30 06:44:27 PM PDT 24
Finished Jul 30 06:44:29 PM PDT 24
Peak memory 215336 kb
Host smart-7fae50ec-4bf6-4568-a42d-27c1938b445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638780832 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2638780832
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.686960950
Short name T569
Test name
Test status
Simulation time 136764955 ps
CPU time 1.75 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 217204 kb
Host smart-03159b33-d9b8-4d6c-8456-41b4c5589222
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686960950 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.686960950
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1596282155
Short name T932
Test name
Test status
Simulation time 307038450488 ps
CPU time 1641.95 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 07:11:48 PM PDT 24
Peak memory 225788 kb
Host smart-c6362549-9622-412f-a9b6-67f4c154beb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596282155 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1596282155
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.1241989147
Short name T685
Test name
Test status
Simulation time 75444816 ps
CPU time 1.34 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 215668 kb
Host smart-433d0cb4-47b8-462a-be60-2d327c97f5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241989147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1241989147
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3252207449
Short name T794
Test name
Test status
Simulation time 36868872 ps
CPU time 1.47 seconds
Started Jul 30 06:45:58 PM PDT 24
Finished Jul 30 06:46:00 PM PDT 24
Peak memory 217364 kb
Host smart-b7a1e48e-1947-4839-9160-de3492b6eafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252207449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3252207449
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.1689320347
Short name T354
Test name
Test status
Simulation time 64913154 ps
CPU time 1.14 seconds
Started Jul 30 06:45:58 PM PDT 24
Finished Jul 30 06:45:59 PM PDT 24
Peak memory 218916 kb
Host smart-c0d9cbe2-0dd6-4868-80e7-6327533e5b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689320347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1689320347
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2723470775
Short name T561
Test name
Test status
Simulation time 41459864 ps
CPU time 1.26 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 217184 kb
Host smart-e446fe4d-7122-4e6c-897f-450baa92dc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723470775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2723470775
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.1442456503
Short name T743
Test name
Test status
Simulation time 29236596 ps
CPU time 1.33 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 215816 kb
Host smart-e194a912-4929-4493-a0fe-8961ada63464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442456503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.1442456503
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.2990372457
Short name T455
Test name
Test status
Simulation time 52656532 ps
CPU time 1.21 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 217244 kb
Host smart-03bc845a-ad5b-479f-91cc-77d1815554bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990372457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2990372457
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.3456673905
Short name T289
Test name
Test status
Simulation time 29723314 ps
CPU time 1.27 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 220552 kb
Host smart-0baf8c42-858d-4aa4-b082-907de93877a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456673905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.3456673905
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.1011737777
Short name T639
Test name
Test status
Simulation time 44019347 ps
CPU time 1.35 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 218764 kb
Host smart-1fa19f2e-752f-49a9-a804-20a104e61d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011737777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1011737777
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.1597268616
Short name T540
Test name
Test status
Simulation time 143981204 ps
CPU time 1.16 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 218508 kb
Host smart-e118aa0e-c42f-407b-9c10-5cda4e5ead92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597268616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.1597268616
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3779197522
Short name T412
Test name
Test status
Simulation time 34828680 ps
CPU time 1.59 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 218548 kb
Host smart-0d6b4658-c158-4457-84dd-0dbc45c2671f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779197522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3779197522
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.1093606416
Short name T652
Test name
Test status
Simulation time 24520704 ps
CPU time 1.18 seconds
Started Jul 30 06:46:00 PM PDT 24
Finished Jul 30 06:46:01 PM PDT 24
Peak memory 219104 kb
Host smart-4861fc91-f499-4dbb-9e93-70f02940021c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093606416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1093606416
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.2138346153
Short name T63
Test name
Test status
Simulation time 39678316 ps
CPU time 1.04 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 217476 kb
Host smart-6e46b619-f03d-43a1-aabe-09314b83e646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138346153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2138346153
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.1756124512
Short name T811
Test name
Test status
Simulation time 126896508 ps
CPU time 1.1 seconds
Started Jul 30 06:46:04 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 220548 kb
Host smart-cc5c74b0-9e7a-4dd3-8cb4-bdfcb72a6f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756124512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.1756124512
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.2684309068
Short name T380
Test name
Test status
Simulation time 46304447 ps
CPU time 1.43 seconds
Started Jul 30 06:45:54 PM PDT 24
Finished Jul 30 06:45:56 PM PDT 24
Peak memory 217372 kb
Host smart-68940855-477d-443a-9cb7-2ba260e93e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684309068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2684309068
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.2162447459
Short name T792
Test name
Test status
Simulation time 43354532 ps
CPU time 1.14 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 218692 kb
Host smart-630c0284-dcbf-48c4-bd51-d97fbaeb9cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162447459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2162447459
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3374409432
Short name T651
Test name
Test status
Simulation time 123848836 ps
CPU time 1.22 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 217456 kb
Host smart-47d46de0-55a1-46b3-8208-993f17017eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374409432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3374409432
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.625138970
Short name T165
Test name
Test status
Simulation time 25550198 ps
CPU time 1.17 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:02 PM PDT 24
Peak memory 220652 kb
Host smart-3347f97c-09ca-4253-b957-cdc2fd4bc993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625138970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.625138970
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.1678091992
Short name T387
Test name
Test status
Simulation time 35431035 ps
CPU time 1.26 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 217464 kb
Host smart-86c21fac-85d8-4237-a088-4aea27d64fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678091992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1678091992
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.409586377
Short name T580
Test name
Test status
Simulation time 21729655 ps
CPU time 1.15 seconds
Started Jul 30 06:44:09 PM PDT 24
Finished Jul 30 06:44:11 PM PDT 24
Peak memory 218704 kb
Host smart-28f2878a-c7dc-488a-918e-e950ffd1f05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409586377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.409586377
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3627684871
Short name T626
Test name
Test status
Simulation time 32019179 ps
CPU time 0.77 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 206296 kb
Host smart-9ce1dd3d-bdfb-4e3a-900a-675aa9d4fdd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627684871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3627684871
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2756949608
Short name T719
Test name
Test status
Simulation time 110076387 ps
CPU time 1.19 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 216952 kb
Host smart-47667a35-77e0-42fc-8810-3a52a2fa1120
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756949608 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2756949608
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1825853256
Short name T122
Test name
Test status
Simulation time 21920931 ps
CPU time 1.1 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 218648 kb
Host smart-388e5f92-b195-41a3-bbfe-0ee14b5df6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825853256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1825853256
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1575003679
Short name T711
Test name
Test status
Simulation time 55417149 ps
CPU time 1.1 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 219056 kb
Host smart-a17025aa-11df-4887-ab7d-ef7131fdaec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575003679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1575003679
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1892005854
Short name T85
Test name
Test status
Simulation time 30557964 ps
CPU time 0.86 seconds
Started Jul 30 06:44:18 PM PDT 24
Finished Jul 30 06:44:19 PM PDT 24
Peak memory 215860 kb
Host smart-896270f2-75cc-4741-80da-898150bcb7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892005854 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1892005854
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2221901832
Short name T605
Test name
Test status
Simulation time 36621844 ps
CPU time 0.85 seconds
Started Jul 30 06:44:17 PM PDT 24
Finished Jul 30 06:44:18 PM PDT 24
Peak memory 207140 kb
Host smart-c07ba811-34d4-4d2d-8c55-94622fbf3415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221901832 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2221901832
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.2780240398
Short name T342
Test name
Test status
Simulation time 50755482 ps
CPU time 0.88 seconds
Started Jul 30 06:44:12 PM PDT 24
Finished Jul 30 06:44:13 PM PDT 24
Peak memory 215264 kb
Host smart-dd5a5240-a0ea-4ce6-878f-6be03ead265d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780240398 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2780240398
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3888185983
Short name T253
Test name
Test status
Simulation time 741419496 ps
CPU time 4.04 seconds
Started Jul 30 06:44:23 PM PDT 24
Finished Jul 30 06:44:29 PM PDT 24
Peak memory 217164 kb
Host smart-35c2410b-f3b0-4d66-8cf7-20ee1e25cebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888185983 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3888185983
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2338096557
Short name T772
Test name
Test status
Simulation time 217953086155 ps
CPU time 1104.35 seconds
Started Jul 30 06:44:14 PM PDT 24
Finished Jul 30 07:02:39 PM PDT 24
Peak memory 223792 kb
Host smart-ae74bd2f-9601-4e3e-8cc6-0c45e877f9cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338096557 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2338096557
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1144060622
Short name T906
Test name
Test status
Simulation time 141126089 ps
CPU time 1.15 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 220636 kb
Host smart-6b2cfeed-d84c-41fb-9df3-33d627e29d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144060622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1144060622
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.501066882
Short name T373
Test name
Test status
Simulation time 13178895 ps
CPU time 0.87 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 206652 kb
Host smart-bf7dc414-981c-4a41-af56-cc8b2b4ffbad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501066882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.501066882
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.918721345
Short name T918
Test name
Test status
Simulation time 127618223 ps
CPU time 1.04 seconds
Started Jul 30 06:44:23 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 216784 kb
Host smart-91b972a9-cfd1-492e-8d30-03851e3f71a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918721345 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.918721345
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_genbits.1590429978
Short name T552
Test name
Test status
Simulation time 39820580 ps
CPU time 1.4 seconds
Started Jul 30 06:44:14 PM PDT 24
Finished Jul 30 06:44:16 PM PDT 24
Peak memory 217228 kb
Host smart-db64b36c-bd75-407a-bf31-c9e27e6f4bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590429978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1590429978
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_smoke.771588525
Short name T376
Test name
Test status
Simulation time 47390377 ps
CPU time 0.92 seconds
Started Jul 30 06:44:23 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 215304 kb
Host smart-dfb9d68d-e1f2-44d9-9a25-21f89d67a890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771588525 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.771588525
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1264098608
Short name T99
Test name
Test status
Simulation time 236394369 ps
CPU time 1.42 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 215444 kb
Host smart-e7940f5f-e858-4df6-882f-908c5e6ec66d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264098608 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1264098608
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2607550914
Short name T239
Test name
Test status
Simulation time 30419102050 ps
CPU time 627.62 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:54:55 PM PDT 24
Peak memory 217812 kb
Host smart-51fc4c1a-9d94-4692-bfb3-daff0b9af282
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607550914 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2607550914
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2591350055
Short name T888
Test name
Test status
Simulation time 71982630 ps
CPU time 1.2 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:04 PM PDT 24
Peak memory 219948 kb
Host smart-df189349-6b7d-46a8-bda0-7ab0aee9d519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591350055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2591350055
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.543599819
Short name T655
Test name
Test status
Simulation time 37033260 ps
CPU time 1.46 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 218368 kb
Host smart-6b4327b4-4b35-4e71-9d6d-1059839551ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543599819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.543599819
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3129695719
Short name T943
Test name
Test status
Simulation time 82746059 ps
CPU time 1.13 seconds
Started Jul 30 06:46:17 PM PDT 24
Finished Jul 30 06:46:19 PM PDT 24
Peak memory 217256 kb
Host smart-97af41be-c18c-4c7c-bf38-3cc4a0cbdacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129695719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3129695719
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1213544179
Short name T241
Test name
Test status
Simulation time 35281270 ps
CPU time 1.26 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 217188 kb
Host smart-db218568-6cb3-414a-806a-564ec34b1816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213544179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1213544179
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2964107517
Short name T446
Test name
Test status
Simulation time 620238629 ps
CPU time 4.96 seconds
Started Jul 30 06:46:02 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 219864 kb
Host smart-f0d82d80-4a2a-4a32-87c3-9577187ee7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964107517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2964107517
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.2989544849
Short name T344
Test name
Test status
Simulation time 28381140 ps
CPU time 1.22 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 218484 kb
Host smart-b395f7ed-9153-4121-9ab6-e4770c0e19d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989544849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2989544849
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2378403889
Short name T599
Test name
Test status
Simulation time 131999452 ps
CPU time 1.5 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 218988 kb
Host smart-554cc41e-4f79-4b73-b44e-d31b5700c8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378403889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2378403889
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2138063489
Short name T332
Test name
Test status
Simulation time 103514753 ps
CPU time 1.2 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:12 PM PDT 24
Peak memory 218400 kb
Host smart-520ef968-5051-444e-bdac-bd0455d03d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138063489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2138063489
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1066880746
Short name T11
Test name
Test status
Simulation time 60393768 ps
CPU time 1.37 seconds
Started Jul 30 06:46:04 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 219924 kb
Host smart-521f4c51-434a-45cb-bce5-643ac0cac88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066880746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1066880746
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2488511279
Short name T163
Test name
Test status
Simulation time 26219213 ps
CPU time 1.16 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 218720 kb
Host smart-fac2dbe0-0057-49f5-b730-08d8b2828bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488511279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2488511279
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1619528423
Short name T432
Test name
Test status
Simulation time 11341203 ps
CPU time 0.82 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 206456 kb
Host smart-2c7a20d5-b72f-4207-8830-4f9dfce003a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619528423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1619528423
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.282311887
Short name T917
Test name
Test status
Simulation time 17274012 ps
CPU time 0.78 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 216088 kb
Host smart-72e7d8d4-a8f7-4065-9629-8df6aa6cacde
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282311887 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.282311887
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1399947705
Short name T510
Test name
Test status
Simulation time 175500528 ps
CPU time 1.07 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 215572 kb
Host smart-01c63fff-0c98-4778-ae98-98d7478db01d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399947705 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1399947705
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_intr.796449433
Short name T47
Test name
Test status
Simulation time 24798211 ps
CPU time 1.01 seconds
Started Jul 30 06:44:23 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 224036 kb
Host smart-3bf90800-a3cc-4bc1-854a-7c7223f25abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796449433 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.796449433
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.4272540304
Short name T363
Test name
Test status
Simulation time 28878590 ps
CPU time 0.91 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 215256 kb
Host smart-b55ee036-db92-4eea-a090-3af96174161f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272540304 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.4272540304
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3992141407
Short name T641
Test name
Test status
Simulation time 988278871 ps
CPU time 5.2 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:29 PM PDT 24
Peak memory 217224 kb
Host smart-6a75aca6-6155-4a86-b928-a391ac06501a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992141407 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3992141407
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.640901103
Short name T773
Test name
Test status
Simulation time 29008459541 ps
CPU time 337.71 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:50:05 PM PDT 24
Peak memory 216624 kb
Host smart-9619e36f-3f71-45d8-ad9b-412df4fe2880
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640901103 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.640901103
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.718335080
Short name T749
Test name
Test status
Simulation time 88214218 ps
CPU time 1.16 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 217324 kb
Host smart-aa744a73-d74f-40df-a0f4-1105be13e0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718335080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.718335080
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3967187003
Short name T369
Test name
Test status
Simulation time 52416030 ps
CPU time 1.36 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 218384 kb
Host smart-f3684277-fb55-49e0-9080-42d83ff2612f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967187003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3967187003
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1052919907
Short name T883
Test name
Test status
Simulation time 49004937 ps
CPU time 1.6 seconds
Started Jul 30 06:46:21 PM PDT 24
Finished Jul 30 06:46:23 PM PDT 24
Peak memory 218504 kb
Host smart-2558ddb6-75d8-4017-8eef-a4b98e3295b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052919907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1052919907
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1834012799
Short name T579
Test name
Test status
Simulation time 48984906 ps
CPU time 1.64 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:16 PM PDT 24
Peak memory 218576 kb
Host smart-f106c852-8b84-484b-b7ce-d3506af65588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834012799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1834012799
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3936287617
Short name T501
Test name
Test status
Simulation time 40796713 ps
CPU time 1.33 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 219828 kb
Host smart-d3fdb6e4-a42f-4b56-a219-7f9edb86835e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936287617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3936287617
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1549407810
Short name T855
Test name
Test status
Simulation time 169462343 ps
CPU time 1.03 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 217492 kb
Host smart-2dcae4bd-6517-45a1-b687-cfb2fbd78edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549407810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1549407810
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1418145734
Short name T841
Test name
Test status
Simulation time 114950241 ps
CPU time 1.17 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:12 PM PDT 24
Peak memory 218888 kb
Host smart-ca81b8bc-44c5-4de8-a9ad-ed4cbdf055a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418145734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1418145734
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1544579589
Short name T573
Test name
Test status
Simulation time 55125216 ps
CPU time 1.23 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 215308 kb
Host smart-d633c8eb-d2d4-477f-836f-cb143a6456fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544579589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1544579589
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.423628798
Short name T296
Test name
Test status
Simulation time 80822620 ps
CPU time 1.15 seconds
Started Jul 30 06:46:22 PM PDT 24
Finished Jul 30 06:46:23 PM PDT 24
Peak memory 217192 kb
Host smart-152aa419-85ca-47f4-8700-26efbb2eb22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423628798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.423628798
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3548984600
Short name T523
Test name
Test status
Simulation time 54874438 ps
CPU time 1.79 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 218536 kb
Host smart-a55b906b-5ef4-4837-9c8f-e83ed5088ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548984600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3548984600
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3564960030
Short name T581
Test name
Test status
Simulation time 25849711 ps
CPU time 1.19 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 218480 kb
Host smart-b81ea9c4-7673-4f5a-a8ec-96652a9a6f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564960030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3564960030
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1919997192
Short name T624
Test name
Test status
Simulation time 44276790 ps
CPU time 0.88 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 206672 kb
Host smart-c60c1641-f44c-452e-90b4-5ff76617b185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919997192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1919997192
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3810513586
Short name T120
Test name
Test status
Simulation time 49813231 ps
CPU time 0.81 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 216252 kb
Host smart-34381fe2-f19b-446a-8e1a-1708d2d11022
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810513586 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3810513586
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2686195992
Short name T832
Test name
Test status
Simulation time 79023913 ps
CPU time 0.99 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 218188 kb
Host smart-4e4e40ad-640b-4654-9f09-5d0e42de2827
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686195992 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2686195992
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3411585173
Short name T203
Test name
Test status
Simulation time 32915997 ps
CPU time 0.88 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 218292 kb
Host smart-36a10912-3746-4fed-93f7-d67a7b971de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411585173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3411585173
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3494343082
Short name T726
Test name
Test status
Simulation time 173010435 ps
CPU time 1.16 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 217356 kb
Host smart-b429ab5d-e536-42a9-9caa-7c6ae9623017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494343082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3494343082
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3446780365
Short name T727
Test name
Test status
Simulation time 20850410 ps
CPU time 1.23 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 223996 kb
Host smart-9c260fef-860c-49ff-a08c-0de181a4d96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446780365 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3446780365
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1582952898
Short name T910
Test name
Test status
Simulation time 77164742 ps
CPU time 0.92 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 215276 kb
Host smart-e60dc1ee-ca7a-4dc1-a623-f9848e6b77a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582952898 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1582952898
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2063653966
Short name T845
Test name
Test status
Simulation time 255766251 ps
CPU time 5.19 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:30 PM PDT 24
Peak memory 217280 kb
Host smart-e4ca84ef-caf1-4845-8ad6-fcd12ee2dda4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063653966 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2063653966
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1929219902
Short name T648
Test name
Test status
Simulation time 45592056646 ps
CPU time 561.98 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:53:49 PM PDT 24
Peak memory 218340 kb
Host smart-05f88294-d30e-4d6b-88c2-f24e0a29d309
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929219902 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1929219902
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/221.edn_genbits.128878790
Short name T458
Test name
Test status
Simulation time 166592916 ps
CPU time 2.63 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:15 PM PDT 24
Peak memory 218572 kb
Host smart-d30b13b2-56c9-483e-beb1-a443756fc380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128878790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.128878790
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2051483414
Short name T951
Test name
Test status
Simulation time 154587208 ps
CPU time 2.3 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 219400 kb
Host smart-e0259922-b683-41c0-8b14-e48ea61f0300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051483414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2051483414
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2001762939
Short name T577
Test name
Test status
Simulation time 71064706 ps
CPU time 1.17 seconds
Started Jul 30 06:46:02 PM PDT 24
Finished Jul 30 06:46:03 PM PDT 24
Peak memory 217728 kb
Host smart-48579785-b6c6-4e7a-8f10-abdb7d329875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001762939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2001762939
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2189923060
Short name T491
Test name
Test status
Simulation time 115275309 ps
CPU time 2.53 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 220064 kb
Host smart-7678729e-5d56-4800-b6d6-d85d559a3ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189923060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2189923060
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.257068922
Short name T612
Test name
Test status
Simulation time 40391501 ps
CPU time 1.63 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 220000 kb
Host smart-43f4b8a6-d657-4524-b063-9d2392162ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257068922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.257068922
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3790635283
Short name T325
Test name
Test status
Simulation time 36265862 ps
CPU time 1.16 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 218596 kb
Host smart-f014dc49-1c6e-4cca-a313-9100a45b5a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790635283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3790635283
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3888825689
Short name T805
Test name
Test status
Simulation time 77216389 ps
CPU time 1.02 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 217744 kb
Host smart-d5a10fa0-ca9c-4953-94a6-4418fefa15c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888825689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3888825689
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3310388369
Short name T558
Test name
Test status
Simulation time 592996930 ps
CPU time 4.93 seconds
Started Jul 30 06:46:00 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 219084 kb
Host smart-09818c06-12b7-435b-b56a-fa398ffc5862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310388369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3310388369
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.561771934
Short name T925
Test name
Test status
Simulation time 24671312 ps
CPU time 1.17 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 220468 kb
Host smart-7d0ee690-689a-4ebb-a05e-3225511dbec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561771934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.561771934
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2979043075
Short name T435
Test name
Test status
Simulation time 19223597 ps
CPU time 0.83 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 206704 kb
Host smart-42b9d6db-7cc9-4b8b-8a00-d2709eca5062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979043075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2979043075
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.4183810067
Short name T776
Test name
Test status
Simulation time 38226194 ps
CPU time 0.81 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 216208 kb
Host smart-387b75b0-03d5-4561-9b1d-044f576f60ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183810067 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.4183810067
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.488975166
Short name T534
Test name
Test status
Simulation time 244628273 ps
CPU time 1.06 seconds
Started Jul 30 06:44:23 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 219784 kb
Host smart-9c6f6ad0-d01d-4a67-9f56-ddc95e0e5e50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488975166 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.488975166
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.429786476
Short name T127
Test name
Test status
Simulation time 29895036 ps
CPU time 0.86 seconds
Started Jul 30 06:44:33 PM PDT 24
Finished Jul 30 06:44:34 PM PDT 24
Peak memory 218456 kb
Host smart-814ceae1-d078-453d-bc0e-7e559f139135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429786476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.429786476
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3572220036
Short name T295
Test name
Test status
Simulation time 50921136 ps
CPU time 1.74 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 218248 kb
Host smart-23e6b52f-9958-4da0-9688-2574624ae7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572220036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3572220036
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.3531255029
Short name T434
Test name
Test status
Simulation time 17521226 ps
CPU time 0.92 seconds
Started Jul 30 06:44:27 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 215252 kb
Host smart-ec133251-6ade-4ef2-bf17-7f9512f37372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531255029 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3531255029
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.831674458
Short name T698
Test name
Test status
Simulation time 361564426 ps
CPU time 6.06 seconds
Started Jul 30 06:44:27 PM PDT 24
Finished Jul 30 06:44:34 PM PDT 24
Peak memory 217432 kb
Host smart-79c8cc3a-4f31-4964-8710-00be30167130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831674458 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.831674458
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1904516524
Short name T517
Test name
Test status
Simulation time 13956822045 ps
CPU time 322.16 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:49:49 PM PDT 24
Peak memory 222992 kb
Host smart-159f850d-35c5-4856-8bbc-a05a201dd5c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904516524 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1904516524
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2293422412
Short name T65
Test name
Test status
Simulation time 31019130 ps
CPU time 1.28 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 217256 kb
Host smart-93c7078d-f17f-440f-9758-758c59ad6ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293422412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2293422412
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3335313755
Short name T928
Test name
Test status
Simulation time 54768325 ps
CPU time 1.18 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 217160 kb
Host smart-55dfe35c-7ea0-4bc2-95f1-bce2a0a58f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335313755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3335313755
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1141523062
Short name T594
Test name
Test status
Simulation time 69231031 ps
CPU time 1.35 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 218632 kb
Host smart-ed33da3d-a540-4c9e-bc74-3ba93532597c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141523062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1141523062
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1057340132
Short name T77
Test name
Test status
Simulation time 59582378 ps
CPU time 1.31 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 218856 kb
Host smart-bdfc3fe7-602c-464a-944f-aad92de82b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057340132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1057340132
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2609836158
Short name T631
Test name
Test status
Simulation time 75131025 ps
CPU time 2.78 seconds
Started Jul 30 06:46:19 PM PDT 24
Finished Jul 30 06:46:22 PM PDT 24
Peak memory 219524 kb
Host smart-b8a36728-a43e-4cb3-a7af-b17cc3eee36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609836158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2609836158
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1896176614
Short name T323
Test name
Test status
Simulation time 55990097 ps
CPU time 1.29 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 218368 kb
Host smart-ce67869a-4ae4-4271-8d40-c50b13dd9918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896176614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1896176614
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1279815631
Short name T736
Test name
Test status
Simulation time 41195603 ps
CPU time 1.75 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 218800 kb
Host smart-d94017d3-1c8c-4ca4-ab22-db5371d61e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279815631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1279815631
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.741655728
Short name T636
Test name
Test status
Simulation time 72528796 ps
CPU time 1.1 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:04 PM PDT 24
Peak memory 215312 kb
Host smart-843e33ab-3ed7-4dcd-8cad-cf391b0757e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741655728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.741655728
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2654237302
Short name T744
Test name
Test status
Simulation time 67119325 ps
CPU time 1.46 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:12 PM PDT 24
Peak memory 216732 kb
Host smart-bb91a4b3-d0b2-43d0-9598-873151e33503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654237302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2654237302
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2710220038
Short name T824
Test name
Test status
Simulation time 30443525 ps
CPU time 1.31 seconds
Started Jul 30 06:44:32 PM PDT 24
Finished Jul 30 06:44:33 PM PDT 24
Peak memory 219232 kb
Host smart-5cea439a-9370-4eff-b73b-921b3ff71ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710220038 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2710220038
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.162330495
Short name T733
Test name
Test status
Simulation time 105562373 ps
CPU time 0.81 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 206572 kb
Host smart-33c1966d-3602-487d-844c-d01cad9b24a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162330495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.162330495
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1943213669
Short name T190
Test name
Test status
Simulation time 24039799 ps
CPU time 0.88 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 216600 kb
Host smart-45e1addc-2fb0-4bc8-a62d-bab5dc3126ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943213669 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1943213669
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3063280157
Short name T762
Test name
Test status
Simulation time 45444000 ps
CPU time 1.38 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 217008 kb
Host smart-43ed4683-4dd0-4182-ba9a-f82ab675e71a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063280157 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3063280157
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.662932308
Short name T166
Test name
Test status
Simulation time 18982754 ps
CPU time 1.27 seconds
Started Jul 30 06:44:39 PM PDT 24
Finished Jul 30 06:44:40 PM PDT 24
Peak memory 224112 kb
Host smart-c6a0fd2c-e789-4c20-805d-a64be0c51d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662932308 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.662932308
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1932137708
Short name T37
Test name
Test status
Simulation time 145928772 ps
CPU time 2.04 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:29 PM PDT 24
Peak memory 218692 kb
Host smart-b9c91977-fbfa-4609-8f6d-9614ce0dc1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932137708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1932137708
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.656490038
Short name T86
Test name
Test status
Simulation time 33441087 ps
CPU time 0.83 seconds
Started Jul 30 06:44:23 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 215496 kb
Host smart-ee11f9df-2aca-4cac-adf8-235dd01db448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656490038 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.656490038
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.162907099
Short name T919
Test name
Test status
Simulation time 15911056 ps
CPU time 0.93 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 207096 kb
Host smart-c085daec-45a0-46a4-a119-c37de4febaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162907099 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.162907099
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.658013291
Short name T336
Test name
Test status
Simulation time 513020807 ps
CPU time 3.67 seconds
Started Jul 30 06:44:41 PM PDT 24
Finished Jul 30 06:44:45 PM PDT 24
Peak memory 215264 kb
Host smart-b0a6238c-1b28-4ac9-999e-3763da1e4196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658013291 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.658013291
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3706845756
Short name T635
Test name
Test status
Simulation time 215452861690 ps
CPU time 1502.17 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 07:09:27 PM PDT 24
Peak memory 225036 kb
Host smart-5386f763-8ef1-4b7c-96ce-470da7236ec6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706845756 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3706845756
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.533811512
Short name T628
Test name
Test status
Simulation time 49605633 ps
CPU time 1.4 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:14 PM PDT 24
Peak memory 218772 kb
Host smart-34dbabbe-a9a6-4407-87aa-849c51d6cd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533811512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.533811512
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1383906435
Short name T858
Test name
Test status
Simulation time 83372315 ps
CPU time 1.07 seconds
Started Jul 30 06:46:04 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 217272 kb
Host smart-9a0e2cad-a6a9-4cb6-9165-601534a55f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383906435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1383906435
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2800211620
Short name T607
Test name
Test status
Simulation time 94339014 ps
CPU time 1.47 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 218596 kb
Host smart-55686edd-0d9f-489e-bc4c-daf5700b6ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800211620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2800211620
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.320973235
Short name T724
Test name
Test status
Simulation time 168650275 ps
CPU time 1.52 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:12 PM PDT 24
Peak memory 220144 kb
Host smart-c23cd53e-a4ce-4346-901d-f1bcff8d8abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320973235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.320973235
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2613282425
Short name T704
Test name
Test status
Simulation time 30156090 ps
CPU time 1.5 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:12 PM PDT 24
Peak memory 219892 kb
Host smart-318ee792-7a84-4317-beef-40aaf4ab8f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613282425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2613282425
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.336579893
Short name T553
Test name
Test status
Simulation time 88076425 ps
CPU time 1.67 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 218716 kb
Host smart-e11ab6f7-8680-4f76-bb94-709df95e711e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336579893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.336579893
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.346632414
Short name T830
Test name
Test status
Simulation time 47050716 ps
CPU time 1.52 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 218304 kb
Host smart-2ffca760-7303-4f5b-beb2-adbc6af61279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346632414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.346632414
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.414197073
Short name T614
Test name
Test status
Simulation time 55464976 ps
CPU time 1.25 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:14 PM PDT 24
Peak memory 219836 kb
Host smart-c98a040a-84e2-4ca3-b9c0-2e8d27364005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414197073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.414197073
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3464604774
Short name T35
Test name
Test status
Simulation time 54530208 ps
CPU time 1.51 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 218632 kb
Host smart-3ed58837-ef1b-44ec-b905-e5c4ecae9165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464604774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3464604774
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3659099328
Short name T804
Test name
Test status
Simulation time 41293767 ps
CPU time 1.17 seconds
Started Jul 30 06:44:35 PM PDT 24
Finished Jul 30 06:44:36 PM PDT 24
Peak memory 218872 kb
Host smart-d2c3e5f8-becc-47d8-86ca-878ae364f128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659099328 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3659099328
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2314529143
Short name T885
Test name
Test status
Simulation time 41767863 ps
CPU time 0.88 seconds
Started Jul 30 06:44:36 PM PDT 24
Finished Jul 30 06:44:37 PM PDT 24
Peak memory 206584 kb
Host smart-082d0c13-0b5a-4dcf-9681-ac88823e79b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314529143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2314529143
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2866442986
Short name T894
Test name
Test status
Simulation time 21467578 ps
CPU time 0.89 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 215384 kb
Host smart-232c0f96-b8e1-4919-9aca-a22db79237c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866442986 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2866442986
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1159613132
Short name T176
Test name
Test status
Simulation time 26596350 ps
CPU time 1.15 seconds
Started Jul 30 06:44:34 PM PDT 24
Finished Jul 30 06:44:35 PM PDT 24
Peak memory 216812 kb
Host smart-f74aa734-8649-45af-a33d-155e696b1a6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159613132 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1159613132
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3144602705
Short name T46
Test name
Test status
Simulation time 39059486 ps
CPU time 0.96 seconds
Started Jul 30 06:44:30 PM PDT 24
Finished Jul 30 06:44:31 PM PDT 24
Peak memory 223848 kb
Host smart-693f1ff2-43b2-43de-b76e-f587af3170ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144602705 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3144602705
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3553960431
Short name T19
Test name
Test status
Simulation time 43050644 ps
CPU time 1.49 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 219936 kb
Host smart-68e6f4a6-2855-4dfd-8966-177d6f94d0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553960431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3553960431
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2972908763
Short name T699
Test name
Test status
Simulation time 34108185 ps
CPU time 0.92 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 215356 kb
Host smart-8133ce4b-f3b6-4fd0-9303-1cee0822882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972908763 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2972908763
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1980019643
Short name T537
Test name
Test status
Simulation time 18882322 ps
CPU time 0.99 seconds
Started Jul 30 06:44:27 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 215192 kb
Host smart-9a258b18-5fa7-4d46-880e-e9591e0d3588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980019643 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1980019643
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3071315569
Short name T913
Test name
Test status
Simulation time 34501435 ps
CPU time 1.04 seconds
Started Jul 30 06:44:50 PM PDT 24
Finished Jul 30 06:44:51 PM PDT 24
Peak memory 215256 kb
Host smart-0ef7e00d-5c4f-4501-9e30-118732694672
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071315569 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3071315569
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.166521317
Short name T735
Test name
Test status
Simulation time 567696499280 ps
CPU time 1314.93 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 07:06:22 PM PDT 24
Peak memory 223896 kb
Host smart-8a134e57-d287-493a-a2a0-91b823fe9cf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166521317 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.166521317
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3050303159
Short name T702
Test name
Test status
Simulation time 41622552 ps
CPU time 1.15 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 218504 kb
Host smart-038f59f1-e422-48b2-b4c9-a848e4af375b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050303159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3050303159
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.315803136
Short name T814
Test name
Test status
Simulation time 80972860 ps
CPU time 1.68 seconds
Started Jul 30 06:46:19 PM PDT 24
Finished Jul 30 06:46:21 PM PDT 24
Peak memory 218556 kb
Host smart-968bd422-7194-451b-bea6-c33e2023e804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315803136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.315803136
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1163217691
Short name T795
Test name
Test status
Simulation time 82306737 ps
CPU time 2.49 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 220368 kb
Host smart-add6deb3-d396-4757-b6de-1e12ea85a02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163217691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1163217691
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3393668651
Short name T738
Test name
Test status
Simulation time 162813435 ps
CPU time 1.37 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 218712 kb
Host smart-1a41a67a-902d-4ca4-a15a-76a4672683d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393668651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3393668651
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.991017904
Short name T602
Test name
Test status
Simulation time 58412695 ps
CPU time 1.1 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 217292 kb
Host smart-1f9ceccd-980b-4137-82b8-60bc5f86de21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991017904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.991017904
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.81033843
Short name T886
Test name
Test status
Simulation time 71709832 ps
CPU time 1.41 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 218412 kb
Host smart-983510d2-c0a9-4a9b-b227-9be757c4d029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81033843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.81033843
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3897715557
Short name T349
Test name
Test status
Simulation time 40663425 ps
CPU time 1.12 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 217524 kb
Host smart-db4deea0-d479-445c-bda7-a37ef242171a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897715557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3897715557
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.938557841
Short name T949
Test name
Test status
Simulation time 42756589 ps
CPU time 1.39 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 218524 kb
Host smart-02e79c96-e2c8-410a-8391-d752cbb73481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938557841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.938557841
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.4070075272
Short name T442
Test name
Test status
Simulation time 36046076 ps
CPU time 1.32 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 217408 kb
Host smart-9722ece7-6509-4fd9-8fd9-5e185cfd958b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070075272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.4070075272
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.864104875
Short name T729
Test name
Test status
Simulation time 124414916 ps
CPU time 1.28 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 218872 kb
Host smart-1f5b74c2-6611-4b93-aa19-1b45802b9f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864104875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.864104875
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1608458921
Short name T405
Test name
Test status
Simulation time 40929274 ps
CPU time 1.16 seconds
Started Jul 30 06:44:49 PM PDT 24
Finished Jul 30 06:44:50 PM PDT 24
Peak memory 218524 kb
Host smart-cdc56dd2-3072-4927-a56a-7bc91502bff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608458921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1608458921
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3315349780
Short name T42
Test name
Test status
Simulation time 42960474 ps
CPU time 0.88 seconds
Started Jul 30 06:44:46 PM PDT 24
Finished Jul 30 06:44:47 PM PDT 24
Peak memory 206764 kb
Host smart-767471aa-dff8-4d93-8725-7fb7a5e6e4b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315349780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3315349780
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.852401109
Short name T206
Test name
Test status
Simulation time 14707880 ps
CPU time 0.93 seconds
Started Jul 30 06:44:37 PM PDT 24
Finished Jul 30 06:44:38 PM PDT 24
Peak memory 216488 kb
Host smart-70b3dafd-6a94-4707-8dd9-82d135cb37c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852401109 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.852401109
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2417325390
Short name T78
Test name
Test status
Simulation time 31355487 ps
CPU time 1.2 seconds
Started Jul 30 06:44:45 PM PDT 24
Finished Jul 30 06:44:47 PM PDT 24
Peak memory 217020 kb
Host smart-636b9fd8-0acd-4a6b-a25f-494fb1127eea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417325390 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2417325390
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2984225552
Short name T610
Test name
Test status
Simulation time 27533072 ps
CPU time 1 seconds
Started Jul 30 06:44:53 PM PDT 24
Finished Jul 30 06:44:54 PM PDT 24
Peak memory 223752 kb
Host smart-0e49229a-db82-4bb5-87f4-c1efc85e2cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984225552 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2984225552
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1543272494
Short name T333
Test name
Test status
Simulation time 34182814 ps
CPU time 1.4 seconds
Started Jul 30 06:44:43 PM PDT 24
Finished Jul 30 06:44:45 PM PDT 24
Peak memory 218440 kb
Host smart-fb834fc5-47ef-4c3f-909e-84636b6934a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543272494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1543272494
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2413190703
Short name T768
Test name
Test status
Simulation time 21310106 ps
CPU time 1.07 seconds
Started Jul 30 06:44:39 PM PDT 24
Finished Jul 30 06:44:40 PM PDT 24
Peak memory 215500 kb
Host smart-95a58ccc-efc4-419c-a235-6ee3284672a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413190703 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2413190703
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1564905192
Short name T880
Test name
Test status
Simulation time 24064448 ps
CPU time 0.91 seconds
Started Jul 30 06:44:42 PM PDT 24
Finished Jul 30 06:44:43 PM PDT 24
Peak memory 215240 kb
Host smart-9414ee24-12e9-4a6b-a531-733a76ab7f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564905192 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1564905192
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1707875831
Short name T248
Test name
Test status
Simulation time 1677707071 ps
CPU time 4.91 seconds
Started Jul 30 06:44:41 PM PDT 24
Finished Jul 30 06:44:46 PM PDT 24
Peak memory 217432 kb
Host smart-60f94c25-e48d-40a8-af7d-9d40dbde090b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707875831 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1707875831
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1221057213
Short name T884
Test name
Test status
Simulation time 247759505335 ps
CPU time 1630.66 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 07:11:37 PM PDT 24
Peak memory 235328 kb
Host smart-1cbd32bc-3bcc-4fc3-8afe-d34f6dd86c45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221057213 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1221057213
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.72955976
Short name T665
Test name
Test status
Simulation time 109788333 ps
CPU time 1.31 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 217332 kb
Host smart-915b2a5f-24b0-41d0-8110-9adf07660822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72955976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.72955976
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3586742479
Short name T385
Test name
Test status
Simulation time 68065312 ps
CPU time 1.39 seconds
Started Jul 30 06:45:59 PM PDT 24
Finished Jul 30 06:46:01 PM PDT 24
Peak memory 218844 kb
Host smart-11f0db4a-5629-41b5-97e2-51214a431f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586742479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3586742479
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3192364337
Short name T823
Test name
Test status
Simulation time 38443382 ps
CPU time 1.38 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 219868 kb
Host smart-f3640b74-f153-491f-8967-4adcf95c4ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192364337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3192364337
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1861080388
Short name T41
Test name
Test status
Simulation time 246278122 ps
CPU time 3.68 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:14 PM PDT 24
Peak memory 217620 kb
Host smart-4a8a7d48-a6bf-469d-87af-48396f91b92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861080388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1861080388
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.424536559
Short name T533
Test name
Test status
Simulation time 33781363 ps
CPU time 1.43 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 218124 kb
Host smart-0784c2ae-4000-4026-9087-06f1dbf0d113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424536559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.424536559
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1167050612
Short name T911
Test name
Test status
Simulation time 68041240 ps
CPU time 1.47 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 218828 kb
Host smart-8a635851-f989-4554-b375-cee9e295aee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167050612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1167050612
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3896798752
Short name T255
Test name
Test status
Simulation time 42022198 ps
CPU time 1.14 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 219788 kb
Host smart-6a328442-4431-41bf-86c8-623d8b5123e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896798752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3896798752
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.4159650066
Short name T346
Test name
Test status
Simulation time 47993928 ps
CPU time 1.08 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 217084 kb
Host smart-0e4d1b1d-ea26-4005-8b04-36ddcb5b410c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159650066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.4159650066
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2406554766
Short name T786
Test name
Test status
Simulation time 46075811 ps
CPU time 1.61 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 218616 kb
Host smart-c8591249-71c9-476f-9627-59f55c3fb908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406554766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2406554766
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3240426321
Short name T979
Test name
Test status
Simulation time 47289784 ps
CPU time 1.6 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 218520 kb
Host smart-1399523a-6294-4b98-99d0-daf34b6cb570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240426321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3240426321
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3996858609
Short name T930
Test name
Test status
Simulation time 107678302 ps
CPU time 1.22 seconds
Started Jul 30 06:44:38 PM PDT 24
Finished Jul 30 06:44:39 PM PDT 24
Peak memory 218388 kb
Host smart-9218c468-40f8-4cc8-941a-90cf3e9fbe35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996858609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3996858609
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3441675535
Short name T846
Test name
Test status
Simulation time 137164567 ps
CPU time 1.01 seconds
Started Jul 30 06:44:49 PM PDT 24
Finished Jul 30 06:44:50 PM PDT 24
Peak memory 215140 kb
Host smart-8476449c-24e5-474d-871f-ebd8b896f7ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441675535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3441675535
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2830394179
Short name T242
Test name
Test status
Simulation time 41763305 ps
CPU time 0.92 seconds
Started Jul 30 06:44:36 PM PDT 24
Finished Jul 30 06:44:37 PM PDT 24
Peak memory 216000 kb
Host smart-8f285ca7-db93-47e1-9182-f2717ea7cdb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830394179 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2830394179
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.88616652
Short name T778
Test name
Test status
Simulation time 47609328 ps
CPU time 1.43 seconds
Started Jul 30 06:44:34 PM PDT 24
Finished Jul 30 06:44:36 PM PDT 24
Peak memory 216920 kb
Host smart-62fa1b31-f87b-4b4b-8334-c332c7a87d1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88616652 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_dis
able_auto_req_mode.88616652
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.695241353
Short name T199
Test name
Test status
Simulation time 19495238 ps
CPU time 1.08 seconds
Started Jul 30 06:44:51 PM PDT 24
Finished Jul 30 06:44:52 PM PDT 24
Peak memory 218540 kb
Host smart-901e3e19-76f1-4cb7-bbed-243741d949fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695241353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.695241353
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2642181178
Short name T527
Test name
Test status
Simulation time 45114421 ps
CPU time 1.2 seconds
Started Jul 30 06:44:47 PM PDT 24
Finished Jul 30 06:44:48 PM PDT 24
Peak memory 217316 kb
Host smart-81c6929b-c8e2-410d-9a05-e94c0805f4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642181178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2642181178
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3845725112
Short name T87
Test name
Test status
Simulation time 20378590 ps
CPU time 1.09 seconds
Started Jul 30 06:44:31 PM PDT 24
Finished Jul 30 06:44:32 PM PDT 24
Peak memory 216776 kb
Host smart-1ddb1023-6400-4a86-ba14-b08f8306d957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845725112 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3845725112
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.4173006166
Short name T418
Test name
Test status
Simulation time 27277192 ps
CPU time 0.96 seconds
Started Jul 30 06:44:47 PM PDT 24
Finished Jul 30 06:44:48 PM PDT 24
Peak memory 215260 kb
Host smart-47409dee-da3b-49f6-98c4-f8b44c1d63f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173006166 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.4173006166
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3440156457
Short name T881
Test name
Test status
Simulation time 907079690 ps
CPU time 3.5 seconds
Started Jul 30 06:44:38 PM PDT 24
Finished Jul 30 06:44:41 PM PDT 24
Peak memory 217336 kb
Host smart-f4880564-d010-48be-85be-f92dc2506437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440156457 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3440156457
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3681528909
Short name T760
Test name
Test status
Simulation time 24527703027 ps
CPU time 485.12 seconds
Started Jul 30 06:44:31 PM PDT 24
Finished Jul 30 06:52:36 PM PDT 24
Peak memory 223656 kb
Host smart-82777f11-b44e-487b-a86c-957227d56f7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681528909 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3681528909
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.412048448
Short name T317
Test name
Test status
Simulation time 176084635 ps
CPU time 3.06 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:12 PM PDT 24
Peak memory 215156 kb
Host smart-b0fb9d4f-06f9-4add-aeae-276da463e994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412048448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.412048448
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3831906762
Short name T619
Test name
Test status
Simulation time 324600846 ps
CPU time 1.36 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 218772 kb
Host smart-ab14610b-786f-4386-af7c-2746287d33b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831906762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3831906762
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1965970753
Short name T588
Test name
Test status
Simulation time 58603396 ps
CPU time 1.16 seconds
Started Jul 30 06:46:23 PM PDT 24
Finished Jul 30 06:46:24 PM PDT 24
Peak memory 217380 kb
Host smart-125c17af-e0c9-4955-a83e-e57ac93ae5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965970753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1965970753
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3552158665
Short name T457
Test name
Test status
Simulation time 37060383 ps
CPU time 1.04 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 217188 kb
Host smart-18dc0653-3939-4d7a-ac6b-afaff843f97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552158665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3552158665
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.325408642
Short name T512
Test name
Test status
Simulation time 68262650 ps
CPU time 1.41 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 219980 kb
Host smart-84a1f08e-2027-4005-9381-6ef11ad0881a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325408642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.325408642
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3509053551
Short name T575
Test name
Test status
Simulation time 50120374 ps
CPU time 1.08 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:14 PM PDT 24
Peak memory 217308 kb
Host smart-9074ecc6-32f0-40de-a011-c20fbd1bfd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509053551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3509053551
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1163579757
Short name T550
Test name
Test status
Simulation time 101740232 ps
CPU time 1.07 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:04 PM PDT 24
Peak memory 217268 kb
Host smart-1358de0e-b285-4323-ba62-47e3ba66d3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163579757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1163579757
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2372138422
Short name T638
Test name
Test status
Simulation time 89106310 ps
CPU time 1.09 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:02 PM PDT 24
Peak memory 219744 kb
Host smart-10e1d0ff-d955-4833-a1ff-2829671f0200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372138422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2372138422
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.287744193
Short name T398
Test name
Test status
Simulation time 57819200 ps
CPU time 1.17 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 217348 kb
Host smart-48ba70fa-5e66-40eb-adb0-798528821fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287744193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.287744193
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2069559339
Short name T489
Test name
Test status
Simulation time 128752049 ps
CPU time 2.7 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:15 PM PDT 24
Peak memory 219676 kb
Host smart-c77354a2-2757-4aaf-a64f-76c088624373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069559339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2069559339
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1526922308
Short name T981
Test name
Test status
Simulation time 52192823 ps
CPU time 1.35 seconds
Started Jul 30 06:44:36 PM PDT 24
Finished Jul 30 06:44:37 PM PDT 24
Peak memory 215668 kb
Host smart-3d52e167-2bd6-47ab-a48d-0b6107b127bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526922308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1526922308
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3840961636
Short name T403
Test name
Test status
Simulation time 88719990 ps
CPU time 1.02 seconds
Started Jul 30 06:44:34 PM PDT 24
Finished Jul 30 06:44:35 PM PDT 24
Peak memory 206712 kb
Host smart-3759bd50-568f-4d91-a85a-fb0d18fd2c8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840961636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3840961636
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.553945137
Short name T499
Test name
Test status
Simulation time 11040019 ps
CPU time 0.88 seconds
Started Jul 30 06:44:37 PM PDT 24
Finished Jul 30 06:44:38 PM PDT 24
Peak memory 215408 kb
Host smart-67eecd54-3855-4ebc-97a8-e28edd36a42a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553945137 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.553945137
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3727770899
Short name T161
Test name
Test status
Simulation time 37576690 ps
CPU time 1.26 seconds
Started Jul 30 06:44:51 PM PDT 24
Finished Jul 30 06:44:52 PM PDT 24
Peak memory 216932 kb
Host smart-8b9b7952-cf53-470a-8e01-ab09afd9526d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727770899 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3727770899
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3052625829
Short name T49
Test name
Test status
Simulation time 39583821 ps
CPU time 1.21 seconds
Started Jul 30 06:44:36 PM PDT 24
Finished Jul 30 06:44:37 PM PDT 24
Peak memory 229724 kb
Host smart-92a77806-672f-43ee-be71-e48a4182e775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052625829 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3052625829
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.669121140
Short name T29
Test name
Test status
Simulation time 45237357 ps
CPU time 1.41 seconds
Started Jul 30 06:44:41 PM PDT 24
Finished Jul 30 06:44:43 PM PDT 24
Peak memory 217324 kb
Host smart-c664c6d9-0679-4859-a990-b5d61261fcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669121140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.669121140
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2070407544
Short name T684
Test name
Test status
Simulation time 28884855 ps
CPU time 1.02 seconds
Started Jul 30 06:44:40 PM PDT 24
Finished Jul 30 06:44:42 PM PDT 24
Peak memory 215516 kb
Host smart-fcdeb0fe-ecba-4e78-8a32-5fe8a53ee222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070407544 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2070407544
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2992174399
Short name T477
Test name
Test status
Simulation time 41479401 ps
CPU time 0.89 seconds
Started Jul 30 06:44:38 PM PDT 24
Finished Jul 30 06:44:39 PM PDT 24
Peak memory 215316 kb
Host smart-7b2406f3-1d14-4448-9d5f-fe3b959358b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992174399 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2992174399
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1715325211
Short name T623
Test name
Test status
Simulation time 109777265 ps
CPU time 2.69 seconds
Started Jul 30 06:44:52 PM PDT 24
Finished Jul 30 06:44:55 PM PDT 24
Peak memory 215260 kb
Host smart-26427cc9-9405-489e-a763-c92d88e4d911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715325211 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1715325211
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3584140492
Short name T24
Test name
Test status
Simulation time 121605096801 ps
CPU time 745.32 seconds
Started Jul 30 06:44:41 PM PDT 24
Finished Jul 30 06:57:06 PM PDT 24
Peak memory 221244 kb
Host smart-580e9e0e-39a3-4f81-88a6-282c355f3a94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584140492 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3584140492
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1448554965
Short name T10
Test name
Test status
Simulation time 184189539 ps
CPU time 2.8 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 219968 kb
Host smart-971ef0cd-7441-4c7e-bc83-9e19066641f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448554965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1448554965
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.512701578
Short name T339
Test name
Test status
Simulation time 57155725 ps
CPU time 1.09 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 217240 kb
Host smart-2ba5d9dc-c98f-4d2a-8e63-ccc7fbed1f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512701578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.512701578
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3579872313
Short name T819
Test name
Test status
Simulation time 92790697 ps
CPU time 1.36 seconds
Started Jul 30 06:46:02 PM PDT 24
Finished Jul 30 06:46:03 PM PDT 24
Peak memory 219976 kb
Host smart-a6f2efb9-7675-430a-8faf-0de418d7f79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579872313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3579872313
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.490430753
Short name T984
Test name
Test status
Simulation time 566484650 ps
CPU time 4 seconds
Started Jul 30 06:46:02 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 220332 kb
Host smart-fcf69128-494e-45ec-99de-416060ed673e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490430753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.490430753
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3586504874
Short name T348
Test name
Test status
Simulation time 38850328 ps
CPU time 1.19 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 218496 kb
Host smart-63506c85-1357-4d6b-9481-989c03516b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586504874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3586504874
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2430442459
Short name T584
Test name
Test status
Simulation time 38066473 ps
CPU time 1.8 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 218500 kb
Host smart-3430e38c-a332-419b-be46-fc346a1e35c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430442459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2430442459
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2171486341
Short name T386
Test name
Test status
Simulation time 40435985 ps
CPU time 1.6 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 217392 kb
Host smart-5e0fbcdf-3bde-4b33-89a9-0eac33aa99f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171486341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2171486341
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3125318833
Short name T439
Test name
Test status
Simulation time 105631135 ps
CPU time 1.51 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 218988 kb
Host smart-86193e72-d4dd-4458-b489-4d126cb8f773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125318833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3125318833
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1666485556
Short name T137
Test name
Test status
Simulation time 70056902 ps
CPU time 1.04 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 217252 kb
Host smart-c8d378ee-35b6-4d6b-96f9-48767b2d7611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666485556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1666485556
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3888877390
Short name T327
Test name
Test status
Simulation time 124853407 ps
CPU time 1.38 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:08 PM PDT 24
Peak memory 218548 kb
Host smart-997962a8-f4af-4fe8-a045-915683f6d9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888877390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3888877390
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3374942414
Short name T712
Test name
Test status
Simulation time 23071858 ps
CPU time 1.14 seconds
Started Jul 30 06:44:50 PM PDT 24
Finished Jul 30 06:44:51 PM PDT 24
Peak memory 221000 kb
Host smart-3ed96039-ed57-4af1-a77c-3c551ab5c216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374942414 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3374942414
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1464570645
Short name T872
Test name
Test status
Simulation time 41898400 ps
CPU time 0.87 seconds
Started Jul 30 06:44:54 PM PDT 24
Finished Jul 30 06:44:55 PM PDT 24
Peak memory 214716 kb
Host smart-dddc21f3-0053-42e2-856d-a8dc93b35c9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464570645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1464570645
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_genbits.3695354455
Short name T574
Test name
Test status
Simulation time 195157958 ps
CPU time 1.11 seconds
Started Jul 30 06:44:54 PM PDT 24
Finished Jul 30 06:44:55 PM PDT 24
Peak memory 215388 kb
Host smart-40c58ba2-1186-4a07-90ad-9c7ebd893d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695354455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3695354455
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_smoke.3985544431
Short name T582
Test name
Test status
Simulation time 18370094 ps
CPU time 1.07 seconds
Started Jul 30 06:44:40 PM PDT 24
Finished Jul 30 06:44:41 PM PDT 24
Peak memory 215300 kb
Host smart-c99d8672-d4f3-4c0f-ad11-8f6495620966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985544431 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3985544431
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2608356826
Short name T67
Test name
Test status
Simulation time 250115957 ps
CPU time 5.05 seconds
Started Jul 30 06:44:51 PM PDT 24
Finished Jul 30 06:44:56 PM PDT 24
Peak memory 217208 kb
Host smart-b2dc60b1-9d86-48fa-b4b4-bbbaeb6c37cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608356826 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2608356826
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.74072887
Short name T484
Test name
Test status
Simulation time 47760341232 ps
CPU time 1058.14 seconds
Started Jul 30 06:44:43 PM PDT 24
Finished Jul 30 07:02:21 PM PDT 24
Peak memory 220360 kb
Host smart-a4ae0eb9-5b5f-42ed-a541-73c205220b70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74072887 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.74072887
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2495950163
Short name T644
Test name
Test status
Simulation time 100196589 ps
CPU time 1.53 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 218776 kb
Host smart-ebf1731b-d3c2-40a5-a11f-319404652b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495950163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2495950163
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1295619062
Short name T395
Test name
Test status
Simulation time 141554389 ps
CPU time 1.34 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:15 PM PDT 24
Peak memory 219068 kb
Host smart-9eb9739c-eb6c-45fe-aedc-060fb9041dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295619062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1295619062
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.907256857
Short name T902
Test name
Test status
Simulation time 32797061 ps
CPU time 1.38 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 220168 kb
Host smart-6364a712-8a1a-49d4-82f0-81e59857b6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907256857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.907256857
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1455430142
Short name T706
Test name
Test status
Simulation time 63810168 ps
CPU time 1.82 seconds
Started Jul 30 06:46:18 PM PDT 24
Finished Jul 30 06:46:20 PM PDT 24
Peak memory 218836 kb
Host smart-e0c3b5d0-fa98-4755-a880-cdfbdf4f93a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455430142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1455430142
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1977493039
Short name T859
Test name
Test status
Simulation time 47666404 ps
CPU time 1.25 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:12 PM PDT 24
Peak memory 218476 kb
Host smart-3e48c423-8a4b-49e0-9c2b-304be275ea4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977493039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1977493039
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2619989944
Short name T331
Test name
Test status
Simulation time 57560379 ps
CPU time 2.01 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 219764 kb
Host smart-8206a051-212f-43a5-bda5-5ca7d8af2402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619989944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2619989944
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2358863900
Short name T937
Test name
Test status
Simulation time 89013289 ps
CPU time 1.26 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 217252 kb
Host smart-4e41b7ab-b7a9-4b9d-abdb-82020460240d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358863900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2358863900
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.934812968
Short name T404
Test name
Test status
Simulation time 139966628 ps
CPU time 1.25 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 215252 kb
Host smart-cb87bb9e-bf6e-42b5-947b-0bed29652955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934812968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.934812968
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3574964361
Short name T557
Test name
Test status
Simulation time 86297440 ps
CPU time 1.24 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 218536 kb
Host smart-676afd9e-3542-4295-8362-6d758bc06073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574964361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3574964361
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.875479195
Short name T350
Test name
Test status
Simulation time 30125869 ps
CPU time 1.29 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 219884 kb
Host smart-02b4a179-cdfb-4291-b5f4-0d38a1a9b38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875479195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.875479195
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3606637478
Short name T312
Test name
Test status
Simulation time 39877310 ps
CPU time 1.16 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 218664 kb
Host smart-1328aa64-3557-4787-90a3-faefcb587179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606637478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3606637478
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2882875271
Short name T564
Test name
Test status
Simulation time 41023595 ps
CPU time 0.84 seconds
Started Jul 30 06:44:13 PM PDT 24
Finished Jul 30 06:44:14 PM PDT 24
Peak memory 206492 kb
Host smart-528b476b-b28d-4425-a74e-4b39306f0221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882875271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2882875271
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2036475498
Short name T609
Test name
Test status
Simulation time 10563266 ps
CPU time 0.86 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 215352 kb
Host smart-f61c4e15-9b66-439e-bf5b-111720f39b5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036475498 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2036475498
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2941191200
Short name T286
Test name
Test status
Simulation time 85092598 ps
CPU time 1.02 seconds
Started Jul 30 06:44:15 PM PDT 24
Finished Jul 30 06:44:16 PM PDT 24
Peak memory 218344 kb
Host smart-7177412f-7959-41e2-90a6-9f3ad1c3b72f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941191200 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2941191200
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.4145494606
Short name T105
Test name
Test status
Simulation time 19196507 ps
CPU time 1.05 seconds
Started Jul 30 06:44:17 PM PDT 24
Finished Jul 30 06:44:18 PM PDT 24
Peak memory 219628 kb
Host smart-66cc9451-89f5-42f7-8a01-83f22baa0b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145494606 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.4145494606
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2145438462
Short name T508
Test name
Test status
Simulation time 44235330 ps
CPU time 1.81 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 218820 kb
Host smart-7dc83f27-b132-488b-a4be-b823ef6736ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145438462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2145438462
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.319772492
Short name T45
Test name
Test status
Simulation time 40180652 ps
CPU time 0.99 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 224032 kb
Host smart-61127ebc-0430-44f1-a7ce-df2d6ed2901c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319772492 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.319772492
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2523213602
Short name T82
Test name
Test status
Simulation time 47922167 ps
CPU time 0.88 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 207060 kb
Host smart-ebf93bfd-c2be-4696-9c96-48c170c3d5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523213602 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2523213602
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.1087414062
Short name T490
Test name
Test status
Simulation time 40591613 ps
CPU time 0.93 seconds
Started Jul 30 06:44:06 PM PDT 24
Finished Jul 30 06:44:07 PM PDT 24
Peak memory 215284 kb
Host smart-54f6453e-941e-47c4-9462-ef73e848b406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087414062 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1087414062
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2590697621
Short name T923
Test name
Test status
Simulation time 550396350 ps
CPU time 3.21 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 217040 kb
Host smart-a9b685b5-2fbf-480c-b66c-caa1475952f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590697621 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2590697621
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.816617182
Short name T396
Test name
Test status
Simulation time 142487088798 ps
CPU time 1596.06 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 07:11:00 PM PDT 24
Peak memory 224444 kb
Host smart-996fc695-4aee-47af-8e2a-6ae4bd3297a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816617182 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.816617182
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1142603560
Short name T972
Test name
Test status
Simulation time 145879798 ps
CPU time 1.16 seconds
Started Jul 30 06:44:52 PM PDT 24
Finished Jul 30 06:44:53 PM PDT 24
Peak memory 219000 kb
Host smart-45253a35-9d51-4bc5-932b-f3a05c7761f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142603560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1142603560
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.952056422
Short name T449
Test name
Test status
Simulation time 54153027 ps
CPU time 0.94 seconds
Started Jul 30 06:44:47 PM PDT 24
Finished Jul 30 06:44:48 PM PDT 24
Peak memory 214848 kb
Host smart-6817bf6b-0627-46dd-aea0-f955f677566d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952056422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.952056422
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3937556866
Short name T116
Test name
Test status
Simulation time 11370585 ps
CPU time 0.86 seconds
Started Jul 30 06:44:43 PM PDT 24
Finished Jul 30 06:44:44 PM PDT 24
Peak memory 216204 kb
Host smart-c3abd6a8-b242-4e4d-933d-39d6330dfd90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937556866 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3937556866
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3359643785
Short name T108
Test name
Test status
Simulation time 92237762 ps
CPU time 1.07 seconds
Started Jul 30 06:44:47 PM PDT 24
Finished Jul 30 06:44:48 PM PDT 24
Peak memory 216928 kb
Host smart-8416c7f0-cd17-419e-a2ff-a3db853f18d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359643785 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3359643785
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3811675035
Short name T901
Test name
Test status
Simulation time 56877531 ps
CPU time 1.24 seconds
Started Jul 30 06:44:46 PM PDT 24
Finished Jul 30 06:44:47 PM PDT 24
Peak memory 225844 kb
Host smart-4dcdb648-d563-4919-af7c-298507c1a146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811675035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3811675035
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1680696973
Short name T423
Test name
Test status
Simulation time 48369118 ps
CPU time 1.51 seconds
Started Jul 30 06:44:56 PM PDT 24
Finished Jul 30 06:44:57 PM PDT 24
Peak memory 217328 kb
Host smart-30b2f669-d07b-4612-a82d-9583d174b087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680696973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1680696973
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2248068187
Short name T426
Test name
Test status
Simulation time 36837650 ps
CPU time 0.93 seconds
Started Jul 30 06:44:45 PM PDT 24
Finished Jul 30 06:44:46 PM PDT 24
Peak memory 215336 kb
Host smart-6ee5eea3-cf81-4e72-b5c6-177dd64350bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248068187 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2248068187
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3874599321
Short name T472
Test name
Test status
Simulation time 52371511 ps
CPU time 0.92 seconds
Started Jul 30 06:44:42 PM PDT 24
Finished Jul 30 06:44:43 PM PDT 24
Peak memory 215272 kb
Host smart-a5467adf-4d91-4c04-984c-231de016d8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874599321 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3874599321
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.4207275484
Short name T800
Test name
Test status
Simulation time 803823537 ps
CPU time 5.24 seconds
Started Jul 30 06:44:45 PM PDT 24
Finished Jul 30 06:44:50 PM PDT 24
Peak memory 217288 kb
Host smart-d08dfca8-1e48-469c-8013-e5e4d6ff5560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207275484 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.4207275484
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_alert.4259033927
Short name T608
Test name
Test status
Simulation time 30581229 ps
CPU time 1.24 seconds
Started Jul 30 06:44:48 PM PDT 24
Finished Jul 30 06:44:49 PM PDT 24
Peak memory 218852 kb
Host smart-91148917-80d2-4cf1-b45f-78f28b2b590a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259033927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.4259033927
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2423105834
Short name T365
Test name
Test status
Simulation time 15655686 ps
CPU time 0.88 seconds
Started Jul 30 06:44:56 PM PDT 24
Finished Jul 30 06:44:57 PM PDT 24
Peak memory 206772 kb
Host smart-61115520-abb7-4837-b903-32c2d1ff24dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423105834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2423105834
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3506809714
Short name T180
Test name
Test status
Simulation time 12094938 ps
CPU time 0.9 seconds
Started Jul 30 06:45:08 PM PDT 24
Finished Jul 30 06:45:09 PM PDT 24
Peak memory 215548 kb
Host smart-e3f70fd8-72b2-45f9-bf0c-9a9ae81f3723
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506809714 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3506809714
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2995274719
Short name T162
Test name
Test status
Simulation time 66365696 ps
CPU time 1.04 seconds
Started Jul 30 06:44:42 PM PDT 24
Finished Jul 30 06:44:44 PM PDT 24
Peak memory 218824 kb
Host smart-9592ebf7-8814-497d-aeb1-e45b2d3bc878
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995274719 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2995274719
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1786114291
Short name T615
Test name
Test status
Simulation time 34288201 ps
CPU time 0.98 seconds
Started Jul 30 06:44:45 PM PDT 24
Finished Jul 30 06:44:46 PM PDT 24
Peak memory 223872 kb
Host smart-9bf64793-27e5-4de6-8f80-5f6232d84ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786114291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1786114291
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1406074072
Short name T968
Test name
Test status
Simulation time 42587461 ps
CPU time 1.52 seconds
Started Jul 30 06:45:01 PM PDT 24
Finished Jul 30 06:45:03 PM PDT 24
Peak memory 219824 kb
Host smart-82901119-46a0-4be6-bd45-a361efc5222c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406074072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1406074072
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.130652394
Short name T543
Test name
Test status
Simulation time 66222750 ps
CPU time 0.85 seconds
Started Jul 30 06:44:43 PM PDT 24
Finished Jul 30 06:44:44 PM PDT 24
Peak memory 215680 kb
Host smart-be7b8d75-b604-4f43-beff-67e3993045ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130652394 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.130652394
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.873340867
Short name T55
Test name
Test status
Simulation time 41665732 ps
CPU time 0.93 seconds
Started Jul 30 06:44:54 PM PDT 24
Finished Jul 30 06:44:55 PM PDT 24
Peak memory 215272 kb
Host smart-632732a0-ed21-4a03-ac96-e9f8aa25c545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873340867 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.873340867
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1187672030
Short name T587
Test name
Test status
Simulation time 338298486 ps
CPU time 2.4 seconds
Started Jul 30 06:44:54 PM PDT 24
Finished Jul 30 06:44:56 PM PDT 24
Peak memory 215336 kb
Host smart-9722f9b6-070f-4d33-ad90-af0c729b4b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187672030 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1187672030
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1109871421
Short name T225
Test name
Test status
Simulation time 389103917086 ps
CPU time 2189.35 seconds
Started Jul 30 06:44:54 PM PDT 24
Finished Jul 30 07:21:24 PM PDT 24
Peak memory 226860 kb
Host smart-477bceb6-b2d9-4d8a-bea4-e97a60066bad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109871421 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1109871421
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.4222935410
Short name T433
Test name
Test status
Simulation time 48475390 ps
CPU time 1.2 seconds
Started Jul 30 06:44:57 PM PDT 24
Finished Jul 30 06:44:58 PM PDT 24
Peak memory 220688 kb
Host smart-67ff0d6a-7578-4807-9d41-19402c8cc501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222935410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.4222935410
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.938269063
Short name T436
Test name
Test status
Simulation time 38612533 ps
CPU time 0.86 seconds
Started Jul 30 06:44:56 PM PDT 24
Finished Jul 30 06:44:57 PM PDT 24
Peak memory 215060 kb
Host smart-7d488993-2cfb-4fd9-8bc3-3d61266df763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938269063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.938269063
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2985072730
Short name T672
Test name
Test status
Simulation time 12709318 ps
CPU time 0.9 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:14 PM PDT 24
Peak memory 215628 kb
Host smart-6e2a4ed8-b0c5-43d6-826b-4534d1f68163
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985072730 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2985072730
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1502206486
Short name T284
Test name
Test status
Simulation time 55301356 ps
CPU time 1.04 seconds
Started Jul 30 06:44:49 PM PDT 24
Finished Jul 30 06:44:50 PM PDT 24
Peak memory 217008 kb
Host smart-e1cf1a0c-c60e-4c3f-8b19-5463ef3d563f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502206486 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1502206486
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3946315454
Short name T734
Test name
Test status
Simulation time 18905542 ps
CPU time 1.04 seconds
Started Jul 30 06:44:55 PM PDT 24
Finished Jul 30 06:44:56 PM PDT 24
Peak memory 218604 kb
Host smart-b144f421-770a-4bf5-8190-b34dc9d71793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946315454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3946315454
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2050686735
Short name T730
Test name
Test status
Simulation time 53255905 ps
CPU time 1.06 seconds
Started Jul 30 06:44:47 PM PDT 24
Finished Jul 30 06:44:48 PM PDT 24
Peak memory 217228 kb
Host smart-992d1907-6aeb-4df3-9088-38608d070311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050686735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2050686735
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3401940354
Short name T977
Test name
Test status
Simulation time 68363016 ps
CPU time 0.87 seconds
Started Jul 30 06:44:47 PM PDT 24
Finished Jul 30 06:44:48 PM PDT 24
Peak memory 215356 kb
Host smart-88ff006d-48fc-4efa-8ffd-8c18de09e268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401940354 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3401940354
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.4028742202
Short name T343
Test name
Test status
Simulation time 34739402 ps
CPU time 0.92 seconds
Started Jul 30 06:44:46 PM PDT 24
Finished Jul 30 06:44:47 PM PDT 24
Peak memory 215252 kb
Host smart-8c6e7a75-1b4b-4acf-b2f3-7bd463a7be5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028742202 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.4028742202
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1016213212
Short name T876
Test name
Test status
Simulation time 324707380 ps
CPU time 6.33 seconds
Started Jul 30 06:45:01 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 217228 kb
Host smart-3bfdc823-0ea5-488f-93fd-093494b880e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016213212 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1016213212
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1853903687
Short name T236
Test name
Test status
Simulation time 315081619564 ps
CPU time 1814.51 seconds
Started Jul 30 06:44:52 PM PDT 24
Finished Jul 30 07:15:07 PM PDT 24
Peak memory 224556 kb
Host smart-658006fe-f64e-4d80-a16f-3b15afb9214b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853903687 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1853903687
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2238864150
Short name T761
Test name
Test status
Simulation time 76588198 ps
CPU time 1.11 seconds
Started Jul 30 06:45:02 PM PDT 24
Finished Jul 30 06:45:03 PM PDT 24
Peak memory 218504 kb
Host smart-92a7319c-ea49-4cb1-a4c7-ef28af8879d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238864150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2238864150
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1342295032
Short name T774
Test name
Test status
Simulation time 35012260 ps
CPU time 1.03 seconds
Started Jul 30 06:45:03 PM PDT 24
Finished Jul 30 06:45:04 PM PDT 24
Peak memory 206804 kb
Host smart-add9b1c0-d643-47ab-89fb-4e2c66be22eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342295032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1342295032
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3654843935
Short name T358
Test name
Test status
Simulation time 29975858 ps
CPU time 1.17 seconds
Started Jul 30 06:44:51 PM PDT 24
Finished Jul 30 06:44:52 PM PDT 24
Peak memory 218576 kb
Host smart-a70ade8d-ffb5-4f65-b0a7-d0a1292f8425
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654843935 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3654843935
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2073604277
Short name T172
Test name
Test status
Simulation time 48300829 ps
CPU time 0.99 seconds
Started Jul 30 06:45:01 PM PDT 24
Finished Jul 30 06:45:02 PM PDT 24
Peak memory 219744 kb
Host smart-f896f7a3-8440-4cc8-bb09-29ed617c40ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073604277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2073604277
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2462734547
Short name T757
Test name
Test status
Simulation time 40076295 ps
CPU time 1.4 seconds
Started Jul 30 06:44:48 PM PDT 24
Finished Jul 30 06:44:49 PM PDT 24
Peak memory 218532 kb
Host smart-6637be8d-f6ed-437f-96ee-2e6d95f22e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462734547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2462734547
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.21167487
Short name T133
Test name
Test status
Simulation time 29521142 ps
CPU time 0.89 seconds
Started Jul 30 06:44:52 PM PDT 24
Finished Jul 30 06:44:53 PM PDT 24
Peak memory 215604 kb
Host smart-2cc64904-7ba7-4050-b5e2-2da448be9f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21167487 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.21167487
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3808247909
Short name T799
Test name
Test status
Simulation time 40439616 ps
CPU time 0.88 seconds
Started Jul 30 06:45:06 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 215248 kb
Host smart-f0a36c97-5783-4aef-84b6-34a34aee7486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808247909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3808247909
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3727503961
Short name T955
Test name
Test status
Simulation time 453060240 ps
CPU time 3.01 seconds
Started Jul 30 06:45:08 PM PDT 24
Finished Jul 30 06:45:11 PM PDT 24
Peak memory 217368 kb
Host smart-0b735bcd-34a1-4322-9692-3899a1a0b4b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727503961 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3727503961
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.4120583213
Short name T944
Test name
Test status
Simulation time 157387459535 ps
CPU time 1963.17 seconds
Started Jul 30 06:44:49 PM PDT 24
Finished Jul 30 07:17:32 PM PDT 24
Peak memory 228092 kb
Host smart-beb8d238-84f3-418a-8b45-643044441b30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120583213 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.4120583213
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2275990715
Short name T494
Test name
Test status
Simulation time 29995985 ps
CPU time 1.29 seconds
Started Jul 30 06:45:05 PM PDT 24
Finished Jul 30 06:45:06 PM PDT 24
Peak memory 218660 kb
Host smart-a145606c-3704-4d8b-812f-13e4c8d959f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275990715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2275990715
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3470738734
Short name T388
Test name
Test status
Simulation time 16068055 ps
CPU time 0.94 seconds
Started Jul 30 06:45:05 PM PDT 24
Finished Jul 30 06:45:06 PM PDT 24
Peak memory 214924 kb
Host smart-c175f70c-c7a2-4e4b-80aa-86d9fad34949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470738734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3470738734
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1607515711
Short name T586
Test name
Test status
Simulation time 53395825 ps
CPU time 0.86 seconds
Started Jul 30 06:45:06 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 215908 kb
Host smart-92fc0968-1f5e-44db-8bee-017d9e2a9c09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607515711 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1607515711
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2255774192
Short name T516
Test name
Test status
Simulation time 26596871 ps
CPU time 1.35 seconds
Started Jul 30 06:45:03 PM PDT 24
Finished Jul 30 06:45:05 PM PDT 24
Peak memory 218576 kb
Host smart-a6d845f7-650d-4dd4-8cf5-3939a5d6ac77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255774192 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2255774192
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.4098034413
Short name T556
Test name
Test status
Simulation time 20063118 ps
CPU time 1 seconds
Started Jul 30 06:45:06 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 218456 kb
Host smart-f0d72d50-43a2-4a6a-920e-4aafd249e09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098034413 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4098034413
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1950744473
Short name T741
Test name
Test status
Simulation time 103207055 ps
CPU time 1.55 seconds
Started Jul 30 06:44:57 PM PDT 24
Finished Jul 30 06:44:58 PM PDT 24
Peak memory 218924 kb
Host smart-8ef01f9f-2875-4246-9183-c8cb9820df8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950744473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1950744473
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1549455582
Short name T621
Test name
Test status
Simulation time 45868399 ps
CPU time 0.83 seconds
Started Jul 30 06:45:07 PM PDT 24
Finished Jul 30 06:45:08 PM PDT 24
Peak memory 215268 kb
Host smart-546d5661-eb62-4296-bc97-fea5e2157fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549455582 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1549455582
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3328331872
Short name T963
Test name
Test status
Simulation time 57094872 ps
CPU time 0.94 seconds
Started Jul 30 06:44:47 PM PDT 24
Finished Jul 30 06:44:48 PM PDT 24
Peak memory 215264 kb
Host smart-e0894066-5910-4fcc-a72f-dcd9a7497351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328331872 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3328331872
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1061562764
Short name T682
Test name
Test status
Simulation time 434824031 ps
CPU time 5.04 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:21 PM PDT 24
Peak memory 215392 kb
Host smart-39795715-67c4-4db8-9078-f2619c730df4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061562764 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1061562764
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1546332711
Short name T390
Test name
Test status
Simulation time 194343049829 ps
CPU time 2084.28 seconds
Started Jul 30 06:45:05 PM PDT 24
Finished Jul 30 07:19:50 PM PDT 24
Peak memory 227236 kb
Host smart-91f05c68-9429-4116-9814-e3a2dfc2a07c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546332711 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1546332711
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.863290745
Short name T72
Test name
Test status
Simulation time 39877651 ps
CPU time 1.17 seconds
Started Jul 30 06:45:19 PM PDT 24
Finished Jul 30 06:45:20 PM PDT 24
Peak memory 218596 kb
Host smart-c3d43dd3-27fb-4471-851a-7a6c3b6a08fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863290745 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.863290745
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.827106607
Short name T705
Test name
Test status
Simulation time 15832607 ps
CPU time 0.93 seconds
Started Jul 30 06:45:04 PM PDT 24
Finished Jul 30 06:45:05 PM PDT 24
Peak memory 206668 kb
Host smart-e178eb92-42f2-4986-947c-5fdb11d72b34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827106607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.827106607
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1508744972
Short name T205
Test name
Test status
Simulation time 23254789 ps
CPU time 0.84 seconds
Started Jul 30 06:45:09 PM PDT 24
Finished Jul 30 06:45:10 PM PDT 24
Peak memory 216320 kb
Host smart-7031378a-7172-457b-80d8-6021d2fae4ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508744972 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1508744972
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2435053452
Short name T505
Test name
Test status
Simulation time 39554475 ps
CPU time 1.35 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 216908 kb
Host smart-a33f1a83-91ed-43a7-815a-ff4702c16826
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435053452 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2435053452
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3225033883
Short name T187
Test name
Test status
Simulation time 39350434 ps
CPU time 0.98 seconds
Started Jul 30 06:45:02 PM PDT 24
Finished Jul 30 06:45:03 PM PDT 24
Peak memory 223864 kb
Host smart-d97a944f-3f1c-4bb1-9363-bb3d69758f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225033883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3225033883
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3859611427
Short name T500
Test name
Test status
Simulation time 149468492 ps
CPU time 2.23 seconds
Started Jul 30 06:45:10 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 218508 kb
Host smart-d0779bc1-7c55-4dbf-8276-5a73fe678f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859611427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3859611427
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3807693162
Short name T650
Test name
Test status
Simulation time 31326354 ps
CPU time 0.93 seconds
Started Jul 30 06:45:02 PM PDT 24
Finished Jul 30 06:45:03 PM PDT 24
Peak memory 215304 kb
Host smart-43748d7b-67e5-4966-a673-91e9240e9211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807693162 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3807693162
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.384594300
Short name T410
Test name
Test status
Simulation time 17550207 ps
CPU time 1.03 seconds
Started Jul 30 06:45:10 PM PDT 24
Finished Jul 30 06:45:11 PM PDT 24
Peak memory 215268 kb
Host smart-afae2d04-ec4a-48ee-95c2-6bfa65491d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384594300 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.384594300
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.320114805
Short name T701
Test name
Test status
Simulation time 40382419 ps
CPU time 1.23 seconds
Started Jul 30 06:45:01 PM PDT 24
Finished Jul 30 06:45:02 PM PDT 24
Peak memory 215276 kb
Host smart-eb0d3f9c-d720-4967-902c-f1d75017f421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320114805 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.320114805
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1805674115
Short name T661
Test name
Test status
Simulation time 156623801784 ps
CPU time 755.89 seconds
Started Jul 30 06:45:09 PM PDT 24
Finished Jul 30 06:57:45 PM PDT 24
Peak memory 221304 kb
Host smart-1d9579ef-ec44-4080-9f01-c094b35a2339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805674115 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1805674115
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1685568366
Short name T305
Test name
Test status
Simulation time 31238712 ps
CPU time 1.27 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 220284 kb
Host smart-e2fbc9a5-275e-431e-b07d-d4e53abff3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685568366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1685568366
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3392042175
Short name T714
Test name
Test status
Simulation time 13466013 ps
CPU time 0.9 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 214988 kb
Host smart-d6958a37-4150-420f-9ca0-2188cd7df459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392042175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3392042175
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2845588491
Short name T220
Test name
Test status
Simulation time 27060064 ps
CPU time 0.82 seconds
Started Jul 30 06:45:06 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 215384 kb
Host smart-b9bafb18-4f10-48ea-bfc9-a56118e7deaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845588491 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2845588491
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2650134663
Short name T683
Test name
Test status
Simulation time 43657081 ps
CPU time 1 seconds
Started Jul 30 06:44:58 PM PDT 24
Finished Jul 30 06:44:59 PM PDT 24
Peak memory 218536 kb
Host smart-50a4b87b-9e39-4805-8c33-915440906c27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650134663 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2650134663
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3711008878
Short name T870
Test name
Test status
Simulation time 35064031 ps
CPU time 1.54 seconds
Started Jul 30 06:45:01 PM PDT 24
Finished Jul 30 06:45:03 PM PDT 24
Peak memory 225800 kb
Host smart-31963ee7-9925-49f5-bf5d-79784513ed74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711008878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3711008878
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.55134172
Short name T696
Test name
Test status
Simulation time 42024584 ps
CPU time 1.37 seconds
Started Jul 30 06:45:00 PM PDT 24
Finished Jul 30 06:45:01 PM PDT 24
Peak memory 218448 kb
Host smart-9a72b5b1-0211-4b0f-b289-8692e156b88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55134172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.55134172
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2680849408
Short name T59
Test name
Test status
Simulation time 30631557 ps
CPU time 0.84 seconds
Started Jul 30 06:45:09 PM PDT 24
Finished Jul 30 06:45:10 PM PDT 24
Peak memory 215288 kb
Host smart-80640e2d-153d-4b37-ac32-bde0dca35112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680849408 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2680849408
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3954620019
Short name T246
Test name
Test status
Simulation time 14383722 ps
CPU time 0.95 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 215280 kb
Host smart-3e43579e-582e-427d-b176-2d97331fded0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954620019 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3954620019
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3798738157
Short name T583
Test name
Test status
Simulation time 183406672 ps
CPU time 1.74 seconds
Started Jul 30 06:45:11 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 217244 kb
Host smart-af2048d7-4d15-470c-bbd3-7f76402a5845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798738157 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3798738157
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_alert_test.306600878
Short name T895
Test name
Test status
Simulation time 13254401 ps
CPU time 0.92 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 215072 kb
Host smart-696ca8df-d5e3-4388-ad01-b2a233b7279b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306600878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.306600878
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_err.84820655
Short name T572
Test name
Test status
Simulation time 23687617 ps
CPU time 0.99 seconds
Started Jul 30 06:45:09 PM PDT 24
Finished Jul 30 06:45:10 PM PDT 24
Peak memory 218620 kb
Host smart-7dc3e1aa-ca25-4262-b8cc-b58bd17caa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84820655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.84820655
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2590613430
Short name T419
Test name
Test status
Simulation time 45878377 ps
CPU time 1.46 seconds
Started Jul 30 06:45:00 PM PDT 24
Finished Jul 30 06:45:02 PM PDT 24
Peak memory 217412 kb
Host smart-36d483a4-1fb5-4b31-9b7f-1e67c3956fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590613430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2590613430
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1941559042
Short name T630
Test name
Test status
Simulation time 99770435 ps
CPU time 0.93 seconds
Started Jul 30 06:45:05 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 223844 kb
Host smart-80835ca1-655f-4cd2-b13c-bb508f10e5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941559042 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1941559042
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.4205997706
Short name T836
Test name
Test status
Simulation time 19535126 ps
CPU time 0.97 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 215208 kb
Host smart-2c065157-5169-48c3-9a3e-029c179fda1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205997706 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.4205997706
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1854609268
Short name T70
Test name
Test status
Simulation time 218992741 ps
CPU time 1.99 seconds
Started Jul 30 06:45:03 PM PDT 24
Finished Jul 30 06:45:05 PM PDT 24
Peak memory 215308 kb
Host smart-7b4ca0a7-1fdc-4217-9c94-08484df86096
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854609268 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1854609268
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.601470553
Short name T227
Test name
Test status
Simulation time 16667793541 ps
CPU time 357.39 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:51:10 PM PDT 24
Peak memory 223540 kb
Host smart-1b9da0ed-aad7-4034-a084-7ac05e149537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601470553 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.601470553
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1048915853
Short name T966
Test name
Test status
Simulation time 85366739 ps
CPU time 1.16 seconds
Started Jul 30 06:45:07 PM PDT 24
Finished Jul 30 06:45:08 PM PDT 24
Peak memory 218532 kb
Host smart-721ab6c4-18a1-464c-b01d-a3cedd56a0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048915853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1048915853
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2277744010
Short name T538
Test name
Test status
Simulation time 39484855 ps
CPU time 0.97 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 206932 kb
Host smart-10e70154-8040-40aa-bf2a-5fd1d8cc20c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277744010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2277744010
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.708722325
Short name T182
Test name
Test status
Simulation time 48144692 ps
CPU time 0.88 seconds
Started Jul 30 06:45:05 PM PDT 24
Finished Jul 30 06:45:06 PM PDT 24
Peak memory 215384 kb
Host smart-5bef023e-1b10-45c7-b743-8d56c46d3f3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708722325 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.708722325
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.2664035084
Short name T132
Test name
Test status
Simulation time 25576147 ps
CPU time 0.99 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:14 PM PDT 24
Peak memory 219944 kb
Host smart-58c744e0-f0af-4b6b-b5b5-d812071d3f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664035084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2664035084
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.221287090
Short name T337
Test name
Test status
Simulation time 44146987 ps
CPU time 1.59 seconds
Started Jul 30 06:45:05 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 217560 kb
Host smart-8ae6c40b-60e1-4504-911f-6b3a5038249c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221287090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.221287090
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.473919170
Short name T15
Test name
Test status
Simulation time 35639846 ps
CPU time 1.03 seconds
Started Jul 30 06:45:05 PM PDT 24
Finished Jul 30 06:45:06 PM PDT 24
Peak memory 223820 kb
Host smart-9e9fd475-05cc-411d-baa8-7524ffb73eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473919170 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.473919170
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3479652061
Short name T397
Test name
Test status
Simulation time 25615480 ps
CPU time 0.96 seconds
Started Jul 30 06:45:23 PM PDT 24
Finished Jul 30 06:45:24 PM PDT 24
Peak memory 215264 kb
Host smart-edd1acef-b6b6-4f53-84e8-d0e3cbfcc21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479652061 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3479652061
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.4216605060
Short name T640
Test name
Test status
Simulation time 60432899 ps
CPU time 1.2 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 215276 kb
Host smart-b4a529ac-ce4a-40d6-a372-b18a63bec2bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216605060 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4216605060
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2019488351
Short name T982
Test name
Test status
Simulation time 90806197745 ps
CPU time 568.74 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:54:41 PM PDT 24
Peak memory 223712 kb
Host smart-668d84e2-5b9a-42b0-b0fa-112a65a2e54f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019488351 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2019488351
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.102887020
Short name T900
Test name
Test status
Simulation time 90597333 ps
CPU time 1.15 seconds
Started Jul 30 06:45:04 PM PDT 24
Finished Jul 30 06:45:05 PM PDT 24
Peak memory 219748 kb
Host smart-a7abd521-6936-47e9-8bc9-ba397e64c113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102887020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.102887020
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.716411391
Short name T617
Test name
Test status
Simulation time 57212446 ps
CPU time 0.85 seconds
Started Jul 30 06:45:03 PM PDT 24
Finished Jul 30 06:45:04 PM PDT 24
Peak memory 214664 kb
Host smart-310772fd-c8ae-4696-b84d-76ad21fc1850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716411391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.716411391
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1759996303
Short name T196
Test name
Test status
Simulation time 40779188 ps
CPU time 0.85 seconds
Started Jul 30 06:45:05 PM PDT 24
Finished Jul 30 06:45:06 PM PDT 24
Peak memory 216204 kb
Host smart-20ed2bc0-689f-4ffc-ba1c-24fd377f457e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759996303 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1759996303
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1047736530
Short name T471
Test name
Test status
Simulation time 69556713 ps
CPU time 1.08 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:26 PM PDT 24
Peak memory 217024 kb
Host smart-3f9e380d-c8c7-48f5-a672-00170861df9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047736530 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1047736530
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2799401841
Short name T4
Test name
Test status
Simulation time 19493295 ps
CPU time 1.04 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 218416 kb
Host smart-9938f15b-398d-4e1b-bd87-54408bffb0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799401841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2799401841
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1828234852
Short name T590
Test name
Test status
Simulation time 56873159 ps
CPU time 1.04 seconds
Started Jul 30 06:44:59 PM PDT 24
Finished Jul 30 06:45:00 PM PDT 24
Peak memory 217196 kb
Host smart-da3e60df-5f60-4623-903b-7cea342fc0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828234852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1828234852
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.412288643
Short name T829
Test name
Test status
Simulation time 35160094 ps
CPU time 0.87 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 215372 kb
Host smart-d86f8dd6-7846-4c53-8d46-191f06a77c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412288643 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.412288643
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2537251103
Short name T391
Test name
Test status
Simulation time 26930730 ps
CPU time 0.95 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 215240 kb
Host smart-2c9b5f15-0c9a-4244-b31d-4c755021f654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537251103 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2537251103
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2261252370
Short name T425
Test name
Test status
Simulation time 205084968 ps
CPU time 3.33 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 218432 kb
Host smart-cc6dcc65-d45b-48fe-a9ed-b10e1bd6ff7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261252370 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2261252370
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.97874100
Short name T466
Test name
Test status
Simulation time 27615931566 ps
CPU time 528.67 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:54:06 PM PDT 24
Peak memory 223804 kb
Host smart-3bc1e711-c684-4295-9087-59bed130b707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97874100 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.97874100
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3225236229
Short name T518
Test name
Test status
Simulation time 25393235 ps
CPU time 1.24 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 219232 kb
Host smart-b4c7f1b5-b74d-4c16-8174-97e99b716983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225236229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3225236229
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.4069278718
Short name T657
Test name
Test status
Simulation time 52507439 ps
CPU time 0.86 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:20 PM PDT 24
Peak memory 214864 kb
Host smart-5dbea953-11e7-46ab-882a-4281e957cbff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069278718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.4069278718
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1966389403
Short name T668
Test name
Test status
Simulation time 28228887 ps
CPU time 0.84 seconds
Started Jul 30 06:44:16 PM PDT 24
Finished Jul 30 06:44:17 PM PDT 24
Peak memory 216220 kb
Host smart-6e011acd-a826-40cb-8cff-c706d2927e6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966389403 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1966389403
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3028216336
Short name T52
Test name
Test status
Simulation time 76129781 ps
CPU time 1.33 seconds
Started Jul 30 06:44:16 PM PDT 24
Finished Jul 30 06:44:18 PM PDT 24
Peak memory 216776 kb
Host smart-c3bc33b3-bb44-4d66-a565-1cc338ecebe3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028216336 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3028216336
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_genbits.3549382290
Short name T568
Test name
Test status
Simulation time 61884308 ps
CPU time 1 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:20 PM PDT 24
Peak memory 217064 kb
Host smart-785c4a89-e2e1-4fe0-8897-baaaae0c819c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549382290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3549382290
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1430080779
Short name T835
Test name
Test status
Simulation time 43054488 ps
CPU time 0.99 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 223808 kb
Host smart-d5de932f-6661-4193-ae8d-be4a4a9a8232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430080779 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1430080779
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2020627015
Short name T519
Test name
Test status
Simulation time 39641374 ps
CPU time 0.93 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:20 PM PDT 24
Peak memory 206988 kb
Host smart-606612e0-2c0c-4663-850e-fddf9c3625cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020627015 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2020627015
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.3437593990
Short name T362
Test name
Test status
Simulation time 30699709 ps
CPU time 0.93 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 215256 kb
Host smart-f0130e91-7f88-4b45-a135-36408fea4e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437593990 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3437593990
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1550167693
Short name T891
Test name
Test status
Simulation time 491025612 ps
CPU time 5.03 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 217428 kb
Host smart-6482fb4c-1af6-40ed-b58f-31dfb698fb86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550167693 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1550167693
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1791068643
Short name T509
Test name
Test status
Simulation time 246131503112 ps
CPU time 1381.25 seconds
Started Jul 30 06:44:16 PM PDT 24
Finished Jul 30 07:07:18 PM PDT 24
Peak memory 224392 kb
Host smart-f269f172-1d3d-44c3-9fb3-eb855542f094
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791068643 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1791068643
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1965613295
Short name T725
Test name
Test status
Simulation time 79481017 ps
CPU time 1.18 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 220412 kb
Host smart-ef492701-020b-4689-a441-3d099b1c9517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965613295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1965613295
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2662455544
Short name T675
Test name
Test status
Simulation time 22986150 ps
CPU time 0.93 seconds
Started Jul 30 06:45:06 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 206652 kb
Host smart-57895932-08c9-4142-9d62-ad68fded37db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662455544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2662455544
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2932232910
Short name T526
Test name
Test status
Simulation time 35207815 ps
CPU time 0.85 seconds
Started Jul 30 06:45:10 PM PDT 24
Finished Jul 30 06:45:11 PM PDT 24
Peak memory 215996 kb
Host smart-9b25e485-61e1-4beb-9e0e-95fe9a987239
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932232910 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2932232910
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2471994461
Short name T898
Test name
Test status
Simulation time 101011129 ps
CPU time 1.01 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 216944 kb
Host smart-51caeca1-fb46-4fba-a308-f06d820896a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471994461 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2471994461
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.805225751
Short name T862
Test name
Test status
Simulation time 63115590 ps
CPU time 0.84 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 218496 kb
Host smart-01e8b40f-a320-4625-98d6-396d88c4779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805225751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.805225751
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3593417789
Short name T606
Test name
Test status
Simulation time 52528361 ps
CPU time 1.35 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 217108 kb
Host smart-fc752d5d-89de-4736-a48b-c46e9e197d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593417789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3593417789
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.4035391331
Short name T134
Test name
Test status
Simulation time 70985922 ps
CPU time 0.83 seconds
Started Jul 30 06:45:09 PM PDT 24
Finished Jul 30 06:45:09 PM PDT 24
Peak memory 215564 kb
Host smart-08592e65-f243-4aa2-8351-36ba8dba1403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035391331 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.4035391331
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.600738519
Short name T368
Test name
Test status
Simulation time 18804265 ps
CPU time 1 seconds
Started Jul 30 06:45:06 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 215232 kb
Host smart-79eac388-6345-42cf-9a23-685287980b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600738519 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.600738519
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1589906380
Short name T565
Test name
Test status
Simulation time 366168875 ps
CPU time 4.24 seconds
Started Jul 30 06:45:05 PM PDT 24
Finished Jul 30 06:45:09 PM PDT 24
Peak memory 215288 kb
Host smart-ad0e5327-9af8-405c-b124-4a5b8f438b52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589906380 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1589906380
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2838006158
Short name T445
Test name
Test status
Simulation time 25496629831 ps
CPU time 595.07 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:55:11 PM PDT 24
Peak memory 217956 kb
Host smart-ab1a98cc-e958-4147-acd4-87c42c5625d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838006158 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2838006158
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1650054155
Short name T191
Test name
Test status
Simulation time 192719076 ps
CPU time 1.3 seconds
Started Jul 30 06:45:03 PM PDT 24
Finished Jul 30 06:45:05 PM PDT 24
Peak memory 219564 kb
Host smart-6bb91269-042b-486a-992d-add1462faa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650054155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1650054155
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.736504551
Short name T990
Test name
Test status
Simulation time 45505519 ps
CPU time 0.85 seconds
Started Jul 30 06:45:08 PM PDT 24
Finished Jul 30 06:45:09 PM PDT 24
Peak memory 214732 kb
Host smart-f196f752-e56f-42f1-ad69-23adc8b3dafb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736504551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.736504551
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.319949360
Short name T844
Test name
Test status
Simulation time 16396324 ps
CPU time 0.94 seconds
Started Jul 30 06:45:22 PM PDT 24
Finished Jul 30 06:45:23 PM PDT 24
Peak memory 216260 kb
Host smart-697b4002-a739-48b1-a6e8-d4f4acd2b7a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319949360 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.319949360
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2892103122
Short name T740
Test name
Test status
Simulation time 350077043 ps
CPU time 1.13 seconds
Started Jul 30 06:45:05 PM PDT 24
Finished Jul 30 06:45:06 PM PDT 24
Peak memory 216880 kb
Host smart-d6bc9549-f9be-4486-95ca-67fcc4b5e1c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892103122 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2892103122
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3096026621
Short name T144
Test name
Test status
Simulation time 28084247 ps
CPU time 1.28 seconds
Started Jul 30 06:45:11 PM PDT 24
Finished Jul 30 06:45:12 PM PDT 24
Peak memory 217360 kb
Host smart-26d77333-0d89-4edd-9b77-c859d0b23581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096026621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3096026621
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.4179367589
Short name T544
Test name
Test status
Simulation time 258787827 ps
CPU time 3.97 seconds
Started Jul 30 06:45:07 PM PDT 24
Finished Jul 30 06:45:11 PM PDT 24
Peak memory 219740 kb
Host smart-2fc47bb9-2918-4e92-9a20-d52c2bc93a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179367589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.4179367589
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3855806652
Short name T964
Test name
Test status
Simulation time 39481361 ps
CPU time 0.86 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 215712 kb
Host smart-81739ddb-8baa-44b9-8189-96c0ae1a9f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855806652 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3855806652
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3914243086
Short name T366
Test name
Test status
Simulation time 26566265 ps
CPU time 1 seconds
Started Jul 30 06:45:09 PM PDT 24
Finished Jul 30 06:45:10 PM PDT 24
Peak memory 215328 kb
Host smart-e0dce97d-5b11-4090-b688-33cd2c7ff999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914243086 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3914243086
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1270297730
Short name T443
Test name
Test status
Simulation time 363287929 ps
CPU time 4.27 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:20 PM PDT 24
Peak memory 217264 kb
Host smart-9b3a19c1-047e-49dd-aa35-54397fed1f80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270297730 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1270297730
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.4067164660
Short name T389
Test name
Test status
Simulation time 89294786122 ps
CPU time 950.94 seconds
Started Jul 30 06:45:11 PM PDT 24
Finished Jul 30 07:01:03 PM PDT 24
Peak memory 221740 kb
Host smart-189ebd13-0807-4631-ace3-101a1b7ae0fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067164660 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.4067164660
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.280203314
Short name T460
Test name
Test status
Simulation time 31210857 ps
CPU time 1.3 seconds
Started Jul 30 06:45:09 PM PDT 24
Finished Jul 30 06:45:10 PM PDT 24
Peak memory 215860 kb
Host smart-210eb781-f8c9-47a7-bd1e-e6788903c012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280203314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.280203314
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2483153218
Short name T790
Test name
Test status
Simulation time 41491526 ps
CPU time 0.84 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 206748 kb
Host smart-ac568f8a-9b31-453f-943e-e857babf6218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483153218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2483153218
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.250114925
Short name T34
Test name
Test status
Simulation time 14595182 ps
CPU time 0.89 seconds
Started Jul 30 06:45:09 PM PDT 24
Finished Jul 30 06:45:10 PM PDT 24
Peak memory 216156 kb
Host smart-a306225c-3cb3-4194-9ff5-8031cddd08d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250114925 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.250114925
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3608866687
Short name T394
Test name
Test status
Simulation time 40516919 ps
CPU time 1.06 seconds
Started Jul 30 06:45:10 PM PDT 24
Finished Jul 30 06:45:11 PM PDT 24
Peak memory 216924 kb
Host smart-90b9f7eb-1d6d-4ab0-9b78-614ce2bcda75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608866687 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3608866687
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1083494099
Short name T115
Test name
Test status
Simulation time 38956876 ps
CPU time 0.87 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 218572 kb
Host smart-cfacfddd-29d1-43b9-868d-1e6a9c51962b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083494099 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1083494099
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.699432779
Short name T411
Test name
Test status
Simulation time 261098839 ps
CPU time 3.41 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 220040 kb
Host smart-2f76620a-d384-4655-bd71-fa3a2be37016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699432779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.699432779
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.977026488
Short name T784
Test name
Test status
Simulation time 26893770 ps
CPU time 1.09 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 223384 kb
Host smart-8486ea60-43a8-4305-80d9-f148a7d529f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977026488 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.977026488
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3718126782
Short name T525
Test name
Test status
Simulation time 25648733 ps
CPU time 0.94 seconds
Started Jul 30 06:45:07 PM PDT 24
Finished Jul 30 06:45:08 PM PDT 24
Peak memory 215364 kb
Host smart-2dd4f50c-7ef6-45d7-880f-f97d8f01f9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718126782 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3718126782
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2381452386
Short name T250
Test name
Test status
Simulation time 269452720 ps
CPU time 3.02 seconds
Started Jul 30 06:45:06 PM PDT 24
Finished Jul 30 06:45:10 PM PDT 24
Peak memory 217232 kb
Host smart-a6d7f7b2-6f17-4f3e-b87a-11c4a42ff9bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381452386 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2381452386
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3286988037
Short name T226
Test name
Test status
Simulation time 72457136253 ps
CPU time 828.42 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:59:02 PM PDT 24
Peak memory 222544 kb
Host smart-ce35b29d-73dd-4a92-ba33-7cefc4cb381c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286988037 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3286988037
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1977527719
Short name T662
Test name
Test status
Simulation time 145714473 ps
CPU time 1.26 seconds
Started Jul 30 06:45:08 PM PDT 24
Finished Jul 30 06:45:09 PM PDT 24
Peak memory 219580 kb
Host smart-9e470eb1-8983-42a9-8fa7-84d0f68a232f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977527719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1977527719
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.802340395
Short name T754
Test name
Test status
Simulation time 85951999 ps
CPU time 0.91 seconds
Started Jul 30 06:45:05 PM PDT 24
Finished Jul 30 06:45:06 PM PDT 24
Peak memory 206728 kb
Host smart-7d2b8e30-4e0f-4aef-a565-7f30bb6dccbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802340395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.802340395
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2811863108
Short name T113
Test name
Test status
Simulation time 42975729 ps
CPU time 1 seconds
Started Jul 30 06:45:10 PM PDT 24
Finished Jul 30 06:45:11 PM PDT 24
Peak memory 216260 kb
Host smart-62c7a4f1-1098-4f69-8397-ac69631c4e0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811863108 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2811863108
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1536558767
Short name T961
Test name
Test status
Simulation time 119643447 ps
CPU time 1.2 seconds
Started Jul 30 06:45:01 PM PDT 24
Finished Jul 30 06:45:03 PM PDT 24
Peak memory 218596 kb
Host smart-6c909a81-c1e2-48c5-84d6-e0acf3a85086
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536558767 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1536558767
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1361053540
Short name T171
Test name
Test status
Simulation time 23869913 ps
CPU time 1.11 seconds
Started Jul 30 06:45:04 PM PDT 24
Finished Jul 30 06:45:05 PM PDT 24
Peak memory 229660 kb
Host smart-6a4da572-a35a-40a8-b982-59088131d8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361053540 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1361053540
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3383288364
Short name T324
Test name
Test status
Simulation time 53022955 ps
CPU time 1.25 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 218448 kb
Host smart-3ffadff5-e9cc-4320-b0f8-e8c4763b7658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383288364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3383288364
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3963198324
Short name T84
Test name
Test status
Simulation time 21264367 ps
CPU time 1.1 seconds
Started Jul 30 06:45:07 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 215804 kb
Host smart-3bdde68b-3789-4431-bd4a-c3c41fc06e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963198324 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3963198324
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3456186328
Short name T514
Test name
Test status
Simulation time 19377312 ps
CPU time 1.03 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:14 PM PDT 24
Peak memory 215256 kb
Host smart-300ff311-46c7-490d-b5db-f11fe11b9eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456186328 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3456186328
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.410307803
Short name T689
Test name
Test status
Simulation time 1492417148 ps
CPU time 3.35 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:19 PM PDT 24
Peak memory 217232 kb
Host smart-50a44739-c15c-4449-a584-e65e8b897895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410307803 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.410307803
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.4067985760
Short name T715
Test name
Test status
Simulation time 304381239149 ps
CPU time 1837.62 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 07:15:50 PM PDT 24
Peak memory 227700 kb
Host smart-0ed6801d-d8a2-4511-8eee-3948e455338a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067985760 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.4067985760
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.827116350
Short name T604
Test name
Test status
Simulation time 24899734 ps
CPU time 1.11 seconds
Started Jul 30 06:45:18 PM PDT 24
Finished Jul 30 06:45:20 PM PDT 24
Peak memory 220060 kb
Host smart-c8aab564-66f6-4b80-b004-42dc2605908e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827116350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.827116350
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1821962914
Short name T947
Test name
Test status
Simulation time 24023776 ps
CPU time 0.87 seconds
Started Jul 30 06:45:08 PM PDT 24
Finished Jul 30 06:45:09 PM PDT 24
Peak memory 206672 kb
Host smart-b5255149-18f2-4af8-9191-d53c1c16a6b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821962914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1821962914
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2332258845
Short name T221
Test name
Test status
Simulation time 14670886 ps
CPU time 1.01 seconds
Started Jul 30 06:45:10 PM PDT 24
Finished Jul 30 06:45:11 PM PDT 24
Peak memory 216396 kb
Host smart-17aa53d1-4c6a-402c-8c47-f3db8132755a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332258845 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2332258845
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2292357415
Short name T593
Test name
Test status
Simulation time 119635124 ps
CPU time 1.1 seconds
Started Jul 30 06:45:03 PM PDT 24
Finished Jul 30 06:45:04 PM PDT 24
Peak memory 218340 kb
Host smart-1b1d7279-59e0-4186-bac8-1954972a6c5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292357415 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2292357415
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2045946367
Short name T592
Test name
Test status
Simulation time 30310640 ps
CPU time 1.16 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 219728 kb
Host smart-778c5f0e-e5ba-4428-8558-39a8c16219fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045946367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2045946367
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3593506266
Short name T488
Test name
Test status
Simulation time 84275767 ps
CPU time 1.34 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 217280 kb
Host smart-cf83103c-c49d-48da-babb-9615a19be46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593506266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3593506266
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2432913183
Short name T14
Test name
Test status
Simulation time 22951086 ps
CPU time 1.22 seconds
Started Jul 30 06:45:09 PM PDT 24
Finished Jul 30 06:45:10 PM PDT 24
Peak memory 224068 kb
Host smart-d2f85d8e-3ada-49ae-8335-a6e702cfc5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432913183 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2432913183
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1024468227
Short name T691
Test name
Test status
Simulation time 47200978 ps
CPU time 0.93 seconds
Started Jul 30 06:45:05 PM PDT 24
Finished Jul 30 06:45:06 PM PDT 24
Peak memory 215280 kb
Host smart-4fa22e56-bd2a-491d-98c8-4ffaf7cbd688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024468227 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1024468227
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.498797931
Short name T401
Test name
Test status
Simulation time 513018813 ps
CPU time 5.01 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 215252 kb
Host smart-eb1011fe-0b4c-44a3-b3bf-c57aff810f1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498797931 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.498797931
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.172056700
Short name T406
Test name
Test status
Simulation time 168449378564 ps
CPU time 1093.79 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 07:03:26 PM PDT 24
Peak memory 223844 kb
Host smart-645213a5-39b2-49d1-970e-7bb64e6d3127
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172056700 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.172056700
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3100438064
Short name T822
Test name
Test status
Simulation time 40538359 ps
CPU time 1.18 seconds
Started Jul 30 06:44:58 PM PDT 24
Finished Jul 30 06:45:00 PM PDT 24
Peak memory 218552 kb
Host smart-383608d2-64d5-469e-bae6-3530cc81464b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100438064 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3100438064
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3766237726
Short name T649
Test name
Test status
Simulation time 86254494 ps
CPU time 0.98 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 206744 kb
Host smart-3dbe30c5-9cdc-42e9-ba80-f5f519dadd86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766237726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3766237726
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3091288348
Short name T806
Test name
Test status
Simulation time 78595819 ps
CPU time 0.88 seconds
Started Jul 30 06:45:10 PM PDT 24
Finished Jul 30 06:45:11 PM PDT 24
Peak memory 216348 kb
Host smart-577a308b-6593-473d-87ea-f3ff333a2045
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091288348 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3091288348
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.133607256
Short name T100
Test name
Test status
Simulation time 33200545 ps
CPU time 1.16 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 218396 kb
Host smart-f51b55a6-547d-4f50-8a54-4856bc4ca337
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133607256 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.133607256
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2742967693
Short name T192
Test name
Test status
Simulation time 20335883 ps
CPU time 1.04 seconds
Started Jul 30 06:45:23 PM PDT 24
Finished Jul 30 06:45:24 PM PDT 24
Peak memory 218460 kb
Host smart-e8ea0cc9-43ff-4a48-9151-54895faf6f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742967693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2742967693
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3209902042
Short name T482
Test name
Test status
Simulation time 82433897 ps
CPU time 1.45 seconds
Started Jul 30 06:45:06 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 218464 kb
Host smart-1c356d74-09ee-43d1-9e90-dbcb6991b012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209902042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3209902042
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1493702679
Short name T281
Test name
Test status
Simulation time 32585056 ps
CPU time 0.95 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 215532 kb
Host smart-75d7099c-02c2-4ac2-8aa7-07aee2b6ccc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493702679 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1493702679
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.356637120
Short name T904
Test name
Test status
Simulation time 31682880 ps
CPU time 0.97 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:14 PM PDT 24
Peak memory 215344 kb
Host smart-cc499a91-f5d4-424c-9be6-3139e6f036c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356637120 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.356637120
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.4102313647
Short name T585
Test name
Test status
Simulation time 120753679 ps
CPU time 1.15 seconds
Started Jul 30 06:45:18 PM PDT 24
Finished Jul 30 06:45:20 PM PDT 24
Peak memory 207068 kb
Host smart-470978bc-3d23-4129-bfbe-e4f08aed59a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102313647 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.4102313647
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3550180690
Short name T69
Test name
Test status
Simulation time 101678141277 ps
CPU time 1364.88 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 07:07:59 PM PDT 24
Peak memory 224716 kb
Host smart-a1c97105-f076-4a0d-b5e7-4c21f4b69142
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550180690 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3550180690
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.664639864
Short name T914
Test name
Test status
Simulation time 183410665 ps
CPU time 1.2 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 218396 kb
Host smart-6ac07dce-03b5-4231-a946-32aa5002a323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664639864 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.664639864
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1658720316
Short name T520
Test name
Test status
Simulation time 45212108 ps
CPU time 0.93 seconds
Started Jul 30 06:45:06 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 206720 kb
Host smart-23397a2b-8677-4760-a0b7-a12861973215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658720316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1658720316
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.364017972
Short name T195
Test name
Test status
Simulation time 29364439 ps
CPU time 0.86 seconds
Started Jul 30 06:45:04 PM PDT 24
Finished Jul 30 06:45:05 PM PDT 24
Peak memory 216176 kb
Host smart-45a690b7-73e6-485f-90f2-966f299d61de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364017972 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.364017972
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.180547417
Short name T102
Test name
Test status
Simulation time 79956958 ps
CPU time 1.26 seconds
Started Jul 30 06:45:06 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 217008 kb
Host smart-67832d4d-6202-401c-a1ab-810942a39165
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180547417 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.180547417
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1253924101
Short name T48
Test name
Test status
Simulation time 133564238 ps
CPU time 1.08 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 225772 kb
Host smart-7be245a6-1a71-444f-a4ef-4bd49e6f31a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253924101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1253924101
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2626870963
Short name T645
Test name
Test status
Simulation time 39335872 ps
CPU time 1.56 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 218636 kb
Host smart-69794420-93e9-41d3-bcd3-c082c2d7fe47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626870963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2626870963
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1690183756
Short name T92
Test name
Test status
Simulation time 20052246 ps
CPU time 1.09 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 215868 kb
Host smart-4407ea66-b9c2-4e6b-a9ac-cabe73e8f9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690183756 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1690183756
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.926110267
Short name T347
Test name
Test status
Simulation time 21792958 ps
CPU time 1.01 seconds
Started Jul 30 06:45:23 PM PDT 24
Finished Jul 30 06:45:24 PM PDT 24
Peak memory 215360 kb
Host smart-a5c91d70-1ec6-48a3-9f1e-3ff87ba5029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926110267 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.926110267
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.134978735
Short name T620
Test name
Test status
Simulation time 181465976 ps
CPU time 1.7 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 217168 kb
Host smart-9eaef388-9bdc-4642-9614-010eb6a9aad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134978735 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.134978735
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2287731409
Short name T562
Test name
Test status
Simulation time 156675640138 ps
CPU time 678.4 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:56:32 PM PDT 24
Peak memory 222100 kb
Host smart-b1bf048c-0819-4706-8e09-f7d9903c4036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287731409 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2287731409
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3030400570
Short name T578
Test name
Test status
Simulation time 71857135 ps
CPU time 1.08 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 219412 kb
Host smart-aecf0a95-793b-476d-bb8f-f02421e6cbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030400570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3030400570
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.526716041
Short name T570
Test name
Test status
Simulation time 16449950 ps
CPU time 0.96 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 206696 kb
Host smart-b98691bf-729d-470d-ad33-739d5f6530fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526716041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.526716041
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2574334692
Short name T184
Test name
Test status
Simulation time 26505055 ps
CPU time 0.82 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 215396 kb
Host smart-56e8563b-56ae-4ed9-bfe3-fbc95a515df0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574334692 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2574334692
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3352997804
Short name T502
Test name
Test status
Simulation time 113866726 ps
CPU time 1.27 seconds
Started Jul 30 06:45:21 PM PDT 24
Finished Jul 30 06:45:23 PM PDT 24
Peak memory 216768 kb
Host smart-c0211e6c-a736-45dc-9993-88815fec0894
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352997804 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3352997804
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2204868498
Short name T58
Test name
Test status
Simulation time 37024115 ps
CPU time 0.88 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 219452 kb
Host smart-b022c302-8af1-4dfe-bb2d-169e9d3a67b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204868498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2204868498
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.883156648
Short name T709
Test name
Test status
Simulation time 67950393 ps
CPU time 1.14 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 218728 kb
Host smart-51e99eff-2f62-413d-92f5-ec19d58ae4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883156648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.883156648
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3517056050
Short name T91
Test name
Test status
Simulation time 27910386 ps
CPU time 0.96 seconds
Started Jul 30 06:45:21 PM PDT 24
Finished Jul 30 06:45:22 PM PDT 24
Peak memory 215964 kb
Host smart-d7eb8dc5-db1f-4f00-957c-fec60b6bec71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517056050 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3517056050
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3432571361
Short name T392
Test name
Test status
Simulation time 17510781 ps
CPU time 1.05 seconds
Started Jul 30 06:45:18 PM PDT 24
Finished Jul 30 06:45:19 PM PDT 24
Peak memory 215272 kb
Host smart-3b5994cb-92ab-45f9-a653-baa62df4b9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432571361 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3432571361
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2462290520
Short name T506
Test name
Test status
Simulation time 71734843 ps
CPU time 1.99 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 215280 kb
Host smart-4cc288c2-f865-4266-a2d8-73f6d70f5776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462290520 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2462290520
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3626653681
Short name T228
Test name
Test status
Simulation time 137630539036 ps
CPU time 728.82 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:57:24 PM PDT 24
Peak memory 223672 kb
Host smart-b37fa7a8-97eb-45b4-b5ed-e0807c60c20e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626653681 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3626653681
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3613729427
Short name T76
Test name
Test status
Simulation time 36794883 ps
CPU time 1.16 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 219524 kb
Host smart-22b45ad9-7bed-4bd1-9c9a-1993d27af40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613729427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3613729427
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3318074785
Short name T437
Test name
Test status
Simulation time 61881705 ps
CPU time 0.92 seconds
Started Jul 30 06:45:19 PM PDT 24
Finished Jul 30 06:45:20 PM PDT 24
Peak memory 206728 kb
Host smart-d9cbbdf5-29a6-421c-8983-4b2f32b6cb36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318074785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3318074785
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1390376333
Short name T109
Test name
Test status
Simulation time 11016894 ps
CPU time 0.91 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 216200 kb
Host smart-62ce945e-5bdb-43a4-b822-3a53aab6278a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390376333 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1390376333
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1989374748
Short name T53
Test name
Test status
Simulation time 29847513 ps
CPU time 1.12 seconds
Started Jul 30 06:45:18 PM PDT 24
Finished Jul 30 06:45:19 PM PDT 24
Peak memory 216760 kb
Host smart-896a5120-8013-41fe-913f-56637b47ac55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989374748 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1989374748
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3192060889
Short name T660
Test name
Test status
Simulation time 18680482 ps
CPU time 1.17 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:26 PM PDT 24
Peak memory 218544 kb
Host smart-1ad86caf-e7f0-4af8-b77a-c85e1049bc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192060889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3192060889
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3473203689
Short name T409
Test name
Test status
Simulation time 48132373 ps
CPU time 1.92 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 220108 kb
Host smart-9ed37510-03fb-4412-8dc6-989b3656a91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473203689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3473203689
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2286378859
Short name T676
Test name
Test status
Simulation time 24601167 ps
CPU time 1.09 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 223984 kb
Host smart-7ee9cbcb-3a34-49db-b386-67cf3e7056b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286378859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2286378859
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.831109104
Short name T381
Test name
Test status
Simulation time 48171946 ps
CPU time 0.96 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 215360 kb
Host smart-a51b8dc9-9357-4dcc-8eb7-fa685e43f079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831109104 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.831109104
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3993625273
Short name T504
Test name
Test status
Simulation time 62483321 ps
CPU time 1.44 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 215288 kb
Host smart-1611d9ef-3163-4973-832d-b5684204c111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993625273 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3993625273
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4004638932
Short name T230
Test name
Test status
Simulation time 74193167017 ps
CPU time 423.13 seconds
Started Jul 30 06:45:25 PM PDT 24
Finished Jul 30 06:52:28 PM PDT 24
Peak memory 217976 kb
Host smart-4358c422-061f-4e8d-b4b7-69fa34fa683f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004638932 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.4004638932
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1889978757
Short name T980
Test name
Test status
Simulation time 23404276 ps
CPU time 1.09 seconds
Started Jul 30 06:45:09 PM PDT 24
Finished Jul 30 06:45:10 PM PDT 24
Peak memory 219620 kb
Host smart-edda3e32-85ee-4be6-909b-74fe4b62e2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889978757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1889978757
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1561370095
Short name T851
Test name
Test status
Simulation time 187564442 ps
CPU time 0.91 seconds
Started Jul 30 06:45:22 PM PDT 24
Finished Jul 30 06:45:23 PM PDT 24
Peak memory 206688 kb
Host smart-ee405f1e-6d1e-4df5-9bbe-6431fdc169e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561370095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1561370095
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1791997999
Short name T976
Test name
Test status
Simulation time 18855634 ps
CPU time 0.83 seconds
Started Jul 30 06:45:11 PM PDT 24
Finished Jul 30 06:45:12 PM PDT 24
Peak memory 215828 kb
Host smart-dade757c-af45-4074-ba8b-d39773d088f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791997999 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1791997999
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1719244759
Short name T664
Test name
Test status
Simulation time 34527051 ps
CPU time 1.32 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 216620 kb
Host smart-65114c4f-941c-4442-b2ec-88d81a984cf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719244759 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1719244759
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3116062895
Short name T382
Test name
Test status
Simulation time 22722916 ps
CPU time 1.1 seconds
Started Jul 30 06:45:18 PM PDT 24
Finished Jul 30 06:45:19 PM PDT 24
Peak memory 218548 kb
Host smart-4ab6e1d4-e98b-493b-bbb2-590ed0542ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116062895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3116062895
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2875086420
Short name T839
Test name
Test status
Simulation time 49496537 ps
CPU time 1.59 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 217300 kb
Host smart-4221695a-b445-4268-873a-66ea91774bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875086420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2875086420
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3709743191
Short name T838
Test name
Test status
Simulation time 73753710 ps
CPU time 0.79 seconds
Started Jul 30 06:45:21 PM PDT 24
Finished Jul 30 06:45:22 PM PDT 24
Peak memory 215432 kb
Host smart-a1d5afa7-d165-4bca-81f5-6670a77be28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709743191 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3709743191
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2345219227
Short name T469
Test name
Test status
Simulation time 248967356 ps
CPU time 0.96 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:19 PM PDT 24
Peak memory 215164 kb
Host smart-fe996a5d-0d7c-47a8-bbcb-7a2037db7538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345219227 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2345219227
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2540873048
Short name T646
Test name
Test status
Simulation time 1256875505 ps
CPU time 4 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:29 PM PDT 24
Peak memory 219824 kb
Host smart-286d1170-8df7-4410-af0e-c138aa1c6370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540873048 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2540873048
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1884899151
Short name T138
Test name
Test status
Simulation time 289699813241 ps
CPU time 2000.14 seconds
Started Jul 30 06:45:05 PM PDT 24
Finished Jul 30 07:18:25 PM PDT 24
Peak memory 227152 kb
Host smart-a9e4a7ec-e5c8-49e1-b9ae-0ba84ea545e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884899151 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1884899151
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.425610228
Short name T154
Test name
Test status
Simulation time 24501008 ps
CPU time 1.17 seconds
Started Jul 30 06:44:27 PM PDT 24
Finished Jul 30 06:44:29 PM PDT 24
Peak memory 220176 kb
Host smart-43d66070-1950-4da2-bcb9-220bfd41ffa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425610228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.425610228
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1930971542
Short name T989
Test name
Test status
Simulation time 22533532 ps
CPU time 1.05 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 206928 kb
Host smart-09155555-9f6c-4dd6-a461-c75411ac131d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930971542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1930971542
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2644486054
Short name T681
Test name
Test status
Simulation time 37399578 ps
CPU time 1.15 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 218344 kb
Host smart-f120ee98-40b5-43aa-882d-54205e5cd6de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644486054 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2644486054
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1866831121
Short name T521
Test name
Test status
Simulation time 67247326 ps
CPU time 1.13 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 225484 kb
Host smart-42a4d822-a913-4063-8b8b-10253a87f5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866831121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1866831121
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.406562173
Short name T903
Test name
Test status
Simulation time 50179865 ps
CPU time 1.46 seconds
Started Jul 30 06:44:13 PM PDT 24
Finished Jul 30 06:44:15 PM PDT 24
Peak memory 218716 kb
Host smart-12384781-5b81-435b-a8c5-772e6864adde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406562173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.406562173
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1193247006
Short name T447
Test name
Test status
Simulation time 47174267 ps
CPU time 0.86 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 215300 kb
Host smart-6de3b278-734b-42a6-90e7-9c0b5c8e1fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193247006 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1193247006
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1236017486
Short name T249
Test name
Test status
Simulation time 27728968 ps
CPU time 0.98 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 207012 kb
Host smart-e810f51a-7728-4e40-bae5-fb146ab7d9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236017486 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1236017486
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1730664569
Short name T531
Test name
Test status
Simulation time 17288067 ps
CPU time 0.97 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 215236 kb
Host smart-079c263e-f0a0-4135-9106-e5b971120663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730664569 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1730664569
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1022927426
Short name T700
Test name
Test status
Simulation time 286947609 ps
CPU time 3.13 seconds
Started Jul 30 06:44:17 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 215276 kb
Host smart-9803ec0d-0b9a-41e1-9fc7-95fb0dcf816d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022927426 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1022927426
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2292023364
Short name T237
Test name
Test status
Simulation time 91252466369 ps
CPU time 1049.42 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 07:01:56 PM PDT 24
Peak memory 222688 kb
Host smart-5526e6d8-37b2-465c-bb3d-6150cdfb1c29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292023364 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2292023364
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.75856337
Short name T213
Test name
Test status
Simulation time 249685173 ps
CPU time 1.45 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 215408 kb
Host smart-94e21cdf-d82e-4706-a2a7-2b7016d02c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75856337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.75856337
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.4011181153
Short name T407
Test name
Test status
Simulation time 50286770 ps
CPU time 0.79 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:14 PM PDT 24
Peak memory 218468 kb
Host smart-62d9815d-2f28-4ecb-9cf1-a5be170b3c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011181153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.4011181153
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3970937306
Short name T379
Test name
Test status
Simulation time 29498509 ps
CPU time 1.22 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 217312 kb
Host smart-9f870110-7ac2-4c5f-8832-05f7ef6d4e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970937306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3970937306
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3584696873
Short name T764
Test name
Test status
Simulation time 40492678 ps
CPU time 1.17 seconds
Started Jul 30 06:45:10 PM PDT 24
Finished Jul 30 06:45:12 PM PDT 24
Peak memory 218548 kb
Host smart-eef4741c-8ce4-46e1-94b7-ef7f35f3e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584696873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3584696873
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.2245883385
Short name T151
Test name
Test status
Simulation time 26119518 ps
CPU time 1.3 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:14 PM PDT 24
Peak memory 229780 kb
Host smart-159e6942-5451-4fe8-9a43-0e1203c048c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245883385 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2245883385
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2238738528
Short name T244
Test name
Test status
Simulation time 80038618 ps
CPU time 1.14 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 217428 kb
Host smart-681d2f4a-ecba-4cf3-a1d0-16b4fc705895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238738528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2238738528
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.2388588558
Short name T164
Test name
Test status
Simulation time 30391877 ps
CPU time 1.31 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:19 PM PDT 24
Peak memory 219700 kb
Host smart-07d942f6-4c58-4538-8d37-fb39ccbbac22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388588558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.2388588558
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.2588941828
Short name T483
Test name
Test status
Simulation time 23904412 ps
CPU time 1.03 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:26 PM PDT 24
Peak memory 223912 kb
Host smart-9b9d003b-abaa-43dd-ba0f-2bc86b57f0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588941828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2588941828
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.4162966343
Short name T280
Test name
Test status
Simulation time 38311644 ps
CPU time 1.37 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 217200 kb
Host smart-5abefde9-58be-430f-b005-590e0e711ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162966343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.4162966343
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.1132405412
Short name T524
Test name
Test status
Simulation time 36909384 ps
CPU time 1.21 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 219832 kb
Host smart-c25a3f89-eef0-49f8-85a4-c63ba238a44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132405412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.1132405412
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.3868296353
Short name T589
Test name
Test status
Simulation time 32416690 ps
CPU time 1.12 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 224000 kb
Host smart-0beed45e-9834-4a79-9532-031f90a2ecd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868296353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3868296353
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2249678583
Short name T545
Test name
Test status
Simulation time 96357706 ps
CPU time 1.04 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 217488 kb
Host smart-844271ec-f7b6-4b93-a2f9-58f8d95abbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249678583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2249678583
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.2743832558
Short name T304
Test name
Test status
Simulation time 68751992 ps
CPU time 1.12 seconds
Started Jul 30 06:45:21 PM PDT 24
Finished Jul 30 06:45:23 PM PDT 24
Peak memory 219396 kb
Host smart-56d50bb9-3a77-487f-9e56-f5f81ecc5217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743832558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2743832558
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.1113128922
Short name T987
Test name
Test status
Simulation time 20756423 ps
CPU time 1.04 seconds
Started Jul 30 06:45:07 PM PDT 24
Finished Jul 30 06:45:08 PM PDT 24
Peak memory 224104 kb
Host smart-4faf32b6-30bf-4b16-9fff-8ef0ead9c711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113128922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1113128922
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1028599493
Short name T20
Test name
Test status
Simulation time 63492873 ps
CPU time 2.49 seconds
Started Jul 30 06:45:19 PM PDT 24
Finished Jul 30 06:45:22 PM PDT 24
Peak memory 217484 kb
Host smart-e5f261dd-4c9e-4afc-9766-f0dc73bc76e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028599493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1028599493
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.3355033258
Short name T415
Test name
Test status
Simulation time 33254845 ps
CPU time 1.14 seconds
Started Jul 30 06:46:47 PM PDT 24
Finished Jul 30 06:46:48 PM PDT 24
Peak memory 220736 kb
Host smart-a0a8d687-82e2-4780-8ca7-c2a3044a73bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355033258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.3355033258
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2635027108
Short name T479
Test name
Test status
Simulation time 34343285 ps
CPU time 0.95 seconds
Started Jul 30 06:45:23 PM PDT 24
Finished Jul 30 06:45:24 PM PDT 24
Peak memory 218552 kb
Host smart-d12a8560-9ac0-4f77-bbcf-523c619a5ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635027108 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2635027108
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3633369424
Short name T721
Test name
Test status
Simulation time 36525970 ps
CPU time 1.45 seconds
Started Jul 30 06:45:10 PM PDT 24
Finished Jul 30 06:45:12 PM PDT 24
Peak memory 218496 kb
Host smart-295a5385-e60d-45ce-a05b-5a3a09b28218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633369424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3633369424
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3403792061
Short name T126
Test name
Test status
Simulation time 28422391 ps
CPU time 1.05 seconds
Started Jul 30 06:45:21 PM PDT 24
Finished Jul 30 06:45:23 PM PDT 24
Peak memory 224100 kb
Host smart-67446060-61b5-4ea3-b8a2-a41662d2608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403792061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3403792061
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3975557967
Short name T632
Test name
Test status
Simulation time 71724667 ps
CPU time 1.06 seconds
Started Jul 30 06:45:21 PM PDT 24
Finished Jul 30 06:45:23 PM PDT 24
Peak memory 219836 kb
Host smart-fc72820a-b470-45a7-b703-d65e2db8dfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975557967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3975557967
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.2670642840
Short name T950
Test name
Test status
Simulation time 122530543 ps
CPU time 1.21 seconds
Started Jul 30 06:46:41 PM PDT 24
Finished Jul 30 06:46:43 PM PDT 24
Peak memory 219588 kb
Host smart-16589bd4-8a24-48dd-b6c4-9af5de316312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670642840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2670642840
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.1893602275
Short name T7
Test name
Test status
Simulation time 33089211 ps
CPU time 1.09 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 220572 kb
Host smart-c9cef7c7-950e-4154-af85-feff00ec81df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893602275 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1893602275
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2216201513
Short name T549
Test name
Test status
Simulation time 64408910 ps
CPU time 1.07 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 219668 kb
Host smart-8ec920cd-6e5b-4993-99d9-54305fe46ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216201513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2216201513
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.921329965
Short name T728
Test name
Test status
Simulation time 69042021 ps
CPU time 1.08 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 219776 kb
Host smart-2585be45-1a0a-4708-bec1-d0da6ca298f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921329965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.921329965
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.1054175876
Short name T148
Test name
Test status
Simulation time 49306452 ps
CPU time 0.98 seconds
Started Jul 30 06:45:09 PM PDT 24
Finished Jul 30 06:45:10 PM PDT 24
Peak memory 219384 kb
Host smart-75aab3ce-10e4-47b7-b2dd-ae161703ff6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054175876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1054175876
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1582557588
Short name T338
Test name
Test status
Simulation time 71593305 ps
CPU time 1.08 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 217204 kb
Host smart-4b35eb84-881a-4260-956f-f58d9ae252a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582557588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1582557588
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1453136443
Short name T185
Test name
Test status
Simulation time 87218690 ps
CPU time 1.16 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:14 PM PDT 24
Peak memory 221088 kb
Host smart-fdd97fd7-6dc8-461c-87e5-db775ccb2f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453136443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1453136443
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2415795911
Short name T817
Test name
Test status
Simulation time 30272037 ps
CPU time 1.33 seconds
Started Jul 30 06:45:09 PM PDT 24
Finished Jul 30 06:45:11 PM PDT 24
Peak memory 225700 kb
Host smart-f17f029e-2d0f-4f88-b9da-3a82cc0ce258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415795911 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2415795911
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.720695919
Short name T486
Test name
Test status
Simulation time 48937927 ps
CPU time 1.14 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 215260 kb
Host smart-761bebe2-e00c-4277-9890-f760006b6efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720695919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.720695919
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1392502610
Short name T959
Test name
Test status
Simulation time 27608027 ps
CPU time 1.26 seconds
Started Jul 30 06:44:13 PM PDT 24
Finished Jul 30 06:44:15 PM PDT 24
Peak memory 219160 kb
Host smart-95e923db-44d8-4c25-8a48-16990a408fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392502610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1392502610
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3682458814
Short name T357
Test name
Test status
Simulation time 55249515 ps
CPU time 0.94 seconds
Started Jul 30 06:44:14 PM PDT 24
Finished Jul 30 06:44:16 PM PDT 24
Peak memory 214892 kb
Host smart-192bf157-6d19-4995-8808-cc567c1bf6c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682458814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3682458814
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.806253767
Short name T103
Test name
Test status
Simulation time 11913455 ps
CPU time 0.88 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 216188 kb
Host smart-c6cecbd8-7b46-4fa1-b5a0-0729a9a7e4a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806253767 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.806253767
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1245150915
Short name T104
Test name
Test status
Simulation time 49856257 ps
CPU time 1.16 seconds
Started Jul 30 06:44:18 PM PDT 24
Finished Jul 30 06:44:19 PM PDT 24
Peak memory 216996 kb
Host smart-85da0da0-7462-4028-a236-6e08c18b2979
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245150915 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1245150915
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1369596320
Short name T863
Test name
Test status
Simulation time 19062810 ps
CPU time 0.99 seconds
Started Jul 30 06:44:18 PM PDT 24
Finished Jul 30 06:44:19 PM PDT 24
Peak memory 218624 kb
Host smart-f892f6df-aeb9-4314-a0a4-a214e478f6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369596320 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1369596320
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3676616793
Short name T643
Test name
Test status
Simulation time 34554655 ps
CPU time 1.43 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 217316 kb
Host smart-1359396a-4198-49f3-ba25-00b40e209f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676616793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3676616793
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.410765918
Short name T377
Test name
Test status
Simulation time 39475007 ps
CPU time 0.9 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 215356 kb
Host smart-a691d2b8-0dc0-43ca-871b-8e5139e1947c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410765918 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.410765918
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.2854981396
Short name T81
Test name
Test status
Simulation time 18801916 ps
CPU time 1.03 seconds
Started Jul 30 06:44:18 PM PDT 24
Finished Jul 30 06:44:19 PM PDT 24
Peak memory 207280 kb
Host smart-3a1596fc-b9e0-43ef-8680-513745f1bea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854981396 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2854981396
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.384602528
Short name T503
Test name
Test status
Simulation time 28554769 ps
CPU time 0.91 seconds
Started Jul 30 06:44:25 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 215264 kb
Host smart-1f48a72c-81c8-48b7-b8eb-48781b22bad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384602528 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.384602528
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1266657900
Short name T637
Test name
Test status
Simulation time 177644395 ps
CPU time 1.32 seconds
Started Jul 30 06:44:15 PM PDT 24
Finished Jul 30 06:44:16 PM PDT 24
Peak memory 217208 kb
Host smart-368275ed-f32b-4d88-9bee-9dcf33339f6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266657900 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1266657900
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3432071837
Short name T378
Test name
Test status
Simulation time 21569664176 ps
CPU time 562.47 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:53:44 PM PDT 24
Peak memory 217700 kb
Host smart-6d599722-9412-4e45-877c-166d0c2c3d62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432071837 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3432071837
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.694282214
Short name T596
Test name
Test status
Simulation time 121941543 ps
CPU time 1.25 seconds
Started Jul 30 06:45:10 PM PDT 24
Finished Jul 30 06:45:12 PM PDT 24
Peak memory 218512 kb
Host smart-9677e764-1c32-4cfb-832c-1251ce8f7c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694282214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.694282214
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1877587238
Short name T130
Test name
Test status
Simulation time 29852467 ps
CPU time 1.23 seconds
Started Jul 30 06:45:09 PM PDT 24
Finished Jul 30 06:45:10 PM PDT 24
Peak memory 219436 kb
Host smart-850dfe1f-500a-428e-96e6-199c3c67626a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877587238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1877587238
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2734695567
Short name T384
Test name
Test status
Simulation time 35015400 ps
CPU time 1.38 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:26 PM PDT 24
Peak memory 218556 kb
Host smart-c111ae05-5338-4a36-aedd-13a0e76f7f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734695567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2734695567
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1052408944
Short name T158
Test name
Test status
Simulation time 35179202 ps
CPU time 1.36 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 221632 kb
Host smart-4839c7e4-dffb-4ffe-8b7d-bf0eceb3b0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052408944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1052408944
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1665287660
Short name T813
Test name
Test status
Simulation time 49465241 ps
CPU time 1.05 seconds
Started Jul 30 06:45:06 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 220596 kb
Host smart-886506d1-f06e-4a91-8591-f4437c37040e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665287660 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1665287660
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2171801960
Short name T329
Test name
Test status
Simulation time 44096201 ps
CPU time 1.42 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 218668 kb
Host smart-faae5950-6bed-4353-b7d3-81a7412aad7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171801960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2171801960
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.1526952194
Short name T290
Test name
Test status
Simulation time 290360252 ps
CPU time 1.25 seconds
Started Jul 30 06:45:49 PM PDT 24
Finished Jul 30 06:45:51 PM PDT 24
Peak memory 219444 kb
Host smart-0ea1dd03-e01d-44c2-ad63-c3e4c7af3c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526952194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1526952194
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.3560051076
Short name T101
Test name
Test status
Simulation time 19864989 ps
CPU time 0.99 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 218532 kb
Host smart-9414d28b-4935-447a-988c-f329b2a8b380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560051076 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3560051076
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3073667724
Short name T758
Test name
Test status
Simulation time 62305499 ps
CPU time 1.1 seconds
Started Jul 30 06:45:04 PM PDT 24
Finished Jul 30 06:45:05 PM PDT 24
Peak memory 218900 kb
Host smart-1da9f08c-6793-45fe-88bf-5b15dfbf2a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073667724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3073667724
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.3588389285
Short name T243
Test name
Test status
Simulation time 44532925 ps
CPU time 1.19 seconds
Started Jul 30 06:45:07 PM PDT 24
Finished Jul 30 06:45:08 PM PDT 24
Peak memory 215676 kb
Host smart-6f643671-8a06-4426-8d76-7bd837a343d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588389285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3588389285
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.519541286
Short name T167
Test name
Test status
Simulation time 29451481 ps
CPU time 1.02 seconds
Started Jul 30 06:45:21 PM PDT 24
Finished Jul 30 06:45:23 PM PDT 24
Peak memory 218476 kb
Host smart-d5c4e663-b634-4c50-a4b7-d62aff3bf90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519541286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.519541286
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2227888554
Short name T31
Test name
Test status
Simulation time 35125729 ps
CPU time 1.45 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:14 PM PDT 24
Peak memory 217484 kb
Host smart-48b6ceb0-bf98-4061-8687-29c29c71e004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227888554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2227888554
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.377308856
Short name T522
Test name
Test status
Simulation time 87892339 ps
CPU time 1.12 seconds
Started Jul 30 06:45:19 PM PDT 24
Finished Jul 30 06:45:20 PM PDT 24
Peak memory 219512 kb
Host smart-6306e388-fec5-45f8-9941-462ea3d7d966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377308856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.377308856
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.499246806
Short name T28
Test name
Test status
Simulation time 27963774 ps
CPU time 1.21 seconds
Started Jul 30 06:46:46 PM PDT 24
Finished Jul 30 06:46:47 PM PDT 24
Peak memory 215404 kb
Host smart-5ea66c43-2822-4a65-b477-46162e8d8b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499246806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.499246806
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.948685842
Short name T666
Test name
Test status
Simulation time 108593890 ps
CPU time 1.4 seconds
Started Jul 30 06:45:22 PM PDT 24
Finished Jul 30 06:45:23 PM PDT 24
Peak memory 218860 kb
Host smart-4d20b906-1fba-4b71-9472-c4ed7d026ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948685842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.948685842
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.1073619032
Short name T973
Test name
Test status
Simulation time 109077370 ps
CPU time 1.19 seconds
Started Jul 30 06:46:41 PM PDT 24
Finished Jul 30 06:46:43 PM PDT 24
Peak memory 218484 kb
Host smart-d3592720-ef93-4217-b01d-e6984aafd949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073619032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.1073619032
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.1424610621
Short name T370
Test name
Test status
Simulation time 33376408 ps
CPU time 0.85 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 218268 kb
Host smart-23e15df3-e206-41f6-b855-86c9180ee869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424610621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1424610621
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.65244404
Short name T941
Test name
Test status
Simulation time 216557473 ps
CPU time 1.04 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:21 PM PDT 24
Peak memory 217340 kb
Host smart-faf92b5e-e1e7-417a-be8a-2cfcba9e9aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65244404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.65244404
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.579045375
Short name T875
Test name
Test status
Simulation time 49603030 ps
CPU time 1.2 seconds
Started Jul 30 06:45:18 PM PDT 24
Finished Jul 30 06:45:20 PM PDT 24
Peak memory 219396 kb
Host smart-4ad9fb0c-76cc-411d-bd98-56ffbdd9488f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579045375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.579045375
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.819694245
Short name T160
Test name
Test status
Simulation time 31619847 ps
CPU time 1.02 seconds
Started Jul 30 06:46:30 PM PDT 24
Finished Jul 30 06:46:31 PM PDT 24
Peak memory 229636 kb
Host smart-8c030bb8-5d56-4c8e-a1f1-089b134fdde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819694245 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.819694245
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1568138041
Short name T393
Test name
Test status
Simulation time 364642018 ps
CPU time 1.13 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 217348 kb
Host smart-5fc7c63d-5216-442d-9746-255a98490ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568138041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1568138041
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.63212823
Short name T946
Test name
Test status
Simulation time 84368683 ps
CPU time 1.18 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:26 PM PDT 24
Peak memory 220592 kb
Host smart-ff762897-ab99-4e08-9059-e95a26096bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63212823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.63212823
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.407759552
Short name T131
Test name
Test status
Simulation time 26256529 ps
CPU time 1.06 seconds
Started Jul 30 06:46:42 PM PDT 24
Finished Jul 30 06:46:43 PM PDT 24
Peak memory 219596 kb
Host smart-581a4e81-6962-4421-b7ff-891cd26a5b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407759552 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.407759552
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2766274638
Short name T922
Test name
Test status
Simulation time 56917950 ps
CPU time 1.23 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 218652 kb
Host smart-c99c25fe-ae13-4ecd-bc21-2fdfcb4259bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766274638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2766274638
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1435249047
Short name T808
Test name
Test status
Simulation time 320181987 ps
CPU time 1.22 seconds
Started Jul 30 06:45:29 PM PDT 24
Finished Jul 30 06:45:30 PM PDT 24
Peak memory 219412 kb
Host smart-41080f10-8c86-4214-9084-cf5f26997416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435249047 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1435249047
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.2790323789
Short name T6
Test name
Test status
Simulation time 35003568 ps
CPU time 1.11 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 217288 kb
Host smart-798aa74d-1392-4f56-af6f-23e71407e406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790323789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2790323789
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3989719754
Short name T667
Test name
Test status
Simulation time 40547276 ps
CPU time 1.43 seconds
Started Jul 30 06:45:27 PM PDT 24
Finished Jul 30 06:45:29 PM PDT 24
Peak memory 218436 kb
Host smart-4a6f895a-815b-4ef2-b519-d8660d73ca85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989719754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3989719754
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.2985763758
Short name T303
Test name
Test status
Simulation time 25203010 ps
CPU time 1.2 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:25 PM PDT 24
Peak memory 219236 kb
Host smart-fc88c50f-0ee4-407a-892b-3cad9e53aac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985763758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.2985763758
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2673233160
Short name T791
Test name
Test status
Simulation time 48304554 ps
CPU time 1.03 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:25 PM PDT 24
Peak memory 220540 kb
Host smart-82e916b7-3319-4abf-bac9-dbad3d2c70c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673233160 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2673233160
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1569911499
Short name T245
Test name
Test status
Simulation time 59554746 ps
CPU time 1.23 seconds
Started Jul 30 06:45:18 PM PDT 24
Finished Jul 30 06:45:20 PM PDT 24
Peak memory 218948 kb
Host smart-72fc1dbe-3e1a-4331-98e6-281c4a1fb549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569911499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1569911499
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3506235413
Short name T36
Test name
Test status
Simulation time 89147140 ps
CPU time 1.16 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 215676 kb
Host smart-90326080-9a8e-4f34-8760-e5944e951063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506235413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3506235413
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.264760185
Short name T825
Test name
Test status
Simulation time 50136253 ps
CPU time 0.93 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 206764 kb
Host smart-69803904-a49c-4f62-b755-317996222cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264760185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.264760185
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2926729095
Short name T536
Test name
Test status
Simulation time 163479969 ps
CPU time 1.02 seconds
Started Jul 30 06:44:23 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 216744 kb
Host smart-5e56585e-8776-45e1-94d2-5ed42e3e36fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926729095 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2926729095
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3896142171
Short name T622
Test name
Test status
Simulation time 37598761 ps
CPU time 1.57 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 225632 kb
Host smart-91e832d5-bc38-4693-8a52-fc93ce8112a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896142171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3896142171
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3316071002
Short name T465
Test name
Test status
Simulation time 109408875 ps
CPU time 1.69 seconds
Started Jul 30 06:44:32 PM PDT 24
Finished Jul 30 06:44:34 PM PDT 24
Peak memory 218488 kb
Host smart-bd239421-3223-4e73-9c81-65eb821c5308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316071002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3316071002
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1373038515
Short name T742
Test name
Test status
Simulation time 38078645 ps
CPU time 1.29 seconds
Started Jul 30 06:44:14 PM PDT 24
Finished Jul 30 06:44:15 PM PDT 24
Peak memory 215504 kb
Host smart-79652e6c-14c3-4f43-94e6-6c118ef129a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373038515 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1373038515
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3056574830
Short name T688
Test name
Test status
Simulation time 52148432 ps
CPU time 1.05 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 207144 kb
Host smart-02ca78d3-99cc-4008-9038-87dec3537629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056574830 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3056574830
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2793573317
Short name T708
Test name
Test status
Simulation time 50327692 ps
CPU time 0.94 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 215264 kb
Host smart-d5b9dc20-ba8b-4722-ba65-a67b596ca21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793573317 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2793573317
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.515825603
Short name T759
Test name
Test status
Simulation time 182809212 ps
CPU time 2.96 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 220212 kb
Host smart-80f8f9cc-a65a-4384-851c-d8ec90864d8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515825603 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.515825603
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3652109661
Short name T985
Test name
Test status
Simulation time 89342723321 ps
CPU time 718.4 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:56:19 PM PDT 24
Peak memory 219948 kb
Host smart-e4720fb1-8204-455a-820d-8e1fca2b190e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652109661 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3652109661
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.418337928
Short name T831
Test name
Test status
Simulation time 39402337 ps
CPU time 1.06 seconds
Started Jul 30 06:46:37 PM PDT 24
Finished Jul 30 06:46:38 PM PDT 24
Peak memory 218404 kb
Host smart-153df758-f491-4fb4-8650-334258e9a3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418337928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.418337928
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.1426346014
Short name T988
Test name
Test status
Simulation time 67349916 ps
CPU time 1.07 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:26 PM PDT 24
Peak memory 219916 kb
Host smart-21f1b655-0007-4934-a481-9490752a4008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426346014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1426346014
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.4294318272
Short name T473
Test name
Test status
Simulation time 106388266 ps
CPU time 1.33 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:25 PM PDT 24
Peak memory 218728 kb
Host smart-fbf193e0-2988-427c-819f-abeb35175c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294318272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.4294318272
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.842305629
Short name T169
Test name
Test status
Simulation time 34634955 ps
CPU time 1.19 seconds
Started Jul 30 06:45:26 PM PDT 24
Finished Jul 30 06:45:28 PM PDT 24
Peak memory 218624 kb
Host smart-111c5fe2-c4cd-41a0-8625-e32b00efea57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842305629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.842305629
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.1533528608
Short name T117
Test name
Test status
Simulation time 33780294 ps
CPU time 0.86 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:14 PM PDT 24
Peak memory 218516 kb
Host smart-1f349144-55b7-432e-8e24-4f00176eee01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533528608 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1533528608
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.4034683386
Short name T756
Test name
Test status
Simulation time 92099439 ps
CPU time 1.71 seconds
Started Jul 30 06:45:22 PM PDT 24
Finished Jul 30 06:45:24 PM PDT 24
Peak memory 218580 kb
Host smart-757c81bf-5260-4ae3-ac12-6ac2e679f1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034683386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.4034683386
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.3032354326
Short name T155
Test name
Test status
Simulation time 40034502 ps
CPU time 1.23 seconds
Started Jul 30 06:45:03 PM PDT 24
Finished Jul 30 06:45:04 PM PDT 24
Peak memory 219684 kb
Host smart-dc818a53-5990-42f0-9c7e-60a325d73bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032354326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.3032354326
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3676045442
Short name T146
Test name
Test status
Simulation time 62726382 ps
CPU time 1.14 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 229696 kb
Host smart-1f6bc0ad-8cc9-40a1-8e0a-2f8d3be557fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676045442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3676045442
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.869027148
Short name T140
Test name
Test status
Simulation time 48098485 ps
CPU time 1.24 seconds
Started Jul 30 06:46:36 PM PDT 24
Finished Jul 30 06:46:38 PM PDT 24
Peak memory 218732 kb
Host smart-b79f534b-761b-431b-a763-ca8426db2b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869027148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.869027148
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3045699642
Short name T551
Test name
Test status
Simulation time 26160534 ps
CPU time 1.08 seconds
Started Jul 30 06:45:18 PM PDT 24
Finished Jul 30 06:45:20 PM PDT 24
Peak memory 219240 kb
Host smart-0bb5c219-156e-4640-80ed-6198faad0405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045699642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3045699642
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3343282049
Short name T782
Test name
Test status
Simulation time 23902729 ps
CPU time 0.92 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 218528 kb
Host smart-cf1320a7-48c1-439c-badc-d460c4419cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343282049 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3343282049
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1394900691
Short name T750
Test name
Test status
Simulation time 46549695 ps
CPU time 1.28 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 218572 kb
Host smart-dcf5005c-bfe2-4cbf-ac84-193554c43e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394900691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1394900691
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2907512465
Short name T787
Test name
Test status
Simulation time 30121972 ps
CPU time 1.29 seconds
Started Jul 30 06:45:07 PM PDT 24
Finished Jul 30 06:45:08 PM PDT 24
Peak memory 220112 kb
Host smart-5726c518-d2f5-4a9a-9050-11082f6c0d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907512465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2907512465
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2551482712
Short name T150
Test name
Test status
Simulation time 26831640 ps
CPU time 1.19 seconds
Started Jul 30 06:46:43 PM PDT 24
Finished Jul 30 06:46:45 PM PDT 24
Peak memory 220512 kb
Host smart-3288812b-91e5-46af-bc4c-05b7bf9c43d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551482712 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2551482712
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2954342268
Short name T61
Test name
Test status
Simulation time 157289768 ps
CPU time 1.35 seconds
Started Jul 30 06:45:18 PM PDT 24
Finished Jul 30 06:45:20 PM PDT 24
Peak memory 218528 kb
Host smart-13a90f36-aba1-4efe-805d-f3d0cd4911a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954342268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2954342268
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.1139640266
Short name T940
Test name
Test status
Simulation time 30451041 ps
CPU time 1.18 seconds
Started Jul 30 06:46:16 PM PDT 24
Finished Jul 30 06:46:18 PM PDT 24
Peak memory 218212 kb
Host smart-88cf7f6f-24e2-4aa3-9deb-f178544c146f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139640266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1139640266
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.420665159
Short name T119
Test name
Test status
Simulation time 30625207 ps
CPU time 1.25 seconds
Started Jul 30 06:45:21 PM PDT 24
Finished Jul 30 06:45:23 PM PDT 24
Peak memory 219848 kb
Host smart-a87cc9f2-2f29-4583-8e23-d6191c0e6452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420665159 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.420665159
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1994522315
Short name T511
Test name
Test status
Simulation time 37698684 ps
CPU time 1.3 seconds
Started Jul 30 06:45:09 PM PDT 24
Finished Jul 30 06:45:10 PM PDT 24
Peak memory 215260 kb
Host smart-ce3d390a-d1cd-4c19-8858-5d7b17580ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994522315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1994522315
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.3884620768
Short name T27
Test name
Test status
Simulation time 80819892 ps
CPU time 1.11 seconds
Started Jul 30 06:45:06 PM PDT 24
Finished Jul 30 06:45:07 PM PDT 24
Peak memory 219704 kb
Host smart-7a5c7403-349b-4357-baac-ea350720333a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884620768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3884620768
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.4105375620
Short name T204
Test name
Test status
Simulation time 20256572 ps
CPU time 1.11 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 218704 kb
Host smart-ad046a18-9482-47d7-ad1e-903e2af8a75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105375620 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.4105375620
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3944883433
Short name T747
Test name
Test status
Simulation time 72228082 ps
CPU time 1.41 seconds
Started Jul 30 06:46:39 PM PDT 24
Finished Jul 30 06:46:41 PM PDT 24
Peak memory 219296 kb
Host smart-0d125c63-71e4-4cff-96cf-2330cecee940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944883433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3944883433
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.245715427
Short name T889
Test name
Test status
Simulation time 48838660 ps
CPU time 1.28 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 220244 kb
Host smart-d7e77d85-52e1-47dc-980b-83efad669d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245715427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.245715427
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3959084905
Short name T198
Test name
Test status
Simulation time 36777607 ps
CPU time 0.99 seconds
Started Jul 30 06:45:10 PM PDT 24
Finished Jul 30 06:45:11 PM PDT 24
Peak memory 223888 kb
Host smart-156ceb56-b866-4d9b-8f77-6faf87c4b5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959084905 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3959084905
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.551220182
Short name T924
Test name
Test status
Simulation time 36096023 ps
CPU time 1.23 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 218872 kb
Host smart-773868b2-b399-4f6f-98bb-e32fa0a30093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551220182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.551220182
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.3780302260
Short name T970
Test name
Test status
Simulation time 44154351 ps
CPU time 1.12 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 219708 kb
Host smart-830b0288-c665-4c7f-8998-5d0558e3eaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780302260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.3780302260
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2817939635
Short name T601
Test name
Test status
Simulation time 51541762 ps
CPU time 0.85 seconds
Started Jul 30 06:45:15 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 218324 kb
Host smart-853dcdd8-1073-45db-baa4-eb14ee88cf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817939635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2817939635
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1509967159
Short name T969
Test name
Test status
Simulation time 35925982 ps
CPU time 1.36 seconds
Started Jul 30 06:45:31 PM PDT 24
Finished Jul 30 06:45:33 PM PDT 24
Peak memory 218448 kb
Host smart-34dd221d-b78f-4fac-92b9-c54088bb8df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509967159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1509967159
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.2517714336
Short name T356
Test name
Test status
Simulation time 82359663 ps
CPU time 1.09 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 220464 kb
Host smart-047e14f4-2f82-4021-b93c-c153d3f85fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517714336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2517714336
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.1376090005
Short name T678
Test name
Test status
Simulation time 20752093 ps
CPU time 1.14 seconds
Started Jul 30 06:45:07 PM PDT 24
Finished Jul 30 06:45:08 PM PDT 24
Peak memory 219900 kb
Host smart-bc18160f-d378-48b5-ab52-0578f3011247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376090005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1376090005
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.890097385
Short name T68
Test name
Test status
Simulation time 42982643 ps
CPU time 1.45 seconds
Started Jul 30 06:45:26 PM PDT 24
Finished Jul 30 06:45:28 PM PDT 24
Peak memory 218468 kb
Host smart-8d484872-0c3d-40f3-b44c-5659b39db355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890097385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.890097385
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.574526122
Short name T429
Test name
Test status
Simulation time 74069528 ps
CPU time 1.35 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 219868 kb
Host smart-8df3924c-7d91-4364-99d0-8097020fca00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574526122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.574526122
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.158992818
Short name T351
Test name
Test status
Simulation time 15469861 ps
CPU time 0.9 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 214852 kb
Host smart-bc523fa9-85d0-4c84-a96a-51f8da316477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158992818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.158992818
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1195820179
Short name T810
Test name
Test status
Simulation time 12201043 ps
CPU time 0.86 seconds
Started Jul 30 06:44:15 PM PDT 24
Finished Jul 30 06:44:16 PM PDT 24
Peak memory 215516 kb
Host smart-5c2fa59d-7828-46c6-9939-70681320c4e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195820179 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1195820179
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2623156647
Short name T177
Test name
Test status
Simulation time 180938281 ps
CPU time 1.14 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 216948 kb
Host smart-144fbd72-660d-4b69-8023-ab38314aad45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623156647 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2623156647
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3021568780
Short name T954
Test name
Test status
Simulation time 30035162 ps
CPU time 0.88 seconds
Started Jul 30 06:44:14 PM PDT 24
Finished Jul 30 06:44:15 PM PDT 24
Peak memory 218452 kb
Host smart-44cd3050-5d51-4360-bf33-a1c6a9e21d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021568780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3021568780
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1596286461
Short name T322
Test name
Test status
Simulation time 116793982 ps
CPU time 1.63 seconds
Started Jul 30 06:44:15 PM PDT 24
Finished Jul 30 06:44:17 PM PDT 24
Peak memory 218976 kb
Host smart-099ae8c5-85e8-4469-9b62-046e8d5df3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596286461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1596286461
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2925093602
Short name T420
Test name
Test status
Simulation time 29865632 ps
CPU time 1.12 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 224008 kb
Host smart-66a6d5b6-1a9b-4038-b6cf-ff6c2a43c807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925093602 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2925093602
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2479041592
Short name T879
Test name
Test status
Simulation time 36666460 ps
CPU time 0.94 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 207256 kb
Host smart-7d3b3933-2011-4001-a623-b9d9f0230c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479041592 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2479041592
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3025784537
Short name T669
Test name
Test status
Simulation time 17226291 ps
CPU time 1.02 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 215300 kb
Host smart-e8aed7b5-3392-4c73-8575-5314d7618f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025784537 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3025784537
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1183942264
Short name T252
Test name
Test status
Simulation time 339998626 ps
CPU time 3.57 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:29 PM PDT 24
Peak memory 217192 kb
Host smart-6405f917-f276-436b-9dae-1218bdef2567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183942264 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1183942264
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.926302593
Short name T231
Test name
Test status
Simulation time 80107927035 ps
CPU time 1802.82 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 07:14:23 PM PDT 24
Peak memory 224300 kb
Host smart-9b6c1196-3641-4174-abba-133225222190
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926302593 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.926302593
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.1483924114
Short name T188
Test name
Test status
Simulation time 21498817 ps
CPU time 1.04 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 223948 kb
Host smart-5d4a4f85-12bb-483e-9bc8-b0393b8dfc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483924114 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1483924114
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3538327386
Short name T576
Test name
Test status
Simulation time 47835455 ps
CPU time 1.5 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:14 PM PDT 24
Peak memory 218464 kb
Host smart-a3c0d871-b3b9-4a5a-ae76-3d23fc9cb6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538327386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3538327386
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1460740934
Short name T157
Test name
Test status
Simulation time 52108625 ps
CPU time 1.19 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 218668 kb
Host smart-bd7a0a5e-e75a-437a-9c7d-447258c7a0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460740934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1460740934
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.258674189
Short name T481
Test name
Test status
Simulation time 46027081 ps
CPU time 1.16 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 219780 kb
Host smart-ef7fc8ab-64c3-42dc-b66f-77f5ee3b23e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258674189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.258674189
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2868584592
Short name T775
Test name
Test status
Simulation time 57510393 ps
CPU time 1.44 seconds
Started Jul 30 06:45:18 PM PDT 24
Finished Jul 30 06:45:20 PM PDT 24
Peak memory 218336 kb
Host smart-6240f568-3fce-4657-91b2-8278245b77d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868584592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2868584592
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3692240235
Short name T978
Test name
Test status
Simulation time 25114050 ps
CPU time 1.15 seconds
Started Jul 30 06:45:18 PM PDT 24
Finished Jul 30 06:45:20 PM PDT 24
Peak memory 219864 kb
Host smart-cfde6cbf-13b5-4064-a54e-9b78023e5e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692240235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3692240235
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3705513150
Short name T211
Test name
Test status
Simulation time 31631404 ps
CPU time 0.99 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 229396 kb
Host smart-22abc70c-461b-4089-8987-ce9041aab951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705513150 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3705513150
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.481682216
Short name T413
Test name
Test status
Simulation time 52873245 ps
CPU time 1.63 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 218444 kb
Host smart-85ba0d31-66c3-4fb2-b907-b57a38a14c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481682216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.481682216
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.3091990225
Short name T179
Test name
Test status
Simulation time 45973790 ps
CPU time 1.22 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 219352 kb
Host smart-34f12ba2-071c-46fd-b3e2-dfd5863cafc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091990225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.3091990225
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.1314597039
Short name T193
Test name
Test status
Simulation time 19938120 ps
CPU time 1.14 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 224028 kb
Host smart-7d251a2a-8f79-4ca6-b50b-4763ac7a0b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314597039 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1314597039
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3309802546
Short name T634
Test name
Test status
Simulation time 42925707 ps
CPU time 1.32 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 217168 kb
Host smart-c2793554-c02d-454d-a6ab-be5139501ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309802546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3309802546
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2441777671
Short name T313
Test name
Test status
Simulation time 131610906 ps
CPU time 1.22 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 218364 kb
Host smart-359f25b5-6ca2-4af0-add5-adc7f25fe769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441777671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2441777671
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.4114763912
Short name T175
Test name
Test status
Simulation time 22850178 ps
CPU time 1.16 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:14 PM PDT 24
Peak memory 219544 kb
Host smart-0c72e484-7723-45c7-8696-f8d1b57d5780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114763912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.4114763912
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2106971312
Short name T539
Test name
Test status
Simulation time 44858942 ps
CPU time 1.66 seconds
Started Jul 30 06:45:22 PM PDT 24
Finished Jul 30 06:45:23 PM PDT 24
Peak memory 218560 kb
Host smart-796d082e-7ca2-4bd0-98af-9af3b603b64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106971312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2106971312
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.143155637
Short name T26
Test name
Test status
Simulation time 24545888 ps
CPU time 1.2 seconds
Started Jul 30 06:45:25 PM PDT 24
Finished Jul 30 06:45:26 PM PDT 24
Peak memory 220480 kb
Host smart-3f01f4de-c3e0-4b5b-b916-7e618dde6bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143155637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.143155637
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.2944217428
Short name T812
Test name
Test status
Simulation time 25221610 ps
CPU time 0.98 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:26 PM PDT 24
Peak memory 218480 kb
Host smart-ab1b51c0-e2a4-4885-9bc2-36d065e654de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944217428 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2944217428
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/86.edn_alert.3568024772
Short name T856
Test name
Test status
Simulation time 90193195 ps
CPU time 1.22 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 219252 kb
Host smart-b111709a-fe91-4866-abbb-1335beb3265a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568024772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.3568024772
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2998792188
Short name T967
Test name
Test status
Simulation time 29460334 ps
CPU time 1.33 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 225740 kb
Host smart-6da8d60d-4613-42fe-b7c4-e7e92795e0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998792188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2998792188
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3639163830
Short name T882
Test name
Test status
Simulation time 42116066 ps
CPU time 1.47 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:19 PM PDT 24
Peak memory 218692 kb
Host smart-3947daa4-cbce-469b-988d-f34c638a6b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639163830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3639163830
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.3340140603
Short name T57
Test name
Test status
Simulation time 59134009 ps
CPU time 1.28 seconds
Started Jul 30 06:45:12 PM PDT 24
Finished Jul 30 06:45:13 PM PDT 24
Peak memory 215860 kb
Host smart-e6696d8a-004a-4291-93ab-67859b05e152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340140603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.3340140603
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.3911338856
Short name T121
Test name
Test status
Simulation time 21395370 ps
CPU time 0.93 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 218504 kb
Host smart-148df792-08c1-4f9a-8596-2d1e0e926483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911338856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3911338856
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1372835803
Short name T748
Test name
Test status
Simulation time 46423782 ps
CPU time 1.5 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 218708 kb
Host smart-bf93f65a-0b60-4907-9f90-58ca45550cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372835803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1372835803
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.2798407902
Short name T671
Test name
Test status
Simulation time 30586881 ps
CPU time 1.24 seconds
Started Jul 30 06:45:13 PM PDT 24
Finished Jul 30 06:45:15 PM PDT 24
Peak memory 218636 kb
Host smart-5229faca-a110-4f5f-bb38-dde9138f8135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798407902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.2798407902
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2792564279
Short name T147
Test name
Test status
Simulation time 56180718 ps
CPU time 0.96 seconds
Started Jul 30 06:45:19 PM PDT 24
Finished Jul 30 06:45:25 PM PDT 24
Peak memory 219728 kb
Host smart-421832bf-4249-406e-8ef3-02b5780dd132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792564279 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2792564279
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1410574710
Short name T528
Test name
Test status
Simulation time 64606547 ps
CPU time 1.13 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 218784 kb
Host smart-9efccb06-9e98-4133-b62a-eda060e3afd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410574710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1410574710
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.3027704932
Short name T79
Test name
Test status
Simulation time 26346486 ps
CPU time 1.2 seconds
Started Jul 30 06:45:28 PM PDT 24
Finished Jul 30 06:45:30 PM PDT 24
Peak memory 220824 kb
Host smart-6c7ad521-5257-4efb-bfa5-2e9d32cef080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027704932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.3027704932
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2581401353
Short name T114
Test name
Test status
Simulation time 45698894 ps
CPU time 1.18 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 225764 kb
Host smart-2725b13b-56f2-4b3d-910b-b8d45ef7f267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581401353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2581401353
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1506935624
Short name T653
Test name
Test status
Simulation time 48939172 ps
CPU time 1.12 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 218492 kb
Host smart-3c1fca29-ccef-4984-86e7-5e89b52f90cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506935624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1506935624
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3970643295
Short name T444
Test name
Test status
Simulation time 27033421 ps
CPU time 1.25 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 215696 kb
Host smart-741d6d1b-3687-486f-8bdf-3f2c2ca77697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970643295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3970643295
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.464500874
Short name T51
Test name
Test status
Simulation time 11921405 ps
CPU time 0.9 seconds
Started Jul 30 06:44:18 PM PDT 24
Finished Jul 30 06:44:19 PM PDT 24
Peak memory 207000 kb
Host smart-38f17dc4-1942-4649-9a2c-eeb2a7da389b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464500874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.464500874
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.338721420
Short name T723
Test name
Test status
Simulation time 12981733 ps
CPU time 0.88 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 216336 kb
Host smart-fdc02960-f18e-475c-be97-4ed6614931c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338721420 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.338721420
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_err.3087979308
Short name T156
Test name
Test status
Simulation time 33344031 ps
CPU time 1.04 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 219664 kb
Host smart-9c2c613d-e838-4573-8a2f-7b1474e2721b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087979308 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3087979308
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2240871927
Short name T507
Test name
Test status
Simulation time 44932948 ps
CPU time 1.36 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 218440 kb
Host smart-528c94d7-5b8c-4f48-94d0-b24695eb7c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240871927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2240871927
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1568648286
Short name T820
Test name
Test status
Simulation time 64962041 ps
CPU time 0.85 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 215180 kb
Host smart-470fd57b-67c5-44b1-9e69-09eff5409031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568648286 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1568648286
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3811596500
Short name T717
Test name
Test status
Simulation time 38085896 ps
CPU time 0.88 seconds
Started Jul 30 06:44:17 PM PDT 24
Finished Jul 30 06:44:18 PM PDT 24
Peak memory 207080 kb
Host smart-29d1ef7d-ba00-430e-b1f3-4c02d9b6e58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811596500 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3811596500
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.990278655
Short name T916
Test name
Test status
Simulation time 57747731 ps
CPU time 0.92 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:25 PM PDT 24
Peak memory 215220 kb
Host smart-c7d4da28-9a0d-45af-8648-37815195a318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990278655 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.990278655
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2809202570
Short name T421
Test name
Test status
Simulation time 247330823 ps
CPU time 5.07 seconds
Started Jul 30 06:44:18 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 217244 kb
Host smart-137a82e3-7e75-4576-b9d1-f563e37943c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809202570 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2809202570
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.4163222806
Short name T233
Test name
Test status
Simulation time 82447792669 ps
CPU time 1038.89 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 07:01:43 PM PDT 24
Peak memory 221216 kb
Host smart-be4196a4-c947-4ca9-a78c-355b16a64491
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163222806 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.4163222806
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.927984927
Short name T926
Test name
Test status
Simulation time 80335226 ps
CPU time 1.11 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 218352 kb
Host smart-41ea9ec9-8a95-4898-b104-13dc87372b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927984927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.927984927
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3108237905
Short name T43
Test name
Test status
Simulation time 40050439 ps
CPU time 1.19 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:26 PM PDT 24
Peak memory 229796 kb
Host smart-fe4f1799-6692-4f9b-ae56-140657384de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108237905 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3108237905
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3977875530
Short name T720
Test name
Test status
Simulation time 38931164 ps
CPU time 1.38 seconds
Started Jul 30 06:45:22 PM PDT 24
Finished Jul 30 06:45:24 PM PDT 24
Peak memory 218536 kb
Host smart-648b16ab-64dd-48e0-a36f-33316b6bd527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977875530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3977875530
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1653578325
Short name T464
Test name
Test status
Simulation time 113315275 ps
CPU time 1.14 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 220832 kb
Host smart-556e97a7-5734-4594-9f0d-02d0e057c8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653578325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1653578325
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.4020048319
Short name T673
Test name
Test status
Simulation time 21506527 ps
CPU time 1.02 seconds
Started Jul 30 06:45:14 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 218728 kb
Host smart-df7ccfff-77e9-4692-bfac-e997b5fed2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020048319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.4020048319
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.4066352039
Short name T849
Test name
Test status
Simulation time 152898009 ps
CPU time 2.07 seconds
Started Jul 30 06:45:23 PM PDT 24
Finished Jul 30 06:45:25 PM PDT 24
Peak memory 219728 kb
Host smart-b68930bd-7f73-4023-8e19-1eaa1a373245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066352039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.4066352039
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.2348259020
Short name T695
Test name
Test status
Simulation time 65130558 ps
CPU time 1.03 seconds
Started Jul 30 06:45:22 PM PDT 24
Finished Jul 30 06:45:24 PM PDT 24
Peak memory 219748 kb
Host smart-4cd3e05f-417c-4cd6-8962-a03bfe9c3789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348259020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2348259020
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.582032031
Short name T375
Test name
Test status
Simulation time 22053210 ps
CPU time 0.91 seconds
Started Jul 30 06:45:22 PM PDT 24
Finished Jul 30 06:45:23 PM PDT 24
Peak memory 218524 kb
Host smart-9ad7119c-21ad-4276-9868-70d21b870d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582032031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.582032031
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.163178910
Short name T468
Test name
Test status
Simulation time 96381784 ps
CPU time 1.04 seconds
Started Jul 30 06:45:16 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 217344 kb
Host smart-82717f25-09b6-4684-86ec-69b9bd84d22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163178910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.163178910
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2496280148
Short name T430
Test name
Test status
Simulation time 37233494 ps
CPU time 1.28 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:19 PM PDT 24
Peak memory 219292 kb
Host smart-ff781606-a45a-4dd7-bbe1-7536eb58fc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496280148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2496280148
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.788604763
Short name T694
Test name
Test status
Simulation time 19462987 ps
CPU time 1.01 seconds
Started Jul 30 06:45:23 PM PDT 24
Finished Jul 30 06:45:24 PM PDT 24
Peak memory 218368 kb
Host smart-bf273008-b1f1-4564-a71a-fff64afb72e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788604763 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.788604763
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2458671511
Short name T781
Test name
Test status
Simulation time 50554905 ps
CPU time 1.57 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:26 PM PDT 24
Peak memory 218620 kb
Host smart-0fec6681-e3f2-41bd-9667-c3c3161592ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458671511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2458671511
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.695162041
Short name T971
Test name
Test status
Simulation time 46350336 ps
CPU time 1.19 seconds
Started Jul 30 06:45:18 PM PDT 24
Finished Jul 30 06:45:25 PM PDT 24
Peak memory 219956 kb
Host smart-c3eb2641-144a-4ad1-8c95-024cda244f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695162041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.695162041
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.3307388239
Short name T44
Test name
Test status
Simulation time 32287828 ps
CPU time 1.01 seconds
Started Jul 30 06:45:26 PM PDT 24
Finished Jul 30 06:45:27 PM PDT 24
Peak memory 224020 kb
Host smart-c4f5b3fb-3081-4031-98ff-69a3cabbee86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307388239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3307388239
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2752449698
Short name T871
Test name
Test status
Simulation time 83519865 ps
CPU time 1.14 seconds
Started Jul 30 06:45:20 PM PDT 24
Finished Jul 30 06:45:21 PM PDT 24
Peak memory 217436 kb
Host smart-f5057ccc-50c7-4885-9da9-5e73498527db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752449698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2752449698
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3422709541
Short name T907
Test name
Test status
Simulation time 24293878 ps
CPU time 1.2 seconds
Started Jul 30 06:45:29 PM PDT 24
Finished Jul 30 06:45:30 PM PDT 24
Peak memory 218608 kb
Host smart-bdd9684b-4c31-42c9-9c57-3aa6687a6ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422709541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3422709541
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1087192053
Short name T189
Test name
Test status
Simulation time 22629513 ps
CPU time 0.93 seconds
Started Jul 30 06:45:28 PM PDT 24
Finished Jul 30 06:45:29 PM PDT 24
Peak memory 218372 kb
Host smart-f8530698-8561-4358-ab3d-12dac07d76ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087192053 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1087192053
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2305678165
Short name T334
Test name
Test status
Simulation time 117266792 ps
CPU time 1.26 seconds
Started Jul 30 06:45:17 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 218736 kb
Host smart-c4d1201e-b54e-4ccf-9f28-329d349fdf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305678165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2305678165
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.844424212
Short name T128
Test name
Test status
Simulation time 26680009 ps
CPU time 1.27 seconds
Started Jul 30 06:45:26 PM PDT 24
Finished Jul 30 06:45:27 PM PDT 24
Peak memory 229624 kb
Host smart-c3696ef8-7881-4edc-8c9e-4c38586dd418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844424212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.844424212
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1919551110
Short name T367
Test name
Test status
Simulation time 279257918 ps
CPU time 1.81 seconds
Started Jul 30 06:45:29 PM PDT 24
Finished Jul 30 06:45:31 PM PDT 24
Peak memory 218664 kb
Host smart-91284851-24c4-46d6-8a9b-4b9d4652d7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919551110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1919551110
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2522788128
Short name T674
Test name
Test status
Simulation time 113529882 ps
CPU time 1.22 seconds
Started Jul 30 06:45:28 PM PDT 24
Finished Jul 30 06:45:29 PM PDT 24
Peak memory 215736 kb
Host smart-db73ba81-087c-4b81-b9dc-ccb7be1cf435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522788128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2522788128
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.3762846706
Short name T106
Test name
Test status
Simulation time 67455723 ps
CPU time 1.12 seconds
Started Jul 30 06:45:27 PM PDT 24
Finished Jul 30 06:45:28 PM PDT 24
Peak memory 225704 kb
Host smart-611d1dc9-afa9-48be-94cb-592330886e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762846706 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3762846706
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.877727899
Short name T670
Test name
Test status
Simulation time 90367321 ps
CPU time 1.12 seconds
Started Jul 30 06:45:21 PM PDT 24
Finished Jul 30 06:45:23 PM PDT 24
Peak memory 218968 kb
Host smart-d27186ea-7fc6-4764-a9fe-c8569101d5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877727899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.877727899
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2122842501
Short name T214
Test name
Test status
Simulation time 24924432 ps
CPU time 1.29 seconds
Started Jul 30 06:45:35 PM PDT 24
Finished Jul 30 06:45:36 PM PDT 24
Peak memory 219208 kb
Host smart-6827371f-1027-49d5-8fd8-1b0596953450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122842501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2122842501
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1039700512
Short name T807
Test name
Test status
Simulation time 28829634 ps
CPU time 1.03 seconds
Started Jul 30 06:45:34 PM PDT 24
Finished Jul 30 06:45:35 PM PDT 24
Peak memory 219796 kb
Host smart-c6752f65-1a6b-4482-b5db-6ce81eea1d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039700512 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1039700512
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2222611541
Short name T470
Test name
Test status
Simulation time 118086357 ps
CPU time 2.53 seconds
Started Jul 30 06:45:32 PM PDT 24
Finished Jul 30 06:45:34 PM PDT 24
Peak memory 220336 kb
Host smart-9ee04712-0de0-4b54-a43d-2a8e710081b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222611541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2222611541
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2305722123
Short name T287
Test name
Test status
Simulation time 95649851 ps
CPU time 1.17 seconds
Started Jul 30 06:45:26 PM PDT 24
Finished Jul 30 06:45:28 PM PDT 24
Peak memory 219636 kb
Host smart-b880f5fe-13b7-485d-a141-6967b7aa0a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305722123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2305722123
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.4277769810
Short name T936
Test name
Test status
Simulation time 94040535 ps
CPU time 0.88 seconds
Started Jul 30 06:45:24 PM PDT 24
Finished Jul 30 06:45:26 PM PDT 24
Peak memory 218400 kb
Host smart-4eb01364-736a-4410-803c-6bedb5751f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277769810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.4277769810
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3344703857
Short name T763
Test name
Test status
Simulation time 75290786 ps
CPU time 1.32 seconds
Started Jul 30 06:45:35 PM PDT 24
Finished Jul 30 06:45:36 PM PDT 24
Peak memory 218720 kb
Host smart-2ee33eca-26d7-41f3-95c6-8050ef2e84cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344703857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3344703857
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%