Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

8262

1

T1

8

T45

14

T46

33

all_values[1]

8262

1

T1

8

T45

14

T46

33

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8571

1

T1

10

T45

10

T46

33

auto[1]

7953

1

T1

6

T45

18

T46

33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6439

1

T1

6

T45

13

T46

24

auto[1]

10085

1

T1

10

T45

15

T46

42

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9691

1

T1

10

T45

18

T46

37

auto[1]

6833

1

T1

6

T45

10

T46

29

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	0	12	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

1649

1

T1

2

T45

2

T46

2

all_values[0]

auto[0]

auto[0]

auto[1]

831

1

T1

2

T45

1

T46

6

all_values[0]

auto[0]

auto[1]

auto[0]

1539

1

T1

2

T45

3

T46

11

all_values[0]

auto[0]

auto[1]

auto[1]

810

1

T45

2

T24

17

T102

3

all_values[0]

auto[1]

auto[0]

auto[1]

1841

1

T1

1

T45

3

T46

9

all_values[0]

auto[1]

auto[1]

auto[1]

1592

1

T1

1

T45

3

T46

5

all_values[1]

auto[0]

auto[0]

auto[0]

1683

1

T45

2

T46

8

T24

40

all_values[1]

auto[0]

auto[0]

auto[1]

814

1

T1

2

T45

1

T46

1

all_values[1]

auto[0]

auto[1]

auto[0]

1568

1

T1

2

T45

6

T46

3

all_values[1]

auto[0]

auto[1]

auto[1]

797

1

T45

1

T46

6

T24

13

all_values[1]

auto[1]

auto[0]

auto[1]

1753

1

T1

3

T45

1

T46

7

all_values[1]

auto[1]

auto[1]

auto[1]

1647

1

T1

1

T45

3

T46

8

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal