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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.59 98.25 93.25 90.85 88.95 95.50 96.83 91.51


Total test records in report: 1125
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T1016 /workspace/coverage/cover_reg_top/12.edn_intr_test.2329930668 Jul 31 05:47:46 PM PDT 24 Jul 31 05:47:47 PM PDT 24 93057272 ps
T1017 /workspace/coverage/cover_reg_top/42.edn_intr_test.2833967924 Jul 31 05:47:48 PM PDT 24 Jul 31 05:47:50 PM PDT 24 89730512 ps
T1018 /workspace/coverage/cover_reg_top/48.edn_intr_test.2725961869 Jul 31 05:47:50 PM PDT 24 Jul 31 05:47:50 PM PDT 24 48816773 ps
T289 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1907438311 Jul 31 05:47:29 PM PDT 24 Jul 31 05:47:31 PM PDT 24 116927559 ps
T1019 /workspace/coverage/cover_reg_top/15.edn_tl_errors.948972924 Jul 31 05:47:37 PM PDT 24 Jul 31 05:47:39 PM PDT 24 95794568 ps
T261 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.41553514 Jul 31 05:47:24 PM PDT 24 Jul 31 05:47:26 PM PDT 24 25826443 ps
T1020 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1128073615 Jul 31 05:47:35 PM PDT 24 Jul 31 05:47:36 PM PDT 24 76799331 ps
T1021 /workspace/coverage/cover_reg_top/26.edn_intr_test.4215192294 Jul 31 05:47:42 PM PDT 24 Jul 31 05:47:44 PM PDT 24 23923282 ps
T1022 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3623433498 Jul 31 05:47:35 PM PDT 24 Jul 31 05:47:36 PM PDT 24 23702793 ps
T1023 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2753053337 Jul 31 05:47:24 PM PDT 24 Jul 31 05:47:26 PM PDT 24 50831259 ps
T1024 /workspace/coverage/cover_reg_top/1.edn_intr_test.4136158477 Jul 31 05:47:28 PM PDT 24 Jul 31 05:47:29 PM PDT 24 45305136 ps
T1025 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2313204486 Jul 31 05:47:25 PM PDT 24 Jul 31 05:47:26 PM PDT 24 228096088 ps
T1026 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2402227129 Jul 31 05:47:31 PM PDT 24 Jul 31 05:47:33 PM PDT 24 108980071 ps
T1027 /workspace/coverage/cover_reg_top/6.edn_csr_rw.734493479 Jul 31 05:47:30 PM PDT 24 Jul 31 05:47:31 PM PDT 24 45150546 ps
T1028 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.797605352 Jul 31 05:47:40 PM PDT 24 Jul 31 05:47:42 PM PDT 24 45387550 ps
T1029 /workspace/coverage/cover_reg_top/33.edn_intr_test.724350653 Jul 31 05:47:43 PM PDT 24 Jul 31 05:47:44 PM PDT 24 88594559 ps
T1030 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.350069705 Jul 31 05:47:40 PM PDT 24 Jul 31 05:47:42 PM PDT 24 25586346 ps
T287 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2170364854 Jul 31 05:47:41 PM PDT 24 Jul 31 05:47:43 PM PDT 24 76725287 ps
T1031 /workspace/coverage/cover_reg_top/0.edn_intr_test.157754095 Jul 31 05:47:27 PM PDT 24 Jul 31 05:47:29 PM PDT 24 33405670 ps
T275 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.884848788 Jul 31 05:47:26 PM PDT 24 Jul 31 05:47:27 PM PDT 24 128786528 ps
T1032 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1547545545 Jul 31 05:47:33 PM PDT 24 Jul 31 05:47:35 PM PDT 24 106451299 ps
T262 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2680765916 Jul 31 05:47:20 PM PDT 24 Jul 31 05:47:21 PM PDT 24 19848102 ps
T276 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2598521452 Jul 31 05:47:29 PM PDT 24 Jul 31 05:47:30 PM PDT 24 73136992 ps
T1033 /workspace/coverage/cover_reg_top/29.edn_intr_test.2444548845 Jul 31 05:47:42 PM PDT 24 Jul 31 05:47:43 PM PDT 24 16772578 ps
T1034 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2717675587 Jul 31 05:47:28 PM PDT 24 Jul 31 05:47:30 PM PDT 24 58868027 ps
T1035 /workspace/coverage/cover_reg_top/32.edn_intr_test.3548902351 Jul 31 05:47:43 PM PDT 24 Jul 31 05:47:44 PM PDT 24 13454512 ps
T1036 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1835112338 Jul 31 05:47:26 PM PDT 24 Jul 31 05:47:28 PM PDT 24 54163901 ps
T1037 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3099768166 Jul 31 05:47:28 PM PDT 24 Jul 31 05:47:29 PM PDT 24 222387230 ps
T263 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1820943368 Jul 31 05:47:23 PM PDT 24 Jul 31 05:47:24 PM PDT 24 36575646 ps
T1038 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.4221236075 Jul 31 05:47:28 PM PDT 24 Jul 31 05:47:29 PM PDT 24 18238018 ps
T1039 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2971228907 Jul 31 05:47:26 PM PDT 24 Jul 31 05:47:28 PM PDT 24 130865039 ps
T1040 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4171673488 Jul 31 05:47:25 PM PDT 24 Jul 31 05:47:32 PM PDT 24 459787779 ps
T1041 /workspace/coverage/cover_reg_top/4.edn_intr_test.1970213087 Jul 31 05:47:33 PM PDT 24 Jul 31 05:47:34 PM PDT 24 15754482 ps
T290 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2783404683 Jul 31 05:47:34 PM PDT 24 Jul 31 05:47:37 PM PDT 24 221927648 ps
T1042 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1674687403 Jul 31 05:47:40 PM PDT 24 Jul 31 05:47:42 PM PDT 24 75140120 ps
T1043 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1644540312 Jul 31 05:47:35 PM PDT 24 Jul 31 05:47:36 PM PDT 24 40014435 ps
T1044 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.4283956657 Jul 31 05:47:40 PM PDT 24 Jul 31 05:47:41 PM PDT 24 34734922 ps
T266 /workspace/coverage/cover_reg_top/13.edn_csr_rw.795405107 Jul 31 05:47:33 PM PDT 24 Jul 31 05:47:34 PM PDT 24 22428564 ps
T1045 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2046650059 Jul 31 05:47:45 PM PDT 24 Jul 31 05:47:47 PM PDT 24 13227303 ps
T1046 /workspace/coverage/cover_reg_top/17.edn_intr_test.550887838 Jul 31 05:47:42 PM PDT 24 Jul 31 05:47:43 PM PDT 24 30371526 ps
T1047 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4052103354 Jul 31 05:47:36 PM PDT 24 Jul 31 05:47:37 PM PDT 24 15685350 ps
T288 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3059146578 Jul 31 05:47:27 PM PDT 24 Jul 31 05:47:28 PM PDT 24 95172729 ps
T1048 /workspace/coverage/cover_reg_top/49.edn_intr_test.1117393559 Jul 31 05:47:52 PM PDT 24 Jul 31 05:47:53 PM PDT 24 28793037 ps
T1049 /workspace/coverage/cover_reg_top/44.edn_intr_test.1038909988 Jul 31 05:47:47 PM PDT 24 Jul 31 05:47:48 PM PDT 24 11743742 ps
T1050 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2572520839 Jul 31 05:47:34 PM PDT 24 Jul 31 05:47:38 PM PDT 24 122180142 ps
T1051 /workspace/coverage/cover_reg_top/34.edn_intr_test.2562749274 Jul 31 05:47:42 PM PDT 24 Jul 31 05:47:43 PM PDT 24 18526784 ps
T1052 /workspace/coverage/cover_reg_top/7.edn_intr_test.2161666340 Jul 31 05:47:31 PM PDT 24 Jul 31 05:47:32 PM PDT 24 15501570 ps
T1053 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3464152934 Jul 31 05:47:33 PM PDT 24 Jul 31 05:47:34 PM PDT 24 119809511 ps
T1054 /workspace/coverage/cover_reg_top/20.edn_intr_test.3430979785 Jul 31 05:47:43 PM PDT 24 Jul 31 05:47:44 PM PDT 24 61923664 ps
T1055 /workspace/coverage/cover_reg_top/15.edn_intr_test.3992415412 Jul 31 05:47:40 PM PDT 24 Jul 31 05:47:41 PM PDT 24 33220649 ps
T1056 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.844884601 Jul 31 05:47:32 PM PDT 24 Jul 31 05:47:34 PM PDT 24 57081137 ps
T1057 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2823941958 Jul 31 05:47:26 PM PDT 24 Jul 31 05:47:27 PM PDT 24 102384667 ps
T1058 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2303145182 Jul 31 05:47:39 PM PDT 24 Jul 31 05:47:42 PM PDT 24 146966521 ps
T1059 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2941850758 Jul 31 05:47:24 PM PDT 24 Jul 31 05:47:25 PM PDT 24 13711554 ps
T1060 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2610041352 Jul 31 05:47:36 PM PDT 24 Jul 31 05:47:38 PM PDT 24 40599523 ps
T1061 /workspace/coverage/cover_reg_top/40.edn_intr_test.1323882560 Jul 31 05:47:49 PM PDT 24 Jul 31 05:47:50 PM PDT 24 23929540 ps
T1062 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4103643295 Jul 31 05:47:47 PM PDT 24 Jul 31 05:47:50 PM PDT 24 813784566 ps
T1063 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2059331644 Jul 31 05:47:30 PM PDT 24 Jul 31 05:47:31 PM PDT 24 66085258 ps
T1064 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2426203228 Jul 31 05:47:37 PM PDT 24 Jul 31 05:47:39 PM PDT 24 39521510 ps
T1065 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2432308219 Jul 31 05:47:40 PM PDT 24 Jul 31 05:47:41 PM PDT 24 20441491 ps
T1066 /workspace/coverage/cover_reg_top/16.edn_tl_errors.663988464 Jul 31 05:47:36 PM PDT 24 Jul 31 05:47:40 PM PDT 24 514120729 ps
T1067 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1426875478 Jul 31 05:47:31 PM PDT 24 Jul 31 05:47:34 PM PDT 24 266406880 ps
T1068 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3375119283 Jul 31 05:47:36 PM PDT 24 Jul 31 05:47:37 PM PDT 24 37766136 ps
T1069 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3763731331 Jul 31 05:47:33 PM PDT 24 Jul 31 05:47:36 PM PDT 24 48384680 ps
T1070 /workspace/coverage/cover_reg_top/2.edn_intr_test.1196024919 Jul 31 05:47:28 PM PDT 24 Jul 31 05:47:29 PM PDT 24 14692633 ps
T1071 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2860983399 Jul 31 05:47:43 PM PDT 24 Jul 31 05:47:44 PM PDT 24 43080245 ps
T1072 /workspace/coverage/cover_reg_top/19.edn_intr_test.1492095094 Jul 31 05:47:38 PM PDT 24 Jul 31 05:47:39 PM PDT 24 28994989 ps
T1073 /workspace/coverage/cover_reg_top/39.edn_intr_test.4238055596 Jul 31 05:47:40 PM PDT 24 Jul 31 05:47:41 PM PDT 24 13502568 ps
T1074 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1829334236 Jul 31 05:47:43 PM PDT 24 Jul 31 05:47:44 PM PDT 24 22745083 ps
T1075 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1219052568 Jul 31 05:47:36 PM PDT 24 Jul 31 05:47:38 PM PDT 24 139540999 ps
T1076 /workspace/coverage/cover_reg_top/46.edn_intr_test.1641382858 Jul 31 05:47:42 PM PDT 24 Jul 31 05:47:42 PM PDT 24 35126071 ps
T291 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.841452394 Jul 31 05:47:36 PM PDT 24 Jul 31 05:47:39 PM PDT 24 215660199 ps
T1077 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1586545211 Jul 31 05:47:27 PM PDT 24 Jul 31 05:47:29 PM PDT 24 200548493 ps
T1078 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.408611505 Jul 31 05:47:29 PM PDT 24 Jul 31 05:47:31 PM PDT 24 61055039 ps
T1079 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3601153789 Jul 31 05:47:29 PM PDT 24 Jul 31 05:47:32 PM PDT 24 494140401 ps
T1080 /workspace/coverage/cover_reg_top/36.edn_intr_test.3197006644 Jul 31 05:47:45 PM PDT 24 Jul 31 05:47:51 PM PDT 24 24262405 ps
T264 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1498255301 Jul 31 05:47:36 PM PDT 24 Jul 31 05:47:37 PM PDT 24 24896483 ps
T1081 /workspace/coverage/cover_reg_top/14.edn_intr_test.2973136606 Jul 31 05:47:45 PM PDT 24 Jul 31 05:47:47 PM PDT 24 41444244 ps
T1082 /workspace/coverage/cover_reg_top/5.edn_intr_test.1048290780 Jul 31 05:47:24 PM PDT 24 Jul 31 05:47:25 PM PDT 24 14307996 ps
T1083 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2857625850 Jul 31 05:47:30 PM PDT 24 Jul 31 05:47:31 PM PDT 24 23782867 ps
T1084 /workspace/coverage/cover_reg_top/9.edn_tl_errors.4224519486 Jul 31 05:47:31 PM PDT 24 Jul 31 05:47:34 PM PDT 24 144893651 ps
T1085 /workspace/coverage/cover_reg_top/16.edn_intr_test.3879581040 Jul 31 05:47:36 PM PDT 24 Jul 31 05:47:37 PM PDT 24 47759795 ps
T1086 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2843040828 Jul 31 05:47:45 PM PDT 24 Jul 31 05:47:47 PM PDT 24 49243477 ps
T265 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1333807134 Jul 31 05:47:45 PM PDT 24 Jul 31 05:47:47 PM PDT 24 20940947 ps
T1087 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1766632757 Jul 31 05:47:22 PM PDT 24 Jul 31 05:47:24 PM PDT 24 151682176 ps
T1088 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.4234416245 Jul 31 05:47:24 PM PDT 24 Jul 31 05:47:27 PM PDT 24 167632113 ps
T1089 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.796571625 Jul 31 05:47:35 PM PDT 24 Jul 31 05:47:38 PM PDT 24 339676852 ps
T1090 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2313146276 Jul 31 05:47:42 PM PDT 24 Jul 31 05:47:44 PM PDT 24 105335922 ps
T268 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.917757733 Jul 31 05:47:21 PM PDT 24 Jul 31 05:47:23 PM PDT 24 25755282 ps
T1091 /workspace/coverage/cover_reg_top/31.edn_intr_test.656387499 Jul 31 05:47:42 PM PDT 24 Jul 31 05:47:42 PM PDT 24 36780774 ps
T1092 /workspace/coverage/cover_reg_top/25.edn_intr_test.935116509 Jul 31 05:47:45 PM PDT 24 Jul 31 05:47:46 PM PDT 24 47013906 ps
T267 /workspace/coverage/cover_reg_top/8.edn_csr_rw.165394904 Jul 31 05:47:32 PM PDT 24 Jul 31 05:47:33 PM PDT 24 12592524 ps
T1093 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3571020690 Jul 31 05:47:34 PM PDT 24 Jul 31 05:47:36 PM PDT 24 36656199 ps
T1094 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2371031248 Jul 31 05:47:52 PM PDT 24 Jul 31 05:47:53 PM PDT 24 27262640 ps
T1095 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2732847343 Jul 31 05:47:40 PM PDT 24 Jul 31 05:47:43 PM PDT 24 102890910 ps
T1096 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2008911449 Jul 31 05:47:35 PM PDT 24 Jul 31 05:47:37 PM PDT 24 308004193 ps
T1097 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4164622878 Jul 31 05:47:39 PM PDT 24 Jul 31 05:47:40 PM PDT 24 181322740 ps
T1098 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3846787606 Jul 31 05:47:36 PM PDT 24 Jul 31 05:47:41 PM PDT 24 290770011 ps
T1099 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.628595755 Jul 31 05:47:25 PM PDT 24 Jul 31 05:47:29 PM PDT 24 139667238 ps
T1100 /workspace/coverage/cover_reg_top/38.edn_intr_test.3241901096 Jul 31 05:47:43 PM PDT 24 Jul 31 05:47:44 PM PDT 24 25944417 ps
T1101 /workspace/coverage/cover_reg_top/30.edn_intr_test.4180228786 Jul 31 05:47:38 PM PDT 24 Jul 31 05:47:39 PM PDT 24 58389273 ps
T1102 /workspace/coverage/cover_reg_top/18.edn_intr_test.744486266 Jul 31 05:47:41 PM PDT 24 Jul 31 05:47:42 PM PDT 24 25985452 ps
T1103 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3249572382 Jul 31 05:47:36 PM PDT 24 Jul 31 05:47:38 PM PDT 24 95066203 ps
T1104 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3481549618 Jul 31 05:47:25 PM PDT 24 Jul 31 05:47:26 PM PDT 24 61055023 ps
T1105 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3396522658 Jul 31 05:47:36 PM PDT 24 Jul 31 05:47:38 PM PDT 24 110911851 ps
T1106 /workspace/coverage/cover_reg_top/27.edn_intr_test.4130726182 Jul 31 05:47:48 PM PDT 24 Jul 31 05:47:50 PM PDT 24 23893744 ps
T1107 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2397502371 Jul 31 05:47:46 PM PDT 24 Jul 31 05:47:47 PM PDT 24 114854185 ps
T1108 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2078982839 Jul 31 05:47:19 PM PDT 24 Jul 31 05:47:20 PM PDT 24 113948337 ps
T1109 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2099824041 Jul 31 05:47:42 PM PDT 24 Jul 31 05:47:46 PM PDT 24 425850440 ps
T1110 /workspace/coverage/cover_reg_top/24.edn_intr_test.1197687254 Jul 31 05:47:46 PM PDT 24 Jul 31 05:47:47 PM PDT 24 22678554 ps
T1111 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2063269431 Jul 31 05:47:18 PM PDT 24 Jul 31 05:47:21 PM PDT 24 173520714 ps
T1112 /workspace/coverage/cover_reg_top/1.edn_tl_errors.328616837 Jul 31 05:47:23 PM PDT 24 Jul 31 05:47:25 PM PDT 24 464874562 ps
T1113 /workspace/coverage/cover_reg_top/37.edn_intr_test.1462062475 Jul 31 05:47:48 PM PDT 24 Jul 31 05:47:49 PM PDT 24 51498134 ps
T1114 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2995120414 Jul 31 05:47:30 PM PDT 24 Jul 31 05:47:31 PM PDT 24 26353178 ps
T1115 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2464226474 Jul 31 05:47:36 PM PDT 24 Jul 31 05:47:38 PM PDT 24 65698640 ps
T1116 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4185566375 Jul 31 05:47:37 PM PDT 24 Jul 31 05:47:38 PM PDT 24 185839710 ps
T1117 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2694369315 Jul 31 05:47:27 PM PDT 24 Jul 31 05:47:32 PM PDT 24 1384231080 ps
T1118 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3555257923 Jul 31 05:47:30 PM PDT 24 Jul 31 05:47:31 PM PDT 24 29292093 ps
T1119 /workspace/coverage/cover_reg_top/6.edn_intr_test.1636699039 Jul 31 05:47:31 PM PDT 24 Jul 31 05:47:32 PM PDT 24 117001968 ps
T1120 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2192256324 Jul 31 05:47:25 PM PDT 24 Jul 31 05:47:26 PM PDT 24 30989064 ps
T1121 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.188218997 Jul 31 05:47:35 PM PDT 24 Jul 31 05:47:37 PM PDT 24 24094454 ps
T1122 /workspace/coverage/cover_reg_top/43.edn_intr_test.3811349903 Jul 31 05:47:41 PM PDT 24 Jul 31 05:47:42 PM PDT 24 21442684 ps
T1123 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3029024007 Jul 31 05:47:33 PM PDT 24 Jul 31 05:47:36 PM PDT 24 78258274 ps
T1124 /workspace/coverage/cover_reg_top/11.edn_intr_test.3352817263 Jul 31 05:47:39 PM PDT 24 Jul 31 05:47:40 PM PDT 24 21951669 ps
T1125 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1322026934 Jul 31 05:47:23 PM PDT 24 Jul 31 05:47:24 PM PDT 24 20518423 ps

Test location /workspace/coverage/default/154.edn_alert.2259448187
Short name T8
Test name
Test status
Simulation time 34366470 ps
CPU time 1.34 seconds
Started Jul 31 05:50:38 PM PDT 24
Finished Jul 31 05:50:39 PM PDT 24
Peak memory 218724 kb
Host smart-a08ce9ac-be62-41fe-b781-98f534d2c827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259448187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.2259448187
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/40.edn_genbits.2544186588
Short name T27
Test name
Test status
Simulation time 91570514 ps
CPU time 1.26 seconds
Started Jul 31 05:49:37 PM PDT 24
Finished Jul 31 05:49:38 PM PDT 24
Peak memory 217332 kb
Host smart-354d701c-ad91-4240-a18d-3c4311c277b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544186588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2544186588
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.436818001
Short name T24
Test name
Test status
Simulation time 182329298528 ps
CPU time 1161.67 seconds
Started Jul 31 05:49:01 PM PDT 24
Finished Jul 31 06:08:23 PM PDT 24
Peak memory 224328 kb
Host smart-a08a5667-eadc-41db-8c61-c411f9082e99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436818001 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.436818001
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.edn_genbits.3763872781
Short name T33
Test name
Test status
Simulation time 95519037 ps
CPU time 1.36 seconds
Started Jul 31 05:50:43 PM PDT 24
Finished Jul 31 05:50:44 PM PDT 24
Peak memory 218908 kb
Host smart-b9610795-4ac5-456e-9c7a-c69883a08187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763872781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3763872781
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_err.3328126410
Short name T4
Test name
Test status
Simulation time 62310572 ps
CPU time 1.18 seconds
Started Jul 31 05:49:11 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 229720 kb
Host smart-5f33837e-6b68-4c63-9073-bdad76c2cc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328126410 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3328126410
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/147.edn_genbits.3719646684
Short name T18
Test name
Test status
Simulation time 71205829 ps
CPU time 1.42 seconds
Started Jul 31 05:50:42 PM PDT 24
Finished Jul 31 05:50:43 PM PDT 24
Peak memory 220128 kb
Host smart-1e058e25-e85f-4c87-9fe8-b2248469db82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719646684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3719646684
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/80.edn_err.378967916
Short name T48
Test name
Test status
Simulation time 28603513 ps
CPU time 0.95 seconds
Started Jul 31 05:50:13 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 223600 kb
Host smart-2a31f9a4-3871-4d02-bd1f-4cfa07fb0261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378967916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.378967916
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1251869940
Short name T459
Test name
Test status
Simulation time 92823447 ps
CPU time 1.13 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 218544 kb
Host smart-7c4257be-1166-4bc6-8014-5696b5a7480c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251869940 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1251869940
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/65.edn_alert.3162422301
Short name T2
Test name
Test status
Simulation time 66023217 ps
CPU time 1.27 seconds
Started Jul 31 05:49:55 PM PDT 24
Finished Jul 31 05:49:57 PM PDT 24
Peak memory 219292 kb
Host smart-4154e162-d689-4efa-b3cc-351a1703c8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162422301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3162422301
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert.762016998
Short name T94
Test name
Test status
Simulation time 59800181 ps
CPU time 1.26 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 215552 kb
Host smart-6e33dd82-473c-4e6f-b297-8c59bb1a43a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762016998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.762016998
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/2.edn_regwen.3562770370
Short name T47
Test name
Test status
Simulation time 26749959 ps
CPU time 0.92 seconds
Started Jul 31 05:48:57 PM PDT 24
Finished Jul 31 05:48:58 PM PDT 24
Peak memory 207080 kb
Host smart-888d6e13-2497-400f-968b-d12c7be6faa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562770370 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3562770370
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/11.edn_intr.839993541
Short name T85
Test name
Test status
Simulation time 25639929 ps
CPU time 0.92 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:08 PM PDT 24
Peak memory 215768 kb
Host smart-1c6bf9fb-0829-4f41-a488-dc6531b690ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839993541 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.839993541
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1975507708
Short name T232
Test name
Test status
Simulation time 99675228693 ps
CPU time 725.97 seconds
Started Jul 31 05:49:04 PM PDT 24
Finished Jul 31 06:01:10 PM PDT 24
Peak memory 219968 kb
Host smart-e00d003d-d4b9-4dde-bbc9-7ca211e95ca6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975507708 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1975507708
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.952177557
Short name T227
Test name
Test status
Simulation time 1283848987 ps
CPU time 2.17 seconds
Started Jul 31 05:47:30 PM PDT 24
Finished Jul 31 05:47:33 PM PDT 24
Peak memory 206684 kb
Host smart-799c1aee-da04-4de2-8fd5-d3bd62391d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952177557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.952177557
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3633283120
Short name T10
Test name
Test status
Simulation time 67137105 ps
CPU time 1.11 seconds
Started Jul 31 05:49:16 PM PDT 24
Finished Jul 31 05:49:17 PM PDT 24
Peak memory 216780 kb
Host smart-4a003cd1-d594-4aca-b30d-a095e86ca175
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633283120 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3633283120
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/74.edn_alert.4210015199
Short name T73
Test name
Test status
Simulation time 95973569 ps
CPU time 1.25 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 218476 kb
Host smart-690c1bed-9928-4736-95f1-f8015c568795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210015199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.4210015199
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/185.edn_alert.925871263
Short name T325
Test name
Test status
Simulation time 76077033 ps
CPU time 1.13 seconds
Started Jul 31 05:50:57 PM PDT 24
Finished Jul 31 05:50:58 PM PDT 24
Peak memory 219748 kb
Host smart-631d2f19-812e-4e4f-9fdf-ebb27afb325f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925871263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.925871263
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.2529385782
Short name T115
Test name
Test status
Simulation time 33394549 ps
CPU time 0.87 seconds
Started Jul 31 05:48:49 PM PDT 24
Finished Jul 31 05:48:50 PM PDT 24
Peak memory 216288 kb
Host smart-91045ebb-30a3-494b-bff3-28f381d85325
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529385782 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2529385782
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.471937612
Short name T256
Test name
Test status
Simulation time 11800890 ps
CPU time 0.89 seconds
Started Jul 31 05:47:29 PM PDT 24
Finished Jul 31 05:47:30 PM PDT 24
Peak memory 206676 kb
Host smart-5be6cbcb-d1b6-4c07-9fa7-8c49f72c795a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471937612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.471937612
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/default/25.edn_disable.2786861686
Short name T127
Test name
Test status
Simulation time 38972837 ps
CPU time 0.84 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 216324 kb
Host smart-957d9555-5005-4693-a4d4-c2b09b82d3f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786861686 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2786861686
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2717453392
Short name T123
Test name
Test status
Simulation time 155121728 ps
CPU time 1.24 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 05:49:19 PM PDT 24
Peak memory 216988 kb
Host smart-16e75053-96a5-4b62-b94c-bd1c1ec8ee7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717453392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2717453392
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_disable.2304816420
Short name T133
Test name
Test status
Simulation time 12548981 ps
CPU time 0.93 seconds
Started Jul 31 05:49:53 PM PDT 24
Finished Jul 31 05:49:54 PM PDT 24
Peak memory 216396 kb
Host smart-93cadd6f-980e-44da-b581-1e518623d99c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304816420 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2304816420
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/35.edn_alert.2483667336
Short name T333
Test name
Test status
Simulation time 50120341 ps
CPU time 1.24 seconds
Started Jul 31 05:49:42 PM PDT 24
Finished Jul 31 05:49:43 PM PDT 24
Peak memory 220692 kb
Host smart-9c0bd9f6-0cb0-420a-845f-c23af6a76e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483667336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2483667336
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/1.edn_intr.3924423859
Short name T101
Test name
Test status
Simulation time 21379036 ps
CPU time 1.06 seconds
Started Jul 31 05:48:45 PM PDT 24
Finished Jul 31 05:48:46 PM PDT 24
Peak memory 215760 kb
Host smart-d29ed98f-d2b8-4600-90db-26730b85ee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924423859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3924423859
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/153.edn_genbits.2896840915
Short name T9
Test name
Test status
Simulation time 166467243 ps
CPU time 2.28 seconds
Started Jul 31 05:50:30 PM PDT 24
Finished Jul 31 05:50:33 PM PDT 24
Peak memory 220420 kb
Host smart-56464861-ebd9-499e-819f-57370815de5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896840915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2896840915
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2145734961
Short name T164
Test name
Test status
Simulation time 41656503 ps
CPU time 1.42 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 05:50:03 PM PDT 24
Peak memory 219720 kb
Host smart-e3ee2432-2b80-4d41-85a2-c17df9b1be00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145734961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2145734961
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/143.edn_alert.3480677970
Short name T285
Test name
Test status
Simulation time 32709773 ps
CPU time 1.28 seconds
Started Jul 31 05:50:22 PM PDT 24
Finished Jul 31 05:50:23 PM PDT 24
Peak memory 215668 kb
Host smart-aa4bb0e8-d821-4c9b-a1c4-bd394161ec32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480677970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.3480677970
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/161.edn_alert.1727115235
Short name T689
Test name
Test status
Simulation time 27704289 ps
CPU time 1.25 seconds
Started Jul 31 05:50:35 PM PDT 24
Finished Jul 31 05:50:37 PM PDT 24
Peak memory 220028 kb
Host smart-673e4792-e9af-4020-ad74-593ceb22afa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727115235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.1727115235
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/10.edn_err.491835985
Short name T203
Test name
Test status
Simulation time 21003825 ps
CPU time 1 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:08 PM PDT 24
Peak memory 218388 kb
Host smart-b428d35b-ea9e-48bd-9a80-ea20df91a0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491835985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.491835985
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/104.edn_alert.1617913823
Short name T158
Test name
Test status
Simulation time 27736785 ps
CPU time 1.33 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 220444 kb
Host smart-e85d7667-bcb0-4241-a51d-deeb237eea9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617913823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1617913823
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/118.edn_alert.2094146767
Short name T225
Test name
Test status
Simulation time 96212056 ps
CPU time 1.21 seconds
Started Jul 31 05:50:14 PM PDT 24
Finished Jul 31 05:50:15 PM PDT 24
Peak memory 219352 kb
Host smart-30d675a2-cbd1-4e2a-a081-12a95b0033e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094146767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.2094146767
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/121.edn_alert.1718262024
Short name T177
Test name
Test status
Simulation time 136124611 ps
CPU time 1.16 seconds
Started Jul 31 05:50:11 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 220720 kb
Host smart-d1af1a37-0ce6-4b4a-bda2-9e93029e0c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718262024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1718262024
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert.1357782981
Short name T247
Test name
Test status
Simulation time 93888792 ps
CPU time 1.16 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:09 PM PDT 24
Peak memory 219768 kb
Host smart-9e8366fe-f660-47a0-ae74-e22205d85a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357782981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1357782981
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.503013508
Short name T302
Test name
Test status
Simulation time 116542552 ps
CPU time 1.54 seconds
Started Jul 31 05:50:12 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 220216 kb
Host smart-a54365ab-5b6f-4397-8d63-6700b9a55c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503013508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.503013508
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_alert.2386545768
Short name T815
Test name
Test status
Simulation time 45697100 ps
CPU time 1.09 seconds
Started Jul 31 05:49:43 PM PDT 24
Finished Jul 31 05:49:44 PM PDT 24
Peak memory 219728 kb
Host smart-52ae15d4-6a69-41af-b3fa-57cca60f848c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386545768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2386545768
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3765030349
Short name T17
Test name
Test status
Simulation time 34536883 ps
CPU time 1.2 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 216840 kb
Host smart-a879d680-b557-4f27-86b6-396335e839f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765030349 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3765030349
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_disable.2523906891
Short name T200
Test name
Test status
Simulation time 89983701 ps
CPU time 0.86 seconds
Started Jul 31 05:48:38 PM PDT 24
Finished Jul 31 05:48:39 PM PDT 24
Peak memory 216200 kb
Host smart-a08c8fd9-e858-40cd-b3cf-3cb51205323b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523906891 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2523906891
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3301731785
Short name T925
Test name
Test status
Simulation time 53652636 ps
CPU time 1.1 seconds
Started Jul 31 05:48:47 PM PDT 24
Finished Jul 31 05:48:48 PM PDT 24
Peak memory 216840 kb
Host smart-f683d840-4e82-4c46-a82d-cf02e862df80
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301731785 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3301731785
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/109.edn_alert.972388512
Short name T610
Test name
Test status
Simulation time 25300525 ps
CPU time 1.19 seconds
Started Jul 31 05:50:07 PM PDT 24
Finished Jul 31 05:50:08 PM PDT 24
Peak memory 219592 kb
Host smart-906c939b-24eb-476f-9eef-65995b71fc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972388512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.972388512
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert.310339809
Short name T197
Test name
Test status
Simulation time 46819835 ps
CPU time 1.18 seconds
Started Jul 31 05:49:01 PM PDT 24
Finished Jul 31 05:49:02 PM PDT 24
Peak memory 219596 kb
Host smart-a2843e65-20f2-45b9-b699-f1dc49c9075e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310339809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.310339809
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.379935443
Short name T751
Test name
Test status
Simulation time 216406487 ps
CPU time 1.01 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 05:49:18 PM PDT 24
Peak memory 216784 kb
Host smart-aab00394-a908-4e41-b2fe-e8ba27176e07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379935443 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.379935443
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.885056782
Short name T213
Test name
Test status
Simulation time 21079010 ps
CPU time 1.1 seconds
Started Jul 31 05:49:01 PM PDT 24
Finished Jul 31 05:49:02 PM PDT 24
Peak memory 219488 kb
Host smart-e91c04ce-663f-4f02-9680-f19b983e6979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885056782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.885056782
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_intr.3874034297
Short name T481
Test name
Test status
Simulation time 26380001 ps
CPU time 1.12 seconds
Started Jul 31 05:49:04 PM PDT 24
Finished Jul 31 05:49:05 PM PDT 24
Peak memory 223968 kb
Host smart-e9100eca-341f-474c-b283-25db97f1fc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874034297 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3874034297
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/13.edn_disable.1827417557
Short name T114
Test name
Test status
Simulation time 21648635 ps
CPU time 0.85 seconds
Started Jul 31 05:49:04 PM PDT 24
Finished Jul 31 05:49:05 PM PDT 24
Peak memory 216280 kb
Host smart-e6b209b2-fa70-4ad8-b4a3-a8bb0c996c01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827417557 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1827417557
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable.88285900
Short name T138
Test name
Test status
Simulation time 10459456 ps
CPU time 0.86 seconds
Started Jul 31 05:49:15 PM PDT 24
Finished Jul 31 05:49:16 PM PDT 24
Peak memory 216196 kb
Host smart-a9d040c5-b282-4184-8f59-d6e19d52f6bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88285900 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.88285900
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable.4031535894
Short name T136
Test name
Test status
Simulation time 16703932 ps
CPU time 0.91 seconds
Started Jul 31 05:49:18 PM PDT 24
Finished Jul 31 05:49:19 PM PDT 24
Peak memory 216528 kb
Host smart-c609a19b-2c1e-4ca9-b31e-fdcd017991f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031535894 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4031535894
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable.2821306018
Short name T186
Test name
Test status
Simulation time 15763733 ps
CPU time 0.93 seconds
Started Jul 31 05:49:19 PM PDT 24
Finished Jul 31 05:49:20 PM PDT 24
Peak memory 215376 kb
Host smart-4e5d382e-2be5-448a-be3b-d88b562c4e7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821306018 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2821306018
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable.892040832
Short name T149
Test name
Test status
Simulation time 12124348 ps
CPU time 0.9 seconds
Started Jul 31 05:49:47 PM PDT 24
Finished Jul 31 05:49:48 PM PDT 24
Peak memory 216384 kb
Host smart-52e348df-dd22-4924-be6f-05879711983f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892040832 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.892040832
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable.278988523
Short name T143
Test name
Test status
Simulation time 11809292 ps
CPU time 0.89 seconds
Started Jul 31 05:49:48 PM PDT 24
Finished Jul 31 05:49:49 PM PDT 24
Peak memory 216144 kb
Host smart-d3781190-40a2-4474-bef0-7c63e022fb32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278988523 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.278988523
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable.3208462812
Short name T116
Test name
Test status
Simulation time 67831232 ps
CPU time 0.84 seconds
Started Jul 31 05:49:47 PM PDT 24
Finished Jul 31 05:49:48 PM PDT 24
Peak memory 216260 kb
Host smart-75888dc3-8668-430b-bccd-2d72889802b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208462812 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3208462812
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/66.edn_err.4231094946
Short name T212
Test name
Test status
Simulation time 32862969 ps
CPU time 0.87 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 218268 kb
Host smart-8814c9ef-881a-4018-b957-6e99e6cefaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231094946 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.4231094946
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/108.edn_genbits.3671473354
Short name T11
Test name
Test status
Simulation time 106057441 ps
CPU time 1.39 seconds
Started Jul 31 05:50:12 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 217488 kb
Host smart-74211ad3-43bc-4db7-9446-f5066ec40df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671473354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3671473354
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_alert_test.2723618793
Short name T377
Test name
Test status
Simulation time 46614125 ps
CPU time 0.99 seconds
Started Jul 31 05:49:02 PM PDT 24
Finished Jul 31 05:49:03 PM PDT 24
Peak memory 206684 kb
Host smart-df0b3b44-6e5c-4ce9-a939-dc6668a1f3cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723618793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2723618793
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/121.edn_genbits.2832747037
Short name T295
Test name
Test status
Simulation time 58445763 ps
CPU time 1.27 seconds
Started Jul 31 05:50:08 PM PDT 24
Finished Jul 31 05:50:09 PM PDT 24
Peak memory 218372 kb
Host smart-a0d18b7f-db8c-4ac9-842a-306957aea914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832747037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2832747037
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/100.edn_genbits.325552944
Short name T74
Test name
Test status
Simulation time 84108267 ps
CPU time 2.7 seconds
Started Jul 31 05:49:57 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 219856 kb
Host smart-c4ed852d-0268-43c4-9637-6134d52205d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325552944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.325552944
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.323221686
Short name T311
Test name
Test status
Simulation time 260474818 ps
CPU time 3.51 seconds
Started Jul 31 05:50:13 PM PDT 24
Finished Jul 31 05:50:21 PM PDT 24
Peak memory 220308 kb
Host smart-2584c1f0-a3c0-4177-b440-a4b5c732ebf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323221686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.323221686
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_alert.519642806
Short name T293
Test name
Test status
Simulation time 37089349 ps
CPU time 1.09 seconds
Started Jul 31 05:49:45 PM PDT 24
Finished Jul 31 05:49:46 PM PDT 24
Peak memory 220052 kb
Host smart-a1551cc0-5c0d-4e12-9336-9aebafac593d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519642806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.519642806
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/13.edn_stress_all.3972250998
Short name T345
Test name
Test status
Simulation time 223702350 ps
CPU time 4.82 seconds
Started Jul 31 05:49:05 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 215320 kb
Host smart-c467957d-a971-4b80-98a0-46a095ad7dce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972250998 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3972250998
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_intr.1164225823
Short name T854
Test name
Test status
Simulation time 35539721 ps
CPU time 0.85 seconds
Started Jul 31 05:49:19 PM PDT 24
Finished Jul 31 05:49:20 PM PDT 24
Peak memory 215624 kb
Host smart-24c7442d-d830-4d9c-b76d-6f11328d3466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164225823 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1164225823
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/14.edn_err.1289987422
Short name T5
Test name
Test status
Simulation time 18206664 ps
CPU time 1.04 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:04 PM PDT 24
Peak memory 218600 kb
Host smart-67fffb5b-5894-4fa1-8a50-5cc06993e6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289987422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1289987422
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.841452394
Short name T291
Test name
Test status
Simulation time 215660199 ps
CPU time 2.18 seconds
Started Jul 31 05:47:36 PM PDT 24
Finished Jul 31 05:47:39 PM PDT 24
Peak memory 215512 kb
Host smart-4631952c-8f35-4f62-80d3-fc58707dd68e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841452394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.841452394
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1763693524
Short name T922
Test name
Test status
Simulation time 38638259 ps
CPU time 1.45 seconds
Started Jul 31 05:48:44 PM PDT 24
Finished Jul 31 05:48:46 PM PDT 24
Peak memory 218604 kb
Host smart-1a5f02d3-26ed-4b71-99f0-354b37d83535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763693524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1763693524
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.3239990828
Short name T319
Test name
Test status
Simulation time 21902240 ps
CPU time 1.17 seconds
Started Jul 31 05:50:07 PM PDT 24
Finished Jul 31 05:50:08 PM PDT 24
Peak memory 220036 kb
Host smart-313d9fc8-bf3b-44d5-b88d-264742d8ca7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239990828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3239990828
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.2253059406
Short name T365
Test name
Test status
Simulation time 37138561 ps
CPU time 1.47 seconds
Started Jul 31 05:50:06 PM PDT 24
Finished Jul 31 05:50:08 PM PDT 24
Peak memory 218408 kb
Host smart-aa2ad6a2-78b3-46bf-844c-79db53bb5191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253059406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2253059406
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.1972739614
Short name T330
Test name
Test status
Simulation time 39040593 ps
CPU time 1.13 seconds
Started Jul 31 05:50:12 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 219716 kb
Host smart-e86340c7-d67f-429a-9f55-5d91d8264302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972739614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.1972739614
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.3960210475
Short name T635
Test name
Test status
Simulation time 34838896 ps
CPU time 1.25 seconds
Started Jul 31 05:50:29 PM PDT 24
Finished Jul 31 05:50:30 PM PDT 24
Peak memory 217596 kb
Host smart-3ef7419f-458a-4a35-b75c-2611a5b8f225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960210475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3960210475
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.471279767
Short name T306
Test name
Test status
Simulation time 46534556 ps
CPU time 1.29 seconds
Started Jul 31 05:50:20 PM PDT 24
Finished Jul 31 05:50:21 PM PDT 24
Peak memory 218772 kb
Host smart-592576d8-137a-48ba-9ac6-53af58ec4d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471279767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.471279767
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.967029266
Short name T294
Test name
Test status
Simulation time 65821494 ps
CPU time 1.31 seconds
Started Jul 31 05:50:50 PM PDT 24
Finished Jul 31 05:50:51 PM PDT 24
Peak memory 218468 kb
Host smart-662f8487-a664-47e2-b536-96229aff82cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967029266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.967029266
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.155984540
Short name T312
Test name
Test status
Simulation time 321472811 ps
CPU time 1.06 seconds
Started Jul 31 05:50:47 PM PDT 24
Finished Jul 31 05:50:48 PM PDT 24
Peak memory 217168 kb
Host smart-14abb704-0084-427d-8b54-3d197d32e7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155984540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.155984540
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2381127504
Short name T528
Test name
Test status
Simulation time 25355063 ps
CPU time 1.15 seconds
Started Jul 31 05:50:51 PM PDT 24
Finished Jul 31 05:50:52 PM PDT 24
Peak memory 217156 kb
Host smart-bbfc348a-114f-4c6e-a8a4-56b1ce77ab82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381127504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2381127504
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2982034694
Short name T88
Test name
Test status
Simulation time 42755751 ps
CPU time 0.84 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:08 PM PDT 24
Peak memory 215600 kb
Host smart-f8720242-5ca6-42d9-b5ba-25db44b09c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982034694 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2982034694
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/11.edn_genbits.2666372549
Short name T834
Test name
Test status
Simulation time 80976991 ps
CPU time 1.18 seconds
Started Jul 31 05:49:04 PM PDT 24
Finished Jul 31 05:49:05 PM PDT 24
Peak memory 215384 kb
Host smart-6de68766-dc8d-4e2c-bc6c-85e24084fa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666372549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2666372549
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2680765916
Short name T262
Test name
Test status
Simulation time 19848102 ps
CPU time 1.03 seconds
Started Jul 31 05:47:20 PM PDT 24
Finished Jul 31 05:47:21 PM PDT 24
Peak memory 206600 kb
Host smart-9ec1a4d4-cfb5-47dd-9adc-37f1859200ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680765916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2680765916
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2694369315
Short name T1117
Test name
Test status
Simulation time 1384231080 ps
CPU time 5.07 seconds
Started Jul 31 05:47:27 PM PDT 24
Finished Jul 31 05:47:32 PM PDT 24
Peak memory 206552 kb
Host smart-0f70c848-f8a9-4eee-b1a1-aa8e8ec89f9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694369315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2694369315
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2078982839
Short name T1108
Test name
Test status
Simulation time 113948337 ps
CPU time 0.95 seconds
Started Jul 31 05:47:19 PM PDT 24
Finished Jul 31 05:47:20 PM PDT 24
Peak memory 206372 kb
Host smart-04c8a26c-1e8c-4528-a5d0-ade5bbc2af98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078982839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2078982839
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1322026934
Short name T1125
Test name
Test status
Simulation time 20518423 ps
CPU time 1.13 seconds
Started Jul 31 05:47:23 PM PDT 24
Finished Jul 31 05:47:24 PM PDT 24
Peak memory 216644 kb
Host smart-d30d83eb-b819-4cb5-b01d-cebd83654e47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322026934 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1322026934
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.273398645
Short name T1008
Test name
Test status
Simulation time 16294446 ps
CPU time 0.93 seconds
Started Jul 31 05:47:19 PM PDT 24
Finished Jul 31 05:47:20 PM PDT 24
Peak memory 206560 kb
Host smart-d77aec55-b5b1-46ca-a13d-4199e0aed110
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273398645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.273398645
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.157754095
Short name T1031
Test name
Test status
Simulation time 33405670 ps
CPU time 0.91 seconds
Started Jul 31 05:47:27 PM PDT 24
Finished Jul 31 05:47:29 PM PDT 24
Peak memory 206568 kb
Host smart-b34124fb-f592-4f05-8958-124e35f6e8de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157754095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.157754095
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3099768166
Short name T1037
Test name
Test status
Simulation time 222387230 ps
CPU time 1.18 seconds
Started Jul 31 05:47:28 PM PDT 24
Finished Jul 31 05:47:29 PM PDT 24
Peak memory 206680 kb
Host smart-510d2c5a-a9a2-4bcf-aa30-337650983451
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099768166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3099768166
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2063269431
Short name T1111
Test name
Test status
Simulation time 173520714 ps
CPU time 3.23 seconds
Started Jul 31 05:47:18 PM PDT 24
Finished Jul 31 05:47:21 PM PDT 24
Peak memory 214976 kb
Host smart-c5e86e9f-0f3d-44b4-bcc1-7c618aedb49c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063269431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2063269431
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.556235630
Short name T1007
Test name
Test status
Simulation time 71591490 ps
CPU time 2.2 seconds
Started Jul 31 05:47:21 PM PDT 24
Finished Jul 31 05:47:23 PM PDT 24
Peak memory 214620 kb
Host smart-a382c6f2-f639-4724-ad4b-95098a9ae0f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556235630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.556235630
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2753053337
Short name T1023
Test name
Test status
Simulation time 50831259 ps
CPU time 1.55 seconds
Started Jul 31 05:47:24 PM PDT 24
Finished Jul 31 05:47:26 PM PDT 24
Peak memory 206584 kb
Host smart-8e282af1-d746-4125-a848-dd1e4a90ccb1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753053337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2753053337
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.628595755
Short name T1099
Test name
Test status
Simulation time 139667238 ps
CPU time 3.62 seconds
Started Jul 31 05:47:25 PM PDT 24
Finished Jul 31 05:47:29 PM PDT 24
Peak memory 206520 kb
Host smart-ba4ef86d-705f-4d37-bd07-00bfbc7f8ef9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628595755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.628595755
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4037444898
Short name T260
Test name
Test status
Simulation time 53092483 ps
CPU time 0.91 seconds
Started Jul 31 05:47:27 PM PDT 24
Finished Jul 31 05:47:28 PM PDT 24
Peak memory 206548 kb
Host smart-b9095635-b3ba-4513-8774-8aed40d9b7d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037444898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.4037444898
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4042348466
Short name T999
Test name
Test status
Simulation time 37176639 ps
CPU time 1.33 seconds
Started Jul 31 05:47:28 PM PDT 24
Finished Jul 31 05:47:30 PM PDT 24
Peak memory 215068 kb
Host smart-da847125-e395-4d0e-b07b-2083760897af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042348466 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.4042348466
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1820943368
Short name T263
Test name
Test status
Simulation time 36575646 ps
CPU time 0.83 seconds
Started Jul 31 05:47:23 PM PDT 24
Finished Jul 31 05:47:24 PM PDT 24
Peak memory 206404 kb
Host smart-54d96276-6288-41b9-91dc-3e8c14510279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820943368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1820943368
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.4136158477
Short name T1024
Test name
Test status
Simulation time 45305136 ps
CPU time 0.9 seconds
Started Jul 31 05:47:28 PM PDT 24
Finished Jul 31 05:47:29 PM PDT 24
Peak memory 206560 kb
Host smart-c30b59f2-2018-4011-aeba-640b9746a5fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136158477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.4136158477
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.884848788
Short name T275
Test name
Test status
Simulation time 128786528 ps
CPU time 1.06 seconds
Started Jul 31 05:47:26 PM PDT 24
Finished Jul 31 05:47:27 PM PDT 24
Peak memory 206672 kb
Host smart-40039ccf-fac9-4c80-88cc-d0e126cc1151
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884848788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.884848788
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.328616837
Short name T1112
Test name
Test status
Simulation time 464874562 ps
CPU time 1.78 seconds
Started Jul 31 05:47:23 PM PDT 24
Finished Jul 31 05:47:25 PM PDT 24
Peak memory 223104 kb
Host smart-777cb81e-b543-4cb4-b7c4-53e02c93dbdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328616837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.328616837
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1766632757
Short name T1087
Test name
Test status
Simulation time 151682176 ps
CPU time 1.72 seconds
Started Jul 31 05:47:22 PM PDT 24
Finished Jul 31 05:47:24 PM PDT 24
Peak memory 214888 kb
Host smart-dbdcd2e8-6e93-4900-acda-5075aac4f13c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766632757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1766632757
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4185566375
Short name T1116
Test name
Test status
Simulation time 185839710 ps
CPU time 1.02 seconds
Started Jul 31 05:47:37 PM PDT 24
Finished Jul 31 05:47:38 PM PDT 24
Peak memory 206760 kb
Host smart-9af8ab6e-08fd-4f42-8b33-98c0e5516eb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185566375 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.4185566375
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.968365844
Short name T269
Test name
Test status
Simulation time 119949301 ps
CPU time 0.93 seconds
Started Jul 31 05:47:35 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 206560 kb
Host smart-741b16dc-00ff-42e3-829b-c91ee36ab354
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968365844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.968365844
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3066310617
Short name T992
Test name
Test status
Simulation time 67730079 ps
CPU time 0.78 seconds
Started Jul 31 05:47:35 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 206388 kb
Host smart-ec416246-736a-4ea8-9d58-29ca8ba4c72e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066310617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3066310617
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.188218997
Short name T1121
Test name
Test status
Simulation time 24094454 ps
CPU time 1.14 seconds
Started Jul 31 05:47:35 PM PDT 24
Finished Jul 31 05:47:37 PM PDT 24
Peak memory 206768 kb
Host smart-6430b812-836f-4296-ab00-85b2203777d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188218997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.188218997
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2572520839
Short name T1050
Test name
Test status
Simulation time 122180142 ps
CPU time 4.02 seconds
Started Jul 31 05:47:34 PM PDT 24
Finished Jul 31 05:47:38 PM PDT 24
Peak memory 215000 kb
Host smart-893d2ec2-3b41-40d0-a591-ca0c2b7691f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572520839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2572520839
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1673653919
Short name T997
Test name
Test status
Simulation time 52433685 ps
CPU time 1.41 seconds
Started Jul 31 05:47:35 PM PDT 24
Finished Jul 31 05:47:37 PM PDT 24
Peak memory 217264 kb
Host smart-bc8a5569-57bc-40b6-a890-af69f3d70a89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673653919 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1673653919
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2046650059
Short name T1045
Test name
Test status
Simulation time 13227303 ps
CPU time 0.96 seconds
Started Jul 31 05:47:45 PM PDT 24
Finished Jul 31 05:47:47 PM PDT 24
Peak memory 206620 kb
Host smart-32aa7301-c914-443c-9cb5-5e64c4233f93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046650059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2046650059
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3352817263
Short name T1124
Test name
Test status
Simulation time 21951669 ps
CPU time 0.82 seconds
Started Jul 31 05:47:39 PM PDT 24
Finished Jul 31 05:47:40 PM PDT 24
Peak memory 206556 kb
Host smart-97f3b175-cbe5-4e70-b291-8d87c0317a66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352817263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3352817263
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3375119283
Short name T1068
Test name
Test status
Simulation time 37766136 ps
CPU time 1.07 seconds
Started Jul 31 05:47:36 PM PDT 24
Finished Jul 31 05:47:37 PM PDT 24
Peak memory 206660 kb
Host smart-be7ac9a3-b8dc-467c-972c-0f760a53d1de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375119283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3375119283
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3763731331
Short name T1069
Test name
Test status
Simulation time 48384680 ps
CPU time 3.51 seconds
Started Jul 31 05:47:33 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 215072 kb
Host smart-1ba40b65-f1ad-499e-b666-df1ebbf5e151
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763731331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3763731331
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2189435748
Short name T226
Test name
Test status
Simulation time 202816315 ps
CPU time 2.75 seconds
Started Jul 31 05:47:37 PM PDT 24
Finished Jul 31 05:47:40 PM PDT 24
Peak memory 206728 kb
Host smart-ec887573-420f-413d-877b-7d0e736a477a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189435748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2189435748
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3623433498
Short name T1022
Test name
Test status
Simulation time 23702793 ps
CPU time 1.59 seconds
Started Jul 31 05:47:35 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 214984 kb
Host smart-c5ab7fda-32d8-4838-ab1f-65a5f80027dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623433498 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3623433498
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1644540312
Short name T1043
Test name
Test status
Simulation time 40014435 ps
CPU time 0.88 seconds
Started Jul 31 05:47:35 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 206524 kb
Host smart-213fc1d3-c031-4408-98c6-22d1af98d266
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644540312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1644540312
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2329930668
Short name T1016
Test name
Test status
Simulation time 93057272 ps
CPU time 0.92 seconds
Started Jul 31 05:47:46 PM PDT 24
Finished Jul 31 05:47:47 PM PDT 24
Peak memory 206632 kb
Host smart-5f616155-bda7-4312-87fd-1fb8a3927525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329930668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2329930668
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.861227094
Short name T274
Test name
Test status
Simulation time 113923158 ps
CPU time 1.39 seconds
Started Jul 31 05:47:34 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 206736 kb
Host smart-3891c77a-b858-4b86-8dad-bd32e7ae3cdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861227094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.861227094
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3396522658
Short name T1105
Test name
Test status
Simulation time 110911851 ps
CPU time 2.19 seconds
Started Jul 31 05:47:36 PM PDT 24
Finished Jul 31 05:47:38 PM PDT 24
Peak memory 215032 kb
Host smart-d9f2686f-5442-4f0f-ad3b-76cc56518001
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396522658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3396522658
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2397502371
Short name T1107
Test name
Test status
Simulation time 114854185 ps
CPU time 1.32 seconds
Started Jul 31 05:47:46 PM PDT 24
Finished Jul 31 05:47:47 PM PDT 24
Peak memory 215020 kb
Host smart-03abb3ab-659b-409f-9300-10fa5bb37b05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397502371 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2397502371
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.795405107
Short name T266
Test name
Test status
Simulation time 22428564 ps
CPU time 0.9 seconds
Started Jul 31 05:47:33 PM PDT 24
Finished Jul 31 05:47:34 PM PDT 24
Peak memory 206548 kb
Host smart-4cc55ecb-277a-4fa7-bc50-b4df8afbc853
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795405107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.795405107
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.221114369
Short name T1004
Test name
Test status
Simulation time 23340982 ps
CPU time 0.86 seconds
Started Jul 31 05:47:35 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 206560 kb
Host smart-cdb6195b-6af3-4e64-a697-78df7ef54e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221114369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.221114369
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3464152934
Short name T1053
Test name
Test status
Simulation time 119809511 ps
CPU time 1.15 seconds
Started Jul 31 05:47:33 PM PDT 24
Finished Jul 31 05:47:34 PM PDT 24
Peak memory 206708 kb
Host smart-89ba5f9a-8f70-4195-ae20-a8df8bec166a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464152934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3464152934
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3846787606
Short name T1098
Test name
Test status
Simulation time 290770011 ps
CPU time 4.83 seconds
Started Jul 31 05:47:36 PM PDT 24
Finished Jul 31 05:47:41 PM PDT 24
Peak memory 214860 kb
Host smart-b753af43-a896-4f3d-b348-7e1bb9e820c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846787606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3846787606
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2990666391
Short name T1011
Test name
Test status
Simulation time 70294555 ps
CPU time 2.01 seconds
Started Jul 31 05:47:45 PM PDT 24
Finished Jul 31 05:47:48 PM PDT 24
Peak memory 206824 kb
Host smart-54c892ca-13ca-4d9f-bb92-5adc5f1ddfd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990666391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2990666391
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2843040828
Short name T1086
Test name
Test status
Simulation time 49243477 ps
CPU time 1.38 seconds
Started Jul 31 05:47:45 PM PDT 24
Finished Jul 31 05:47:47 PM PDT 24
Peak memory 223272 kb
Host smart-4f6e9468-4bd5-423d-bc9d-c75032cfd2c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843040828 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2843040828
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3571020690
Short name T1093
Test name
Test status
Simulation time 36656199 ps
CPU time 1.02 seconds
Started Jul 31 05:47:34 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 206640 kb
Host smart-984ed324-12fa-4cac-bfd0-bdd17ad1f28a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571020690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3571020690
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2973136606
Short name T1081
Test name
Test status
Simulation time 41444244 ps
CPU time 0.9 seconds
Started Jul 31 05:47:45 PM PDT 24
Finished Jul 31 05:47:47 PM PDT 24
Peak memory 206632 kb
Host smart-057053a6-4b8e-455c-89ae-80845ebce31c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973136606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2973136606
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2426203228
Short name T1064
Test name
Test status
Simulation time 39521510 ps
CPU time 1.49 seconds
Started Jul 31 05:47:37 PM PDT 24
Finished Jul 31 05:47:39 PM PDT 24
Peak memory 206744 kb
Host smart-fa9cafa1-5e36-44bb-8d31-7d1f6b4480d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426203228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2426203228
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1219052568
Short name T1075
Test name
Test status
Simulation time 139540999 ps
CPU time 2.61 seconds
Started Jul 31 05:47:36 PM PDT 24
Finished Jul 31 05:47:38 PM PDT 24
Peak memory 215032 kb
Host smart-68416236-6629-4ac3-a60d-ec50be5eec70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219052568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1219052568
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2610041352
Short name T1060
Test name
Test status
Simulation time 40599523 ps
CPU time 1.57 seconds
Started Jul 31 05:47:36 PM PDT 24
Finished Jul 31 05:47:38 PM PDT 24
Peak memory 206684 kb
Host smart-75967c88-94b7-4f70-8e1a-c68b28a47ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610041352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2610041352
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1128073615
Short name T1020
Test name
Test status
Simulation time 76799331 ps
CPU time 1.17 seconds
Started Jul 31 05:47:35 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 217516 kb
Host smart-a44701bd-ae8f-4c09-9fa6-324c07de22de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128073615 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1128073615
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2120102102
Short name T257
Test name
Test status
Simulation time 12172384 ps
CPU time 0.86 seconds
Started Jul 31 05:47:35 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 206616 kb
Host smart-eb7e667a-39a7-43ef-8336-d485892f8de3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120102102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2120102102
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3992415412
Short name T1055
Test name
Test status
Simulation time 33220649 ps
CPU time 0.82 seconds
Started Jul 31 05:47:40 PM PDT 24
Finished Jul 31 05:47:41 PM PDT 24
Peak memory 206404 kb
Host smart-256d9121-8b4c-4c98-9307-cc64c5908425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992415412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3992415412
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3249572382
Short name T1103
Test name
Test status
Simulation time 95066203 ps
CPU time 1.03 seconds
Started Jul 31 05:47:36 PM PDT 24
Finished Jul 31 05:47:38 PM PDT 24
Peak memory 206628 kb
Host smart-a8513e52-1615-49be-afe0-75c2101a01d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249572382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3249572382
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.948972924
Short name T1019
Test name
Test status
Simulation time 95794568 ps
CPU time 1.84 seconds
Started Jul 31 05:47:37 PM PDT 24
Finished Jul 31 05:47:39 PM PDT 24
Peak memory 215068 kb
Host smart-da594db5-419c-4f42-ac6d-6610fd571bf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948972924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.948972924
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2008911449
Short name T1096
Test name
Test status
Simulation time 308004193 ps
CPU time 2.31 seconds
Started Jul 31 05:47:35 PM PDT 24
Finished Jul 31 05:47:37 PM PDT 24
Peak memory 206792 kb
Host smart-3c7d6cc9-45e4-4cdf-a8f5-e0c86bfdf2bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008911449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2008911449
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.797605352
Short name T1028
Test name
Test status
Simulation time 45387550 ps
CPU time 1.47 seconds
Started Jul 31 05:47:40 PM PDT 24
Finished Jul 31 05:47:42 PM PDT 24
Peak memory 215056 kb
Host smart-5f43bdfc-62c2-442e-ad7f-40bca1c5a9a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797605352 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.797605352
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1333807134
Short name T265
Test name
Test status
Simulation time 20940947 ps
CPU time 0.93 seconds
Started Jul 31 05:47:45 PM PDT 24
Finished Jul 31 05:47:47 PM PDT 24
Peak memory 206620 kb
Host smart-e6804b9b-8f65-4d5d-ae7c-dcb3dd878783
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333807134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1333807134
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3879581040
Short name T1085
Test name
Test status
Simulation time 47759795 ps
CPU time 0.84 seconds
Started Jul 31 05:47:36 PM PDT 24
Finished Jul 31 05:47:37 PM PDT 24
Peak memory 206552 kb
Host smart-50544795-a9f5-4394-8f92-920d1ec6cd9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879581040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3879581040
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.67609155
Short name T270
Test name
Test status
Simulation time 36707292 ps
CPU time 1.13 seconds
Started Jul 31 05:47:36 PM PDT 24
Finished Jul 31 05:47:37 PM PDT 24
Peak memory 206724 kb
Host smart-4a633e22-6548-445d-99b5-d6bc99ac515d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67609155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_out
standing.67609155
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.663988464
Short name T1066
Test name
Test status
Simulation time 514120729 ps
CPU time 4.35 seconds
Started Jul 31 05:47:36 PM PDT 24
Finished Jul 31 05:47:40 PM PDT 24
Peak memory 214960 kb
Host smart-ce392c44-ac6e-48b6-866d-5402199ef46a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663988464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.663988464
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2783404683
Short name T290
Test name
Test status
Simulation time 221927648 ps
CPU time 2.44 seconds
Started Jul 31 05:47:34 PM PDT 24
Finished Jul 31 05:47:37 PM PDT 24
Peak memory 206736 kb
Host smart-4a0d4893-4397-4dac-b826-938b6201d6c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783404683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2783404683
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.350069705
Short name T1030
Test name
Test status
Simulation time 25586346 ps
CPU time 1.54 seconds
Started Jul 31 05:47:40 PM PDT 24
Finished Jul 31 05:47:42 PM PDT 24
Peak memory 215012 kb
Host smart-d4ba7862-9f35-4dbf-9886-928de9545baa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350069705 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.350069705
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2313146276
Short name T1090
Test name
Test status
Simulation time 105335922 ps
CPU time 0.86 seconds
Started Jul 31 05:47:42 PM PDT 24
Finished Jul 31 05:47:44 PM PDT 24
Peak memory 206364 kb
Host smart-72bfc538-fc2e-493b-be6d-d622ec9d3b58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313146276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2313146276
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.550887838
Short name T1046
Test name
Test status
Simulation time 30371526 ps
CPU time 0.86 seconds
Started Jul 31 05:47:42 PM PDT 24
Finished Jul 31 05:47:43 PM PDT 24
Peak memory 206412 kb
Host smart-8ddfddc6-83f0-4df3-81bf-d1e1d856ed7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550887838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.550887838
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.4283956657
Short name T1044
Test name
Test status
Simulation time 34734922 ps
CPU time 1.5 seconds
Started Jul 31 05:47:40 PM PDT 24
Finished Jul 31 05:47:41 PM PDT 24
Peak memory 206780 kb
Host smart-2471fee6-8bea-49e0-8000-0c742af1617b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283956657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.4283956657
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1055533941
Short name T1000
Test name
Test status
Simulation time 254410459 ps
CPU time 2.46 seconds
Started Jul 31 05:47:41 PM PDT 24
Finished Jul 31 05:47:44 PM PDT 24
Peak memory 214936 kb
Host smart-9d77dd01-9858-4ab6-b60f-e898654548c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055533941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1055533941
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2170364854
Short name T287
Test name
Test status
Simulation time 76725287 ps
CPU time 2.25 seconds
Started Jul 31 05:47:41 PM PDT 24
Finished Jul 31 05:47:43 PM PDT 24
Peak memory 206716 kb
Host smart-88c78863-93ad-4c04-9e2d-04652e88fa1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170364854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2170364854
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1829334236
Short name T1074
Test name
Test status
Simulation time 22745083 ps
CPU time 1.17 seconds
Started Jul 31 05:47:43 PM PDT 24
Finished Jul 31 05:47:44 PM PDT 24
Peak memory 214956 kb
Host smart-362b5ac3-8e8b-46d3-b5d2-a582ec50ef6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829334236 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1829334236
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2860983399
Short name T1071
Test name
Test status
Simulation time 43080245 ps
CPU time 0.91 seconds
Started Jul 31 05:47:43 PM PDT 24
Finished Jul 31 05:47:44 PM PDT 24
Peak memory 206596 kb
Host smart-2b1f13d7-33c7-452b-b41f-1e7d44690577
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860983399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2860983399
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.744486266
Short name T1102
Test name
Test status
Simulation time 25985452 ps
CPU time 0.92 seconds
Started Jul 31 05:47:41 PM PDT 24
Finished Jul 31 05:47:42 PM PDT 24
Peak memory 206540 kb
Host smart-a9f98ec2-8763-44bd-b8fb-9a9454c0f3ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744486266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.744486266
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4164622878
Short name T1097
Test name
Test status
Simulation time 181322740 ps
CPU time 1.43 seconds
Started Jul 31 05:47:39 PM PDT 24
Finished Jul 31 05:47:40 PM PDT 24
Peak memory 206812 kb
Host smart-6aeb5e3d-0431-46df-971f-29cf0f867cd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164622878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.4164622878
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2303145182
Short name T1058
Test name
Test status
Simulation time 146966521 ps
CPU time 3.64 seconds
Started Jul 31 05:47:39 PM PDT 24
Finished Jul 31 05:47:42 PM PDT 24
Peak memory 215056 kb
Host smart-a810161f-a8c4-4b52-bd32-e2bd26e86bb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303145182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2303145182
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4103643295
Short name T1062
Test name
Test status
Simulation time 813784566 ps
CPU time 2.23 seconds
Started Jul 31 05:47:47 PM PDT 24
Finished Jul 31 05:47:50 PM PDT 24
Peak memory 206820 kb
Host smart-c533c72f-d60c-4be5-aa96-5db2275aeb8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103643295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4103643295
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2371031248
Short name T1094
Test name
Test status
Simulation time 27262640 ps
CPU time 1.11 seconds
Started Jul 31 05:47:52 PM PDT 24
Finished Jul 31 05:47:53 PM PDT 24
Peak memory 214972 kb
Host smart-90264124-684c-4dfc-ab43-dd7f657f62aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371031248 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2371031248
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2432308219
Short name T1065
Test name
Test status
Simulation time 20441491 ps
CPU time 0.86 seconds
Started Jul 31 05:47:40 PM PDT 24
Finished Jul 31 05:47:41 PM PDT 24
Peak memory 206572 kb
Host smart-b081301a-3fea-4496-81bb-06c81a5b0ac6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432308219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2432308219
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1492095094
Short name T1072
Test name
Test status
Simulation time 28994989 ps
CPU time 0.78 seconds
Started Jul 31 05:47:38 PM PDT 24
Finished Jul 31 05:47:39 PM PDT 24
Peak memory 206416 kb
Host smart-7e95a856-5340-4ef8-91ff-e984aea7ae57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492095094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1492095094
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1674687403
Short name T1042
Test name
Test status
Simulation time 75140120 ps
CPU time 1.47 seconds
Started Jul 31 05:47:40 PM PDT 24
Finished Jul 31 05:47:42 PM PDT 24
Peak memory 206780 kb
Host smart-27478285-a7eb-45f3-a634-81a4735e01c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674687403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1674687403
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2099824041
Short name T1109
Test name
Test status
Simulation time 425850440 ps
CPU time 3.85 seconds
Started Jul 31 05:47:42 PM PDT 24
Finished Jul 31 05:47:46 PM PDT 24
Peak memory 215072 kb
Host smart-83a7e520-4a80-4495-b226-9d9a60cb145c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099824041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2099824041
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2732847343
Short name T1095
Test name
Test status
Simulation time 102890910 ps
CPU time 2.5 seconds
Started Jul 31 05:47:40 PM PDT 24
Finished Jul 31 05:47:43 PM PDT 24
Peak memory 206840 kb
Host smart-030a8525-2254-4b2c-8be7-60d1cbc7dae2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732847343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2732847343
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1304766455
Short name T259
Test name
Test status
Simulation time 51180003 ps
CPU time 1.25 seconds
Started Jul 31 05:47:25 PM PDT 24
Finished Jul 31 05:47:26 PM PDT 24
Peak memory 206588 kb
Host smart-1baa1772-ecb0-4823-8e37-086f457f2919
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304766455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1304766455
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2570502571
Short name T1010
Test name
Test status
Simulation time 697620168 ps
CPU time 5.3 seconds
Started Jul 31 05:47:27 PM PDT 24
Finished Jul 31 05:47:33 PM PDT 24
Peak memory 206572 kb
Host smart-3f49aeb2-76e0-4c86-a1e1-017806ce1c79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570502571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2570502571
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3035013888
Short name T258
Test name
Test status
Simulation time 31744788 ps
CPU time 0.81 seconds
Started Jul 31 05:47:29 PM PDT 24
Finished Jul 31 05:47:30 PM PDT 24
Peak memory 206408 kb
Host smart-b91248e1-9dca-4a9a-be56-69f850fbb2ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035013888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3035013888
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2313204486
Short name T1025
Test name
Test status
Simulation time 228096088 ps
CPU time 1.49 seconds
Started Jul 31 05:47:25 PM PDT 24
Finished Jul 31 05:47:26 PM PDT 24
Peak memory 214964 kb
Host smart-37c77820-c2d9-44f9-ac50-f729d0e7be5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313204486 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2313204486
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1196024919
Short name T1070
Test name
Test status
Simulation time 14692633 ps
CPU time 0.94 seconds
Started Jul 31 05:47:28 PM PDT 24
Finished Jul 31 05:47:29 PM PDT 24
Peak memory 206604 kb
Host smart-4553d00f-5b76-4ced-9630-6f28a6ecb726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196024919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1196024919
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2971228907
Short name T1039
Test name
Test status
Simulation time 130865039 ps
CPU time 1.33 seconds
Started Jul 31 05:47:26 PM PDT 24
Finished Jul 31 05:47:28 PM PDT 24
Peak memory 206720 kb
Host smart-01a9242c-69ca-4234-9e30-766bc926b682
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971228907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2971228907
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2717675587
Short name T1034
Test name
Test status
Simulation time 58868027 ps
CPU time 2.06 seconds
Started Jul 31 05:47:28 PM PDT 24
Finished Jul 31 05:47:30 PM PDT 24
Peak memory 214996 kb
Host smart-c2061931-0070-47cd-a689-b3ae6f39560c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717675587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2717675587
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1907438311
Short name T289
Test name
Test status
Simulation time 116927559 ps
CPU time 2.11 seconds
Started Jul 31 05:47:29 PM PDT 24
Finished Jul 31 05:47:31 PM PDT 24
Peak memory 206772 kb
Host smart-80f16d38-8fe7-4f29-9bcd-e40fcbf94ae2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907438311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1907438311
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3430979785
Short name T1054
Test name
Test status
Simulation time 61923664 ps
CPU time 0.88 seconds
Started Jul 31 05:47:43 PM PDT 24
Finished Jul 31 05:47:44 PM PDT 24
Peak memory 206400 kb
Host smart-e9dabdc8-18da-4055-a391-9900af8fbfba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430979785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3430979785
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3650387431
Short name T995
Test name
Test status
Simulation time 53487041 ps
CPU time 0.83 seconds
Started Jul 31 05:47:39 PM PDT 24
Finished Jul 31 05:47:40 PM PDT 24
Peak memory 206640 kb
Host smart-d332376b-8b64-4386-95fd-faf43dc9d2c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650387431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3650387431
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2467864600
Short name T996
Test name
Test status
Simulation time 39715749 ps
CPU time 0.86 seconds
Started Jul 31 05:47:51 PM PDT 24
Finished Jul 31 05:47:52 PM PDT 24
Peak memory 206328 kb
Host smart-fe7b0d8f-5c5f-4022-915e-b199c876b70e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467864600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2467864600
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.18954838
Short name T1005
Test name
Test status
Simulation time 46525336 ps
CPU time 0.85 seconds
Started Jul 31 05:47:41 PM PDT 24
Finished Jul 31 05:47:41 PM PDT 24
Peak memory 206400 kb
Host smart-2d59ecb3-9939-4400-a00a-8aa46abbd5b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18954838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.18954838
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1197687254
Short name T1110
Test name
Test status
Simulation time 22678554 ps
CPU time 0.82 seconds
Started Jul 31 05:47:46 PM PDT 24
Finished Jul 31 05:47:47 PM PDT 24
Peak memory 206516 kb
Host smart-07354bf5-016a-4942-8da0-ec45965f0c7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197687254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1197687254
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.935116509
Short name T1092
Test name
Test status
Simulation time 47013906 ps
CPU time 0.86 seconds
Started Jul 31 05:47:45 PM PDT 24
Finished Jul 31 05:47:46 PM PDT 24
Peak memory 206576 kb
Host smart-57dc0ef1-75bb-4930-a7a9-e4a692217271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935116509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.935116509
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4215192294
Short name T1021
Test name
Test status
Simulation time 23923282 ps
CPU time 0.92 seconds
Started Jul 31 05:47:42 PM PDT 24
Finished Jul 31 05:47:44 PM PDT 24
Peak memory 206636 kb
Host smart-4f77c174-9efb-4753-a8f2-bbeaf2c263a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215192294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4215192294
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.4130726182
Short name T1106
Test name
Test status
Simulation time 23893744 ps
CPU time 0.86 seconds
Started Jul 31 05:47:48 PM PDT 24
Finished Jul 31 05:47:50 PM PDT 24
Peak memory 206616 kb
Host smart-7010763b-e641-4892-ab79-b5ec2f6f4f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130726182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.4130726182
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2147703002
Short name T1012
Test name
Test status
Simulation time 48890626 ps
CPU time 0.87 seconds
Started Jul 31 05:47:41 PM PDT 24
Finished Jul 31 05:47:42 PM PDT 24
Peak memory 206592 kb
Host smart-52ece496-a401-4045-aae1-6a69f2481b0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147703002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2147703002
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2444548845
Short name T1033
Test name
Test status
Simulation time 16772578 ps
CPU time 0.95 seconds
Started Jul 31 05:47:42 PM PDT 24
Finished Jul 31 05:47:43 PM PDT 24
Peak memory 206544 kb
Host smart-aab840bd-7a99-43ec-a3d6-c8e727151278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444548845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2444548845
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.41553514
Short name T261
Test name
Test status
Simulation time 25826443 ps
CPU time 1.2 seconds
Started Jul 31 05:47:24 PM PDT 24
Finished Jul 31 05:47:26 PM PDT 24
Peak memory 206636 kb
Host smart-6cf4c34b-6f7e-4d44-82f5-61bf68c285aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41553514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.41553514
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4171673488
Short name T1040
Test name
Test status
Simulation time 459787779 ps
CPU time 6.45 seconds
Started Jul 31 05:47:25 PM PDT 24
Finished Jul 31 05:47:32 PM PDT 24
Peak memory 206600 kb
Host smart-9216b33e-82c5-4496-b4fc-243a2ee1856b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171673488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.4171673488
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2823941958
Short name T1057
Test name
Test status
Simulation time 102384667 ps
CPU time 1.02 seconds
Started Jul 31 05:47:26 PM PDT 24
Finished Jul 31 05:47:27 PM PDT 24
Peak memory 206556 kb
Host smart-8693d3e6-55b0-417e-85cc-ff3f5d833440
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823941958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2823941958
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3194378925
Short name T994
Test name
Test status
Simulation time 27413602 ps
CPU time 1.34 seconds
Started Jul 31 05:47:30 PM PDT 24
Finished Jul 31 05:47:32 PM PDT 24
Peak memory 217676 kb
Host smart-f017b9b0-c3fd-4d29-999c-ed5f040c3369
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194378925 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3194378925
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2192256324
Short name T1120
Test name
Test status
Simulation time 30989064 ps
CPU time 0.95 seconds
Started Jul 31 05:47:25 PM PDT 24
Finished Jul 31 05:47:26 PM PDT 24
Peak memory 206548 kb
Host smart-1a6b52b8-92a6-4ce6-99db-b100e91451c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192256324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2192256324
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1361347394
Short name T990
Test name
Test status
Simulation time 14191208 ps
CPU time 0.88 seconds
Started Jul 31 05:47:25 PM PDT 24
Finished Jul 31 05:47:26 PM PDT 24
Peak memory 206616 kb
Host smart-3256c13b-251e-4ea6-9079-8560feb23af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361347394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1361347394
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2598521452
Short name T276
Test name
Test status
Simulation time 73136992 ps
CPU time 1.12 seconds
Started Jul 31 05:47:29 PM PDT 24
Finished Jul 31 05:47:30 PM PDT 24
Peak memory 206688 kb
Host smart-ab77e66b-28ea-4c7e-a51e-3ced17ce064f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598521452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2598521452
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3029024007
Short name T1123
Test name
Test status
Simulation time 78258274 ps
CPU time 3.04 seconds
Started Jul 31 05:47:33 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 215000 kb
Host smart-888c5508-68e9-43ef-aaf2-64cc8b312620
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029024007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3029024007
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3059146578
Short name T288
Test name
Test status
Simulation time 95172729 ps
CPU time 1.49 seconds
Started Jul 31 05:47:27 PM PDT 24
Finished Jul 31 05:47:28 PM PDT 24
Peak memory 206800 kb
Host smart-0ace1b54-ba3e-4ad2-b4a7-529cc48c13d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059146578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3059146578
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.4180228786
Short name T1101
Test name
Test status
Simulation time 58389273 ps
CPU time 0.93 seconds
Started Jul 31 05:47:38 PM PDT 24
Finished Jul 31 05:47:39 PM PDT 24
Peak memory 206620 kb
Host smart-e255beb5-61fa-4218-9fec-e9e46bb78e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180228786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.4180228786
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.656387499
Short name T1091
Test name
Test status
Simulation time 36780774 ps
CPU time 0.79 seconds
Started Jul 31 05:47:42 PM PDT 24
Finished Jul 31 05:47:42 PM PDT 24
Peak memory 206412 kb
Host smart-3c81fb9a-115d-4a1c-ae6e-61aff7ca6243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656387499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.656387499
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3548902351
Short name T1035
Test name
Test status
Simulation time 13454512 ps
CPU time 0.9 seconds
Started Jul 31 05:47:43 PM PDT 24
Finished Jul 31 05:47:44 PM PDT 24
Peak memory 206580 kb
Host smart-8a1104d5-edca-4c55-a1a5-4ca7cd732a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548902351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3548902351
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.724350653
Short name T1029
Test name
Test status
Simulation time 88594559 ps
CPU time 0.77 seconds
Started Jul 31 05:47:43 PM PDT 24
Finished Jul 31 05:47:44 PM PDT 24
Peak memory 206436 kb
Host smart-8a6be52e-40b1-45fa-a895-9e49fd71eec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724350653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.724350653
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2562749274
Short name T1051
Test name
Test status
Simulation time 18526784 ps
CPU time 0.86 seconds
Started Jul 31 05:47:42 PM PDT 24
Finished Jul 31 05:47:43 PM PDT 24
Peak memory 206544 kb
Host smart-793168dd-46da-4752-88b5-566183216d3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562749274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2562749274
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2228235816
Short name T1015
Test name
Test status
Simulation time 32222512 ps
CPU time 0.93 seconds
Started Jul 31 05:47:41 PM PDT 24
Finished Jul 31 05:47:42 PM PDT 24
Peak memory 206584 kb
Host smart-60232291-08c1-431a-9695-173ed081d032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228235816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2228235816
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3197006644
Short name T1080
Test name
Test status
Simulation time 24262405 ps
CPU time 0.88 seconds
Started Jul 31 05:47:45 PM PDT 24
Finished Jul 31 05:47:51 PM PDT 24
Peak memory 206516 kb
Host smart-61c238ae-5c7e-4eec-ba34-6d839a7618ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197006644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3197006644
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1462062475
Short name T1113
Test name
Test status
Simulation time 51498134 ps
CPU time 0.92 seconds
Started Jul 31 05:47:48 PM PDT 24
Finished Jul 31 05:47:49 PM PDT 24
Peak memory 206624 kb
Host smart-f9add01e-5fa4-4ad1-a4be-ff32f88c482c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462062475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1462062475
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3241901096
Short name T1100
Test name
Test status
Simulation time 25944417 ps
CPU time 0.85 seconds
Started Jul 31 05:47:43 PM PDT 24
Finished Jul 31 05:47:44 PM PDT 24
Peak memory 206620 kb
Host smart-6b064c33-f392-421c-a91b-7071bd7d34d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241901096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3241901096
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.4238055596
Short name T1073
Test name
Test status
Simulation time 13502568 ps
CPU time 0.9 seconds
Started Jul 31 05:47:40 PM PDT 24
Finished Jul 31 05:47:41 PM PDT 24
Peak memory 206580 kb
Host smart-9ef3498c-64b7-4442-9268-49f1f08f128f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238055596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.4238055596
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.917757733
Short name T268
Test name
Test status
Simulation time 25755282 ps
CPU time 1.03 seconds
Started Jul 31 05:47:21 PM PDT 24
Finished Jul 31 05:47:23 PM PDT 24
Peak memory 206656 kb
Host smart-04bf89e3-a784-4200-a0f8-2606650a7340
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917757733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.917757733
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2845238178
Short name T1014
Test name
Test status
Simulation time 137101110 ps
CPU time 2.09 seconds
Started Jul 31 05:47:25 PM PDT 24
Finished Jul 31 05:47:27 PM PDT 24
Peak memory 206564 kb
Host smart-749cd558-26fc-4d46-a29f-1e78282605ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845238178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2845238178
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.4221236075
Short name T1038
Test name
Test status
Simulation time 18238018 ps
CPU time 1 seconds
Started Jul 31 05:47:28 PM PDT 24
Finished Jul 31 05:47:29 PM PDT 24
Peak memory 206584 kb
Host smart-bfc776bc-a44e-4a40-9f03-e881f137fc17
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221236075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.4221236075
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1727040049
Short name T1013
Test name
Test status
Simulation time 38079531 ps
CPU time 0.88 seconds
Started Jul 31 05:47:28 PM PDT 24
Finished Jul 31 05:47:29 PM PDT 24
Peak memory 206792 kb
Host smart-20145d5a-3b44-47cb-a48f-6ee632ecdb4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727040049 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1727040049
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.4242662168
Short name T998
Test name
Test status
Simulation time 16086687 ps
CPU time 1 seconds
Started Jul 31 05:47:27 PM PDT 24
Finished Jul 31 05:47:28 PM PDT 24
Peak memory 206592 kb
Host smart-9b2fca98-3009-4d0c-9b5d-f2619a71bcd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242662168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.4242662168
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1970213087
Short name T1041
Test name
Test status
Simulation time 15754482 ps
CPU time 0.92 seconds
Started Jul 31 05:47:33 PM PDT 24
Finished Jul 31 05:47:34 PM PDT 24
Peak memory 206556 kb
Host smart-a362b8cf-f27a-42bf-bac8-6174e0644c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970213087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1970213087
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3481549618
Short name T1104
Test name
Test status
Simulation time 61055023 ps
CPU time 1.37 seconds
Started Jul 31 05:47:25 PM PDT 24
Finished Jul 31 05:47:26 PM PDT 24
Peak memory 206720 kb
Host smart-8bb7db60-dac6-4bb2-b446-eecb4abaa8e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481549618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3481549618
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1835112338
Short name T1036
Test name
Test status
Simulation time 54163901 ps
CPU time 2.07 seconds
Started Jul 31 05:47:26 PM PDT 24
Finished Jul 31 05:47:28 PM PDT 24
Peak memory 215020 kb
Host smart-bbf10b47-5f23-4439-bd05-f1b27c8ff6e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835112338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1835112338
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.4234416245
Short name T1088
Test name
Test status
Simulation time 167632113 ps
CPU time 2.43 seconds
Started Jul 31 05:47:24 PM PDT 24
Finished Jul 31 05:47:27 PM PDT 24
Peak memory 206980 kb
Host smart-20ae8701-21fa-46e6-bede-1286f3defa97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234416245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.4234416245
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1323882560
Short name T1061
Test name
Test status
Simulation time 23929540 ps
CPU time 0.87 seconds
Started Jul 31 05:47:49 PM PDT 24
Finished Jul 31 05:47:50 PM PDT 24
Peak memory 206608 kb
Host smart-9d70c5d8-b7b4-41d3-8e0d-5fb7ede829ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323882560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1323882560
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3415776326
Short name T991
Test name
Test status
Simulation time 12680407 ps
CPU time 0.92 seconds
Started Jul 31 05:47:47 PM PDT 24
Finished Jul 31 05:47:48 PM PDT 24
Peak memory 206560 kb
Host smart-ace3d908-4341-4562-9723-667c63db98f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415776326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3415776326
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2833967924
Short name T1017
Test name
Test status
Simulation time 89730512 ps
CPU time 0.85 seconds
Started Jul 31 05:47:48 PM PDT 24
Finished Jul 31 05:47:50 PM PDT 24
Peak memory 206432 kb
Host smart-514feae1-33ba-47bf-ac8f-3b1c9dcaac67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833967924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2833967924
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3811349903
Short name T1122
Test name
Test status
Simulation time 21442684 ps
CPU time 0.9 seconds
Started Jul 31 05:47:41 PM PDT 24
Finished Jul 31 05:47:42 PM PDT 24
Peak memory 206492 kb
Host smart-8a433f74-5e0a-4e36-96bf-1963827692ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811349903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3811349903
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1038909988
Short name T1049
Test name
Test status
Simulation time 11743742 ps
CPU time 0.86 seconds
Started Jul 31 05:47:47 PM PDT 24
Finished Jul 31 05:47:48 PM PDT 24
Peak memory 206528 kb
Host smart-84895e9c-7b18-424f-b467-32a3018036fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038909988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1038909988
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3673373971
Short name T1003
Test name
Test status
Simulation time 50154065 ps
CPU time 0.86 seconds
Started Jul 31 05:47:39 PM PDT 24
Finished Jul 31 05:47:40 PM PDT 24
Peak memory 206616 kb
Host smart-f979d9cd-a451-44da-a4b3-870385375aed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673373971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3673373971
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1641382858
Short name T1076
Test name
Test status
Simulation time 35126071 ps
CPU time 0.82 seconds
Started Jul 31 05:47:42 PM PDT 24
Finished Jul 31 05:47:42 PM PDT 24
Peak memory 206428 kb
Host smart-a7f8af6e-36c8-4b10-abcb-a3689c56ef8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641382858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1641382858
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2984484160
Short name T1001
Test name
Test status
Simulation time 38260824 ps
CPU time 0.86 seconds
Started Jul 31 05:47:43 PM PDT 24
Finished Jul 31 05:47:44 PM PDT 24
Peak memory 206392 kb
Host smart-91d4f81d-393c-4034-934c-b50211b2b98b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984484160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2984484160
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2725961869
Short name T1018
Test name
Test status
Simulation time 48816773 ps
CPU time 0.86 seconds
Started Jul 31 05:47:50 PM PDT 24
Finished Jul 31 05:47:50 PM PDT 24
Peak memory 206580 kb
Host smart-fb08c785-c244-4a5a-860f-44a6d9e23267
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725961869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2725961869
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1117393559
Short name T1048
Test name
Test status
Simulation time 28793037 ps
CPU time 0.91 seconds
Started Jul 31 05:47:52 PM PDT 24
Finished Jul 31 05:47:53 PM PDT 24
Peak memory 206612 kb
Host smart-39b7e7ad-b227-4471-ae18-a80dcd6a9f39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117393559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1117393559
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2228483925
Short name T1006
Test name
Test status
Simulation time 28572647 ps
CPU time 1.14 seconds
Started Jul 31 05:47:28 PM PDT 24
Finished Jul 31 05:47:29 PM PDT 24
Peak memory 215080 kb
Host smart-7e15ed72-9916-4039-8be1-78b32ed1cb24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228483925 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2228483925
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2941850758
Short name T1059
Test name
Test status
Simulation time 13711554 ps
CPU time 0.91 seconds
Started Jul 31 05:47:24 PM PDT 24
Finished Jul 31 05:47:25 PM PDT 24
Peak memory 206524 kb
Host smart-52cdc9a3-0430-40d0-8e52-3b141cd515f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941850758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2941850758
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1048290780
Short name T1082
Test name
Test status
Simulation time 14307996 ps
CPU time 0.86 seconds
Started Jul 31 05:47:24 PM PDT 24
Finished Jul 31 05:47:25 PM PDT 24
Peak memory 206572 kb
Host smart-fd7063aa-dedf-4303-935d-db2150c8800d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048290780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1048290780
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3555257923
Short name T1118
Test name
Test status
Simulation time 29292093 ps
CPU time 1.1 seconds
Started Jul 31 05:47:30 PM PDT 24
Finished Jul 31 05:47:31 PM PDT 24
Peak memory 206780 kb
Host smart-abb81c39-6810-495b-92ab-0815706d4b2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555257923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3555257923
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3601153789
Short name T1079
Test name
Test status
Simulation time 494140401 ps
CPU time 2.53 seconds
Started Jul 31 05:47:29 PM PDT 24
Finished Jul 31 05:47:32 PM PDT 24
Peak memory 215072 kb
Host smart-722545a7-ed50-4510-8953-aa07131094a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601153789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3601153789
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1586545211
Short name T1077
Test name
Test status
Simulation time 200548493 ps
CPU time 1.63 seconds
Started Jul 31 05:47:27 PM PDT 24
Finished Jul 31 05:47:29 PM PDT 24
Peak memory 206852 kb
Host smart-91097a27-52fa-4bcb-bdbe-09867179653a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586545211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1586545211
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2857625850
Short name T1083
Test name
Test status
Simulation time 23782867 ps
CPU time 1.62 seconds
Started Jul 31 05:47:30 PM PDT 24
Finished Jul 31 05:47:31 PM PDT 24
Peak memory 214920 kb
Host smart-c978ccd3-1f33-40a3-a459-7d3513f6827b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857625850 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2857625850
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.734493479
Short name T1027
Test name
Test status
Simulation time 45150546 ps
CPU time 0.88 seconds
Started Jul 31 05:47:30 PM PDT 24
Finished Jul 31 05:47:31 PM PDT 24
Peak memory 206412 kb
Host smart-7012e03d-a995-4e08-b40e-7633da80321e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734493479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.734493479
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1636699039
Short name T1119
Test name
Test status
Simulation time 117001968 ps
CPU time 0.86 seconds
Started Jul 31 05:47:31 PM PDT 24
Finished Jul 31 05:47:32 PM PDT 24
Peak memory 206616 kb
Host smart-ef9feec7-3a2a-48c5-94e5-2c3bd88e04c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636699039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1636699039
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4052103354
Short name T1047
Test name
Test status
Simulation time 15685350 ps
CPU time 1 seconds
Started Jul 31 05:47:36 PM PDT 24
Finished Jul 31 05:47:37 PM PDT 24
Peak memory 206760 kb
Host smart-9e7fa9b2-76d5-47b3-8aad-bd694a762951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052103354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.4052103354
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1426875478
Short name T1067
Test name
Test status
Simulation time 266406880 ps
CPU time 2.7 seconds
Started Jul 31 05:47:31 PM PDT 24
Finished Jul 31 05:47:34 PM PDT 24
Peak memory 215008 kb
Host smart-12c8ee0e-b0a8-4ffa-a33d-f6901040c2a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426875478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1426875478
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.796571625
Short name T1089
Test name
Test status
Simulation time 339676852 ps
CPU time 2.45 seconds
Started Jul 31 05:47:35 PM PDT 24
Finished Jul 31 05:47:38 PM PDT 24
Peak memory 206812 kb
Host smart-20da0067-0a2a-456c-86e4-39af42ebaa39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796571625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.796571625
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2059331644
Short name T1063
Test name
Test status
Simulation time 66085258 ps
CPU time 1.3 seconds
Started Jul 31 05:47:30 PM PDT 24
Finished Jul 31 05:47:31 PM PDT 24
Peak memory 214964 kb
Host smart-6fba72e8-bf3c-4609-971a-c0c33b5247eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059331644 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2059331644
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2822338808
Short name T272
Test name
Test status
Simulation time 15793259 ps
CPU time 0.92 seconds
Started Jul 31 05:47:29 PM PDT 24
Finished Jul 31 05:47:31 PM PDT 24
Peak memory 206584 kb
Host smart-0ee2e32b-39f0-4d62-aff6-578453315708
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822338808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2822338808
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2161666340
Short name T1052
Test name
Test status
Simulation time 15501570 ps
CPU time 0.78 seconds
Started Jul 31 05:47:31 PM PDT 24
Finished Jul 31 05:47:32 PM PDT 24
Peak memory 206344 kb
Host smart-9f2f2b07-c777-47de-8efd-467c6acfe9c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161666340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2161666340
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1423925185
Short name T271
Test name
Test status
Simulation time 46159632 ps
CPU time 1.2 seconds
Started Jul 31 05:47:35 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 206656 kb
Host smart-80ed32a6-17a4-4ea7-b5c4-4786a4d13454
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423925185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1423925185
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2464226474
Short name T1115
Test name
Test status
Simulation time 65698640 ps
CPU time 1.42 seconds
Started Jul 31 05:47:36 PM PDT 24
Finished Jul 31 05:47:38 PM PDT 24
Peak memory 215072 kb
Host smart-0561a757-989d-46a7-8128-99483ef08f81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464226474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2464226474
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2402227129
Short name T1026
Test name
Test status
Simulation time 108980071 ps
CPU time 1.65 seconds
Started Jul 31 05:47:31 PM PDT 24
Finished Jul 31 05:47:33 PM PDT 24
Peak memory 214880 kb
Host smart-da85c805-4acd-4d96-b7d4-51bad4ea7ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402227129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2402227129
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.408611505
Short name T1078
Test name
Test status
Simulation time 61055039 ps
CPU time 1.49 seconds
Started Jul 31 05:47:29 PM PDT 24
Finished Jul 31 05:47:31 PM PDT 24
Peak memory 214980 kb
Host smart-b6c9f2ac-09cc-4d7a-bd8c-80bdb268496b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408611505 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.408611505
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.165394904
Short name T267
Test name
Test status
Simulation time 12592524 ps
CPU time 0.88 seconds
Started Jul 31 05:47:32 PM PDT 24
Finished Jul 31 05:47:33 PM PDT 24
Peak memory 206596 kb
Host smart-61f5b415-8814-4660-83bd-8890a172a930
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165394904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.165394904
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3826839688
Short name T1002
Test name
Test status
Simulation time 55899058 ps
CPU time 0.8 seconds
Started Jul 31 05:47:36 PM PDT 24
Finished Jul 31 05:47:37 PM PDT 24
Peak memory 206404 kb
Host smart-cac1ae1d-afa2-4d73-ae10-4b5824956fe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826839688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3826839688
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3896656646
Short name T273
Test name
Test status
Simulation time 50470119 ps
CPU time 1.04 seconds
Started Jul 31 05:47:33 PM PDT 24
Finished Jul 31 05:47:34 PM PDT 24
Peak memory 206772 kb
Host smart-c2e1aa20-33f2-4920-8b80-65e1a0411103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896656646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3896656646
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2131811053
Short name T1009
Test name
Test status
Simulation time 208481014 ps
CPU time 2.29 seconds
Started Jul 31 05:47:32 PM PDT 24
Finished Jul 31 05:47:35 PM PDT 24
Peak memory 215052 kb
Host smart-22612e4e-729a-4de3-aaff-5403c21b8dae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131811053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2131811053
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.844884601
Short name T1056
Test name
Test status
Simulation time 57081137 ps
CPU time 1.8 seconds
Started Jul 31 05:47:32 PM PDT 24
Finished Jul 31 05:47:34 PM PDT 24
Peak memory 206816 kb
Host smart-fc46b700-0964-42ff-b874-0c9bea4c9f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844884601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.844884601
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1547545545
Short name T1032
Test name
Test status
Simulation time 106451299 ps
CPU time 1.28 seconds
Started Jul 31 05:47:33 PM PDT 24
Finished Jul 31 05:47:35 PM PDT 24
Peak memory 217972 kb
Host smart-c648ac66-5381-4aa2-b91f-0de3fbc4c407
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547545545 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1547545545
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1498255301
Short name T264
Test name
Test status
Simulation time 24896483 ps
CPU time 0.85 seconds
Started Jul 31 05:47:36 PM PDT 24
Finished Jul 31 05:47:37 PM PDT 24
Peak memory 206544 kb
Host smart-52ad66c4-ed8b-47ec-b8c6-bf548c640c81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498255301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1498255301
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.4207512225
Short name T993
Test name
Test status
Simulation time 20924629 ps
CPU time 0.82 seconds
Started Jul 31 05:47:32 PM PDT 24
Finished Jul 31 05:47:33 PM PDT 24
Peak memory 206432 kb
Host smart-21f04846-0797-46d0-8e5d-79b7774d015a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207512225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4207512225
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2995120414
Short name T1114
Test name
Test status
Simulation time 26353178 ps
CPU time 0.92 seconds
Started Jul 31 05:47:30 PM PDT 24
Finished Jul 31 05:47:31 PM PDT 24
Peak memory 206764 kb
Host smart-1d42b272-3ea1-4829-b34f-e34965878a5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995120414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2995120414
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4224519486
Short name T1084
Test name
Test status
Simulation time 144893651 ps
CPU time 2.03 seconds
Started Jul 31 05:47:31 PM PDT 24
Finished Jul 31 05:47:34 PM PDT 24
Peak memory 215068 kb
Host smart-91a9602f-9bdb-4dde-bbd0-4818905bbf23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224519486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4224519486
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.523264757
Short name T228
Test name
Test status
Simulation time 112617670 ps
CPU time 1.84 seconds
Started Jul 31 05:47:29 PM PDT 24
Finished Jul 31 05:47:30 PM PDT 24
Peak memory 206696 kb
Host smart-2ee528b4-e22f-4372-9492-c0a85145cdae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523264757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.523264757
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2002680648
Short name T209
Test name
Test status
Simulation time 47185274 ps
CPU time 1.17 seconds
Started Jul 31 05:48:47 PM PDT 24
Finished Jul 31 05:48:49 PM PDT 24
Peak memory 218792 kb
Host smart-a33a086e-bbd2-450a-9a11-7f936f5e0fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002680648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2002680648
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.4248917730
Short name T640
Test name
Test status
Simulation time 17488993 ps
CPU time 1.09 seconds
Started Jul 31 05:48:52 PM PDT 24
Finished Jul 31 05:48:53 PM PDT 24
Peak memory 206724 kb
Host smart-b3fc878c-6e3c-4f95-9083-eee2492a3118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248917730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.4248917730
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_err.4152108514
Short name T686
Test name
Test status
Simulation time 42384969 ps
CPU time 1.12 seconds
Started Jul 31 05:48:51 PM PDT 24
Finished Jul 31 05:48:52 PM PDT 24
Peak memory 220720 kb
Host smart-ff56f6ea-b8e2-47b7-af28-04c9b728c64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152108514 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.4152108514
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.152362342
Short name T81
Test name
Test status
Simulation time 34053040 ps
CPU time 0.93 seconds
Started Jul 31 05:48:56 PM PDT 24
Finished Jul 31 05:48:57 PM PDT 24
Peak memory 215612 kb
Host smart-92332519-2be3-4bcc-819e-3a49af2daed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152362342 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.152362342
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.250856107
Short name T973
Test name
Test status
Simulation time 21676922 ps
CPU time 0.89 seconds
Started Jul 31 05:48:46 PM PDT 24
Finished Jul 31 05:48:47 PM PDT 24
Peak memory 207100 kb
Host smart-3487c5f5-7a62-4d5e-9527-c65562f41fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250856107 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.250856107
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.1644128208
Short name T643
Test name
Test status
Simulation time 15181648 ps
CPU time 1 seconds
Started Jul 31 05:48:44 PM PDT 24
Finished Jul 31 05:48:45 PM PDT 24
Peak memory 215288 kb
Host smart-0f51b4fa-b4fb-445b-9fb3-b9b7499047e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644128208 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1644128208
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1602861823
Short name T676
Test name
Test status
Simulation time 1759148017 ps
CPU time 5.23 seconds
Started Jul 31 05:48:34 PM PDT 24
Finished Jul 31 05:48:39 PM PDT 24
Peak memory 220476 kb
Host smart-82d1ee5e-918f-46dc-9e2e-5d2cd6744a52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602861823 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1602861823
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2111375843
Short name T238
Test name
Test status
Simulation time 51576703071 ps
CPU time 1132.79 seconds
Started Jul 31 05:48:48 PM PDT 24
Finished Jul 31 06:07:41 PM PDT 24
Peak memory 219708 kb
Host smart-6f3f956b-3a15-4e2d-bf21-11692958755f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111375843 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2111375843
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.2456808665
Short name T36
Test name
Test status
Simulation time 45479912 ps
CPU time 1.15 seconds
Started Jul 31 05:48:48 PM PDT 24
Finished Jul 31 05:48:49 PM PDT 24
Peak memory 218636 kb
Host smart-2f121af5-4fcf-4eb4-86ea-448633cada1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456808665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2456808665
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.2712033748
Short name T802
Test name
Test status
Simulation time 69987567 ps
CPU time 1.2 seconds
Started Jul 31 05:48:46 PM PDT 24
Finished Jul 31 05:48:48 PM PDT 24
Peak memory 214948 kb
Host smart-53214e12-c1ae-49ce-82b0-05d38658f35f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712033748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2712033748
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2249415215
Short name T411
Test name
Test status
Simulation time 28624104 ps
CPU time 1.12 seconds
Started Jul 31 05:48:51 PM PDT 24
Finished Jul 31 05:48:52 PM PDT 24
Peak memory 218276 kb
Host smart-37ffdc2e-fb2d-4e26-afd3-ee98d6b2ed60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249415215 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2249415215
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3801821420
Short name T696
Test name
Test status
Simulation time 28023677 ps
CPU time 0.87 seconds
Started Jul 31 05:48:58 PM PDT 24
Finished Jul 31 05:48:59 PM PDT 24
Peak memory 219584 kb
Host smart-031a2022-b65d-4e76-9464-3ffb0f1f9ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801821420 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3801821420
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3510597687
Short name T933
Test name
Test status
Simulation time 71141191 ps
CPU time 1.6 seconds
Started Jul 31 05:48:50 PM PDT 24
Finished Jul 31 05:48:52 PM PDT 24
Peak memory 218604 kb
Host smart-e72741b3-575d-4182-a69f-5c791992c02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510597687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3510597687
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.3671118674
Short name T324
Test name
Test status
Simulation time 21297670 ps
CPU time 0.94 seconds
Started Jul 31 05:48:51 PM PDT 24
Finished Jul 31 05:48:52 PM PDT 24
Peak memory 207040 kb
Host smart-6ffa8822-c38d-45d1-962a-c7aec9d3e633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671118674 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3671118674
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.3926548297
Short name T972
Test name
Test status
Simulation time 180964826 ps
CPU time 0.89 seconds
Started Jul 31 05:48:55 PM PDT 24
Finished Jul 31 05:48:56 PM PDT 24
Peak memory 215268 kb
Host smart-22ca1fab-5597-43ad-9505-dcea676690fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926548297 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3926548297
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1096666464
Short name T734
Test name
Test status
Simulation time 63693901 ps
CPU time 1.79 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 215252 kb
Host smart-8d140ad6-6043-40a8-8010-687dc6e79d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096666464 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1096666464
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3231968506
Short name T241
Test name
Test status
Simulation time 18592316506 ps
CPU time 415.32 seconds
Started Jul 31 05:48:50 PM PDT 24
Finished Jul 31 05:55:46 PM PDT 24
Peak memory 218856 kb
Host smart-e091efa4-0d0f-45e9-935e-7919f3594a6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231968506 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3231968506
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3039863704
Short name T982
Test name
Test status
Simulation time 33284751 ps
CPU time 1.36 seconds
Started Jul 31 05:49:11 PM PDT 24
Finished Jul 31 05:49:13 PM PDT 24
Peak memory 215644 kb
Host smart-1e7e2c3b-01ea-4b4b-99c8-5cea214a3fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039863704 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3039863704
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.1967435533
Short name T493
Test name
Test status
Simulation time 17019483 ps
CPU time 0.82 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:08 PM PDT 24
Peak memory 215896 kb
Host smart-c5100898-060f-47fc-8284-327a495c1a8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967435533 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1967435533
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3875546426
Short name T163
Test name
Test status
Simulation time 43661953 ps
CPU time 1.2 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:09 PM PDT 24
Peak memory 216956 kb
Host smart-7f3b9ee5-dcb3-4720-987f-e89abfbeb493
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875546426 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3875546426
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_genbits.2426003425
Short name T558
Test name
Test status
Simulation time 157854160 ps
CPU time 1.36 seconds
Started Jul 31 05:49:06 PM PDT 24
Finished Jul 31 05:49:08 PM PDT 24
Peak memory 219024 kb
Host smart-f5a47250-4c1d-437f-bd2a-fbedac0be9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426003425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2426003425
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1462190938
Short name T86
Test name
Test status
Simulation time 21953332 ps
CPU time 0.92 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:08 PM PDT 24
Peak memory 215828 kb
Host smart-4fd2a5bc-57d7-4728-a688-37379c223e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462190938 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1462190938
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1348714378
Short name T832
Test name
Test status
Simulation time 47477186 ps
CPU time 0.91 seconds
Started Jul 31 05:49:12 PM PDT 24
Finished Jul 31 05:49:13 PM PDT 24
Peak memory 215320 kb
Host smart-2af9f9a2-cb31-44c9-9173-af625aa07b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348714378 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1348714378
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3293195551
Short name T951
Test name
Test status
Simulation time 120873348 ps
CPU time 1.17 seconds
Started Jul 31 05:49:00 PM PDT 24
Finished Jul 31 05:49:01 PM PDT 24
Peak memory 215320 kb
Host smart-3c5e576a-a113-4bf7-a243-c9510a9692c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293195551 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3293195551
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2437575747
Short name T231
Test name
Test status
Simulation time 591937367272 ps
CPU time 1887.16 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 06:20:36 PM PDT 24
Peak memory 226192 kb
Host smart-283e55c4-9c38-47e7-bae6-c7a83e1f61a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437575747 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2437575747
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.3025428179
Short name T191
Test name
Test status
Simulation time 31018733 ps
CPU time 1.17 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 218272 kb
Host smart-0487c814-49fd-4393-97f4-0a68113bdfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025428179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3025428179
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/101.edn_alert.2569219413
Short name T427
Test name
Test status
Simulation time 350233385 ps
CPU time 1.35 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 220684 kb
Host smart-e59b5e95-3ed7-4aee-925e-624963174fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569219413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2569219413
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.3075387351
Short name T874
Test name
Test status
Simulation time 74940185 ps
CPU time 2.4 seconds
Started Jul 31 05:50:06 PM PDT 24
Finished Jul 31 05:50:09 PM PDT 24
Peak memory 220324 kb
Host smart-936f5cbc-372e-491b-b787-feb7b07dd046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075387351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3075387351
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.3901861274
Short name T849
Test name
Test status
Simulation time 80306957 ps
CPU time 1.22 seconds
Started Jul 31 05:50:02 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 220108 kb
Host smart-bafad41b-cbed-49d6-921c-b1d3ad69794c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901861274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.3901861274
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.3847639903
Short name T249
Test name
Test status
Simulation time 52254004 ps
CPU time 0.97 seconds
Started Jul 31 05:50:11 PM PDT 24
Finished Jul 31 05:50:12 PM PDT 24
Peak memory 217344 kb
Host smart-b3164799-13d8-47f2-a9c1-3c829736f51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847639903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3847639903
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.766998737
Short name T494
Test name
Test status
Simulation time 87220653 ps
CPU time 1.17 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:05 PM PDT 24
Peak memory 219692 kb
Host smart-92a231ae-2710-4618-b476-0a561ebdd8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766998737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.766998737
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.3769875788
Short name T665
Test name
Test status
Simulation time 53796560 ps
CPU time 1.08 seconds
Started Jul 31 05:50:12 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 217176 kb
Host smart-6a95c7aa-5630-4fd7-b2f5-cfd84cd004ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769875788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3769875788
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1895519850
Short name T761
Test name
Test status
Simulation time 67115784 ps
CPU time 1.21 seconds
Started Jul 31 05:50:13 PM PDT 24
Finished Jul 31 05:50:15 PM PDT 24
Peak memory 218912 kb
Host smart-6df56a1d-016e-4ef6-8728-e00a3685aa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895519850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1895519850
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.3940610937
Short name T985
Test name
Test status
Simulation time 39282371 ps
CPU time 1.17 seconds
Started Jul 31 05:50:07 PM PDT 24
Finished Jul 31 05:50:08 PM PDT 24
Peak memory 218676 kb
Host smart-1ecc6924-2477-46a9-be80-c1a3c0236876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940610937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.3940610937
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.1368469529
Short name T42
Test name
Test status
Simulation time 176437694 ps
CPU time 1.53 seconds
Started Jul 31 05:50:06 PM PDT 24
Finished Jul 31 05:50:08 PM PDT 24
Peak memory 218644 kb
Host smart-fdd3b8b5-5434-45e4-beca-18baa665fe7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368469529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1368469529
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.131894405
Short name T574
Test name
Test status
Simulation time 65535249 ps
CPU time 1.04 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 218908 kb
Host smart-26f6fad2-3f39-406c-a16e-12111697dd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131894405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.131894405
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.3105655803
Short name T344
Test name
Test status
Simulation time 62445501 ps
CPU time 2.06 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:03 PM PDT 24
Peak memory 220072 kb
Host smart-a2bd95ee-4bd3-4dad-8e46-6ab00cca47aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105655803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3105655803
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.605492037
Short name T456
Test name
Test status
Simulation time 26659683 ps
CPU time 1.21 seconds
Started Jul 31 05:50:13 PM PDT 24
Finished Jul 31 05:50:15 PM PDT 24
Peak memory 219856 kb
Host smart-7080a944-7ebc-41f6-8d50-174310e487bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605492037 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.605492037
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.2236995881
Short name T620
Test name
Test status
Simulation time 56641871 ps
CPU time 1.96 seconds
Started Jul 31 05:50:07 PM PDT 24
Finished Jul 31 05:50:09 PM PDT 24
Peak memory 218664 kb
Host smart-d8b656e5-718f-437d-bf64-2d6977fea85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236995881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2236995881
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.3676039259
Short name T586
Test name
Test status
Simulation time 174447497 ps
CPU time 1.16 seconds
Started Jul 31 05:50:07 PM PDT 24
Finished Jul 31 05:50:08 PM PDT 24
Peak memory 218448 kb
Host smart-14cd72a5-7431-48b1-a21d-d29c8ddd73f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676039259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3676039259
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3471421217
Short name T595
Test name
Test status
Simulation time 45863670 ps
CPU time 1.35 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 217144 kb
Host smart-b953765c-16ba-426c-98c2-1ddfabb50347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471421217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3471421217
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2463344544
Short name T700
Test name
Test status
Simulation time 25288277 ps
CPU time 1.16 seconds
Started Jul 31 05:48:59 PM PDT 24
Finished Jul 31 05:49:01 PM PDT 24
Peak memory 218424 kb
Host smart-4a7aeada-3d90-47a3-afbc-a2a45ed6893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463344544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2463344544
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.970995184
Short name T778
Test name
Test status
Simulation time 26907157 ps
CPU time 0.97 seconds
Started Jul 31 05:49:01 PM PDT 24
Finished Jul 31 05:49:02 PM PDT 24
Peak memory 214892 kb
Host smart-84274094-a46c-43dd-aa2b-b3f0e88b3adf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970995184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.970995184
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.4052287436
Short name T819
Test name
Test status
Simulation time 40592505 ps
CPU time 0.86 seconds
Started Jul 31 05:49:02 PM PDT 24
Finished Jul 31 05:49:03 PM PDT 24
Peak memory 216212 kb
Host smart-0e41f4c7-3cf2-419f-80be-7279ac7161f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052287436 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.4052287436
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.4252343550
Short name T796
Test name
Test status
Simulation time 66629103 ps
CPU time 1.19 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:04 PM PDT 24
Peak memory 216964 kb
Host smart-940c6eaf-96e1-4a33-a9fb-df31582b7e0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252343550 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.4252343550
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2841860576
Short name T112
Test name
Test status
Simulation time 26761451 ps
CPU time 0.99 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:08 PM PDT 24
Peak memory 219768 kb
Host smart-079911aa-9c86-4145-b7b9-3b40e54645a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841860576 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2841860576
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_smoke.2590021198
Short name T375
Test name
Test status
Simulation time 38588267 ps
CPU time 0.96 seconds
Started Jul 31 05:49:05 PM PDT 24
Finished Jul 31 05:49:07 PM PDT 24
Peak memory 215072 kb
Host smart-8fc842db-291c-48dc-aa25-190504016c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590021198 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2590021198
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1855168299
Short name T632
Test name
Test status
Simulation time 288022096 ps
CPU time 3.5 seconds
Started Jul 31 05:49:47 PM PDT 24
Finished Jul 31 05:49:51 PM PDT 24
Peak memory 218448 kb
Host smart-b8ad7d20-2009-46c2-9fc1-2fa01d6ef354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855168299 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1855168299
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.5378212
Short name T236
Test name
Test status
Simulation time 322434765511 ps
CPU time 1871.88 seconds
Started Jul 31 05:49:01 PM PDT 24
Finished Jul 31 06:20:13 PM PDT 24
Peak memory 225640 kb
Host smart-1606befe-abb4-41d9-b8c7-bbca7235396d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5378212 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.5378212
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.1705208112
Short name T597
Test name
Test status
Simulation time 91518246 ps
CPU time 1.16 seconds
Started Jul 31 05:50:12 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 215660 kb
Host smart-ffef5ae1-465c-458c-bce8-4ecf372388af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705208112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1705208112
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.2079921989
Short name T393
Test name
Test status
Simulation time 70144605 ps
CPU time 1.21 seconds
Started Jul 31 05:50:09 PM PDT 24
Finished Jul 31 05:50:10 PM PDT 24
Peak memory 218976 kb
Host smart-96c59b3f-81c2-42db-9a0b-3cf53e5d5167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079921989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2079921989
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.3851744412
Short name T743
Test name
Test status
Simulation time 30477325 ps
CPU time 1.23 seconds
Started Jul 31 05:50:07 PM PDT 24
Finished Jul 31 05:50:08 PM PDT 24
Peak memory 215596 kb
Host smart-81dc2f7c-388f-4014-a208-36975ae67bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851744412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.3851744412
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.76638653
Short name T30
Test name
Test status
Simulation time 55463772 ps
CPU time 1.24 seconds
Started Jul 31 05:50:06 PM PDT 24
Finished Jul 31 05:50:08 PM PDT 24
Peak memory 217188 kb
Host smart-c272474d-c1f6-407c-be8d-2a9e7922f31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76638653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.76638653
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3089655281
Short name T251
Test name
Test status
Simulation time 29715000 ps
CPU time 1.26 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 219304 kb
Host smart-a5b9964f-ff73-4ad9-8ba8-41af0a1605ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089655281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3089655281
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.332430569
Short name T448
Test name
Test status
Simulation time 32700226 ps
CPU time 1.05 seconds
Started Jul 31 05:50:08 PM PDT 24
Finished Jul 31 05:50:09 PM PDT 24
Peak memory 217352 kb
Host smart-a154d5cd-22c1-4aa9-9a15-be64f5f926b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332430569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.332430569
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.1442135529
Short name T357
Test name
Test status
Simulation time 63926211 ps
CPU time 1.11 seconds
Started Jul 31 05:50:13 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 218512 kb
Host smart-80efc951-5a97-465e-b330-0676d61f2e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442135529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1442135529
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/114.edn_alert.1543793408
Short name T659
Test name
Test status
Simulation time 66829439 ps
CPU time 1.23 seconds
Started Jul 31 05:50:05 PM PDT 24
Finished Jul 31 05:50:07 PM PDT 24
Peak memory 218820 kb
Host smart-58d97736-079f-41df-bd39-7fdfdabe693b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543793408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.1543793408
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.4199919511
Short name T938
Test name
Test status
Simulation time 83872767 ps
CPU time 1.43 seconds
Started Jul 31 05:50:07 PM PDT 24
Finished Jul 31 05:50:08 PM PDT 24
Peak memory 218960 kb
Host smart-1f80b28a-d9be-4df9-9247-b55545cf7005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199919511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.4199919511
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.188522871
Short name T218
Test name
Test status
Simulation time 40257874 ps
CPU time 1.16 seconds
Started Jul 31 05:50:07 PM PDT 24
Finished Jul 31 05:50:08 PM PDT 24
Peak memory 219712 kb
Host smart-b70afd19-dc86-44a9-8866-f40300d75231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188522871 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.188522871
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/116.edn_alert.4134128620
Short name T817
Test name
Test status
Simulation time 84735514 ps
CPU time 1.2 seconds
Started Jul 31 05:50:07 PM PDT 24
Finished Jul 31 05:50:08 PM PDT 24
Peak memory 218564 kb
Host smart-b544333d-79f3-478c-b470-c55f52b83d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134128620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.4134128620
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.1231049472
Short name T56
Test name
Test status
Simulation time 56602096 ps
CPU time 1.94 seconds
Started Jul 31 05:50:04 PM PDT 24
Finished Jul 31 05:50:06 PM PDT 24
Peak memory 217248 kb
Host smart-d9688955-2a3d-4020-a1af-87079fbf2a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231049472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1231049472
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.3207185419
Short name T533
Test name
Test status
Simulation time 47671153 ps
CPU time 1.18 seconds
Started Jul 31 05:50:13 PM PDT 24
Finished Jul 31 05:50:15 PM PDT 24
Peak memory 220624 kb
Host smart-27ce5102-1585-454b-8e7b-2c7920899f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207185419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.3207185419
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.877789473
Short name T318
Test name
Test status
Simulation time 44336575 ps
CPU time 1.27 seconds
Started Jul 31 05:50:04 PM PDT 24
Finished Jul 31 05:50:06 PM PDT 24
Peak memory 218532 kb
Host smart-ec4904b3-b3b2-40ba-9089-2bc932f5ea1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877789473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.877789473
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2285718365
Short name T850
Test name
Test status
Simulation time 129091325 ps
CPU time 2.17 seconds
Started Jul 31 05:50:11 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 218564 kb
Host smart-1be8dfc3-99b8-49a3-a0df-9d5cd0427c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285718365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2285718365
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.2472307303
Short name T166
Test name
Test status
Simulation time 53132344 ps
CPU time 1.2 seconds
Started Jul 31 05:50:09 PM PDT 24
Finished Jul 31 05:50:10 PM PDT 24
Peak memory 218532 kb
Host smart-b91ccd59-e4b3-4b36-b37e-c65fcb6f9c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472307303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.2472307303
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.271298686
Short name T727
Test name
Test status
Simulation time 64846592 ps
CPU time 2.16 seconds
Started Jul 31 05:50:04 PM PDT 24
Finished Jul 31 05:50:07 PM PDT 24
Peak memory 215340 kb
Host smart-65aa6d59-e0f4-4ca4-b724-d1672f6054f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271298686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.271298686
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.4140932885
Short name T435
Test name
Test status
Simulation time 15674813 ps
CPU time 0.92 seconds
Started Jul 31 05:49:06 PM PDT 24
Finished Jul 31 05:49:07 PM PDT 24
Peak memory 206688 kb
Host smart-e7a4a627-15e9-4ec4-8aa5-07c2efd70bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140932885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.4140932885
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3219171030
Short name T195
Test name
Test status
Simulation time 13295938 ps
CPU time 0.91 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 216428 kb
Host smart-900fc86b-668a-4032-b5ae-646768616c85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219171030 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3219171030
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_genbits.2717706939
Short name T967
Test name
Test status
Simulation time 64940672 ps
CPU time 1.04 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:04 PM PDT 24
Peak memory 217328 kb
Host smart-cc87c658-7fcf-4124-ad0d-bb710b7c364c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717706939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2717706939
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.680198898
Short name T838
Test name
Test status
Simulation time 40478308 ps
CPU time 0.89 seconds
Started Jul 31 05:48:59 PM PDT 24
Finished Jul 31 05:49:00 PM PDT 24
Peak memory 215232 kb
Host smart-62d33378-c2cd-4913-822d-94d67a6da916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680198898 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.680198898
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1707463879
Short name T472
Test name
Test status
Simulation time 141459713 ps
CPU time 2.31 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 217180 kb
Host smart-ab46c259-c675-42cf-8cff-5de8c1ddcf21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707463879 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1707463879
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/120.edn_alert.1301168258
Short name T966
Test name
Test status
Simulation time 29342584 ps
CPU time 1.24 seconds
Started Jul 31 05:50:09 PM PDT 24
Finished Jul 31 05:50:11 PM PDT 24
Peak memory 219780 kb
Host smart-06b82f7c-947d-4a0d-8fd5-629beddf0f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301168258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1301168258
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.3169842031
Short name T484
Test name
Test status
Simulation time 67031115 ps
CPU time 2.17 seconds
Started Jul 31 05:50:08 PM PDT 24
Finished Jul 31 05:50:11 PM PDT 24
Peak memory 220240 kb
Host smart-7501ca5f-f76f-4423-b8ab-46b4a86ff209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169842031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3169842031
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.4217251475
Short name T109
Test name
Test status
Simulation time 63828616 ps
CPU time 1.05 seconds
Started Jul 31 05:50:09 PM PDT 24
Finished Jul 31 05:50:11 PM PDT 24
Peak memory 219500 kb
Host smart-76561d13-6b4e-488f-9cb2-765f1aa0fac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217251475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.4217251475
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.1938985186
Short name T554
Test name
Test status
Simulation time 46518418 ps
CPU time 1.19 seconds
Started Jul 31 05:50:11 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 217076 kb
Host smart-b27746fd-1f61-4a0b-b1a7-aa4026fa9a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938985186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1938985186
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.1075121703
Short name T745
Test name
Test status
Simulation time 137577177 ps
CPU time 2.11 seconds
Started Jul 31 05:50:02 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 219944 kb
Host smart-90d4e8a7-1fd1-475e-99ae-67286aa46ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075121703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1075121703
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2656991664
Short name T934
Test name
Test status
Simulation time 381185448 ps
CPU time 1.35 seconds
Started Jul 31 05:50:17 PM PDT 24
Finished Jul 31 05:50:18 PM PDT 24
Peak memory 218564 kb
Host smart-bc9b966c-3c02-457d-9e09-4f9737c8e7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656991664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2656991664
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.2563748560
Short name T851
Test name
Test status
Simulation time 38220264 ps
CPU time 1.47 seconds
Started Jul 31 05:50:12 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 215232 kb
Host smart-1bafba7d-e040-4700-a2ef-94f4a81b4755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563748560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2563748560
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.453391671
Short name T826
Test name
Test status
Simulation time 56159645 ps
CPU time 1.35 seconds
Started Jul 31 05:50:34 PM PDT 24
Finished Jul 31 05:50:35 PM PDT 24
Peak memory 219924 kb
Host smart-b0231fad-385c-43c3-b10a-abea887d136e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453391671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.453391671
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.1861910374
Short name T583
Test name
Test status
Simulation time 85488279 ps
CPU time 1.83 seconds
Started Jul 31 05:50:12 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 219704 kb
Host smart-840c8ca9-004b-422c-8c2a-f094a6632ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861910374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1861910374
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.3245483492
Short name T547
Test name
Test status
Simulation time 45628510 ps
CPU time 1.21 seconds
Started Jul 31 05:50:10 PM PDT 24
Finished Jul 31 05:50:11 PM PDT 24
Peak memory 220064 kb
Host smart-551791b2-dd51-48cf-8e04-ce6abffedba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245483492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3245483492
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.3584071255
Short name T392
Test name
Test status
Simulation time 55405165 ps
CPU time 1.35 seconds
Started Jul 31 05:50:11 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 218520 kb
Host smart-49a73535-dfab-4930-b870-9d17e92d293b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584071255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3584071255
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.1961439591
Short name T532
Test name
Test status
Simulation time 56793891 ps
CPU time 1.26 seconds
Started Jul 31 05:50:12 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 219196 kb
Host smart-37da4bff-0e03-46de-a04c-4591eb796b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961439591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.1961439591
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.610659765
Short name T592
Test name
Test status
Simulation time 103066824 ps
CPU time 2.22 seconds
Started Jul 31 05:50:15 PM PDT 24
Finished Jul 31 05:50:17 PM PDT 24
Peak memory 217584 kb
Host smart-8ccfa098-0d06-4c3f-bb45-f57f9ab0a83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610659765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.610659765
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.1841937792
Short name T196
Test name
Test status
Simulation time 25644706 ps
CPU time 1.16 seconds
Started Jul 31 05:50:14 PM PDT 24
Finished Jul 31 05:50:15 PM PDT 24
Peak memory 218508 kb
Host smart-2d4d4453-f63b-4453-b942-257f828c3414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841937792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.1841937792
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/129.edn_alert.171482891
Short name T929
Test name
Test status
Simulation time 131256630 ps
CPU time 1.21 seconds
Started Jul 31 05:50:17 PM PDT 24
Finished Jul 31 05:50:18 PM PDT 24
Peak memory 220124 kb
Host smart-1f375ebe-bf4d-4169-b629-646708981d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171482891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.171482891
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.904962486
Short name T370
Test name
Test status
Simulation time 32327937 ps
CPU time 1.03 seconds
Started Jul 31 05:50:09 PM PDT 24
Finished Jul 31 05:50:10 PM PDT 24
Peak memory 217208 kb
Host smart-772a46b2-5c1f-459d-9814-5325eab2f77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904962486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.904962486
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3915489360
Short name T804
Test name
Test status
Simulation time 25788026 ps
CPU time 1.17 seconds
Started Jul 31 05:48:56 PM PDT 24
Finished Jul 31 05:48:57 PM PDT 24
Peak memory 219824 kb
Host smart-b2f3380e-18fb-4f60-a777-cb3b024e5621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915489360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3915489360
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.744128940
Short name T920
Test name
Test status
Simulation time 12399794 ps
CPU time 0.9 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:04 PM PDT 24
Peak memory 206676 kb
Host smart-200696c9-cac9-4bb3-a478-26bff718fdcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744128940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.744128940
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2281084584
Short name T959
Test name
Test status
Simulation time 73413945 ps
CPU time 0.96 seconds
Started Jul 31 05:49:06 PM PDT 24
Finished Jul 31 05:49:07 PM PDT 24
Peak memory 216908 kb
Host smart-2f1ddf41-7a66-4910-a356-aee12be9ce08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281084584 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2281084584
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.197393205
Short name T892
Test name
Test status
Simulation time 25877612 ps
CPU time 1 seconds
Started Jul 31 05:49:04 PM PDT 24
Finished Jul 31 05:49:05 PM PDT 24
Peak memory 223840 kb
Host smart-e0974052-4de9-487f-bca2-089035189597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197393205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.197393205
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.298798315
Short name T769
Test name
Test status
Simulation time 37358659 ps
CPU time 1.67 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:05 PM PDT 24
Peak memory 218768 kb
Host smart-d6a8847e-ae28-490b-82d4-5f02addfa1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298798315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.298798315
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2933365445
Short name T84
Test name
Test status
Simulation time 26720161 ps
CPU time 1.05 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 215888 kb
Host smart-dd234b0d-ddf3-400f-8994-7cf185fa4fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933365445 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2933365445
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.51124713
Short name T730
Test name
Test status
Simulation time 46205015 ps
CPU time 0.95 seconds
Started Jul 31 05:49:06 PM PDT 24
Finished Jul 31 05:49:08 PM PDT 24
Peak memory 207096 kb
Host smart-ffeed764-8a37-45ce-b3b3-1abde159bb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51124713 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.51124713
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3501611623
Short name T872
Test name
Test status
Simulation time 52291917399 ps
CPU time 1259 seconds
Started Jul 31 05:49:11 PM PDT 24
Finished Jul 31 06:10:10 PM PDT 24
Peak memory 222292 kb
Host smart-91f9e9ea-911d-4212-ac8d-56d1d9261912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501611623 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3501611623
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2935891840
Short name T322
Test name
Test status
Simulation time 23936083 ps
CPU time 1.21 seconds
Started Jul 31 05:50:11 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 218760 kb
Host smart-e8efeacd-cbbe-4bb1-8e57-af05d08095fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935891840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2935891840
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2163686827
Short name T744
Test name
Test status
Simulation time 72159560 ps
CPU time 1.61 seconds
Started Jul 31 05:50:16 PM PDT 24
Finished Jul 31 05:50:17 PM PDT 24
Peak memory 218792 kb
Host smart-ee9071a8-0730-43e2-8774-2d4e374dd4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163686827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2163686827
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.815127288
Short name T176
Test name
Test status
Simulation time 28361510 ps
CPU time 1.32 seconds
Started Jul 31 05:50:12 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 218724 kb
Host smart-72cc4293-4eba-44f9-a3b0-7e4daf128723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815127288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.815127288
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.2779149871
Short name T798
Test name
Test status
Simulation time 33888900 ps
CPU time 1.27 seconds
Started Jul 31 05:50:09 PM PDT 24
Finished Jul 31 05:50:10 PM PDT 24
Peak memory 215220 kb
Host smart-3d6bedf5-665e-44ba-9874-239bdea989ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779149871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2779149871
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.604021985
Short name T679
Test name
Test status
Simulation time 36268306 ps
CPU time 1.17 seconds
Started Jul 31 05:50:10 PM PDT 24
Finished Jul 31 05:50:11 PM PDT 24
Peak memory 219508 kb
Host smart-0886ce12-bf5c-4d19-b267-6b11575a846f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604021985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.604021985
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/133.edn_alert.2206581553
Short name T637
Test name
Test status
Simulation time 25186567 ps
CPU time 1.19 seconds
Started Jul 31 05:50:35 PM PDT 24
Finished Jul 31 05:50:37 PM PDT 24
Peak memory 218640 kb
Host smart-f3d5f489-b721-4c03-ad6e-c069b3c3c048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206581553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2206581553
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.1600387426
Short name T568
Test name
Test status
Simulation time 34129382 ps
CPU time 1.34 seconds
Started Jul 31 05:50:27 PM PDT 24
Finished Jul 31 05:50:29 PM PDT 24
Peak memory 218680 kb
Host smart-6cfe40a7-4b9e-479d-9892-310399dbf6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600387426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1600387426
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.2210248720
Short name T282
Test name
Test status
Simulation time 65005193 ps
CPU time 1.15 seconds
Started Jul 31 05:50:14 PM PDT 24
Finished Jul 31 05:50:16 PM PDT 24
Peak memory 219596 kb
Host smart-2427b6b4-1e9e-4763-92f5-46426ea64a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210248720 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2210248720
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3241321595
Short name T358
Test name
Test status
Simulation time 69505221 ps
CPU time 1.45 seconds
Started Jul 31 05:50:33 PM PDT 24
Finished Jul 31 05:50:34 PM PDT 24
Peak memory 219248 kb
Host smart-d9c76fe3-54bc-47d1-a8bb-e1d1379f4578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241321595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3241321595
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.476099858
Short name T795
Test name
Test status
Simulation time 136056633 ps
CPU time 1.24 seconds
Started Jul 31 05:50:13 PM PDT 24
Finished Jul 31 05:50:15 PM PDT 24
Peak memory 219688 kb
Host smart-f9e71713-b30c-42ed-a63a-135f3c1d800a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476099858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.476099858
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.1707332785
Short name T57
Test name
Test status
Simulation time 70302486 ps
CPU time 1.11 seconds
Started Jul 31 05:50:22 PM PDT 24
Finished Jul 31 05:50:23 PM PDT 24
Peak memory 217248 kb
Host smart-c2c3989a-9395-4a4d-8e8a-99d9a48d3eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707332785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1707332785
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.144822663
Short name T323
Test name
Test status
Simulation time 198904317 ps
CPU time 1.22 seconds
Started Jul 31 05:50:29 PM PDT 24
Finished Jul 31 05:50:31 PM PDT 24
Peak memory 218576 kb
Host smart-2a53147c-13a6-4f2e-9545-ac3993c1400e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144822663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.144822663
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.1617963615
Short name T224
Test name
Test status
Simulation time 29990184 ps
CPU time 1.22 seconds
Started Jul 31 05:50:17 PM PDT 24
Finished Jul 31 05:50:18 PM PDT 24
Peak memory 219828 kb
Host smart-45f822e1-969f-453b-a849-d6cb1b8aaf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617963615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1617963615
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.332852628
Short name T75
Test name
Test status
Simulation time 215422094 ps
CPU time 2.86 seconds
Started Jul 31 05:50:18 PM PDT 24
Finished Jul 31 05:50:21 PM PDT 24
Peak memory 219284 kb
Host smart-662712af-55be-46cf-9b73-cf9b710e6c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332852628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.332852628
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.1200438525
Short name T108
Test name
Test status
Simulation time 139363360 ps
CPU time 1.09 seconds
Started Jul 31 05:50:20 PM PDT 24
Finished Jul 31 05:50:21 PM PDT 24
Peak memory 219552 kb
Host smart-52135bae-d057-4bff-ba41-6f87c0265032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200438525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.1200438525
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.3196044682
Short name T76
Test name
Test status
Simulation time 83898412 ps
CPU time 2.07 seconds
Started Jul 31 05:50:16 PM PDT 24
Finished Jul 31 05:50:18 PM PDT 24
Peak memory 219708 kb
Host smart-af253bdd-8e2a-4207-95cb-ef0ecf2778b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196044682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3196044682
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.554011559
Short name T222
Test name
Test status
Simulation time 312713980 ps
CPU time 1.42 seconds
Started Jul 31 05:50:16 PM PDT 24
Finished Jul 31 05:50:18 PM PDT 24
Peak memory 219848 kb
Host smart-3c78b3f0-5193-4f73-995c-40a78675547c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554011559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.554011559
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert.3976671360
Short name T961
Test name
Test status
Simulation time 45391423 ps
CPU time 1.1 seconds
Started Jul 31 05:48:59 PM PDT 24
Finished Jul 31 05:49:01 PM PDT 24
Peak memory 220716 kb
Host smart-510d426f-378d-4862-a1fd-336625ff6752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976671360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3976671360
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.4062443964
Short name T764
Test name
Test status
Simulation time 49631029 ps
CPU time 1.01 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 206668 kb
Host smart-ef145a2b-689d-47be-a9e3-29c6c575873c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062443964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.4062443964
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.81842585
Short name T117
Test name
Test status
Simulation time 66980248 ps
CPU time 1.2 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 216776 kb
Host smart-feabe5c2-b79a-42a3-b842-4c692d8a9abf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81842585 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_dis
able_auto_req_mode.81842585
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_genbits.3121291075
Short name T551
Test name
Test status
Simulation time 58086204 ps
CPU time 1.35 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 218616 kb
Host smart-92a78a3f-5242-4a88-bec7-51541f9219e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121291075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3121291075
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2250126383
Short name T672
Test name
Test status
Simulation time 28507693 ps
CPU time 1.04 seconds
Started Jul 31 05:49:05 PM PDT 24
Finished Jul 31 05:49:07 PM PDT 24
Peak memory 223860 kb
Host smart-b53fb8d9-eada-46ab-911b-c4b38b892565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250126383 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2250126383
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3256326156
Short name T404
Test name
Test status
Simulation time 26749365 ps
CPU time 0.93 seconds
Started Jul 31 05:49:12 PM PDT 24
Finished Jul 31 05:49:13 PM PDT 24
Peak memory 215320 kb
Host smart-31889c6d-0da2-4820-9e7a-08ef290a28fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256326156 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3256326156
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3548107857
Short name T303
Test name
Test status
Simulation time 295531359 ps
CPU time 3.19 seconds
Started Jul 31 05:49:04 PM PDT 24
Finished Jul 31 05:49:07 PM PDT 24
Peak memory 215372 kb
Host smart-8ed4a449-7726-4504-ad55-6075dd32bd0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548107857 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3548107857
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1236421018
Short name T787
Test name
Test status
Simulation time 189361831554 ps
CPU time 1030.26 seconds
Started Jul 31 05:48:53 PM PDT 24
Finished Jul 31 06:06:04 PM PDT 24
Peak memory 220972 kb
Host smart-38a89a35-c5c9-435d-8c68-869115b2d42f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236421018 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1236421018
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.2424805442
Short name T681
Test name
Test status
Simulation time 34099074 ps
CPU time 1.22 seconds
Started Jul 31 05:50:30 PM PDT 24
Finished Jul 31 05:50:31 PM PDT 24
Peak memory 219584 kb
Host smart-85f77a51-f907-4354-9b6f-83dfb04f0673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424805442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.2424805442
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.2058993652
Short name T655
Test name
Test status
Simulation time 69685713 ps
CPU time 2.05 seconds
Started Jul 31 05:50:22 PM PDT 24
Finished Jul 31 05:50:25 PM PDT 24
Peak memory 218752 kb
Host smart-4d3b8067-79cc-44ae-9448-4bd961da3f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058993652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2058993652
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2201511724
Short name T92
Test name
Test status
Simulation time 62629786 ps
CPU time 1.02 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:48 PM PDT 24
Peak memory 219840 kb
Host smart-a8655b6c-e0a3-4c8c-ba38-4d979acf5dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201511724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2201511724
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.3513945336
Short name T580
Test name
Test status
Simulation time 51862403 ps
CPU time 1.2 seconds
Started Jul 31 05:50:22 PM PDT 24
Finished Jul 31 05:50:24 PM PDT 24
Peak memory 215252 kb
Host smart-ef2fc4fe-cb34-4973-a88a-621520d842ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513945336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3513945336
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.326006703
Short name T255
Test name
Test status
Simulation time 32862098 ps
CPU time 1.38 seconds
Started Jul 31 05:50:14 PM PDT 24
Finished Jul 31 05:50:16 PM PDT 24
Peak memory 221708 kb
Host smart-58e7eaa9-c96f-4c7f-9ff1-19eef2d27451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326006703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.326006703
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.2673872407
Short name T531
Test name
Test status
Simulation time 27632423 ps
CPU time 1.2 seconds
Started Jul 31 05:50:28 PM PDT 24
Finished Jul 31 05:50:29 PM PDT 24
Peak memory 220020 kb
Host smart-a338bb80-7c01-4c36-b4dd-38c5afbe9e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673872407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2673872407
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.623882928
Short name T694
Test name
Test status
Simulation time 95266526 ps
CPU time 1.34 seconds
Started Jul 31 05:50:27 PM PDT 24
Finished Jul 31 05:50:28 PM PDT 24
Peak memory 218932 kb
Host smart-3292262c-b563-4b1d-b397-dc0d7406cc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623882928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.623882928
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.2476201368
Short name T812
Test name
Test status
Simulation time 41670720 ps
CPU time 1.12 seconds
Started Jul 31 05:50:23 PM PDT 24
Finished Jul 31 05:50:24 PM PDT 24
Peak memory 218536 kb
Host smart-e017cdd2-a101-489a-8f63-600a895774a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476201368 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.2476201368
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.2648115160
Short name T739
Test name
Test status
Simulation time 49826175 ps
CPU time 1.27 seconds
Started Jul 31 05:50:29 PM PDT 24
Finished Jul 31 05:50:30 PM PDT 24
Peak memory 217352 kb
Host smart-c88010bb-59be-4a43-ac19-682591a3fdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648115160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2648115160
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2998386289
Short name T221
Test name
Test status
Simulation time 89921361 ps
CPU time 1.19 seconds
Started Jul 31 05:50:17 PM PDT 24
Finished Jul 31 05:50:18 PM PDT 24
Peak memory 215684 kb
Host smart-3e9943d9-14c7-48db-8b2c-0b1f11f569ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998386289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2998386289
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.855609943
Short name T374
Test name
Test status
Simulation time 65198310 ps
CPU time 1.16 seconds
Started Jul 31 05:50:23 PM PDT 24
Finished Jul 31 05:50:24 PM PDT 24
Peak memory 218836 kb
Host smart-ea0d8689-5678-402a-b59e-4c6102874f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855609943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.855609943
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.652094554
Short name T113
Test name
Test status
Simulation time 23291416 ps
CPU time 1.22 seconds
Started Jul 31 05:50:16 PM PDT 24
Finished Jul 31 05:50:18 PM PDT 24
Peak memory 219776 kb
Host smart-533e2edf-0fdb-4161-80c1-c68620077379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652094554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.652094554
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.388650211
Short name T19
Test name
Test status
Simulation time 44465156 ps
CPU time 1.31 seconds
Started Jul 31 05:50:22 PM PDT 24
Finished Jul 31 05:50:23 PM PDT 24
Peak memory 219752 kb
Host smart-bdfb335a-48c9-4982-bd76-d50c8aed02db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388650211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.388650211
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.83711186
Short name T157
Test name
Test status
Simulation time 33675982 ps
CPU time 1.19 seconds
Started Jul 31 05:50:32 PM PDT 24
Finished Jul 31 05:50:34 PM PDT 24
Peak memory 219652 kb
Host smart-625f72c3-89df-4f5a-8338-8551b5aca60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83711186 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.83711186
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/148.edn_alert.65046943
Short name T156
Test name
Test status
Simulation time 98065914 ps
CPU time 1.23 seconds
Started Jul 31 05:50:42 PM PDT 24
Finished Jul 31 05:50:43 PM PDT 24
Peak memory 218512 kb
Host smart-bc8b4fcb-2892-4c63-90bc-ea1d62a7c8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65046943 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.65046943
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.2472058830
Short name T542
Test name
Test status
Simulation time 90531624 ps
CPU time 1.16 seconds
Started Jul 31 05:50:36 PM PDT 24
Finished Jul 31 05:50:38 PM PDT 24
Peak memory 217372 kb
Host smart-5e0ddda8-2861-4ae8-bab5-59f9600c0b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472058830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2472058830
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3422529129
Short name T110
Test name
Test status
Simulation time 24373865 ps
CPU time 1.14 seconds
Started Jul 31 05:50:41 PM PDT 24
Finished Jul 31 05:50:42 PM PDT 24
Peak memory 218780 kb
Host smart-6891093b-23a5-4597-bf46-75adc438684d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422529129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3422529129
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.3871075025
Short name T450
Test name
Test status
Simulation time 42034417 ps
CPU time 1.46 seconds
Started Jul 31 05:50:52 PM PDT 24
Finished Jul 31 05:50:54 PM PDT 24
Peak memory 218580 kb
Host smart-bbf12235-fe0c-4d79-8db2-40ba1e4e58e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871075025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3871075025
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.2896681911
Short name T58
Test name
Test status
Simulation time 50277709 ps
CPU time 0.84 seconds
Started Jul 31 05:49:04 PM PDT 24
Finished Jul 31 05:49:05 PM PDT 24
Peak memory 214660 kb
Host smart-4f711aa1-4e13-4de7-84e9-d495648e1fda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896681911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2896681911
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2756783373
Short name T137
Test name
Test status
Simulation time 19722884 ps
CPU time 0.85 seconds
Started Jul 31 05:48:59 PM PDT 24
Finished Jul 31 05:49:04 PM PDT 24
Peak memory 216268 kb
Host smart-89b6a735-d068-4b71-b332-fd733aba2db9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756783373 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2756783373
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3253197033
Short name T139
Test name
Test status
Simulation time 42517843 ps
CPU time 1.08 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:08 PM PDT 24
Peak memory 216956 kb
Host smart-e0d3a37c-57d4-4262-be65-95a006e8c182
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253197033 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3253197033
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.387524291
Short name T418
Test name
Test status
Simulation time 81797541 ps
CPU time 0.83 seconds
Started Jul 31 05:49:01 PM PDT 24
Finished Jul 31 05:49:03 PM PDT 24
Peak memory 218132 kb
Host smart-7f3fcb31-c0c3-4304-a5f9-f504e9087fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387524291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.387524291
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1159867351
Short name T664
Test name
Test status
Simulation time 29760248 ps
CPU time 1.14 seconds
Started Jul 31 05:49:05 PM PDT 24
Finished Jul 31 05:49:06 PM PDT 24
Peak memory 217472 kb
Host smart-58a470ca-0947-4428-89d8-f3b37df71efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159867351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1159867351
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.4271953807
Short name T387
Test name
Test status
Simulation time 17726054 ps
CPU time 0.99 seconds
Started Jul 31 05:49:06 PM PDT 24
Finished Jul 31 05:49:08 PM PDT 24
Peak memory 215264 kb
Host smart-92af18cd-c753-4c25-a87d-fb7979875062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271953807 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.4271953807
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3317381759
Short name T636
Test name
Test status
Simulation time 84628334 ps
CPU time 2.12 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 217336 kb
Host smart-eae5243b-dc95-47d5-90c2-a9ec82414e05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317381759 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3317381759
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2838542816
Short name T578
Test name
Test status
Simulation time 21433667476 ps
CPU time 488.22 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:57:12 PM PDT 24
Peak memory 217064 kb
Host smart-328c2802-385f-4e7d-96c7-4b73d91aae64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838542816 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2838542816
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.586800942
Short name T897
Test name
Test status
Simulation time 29938241 ps
CPU time 1.28 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:47 PM PDT 24
Peak memory 219824 kb
Host smart-ff103cc5-0034-49b2-80de-7902c764f81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586800942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.586800942
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.2430057501
Short name T379
Test name
Test status
Simulation time 76090082 ps
CPU time 1.16 seconds
Started Jul 31 05:50:33 PM PDT 24
Finished Jul 31 05:50:34 PM PDT 24
Peak memory 217180 kb
Host smart-95e76dc8-a2ba-4333-9945-7005da8e2cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430057501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2430057501
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.4185020919
Short name T68
Test name
Test status
Simulation time 44283257 ps
CPU time 1.2 seconds
Started Jul 31 05:50:40 PM PDT 24
Finished Jul 31 05:50:42 PM PDT 24
Peak memory 219704 kb
Host smart-947cbae8-d623-49f4-a7ad-3cbcfcbc2fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185020919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.4185020919
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.2294720630
Short name T557
Test name
Test status
Simulation time 47633578 ps
CPU time 1.05 seconds
Started Jul 31 05:50:38 PM PDT 24
Finished Jul 31 05:50:40 PM PDT 24
Peak memory 217240 kb
Host smart-5ee6ad6b-42f6-4182-bce5-b7ac665c2fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294720630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2294720630
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.1959393386
Short name T348
Test name
Test status
Simulation time 22678399 ps
CPU time 1.12 seconds
Started Jul 31 05:50:32 PM PDT 24
Finished Jul 31 05:50:33 PM PDT 24
Peak memory 218644 kb
Host smart-c8174662-1b31-4243-8980-e2bad6c667c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959393386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.1959393386
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.2340377947
Short name T905
Test name
Test status
Simulation time 29511410 ps
CPU time 1.28 seconds
Started Jul 31 05:50:31 PM PDT 24
Finished Jul 31 05:50:32 PM PDT 24
Peak memory 217572 kb
Host smart-9dc03f15-008f-4b11-88a3-3a82b7c118c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340377947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2340377947
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2504041827
Short name T883
Test name
Test status
Simulation time 45703807 ps
CPU time 1.21 seconds
Started Jul 31 05:50:30 PM PDT 24
Finished Jul 31 05:50:32 PM PDT 24
Peak memory 218540 kb
Host smart-add9a251-f8a0-4ee8-a43c-44f3da49b391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504041827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2504041827
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.4170852381
Short name T412
Test name
Test status
Simulation time 45455260 ps
CPU time 1.17 seconds
Started Jul 31 05:50:41 PM PDT 24
Finished Jul 31 05:50:43 PM PDT 24
Peak memory 217440 kb
Host smart-d26ad872-8a79-4bcc-9378-a70d7ba0ac92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170852381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.4170852381
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2558076970
Short name T278
Test name
Test status
Simulation time 34387438 ps
CPU time 1.32 seconds
Started Jul 31 05:50:36 PM PDT 24
Finished Jul 31 05:50:38 PM PDT 24
Peak memory 218564 kb
Host smart-162e7603-979f-415d-a204-ac3fd789acff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558076970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2558076970
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.2043321174
Short name T436
Test name
Test status
Simulation time 27438508 ps
CPU time 1.11 seconds
Started Jul 31 05:50:38 PM PDT 24
Finished Jul 31 05:50:39 PM PDT 24
Peak memory 217268 kb
Host smart-292a6910-f5e9-46dc-b5f0-b2bc604b212f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043321174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2043321174
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.3873411032
Short name T183
Test name
Test status
Simulation time 24840915 ps
CPU time 1.25 seconds
Started Jul 31 05:50:33 PM PDT 24
Finished Jul 31 05:50:34 PM PDT 24
Peak memory 218600 kb
Host smart-d880d5f6-f47e-4450-8a1d-a424aeb385dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873411032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3873411032
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3432186394
Short name T873
Test name
Test status
Simulation time 88347785 ps
CPU time 1.58 seconds
Started Jul 31 05:50:37 PM PDT 24
Finished Jul 31 05:50:39 PM PDT 24
Peak memory 218660 kb
Host smart-55402cb3-b5ce-4338-981a-163baa044b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432186394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3432186394
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.3366732529
Short name T647
Test name
Test status
Simulation time 90660633 ps
CPU time 1.3 seconds
Started Jul 31 05:50:40 PM PDT 24
Finished Jul 31 05:50:42 PM PDT 24
Peak memory 218472 kb
Host smart-edd4178b-2ffd-494d-89c8-572e55e9d1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366732529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3366732529
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.1388253099
Short name T248
Test name
Test status
Simulation time 56978027 ps
CPU time 0.99 seconds
Started Jul 31 05:50:43 PM PDT 24
Finished Jul 31 05:50:44 PM PDT 24
Peak memory 217224 kb
Host smart-04c1c273-b459-4ac0-b4e0-beac83160cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388253099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1388253099
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.1162403586
Short name T396
Test name
Test status
Simulation time 74935277 ps
CPU time 1.13 seconds
Started Jul 31 05:50:32 PM PDT 24
Finished Jul 31 05:50:33 PM PDT 24
Peak memory 219292 kb
Host smart-5f7f8366-07a9-49e9-a64c-a0fe0fbf5486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162403586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1162403586
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.4124176250
Short name T688
Test name
Test status
Simulation time 61002411 ps
CPU time 2.14 seconds
Started Jul 31 05:50:31 PM PDT 24
Finished Jul 31 05:50:33 PM PDT 24
Peak memory 218516 kb
Host smart-16d8ac1e-4d52-406d-a61c-f5c89718655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124176250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.4124176250
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.3367567119
Short name T16
Test name
Test status
Simulation time 258893487 ps
CPU time 1.23 seconds
Started Jul 31 05:50:33 PM PDT 24
Finished Jul 31 05:50:34 PM PDT 24
Peak memory 219508 kb
Host smart-e6b31d30-3e1b-480b-84e9-4077ad7e12ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367567119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.3367567119
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.2670731274
Short name T654
Test name
Test status
Simulation time 70501200 ps
CPU time 1.47 seconds
Started Jul 31 05:50:41 PM PDT 24
Finished Jul 31 05:50:43 PM PDT 24
Peak memory 217404 kb
Host smart-dd4698ea-7710-465f-9316-5c533b2ae450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670731274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2670731274
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3051386879
Short name T684
Test name
Test status
Simulation time 67886683 ps
CPU time 1.11 seconds
Started Jul 31 05:49:04 PM PDT 24
Finished Jul 31 05:49:06 PM PDT 24
Peak memory 218452 kb
Host smart-0c2df63a-2aa9-4b60-9970-72e18a68c00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051386879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3051386879
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2119273823
Short name T474
Test name
Test status
Simulation time 15825369 ps
CPU time 0.95 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 206672 kb
Host smart-dcafc5b7-6c08-4536-828c-e6feb87f161f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119273823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2119273823
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.4160074749
Short name T201
Test name
Test status
Simulation time 11620508 ps
CPU time 0.86 seconds
Started Jul 31 05:49:05 PM PDT 24
Finished Jul 31 05:49:06 PM PDT 24
Peak memory 216060 kb
Host smart-2dcc5348-78f3-4af1-b44e-f5d609eb2791
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160074749 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.4160074749
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2583530183
Short name T128
Test name
Test status
Simulation time 65699275 ps
CPU time 1.26 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 216632 kb
Host smart-d15d7aa6-fa59-4c41-ad46-54599c589c6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583530183 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2583530183
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.130484897
Short name T142
Test name
Test status
Simulation time 99476696 ps
CPU time 1.2 seconds
Started Jul 31 05:49:05 PM PDT 24
Finished Jul 31 05:49:07 PM PDT 24
Peak memory 219464 kb
Host smart-34535eeb-c7b3-4888-be60-d3a45840c017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130484897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.130484897
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2912755929
Short name T910
Test name
Test status
Simulation time 59417437 ps
CPU time 1.43 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 218524 kb
Host smart-c7d5b909-b728-41af-bbc7-b9e02c947d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912755929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2912755929
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.295651483
Short name T341
Test name
Test status
Simulation time 25736794 ps
CPU time 0.92 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:08 PM PDT 24
Peak memory 215476 kb
Host smart-3eab2a25-224b-4f0c-8cdf-ce9acc26d655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295651483 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.295651483
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2605753352
Short name T718
Test name
Test status
Simulation time 57948686 ps
CPU time 0.96 seconds
Started Jul 31 05:49:15 PM PDT 24
Finished Jul 31 05:49:16 PM PDT 24
Peak memory 215240 kb
Host smart-6b7108f8-c962-404f-829d-e57921890b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605753352 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2605753352
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2458122952
Short name T861
Test name
Test status
Simulation time 44720118 ps
CPU time 1.41 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:09 PM PDT 24
Peak memory 215316 kb
Host smart-123238bd-d6c9-41ca-87d7-e2f8cedd104a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458122952 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2458122952
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.762403891
Short name T575
Test name
Test status
Simulation time 48441968998 ps
CPU time 340.28 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:54:51 PM PDT 24
Peak memory 218452 kb
Host smart-9f1566f4-561e-463b-9d96-f3e8e1b4c978
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762403891 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.762403891
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3219937923
Short name T594
Test name
Test status
Simulation time 25446815 ps
CPU time 1.17 seconds
Started Jul 31 05:50:31 PM PDT 24
Finished Jul 31 05:50:33 PM PDT 24
Peak memory 220960 kb
Host smart-6c9d9b51-07ad-4b09-8b10-822ebce98ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219937923 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3219937923
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.3475695236
Short name T382
Test name
Test status
Simulation time 96055355 ps
CPU time 1.38 seconds
Started Jul 31 05:50:43 PM PDT 24
Finished Jul 31 05:50:44 PM PDT 24
Peak memory 218908 kb
Host smart-05d10a44-6412-4fce-a774-56aacaeb0a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475695236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3475695236
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1683335554
Short name T405
Test name
Test status
Simulation time 57450111 ps
CPU time 1.61 seconds
Started Jul 31 05:50:32 PM PDT 24
Finished Jul 31 05:50:34 PM PDT 24
Peak memory 218672 kb
Host smart-9c229855-f98c-4586-b9c1-26b47d3e12cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683335554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1683335554
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.1048348812
Short name T211
Test name
Test status
Simulation time 28560968 ps
CPU time 1.22 seconds
Started Jul 31 05:50:35 PM PDT 24
Finished Jul 31 05:50:36 PM PDT 24
Peak memory 219668 kb
Host smart-7f17be84-4d87-4cb2-85b5-bcd5b95ea719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048348812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1048348812
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.162484330
Short name T577
Test name
Test status
Simulation time 60109890 ps
CPU time 1.49 seconds
Started Jul 31 05:50:47 PM PDT 24
Finished Jul 31 05:50:49 PM PDT 24
Peak memory 218584 kb
Host smart-ede7f54a-3931-45f1-9640-3ec723b0ce6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162484330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.162484330
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.3779882444
Short name T530
Test name
Test status
Simulation time 44010165 ps
CPU time 1.16 seconds
Started Jul 31 05:50:34 PM PDT 24
Finished Jul 31 05:50:35 PM PDT 24
Peak memory 221288 kb
Host smart-b0d3fc25-0b63-49a7-ba99-91ec5080f45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779882444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.3779882444
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.3391455710
Short name T611
Test name
Test status
Simulation time 27105481 ps
CPU time 0.98 seconds
Started Jul 31 05:50:32 PM PDT 24
Finished Jul 31 05:50:33 PM PDT 24
Peak memory 217260 kb
Host smart-9866c830-bdd7-4e5e-bc1e-970a037c2ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391455710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3391455710
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.952402886
Short name T816
Test name
Test status
Simulation time 22058110 ps
CPU time 1.27 seconds
Started Jul 31 05:50:45 PM PDT 24
Finished Jul 31 05:50:46 PM PDT 24
Peak memory 219876 kb
Host smart-fb46d8a9-f14f-4e84-af1c-6e4be2ff7171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952402886 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.952402886
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2734333205
Short name T677
Test name
Test status
Simulation time 193146789 ps
CPU time 2.69 seconds
Started Jul 31 05:50:32 PM PDT 24
Finished Jul 31 05:50:35 PM PDT 24
Peak memory 219996 kb
Host smart-0f9ca95c-e51c-49e2-9c7b-d017972840fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734333205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2734333205
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.1177177109
Short name T515
Test name
Test status
Simulation time 37670616 ps
CPU time 1.09 seconds
Started Jul 31 05:50:35 PM PDT 24
Finished Jul 31 05:50:36 PM PDT 24
Peak memory 218460 kb
Host smart-ccf1e530-d233-4ef6-8020-3278b73aa018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177177109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.1177177109
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1878235283
Short name T887
Test name
Test status
Simulation time 87412769 ps
CPU time 1.38 seconds
Started Jul 31 05:50:38 PM PDT 24
Finished Jul 31 05:50:39 PM PDT 24
Peak memory 218956 kb
Host smart-9691000c-b999-492c-a692-8a8759d08917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878235283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1878235283
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.1979546503
Short name T974
Test name
Test status
Simulation time 28163821 ps
CPU time 1.28 seconds
Started Jul 31 05:50:32 PM PDT 24
Finished Jul 31 05:50:33 PM PDT 24
Peak memory 219692 kb
Host smart-975cd999-67bc-427a-acd6-bda37ca4f568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979546503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.1979546503
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.3239089489
Short name T848
Test name
Test status
Simulation time 61224958 ps
CPU time 1.52 seconds
Started Jul 31 05:50:41 PM PDT 24
Finished Jul 31 05:50:42 PM PDT 24
Peak memory 218620 kb
Host smart-3ed2a644-594f-4efb-ab44-9f53e126ceac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239089489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3239089489
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.3886151946
Short name T174
Test name
Test status
Simulation time 73875764 ps
CPU time 1.09 seconds
Started Jul 31 05:50:53 PM PDT 24
Finished Jul 31 05:50:54 PM PDT 24
Peak memory 218500 kb
Host smart-635a1ad2-ff58-465f-b2c6-afb827a9e3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886151946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.3886151946
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/168.edn_alert.1521265201
Short name T292
Test name
Test status
Simulation time 88909284 ps
CPU time 1.19 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:48 PM PDT 24
Peak memory 218628 kb
Host smart-943856ee-039e-4ca1-bd5c-33a0098d55b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521265201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1521265201
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.8574792
Short name T69
Test name
Test status
Simulation time 45824145 ps
CPU time 1.55 seconds
Started Jul 31 05:50:30 PM PDT 24
Finished Jul 31 05:50:32 PM PDT 24
Peak memory 218524 kb
Host smart-8ca215c8-6d95-421e-aaa8-10d47b0dedd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8574792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.8574792
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.4037907900
Short name T906
Test name
Test status
Simulation time 49738201 ps
CPU time 1.24 seconds
Started Jul 31 05:50:33 PM PDT 24
Finished Jul 31 05:50:34 PM PDT 24
Peak memory 220352 kb
Host smart-982b1a07-3a80-4a66-a561-52dac7236085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037907900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.4037907900
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.4212976292
Short name T441
Test name
Test status
Simulation time 49410689 ps
CPU time 1.21 seconds
Started Jul 31 05:50:35 PM PDT 24
Finished Jul 31 05:50:36 PM PDT 24
Peak memory 217148 kb
Host smart-319aa51f-6b4e-4ca3-a91c-a56a9eaf34fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212976292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.4212976292
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.222027377
Short name T630
Test name
Test status
Simulation time 26704171 ps
CPU time 1.3 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 219832 kb
Host smart-ece8e2eb-1393-41d6-90f4-851cde84d948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222027377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.222027377
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.788273698
Short name T584
Test name
Test status
Simulation time 61650600 ps
CPU time 0.89 seconds
Started Jul 31 05:49:19 PM PDT 24
Finished Jul 31 05:49:20 PM PDT 24
Peak memory 206000 kb
Host smart-4069898c-f3af-4f1e-a0dd-0525b3f88dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788273698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.788273698
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.365779653
Short name T692
Test name
Test status
Simulation time 35363556 ps
CPU time 0.87 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 216272 kb
Host smart-2c599643-78cb-453c-acc5-10200e534c86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365779653 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.365779653
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1621424858
Short name T895
Test name
Test status
Simulation time 65958239 ps
CPU time 1.13 seconds
Started Jul 31 05:49:16 PM PDT 24
Finished Jul 31 05:49:17 PM PDT 24
Peak memory 218324 kb
Host smart-cf62e29f-d9d3-4983-bba0-6fadcf11d53a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621424858 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1621424858
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_genbits.3199634014
Short name T809
Test name
Test status
Simulation time 89581601 ps
CPU time 1.03 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 215312 kb
Host smart-ae3a925d-9a86-4b50-bd8b-64cbd3120d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199634014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3199634014
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3052281468
Short name T216
Test name
Test status
Simulation time 22591230 ps
CPU time 1.23 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:04 PM PDT 24
Peak memory 223980 kb
Host smart-888accdd-097d-48bc-b16d-9314653a377b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052281468 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3052281468
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.418187138
Short name T340
Test name
Test status
Simulation time 19350065 ps
CPU time 1.04 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 215352 kb
Host smart-db07b37c-dfb0-45d2-8d1d-9be817de629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418187138 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.418187138
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1277042555
Short name T976
Test name
Test status
Simulation time 644615715 ps
CPU time 5.38 seconds
Started Jul 31 05:49:05 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 217332 kb
Host smart-56e32adf-0427-45b0-9d91-e0ae6713659e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277042555 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1277042555
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2838345811
Short name T60
Test name
Test status
Simulation time 274546292978 ps
CPU time 1687.13 seconds
Started Jul 31 05:49:02 PM PDT 24
Finished Jul 31 06:17:10 PM PDT 24
Peak memory 224492 kb
Host smart-689a9624-88f1-424b-9dc7-77aef4a8f2d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838345811 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2838345811
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1077992789
Short name T220
Test name
Test status
Simulation time 84110683 ps
CPU time 1.22 seconds
Started Jul 31 05:50:32 PM PDT 24
Finished Jul 31 05:50:33 PM PDT 24
Peak memory 219492 kb
Host smart-7bebbf3b-e37a-4485-866f-dc0ccf317fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077992789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1077992789
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1894294290
Short name T105
Test name
Test status
Simulation time 126866655 ps
CPU time 1.19 seconds
Started Jul 31 05:50:33 PM PDT 24
Finished Jul 31 05:50:34 PM PDT 24
Peak memory 219012 kb
Host smart-708372c0-8c35-4781-8430-f5624a4dc7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894294290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1894294290
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.881810914
Short name T332
Test name
Test status
Simulation time 69677186 ps
CPU time 1.08 seconds
Started Jul 31 05:50:43 PM PDT 24
Finished Jul 31 05:50:44 PM PDT 24
Peak memory 220232 kb
Host smart-792543a3-89a0-450b-90e8-5051e6c6ecad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881810914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.881810914
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.1545245610
Short name T413
Test name
Test status
Simulation time 170140365 ps
CPU time 1.81 seconds
Started Jul 31 05:50:38 PM PDT 24
Finished Jul 31 05:50:40 PM PDT 24
Peak memory 219764 kb
Host smart-69612120-dcc9-41b3-a2ae-65627f0dc2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545245610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1545245610
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1682283435
Short name T190
Test name
Test status
Simulation time 42970153 ps
CPU time 1.11 seconds
Started Jul 31 05:50:41 PM PDT 24
Finished Jul 31 05:50:42 PM PDT 24
Peak memory 218920 kb
Host smart-33ab4126-6d6f-4b08-9ebc-b6c8fd418839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682283435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1682283435
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.4233516758
Short name T467
Test name
Test status
Simulation time 35045686 ps
CPU time 1.22 seconds
Started Jul 31 05:50:34 PM PDT 24
Finished Jul 31 05:50:36 PM PDT 24
Peak memory 217224 kb
Host smart-4cbb3429-3306-4dd5-bd72-331265e8827a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233516758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.4233516758
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3941796084
Short name T219
Test name
Test status
Simulation time 26016147 ps
CPU time 1.18 seconds
Started Jul 31 05:50:43 PM PDT 24
Finished Jul 31 05:50:44 PM PDT 24
Peak memory 219704 kb
Host smart-7aff17ac-ff3b-42c8-8e39-c9b593e9e9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941796084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3941796084
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.2526800819
Short name T496
Test name
Test status
Simulation time 80677235 ps
CPU time 1.08 seconds
Started Jul 31 05:50:47 PM PDT 24
Finished Jul 31 05:50:49 PM PDT 24
Peak memory 217224 kb
Host smart-f9adf00e-b277-4e67-956d-f3453b5cd1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526800819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2526800819
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.3611195632
Short name T284
Test name
Test status
Simulation time 32587992 ps
CPU time 1.35 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:47 PM PDT 24
Peak memory 218656 kb
Host smart-6aa72f70-a99a-4403-83b5-850a9a589e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611195632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3611195632
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.840426825
Short name T31
Test name
Test status
Simulation time 45262642 ps
CPU time 1.33 seconds
Started Jul 31 05:50:36 PM PDT 24
Finished Jul 31 05:50:37 PM PDT 24
Peak memory 218712 kb
Host smart-7da0997a-76a2-4858-aa96-6ed2f0af9a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840426825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.840426825
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.4282039830
Short name T825
Test name
Test status
Simulation time 40424909 ps
CPU time 1.49 seconds
Started Jul 31 05:50:44 PM PDT 24
Finished Jul 31 05:50:45 PM PDT 24
Peak memory 215716 kb
Host smart-a9f07ff0-935d-4048-89cf-f0293895e362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282039830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.4282039830
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.27798422
Short name T398
Test name
Test status
Simulation time 66762406 ps
CPU time 1.23 seconds
Started Jul 31 05:50:39 PM PDT 24
Finished Jul 31 05:50:41 PM PDT 24
Peak memory 217356 kb
Host smart-831c6694-06b4-4d9a-bced-f46f547c599f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27798422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.27798422
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1800280218
Short name T763
Test name
Test status
Simulation time 41633868 ps
CPU time 1.12 seconds
Started Jul 31 05:50:53 PM PDT 24
Finished Jul 31 05:50:54 PM PDT 24
Peak memory 218568 kb
Host smart-80156a11-8d9f-4188-a1fc-a1f5f82fef4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800280218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1800280218
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.2164269362
Short name T543
Test name
Test status
Simulation time 212862796 ps
CPU time 1.35 seconds
Started Jul 31 05:50:39 PM PDT 24
Finished Jul 31 05:50:40 PM PDT 24
Peak memory 217360 kb
Host smart-c295d137-caa1-4db4-9c77-fb1b4158ee66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164269362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2164269362
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.3492314991
Short name T426
Test name
Test status
Simulation time 139649629 ps
CPU time 1.1 seconds
Started Jul 31 05:50:31 PM PDT 24
Finished Jul 31 05:50:32 PM PDT 24
Peak memory 218676 kb
Host smart-8e1ef5cc-df05-4bb5-a9a4-7bcef2aaa195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492314991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.3492314991
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.3536761556
Short name T652
Test name
Test status
Simulation time 43419768 ps
CPU time 1.48 seconds
Started Jul 31 05:50:29 PM PDT 24
Finished Jul 31 05:50:30 PM PDT 24
Peak memory 218648 kb
Host smart-5ce1688b-3efa-457b-8e58-3629de09412d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536761556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3536761556
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.3374648889
Short name T416
Test name
Test status
Simulation time 22601150 ps
CPU time 1.15 seconds
Started Jul 31 05:50:42 PM PDT 24
Finished Jul 31 05:50:43 PM PDT 24
Peak memory 218544 kb
Host smart-03f03652-43f1-4e66-a591-fee4a3b95521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374648889 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3374648889
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.2680503434
Short name T806
Test name
Test status
Simulation time 50540601 ps
CPU time 1.55 seconds
Started Jul 31 05:50:40 PM PDT 24
Finished Jul 31 05:50:42 PM PDT 24
Peak memory 219992 kb
Host smart-cd4c4e9a-0faa-47da-9527-231d62c730f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680503434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2680503434
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.958887807
Short name T189
Test name
Test status
Simulation time 41805845 ps
CPU time 1.09 seconds
Started Jul 31 05:50:32 PM PDT 24
Finished Jul 31 05:50:33 PM PDT 24
Peak memory 218672 kb
Host smart-c67eb95d-d7f3-4e1b-b86f-526e6cf23d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958887807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.958887807
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2514689790
Short name T865
Test name
Test status
Simulation time 50688515 ps
CPU time 1.52 seconds
Started Jul 31 05:50:35 PM PDT 24
Finished Jul 31 05:50:37 PM PDT 24
Peak memory 218388 kb
Host smart-a6d7a266-8831-4f5a-8c78-f3fbe52941cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514689790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2514689790
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3635271619
Short name T194
Test name
Test status
Simulation time 75500595 ps
CPU time 1.16 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 218580 kb
Host smart-14124a33-170a-43bf-89a6-a9caf4b1f5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635271619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3635271619
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1428549376
Short name T489
Test name
Test status
Simulation time 48701341 ps
CPU time 0.9 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 05:49:18 PM PDT 24
Peak memory 206692 kb
Host smart-07e24ba1-0ab1-45a6-a510-3cd211ab6752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428549376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1428549376
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.866387751
Short name T981
Test name
Test status
Simulation time 17358093 ps
CPU time 0.85 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 216208 kb
Host smart-d010c9cf-69db-46ec-8ca9-ffc9d14b8c74
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866387751 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.866387751
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.2892821480
Short name T134
Test name
Test status
Simulation time 19404348 ps
CPU time 1.08 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 218696 kb
Host smart-8ed5f946-64b6-4d12-ac65-37cfc4454a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892821480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2892821480
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.4028013791
Short name T955
Test name
Test status
Simulation time 42399104 ps
CPU time 1.15 seconds
Started Jul 31 05:49:15 PM PDT 24
Finished Jul 31 05:49:17 PM PDT 24
Peak memory 217260 kb
Host smart-a61f9df2-5877-4a96-8d96-d77cb1e2bca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028013791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.4028013791
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1026175474
Short name T50
Test name
Test status
Simulation time 40132855 ps
CPU time 0.97 seconds
Started Jul 31 05:49:15 PM PDT 24
Finished Jul 31 05:49:16 PM PDT 24
Peak memory 223832 kb
Host smart-b6a9ce14-befa-4cf6-837c-1c11dddc25f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026175474 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1026175474
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.123076460
Short name T420
Test name
Test status
Simulation time 31900319 ps
CPU time 1.01 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 207060 kb
Host smart-7e3282e7-7be5-4823-8e35-edc2436047c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123076460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.123076460
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1533845499
Short name T820
Test name
Test status
Simulation time 1278545254 ps
CPU time 5.86 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:17 PM PDT 24
Peak memory 217380 kb
Host smart-e9550be1-0eca-4036-b42e-a393244db35b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533845499 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1533845499
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2230792710
Short name T395
Test name
Test status
Simulation time 54599043509 ps
CPU time 701.66 seconds
Started Jul 31 05:49:04 PM PDT 24
Finished Jul 31 06:00:46 PM PDT 24
Peak memory 223736 kb
Host smart-2d3f9d7c-cd93-420c-b127-9e9f6bf61838
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230792710 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2230792710
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.4249225840
Short name T461
Test name
Test status
Simulation time 27447016 ps
CPU time 1.18 seconds
Started Jul 31 05:50:39 PM PDT 24
Finished Jul 31 05:50:40 PM PDT 24
Peak memory 218540 kb
Host smart-3da68a67-24f8-4170-873e-b543bd67fd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249225840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.4249225840
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1723496045
Short name T414
Test name
Test status
Simulation time 41213175 ps
CPU time 1.25 seconds
Started Jul 31 05:50:34 PM PDT 24
Finished Jul 31 05:50:35 PM PDT 24
Peak memory 218828 kb
Host smart-cec0bd90-1122-4170-9c16-649644607013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723496045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1723496045
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.56013339
Short name T843
Test name
Test status
Simulation time 27809952 ps
CPU time 1.25 seconds
Started Jul 31 05:50:37 PM PDT 24
Finished Jul 31 05:50:38 PM PDT 24
Peak memory 218548 kb
Host smart-7e23ca96-8094-4800-9fcf-9de4f2a84644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56013339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.56013339
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.2226216943
Short name T638
Test name
Test status
Simulation time 64794672 ps
CPU time 1.16 seconds
Started Jul 31 05:50:41 PM PDT 24
Finished Jul 31 05:50:43 PM PDT 24
Peak memory 219000 kb
Host smart-05657cf2-9d81-4faf-84e8-1b6eb8782011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226216943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2226216943
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2741491663
Short name T603
Test name
Test status
Simulation time 93760914 ps
CPU time 1.21 seconds
Started Jul 31 05:50:37 PM PDT 24
Finished Jul 31 05:50:39 PM PDT 24
Peak memory 218960 kb
Host smart-6d7137c5-e0f8-4468-ae6e-30fe40451160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741491663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2741491663
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/183.edn_alert.2151428385
Short name T682
Test name
Test status
Simulation time 40237163 ps
CPU time 1.05 seconds
Started Jul 31 05:50:29 PM PDT 24
Finished Jul 31 05:50:30 PM PDT 24
Peak memory 218492 kb
Host smart-f5497fc4-c978-4518-b04b-b0ce210df2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151428385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.2151428385
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.2996238936
Short name T746
Test name
Test status
Simulation time 179176997 ps
CPU time 1.49 seconds
Started Jul 31 05:50:33 PM PDT 24
Finished Jul 31 05:50:34 PM PDT 24
Peak memory 220176 kb
Host smart-f9461e15-9966-48b0-a013-ce90e3a5cbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996238936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2996238936
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.341599024
Short name T525
Test name
Test status
Simulation time 21452582 ps
CPU time 1.1 seconds
Started Jul 31 05:50:43 PM PDT 24
Finished Jul 31 05:50:44 PM PDT 24
Peak memory 218720 kb
Host smart-ee968a4f-a214-4a5e-8449-01a8ef619c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341599024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.341599024
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.1165226776
Short name T301
Test name
Test status
Simulation time 111583640 ps
CPU time 1.29 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:48 PM PDT 24
Peak memory 219696 kb
Host smart-0148332b-b43a-4a94-b9d0-06bbdd602c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165226776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1165226776
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.3815813830
Short name T514
Test name
Test status
Simulation time 75489461 ps
CPU time 1.31 seconds
Started Jul 31 05:50:53 PM PDT 24
Finished Jul 31 05:50:54 PM PDT 24
Peak memory 217348 kb
Host smart-18439f7e-dbd2-44c1-a3b2-24138ff143e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815813830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3815813830
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.3821972207
Short name T869
Test name
Test status
Simulation time 54780922 ps
CPU time 1.14 seconds
Started Jul 31 05:50:50 PM PDT 24
Finished Jul 31 05:50:51 PM PDT 24
Peak memory 220484 kb
Host smart-844a8671-c42c-4a59-8232-33b9e974852b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821972207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3821972207
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.3028418051
Short name T859
Test name
Test status
Simulation time 42423623 ps
CPU time 1.12 seconds
Started Jul 31 05:50:52 PM PDT 24
Finished Jul 31 05:50:53 PM PDT 24
Peak memory 217368 kb
Host smart-1bc8f251-bac0-476b-9ff9-786889d53a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028418051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3028418051
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.2926535534
Short name T327
Test name
Test status
Simulation time 28811927 ps
CPU time 1.23 seconds
Started Jul 31 05:50:51 PM PDT 24
Finished Jul 31 05:50:52 PM PDT 24
Peak memory 218684 kb
Host smart-06a2fa93-9260-4084-9a38-0f1ef69e78d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926535534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.2926535534
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.428377083
Short name T41
Test name
Test status
Simulation time 54179082 ps
CPU time 1.24 seconds
Started Jul 31 05:50:39 PM PDT 24
Finished Jul 31 05:50:40 PM PDT 24
Peak memory 217240 kb
Host smart-fccb7555-4e2f-434d-bc0b-79b1d0610f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428377083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.428377083
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.3000745941
Short name T178
Test name
Test status
Simulation time 52963670 ps
CPU time 1.2 seconds
Started Jul 31 05:50:47 PM PDT 24
Finished Jul 31 05:50:49 PM PDT 24
Peak memory 220864 kb
Host smart-25063f5c-8cdb-4147-ab33-f0e593d66525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000745941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.3000745941
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.2667549474
Short name T956
Test name
Test status
Simulation time 31768757 ps
CPU time 1.24 seconds
Started Jul 31 05:50:58 PM PDT 24
Finished Jul 31 05:50:59 PM PDT 24
Peak memory 217508 kb
Host smart-537af78a-1cb4-4508-86a4-dac6f4770f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667549474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2667549474
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.731965300
Short name T789
Test name
Test status
Simulation time 142342929 ps
CPU time 1.28 seconds
Started Jul 31 05:50:48 PM PDT 24
Finished Jul 31 05:50:49 PM PDT 24
Peak memory 220368 kb
Host smart-2553a349-390d-4df9-b761-c3cf65e8d8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731965300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.731965300
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2014144039
Short name T434
Test name
Test status
Simulation time 92198417 ps
CPU time 1.16 seconds
Started Jul 31 05:50:43 PM PDT 24
Finished Jul 31 05:50:44 PM PDT 24
Peak memory 219772 kb
Host smart-ed66e87b-f680-4166-86d5-6eacec6dd322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014144039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2014144039
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1337183658
Short name T526
Test name
Test status
Simulation time 39532030 ps
CPU time 1.19 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 219808 kb
Host smart-6b2af91c-9cc1-4db2-b77e-f6ba738b2413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337183658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1337183658
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2022709898
Short name T756
Test name
Test status
Simulation time 18436531 ps
CPU time 0.87 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:08 PM PDT 24
Peak memory 215184 kb
Host smart-26604eed-b018-4c01-a2ee-04ed68ca829a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022709898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2022709898
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3536693210
Short name T900
Test name
Test status
Simulation time 31422997 ps
CPU time 0.83 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 215928 kb
Host smart-9d656ea2-2416-4bca-91c1-91325d534d85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536693210 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3536693210
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1589814717
Short name T980
Test name
Test status
Simulation time 31309417 ps
CPU time 1.21 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 218372 kb
Host smart-215b7522-a7e0-4a29-af4d-62203dba53e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589814717 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1589814717
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1566784735
Short name T346
Test name
Test status
Simulation time 25137840 ps
CPU time 1.12 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 220504 kb
Host smart-151dedf6-f8a0-4c6b-80ba-2d4461cc5837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566784735 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1566784735
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1502936014
Short name T566
Test name
Test status
Simulation time 68561260 ps
CPU time 1.66 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 05:49:19 PM PDT 24
Peak memory 218532 kb
Host smart-751fd51f-9ed0-48cb-a8ee-a856f296b259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502936014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1502936014
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3513604295
Short name T846
Test name
Test status
Simulation time 21733805 ps
CPU time 1.07 seconds
Started Jul 31 05:49:15 PM PDT 24
Finished Jul 31 05:49:16 PM PDT 24
Peak memory 215784 kb
Host smart-1733a2db-6ea3-46ae-96ba-73d12c52d8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513604295 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3513604295
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.713031389
Short name T556
Test name
Test status
Simulation time 37351684 ps
CPU time 0.96 seconds
Started Jul 31 05:49:05 PM PDT 24
Finished Jul 31 05:49:06 PM PDT 24
Peak memory 207044 kb
Host smart-80b377e2-98fe-48aa-9fed-082e076e853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713031389 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.713031389
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3487593919
Short name T362
Test name
Test status
Simulation time 452648231 ps
CPU time 2.88 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 215336 kb
Host smart-4a5ce8c8-239c-4219-a33d-2080e399ad24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487593919 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3487593919
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2411123189
Short name T488
Test name
Test status
Simulation time 68476057544 ps
CPU time 533.03 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 05:58:11 PM PDT 24
Peak memory 223700 kb
Host smart-79af3251-91da-42f2-bce7-e7d72a532878
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411123189 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2411123189
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.3551803198
Short name T168
Test name
Test status
Simulation time 35082119 ps
CPU time 1.46 seconds
Started Jul 31 05:50:54 PM PDT 24
Finished Jul 31 05:50:55 PM PDT 24
Peak memory 215680 kb
Host smart-69f25070-240c-4d33-abb9-0a2ec2bd1ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551803198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.3551803198
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.772524967
Short name T749
Test name
Test status
Simulation time 111310343 ps
CPU time 1.04 seconds
Started Jul 31 05:50:56 PM PDT 24
Finished Jul 31 05:50:57 PM PDT 24
Peak memory 215332 kb
Host smart-5e1a5f27-97ab-4d3a-abfa-4590ae824c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772524967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.772524967
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.1987937477
Short name T604
Test name
Test status
Simulation time 28623434 ps
CPU time 1.23 seconds
Started Jul 31 05:50:50 PM PDT 24
Finished Jul 31 05:50:51 PM PDT 24
Peak memory 220132 kb
Host smart-20b9ccae-2840-4dc2-a4c3-73191a1f62c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987937477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.1987937477
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.2776896856
Short name T921
Test name
Test status
Simulation time 40813444 ps
CPU time 1.5 seconds
Started Jul 31 05:50:48 PM PDT 24
Finished Jul 31 05:50:49 PM PDT 24
Peak memory 218644 kb
Host smart-c2616cd9-f6e9-4c1b-812f-d4be176eec8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776896856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2776896856
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3867116791
Short name T184
Test name
Test status
Simulation time 129057298 ps
CPU time 1.27 seconds
Started Jul 31 05:50:50 PM PDT 24
Finished Jul 31 05:50:52 PM PDT 24
Peak memory 218712 kb
Host smart-d0f81120-db93-4d64-a16a-80a4d0259077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867116791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3867116791
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.3585323435
Short name T964
Test name
Test status
Simulation time 98293771 ps
CPU time 1.39 seconds
Started Jul 31 05:50:50 PM PDT 24
Finished Jul 31 05:50:52 PM PDT 24
Peak memory 217424 kb
Host smart-b5999c75-4dde-4231-b46b-ed89a11609b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585323435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3585323435
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.14527404
Short name T942
Test name
Test status
Simulation time 30554199 ps
CPU time 1.38 seconds
Started Jul 31 05:50:49 PM PDT 24
Finished Jul 31 05:50:50 PM PDT 24
Peak memory 219448 kb
Host smart-7483278f-ea87-4541-9d84-d64b970b64bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14527404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.14527404
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/194.edn_alert.1773253927
Short name T811
Test name
Test status
Simulation time 348561645 ps
CPU time 1.04 seconds
Started Jul 31 05:50:44 PM PDT 24
Finished Jul 31 05:50:46 PM PDT 24
Peak memory 218596 kb
Host smart-562e9465-5b47-4aec-8e9a-282edeb6e62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773253927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.1773253927
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.3979350329
Short name T939
Test name
Test status
Simulation time 43643015 ps
CPU time 1.16 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:47 PM PDT 24
Peak memory 217504 kb
Host smart-261ce754-e043-4b4a-91f6-19d8383867f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979350329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3979350329
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.543830545
Short name T623
Test name
Test status
Simulation time 94012634 ps
CPU time 1.32 seconds
Started Jul 31 05:50:34 PM PDT 24
Finished Jul 31 05:50:36 PM PDT 24
Peak memory 219424 kb
Host smart-6ca07ad7-5bf7-4d51-939f-388213994e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543830545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.543830545
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.2646419182
Short name T336
Test name
Test status
Simulation time 129337606 ps
CPU time 3.07 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:50 PM PDT 24
Peak memory 218848 kb
Host smart-70309abc-13ea-426a-939d-c974c8ac6a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646419182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2646419182
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.3180751795
Short name T559
Test name
Test status
Simulation time 50730419 ps
CPU time 1.27 seconds
Started Jul 31 05:50:49 PM PDT 24
Finished Jul 31 05:50:51 PM PDT 24
Peak memory 219068 kb
Host smart-b8ee7f05-fffe-4cbf-b792-4b32e9bf49d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180751795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.3180751795
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.1968274137
Short name T683
Test name
Test status
Simulation time 42750956 ps
CPU time 1.39 seconds
Started Jul 31 05:50:47 PM PDT 24
Finished Jul 31 05:50:49 PM PDT 24
Peak memory 218280 kb
Host smart-2885ab2e-c853-463b-a42a-319f481991e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968274137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1968274137
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.118524205
Short name T714
Test name
Test status
Simulation time 20453428 ps
CPU time 1.12 seconds
Started Jul 31 05:50:58 PM PDT 24
Finished Jul 31 05:50:59 PM PDT 24
Peak memory 219576 kb
Host smart-1eee6588-8156-4cc2-b4f7-958ea20e7776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118524205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.118524205
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.494479699
Short name T37
Test name
Test status
Simulation time 166223720 ps
CPU time 3.26 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:50 PM PDT 24
Peak memory 220332 kb
Host smart-42aca22b-8987-48e3-80ab-6815135347ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494479699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.494479699
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.3848087857
Short name T437
Test name
Test status
Simulation time 43626529 ps
CPU time 1.15 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:47 PM PDT 24
Peak memory 218672 kb
Host smart-eb4d4f3c-867a-48a2-bd44-6c5d95aac5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848087857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.3848087857
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.2553806792
Short name T950
Test name
Test status
Simulation time 58387648 ps
CPU time 1.82 seconds
Started Jul 31 05:51:09 PM PDT 24
Finished Jul 31 05:51:11 PM PDT 24
Peak memory 220280 kb
Host smart-29fa47ea-a4d0-4434-a5a4-d183201d44ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553806792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2553806792
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.3949135350
Short name T223
Test name
Test status
Simulation time 29449387 ps
CPU time 1.23 seconds
Started Jul 31 05:50:58 PM PDT 24
Finished Jul 31 05:51:00 PM PDT 24
Peak memory 219812 kb
Host smart-b895c484-1254-4538-a099-74934920f4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949135350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.3949135350
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.3507135910
Short name T409
Test name
Test status
Simulation time 43598549 ps
CPU time 1.43 seconds
Started Jul 31 05:50:45 PM PDT 24
Finished Jul 31 05:50:47 PM PDT 24
Peak memory 217148 kb
Host smart-a282b28f-7ceb-45d7-990b-ec104ce6bb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507135910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3507135910
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2700506915
Short name T779
Test name
Test status
Simulation time 245060704 ps
CPU time 1.09 seconds
Started Jul 31 05:49:00 PM PDT 24
Finished Jul 31 05:49:01 PM PDT 24
Peak memory 220508 kb
Host smart-49050805-0773-4cf4-bae6-d6e2201e4ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700506915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2700506915
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3012505180
Short name T944
Test name
Test status
Simulation time 31228888 ps
CPU time 0.89 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:04 PM PDT 24
Peak memory 206704 kb
Host smart-0da1b94e-9131-400a-b086-b6f66c7e5d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012505180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3012505180
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1855064997
Short name T150
Test name
Test status
Simulation time 14244989 ps
CPU time 0.89 seconds
Started Jul 31 05:48:53 PM PDT 24
Finished Jul 31 05:48:54 PM PDT 24
Peak memory 216324 kb
Host smart-b7205e78-edf9-415c-a801-5bcc4081ad24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855064997 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1855064997
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1237347644
Short name T132
Test name
Test status
Simulation time 63598830 ps
CPU time 1.08 seconds
Started Jul 31 05:48:58 PM PDT 24
Finished Jul 31 05:48:59 PM PDT 24
Peak memory 216792 kb
Host smart-2ea5cc96-d30a-43cb-abfe-8afc0e15e506
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237347644 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1237347644
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3869676725
Short name T507
Test name
Test status
Simulation time 47197347 ps
CPU time 0.96 seconds
Started Jul 31 05:48:59 PM PDT 24
Finished Jul 31 05:49:01 PM PDT 24
Peak memory 218564 kb
Host smart-5797aabe-d1b6-48f9-89b9-a9f598d215ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869676725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3869676725
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.4085345091
Short name T680
Test name
Test status
Simulation time 155333901 ps
CPU time 3.2 seconds
Started Jul 31 05:48:49 PM PDT 24
Finished Jul 31 05:48:53 PM PDT 24
Peak memory 218560 kb
Host smart-60c3b163-6790-4d79-866a-e275d9b51ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085345091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.4085345091
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2320090211
Short name T958
Test name
Test status
Simulation time 31704193 ps
CPU time 0.9 seconds
Started Jul 31 05:48:54 PM PDT 24
Finished Jul 31 05:48:55 PM PDT 24
Peak memory 215172 kb
Host smart-338b8645-80e1-45e0-97da-b4de3493ab32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320090211 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2320090211
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_smoke.1622924658
Short name T339
Test name
Test status
Simulation time 17736394 ps
CPU time 0.97 seconds
Started Jul 31 05:48:58 PM PDT 24
Finished Jul 31 05:48:59 PM PDT 24
Peak memory 215300 kb
Host smart-1d68dea5-6890-4cbc-ab5c-e5e38b922c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622924658 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1622924658
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.108834791
Short name T911
Test name
Test status
Simulation time 203045491 ps
CPU time 4.35 seconds
Started Jul 31 05:48:45 PM PDT 24
Finished Jul 31 05:48:49 PM PDT 24
Peak memory 218672 kb
Host smart-ea1af6cb-e173-4ce8-93a6-9b55ab7a8d8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108834791 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.108834791
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.541882615
Short name T376
Test name
Test status
Simulation time 80143439817 ps
CPU time 1851.78 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 06:19:59 PM PDT 24
Peak memory 224804 kb
Host smart-e87bce2a-cece-40aa-b2c6-19b14e86d227
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541882615 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.541882615
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.2259678720
Short name T685
Test name
Test status
Simulation time 23946852 ps
CPU time 1.09 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 214864 kb
Host smart-f1f465c1-2901-44c2-bc2d-7954bcc1bd28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259678720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2259678720
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.202173687
Short name T354
Test name
Test status
Simulation time 26082424 ps
CPU time 0.77 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:04 PM PDT 24
Peak memory 215948 kb
Host smart-0d314899-ecc5-4098-9836-7214591d9362
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202173687 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.202173687
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1982426062
Short name T95
Test name
Test status
Simulation time 224264958 ps
CPU time 1.13 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 217068 kb
Host smart-67a53311-6215-4c36-9370-b438f0b100a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982426062 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1982426062
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1188640176
Short name T52
Test name
Test status
Simulation time 19926759 ps
CPU time 1.13 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 223992 kb
Host smart-45cce280-93c9-4eae-9508-400abe587c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188640176 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1188640176
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2669483236
Short name T932
Test name
Test status
Simulation time 75623745 ps
CPU time 1.6 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 218668 kb
Host smart-a486ec83-88d8-40a5-9abd-47ee5ef6e3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669483236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2669483236
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.468025321
Short name T589
Test name
Test status
Simulation time 22502417 ps
CPU time 1.29 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 224048 kb
Host smart-3c0325ef-e8ca-43ab-9566-6672f1f00884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468025321 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.468025321
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.856692909
Short name T805
Test name
Test status
Simulation time 62407900 ps
CPU time 0.93 seconds
Started Jul 31 05:49:11 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 215284 kb
Host smart-e8a4ed6e-4a99-461a-ad20-599bf40ee3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856692909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.856692909
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2625741693
Short name T777
Test name
Test status
Simulation time 579910005 ps
CPU time 3.71 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:07 PM PDT 24
Peak memory 217284 kb
Host smart-681bfde6-9374-4c20-93ff-3045c0e45191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625741693 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2625741693
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2738758898
Short name T924
Test name
Test status
Simulation time 36841894384 ps
CPU time 841.74 seconds
Started Jul 31 05:49:00 PM PDT 24
Finished Jul 31 06:03:07 PM PDT 24
Peak memory 218988 kb
Host smart-58aac73d-d0c3-4f47-8509-18f0a282fe99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738758898 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2738758898
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2362365136
Short name T334
Test name
Test status
Simulation time 202097551 ps
CPU time 2.51 seconds
Started Jul 31 05:50:52 PM PDT 24
Finished Jul 31 05:50:55 PM PDT 24
Peak memory 219800 kb
Host smart-9f0dd885-b255-4bf1-b8af-1a9fe2bf600c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362365136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2362365136
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2906410722
Short name T842
Test name
Test status
Simulation time 99053695 ps
CPU time 1.2 seconds
Started Jul 31 05:50:43 PM PDT 24
Finished Jul 31 05:50:44 PM PDT 24
Peak memory 217428 kb
Host smart-2ac04220-b243-4375-be55-189bf5ff4fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906410722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2906410722
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.85603000
Short name T522
Test name
Test status
Simulation time 44360800 ps
CPU time 1.81 seconds
Started Jul 31 05:50:51 PM PDT 24
Finished Jul 31 05:50:53 PM PDT 24
Peak memory 218856 kb
Host smart-641a68e7-e1a6-40d7-b318-cfb3717c0051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85603000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.85603000
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.299579644
Short name T367
Test name
Test status
Simulation time 46841899 ps
CPU time 1.47 seconds
Started Jul 31 05:50:42 PM PDT 24
Finished Jul 31 05:50:43 PM PDT 24
Peak memory 218464 kb
Host smart-3faa1d65-7c79-4f0c-8e55-216538716d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299579644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.299579644
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.245010758
Short name T829
Test name
Test status
Simulation time 91350203 ps
CPU time 1.02 seconds
Started Jul 31 05:50:47 PM PDT 24
Finished Jul 31 05:50:48 PM PDT 24
Peak memory 217488 kb
Host smart-5bea832c-a048-4eef-b7de-6deb95c1f0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245010758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.245010758
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1657851929
Short name T538
Test name
Test status
Simulation time 61920526 ps
CPU time 1.13 seconds
Started Jul 31 05:51:01 PM PDT 24
Finished Jul 31 05:51:02 PM PDT 24
Peak memory 218736 kb
Host smart-ba515fff-51a5-4275-83d4-54ef06935a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657851929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1657851929
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.537509239
Short name T310
Test name
Test status
Simulation time 65596640 ps
CPU time 1.09 seconds
Started Jul 31 05:50:44 PM PDT 24
Finished Jul 31 05:50:45 PM PDT 24
Peak memory 217432 kb
Host smart-1fd60497-b289-4515-9b28-bcaa94795786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537509239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.537509239
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1025319572
Short name T716
Test name
Test status
Simulation time 42757676 ps
CPU time 1.45 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:48 PM PDT 24
Peak memory 219804 kb
Host smart-cdea0867-a42a-46e4-ad2c-566531e16326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025319572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1025319572
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1347261455
Short name T308
Test name
Test status
Simulation time 135073114 ps
CPU time 1.12 seconds
Started Jul 31 05:50:44 PM PDT 24
Finished Jul 31 05:50:45 PM PDT 24
Peak memory 219916 kb
Host smart-e5ad2336-625b-479b-89eb-9dc47008f367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347261455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1347261455
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1482178629
Short name T599
Test name
Test status
Simulation time 188503546 ps
CPU time 1.73 seconds
Started Jul 31 05:50:45 PM PDT 24
Finished Jul 31 05:50:47 PM PDT 24
Peak memory 218520 kb
Host smart-1fb7acb9-92d0-4fdd-82ce-287faf3ee8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482178629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1482178629
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.4148819378
Short name T250
Test name
Test status
Simulation time 160986703 ps
CPU time 1.22 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 218448 kb
Host smart-2a1461d1-b1f3-4342-8c2e-547f526711cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148819378 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.4148819378
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1259315075
Short name T466
Test name
Test status
Simulation time 20547878 ps
CPU time 0.87 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:04 PM PDT 24
Peak memory 214976 kb
Host smart-92c67782-a105-45f7-9275-fd49603d3a79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259315075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1259315075
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_err.3521511173
Short name T64
Test name
Test status
Simulation time 18682724 ps
CPU time 1.14 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 218660 kb
Host smart-0581ad86-34c3-4ddb-b05e-947e97b4e639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521511173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3521511173
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.23508696
Short name T860
Test name
Test status
Simulation time 43370196 ps
CPU time 1.11 seconds
Started Jul 31 05:49:20 PM PDT 24
Finished Jul 31 05:49:21 PM PDT 24
Peak memory 218764 kb
Host smart-bd7d6aa4-f51f-4602-9a63-fb292e1c5310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23508696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.23508696
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.227382774
Short name T736
Test name
Test status
Simulation time 22751949 ps
CPU time 1.1 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 215512 kb
Host smart-0c3292bf-c25c-4f1a-bd69-1eb7ac971be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227382774 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.227382774
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2588843103
Short name T613
Test name
Test status
Simulation time 19409257 ps
CPU time 0.92 seconds
Started Jul 31 05:49:11 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 207068 kb
Host smart-67d028aa-0270-49c2-a3cb-fe9372a7ec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588843103 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2588843103
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2563897342
Short name T46
Test name
Test status
Simulation time 195270581 ps
CPU time 4.07 seconds
Started Jul 31 05:49:06 PM PDT 24
Finished Jul 31 05:49:15 PM PDT 24
Peak memory 217236 kb
Host smart-bd3de1b9-d40f-4717-8353-c8944e855f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563897342 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2563897342
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2483154543
Short name T388
Test name
Test status
Simulation time 121460302495 ps
CPU time 1581.91 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 06:15:33 PM PDT 24
Peak memory 225740 kb
Host smart-798fd34c-4bd1-4834-af05-3090b3cb03e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483154543 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2483154543
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2468207652
Short name T338
Test name
Test status
Simulation time 24210031 ps
CPU time 1.18 seconds
Started Jul 31 05:50:47 PM PDT 24
Finished Jul 31 05:50:48 PM PDT 24
Peak memory 218536 kb
Host smart-080ac6b3-2cff-4bc2-bec7-3325dd65a854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468207652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2468207652
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.322325493
Short name T351
Test name
Test status
Simulation time 37291480 ps
CPU time 1.26 seconds
Started Jul 31 05:50:49 PM PDT 24
Finished Jul 31 05:50:50 PM PDT 24
Peak memory 217128 kb
Host smart-cb4c476d-6762-4192-9c23-db961ce079e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322325493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.322325493
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1795573057
Short name T949
Test name
Test status
Simulation time 31232674 ps
CPU time 1.2 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:47 PM PDT 24
Peak memory 217472 kb
Host smart-55affa7c-51c5-4dd7-a5be-53546e46f42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795573057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1795573057
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.4117698033
Short name T767
Test name
Test status
Simulation time 64625380 ps
CPU time 1.1 seconds
Started Jul 31 05:50:51 PM PDT 24
Finished Jul 31 05:50:52 PM PDT 24
Peak memory 217468 kb
Host smart-43f439d6-f82b-415e-8331-182dc6b87038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117698033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.4117698033
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3273354301
Short name T650
Test name
Test status
Simulation time 251481262 ps
CPU time 1.51 seconds
Started Jul 31 05:50:55 PM PDT 24
Finished Jul 31 05:50:57 PM PDT 24
Peak memory 218540 kb
Host smart-fed6bb25-aa48-4dfa-bddb-84bfb44b16a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273354301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3273354301
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.925913632
Short name T38
Test name
Test status
Simulation time 104096246 ps
CPU time 1.34 seconds
Started Jul 31 05:50:49 PM PDT 24
Finished Jul 31 05:50:50 PM PDT 24
Peak memory 218824 kb
Host smart-dd793985-40e8-433a-b73b-b5e0277280b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925913632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.925913632
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.3316814378
Short name T971
Test name
Test status
Simulation time 122520527 ps
CPU time 1.69 seconds
Started Jul 31 05:50:51 PM PDT 24
Finished Jul 31 05:50:53 PM PDT 24
Peak memory 220160 kb
Host smart-1d0225b2-6f74-4b86-a231-667a2619f09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316814378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3316814378
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.848870318
Short name T43
Test name
Test status
Simulation time 38888082 ps
CPU time 1.3 seconds
Started Jul 31 05:50:47 PM PDT 24
Finished Jul 31 05:50:49 PM PDT 24
Peak memory 215232 kb
Host smart-ffb363cb-9976-4319-8941-53fba536280d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848870318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.848870318
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.4055395171
Short name T307
Test name
Test status
Simulation time 35661316 ps
CPU time 1.38 seconds
Started Jul 31 05:50:54 PM PDT 24
Finished Jul 31 05:50:56 PM PDT 24
Peak memory 220000 kb
Host smart-5448ecf5-58b2-4a3e-a06c-7c4891e2c533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055395171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.4055395171
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1173697322
Short name T725
Test name
Test status
Simulation time 25543617 ps
CPU time 1.21 seconds
Started Jul 31 05:49:12 PM PDT 24
Finished Jul 31 05:49:13 PM PDT 24
Peak memory 220496 kb
Host smart-e39f31d5-a2ac-49d4-b977-a528a5ba0aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173697322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1173697322
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3077284113
Short name T708
Test name
Test status
Simulation time 26028181 ps
CPU time 0.92 seconds
Started Jul 31 05:49:04 PM PDT 24
Finished Jul 31 05:49:06 PM PDT 24
Peak memory 214840 kb
Host smart-ca94bed9-32b6-453c-9821-063057fc2964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077284113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3077284113
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2013820771
Short name T622
Test name
Test status
Simulation time 12928428 ps
CPU time 0.92 seconds
Started Jul 31 05:49:12 PM PDT 24
Finished Jul 31 05:49:13 PM PDT 24
Peak memory 216328 kb
Host smart-a1d9265a-c7ee-4c4c-91f7-4c3047c4607e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013820771 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2013820771
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1007428701
Short name T162
Test name
Test status
Simulation time 59032458 ps
CPU time 1.12 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 216992 kb
Host smart-c2c99356-ec6b-4ae6-bd33-de86cd9ca98d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007428701 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1007428701
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.660747821
Short name T54
Test name
Test status
Simulation time 38350154 ps
CPU time 1.16 seconds
Started Jul 31 05:49:19 PM PDT 24
Finished Jul 31 05:49:20 PM PDT 24
Peak memory 229720 kb
Host smart-6111b2f8-be9c-45e6-8374-ceb0925c0d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660747821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.660747821
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3608051339
Short name T492
Test name
Test status
Simulation time 87626932 ps
CPU time 1.07 seconds
Started Jul 31 05:49:15 PM PDT 24
Finished Jul 31 05:49:16 PM PDT 24
Peak memory 217316 kb
Host smart-e62e2d34-cc3e-4f16-a83f-6073e084c5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608051339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3608051339
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2369771007
Short name T361
Test name
Test status
Simulation time 21299228 ps
CPU time 1.05 seconds
Started Jul 31 05:49:04 PM PDT 24
Finished Jul 31 05:49:06 PM PDT 24
Peak memory 215524 kb
Host smart-58e7c4cc-f83e-408f-a0c0-a2f18950209e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369771007 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2369771007
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.4168151167
Short name T818
Test name
Test status
Simulation time 28977117 ps
CPU time 1.02 seconds
Started Jul 31 05:49:20 PM PDT 24
Finished Jul 31 05:49:21 PM PDT 24
Peak memory 215268 kb
Host smart-45880f0e-eba8-4b1c-bfaf-b4ee2efcf87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168151167 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.4168151167
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1867054592
Short name T298
Test name
Test status
Simulation time 312881558 ps
CPU time 3.2 seconds
Started Jul 31 05:49:14 PM PDT 24
Finished Jul 31 05:49:23 PM PDT 24
Peak memory 215456 kb
Host smart-139286fb-fadd-4b38-8384-35ae905d55c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867054592 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1867054592
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1887092840
Short name T239
Test name
Test status
Simulation time 45627379093 ps
CPU time 999.2 seconds
Started Jul 31 05:49:06 PM PDT 24
Finished Jul 31 06:05:45 PM PDT 24
Peak memory 218544 kb
Host smart-d03a1638-9c09-4c51-8f9a-a6dcffd36f27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887092840 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1887092840
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.478027030
Short name T582
Test name
Test status
Simulation time 65800290 ps
CPU time 1.25 seconds
Started Jul 31 05:50:51 PM PDT 24
Finished Jul 31 05:50:52 PM PDT 24
Peak memory 218884 kb
Host smart-1848f180-6a5c-42a9-8e54-f48d26f3a008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478027030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.478027030
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.565537258
Short name T423
Test name
Test status
Simulation time 38536267 ps
CPU time 1.48 seconds
Started Jul 31 05:50:51 PM PDT 24
Finished Jul 31 05:50:53 PM PDT 24
Peak memory 217352 kb
Host smart-bd5ca71c-004c-4a27-bcaa-8bccece27b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565537258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.565537258
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.488366529
Short name T691
Test name
Test status
Simulation time 39872128 ps
CPU time 1.63 seconds
Started Jul 31 05:50:48 PM PDT 24
Finished Jul 31 05:50:50 PM PDT 24
Peak memory 218616 kb
Host smart-eb96caff-f5cc-4874-b84e-5734f0ad6d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488366529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.488366529
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.8588245
Short name T602
Test name
Test status
Simulation time 70994997 ps
CPU time 1.62 seconds
Started Jul 31 05:50:48 PM PDT 24
Finished Jul 31 05:50:49 PM PDT 24
Peak memory 218520 kb
Host smart-82dd7979-5192-45b1-bfcd-dd244e489ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8588245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.8588245
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.988462034
Short name T703
Test name
Test status
Simulation time 29519016 ps
CPU time 1.17 seconds
Started Jul 31 05:50:52 PM PDT 24
Finished Jul 31 05:50:53 PM PDT 24
Peak memory 219800 kb
Host smart-bf68650e-2841-4162-94dc-34c00b475911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988462034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.988462034
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3341132166
Short name T72
Test name
Test status
Simulation time 56128994 ps
CPU time 1.29 seconds
Started Jul 31 05:50:52 PM PDT 24
Finished Jul 31 05:50:54 PM PDT 24
Peak memory 218424 kb
Host smart-b565a2b0-4996-4a82-8664-1e53aa1330f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341132166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3341132166
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3051114941
Short name T868
Test name
Test status
Simulation time 63188305 ps
CPU time 0.99 seconds
Started Jul 31 05:50:51 PM PDT 24
Finished Jul 31 05:50:52 PM PDT 24
Peak memory 217192 kb
Host smart-df7360fb-8336-46fe-89e3-cd4881b79811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051114941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3051114941
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3695613698
Short name T644
Test name
Test status
Simulation time 117235463 ps
CPU time 1.1 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:47 PM PDT 24
Peak memory 218584 kb
Host smart-1a90e57d-1154-40b7-a01a-dd76bd50ab5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695613698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3695613698
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3514203378
Short name T430
Test name
Test status
Simulation time 34423456 ps
CPU time 1.27 seconds
Started Jul 31 05:50:52 PM PDT 24
Finished Jul 31 05:50:53 PM PDT 24
Peak memory 217192 kb
Host smart-9e3c20dc-d8ea-451b-aeed-cefe8b65155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514203378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3514203378
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.362950421
Short name T837
Test name
Test status
Simulation time 120067083 ps
CPU time 1.12 seconds
Started Jul 31 05:50:57 PM PDT 24
Finished Jul 31 05:50:58 PM PDT 24
Peak memory 219924 kb
Host smart-20ef6f88-c455-4818-8d4a-c664d9d8ae1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362950421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.362950421
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2614675271
Short name T181
Test name
Test status
Simulation time 77292028 ps
CPU time 1.18 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:09 PM PDT 24
Peak memory 219680 kb
Host smart-7becc881-9ace-4fa4-b07b-1c50535e99ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614675271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2614675271
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1917194316
Short name T501
Test name
Test status
Simulation time 24477193 ps
CPU time 0.95 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 206644 kb
Host smart-9c971eb4-d353-4483-a48f-e431861347d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917194316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1917194316
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2892371569
Short name T657
Test name
Test status
Simulation time 208739024 ps
CPU time 1.24 seconds
Started Jul 31 05:49:20 PM PDT 24
Finished Jul 31 05:49:21 PM PDT 24
Peak memory 216916 kb
Host smart-af172ea4-4eff-496d-818a-123f0aae4180
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892371569 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2892371569
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.981984562
Short name T126
Test name
Test status
Simulation time 23970746 ps
CPU time 1.07 seconds
Started Jul 31 05:49:20 PM PDT 24
Finished Jul 31 05:49:21 PM PDT 24
Peak memory 229560 kb
Host smart-d68e79d9-2527-42fc-a099-d53f866d4089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981984562 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.981984562
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2991516594
Short name T433
Test name
Test status
Simulation time 92875022 ps
CPU time 2.15 seconds
Started Jul 31 05:49:19 PM PDT 24
Finished Jul 31 05:49:21 PM PDT 24
Peak memory 220148 kb
Host smart-7349b8af-44ef-4a23-8f4f-793272e59d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991516594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2991516594
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1703224054
Short name T947
Test name
Test status
Simulation time 22192203 ps
CPU time 1.2 seconds
Started Jul 31 05:49:11 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 215480 kb
Host smart-d38e2e49-6344-4823-84f1-882e1ec5fa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703224054 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1703224054
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3107536394
Short name T399
Test name
Test status
Simulation time 173481600 ps
CPU time 0.87 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 215120 kb
Host smart-d3ce97e1-1692-406e-82af-12a90b379d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107536394 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3107536394
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.854422209
Short name T512
Test name
Test status
Simulation time 139473981 ps
CPU time 1.18 seconds
Started Jul 31 05:49:18 PM PDT 24
Finished Jul 31 05:49:19 PM PDT 24
Peak memory 215336 kb
Host smart-05bfded9-6671-46e6-97f1-c4d0a79808c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854422209 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.854422209
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2915989893
Short name T233
Test name
Test status
Simulation time 54643421880 ps
CPU time 1182.63 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 06:08:53 PM PDT 24
Peak memory 219824 kb
Host smart-82ae4b5e-8289-4845-ad1f-e07049037afc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915989893 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2915989893
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.317915464
Short name T498
Test name
Test status
Simulation time 54362325 ps
CPU time 2.11 seconds
Started Jul 31 05:50:53 PM PDT 24
Finished Jul 31 05:50:55 PM PDT 24
Peak memory 220260 kb
Host smart-ebe0ae45-12b6-439e-818b-65af6ea18b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317915464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.317915464
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2171843623
Short name T20
Test name
Test status
Simulation time 45179476 ps
CPU time 1.46 seconds
Started Jul 31 05:50:47 PM PDT 24
Finished Jul 31 05:50:49 PM PDT 24
Peak memory 220124 kb
Host smart-e9206341-9bb1-4346-9c9d-30d7db88a0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171843623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2171843623
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3620248367
Short name T29
Test name
Test status
Simulation time 40294817 ps
CPU time 1.42 seconds
Started Jul 31 05:50:54 PM PDT 24
Finished Jul 31 05:50:55 PM PDT 24
Peak memory 218600 kb
Host smart-f8ff27eb-4cd0-4443-a887-5429fb9fb197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620248367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3620248367
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3031304933
Short name T701
Test name
Test status
Simulation time 40906492 ps
CPU time 1.18 seconds
Started Jul 31 05:50:53 PM PDT 24
Finished Jul 31 05:50:54 PM PDT 24
Peak memory 218544 kb
Host smart-fbe0cee8-40c5-4807-9145-06d36970e4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031304933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3031304933
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3869171059
Short name T320
Test name
Test status
Simulation time 57583201 ps
CPU time 2.23 seconds
Started Jul 31 05:50:47 PM PDT 24
Finished Jul 31 05:50:49 PM PDT 24
Peak memory 220104 kb
Host smart-0b531d08-c844-44d4-ba5d-481e3704261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869171059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3869171059
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3860892610
Short name T770
Test name
Test status
Simulation time 85552310 ps
CPU time 1.24 seconds
Started Jul 31 05:50:55 PM PDT 24
Finished Jul 31 05:50:57 PM PDT 24
Peak memory 217296 kb
Host smart-7f5d0bbc-2490-4fea-8404-5ed8772df5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860892610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3860892610
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1047842199
Short name T607
Test name
Test status
Simulation time 77597359 ps
CPU time 2.75 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:49 PM PDT 24
Peak memory 218488 kb
Host smart-5c4d3ad4-46a2-4566-8bb6-07ce08c8b49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047842199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1047842199
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3992456198
Short name T852
Test name
Test status
Simulation time 203156294 ps
CPU time 1.12 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:47 PM PDT 24
Peak memory 217200 kb
Host smart-c2a58ac5-ed60-40d3-b454-c1b2028c7832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992456198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3992456198
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.800468491
Short name T296
Test name
Test status
Simulation time 41999066 ps
CPU time 1.48 seconds
Started Jul 31 05:50:52 PM PDT 24
Finished Jul 31 05:50:53 PM PDT 24
Peak memory 218396 kb
Host smart-79c4c0fc-1290-490a-aba4-2de58536ccce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800468491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.800468491
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1361345891
Short name T394
Test name
Test status
Simulation time 51440806 ps
CPU time 1.54 seconds
Started Jul 31 05:50:56 PM PDT 24
Finished Jul 31 05:50:58 PM PDT 24
Peak memory 218832 kb
Host smart-3d3ac684-e532-4885-8764-f44c93a6465e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361345891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1361345891
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1239339557
Short name T391
Test name
Test status
Simulation time 27518001 ps
CPU time 1.2 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 219868 kb
Host smart-c9056678-03bc-4411-9a74-23222f872bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239339557 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1239339557
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1014909981
Short name T653
Test name
Test status
Simulation time 34597535 ps
CPU time 1.02 seconds
Started Jul 31 05:49:06 PM PDT 24
Finished Jul 31 05:49:07 PM PDT 24
Peak memory 214896 kb
Host smart-ad732817-e16d-4a0f-bc09-c5365cc5df6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014909981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1014909981
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3781940870
Short name T188
Test name
Test status
Simulation time 14476840 ps
CPU time 0.91 seconds
Started Jul 31 05:49:14 PM PDT 24
Finished Jul 31 05:49:15 PM PDT 24
Peak memory 215576 kb
Host smart-12a4c43e-54e3-4883-9ee6-430f75f249e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781940870 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3781940870
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2587036615
Short name T587
Test name
Test status
Simulation time 47935640 ps
CPU time 1.1 seconds
Started Jul 31 05:49:11 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 216912 kb
Host smart-424c3b72-52f5-45a3-bb76-7abe1bd55b1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587036615 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2587036615
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2074448763
Short name T7
Test name
Test status
Simulation time 25801680 ps
CPU time 1.18 seconds
Started Jul 31 05:49:14 PM PDT 24
Finished Jul 31 05:49:15 PM PDT 24
Peak memory 220576 kb
Host smart-724f6192-f93c-440a-9f11-ea694c575aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074448763 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2074448763
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.255758601
Short name T473
Test name
Test status
Simulation time 31976445 ps
CPU time 1.23 seconds
Started Jul 31 05:49:16 PM PDT 24
Finished Jul 31 05:49:18 PM PDT 24
Peak memory 220048 kb
Host smart-e714aac9-2417-4484-bda8-3b37127a58f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255758601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.255758601
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_smoke.2308062350
Short name T425
Test name
Test status
Simulation time 51399269 ps
CPU time 0.92 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 215124 kb
Host smart-4911cf7f-9169-4368-b773-5f6390eec334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308062350 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2308062350
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3131967106
Short name T793
Test name
Test status
Simulation time 563996920 ps
CPU time 2.08 seconds
Started Jul 31 05:49:12 PM PDT 24
Finished Jul 31 05:49:15 PM PDT 24
Peak memory 217376 kb
Host smart-e0a662d2-a968-4dc3-996b-fd5423c6f4ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131967106 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3131967106
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2909494729
Short name T862
Test name
Test status
Simulation time 191731893956 ps
CPU time 1000.89 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 06:05:51 PM PDT 24
Peak memory 222232 kb
Host smart-f0b029bc-36a8-4d7d-aa79-96b6e9242ce6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909494729 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2909494729
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1085957126
Short name T504
Test name
Test status
Simulation time 71811693 ps
CPU time 1.37 seconds
Started Jul 31 05:50:41 PM PDT 24
Finished Jul 31 05:50:42 PM PDT 24
Peak memory 217468 kb
Host smart-bb636a89-c391-4b8c-b184-6805101c8c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085957126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1085957126
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3754919568
Short name T864
Test name
Test status
Simulation time 39672154 ps
CPU time 1.45 seconds
Started Jul 31 05:50:52 PM PDT 24
Finished Jul 31 05:50:53 PM PDT 24
Peak memory 218492 kb
Host smart-9ad036e1-2455-40c4-a72b-d57a712e93a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754919568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3754919568
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2474095441
Short name T651
Test name
Test status
Simulation time 210610509 ps
CPU time 3.06 seconds
Started Jul 31 05:50:45 PM PDT 24
Finished Jul 31 05:50:48 PM PDT 24
Peak memory 220168 kb
Host smart-0b9a9cb2-557e-484a-8b55-4a70c06f17c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474095441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2474095441
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.296916864
Short name T458
Test name
Test status
Simulation time 48283269 ps
CPU time 1.29 seconds
Started Jul 31 05:50:55 PM PDT 24
Finished Jul 31 05:50:57 PM PDT 24
Peak memory 218624 kb
Host smart-529b55e8-aece-4fb3-a2f5-ef98ce14599d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296916864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.296916864
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.4043492929
Short name T540
Test name
Test status
Simulation time 70906054 ps
CPU time 1.66 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:47 PM PDT 24
Peak memory 218764 kb
Host smart-9821609e-7816-4d2c-8eaa-0154dcae0b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043492929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.4043492929
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.4187445321
Short name T555
Test name
Test status
Simulation time 39601890 ps
CPU time 1.12 seconds
Started Jul 31 05:50:57 PM PDT 24
Finished Jul 31 05:50:58 PM PDT 24
Peak memory 218608 kb
Host smart-2451332b-df11-4e53-ac76-2b9f8aa7dcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187445321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.4187445321
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2627306830
Short name T315
Test name
Test status
Simulation time 286810591 ps
CPU time 4.03 seconds
Started Jul 31 05:50:53 PM PDT 24
Finished Jul 31 05:50:57 PM PDT 24
Peak memory 220176 kb
Host smart-5ff4d97f-ebc8-4700-87a6-db779a1e7cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627306830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2627306830
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.586867323
Short name T783
Test name
Test status
Simulation time 230362320 ps
CPU time 3.13 seconds
Started Jul 31 05:50:52 PM PDT 24
Finished Jul 31 05:50:55 PM PDT 24
Peak memory 219892 kb
Host smart-fed14749-3945-4a8c-9242-0749a74786e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586867323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.586867323
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2181020354
Short name T244
Test name
Test status
Simulation time 65505427 ps
CPU time 1.26 seconds
Started Jul 31 05:50:55 PM PDT 24
Finished Jul 31 05:50:56 PM PDT 24
Peak memory 215216 kb
Host smart-6697bb33-1397-49e7-a146-2f99365e14f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181020354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2181020354
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1857246863
Short name T242
Test name
Test status
Simulation time 53544340 ps
CPU time 1.17 seconds
Started Jul 31 05:50:58 PM PDT 24
Finished Jul 31 05:50:59 PM PDT 24
Peak memory 215296 kb
Host smart-ed111449-c6f7-4097-bb35-0402d0d9db43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857246863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1857246863
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1269672589
Short name T946
Test name
Test status
Simulation time 44236440 ps
CPU time 1.1 seconds
Started Jul 31 05:49:13 PM PDT 24
Finished Jul 31 05:49:14 PM PDT 24
Peak memory 219752 kb
Host smart-ce76944b-0eeb-48f5-86cc-a5834fe6af11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269672589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1269672589
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.200666384
Short name T475
Test name
Test status
Simulation time 49505425 ps
CPU time 0.93 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 05:49:18 PM PDT 24
Peak memory 214880 kb
Host smart-16ef3a69-534e-4802-a4db-52c0d3110c86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200666384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.200666384
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.4043814430
Short name T674
Test name
Test status
Simulation time 62196459 ps
CPU time 1.25 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 216996 kb
Host smart-d74690c8-25b9-44f7-ac14-32177b16360a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043814430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.4043814430
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2995797055
Short name T500
Test name
Test status
Simulation time 34921755 ps
CPU time 1.21 seconds
Started Jul 31 05:49:20 PM PDT 24
Finished Jul 31 05:49:21 PM PDT 24
Peak memory 229620 kb
Host smart-fb1c3f96-8f63-415a-87e7-d2244bec7dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995797055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2995797055
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3168623707
Short name T524
Test name
Test status
Simulation time 22150929 ps
CPU time 1.06 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 05:49:18 PM PDT 24
Peak memory 217544 kb
Host smart-13d7fe49-b83a-49f7-a0ba-8c9124b707f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168623707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3168623707
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.790244472
Short name T100
Test name
Test status
Simulation time 23925107 ps
CPU time 0.92 seconds
Started Jul 31 05:49:39 PM PDT 24
Finished Jul 31 05:49:40 PM PDT 24
Peak memory 215876 kb
Host smart-83e6f625-a48a-45c6-90b2-3a0f9cec4bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790244472 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.790244472
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3170061521
Short name T593
Test name
Test status
Simulation time 16807188 ps
CPU time 0.99 seconds
Started Jul 31 05:49:41 PM PDT 24
Finished Jul 31 05:49:42 PM PDT 24
Peak memory 215244 kb
Host smart-13bb11f1-bdc9-454c-93a6-e82d0502dd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170061521 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3170061521
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1268337852
Short name T722
Test name
Test status
Simulation time 698373468 ps
CPU time 2.99 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 220208 kb
Host smart-3c0ebc0d-8cbb-4b72-b0af-c48c6b26ef0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268337852 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1268337852
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2652269395
Short name T421
Test name
Test status
Simulation time 125909021187 ps
CPU time 769.25 seconds
Started Jul 31 05:49:12 PM PDT 24
Finished Jul 31 06:02:01 PM PDT 24
Peak memory 221612 kb
Host smart-f5d3606f-3e82-46da-8635-8a7ab6f7bec9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652269395 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2652269395
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2486584754
Short name T321
Test name
Test status
Simulation time 47320214 ps
CPU time 1.4 seconds
Started Jul 31 05:51:03 PM PDT 24
Finished Jul 31 05:51:04 PM PDT 24
Peak memory 219944 kb
Host smart-12fa274c-bc89-4ad8-ac53-b15bc6332f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486584754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2486584754
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2850480019
Short name T390
Test name
Test status
Simulation time 62359410 ps
CPU time 1.38 seconds
Started Jul 31 05:50:49 PM PDT 24
Finished Jul 31 05:50:51 PM PDT 24
Peak memory 218480 kb
Host smart-75abddca-f3ea-4f6b-a6af-0986bc4201a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850480019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2850480019
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.4036608964
Short name T649
Test name
Test status
Simulation time 58955779 ps
CPU time 1.4 seconds
Started Jul 31 05:50:48 PM PDT 24
Finished Jul 31 05:50:49 PM PDT 24
Peak memory 218536 kb
Host smart-ba61d9f0-f6af-4a55-bfb0-2564d5e71652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036608964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.4036608964
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3951306683
Short name T667
Test name
Test status
Simulation time 69241074 ps
CPU time 1.32 seconds
Started Jul 31 05:50:47 PM PDT 24
Finished Jul 31 05:50:48 PM PDT 24
Peak memory 219792 kb
Host smart-e1a7c43d-3a73-4af7-900b-54165ef1be06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951306683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3951306683
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2611287428
Short name T449
Test name
Test status
Simulation time 53051264 ps
CPU time 1.39 seconds
Started Jul 31 05:50:53 PM PDT 24
Finished Jul 31 05:50:54 PM PDT 24
Peak memory 218684 kb
Host smart-470e8ce5-9a50-42f4-afcc-0cb1246e3cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611287428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2611287428
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3955447097
Short name T371
Test name
Test status
Simulation time 82756486 ps
CPU time 1.51 seconds
Started Jul 31 05:50:54 PM PDT 24
Finished Jul 31 05:50:56 PM PDT 24
Peak memory 218900 kb
Host smart-7b3766cf-cb7e-430b-8c25-8f32aefe9d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955447097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3955447097
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1366670985
Short name T369
Test name
Test status
Simulation time 42874626 ps
CPU time 1.28 seconds
Started Jul 31 05:50:54 PM PDT 24
Finished Jul 31 05:50:55 PM PDT 24
Peak memory 219976 kb
Host smart-d7afff54-3765-466d-aadc-61616f9d8cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366670985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1366670985
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.4160699538
Short name T519
Test name
Test status
Simulation time 192957457 ps
CPU time 1.39 seconds
Started Jul 31 05:51:03 PM PDT 24
Finished Jul 31 05:51:05 PM PDT 24
Peak memory 218728 kb
Host smart-b52672df-e74c-427a-95b3-c03d3fbf5cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160699538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.4160699538
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3513196548
Short name T480
Test name
Test status
Simulation time 38373634 ps
CPU time 1.43 seconds
Started Jul 31 05:50:54 PM PDT 24
Finished Jul 31 05:50:55 PM PDT 24
Peak memory 218292 kb
Host smart-46c96034-37a9-4630-b38f-751c5e7b2cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513196548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3513196548
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.351860091
Short name T283
Test name
Test status
Simulation time 44371722 ps
CPU time 1.43 seconds
Started Jul 31 05:50:55 PM PDT 24
Finished Jul 31 05:50:56 PM PDT 24
Peak memory 218364 kb
Host smart-e7956446-9ba7-48d1-b372-b7d5df46a7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351860091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.351860091
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.612698551
Short name T66
Test name
Test status
Simulation time 39076225 ps
CPU time 1.06 seconds
Started Jul 31 05:49:11 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 218436 kb
Host smart-d71c1041-11de-4564-bd90-557b530f8634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612698551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.612698551
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.4212623136
Short name T889
Test name
Test status
Simulation time 14769352 ps
CPU time 0.95 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:09 PM PDT 24
Peak memory 214836 kb
Host smart-f3740c59-c20a-4bea-9bf4-477b1a523e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212623136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.4212623136
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2956087215
Short name T836
Test name
Test status
Simulation time 40247027 ps
CPU time 0.91 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 215328 kb
Host smart-22615f7f-7d35-4987-8d89-b37941154f51
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956087215 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2956087215
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1935451959
Short name T741
Test name
Test status
Simulation time 38152661 ps
CPU time 1.38 seconds
Started Jul 31 05:49:12 PM PDT 24
Finished Jul 31 05:49:13 PM PDT 24
Peak memory 217020 kb
Host smart-e2b15b4f-cb0d-4f21-b180-bc2c5f4192e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935451959 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1935451959
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.694139114
Short name T823
Test name
Test status
Simulation time 233416014 ps
CPU time 1.28 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 05:49:19 PM PDT 24
Peak memory 224824 kb
Host smart-037b4b89-9c95-499c-a92d-1e9b90d7f8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694139114 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.694139114
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1877437088
Short name T505
Test name
Test status
Simulation time 34194608 ps
CPU time 1.38 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 218512 kb
Host smart-1081ba3d-3699-466a-991a-9e12b287d650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877437088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1877437088
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.726493876
Short name T363
Test name
Test status
Simulation time 40111213 ps
CPU time 0.9 seconds
Started Jul 31 05:49:14 PM PDT 24
Finished Jul 31 05:49:15 PM PDT 24
Peak memory 215496 kb
Host smart-8a55844c-b5ad-43bf-aaea-430d73878fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726493876 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.726493876
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.382748698
Short name T724
Test name
Test status
Simulation time 18700366 ps
CPU time 0.91 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 215280 kb
Host smart-7aa74cbc-f23c-4c9d-a349-9bdff6f65a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382748698 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.382748698
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3039579018
Short name T102
Test name
Test status
Simulation time 137112471 ps
CPU time 3.17 seconds
Started Jul 31 05:49:33 PM PDT 24
Finished Jul 31 05:49:36 PM PDT 24
Peak memory 215372 kb
Host smart-672b8627-7c20-4c31-aa85-eab9f6d33206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039579018 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3039579018
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2057931349
Short name T25
Test name
Test status
Simulation time 13410241752 ps
CPU time 310.04 seconds
Started Jul 31 05:49:13 PM PDT 24
Finished Jul 31 05:54:24 PM PDT 24
Peak memory 218112 kb
Host smart-3bebc385-4026-4a47-a00c-62fcb940243f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057931349 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2057931349
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.4128038028
Short name T926
Test name
Test status
Simulation time 44517072 ps
CPU time 1.53 seconds
Started Jul 31 05:50:58 PM PDT 24
Finished Jul 31 05:50:59 PM PDT 24
Peak memory 219360 kb
Host smart-39c147f9-3278-4f55-b3e2-2786294dc40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128038028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.4128038028
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2270103005
Short name T93
Test name
Test status
Simulation time 81248830 ps
CPU time 2.95 seconds
Started Jul 31 05:50:44 PM PDT 24
Finished Jul 31 05:50:47 PM PDT 24
Peak memory 220120 kb
Host smart-10cc1216-6aec-4f16-98e4-d9cb0d18f158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270103005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2270103005
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1411367893
Short name T517
Test name
Test status
Simulation time 56327740 ps
CPU time 1.26 seconds
Started Jul 31 05:50:54 PM PDT 24
Finished Jul 31 05:50:55 PM PDT 24
Peak memory 218504 kb
Host smart-e4ffe3cc-42b0-4f9b-8096-aff5777856fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411367893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1411367893
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1912463024
Short name T417
Test name
Test status
Simulation time 28486826 ps
CPU time 1.15 seconds
Started Jul 31 05:50:51 PM PDT 24
Finished Jul 31 05:50:53 PM PDT 24
Peak memory 217288 kb
Host smart-689821a3-b531-428b-b346-d076395b7b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912463024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1912463024
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1985208177
Short name T470
Test name
Test status
Simulation time 59048243 ps
CPU time 1.54 seconds
Started Jul 31 05:50:54 PM PDT 24
Finished Jul 31 05:50:56 PM PDT 24
Peak memory 218928 kb
Host smart-66518ff9-dfdb-4298-8456-02ad5a01e69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985208177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1985208177
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2939940554
Short name T901
Test name
Test status
Simulation time 62548381 ps
CPU time 1.37 seconds
Started Jul 31 05:50:53 PM PDT 24
Finished Jul 31 05:50:55 PM PDT 24
Peak memory 218672 kb
Host smart-1af8aac5-407f-41b0-be12-119212528001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939940554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2939940554
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1061134612
Short name T304
Test name
Test status
Simulation time 74354036 ps
CPU time 1.46 seconds
Started Jul 31 05:50:45 PM PDT 24
Finished Jul 31 05:50:48 PM PDT 24
Peak memory 218512 kb
Host smart-2279c98d-2baa-4da9-8b2e-348ed5a0e1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061134612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1061134612
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1001702085
Short name T386
Test name
Test status
Simulation time 40443990 ps
CPU time 1.05 seconds
Started Jul 31 05:51:00 PM PDT 24
Finished Jul 31 05:51:01 PM PDT 24
Peak memory 217484 kb
Host smart-fe861f0f-edad-47ea-a0b3-e7881b2e5f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001702085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1001702085
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1904727323
Short name T40
Test name
Test status
Simulation time 86715089 ps
CPU time 1.56 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:47 PM PDT 24
Peak memory 218436 kb
Host smart-40135cab-3cb5-4f49-b2f8-c867682e165c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904727323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1904727323
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.4030724929
Short name T366
Test name
Test status
Simulation time 61407277 ps
CPU time 1.49 seconds
Started Jul 31 05:50:56 PM PDT 24
Finished Jul 31 05:50:57 PM PDT 24
Peak memory 218656 kb
Host smart-8f624d12-ec35-46e1-ac92-7f1d9d44af94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030724929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.4030724929
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3393733453
Short name T104
Test name
Test status
Simulation time 23958130 ps
CPU time 1.11 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 219704 kb
Host smart-87fc0e9d-c55b-432e-a46e-348c45f1b6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393733453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3393733453
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.478766282
Short name T965
Test name
Test status
Simulation time 38440940 ps
CPU time 0.86 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 206516 kb
Host smart-d06a2074-1bb3-4988-a05f-ec6b6e042f41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478766282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.478766282
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2937738371
Short name T208
Test name
Test status
Simulation time 17415191 ps
CPU time 0.82 seconds
Started Jul 31 05:49:15 PM PDT 24
Finished Jul 31 05:49:16 PM PDT 24
Peak memory 216192 kb
Host smart-a2c0b19c-5c0d-4889-a577-9f3d00692e93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937738371 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2937738371
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3767336926
Short name T161
Test name
Test status
Simulation time 390136494 ps
CPU time 1.05 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 216844 kb
Host smart-605acf1f-1998-45c9-b262-a27af7fced1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767336926 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3767336926
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1846556809
Short name T835
Test name
Test status
Simulation time 22208624 ps
CPU time 1.12 seconds
Started Jul 31 05:49:20 PM PDT 24
Finished Jul 31 05:49:27 PM PDT 24
Peak memory 218824 kb
Host smart-b00fb22d-26a4-474b-af52-02ab46b51325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846556809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1846556809
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2912106753
Short name T878
Test name
Test status
Simulation time 114686452 ps
CPU time 1.55 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 05:49:18 PM PDT 24
Peak memory 218804 kb
Host smart-fafe89f1-5175-4015-a16f-2bbd761be762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912106753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2912106753
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2051777437
Short name T97
Test name
Test status
Simulation time 23004026 ps
CPU time 1.03 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:09 PM PDT 24
Peak memory 215824 kb
Host smart-d7a9768a-ecc1-486c-8e14-96780dbacd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051777437 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2051777437
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.124494206
Short name T385
Test name
Test status
Simulation time 43501492 ps
CPU time 0.91 seconds
Started Jul 31 05:49:12 PM PDT 24
Finished Jul 31 05:49:13 PM PDT 24
Peak memory 215300 kb
Host smart-3cedd860-2706-413c-b1a7-aa73a6c8d64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124494206 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.124494206
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2616254773
Short name T618
Test name
Test status
Simulation time 241311973 ps
CPU time 2.96 seconds
Started Jul 31 05:49:14 PM PDT 24
Finished Jul 31 05:49:17 PM PDT 24
Peak memory 218452 kb
Host smart-5afcf8b0-7146-46c5-b5b0-c0f00d2cc9a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616254773 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2616254773
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2956603721
Short name T882
Test name
Test status
Simulation time 65397471638 ps
CPU time 855.01 seconds
Started Jul 31 05:49:14 PM PDT 24
Finished Jul 31 06:03:30 PM PDT 24
Peak memory 223736 kb
Host smart-c64df128-2c01-448f-964b-376d440bb581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956603721 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2956603721
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.685398110
Short name T571
Test name
Test status
Simulation time 53176063 ps
CPU time 1.63 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:48 PM PDT 24
Peak memory 218552 kb
Host smart-82b02d68-faf1-45a1-bf83-8577388e1bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685398110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.685398110
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.455413923
Short name T784
Test name
Test status
Simulation time 129486666 ps
CPU time 1.58 seconds
Started Jul 31 05:50:55 PM PDT 24
Finished Jul 31 05:50:57 PM PDT 24
Peak memory 218576 kb
Host smart-44457883-1cac-44ff-af7f-2151dbc3c5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455413923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.455413923
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3191448897
Short name T671
Test name
Test status
Simulation time 44254963 ps
CPU time 1.02 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:47 PM PDT 24
Peak memory 217132 kb
Host smart-ce45520b-2b88-4533-828c-538dcb5f002b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191448897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3191448897
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2858155218
Short name T527
Test name
Test status
Simulation time 109161265 ps
CPU time 1.31 seconds
Started Jul 31 05:50:57 PM PDT 24
Finished Jul 31 05:50:58 PM PDT 24
Peak memory 218948 kb
Host smart-addbcb44-b50a-40d0-878d-89e8a35b6d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858155218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2858155218
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.4162423853
Short name T383
Test name
Test status
Simulation time 74084330 ps
CPU time 1.49 seconds
Started Jul 31 05:50:54 PM PDT 24
Finished Jul 31 05:50:56 PM PDT 24
Peak memory 218920 kb
Host smart-1944522e-c8c0-44dd-b273-4720c2052c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162423853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.4162423853
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3739461816
Short name T821
Test name
Test status
Simulation time 35278196 ps
CPU time 1.43 seconds
Started Jul 31 05:50:48 PM PDT 24
Finished Jul 31 05:50:50 PM PDT 24
Peak memory 217224 kb
Host smart-85c58c28-ab08-41d8-b105-c9672c3e1fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739461816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3739461816
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2136145457
Short name T771
Test name
Test status
Simulation time 39924632 ps
CPU time 1.41 seconds
Started Jul 31 05:50:49 PM PDT 24
Finished Jul 31 05:50:50 PM PDT 24
Peak memory 218652 kb
Host smart-5a71be9d-ed18-4f29-80e9-ce8b73ecbebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136145457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2136145457
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2585208519
Short name T916
Test name
Test status
Simulation time 57618862 ps
CPU time 1.48 seconds
Started Jul 31 05:51:03 PM PDT 24
Finished Jul 31 05:51:04 PM PDT 24
Peak memory 218748 kb
Host smart-281e84d8-e55d-462c-bb3d-e137464918c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585208519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2585208519
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.676300303
Short name T717
Test name
Test status
Simulation time 226558321 ps
CPU time 1.14 seconds
Started Jul 31 05:50:52 PM PDT 24
Finished Jul 31 05:50:53 PM PDT 24
Peak memory 217304 kb
Host smart-2c6fcd84-2870-456a-a4dc-4bd91f79b940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676300303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.676300303
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2596056757
Short name T415
Test name
Test status
Simulation time 2216427365 ps
CPU time 65.55 seconds
Started Jul 31 05:51:02 PM PDT 24
Finished Jul 31 05:52:08 PM PDT 24
Peak memory 217700 kb
Host smart-f6b66339-7396-4eac-999a-347a01c9189d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596056757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2596056757
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3003100978
Short name T753
Test name
Test status
Simulation time 43824293 ps
CPU time 1.23 seconds
Started Jul 31 05:49:11 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 215688 kb
Host smart-f7d9ef7a-3b03-4600-9d62-c53485c7a380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003100978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3003100978
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.624617978
Short name T445
Test name
Test status
Simulation time 48631541 ps
CPU time 0.87 seconds
Started Jul 31 05:49:11 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 206644 kb
Host smart-11cafb5c-93ab-4659-8826-c19159c5b232
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624617978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.624617978
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2391087521
Short name T856
Test name
Test status
Simulation time 41167651 ps
CPU time 0.88 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 215892 kb
Host smart-6d88ae52-96ed-403d-bc66-14a7b76adcce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391087521 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2391087521
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.4286005190
Short name T598
Test name
Test status
Simulation time 54286750 ps
CPU time 1.04 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 216948 kb
Host smart-fcc5bb93-ba3a-4ce6-99b6-08c37950d1d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286005190 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.4286005190
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1934200975
Short name T766
Test name
Test status
Simulation time 77741629 ps
CPU time 1.07 seconds
Started Jul 31 05:49:18 PM PDT 24
Finished Jul 31 05:49:19 PM PDT 24
Peak memory 219692 kb
Host smart-391c2642-de40-4ebf-88ba-72f7aa55074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934200975 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1934200975
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2481126675
Short name T28
Test name
Test status
Simulation time 82686656 ps
CPU time 1.49 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:09 PM PDT 24
Peak memory 218564 kb
Host smart-7a447e27-d89a-4fad-976b-f79cd67b0cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481126675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2481126675
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.222627013
Short name T656
Test name
Test status
Simulation time 55902321 ps
CPU time 0.87 seconds
Started Jul 31 05:49:20 PM PDT 24
Finished Jul 31 05:49:21 PM PDT 24
Peak memory 215316 kb
Host smart-9b8d9f68-0156-42be-80a1-b4405eb1ee54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222627013 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.222627013
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1567464157
Short name T442
Test name
Test status
Simulation time 17888556 ps
CPU time 0.98 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 05:49:18 PM PDT 24
Peak memory 215300 kb
Host smart-4368ba95-203c-48e4-855c-adf0b5f69758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567464157 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1567464157
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.4197196292
Short name T565
Test name
Test status
Simulation time 268634928 ps
CPU time 3.09 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:13 PM PDT 24
Peak memory 215276 kb
Host smart-88a226b4-c447-4b33-985c-49bd3aff45fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197196292 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.4197196292
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3585505401
Short name T877
Test name
Test status
Simulation time 101203796147 ps
CPU time 1188.56 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 06:08:57 PM PDT 24
Peak memory 225160 kb
Host smart-9e4f77fe-156e-4af5-b8e8-14aa14fca9a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585505401 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3585505401
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.465197298
Short name T984
Test name
Test status
Simulation time 40094401 ps
CPU time 1.26 seconds
Started Jul 31 05:50:52 PM PDT 24
Finished Jul 31 05:50:54 PM PDT 24
Peak memory 218768 kb
Host smart-b41f03d2-b00c-4da6-8c8b-78d22be75e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465197298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.465197298
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3519235346
Short name T747
Test name
Test status
Simulation time 66787591 ps
CPU time 1.25 seconds
Started Jul 31 05:50:53 PM PDT 24
Finished Jul 31 05:50:54 PM PDT 24
Peak memory 219844 kb
Host smart-38766dff-31f2-481e-a7f9-f74c7b03f46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519235346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3519235346
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3444488469
Short name T881
Test name
Test status
Simulation time 48933113 ps
CPU time 1.6 seconds
Started Jul 31 05:51:03 PM PDT 24
Finished Jul 31 05:51:05 PM PDT 24
Peak memory 218324 kb
Host smart-9c065b2f-b6c2-4ece-8aa6-77aaabe62684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444488469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3444488469
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1040883634
Short name T35
Test name
Test status
Simulation time 46135990 ps
CPU time 1.57 seconds
Started Jul 31 05:50:54 PM PDT 24
Finished Jul 31 05:50:55 PM PDT 24
Peak memory 218540 kb
Host smart-ef29327e-4180-42f6-9392-7b4651b407e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040883634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1040883634
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2350653713
Short name T402
Test name
Test status
Simulation time 42602254 ps
CPU time 1.08 seconds
Started Jul 31 05:50:51 PM PDT 24
Finished Jul 31 05:50:53 PM PDT 24
Peak memory 217280 kb
Host smart-b3bec8dd-9509-4aee-aad3-dc5b55255951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350653713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2350653713
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.572461974
Short name T625
Test name
Test status
Simulation time 80582741 ps
CPU time 1.14 seconds
Started Jul 31 05:50:46 PM PDT 24
Finished Jul 31 05:50:48 PM PDT 24
Peak memory 218696 kb
Host smart-6ad112c8-ca0a-47db-bce1-638c12833fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572461974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.572461974
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.826570294
Short name T893
Test name
Test status
Simulation time 37805969 ps
CPU time 1.51 seconds
Started Jul 31 05:50:57 PM PDT 24
Finished Jul 31 05:50:59 PM PDT 24
Peak memory 218632 kb
Host smart-c35c87a9-479b-46f8-8aff-19a4ea48bb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826570294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.826570294
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3410821594
Short name T576
Test name
Test status
Simulation time 47492590 ps
CPU time 1.53 seconds
Started Jul 31 05:50:53 PM PDT 24
Finished Jul 31 05:50:55 PM PDT 24
Peak memory 218640 kb
Host smart-a9192045-f169-462b-b510-33b1f70158b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410821594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3410821594
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2342038937
Short name T299
Test name
Test status
Simulation time 39463705 ps
CPU time 1.6 seconds
Started Jul 31 05:51:02 PM PDT 24
Finished Jul 31 05:51:03 PM PDT 24
Peak memory 218592 kb
Host smart-bb1ca575-1361-478e-a10a-d6cb2724363e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342038937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2342038937
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.754699082
Short name T814
Test name
Test status
Simulation time 73737463 ps
CPU time 1.1 seconds
Started Jul 31 05:50:53 PM PDT 24
Finished Jul 31 05:50:54 PM PDT 24
Peak memory 220000 kb
Host smart-d565d7cc-98bc-4bb9-8321-fd38cfe69cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754699082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.754699082
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.4117695521
Short name T670
Test name
Test status
Simulation time 54866807 ps
CPU time 1.2 seconds
Started Jul 31 05:49:13 PM PDT 24
Finished Jul 31 05:49:14 PM PDT 24
Peak memory 220352 kb
Host smart-abbee5f7-a82f-4499-bc9e-643855282924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117695521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.4117695521
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2162714986
Short name T788
Test name
Test status
Simulation time 50934540 ps
CPU time 0.9 seconds
Started Jul 31 05:49:24 PM PDT 24
Finished Jul 31 05:49:25 PM PDT 24
Peak memory 206748 kb
Host smart-ea5687cb-b700-4896-8116-f9ab55138e66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162714986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2162714986
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2882014097
Short name T129
Test name
Test status
Simulation time 23060057 ps
CPU time 0.83 seconds
Started Jul 31 05:49:24 PM PDT 24
Finished Jul 31 05:49:25 PM PDT 24
Peak memory 216204 kb
Host smart-9dbff845-e1d2-49af-97dd-3dab0c3f7c5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882014097 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2882014097
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.695661184
Short name T822
Test name
Test status
Simulation time 39983609 ps
CPU time 1.29 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 05:49:18 PM PDT 24
Peak memory 216796 kb
Host smart-297ed735-5f44-4225-b05b-9417ca75a14f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695661184 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.695661184
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1444975464
Short name T668
Test name
Test status
Simulation time 18801844 ps
CPU time 1.12 seconds
Started Jul 31 05:49:20 PM PDT 24
Finished Jul 31 05:49:21 PM PDT 24
Peak memory 218584 kb
Host smart-c817f7ed-72f1-49b0-a69d-acd561dc2c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444975464 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1444975464
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1436525148
Short name T373
Test name
Test status
Simulation time 49519776 ps
CPU time 1.41 seconds
Started Jul 31 05:49:18 PM PDT 24
Finished Jul 31 05:49:20 PM PDT 24
Peak memory 218700 kb
Host smart-98fcb7fe-cada-4730-ac2c-8c887ef31b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436525148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1436525148
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3133960436
Short name T858
Test name
Test status
Simulation time 21411801 ps
CPU time 1.09 seconds
Started Jul 31 05:49:16 PM PDT 24
Finished Jul 31 05:49:17 PM PDT 24
Peak memory 215888 kb
Host smart-462a0ab6-610b-4edb-bf92-1cae5385443f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133960436 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3133960436
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1808457462
Short name T979
Test name
Test status
Simulation time 57686329 ps
CPU time 0.89 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 215288 kb
Host smart-40b3ec3e-ce5a-4f64-b22f-6d6fd22258fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808457462 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1808457462
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3183834458
Short name T246
Test name
Test status
Simulation time 366138687 ps
CPU time 2.49 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:13 PM PDT 24
Peak memory 218528 kb
Host smart-373bdd1d-c0b3-4b76-9eed-c5d07131aea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183834458 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3183834458
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2082982875
Short name T715
Test name
Test status
Simulation time 156223813536 ps
CPU time 1062.94 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 06:06:52 PM PDT 24
Peak memory 223032 kb
Host smart-8c6c8390-d10c-4449-bcb4-080b91e0d1fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082982875 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2082982875
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.4191564754
Short name T516
Test name
Test status
Simulation time 53370305 ps
CPU time 1.05 seconds
Started Jul 31 05:51:00 PM PDT 24
Finished Jul 31 05:51:01 PM PDT 24
Peak memory 217260 kb
Host smart-fb16f9a5-31f7-475b-8f3d-8c8789c8a7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191564754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.4191564754
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.4013977184
Short name T791
Test name
Test status
Simulation time 51401107 ps
CPU time 1.91 seconds
Started Jul 31 05:50:54 PM PDT 24
Finished Jul 31 05:50:56 PM PDT 24
Peak memory 220192 kb
Host smart-cb6d86ff-6950-464b-bf83-c624e45adf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013977184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.4013977184
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2338592865
Short name T768
Test name
Test status
Simulation time 86398221 ps
CPU time 1.42 seconds
Started Jul 31 05:50:56 PM PDT 24
Finished Jul 31 05:50:58 PM PDT 24
Peak memory 218976 kb
Host smart-aeda4e24-69b1-4b21-a1d3-0f05ee557835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338592865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2338592865
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2501137750
Short name T775
Test name
Test status
Simulation time 112717528 ps
CPU time 1.55 seconds
Started Jul 31 05:50:48 PM PDT 24
Finished Jul 31 05:50:50 PM PDT 24
Peak memory 219896 kb
Host smart-87cc9dcc-2c1f-46a2-b9f7-fe57db7cffb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501137750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2501137750
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1907713589
Short name T352
Test name
Test status
Simulation time 62055296 ps
CPU time 1.18 seconds
Started Jul 31 05:50:59 PM PDT 24
Finished Jul 31 05:51:00 PM PDT 24
Peak memory 218820 kb
Host smart-5848594e-b60b-496a-bded-7d3da3d98704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907713589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1907713589
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3063674905
Short name T462
Test name
Test status
Simulation time 74122272 ps
CPU time 1.09 seconds
Started Jul 31 05:50:51 PM PDT 24
Finished Jul 31 05:50:52 PM PDT 24
Peak memory 218736 kb
Host smart-0469896e-8f66-4356-a9f3-952f0d61b00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063674905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3063674905
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3678097131
Short name T39
Test name
Test status
Simulation time 55049515 ps
CPU time 1.34 seconds
Started Jul 31 05:51:03 PM PDT 24
Finished Jul 31 05:51:04 PM PDT 24
Peak memory 218632 kb
Host smart-8a2f3103-1f77-47ce-9986-5f07c52693a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678097131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3678097131
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2684095897
Short name T471
Test name
Test status
Simulation time 59329151 ps
CPU time 2.3 seconds
Started Jul 31 05:50:50 PM PDT 24
Finished Jul 31 05:50:53 PM PDT 24
Peak memory 220044 kb
Host smart-b2e5e433-f614-4a55-9083-b348d9bf7e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684095897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2684095897
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.348612
Short name T940
Test name
Test status
Simulation time 111288055 ps
CPU time 1.17 seconds
Started Jul 31 05:50:51 PM PDT 24
Finished Jul 31 05:50:52 PM PDT 24
Peak memory 219104 kb
Host smart-a45af028-8c53-4383-ab51-6fd10977f2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.348612
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3439143257
Short name T12
Test name
Test status
Simulation time 98391635 ps
CPU time 1.2 seconds
Started Jul 31 05:50:52 PM PDT 24
Finished Jul 31 05:50:53 PM PDT 24
Peak memory 218564 kb
Host smart-3bf8be53-6953-4a08-88b2-9b7b7c055c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439143257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3439143257
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.899309316
Short name T813
Test name
Test status
Simulation time 72225532 ps
CPU time 1.13 seconds
Started Jul 31 05:48:39 PM PDT 24
Finished Jul 31 05:48:41 PM PDT 24
Peak memory 218676 kb
Host smart-33a6b2b5-2f17-4040-bd1e-e9d8def294b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899309316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.899309316
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1939782134
Short name T799
Test name
Test status
Simulation time 113788945 ps
CPU time 0.85 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:04 PM PDT 24
Peak memory 214704 kb
Host smart-ef3f371d-64a8-421f-920f-5a17e1a8b490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939782134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1939782134
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2306902798
Short name T765
Test name
Test status
Simulation time 11698689 ps
CPU time 0.88 seconds
Started Jul 31 05:48:51 PM PDT 24
Finished Jul 31 05:48:52 PM PDT 24
Peak memory 216072 kb
Host smart-76823bb3-bf07-4342-9469-eee1b026b1b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306902798 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2306902798
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3282160156
Short name T731
Test name
Test status
Simulation time 41760912 ps
CPU time 1 seconds
Started Jul 31 05:48:58 PM PDT 24
Finished Jul 31 05:48:59 PM PDT 24
Peak memory 216800 kb
Host smart-9d364ae5-fa6f-4fba-a588-ceb2d0573828
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282160156 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3282160156
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.240059171
Short name T154
Test name
Test status
Simulation time 64181206 ps
CPU time 1.08 seconds
Started Jul 31 05:49:02 PM PDT 24
Finished Jul 31 05:49:03 PM PDT 24
Peak memory 220752 kb
Host smart-2718e2f0-0b07-4404-8d34-7815a32d1203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240059171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.240059171
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2790251674
Short name T3
Test name
Test status
Simulation time 37257606 ps
CPU time 1.52 seconds
Started Jul 31 05:48:53 PM PDT 24
Finished Jul 31 05:48:55 PM PDT 24
Peak memory 218424 kb
Host smart-2ee096ee-3a5b-402c-8685-f2dbbb298a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790251674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2790251674
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.4028408579
Short name T808
Test name
Test status
Simulation time 23001729 ps
CPU time 1.1 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:08 PM PDT 24
Peak memory 215608 kb
Host smart-29d84c3e-a150-44c9-a231-60e4500822f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028408579 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.4028408579
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2361155502
Short name T529
Test name
Test status
Simulation time 77676093 ps
CPU time 0.9 seconds
Started Jul 31 05:48:58 PM PDT 24
Finished Jul 31 05:48:59 PM PDT 24
Peak memory 207088 kb
Host smart-51afcfb1-2a38-4689-8a14-5768ae29e485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361155502 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2361155502
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.3070029701
Short name T378
Test name
Test status
Simulation time 18110292 ps
CPU time 0.99 seconds
Started Jul 31 05:48:52 PM PDT 24
Finished Jul 31 05:48:53 PM PDT 24
Peak memory 215264 kb
Host smart-200efa1b-13a1-4e1a-8017-1d782a241b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070029701 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3070029701
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1798854900
Short name T497
Test name
Test status
Simulation time 217808868 ps
CPU time 2.83 seconds
Started Jul 31 05:48:51 PM PDT 24
Finished Jul 31 05:48:54 PM PDT 24
Peak memory 217024 kb
Host smart-8e54abbc-c4d8-4a48-ae64-bcdfe6cd7e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798854900 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1798854900
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3888681248
Short name T841
Test name
Test status
Simulation time 68928041945 ps
CPU time 846.05 seconds
Started Jul 31 05:49:01 PM PDT 24
Finished Jul 31 06:03:07 PM PDT 24
Peak memory 223696 kb
Host smart-bf39b180-9a67-49d2-830f-2297495df96d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888681248 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3888681248
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2573661958
Short name T326
Test name
Test status
Simulation time 197171797 ps
CPU time 1.1 seconds
Started Jul 31 05:49:23 PM PDT 24
Finished Jul 31 05:49:24 PM PDT 24
Peak memory 218312 kb
Host smart-c0d8d38c-d9bc-4111-8ded-a6ecd140be63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573661958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2573661958
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2479411688
Short name T628
Test name
Test status
Simulation time 26165217 ps
CPU time 0.93 seconds
Started Jul 31 05:49:33 PM PDT 24
Finished Jul 31 05:49:34 PM PDT 24
Peak memory 206652 kb
Host smart-74323be2-105c-4200-87da-e010b641d7a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479411688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2479411688
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.4176449382
Short name T410
Test name
Test status
Simulation time 16643079 ps
CPU time 0.84 seconds
Started Jul 31 05:49:28 PM PDT 24
Finished Jul 31 05:49:29 PM PDT 24
Peak memory 215892 kb
Host smart-35eb1fbf-4b20-4c7e-b39d-5781b8b003a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176449382 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4176449382
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.675759733
Short name T631
Test name
Test status
Simulation time 93382670 ps
CPU time 1.02 seconds
Started Jul 31 05:49:16 PM PDT 24
Finished Jul 31 05:49:17 PM PDT 24
Peak memory 218536 kb
Host smart-380c9a3d-d9db-450c-aae5-a8feaa643b2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675759733 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.675759733
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1262411987
Short name T160
Test name
Test status
Simulation time 49058014 ps
CPU time 0.94 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 05:49:18 PM PDT 24
Peak memory 219636 kb
Host smart-d50fce07-a538-43a9-bda9-94fc0395ce31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262411987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1262411987
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1161301543
Short name T447
Test name
Test status
Simulation time 33509609 ps
CPU time 1.33 seconds
Started Jul 31 05:49:45 PM PDT 24
Finished Jul 31 05:49:46 PM PDT 24
Peak memory 218448 kb
Host smart-8fd24242-e288-4c4f-b0f3-92f314031e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161301543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1161301543
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1011829571
Short name T79
Test name
Test status
Simulation time 98571201 ps
CPU time 0.83 seconds
Started Jul 31 05:49:13 PM PDT 24
Finished Jul 31 05:49:14 PM PDT 24
Peak memory 215516 kb
Host smart-d260b034-7fe2-402d-a1ab-cfbf8599128e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011829571 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1011829571
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2957174749
Short name T695
Test name
Test status
Simulation time 21140565 ps
CPU time 1 seconds
Started Jul 31 05:49:20 PM PDT 24
Finished Jul 31 05:49:21 PM PDT 24
Peak memory 215272 kb
Host smart-509e7dca-5041-4ccf-8a9e-d0141c284dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957174749 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2957174749
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.33262125
Short name T103
Test name
Test status
Simulation time 286012736 ps
CPU time 5.68 seconds
Started Jul 31 05:49:29 PM PDT 24
Finished Jul 31 05:49:35 PM PDT 24
Peak memory 217328 kb
Host smart-f5c0c726-1432-4224-b9ec-5de1dd9e5135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33262125 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.33262125
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2909171077
Short name T891
Test name
Test status
Simulation time 441781107795 ps
CPU time 1720.38 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 06:17:58 PM PDT 24
Peak memory 223900 kb
Host smart-1c0a0d7f-12ef-4cad-8513-56890ac77390
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909171077 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2909171077
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.359700367
Short name T355
Test name
Test status
Simulation time 52443471 ps
CPU time 1.24 seconds
Started Jul 31 05:49:20 PM PDT 24
Finished Jul 31 05:49:21 PM PDT 24
Peak memory 218548 kb
Host smart-10ca4282-ffab-4abb-b016-052ae8693090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359700367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.359700367
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3854417626
Short name T853
Test name
Test status
Simulation time 19125754 ps
CPU time 0.9 seconds
Started Jul 31 05:49:19 PM PDT 24
Finished Jul 31 05:49:20 PM PDT 24
Peak memory 206636 kb
Host smart-6ab48488-cf28-4450-bfd2-1926f79bf097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854417626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3854417626
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2205112050
Short name T969
Test name
Test status
Simulation time 12465845 ps
CPU time 0.88 seconds
Started Jul 31 05:49:34 PM PDT 24
Finished Jul 31 05:49:35 PM PDT 24
Peak memory 216100 kb
Host smart-8b7ead51-01ce-4be7-a38d-c849f5ed5b5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205112050 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2205112050
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3919107912
Short name T281
Test name
Test status
Simulation time 29991492 ps
CPU time 1.02 seconds
Started Jul 31 05:49:31 PM PDT 24
Finished Jul 31 05:49:32 PM PDT 24
Peak memory 215532 kb
Host smart-c97e910e-3f4d-40c6-adb5-2315acb730ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919107912 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3919107912
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2030157239
Short name T152
Test name
Test status
Simulation time 35708943 ps
CPU time 0.94 seconds
Started Jul 31 05:49:18 PM PDT 24
Finished Jul 31 05:49:19 PM PDT 24
Peak memory 218508 kb
Host smart-13694002-0065-4cf2-b0f5-1e87ab8f5a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030157239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2030157239
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3273218111
Short name T855
Test name
Test status
Simulation time 30307488 ps
CPU time 1.26 seconds
Started Jul 31 05:49:16 PM PDT 24
Finished Jul 31 05:49:17 PM PDT 24
Peak memory 218632 kb
Host smart-ee8d7973-b4f0-418d-b61f-c69b8d1daf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273218111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3273218111
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3695059522
Short name T539
Test name
Test status
Simulation time 28096138 ps
CPU time 0.99 seconds
Started Jul 31 05:49:38 PM PDT 24
Finished Jul 31 05:49:39 PM PDT 24
Peak memory 215420 kb
Host smart-1f0a31fe-96ff-4d13-81b1-0aa5bf123116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695059522 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3695059522
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.216230733
Short name T234
Test name
Test status
Simulation time 25426001 ps
CPU time 0.89 seconds
Started Jul 31 05:49:37 PM PDT 24
Finished Jul 31 05:49:38 PM PDT 24
Peak memory 215272 kb
Host smart-f0e72bf4-1228-4607-a228-98d80bafaafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216230733 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.216230733
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1905115011
Short name T782
Test name
Test status
Simulation time 229511259 ps
CPU time 1.61 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 05:49:19 PM PDT 24
Peak memory 217352 kb
Host smart-f05881ed-1e89-4785-a957-1f7f2c78f755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905115011 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1905115011
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1776381656
Short name T913
Test name
Test status
Simulation time 23696020196 ps
CPU time 271.55 seconds
Started Jul 31 05:49:39 PM PDT 24
Finished Jul 31 05:54:16 PM PDT 24
Peak memory 218588 kb
Host smart-23fc8d2f-c69d-4ebd-9be9-0b0b51e824b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776381656 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1776381656
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2654881706
Short name T780
Test name
Test status
Simulation time 81564820 ps
CPU time 1.18 seconds
Started Jul 31 05:49:20 PM PDT 24
Finished Jul 31 05:49:22 PM PDT 24
Peak memory 219812 kb
Host smart-fd4d01bc-72ad-4d1d-bc92-05b6eba0bda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654881706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2654881706
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.47481216
Short name T827
Test name
Test status
Simulation time 48048276 ps
CPU time 0.85 seconds
Started Jul 31 05:49:23 PM PDT 24
Finished Jul 31 05:49:24 PM PDT 24
Peak memory 206716 kb
Host smart-d4a63d2d-5788-4a26-9d6d-8643c4a06bb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47481216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.47481216
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3062957226
Short name T919
Test name
Test status
Simulation time 14457707 ps
CPU time 0.91 seconds
Started Jul 31 05:49:28 PM PDT 24
Finished Jul 31 05:49:29 PM PDT 24
Peak memory 216400 kb
Host smart-853e208c-b860-4866-9e9b-220612c269d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062957226 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3062957226
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1716262363
Short name T173
Test name
Test status
Simulation time 28094629 ps
CPU time 1.06 seconds
Started Jul 31 05:49:17 PM PDT 24
Finished Jul 31 05:49:18 PM PDT 24
Peak memory 218644 kb
Host smart-f448e6a1-8537-4c2c-b12e-bd84c1f55639
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716262363 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1716262363
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3303251225
Short name T146
Test name
Test status
Simulation time 103229592 ps
CPU time 1.26 seconds
Started Jul 31 05:49:42 PM PDT 24
Finished Jul 31 05:49:43 PM PDT 24
Peak memory 225668 kb
Host smart-9f75eaa5-0ec9-4fb4-9c57-e364a054ec4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303251225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3303251225
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2506609994
Short name T726
Test name
Test status
Simulation time 51134717 ps
CPU time 2.1 seconds
Started Jul 31 05:49:30 PM PDT 24
Finished Jul 31 05:49:33 PM PDT 24
Peak memory 218620 kb
Host smart-093a55fa-d962-41f6-a500-54b5caea7e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506609994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2506609994
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1533318158
Short name T89
Test name
Test status
Simulation time 34272183 ps
CPU time 0.91 seconds
Started Jul 31 05:49:18 PM PDT 24
Finished Jul 31 05:49:19 PM PDT 24
Peak memory 215744 kb
Host smart-edfe7c77-43ad-4ad3-9cb1-f84fa3179b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533318158 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1533318158
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2924515503
Short name T460
Test name
Test status
Simulation time 17843350 ps
CPU time 1.02 seconds
Started Jul 31 05:49:20 PM PDT 24
Finished Jul 31 05:49:21 PM PDT 24
Peak memory 215276 kb
Host smart-7c3bb2ee-07d0-45c5-bf88-35f0da090b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924515503 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2924515503
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2177191736
Short name T963
Test name
Test status
Simulation time 280753718 ps
CPU time 3.93 seconds
Started Jul 31 05:49:39 PM PDT 24
Finished Jul 31 05:49:43 PM PDT 24
Peak memory 219284 kb
Host smart-d70e906a-48b5-4895-8c56-9a7ab9cae3b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177191736 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2177191736
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1738677177
Short name T444
Test name
Test status
Simulation time 117343217374 ps
CPU time 1377.58 seconds
Started Jul 31 05:49:18 PM PDT 24
Finished Jul 31 06:12:16 PM PDT 24
Peak memory 225452 kb
Host smart-dce4417a-bc2b-4e19-b8ae-c9ada0b87eeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738677177 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1738677177
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.4125377799
Short name T180
Test name
Test status
Simulation time 35885211 ps
CPU time 1.28 seconds
Started Jul 31 05:49:35 PM PDT 24
Finished Jul 31 05:49:36 PM PDT 24
Peak memory 218464 kb
Host smart-807a946f-48d9-4b4a-8a39-9a3e71eb9bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125377799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.4125377799
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1936664687
Short name T23
Test name
Test status
Simulation time 16084750 ps
CPU time 0.97 seconds
Started Jul 31 05:49:42 PM PDT 24
Finished Jul 31 05:49:44 PM PDT 24
Peak memory 214816 kb
Host smart-e23c9437-54c2-46bf-91f1-1306dbdf8ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936664687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1936664687
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2176550370
Short name T797
Test name
Test status
Simulation time 30864834 ps
CPU time 0.85 seconds
Started Jul 31 05:49:43 PM PDT 24
Finished Jul 31 05:49:44 PM PDT 24
Peak memory 216232 kb
Host smart-a2fa828a-09d3-4bfd-b3fc-0a4143936a50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176550370 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2176550370
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3952913359
Short name T509
Test name
Test status
Simulation time 25052645 ps
CPU time 1.08 seconds
Started Jul 31 05:49:32 PM PDT 24
Finished Jul 31 05:49:34 PM PDT 24
Peak memory 218464 kb
Host smart-25f43bef-9176-4482-a8fc-6d238837b2a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952913359 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3952913359
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2142926018
Short name T121
Test name
Test status
Simulation time 19367460 ps
CPU time 1.09 seconds
Started Jul 31 05:49:42 PM PDT 24
Finished Jul 31 05:49:43 PM PDT 24
Peak memory 218268 kb
Host smart-9afe95f4-c925-4a2d-adc8-8f35359e4e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142926018 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2142926018
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3397697565
Short name T316
Test name
Test status
Simulation time 64279246 ps
CPU time 1.26 seconds
Started Jul 31 05:49:21 PM PDT 24
Finished Jul 31 05:49:22 PM PDT 24
Peak memory 217580 kb
Host smart-884eda22-76a5-41b8-a6f6-3b739734cb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397697565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3397697565
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1589568740
Short name T90
Test name
Test status
Simulation time 29517567 ps
CPU time 0.95 seconds
Started Jul 31 05:49:37 PM PDT 24
Finished Jul 31 05:49:38 PM PDT 24
Peak memory 215892 kb
Host smart-63d725c7-ed32-490a-85c7-a7327983453f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589568740 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1589568740
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2447646699
Short name T513
Test name
Test status
Simulation time 31710995 ps
CPU time 0.98 seconds
Started Jul 31 05:49:16 PM PDT 24
Finished Jul 31 05:49:17 PM PDT 24
Peak memory 215260 kb
Host smart-0add7431-82b4-419c-890c-d8360bc19832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447646699 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2447646699
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1359167770
Short name T794
Test name
Test status
Simulation time 151606681 ps
CPU time 0.93 seconds
Started Jul 31 05:49:30 PM PDT 24
Finished Jul 31 05:49:31 PM PDT 24
Peak memory 215336 kb
Host smart-9fa82dfc-1eef-4520-bb31-2a305dfc358a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359167770 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1359167770
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.4202925464
Short name T570
Test name
Test status
Simulation time 55502582485 ps
CPU time 383.91 seconds
Started Jul 31 05:49:21 PM PDT 24
Finished Jul 31 05:55:45 PM PDT 24
Peak memory 223700 kb
Host smart-2e76c887-0780-4f14-b112-d1cd7e2c25cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202925464 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.4202925464
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3227313156
Short name T596
Test name
Test status
Simulation time 40298475 ps
CPU time 1.13 seconds
Started Jul 31 05:49:20 PM PDT 24
Finished Jul 31 05:49:21 PM PDT 24
Peak memory 218640 kb
Host smart-7ed199af-3604-46ac-8a8f-a7dc88076615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227313156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3227313156
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1074668207
Short name T943
Test name
Test status
Simulation time 48043166 ps
CPU time 0.94 seconds
Started Jul 31 05:49:38 PM PDT 24
Finished Jul 31 05:49:39 PM PDT 24
Peak memory 214904 kb
Host smart-768679d9-773c-46d8-b5ce-8f66b40f0807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074668207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1074668207
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.839081051
Short name T989
Test name
Test status
Simulation time 12188550 ps
CPU time 0.86 seconds
Started Jul 31 05:49:27 PM PDT 24
Finished Jul 31 05:49:28 PM PDT 24
Peak memory 216020 kb
Host smart-2b3a8e16-4347-479c-a69c-4b363d916bf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839081051 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.839081051
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2138563333
Short name T840
Test name
Test status
Simulation time 40437647 ps
CPU time 1.39 seconds
Started Jul 31 05:49:27 PM PDT 24
Finished Jul 31 05:49:28 PM PDT 24
Peak memory 217080 kb
Host smart-c6df5286-3ccc-44e0-8136-172aff5092a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138563333 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2138563333
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2616087760
Short name T401
Test name
Test status
Simulation time 48162154 ps
CPU time 1.09 seconds
Started Jul 31 05:49:43 PM PDT 24
Finished Jul 31 05:49:44 PM PDT 24
Peak memory 219744 kb
Host smart-f5bffc8e-8009-4f69-8a1b-4969094d6dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616087760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2616087760
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2851809605
Short name T521
Test name
Test status
Simulation time 53805804 ps
CPU time 1.23 seconds
Started Jul 31 05:49:35 PM PDT 24
Finished Jul 31 05:49:37 PM PDT 24
Peak memory 218492 kb
Host smart-4d3015fb-2aec-4c18-84d8-15786398e57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851809605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2851809605
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.200352552
Short name T754
Test name
Test status
Simulation time 22039033 ps
CPU time 0.97 seconds
Started Jul 31 05:49:31 PM PDT 24
Finished Jul 31 05:49:32 PM PDT 24
Peak memory 215804 kb
Host smart-445ddb34-dd14-429f-ac2e-a85c70b666ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200352552 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.200352552
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3830638360
Short name T347
Test name
Test status
Simulation time 25226055 ps
CPU time 0.94 seconds
Started Jul 31 05:49:36 PM PDT 24
Finished Jul 31 05:49:37 PM PDT 24
Peak memory 215292 kb
Host smart-e8562a61-c5bd-42ba-bb8d-b1b9d09104db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830638360 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3830638360
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1579474704
Short name T912
Test name
Test status
Simulation time 728834559 ps
CPU time 4.54 seconds
Started Jul 31 05:49:28 PM PDT 24
Finished Jul 31 05:49:32 PM PDT 24
Peak memory 217040 kb
Host smart-432c8c4d-f5ea-4142-8a39-1f42fbb3c987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579474704 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1579474704
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2624898211
Short name T879
Test name
Test status
Simulation time 30808247323 ps
CPU time 351.57 seconds
Started Jul 31 05:49:20 PM PDT 24
Finished Jul 31 05:55:12 PM PDT 24
Peak memory 218892 kb
Host smart-f6e9b155-6709-4524-b88f-b53873bfe87c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624898211 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2624898211
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert_test.853821888
Short name T380
Test name
Test status
Simulation time 150790944 ps
CPU time 0.94 seconds
Started Jul 31 05:49:30 PM PDT 24
Finished Jul 31 05:49:31 PM PDT 24
Peak memory 206688 kb
Host smart-afa6d977-cdf5-43d2-8890-54305783c5aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853821888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.853821888
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1050642917
Short name T122
Test name
Test status
Simulation time 39319513 ps
CPU time 0.84 seconds
Started Jul 31 05:49:30 PM PDT 24
Finished Jul 31 05:49:31 PM PDT 24
Peak memory 216220 kb
Host smart-43d53269-decf-4b18-a695-823ecc00b939
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050642917 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1050642917
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1505135572
Short name T867
Test name
Test status
Simulation time 41990589 ps
CPU time 1.32 seconds
Started Jul 31 05:49:38 PM PDT 24
Finished Jul 31 05:49:39 PM PDT 24
Peak memory 216932 kb
Host smart-ccb57bb2-96c7-415b-80e9-a4464b7cabac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505135572 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1505135572
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3674175009
Short name T51
Test name
Test status
Simulation time 23270033 ps
CPU time 1.19 seconds
Started Jul 31 05:49:44 PM PDT 24
Finished Jul 31 05:49:45 PM PDT 24
Peak memory 224108 kb
Host smart-d1884317-3bfb-4f5a-87bc-09105c4e50b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674175009 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3674175009
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3569289630
Short name T863
Test name
Test status
Simulation time 41320002 ps
CPU time 1.64 seconds
Started Jul 31 05:49:39 PM PDT 24
Finished Jul 31 05:49:41 PM PDT 24
Peak memory 218604 kb
Host smart-4348dd59-f89b-4cae-8982-d0bd6c47d8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569289630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3569289630
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3218385968
Short name T742
Test name
Test status
Simulation time 21945318 ps
CPU time 1.15 seconds
Started Jul 31 05:49:40 PM PDT 24
Finished Jul 31 05:49:41 PM PDT 24
Peak memory 215512 kb
Host smart-08abbe51-bd03-43e5-a0ae-6615b0a38191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218385968 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3218385968
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2095229014
Short name T880
Test name
Test status
Simulation time 27735152 ps
CPU time 0.94 seconds
Started Jul 31 05:49:37 PM PDT 24
Finished Jul 31 05:49:38 PM PDT 24
Peak memory 215280 kb
Host smart-79d06938-b9a8-4b22-89c5-cf643ab48d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095229014 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2095229014
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.4049009945
Short name T45
Test name
Test status
Simulation time 116371480 ps
CPU time 1.83 seconds
Started Jul 31 05:49:33 PM PDT 24
Finished Jul 31 05:49:35 PM PDT 24
Peak memory 215172 kb
Host smart-ec67346b-aac9-41c2-8db4-a8af6b5050eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049009945 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.4049009945
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1316745592
Short name T314
Test name
Test status
Simulation time 186665360259 ps
CPU time 587.55 seconds
Started Jul 31 05:49:32 PM PDT 24
Finished Jul 31 05:59:20 PM PDT 24
Peak memory 220864 kb
Host smart-043f410c-64bf-45ca-9caa-cfb1840074b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316745592 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1316745592
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert_test.3286205049
Short name T495
Test name
Test status
Simulation time 42452450 ps
CPU time 0.88 seconds
Started Jul 31 05:49:28 PM PDT 24
Finished Jul 31 05:49:28 PM PDT 24
Peak memory 214780 kb
Host smart-279f7154-99cc-486f-94d3-530b5f9877ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286205049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3286205049
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1878604943
Short name T936
Test name
Test status
Simulation time 37955054 ps
CPU time 0.9 seconds
Started Jul 31 05:49:38 PM PDT 24
Finished Jul 31 05:49:39 PM PDT 24
Peak memory 216228 kb
Host smart-fa832343-2bd7-45f4-a7b7-56301a4e256d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878604943 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1878604943
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.4032332048
Short name T735
Test name
Test status
Simulation time 44956322 ps
CPU time 1.37 seconds
Started Jul 31 05:49:29 PM PDT 24
Finished Jul 31 05:49:30 PM PDT 24
Peak memory 216776 kb
Host smart-e357127a-a233-4366-9a8c-fba7b9cd0d1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032332048 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.4032332048
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3666128800
Short name T155
Test name
Test status
Simulation time 57621363 ps
CPU time 0.98 seconds
Started Jul 31 05:49:46 PM PDT 24
Finished Jul 31 05:49:48 PM PDT 24
Peak memory 220564 kb
Host smart-665b920d-a7f8-4f90-9d58-7565887a9c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666128800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3666128800
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1363255188
Short name T898
Test name
Test status
Simulation time 43681706 ps
CPU time 1.49 seconds
Started Jul 31 05:49:27 PM PDT 24
Finished Jul 31 05:49:33 PM PDT 24
Peak memory 219864 kb
Host smart-a340436b-2e47-408a-aea1-d83ff0c81002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363255188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1363255188
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2325354020
Short name T634
Test name
Test status
Simulation time 29716818 ps
CPU time 0.94 seconds
Started Jul 31 05:49:37 PM PDT 24
Finished Jul 31 05:49:38 PM PDT 24
Peak memory 215560 kb
Host smart-95b36104-b040-4ccd-86bd-0779f4945cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325354020 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2325354020
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.943414241
Short name T440
Test name
Test status
Simulation time 29704874 ps
CPU time 0.92 seconds
Started Jul 31 05:49:43 PM PDT 24
Finished Jul 31 05:49:44 PM PDT 24
Peak memory 215308 kb
Host smart-0d259a86-f96e-440e-b5c8-a012a164098a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943414241 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.943414241
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2315398161
Short name T857
Test name
Test status
Simulation time 207127314 ps
CPU time 4.61 seconds
Started Jul 31 05:49:32 PM PDT 24
Finished Jul 31 05:49:37 PM PDT 24
Peak memory 217396 kb
Host smart-a69f684e-c76d-4ebb-85ef-dc9c349dd698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315398161 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2315398161
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3325884884
Short name T240
Test name
Test status
Simulation time 179506145748 ps
CPU time 1126.07 seconds
Started Jul 31 05:49:45 PM PDT 24
Finished Jul 31 06:08:31 PM PDT 24
Peak memory 221488 kb
Host smart-9d8494df-8fde-492b-9bf2-ece9162e82e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325884884 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3325884884
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.111913885
Short name T175
Test name
Test status
Simulation time 51125077 ps
CPU time 1.21 seconds
Started Jul 31 05:49:42 PM PDT 24
Finished Jul 31 05:49:43 PM PDT 24
Peak memory 221464 kb
Host smart-366ee2b5-f1c2-4ee6-becb-8233a0dec2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111913885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.111913885
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1975834499
Short name T483
Test name
Test status
Simulation time 45341803 ps
CPU time 1.44 seconds
Started Jul 31 05:49:35 PM PDT 24
Finished Jul 31 05:49:37 PM PDT 24
Peak memory 214972 kb
Host smart-1d983314-bba9-4f73-a51c-e6406dff1575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975834499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1975834499
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2690041994
Short name T359
Test name
Test status
Simulation time 44533253 ps
CPU time 1.36 seconds
Started Jul 31 05:49:51 PM PDT 24
Finished Jul 31 05:49:52 PM PDT 24
Peak memory 216924 kb
Host smart-cdbed5bf-2bc2-4008-ba72-14604d00a9be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690041994 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2690041994
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1286527053
Short name T182
Test name
Test status
Simulation time 26351842 ps
CPU time 1.12 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 229600 kb
Host smart-76794870-982f-41a2-87c1-47fbba7afadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286527053 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1286527053
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.4173868226
Short name T419
Test name
Test status
Simulation time 54750240 ps
CPU time 1.06 seconds
Started Jul 31 05:49:38 PM PDT 24
Finished Jul 31 05:49:39 PM PDT 24
Peak memory 217324 kb
Host smart-e8134ad1-be29-4124-b0d3-8be25c815ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173868226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.4173868226
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3380690667
Short name T585
Test name
Test status
Simulation time 28391512 ps
CPU time 0.99 seconds
Started Jul 31 05:49:37 PM PDT 24
Finished Jul 31 05:49:38 PM PDT 24
Peak memory 215504 kb
Host smart-82803d9c-ad20-425a-986a-1abbe1a3b82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380690667 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3380690667
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3207934467
Short name T712
Test name
Test status
Simulation time 16348291 ps
CPU time 0.92 seconds
Started Jul 31 05:49:42 PM PDT 24
Finished Jul 31 05:49:43 PM PDT 24
Peak memory 215304 kb
Host smart-977f472e-377e-4a60-a77f-c29ea851f5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207934467 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3207934467
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3377731084
Short name T962
Test name
Test status
Simulation time 143289156 ps
CPU time 1.97 seconds
Started Jul 31 05:49:38 PM PDT 24
Finished Jul 31 05:49:40 PM PDT 24
Peak memory 207236 kb
Host smart-f65518df-7560-4c61-872c-90239e686826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377731084 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3377731084
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.127238284
Short name T639
Test name
Test status
Simulation time 356287880970 ps
CPU time 1017.78 seconds
Started Jul 31 05:49:44 PM PDT 24
Finished Jul 31 06:06:42 PM PDT 24
Peak memory 222528 kb
Host smart-fec0f1e7-fea7-4d4e-abb9-581dc7edc664
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127238284 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.127238284
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3900379843
Short name T702
Test name
Test status
Simulation time 309416753 ps
CPU time 1.22 seconds
Started Jul 31 05:49:42 PM PDT 24
Finished Jul 31 05:49:43 PM PDT 24
Peak memory 219604 kb
Host smart-1f7d4ede-ac78-48e6-bf4d-d059489a9aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900379843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3900379843
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2932073386
Short name T561
Test name
Test status
Simulation time 37396174 ps
CPU time 1.24 seconds
Started Jul 31 05:49:40 PM PDT 24
Finished Jul 31 05:49:41 PM PDT 24
Peak memory 206920 kb
Host smart-c1fc3a00-bd86-4a13-b770-35e7f64ce701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932073386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2932073386
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1696165874
Short name T549
Test name
Test status
Simulation time 10718501 ps
CPU time 0.85 seconds
Started Jul 31 05:49:46 PM PDT 24
Finished Jul 31 05:49:47 PM PDT 24
Peak memory 216244 kb
Host smart-c33c36ad-b160-4ba9-b9d6-c11c89c57774
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696165874 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1696165874
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3085483094
Short name T699
Test name
Test status
Simulation time 48859120 ps
CPU time 1.13 seconds
Started Jul 31 05:49:34 PM PDT 24
Finished Jul 31 05:49:35 PM PDT 24
Peak memory 217136 kb
Host smart-4d7de544-d1c2-4f8b-8f9f-5ee01015151e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085483094 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3085483094
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3453781395
Short name T167
Test name
Test status
Simulation time 26036473 ps
CPU time 1.34 seconds
Started Jul 31 05:49:46 PM PDT 24
Finished Jul 31 05:49:47 PM PDT 24
Peak memory 229640 kb
Host smart-a712bddb-4773-49dd-9c44-d2f9e8979fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453781395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3453781395
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2349748517
Short name T706
Test name
Test status
Simulation time 168577070 ps
CPU time 1.23 seconds
Started Jul 31 05:49:41 PM PDT 24
Finished Jul 31 05:49:42 PM PDT 24
Peak memory 219876 kb
Host smart-b0db3fda-c193-4666-bdf8-39d7406a5114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349748517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2349748517
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3289378638
Short name T96
Test name
Test status
Simulation time 67016618 ps
CPU time 0.8 seconds
Started Jul 31 05:49:44 PM PDT 24
Finished Jul 31 05:49:45 PM PDT 24
Peak memory 215532 kb
Host smart-5861abc9-5c97-4ca0-9c29-a7b0860c908d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289378638 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3289378638
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.2046816722
Short name T451
Test name
Test status
Simulation time 23012387 ps
CPU time 0.92 seconds
Started Jul 31 05:49:45 PM PDT 24
Finished Jul 31 05:49:46 PM PDT 24
Peak memory 215268 kb
Host smart-a392278c-a778-42b7-bc63-8448589eb00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046816722 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2046816722
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3266890317
Short name T1
Test name
Test status
Simulation time 156442781 ps
CPU time 1.31 seconds
Started Jul 31 05:49:45 PM PDT 24
Finished Jul 31 05:49:46 PM PDT 24
Peak memory 207216 kb
Host smart-f1afe94b-366a-4703-b42b-c90fd1c1e8f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266890317 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3266890317
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.108622453
Short name T381
Test name
Test status
Simulation time 6930263462 ps
CPU time 153.47 seconds
Started Jul 31 05:49:40 PM PDT 24
Finished Jul 31 05:52:13 PM PDT 24
Peak memory 221736 kb
Host smart-09530632-5edd-4cdd-8134-0f4d3c9e54e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108622453 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.108622453
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3022871091
Short name T748
Test name
Test status
Simulation time 31472376 ps
CPU time 1.35 seconds
Started Jul 31 05:49:43 PM PDT 24
Finished Jul 31 05:49:45 PM PDT 24
Peak memory 219712 kb
Host smart-b2e4517c-a2e0-44af-a878-19201daa56cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022871091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3022871091
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3007011654
Short name T704
Test name
Test status
Simulation time 11387030 ps
CPU time 0.85 seconds
Started Jul 31 05:49:32 PM PDT 24
Finished Jul 31 05:49:33 PM PDT 24
Peak memory 206716 kb
Host smart-b1e7babb-8e6b-42f8-93a6-0a83e459077c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007011654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3007011654
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.299024080
Short name T941
Test name
Test status
Simulation time 162450995 ps
CPU time 1.06 seconds
Started Jul 31 05:49:55 PM PDT 24
Finished Jul 31 05:49:56 PM PDT 24
Peak memory 217100 kb
Host smart-be45053a-e6ee-4e1f-8302-663b182b4700
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299024080 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.299024080
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.357445004
Short name T978
Test name
Test status
Simulation time 70066380 ps
CPU time 0.84 seconds
Started Jul 31 05:49:38 PM PDT 24
Finished Jul 31 05:49:39 PM PDT 24
Peak memory 218392 kb
Host smart-3fa841a3-0019-4f90-bbaf-01d88b9d8065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357445004 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.357445004
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3256082644
Short name T464
Test name
Test status
Simulation time 46398624 ps
CPU time 1.54 seconds
Started Jul 31 05:49:51 PM PDT 24
Finished Jul 31 05:49:53 PM PDT 24
Peak memory 218640 kb
Host smart-c7aeed98-f562-4bd8-9887-b841839ba846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256082644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3256082644
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.4090427094
Short name T82
Test name
Test status
Simulation time 24600580 ps
CPU time 0.92 seconds
Started Jul 31 05:49:49 PM PDT 24
Finished Jul 31 05:49:50 PM PDT 24
Peak memory 215816 kb
Host smart-40447bc1-567b-4226-9fc2-d2ccd97803c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090427094 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.4090427094
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1635360395
Short name T510
Test name
Test status
Simulation time 25356477 ps
CPU time 0.95 seconds
Started Jul 31 05:49:46 PM PDT 24
Finished Jul 31 05:49:47 PM PDT 24
Peak memory 215268 kb
Host smart-4402c0ed-6434-4e87-9cc1-c7ab609be32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635360395 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1635360395
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3309647392
Short name T550
Test name
Test status
Simulation time 133573870 ps
CPU time 2.9 seconds
Started Jul 31 05:49:39 PM PDT 24
Finished Jul 31 05:49:42 PM PDT 24
Peak memory 217252 kb
Host smart-19870de1-fb03-4ccd-942c-fdffd2e1d5e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309647392 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3309647392
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1784808913
Short name T839
Test name
Test status
Simulation time 181058250792 ps
CPU time 1919.1 seconds
Started Jul 31 05:49:38 PM PDT 24
Finished Jul 31 06:21:37 PM PDT 24
Peak memory 227172 kb
Host smart-f2846a90-c3b6-4235-9f0a-18c8843f676a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784808913 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1784808913
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1260977172
Short name T217
Test name
Test status
Simulation time 130231581 ps
CPU time 1.23 seconds
Started Jul 31 05:49:00 PM PDT 24
Finished Jul 31 05:49:02 PM PDT 24
Peak memory 218744 kb
Host smart-0aa2e86e-f5bb-4970-bfbc-fe9b307adacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260977172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1260977172
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2040409603
Short name T407
Test name
Test status
Simulation time 17828172 ps
CPU time 0.81 seconds
Started Jul 31 05:49:00 PM PDT 24
Finished Jul 31 05:49:01 PM PDT 24
Peak memory 206744 kb
Host smart-356962a2-8fdc-490f-b800-bf20a7d8774f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040409603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2040409603
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.227165741
Short name T572
Test name
Test status
Simulation time 32572674 ps
CPU time 0.85 seconds
Started Jul 31 05:48:48 PM PDT 24
Finished Jul 31 05:48:49 PM PDT 24
Peak memory 215872 kb
Host smart-20662adc-3bed-4678-bb30-4316cb905aa0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227165741 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.227165741
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.3864924958
Short name T198
Test name
Test status
Simulation time 22386565 ps
CPU time 0.89 seconds
Started Jul 31 05:48:56 PM PDT 24
Finished Jul 31 05:48:57 PM PDT 24
Peak memory 218476 kb
Host smart-b338c332-0381-4a29-b86d-60408b7f12a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864924958 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3864924958
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2279256977
Short name T548
Test name
Test status
Simulation time 30039983 ps
CPU time 1.24 seconds
Started Jul 31 05:48:55 PM PDT 24
Finished Jul 31 05:48:57 PM PDT 24
Peak memory 217208 kb
Host smart-32ba68d3-528e-4fd3-9afa-af8ceb32823a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279256977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2279256977
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2335456069
Short name T810
Test name
Test status
Simulation time 26598907 ps
CPU time 1.01 seconds
Started Jul 31 05:48:51 PM PDT 24
Finished Jul 31 05:48:52 PM PDT 24
Peak memory 215540 kb
Host smart-019690a0-21cc-4ffa-bdac-fb4c7e1dd137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335456069 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2335456069
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2413108766
Short name T740
Test name
Test status
Simulation time 17260679 ps
CPU time 0.99 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:14 PM PDT 24
Peak memory 207112 kb
Host smart-26a2c26d-2752-4c2b-9b1f-7ca7b033d10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413108766 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2413108766
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.1598787854
Short name T443
Test name
Test status
Simulation time 19751022 ps
CPU time 0.99 seconds
Started Jul 31 05:48:53 PM PDT 24
Finished Jul 31 05:48:54 PM PDT 24
Peak memory 215252 kb
Host smart-cdf60cee-e684-4b2b-9f06-679c3569b5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598787854 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1598787854
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.58152283
Short name T675
Test name
Test status
Simulation time 276643740 ps
CPU time 5.28 seconds
Started Jul 31 05:49:01 PM PDT 24
Finished Jul 31 05:49:06 PM PDT 24
Peak memory 215300 kb
Host smart-c8735064-4199-497a-ba12-5dab9d58f462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58152283 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.58152283
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3217588986
Short name T774
Test name
Test status
Simulation time 92251824813 ps
CPU time 2124.5 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 06:24:33 PM PDT 24
Peak memory 226184 kb
Host smart-43e3023b-b3ae-4ac5-bc37-83b06acb9ebd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217588986 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3217588986
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2217576597
Short name T389
Test name
Test status
Simulation time 28417253 ps
CPU time 1.23 seconds
Started Jul 31 05:49:48 PM PDT 24
Finished Jul 31 05:49:49 PM PDT 24
Peak memory 219776 kb
Host smart-a6e7d7b9-d822-4659-809d-bcaba18a74fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217576597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2217576597
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3087679173
Short name T975
Test name
Test status
Simulation time 42025945 ps
CPU time 0.86 seconds
Started Jul 31 05:49:49 PM PDT 24
Finished Jul 31 05:49:50 PM PDT 24
Peak memory 206716 kb
Host smart-3d693fdd-1d69-43f0-9f20-6ebe2ffb4d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087679173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3087679173
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2254748981
Short name T733
Test name
Test status
Simulation time 38445551 ps
CPU time 0.89 seconds
Started Jul 31 05:49:46 PM PDT 24
Finished Jul 31 05:49:47 PM PDT 24
Peak memory 216148 kb
Host smart-d780bcd8-3e27-4c8c-bca6-db12c95c2601
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254748981 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2254748981
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2669789607
Short name T918
Test name
Test status
Simulation time 33193339 ps
CPU time 1.16 seconds
Started Jul 31 05:49:47 PM PDT 24
Finished Jul 31 05:49:48 PM PDT 24
Peak memory 218312 kb
Host smart-e8ea8059-5e05-49d4-afd0-69483cb9022d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669789607 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2669789607
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1294031355
Short name T954
Test name
Test status
Simulation time 32926525 ps
CPU time 0.96 seconds
Started Jul 31 05:49:52 PM PDT 24
Finished Jul 31 05:49:53 PM PDT 24
Peak memory 223764 kb
Host smart-29ed403d-9d03-4a54-bc57-487755d1d547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294031355 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1294031355
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_intr.505866934
Short name T98
Test name
Test status
Simulation time 30773718 ps
CPU time 0.9 seconds
Started Jul 31 05:49:41 PM PDT 24
Finished Jul 31 05:49:42 PM PDT 24
Peak memory 215772 kb
Host smart-f33b1e31-af04-4d71-b666-3fa1f24ed398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505866934 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.505866934
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1706708820
Short name T781
Test name
Test status
Simulation time 41336700 ps
CPU time 0.93 seconds
Started Jul 31 05:49:49 PM PDT 24
Finished Jul 31 05:49:50 PM PDT 24
Peak memory 215404 kb
Host smart-629cfd65-7307-438d-a6f3-4124138651ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706708820 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1706708820
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3089781300
Short name T349
Test name
Test status
Simulation time 96753445 ps
CPU time 1.37 seconds
Started Jul 31 05:49:45 PM PDT 24
Finished Jul 31 05:49:46 PM PDT 24
Peak memory 215288 kb
Host smart-af90508b-7b32-4a9e-a022-e40fa1c6d019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089781300 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3089781300
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2456443654
Short name T888
Test name
Test status
Simulation time 182974233690 ps
CPU time 2196.9 seconds
Started Jul 31 05:49:45 PM PDT 24
Finished Jul 31 06:26:22 PM PDT 24
Peak memory 227084 kb
Host smart-70c33136-c2fe-411a-85c5-ea30590156c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456443654 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2456443654
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert_test.1981712805
Short name T776
Test name
Test status
Simulation time 41969180 ps
CPU time 0.91 seconds
Started Jul 31 05:49:50 PM PDT 24
Finished Jul 31 05:49:51 PM PDT 24
Peak memory 206728 kb
Host smart-5abfb6e0-4b24-47f9-9627-43d3e3a85eff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981712805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1981712805
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1432021975
Short name T927
Test name
Test status
Simulation time 16349598 ps
CPU time 0.82 seconds
Started Jul 31 05:49:50 PM PDT 24
Finished Jul 31 05:49:50 PM PDT 24
Peak memory 215916 kb
Host smart-5ef0f747-bafc-406d-adfa-0d5f999f8efe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432021975 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1432021975
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.4129399801
Short name T62
Test name
Test status
Simulation time 45236399 ps
CPU time 1.11 seconds
Started Jul 31 05:49:45 PM PDT 24
Finished Jul 31 05:49:46 PM PDT 24
Peak memory 216796 kb
Host smart-52ae9e9a-c43e-4ccf-b192-f9935a263d31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129399801 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.4129399801
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.488486146
Short name T151
Test name
Test status
Simulation time 25250314 ps
CPU time 1.26 seconds
Started Jul 31 05:49:45 PM PDT 24
Finished Jul 31 05:49:46 PM PDT 24
Peak memory 219936 kb
Host smart-32448b65-f2c6-4299-a776-f9091d1b6a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488486146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.488486146
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2226131082
Short name T608
Test name
Test status
Simulation time 44516979 ps
CPU time 1.74 seconds
Started Jul 31 05:49:50 PM PDT 24
Finished Jul 31 05:49:52 PM PDT 24
Peak memory 217308 kb
Host smart-1e3ffd24-a3dc-4ce4-80e6-87f6106e2b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226131082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2226131082
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.999699132
Short name T800
Test name
Test status
Simulation time 40635066 ps
CPU time 1 seconds
Started Jul 31 05:49:49 PM PDT 24
Finished Jul 31 05:49:50 PM PDT 24
Peak memory 224032 kb
Host smart-3089fcd9-d821-4b37-a638-8d1f68d1e1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999699132 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.999699132
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2103738572
Short name T356
Test name
Test status
Simulation time 39878946 ps
CPU time 0.85 seconds
Started Jul 31 05:49:49 PM PDT 24
Finished Jul 31 05:49:50 PM PDT 24
Peak memory 215300 kb
Host smart-33d67b27-0825-4601-88b2-c389126db74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103738572 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2103738572
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1196384270
Short name T245
Test name
Test status
Simulation time 314720132 ps
CPU time 5.73 seconds
Started Jul 31 05:49:45 PM PDT 24
Finished Jul 31 05:49:51 PM PDT 24
Peak memory 218652 kb
Host smart-edc4b575-01e6-4553-8372-b477be6e4ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196384270 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1196384270
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1547636441
Short name T230
Test name
Test status
Simulation time 225167136190 ps
CPU time 1287.28 seconds
Started Jul 31 05:49:53 PM PDT 24
Finished Jul 31 06:11:21 PM PDT 24
Peak memory 223668 kb
Host smart-705bf18b-5534-4592-a0fe-49a89437eace
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547636441 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1547636441
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1195648765
Short name T614
Test name
Test status
Simulation time 51409260 ps
CPU time 1.21 seconds
Started Jul 31 05:49:43 PM PDT 24
Finished Jul 31 05:49:45 PM PDT 24
Peak memory 220528 kb
Host smart-cab932db-f9ea-49f0-a79e-02b8417c3884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195648765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1195648765
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.77577543
Short name T342
Test name
Test status
Simulation time 19850025 ps
CPU time 1.02 seconds
Started Jul 31 05:49:52 PM PDT 24
Finished Jul 31 05:49:54 PM PDT 24
Peak memory 206760 kb
Host smart-13c0cc66-1276-445e-831e-8bbf4343675b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77577543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.77577543
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2280795090
Short name T845
Test name
Test status
Simulation time 10393352 ps
CPU time 0.85 seconds
Started Jul 31 05:49:41 PM PDT 24
Finished Jul 31 05:49:42 PM PDT 24
Peak memory 216348 kb
Host smart-c6b97e62-26d1-45d6-bf82-65977e075aa0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280795090 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2280795090
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3883331582
Short name T537
Test name
Test status
Simulation time 102310213 ps
CPU time 1.32 seconds
Started Jul 31 05:49:47 PM PDT 24
Finished Jul 31 05:49:48 PM PDT 24
Peak memory 216996 kb
Host smart-494c1644-f84e-4987-b978-351c937768d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883331582 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3883331582
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.4241453811
Short name T986
Test name
Test status
Simulation time 44828578 ps
CPU time 1.22 seconds
Started Jul 31 05:49:50 PM PDT 24
Finished Jul 31 05:49:51 PM PDT 24
Peak memory 225696 kb
Host smart-79adfbec-7e1c-4c1a-bda4-330bd3a4189c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241453811 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.4241453811
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2109008793
Short name T930
Test name
Test status
Simulation time 78358494 ps
CPU time 1.31 seconds
Started Jul 31 05:49:44 PM PDT 24
Finished Jul 31 05:49:46 PM PDT 24
Peak memory 218732 kb
Host smart-23e38efc-0047-47f0-8841-9503c0f050f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109008793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2109008793
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3725563852
Short name T937
Test name
Test status
Simulation time 21341001 ps
CPU time 1.18 seconds
Started Jul 31 05:49:50 PM PDT 24
Finished Jul 31 05:49:51 PM PDT 24
Peak memory 215372 kb
Host smart-162324e8-8f21-4e4f-afba-fbbb3a426d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725563852 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3725563852
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.4205440939
Short name T337
Test name
Test status
Simulation time 31261636 ps
CPU time 0.93 seconds
Started Jul 31 05:49:51 PM PDT 24
Finished Jul 31 05:49:52 PM PDT 24
Peak memory 215288 kb
Host smart-e4610f9a-30bd-42e0-8c11-f7395a75e4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205440939 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.4205440939
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.445434014
Short name T786
Test name
Test status
Simulation time 529769589 ps
CPU time 5.4 seconds
Started Jul 31 05:49:46 PM PDT 24
Finished Jul 31 05:49:51 PM PDT 24
Peak memory 217092 kb
Host smart-3bb9bb6c-fc00-451e-b43a-e069a634cc2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445434014 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.445434014
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.229734986
Short name T772
Test name
Test status
Simulation time 30986878164 ps
CPU time 679.33 seconds
Started Jul 31 05:49:48 PM PDT 24
Finished Jul 31 06:01:08 PM PDT 24
Peak memory 218192 kb
Host smart-165d00fe-4ec6-42f0-89dd-c7d27bd6d4b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229734986 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.229734986
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1210948061
Short name T899
Test name
Test status
Simulation time 104577569 ps
CPU time 1.28 seconds
Started Jul 31 05:49:47 PM PDT 24
Finished Jul 31 05:49:49 PM PDT 24
Peak memory 215696 kb
Host smart-a8212807-27d2-4560-9285-27fea4a0bac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210948061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1210948061
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.4031153329
Short name T720
Test name
Test status
Simulation time 50989971 ps
CPU time 0.94 seconds
Started Jul 31 05:49:53 PM PDT 24
Finished Jul 31 05:49:54 PM PDT 24
Peak memory 206604 kb
Host smart-f4ab4766-7f7a-4633-8ca3-fc839278ffbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031153329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.4031153329
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1836217987
Short name T199
Test name
Test status
Simulation time 23984235 ps
CPU time 0.86 seconds
Started Jul 31 05:49:50 PM PDT 24
Finished Jul 31 05:49:51 PM PDT 24
Peak memory 216324 kb
Host smart-10113b79-1d48-4a15-8c12-a66d67b37285
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836217987 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1836217987
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2394978560
Short name T711
Test name
Test status
Simulation time 63692450 ps
CPU time 1.13 seconds
Started Jul 31 05:49:48 PM PDT 24
Finished Jul 31 05:49:49 PM PDT 24
Peak memory 216920 kb
Host smart-0efce931-e7a7-406c-979b-cbb3e9970915
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394978560 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2394978560
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1913328886
Short name T147
Test name
Test status
Simulation time 27597835 ps
CPU time 0.96 seconds
Started Jul 31 05:49:48 PM PDT 24
Finished Jul 31 05:49:49 PM PDT 24
Peak memory 229440 kb
Host smart-2904fc00-c7d6-42bf-9054-43341143e2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913328886 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1913328886
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3541421870
Short name T633
Test name
Test status
Simulation time 82112095 ps
CPU time 1.09 seconds
Started Jul 31 05:49:51 PM PDT 24
Finished Jul 31 05:49:52 PM PDT 24
Peak memory 217400 kb
Host smart-a2a93f72-2509-44f3-bdde-9cbe45385c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541421870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3541421870
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2580017743
Short name T564
Test name
Test status
Simulation time 26687170 ps
CPU time 0.87 seconds
Started Jul 31 05:49:47 PM PDT 24
Finished Jul 31 05:49:48 PM PDT 24
Peak memory 215520 kb
Host smart-02c0a4bb-5097-42da-8f44-6cef8b5a17a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580017743 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2580017743
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3467603458
Short name T360
Test name
Test status
Simulation time 72815898 ps
CPU time 0.92 seconds
Started Jul 31 05:49:49 PM PDT 24
Finished Jul 31 05:49:50 PM PDT 24
Peak memory 215300 kb
Host smart-b0203030-93b8-42ae-871f-de4dfe5ddd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467603458 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3467603458
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2726861743
Short name T560
Test name
Test status
Simulation time 88397698 ps
CPU time 2.04 seconds
Started Jul 31 05:49:54 PM PDT 24
Finished Jul 31 05:49:56 PM PDT 24
Peak memory 217228 kb
Host smart-15d557e8-ff0a-45d7-86d2-94e5493ab334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726861743 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2726861743
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.4131216511
Short name T229
Test name
Test status
Simulation time 37166861056 ps
CPU time 429.32 seconds
Started Jul 31 05:49:51 PM PDT 24
Finished Jul 31 05:57:00 PM PDT 24
Peak memory 218124 kb
Host smart-340c67d1-30b6-4a4c-806d-7ef284eaec04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131216511 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.4131216511
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1329734486
Short name T606
Test name
Test status
Simulation time 38443721 ps
CPU time 1.2 seconds
Started Jul 31 05:49:51 PM PDT 24
Finished Jul 31 05:49:52 PM PDT 24
Peak memory 218492 kb
Host smart-2809b4ee-f6c9-4456-ba05-acee218bddf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329734486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1329734486
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.4210343736
Short name T581
Test name
Test status
Simulation time 176327754 ps
CPU time 0.92 seconds
Started Jul 31 05:49:46 PM PDT 24
Finished Jul 31 05:49:47 PM PDT 24
Peak memory 215168 kb
Host smart-24d19ad4-b003-4969-821d-17de74f3da6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210343736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.4210343736
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2014019888
Short name T536
Test name
Test status
Simulation time 12724052 ps
CPU time 0.88 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 215992 kb
Host smart-afb4518a-42ea-4ec8-bb23-31a069f65b83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014019888 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2014019888
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3076926105
Short name T118
Test name
Test status
Simulation time 34320285 ps
CPU time 1.22 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 219816 kb
Host smart-f1f9442b-b5cc-4221-8309-f07fc1fe2ca8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076926105 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3076926105
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.4040060614
Short name T693
Test name
Test status
Simulation time 32766286 ps
CPU time 0.96 seconds
Started Jul 31 05:49:56 PM PDT 24
Finished Jul 31 05:49:57 PM PDT 24
Peak memory 219948 kb
Host smart-d8fbf238-d8ea-4d2d-b90a-ef1abc31e6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040060614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.4040060614
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1620435461
Short name T588
Test name
Test status
Simulation time 51485283 ps
CPU time 1.23 seconds
Started Jul 31 05:49:44 PM PDT 24
Finished Jul 31 05:49:45 PM PDT 24
Peak memory 218480 kb
Host smart-49b290fb-1fb9-4cea-8d04-44a8ecf9d3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620435461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1620435461
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1044368387
Short name T80
Test name
Test status
Simulation time 44035915 ps
CPU time 0.87 seconds
Started Jul 31 05:49:50 PM PDT 24
Finished Jul 31 05:49:51 PM PDT 24
Peak memory 215700 kb
Host smart-572281f1-1650-4083-811c-c442d0ec83e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044368387 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1044368387
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.107756416
Short name T55
Test name
Test status
Simulation time 42786720 ps
CPU time 0.89 seconds
Started Jul 31 05:49:51 PM PDT 24
Finished Jul 31 05:49:52 PM PDT 24
Peak memory 215308 kb
Host smart-c7ddc61d-ffe7-4459-aee6-8e6f60a6bda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107756416 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.107756416
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2296206604
Short name T313
Test name
Test status
Simulation time 297349486 ps
CPU time 6.02 seconds
Started Jul 31 05:49:51 PM PDT 24
Finished Jul 31 05:49:57 PM PDT 24
Peak memory 217204 kb
Host smart-e936da65-036a-46b2-b850-e2584a34a662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296206604 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2296206604
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1857173669
Short name T237
Test name
Test status
Simulation time 147955436976 ps
CPU time 873.45 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 06:04:34 PM PDT 24
Peak memory 221600 kb
Host smart-c45aab09-dad2-4724-80f3-d3a29d26ab52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857173669 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1857173669
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2453892556
Short name T661
Test name
Test status
Simulation time 276344546 ps
CPU time 1.16 seconds
Started Jul 31 05:49:56 PM PDT 24
Finished Jul 31 05:49:57 PM PDT 24
Peak memory 218288 kb
Host smart-4598b536-d8d6-411b-afdd-8253f7c6d221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453892556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2453892556
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1254017297
Short name T988
Test name
Test status
Simulation time 44835276 ps
CPU time 0.89 seconds
Started Jul 31 05:49:52 PM PDT 24
Finished Jul 31 05:49:53 PM PDT 24
Peak memory 214864 kb
Host smart-90af72d8-38bd-4831-982e-f96f8c595c0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254017297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1254017297
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1780559423
Short name T478
Test name
Test status
Simulation time 28682660 ps
CPU time 0.84 seconds
Started Jul 31 05:49:47 PM PDT 24
Finished Jul 31 05:49:48 PM PDT 24
Peak memory 215940 kb
Host smart-5609be8b-80e9-4301-8496-f350458b4570
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780559423 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1780559423
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3699460682
Short name T907
Test name
Test status
Simulation time 215901654 ps
CPU time 1.14 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 216668 kb
Host smart-130860e8-ce6e-4a57-8fc2-9cb97a2b2e01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699460682 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3699460682
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3482855780
Short name T503
Test name
Test status
Simulation time 18732416 ps
CPU time 1.03 seconds
Started Jul 31 05:49:57 PM PDT 24
Finished Jul 31 05:49:58 PM PDT 24
Peak memory 218324 kb
Host smart-01b805fe-27d4-421f-8228-db7f9dd62347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482855780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3482855780
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3133510130
Short name T438
Test name
Test status
Simulation time 36208851 ps
CPU time 1.34 seconds
Started Jul 31 05:49:56 PM PDT 24
Finished Jul 31 05:49:58 PM PDT 24
Peak memory 218336 kb
Host smart-7fceb3b7-948f-4071-b972-e0a97b2a9031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133510130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3133510130
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3209732197
Short name T83
Test name
Test status
Simulation time 22735460 ps
CPU time 0.92 seconds
Started Jul 31 05:50:02 PM PDT 24
Finished Jul 31 05:50:03 PM PDT 24
Peak memory 215752 kb
Host smart-bc8fc1a2-d40e-47e8-aa40-d9f394493631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209732197 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3209732197
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1184168511
Short name T977
Test name
Test status
Simulation time 35189607 ps
CPU time 0.92 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 215232 kb
Host smart-6b38f1b0-d7a3-4b3c-93c4-eb5cd3f3d5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184168511 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1184168511
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.4096873316
Short name T713
Test name
Test status
Simulation time 116437904 ps
CPU time 2.6 seconds
Started Jul 31 05:49:48 PM PDT 24
Finished Jul 31 05:49:51 PM PDT 24
Peak memory 217320 kb
Host smart-fe20d2fc-3299-46a7-9e50-cba7d30aa242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096873316 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.4096873316
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3604356630
Short name T26
Test name
Test status
Simulation time 100988260241 ps
CPU time 812.48 seconds
Started Jul 31 05:49:53 PM PDT 24
Finished Jul 31 06:03:26 PM PDT 24
Peak memory 220500 kb
Host smart-b8290ed9-c6de-45b5-b401-1684e57796f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604356630 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3604356630
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2265787431
Short name T491
Test name
Test status
Simulation time 107640317 ps
CPU time 1.16 seconds
Started Jul 31 05:49:51 PM PDT 24
Finished Jul 31 05:49:53 PM PDT 24
Peak memory 220736 kb
Host smart-dda0506e-f087-45c8-9902-7a6d4349ad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265787431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2265787431
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2296728312
Short name T61
Test name
Test status
Simulation time 130772863 ps
CPU time 1.2 seconds
Started Jul 31 05:49:49 PM PDT 24
Finished Jul 31 05:49:51 PM PDT 24
Peak memory 206852 kb
Host smart-56d153a4-5602-41e1-9256-a2671cafc912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296728312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2296728312
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.721993827
Short name T171
Test name
Test status
Simulation time 47853751 ps
CPU time 1.12 seconds
Started Jul 31 05:49:54 PM PDT 24
Finished Jul 31 05:49:56 PM PDT 24
Peak memory 218116 kb
Host smart-46cef233-a41a-4109-a742-707dea5565fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721993827 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.721993827
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.309560172
Short name T697
Test name
Test status
Simulation time 23546794 ps
CPU time 0.98 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 218692 kb
Host smart-18973a8a-4988-465a-821c-184d4443bc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309560172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.309560172
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2311825210
Short name T13
Test name
Test status
Simulation time 58703642 ps
CPU time 1.48 seconds
Started Jul 31 05:49:55 PM PDT 24
Finished Jul 31 05:49:56 PM PDT 24
Peak memory 219368 kb
Host smart-be01d87f-bb9b-4065-a373-fe30d0ba17bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311825210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2311825210
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3961248861
Short name T757
Test name
Test status
Simulation time 21496481 ps
CPU time 1.15 seconds
Started Jul 31 05:49:52 PM PDT 24
Finished Jul 31 05:49:53 PM PDT 24
Peak memory 215528 kb
Host smart-a1945108-7485-43f7-ac80-58bff6d3c10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961248861 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3961248861
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2304823031
Short name T928
Test name
Test status
Simulation time 17291092 ps
CPU time 1.01 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 207056 kb
Host smart-0730c16e-0c87-445a-aacd-46a0a2d7f56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304823031 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2304823031
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.167527301
Short name T904
Test name
Test status
Simulation time 807677984 ps
CPU time 5.4 seconds
Started Jul 31 05:49:51 PM PDT 24
Finished Jul 31 05:49:57 PM PDT 24
Peak memory 215264 kb
Host smart-120b89c5-85a4-40b3-b547-17cd4da9b2bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167527301 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.167527301
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.4155377241
Short name T59
Test name
Test status
Simulation time 231707705587 ps
CPU time 1628.5 seconds
Started Jul 31 05:49:51 PM PDT 24
Finished Jul 31 06:16:59 PM PDT 24
Peak memory 225848 kb
Host smart-421e516a-cf24-4d8f-a2b2-2ed99735249f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155377241 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.4155377241
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2833576653
Short name T21
Test name
Test status
Simulation time 34356694 ps
CPU time 1.27 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 218684 kb
Host smart-a449aa14-0385-48c8-9f00-ec9aea029b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833576653 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2833576653
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.749814232
Short name T520
Test name
Test status
Simulation time 35836854 ps
CPU time 0.79 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 206656 kb
Host smart-d3bbcf0c-b3ab-41b6-afc8-5c351a8ad4d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749814232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.749814232
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1616919510
Short name T948
Test name
Test status
Simulation time 21223541 ps
CPU time 0.9 seconds
Started Jul 31 05:49:44 PM PDT 24
Finished Jul 31 05:49:45 PM PDT 24
Peak memory 215956 kb
Host smart-70e29605-4567-43a0-b16b-2bf8e3e8de01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616919510 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1616919510
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.876895060
Short name T562
Test name
Test status
Simulation time 51608365 ps
CPU time 1.29 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 225608 kb
Host smart-bf771b73-26dd-4e9c-81ab-e7c3dacae784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876895060 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.876895060
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3368165395
Short name T710
Test name
Test status
Simulation time 164117379 ps
CPU time 1.08 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 217252 kb
Host smart-d89d4b1b-c2ae-4576-8fe7-858217a6bb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368165395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3368165395
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1839172528
Short name T87
Test name
Test status
Simulation time 26337619 ps
CPU time 1.01 seconds
Started Jul 31 05:49:53 PM PDT 24
Finished Jul 31 05:49:54 PM PDT 24
Peak memory 216716 kb
Host smart-59166d98-4862-4d06-9adf-1a5c7bec7cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839172528 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1839172528
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3904994949
Short name T502
Test name
Test status
Simulation time 39036302 ps
CPU time 0.87 seconds
Started Jul 31 05:49:51 PM PDT 24
Finished Jul 31 05:49:52 PM PDT 24
Peak memory 215252 kb
Host smart-5c769c0c-42ac-41d2-ae29-d2641883d756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904994949 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3904994949
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.781472461
Short name T807
Test name
Test status
Simulation time 714547805 ps
CPU time 4.08 seconds
Started Jul 31 05:49:57 PM PDT 24
Finished Jul 31 05:50:01 PM PDT 24
Peak memory 217272 kb
Host smart-1b96baa2-7f3a-4f13-b517-8047e4ecb6cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781472461 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.781472461
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.38008041
Short name T485
Test name
Test status
Simulation time 68463566377 ps
CPU time 428.11 seconds
Started Jul 31 05:49:56 PM PDT 24
Finished Jul 31 05:57:05 PM PDT 24
Peak memory 218444 kb
Host smart-83eaea5f-9186-4c81-a3d4-42455e64f718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38008041 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.38008041
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1101223245
Short name T185
Test name
Test status
Simulation time 241038112 ps
CPU time 1.24 seconds
Started Jul 31 05:49:49 PM PDT 24
Finished Jul 31 05:49:51 PM PDT 24
Peak memory 218504 kb
Host smart-b30b96b7-c9af-49f2-94e9-e7e7a4d08aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101223245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1101223245
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3419267441
Short name T384
Test name
Test status
Simulation time 31819645 ps
CPU time 0.94 seconds
Started Jul 31 05:50:04 PM PDT 24
Finished Jul 31 05:50:05 PM PDT 24
Peak memory 206696 kb
Host smart-c6810651-0e95-41f4-9774-936d01e1f67f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419267441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3419267441
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2108687950
Short name T350
Test name
Test status
Simulation time 13980638 ps
CPU time 0.94 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:01 PM PDT 24
Peak memory 216400 kb
Host smart-c20131c8-7fee-4676-a4e8-29a4942bce90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108687950 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2108687950
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.4062252970
Short name T490
Test name
Test status
Simulation time 32425336 ps
CPU time 1.16 seconds
Started Jul 31 05:49:51 PM PDT 24
Finished Jul 31 05:49:53 PM PDT 24
Peak memory 218396 kb
Host smart-f8514f83-dcbc-414f-bfcf-ad8c19eb353b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062252970 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.4062252970
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.831444527
Short name T755
Test name
Test status
Simulation time 19189357 ps
CPU time 1.02 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 218356 kb
Host smart-9717899c-2c12-44df-8dcd-da8dec2bfff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831444527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.831444527
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3801010776
Short name T400
Test name
Test status
Simulation time 43420853 ps
CPU time 1.13 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 217212 kb
Host smart-f9c7b39a-d543-4d59-bdb8-3482241379d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801010776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3801010776
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1906164309
Short name T508
Test name
Test status
Simulation time 22287736 ps
CPU time 0.93 seconds
Started Jul 31 05:49:53 PM PDT 24
Finished Jul 31 05:49:54 PM PDT 24
Peak memory 215816 kb
Host smart-ffbcafd8-f3ad-4730-858b-9964aee57c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906164309 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1906164309
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2432998517
Short name T983
Test name
Test status
Simulation time 31416947 ps
CPU time 0.97 seconds
Started Jul 31 05:49:50 PM PDT 24
Finished Jul 31 05:49:51 PM PDT 24
Peak memory 215260 kb
Host smart-58050fbc-5ed3-47da-962c-f4cfd615b499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432998517 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2432998517
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3640764902
Short name T723
Test name
Test status
Simulation time 816620863 ps
CPU time 4.62 seconds
Started Jul 31 05:49:50 PM PDT 24
Finished Jul 31 05:49:55 PM PDT 24
Peak memory 215248 kb
Host smart-268dae6f-cd4c-4d0c-a812-e2941bdd4c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640764902 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3640764902
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.232596827
Short name T546
Test name
Test status
Simulation time 122111003729 ps
CPU time 733.43 seconds
Started Jul 31 05:49:57 PM PDT 24
Finished Jul 31 06:02:11 PM PDT 24
Peak memory 220044 kb
Host smart-e56e4f36-314a-4039-95fd-e05c6fe31091
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232596827 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.232596827
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.4007982618
Short name T422
Test name
Test status
Simulation time 42379638 ps
CPU time 1.17 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 218712 kb
Host smart-9cdca398-e48e-4597-bbd4-171fcbd2b414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007982618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.4007982618
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.56197525
Short name T728
Test name
Test status
Simulation time 13692675 ps
CPU time 0.87 seconds
Started Jul 31 05:50:05 PM PDT 24
Finished Jul 31 05:50:06 PM PDT 24
Peak memory 214816 kb
Host smart-7448a0e4-d039-42e7-b5a0-d66a2e3a1e4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56197525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.56197525
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3707565885
Short name T144
Test name
Test status
Simulation time 33867684 ps
CPU time 1.25 seconds
Started Jul 31 05:50:02 PM PDT 24
Finished Jul 31 05:50:03 PM PDT 24
Peak memory 216788 kb
Host smart-a33ebe77-49cd-4028-ab77-4204530c38b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707565885 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3707565885
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2945764023
Short name T870
Test name
Test status
Simulation time 33351907 ps
CPU time 0.99 seconds
Started Jul 31 05:54:53 PM PDT 24
Finished Jul 31 05:54:54 PM PDT 24
Peak memory 218900 kb
Host smart-d0049de9-4b48-4c06-826f-42b8fb81e606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945764023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2945764023
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1187490598
Short name T335
Test name
Test status
Simulation time 65779497 ps
CPU time 2.23 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 219632 kb
Host smart-7598fcc0-a845-456d-86dd-6d387be89d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187490598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1187490598
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3544391767
Short name T737
Test name
Test status
Simulation time 41650534 ps
CPU time 0.87 seconds
Started Jul 31 05:49:52 PM PDT 24
Finished Jul 31 05:49:53 PM PDT 24
Peak memory 215324 kb
Host smart-696283d6-98a1-4c16-b8e3-e3d5059f9ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544391767 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3544391767
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.604841932
Short name T446
Test name
Test status
Simulation time 47350979 ps
CPU time 0.88 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 215092 kb
Host smart-011ae903-389e-4b7b-9f41-ad3a2dd620d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604841932 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.604841932
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2860594382
Short name T119
Test name
Test status
Simulation time 247535307 ps
CPU time 4.93 seconds
Started Jul 31 05:50:05 PM PDT 24
Finished Jul 31 05:50:10 PM PDT 24
Peak memory 215276 kb
Host smart-749f3f93-cb49-476e-bb44-d52bd4ac56c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860594382 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2860594382
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1455138711
Short name T235
Test name
Test status
Simulation time 436633284569 ps
CPU time 984.04 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 06:06:26 PM PDT 24
Peak memory 223664 kb
Host smart-1d928f82-5be6-4127-9f88-41bb9fe7913b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455138711 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1455138711
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3297222096
Short name T432
Test name
Test status
Simulation time 98172182 ps
CPU time 1.32 seconds
Started Jul 31 05:49:02 PM PDT 24
Finished Jul 31 05:49:03 PM PDT 24
Peak memory 218576 kb
Host smart-5ad4530d-8649-4db5-8c56-29ed2b204da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297222096 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3297222096
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1896459156
Short name T569
Test name
Test status
Simulation time 30091586 ps
CPU time 0.93 seconds
Started Jul 31 05:48:56 PM PDT 24
Finished Jul 31 05:48:57 PM PDT 24
Peak memory 214424 kb
Host smart-03cd1ea3-8d12-43b7-80ea-6762be78a334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896459156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1896459156
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1575889654
Short name T866
Test name
Test status
Simulation time 34014743 ps
CPU time 0.82 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:04 PM PDT 24
Peak memory 215284 kb
Host smart-cd6d653f-8627-49ac-a4ff-63a577fc4457
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575889654 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1575889654
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.606608424
Short name T131
Test name
Test status
Simulation time 56887148 ps
CPU time 1.16 seconds
Started Jul 31 05:48:51 PM PDT 24
Finished Jul 31 05:48:52 PM PDT 24
Peak memory 216768 kb
Host smart-f6e7031d-44d6-451b-92e8-915e1ffbf342
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606608424 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.606608424
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3728171231
Short name T206
Test name
Test status
Simulation time 18250556 ps
CPU time 1.09 seconds
Started Jul 31 05:48:53 PM PDT 24
Finished Jul 31 05:48:54 PM PDT 24
Peak memory 218372 kb
Host smart-50595341-f5e1-43cb-852f-f716399307de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728171231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3728171231
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1088002861
Short name T487
Test name
Test status
Simulation time 89218909 ps
CPU time 1.52 seconds
Started Jul 31 05:49:06 PM PDT 24
Finished Jul 31 05:49:08 PM PDT 24
Peak memory 218768 kb
Host smart-b79fcc89-1ab5-4046-b5ca-47cd1f706377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088002861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1088002861
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.4080621364
Short name T646
Test name
Test status
Simulation time 21832985 ps
CPU time 1.23 seconds
Started Jul 31 05:48:59 PM PDT 24
Finished Jul 31 05:49:00 PM PDT 24
Peak memory 224052 kb
Host smart-e0dfd254-028d-43de-b1cb-fb727f29d2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080621364 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.4080621364
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2504818935
Short name T77
Test name
Test status
Simulation time 23582608 ps
CPU time 0.95 seconds
Started Jul 31 05:49:12 PM PDT 24
Finished Jul 31 05:49:13 PM PDT 24
Peak memory 207104 kb
Host smart-9a44970e-6593-4bfd-9c9f-cfbffb46ebcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504818935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2504818935
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2600320403
Short name T468
Test name
Test status
Simulation time 40043429 ps
CPU time 0.94 seconds
Started Jul 31 05:48:55 PM PDT 24
Finished Jul 31 05:48:56 PM PDT 24
Peak memory 215300 kb
Host smart-7346af44-8af2-47af-b21f-af9a94331f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600320403 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2600320403
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.417951719
Short name T486
Test name
Test status
Simulation time 247378383 ps
CPU time 5.17 seconds
Started Jul 31 05:49:00 PM PDT 24
Finished Jul 31 05:49:05 PM PDT 24
Peak memory 217388 kb
Host smart-0c168466-fe61-4590-a811-cf8129cc5817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417951719 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.417951719
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1584599086
Short name T465
Test name
Test status
Simulation time 17902091747 ps
CPU time 466.01 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:56:53 PM PDT 24
Peak memory 223612 kb
Host smart-9dc500f9-553a-4468-9ce0-3396886a5932
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584599086 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1584599086
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.929259087
Short name T454
Test name
Test status
Simulation time 23044611 ps
CPU time 1.1 seconds
Started Jul 31 05:49:56 PM PDT 24
Finished Jul 31 05:49:57 PM PDT 24
Peak memory 218528 kb
Host smart-4ef00b41-3794-4856-b195-d2d17ae2db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929259087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.929259087
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.131648237
Short name T179
Test name
Test status
Simulation time 57379270 ps
CPU time 0.94 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 219576 kb
Host smart-55e61928-d50b-4040-a7a5-d17fdf4a1853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131648237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.131648237
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1016705549
Short name T876
Test name
Test status
Simulation time 38393966 ps
CPU time 1.42 seconds
Started Jul 31 05:49:55 PM PDT 24
Finished Jul 31 05:49:56 PM PDT 24
Peak memory 217400 kb
Host smart-98e16bd1-42f9-4115-b83d-16f935524044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016705549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1016705549
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.399334746
Short name T896
Test name
Test status
Simulation time 29362363 ps
CPU time 1.23 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 218276 kb
Host smart-9ad3ce74-9849-47b6-a066-8048f75e9cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399334746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.399334746
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.3695731700
Short name T243
Test name
Test status
Simulation time 51338227 ps
CPU time 1.11 seconds
Started Jul 31 05:49:53 PM PDT 24
Finished Jul 31 05:49:55 PM PDT 24
Peak memory 219736 kb
Host smart-9e90d9de-d097-4e96-906b-49827d2905c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695731700 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3695731700
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1634653539
Short name T894
Test name
Test status
Simulation time 159700031 ps
CPU time 1.18 seconds
Started Jul 31 05:50:04 PM PDT 24
Finished Jul 31 05:50:06 PM PDT 24
Peak memory 219676 kb
Host smart-6f31f2e4-d742-4180-b0af-7165005426a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634653539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1634653539
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1883434387
Short name T107
Test name
Test status
Simulation time 23498929 ps
CPU time 1.19 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:01 PM PDT 24
Peak memory 219896 kb
Host smart-109f0dc1-96dc-4b79-a292-a6ed714a7b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883434387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1883434387
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.285527873
Short name T124
Test name
Test status
Simulation time 24746996 ps
CPU time 0.92 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 218660 kb
Host smart-76a26b84-0676-42cb-8664-cd8bb63bcc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285527873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.285527873
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1467620290
Short name T909
Test name
Test status
Simulation time 68980832 ps
CPU time 1.09 seconds
Started Jul 31 05:50:02 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 217312 kb
Host smart-f544f1dc-4f5d-4fa5-ab88-5522a48b3c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467620290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1467620290
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.435219190
Short name T626
Test name
Test status
Simulation time 31836635 ps
CPU time 1.32 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 215688 kb
Host smart-dd0c70b6-59ee-4d7f-bff4-2c23f4a186c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435219190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.435219190
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2130777766
Short name T792
Test name
Test status
Simulation time 35129685 ps
CPU time 1.49 seconds
Started Jul 31 05:49:53 PM PDT 24
Finished Jul 31 05:49:55 PM PDT 24
Peak memory 225004 kb
Host smart-12bed73f-7b73-4d68-ae35-1dcaf11787b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130777766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2130777766
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1901142972
Short name T952
Test name
Test status
Simulation time 87438772 ps
CPU time 1.41 seconds
Started Jul 31 05:49:56 PM PDT 24
Finished Jul 31 05:49:58 PM PDT 24
Peak memory 218604 kb
Host smart-76acf863-2c98-4aeb-be8e-b9f651848ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901142972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1901142972
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.1656638043
Short name T511
Test name
Test status
Simulation time 179882324 ps
CPU time 1.19 seconds
Started Jul 31 05:50:04 PM PDT 24
Finished Jul 31 05:50:06 PM PDT 24
Peak memory 218500 kb
Host smart-6f863791-ec25-4dda-8c5f-aa5dc2916c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656638043 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.1656638043
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.144169643
Short name T193
Test name
Test status
Simulation time 18092064 ps
CPU time 1.05 seconds
Started Jul 31 05:49:57 PM PDT 24
Finished Jul 31 05:49:58 PM PDT 24
Peak memory 218684 kb
Host smart-c0316ad5-a635-4e48-97f5-a4a6aaf4fd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144169643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.144169643
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2921127710
Short name T476
Test name
Test status
Simulation time 30252887 ps
CPU time 1.33 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 217168 kb
Host smart-bddb4192-804e-438a-87fb-ece4380c4304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921127710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2921127710
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.2366337579
Short name T573
Test name
Test status
Simulation time 44451901 ps
CPU time 1.12 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:01 PM PDT 24
Peak memory 218556 kb
Host smart-9753e683-a390-44e8-a8d1-16de00c9172b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366337579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2366337579
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.4073493607
Short name T612
Test name
Test status
Simulation time 22936859 ps
CPU time 0.91 seconds
Started Jul 31 05:49:55 PM PDT 24
Finished Jul 31 05:49:56 PM PDT 24
Peak memory 218424 kb
Host smart-25cf09e8-dd77-4b35-91c7-5b15b0e6b646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073493607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.4073493607
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.956027912
Short name T368
Test name
Test status
Simulation time 38597688 ps
CPU time 1.48 seconds
Started Jul 31 05:49:57 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 219692 kb
Host smart-4fc18012-99bf-4041-b063-7acbdebd62d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956027912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.956027912
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.2366891457
Short name T463
Test name
Test status
Simulation time 31569891 ps
CPU time 0.89 seconds
Started Jul 31 05:49:54 PM PDT 24
Finished Jul 31 05:49:55 PM PDT 24
Peak memory 218372 kb
Host smart-c5b109fe-ec2e-4582-99ad-bb386450ab5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366891457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2366891457
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3337902045
Short name T690
Test name
Test status
Simulation time 143797493 ps
CPU time 1.17 seconds
Started Jul 31 05:50:04 PM PDT 24
Finished Jul 31 05:50:05 PM PDT 24
Peak memory 217388 kb
Host smart-247b8b34-ba3b-4e4d-9ae6-9faee1240428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337902045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3337902045
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3010749097
Short name T601
Test name
Test status
Simulation time 26697234 ps
CPU time 1.16 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 219516 kb
Host smart-da836a52-a464-4347-96b7-3f689a2b24f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010749097 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3010749097
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.1715374372
Short name T621
Test name
Test status
Simulation time 108079202 ps
CPU time 1.05 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:01 PM PDT 24
Peak memory 219476 kb
Host smart-8d704b2d-8670-4d2c-8d8c-5294b0bce92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715374372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1715374372
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.563209911
Short name T750
Test name
Test status
Simulation time 236636639 ps
CPU time 1 seconds
Started Jul 31 05:50:05 PM PDT 24
Finished Jul 31 05:50:07 PM PDT 24
Peak memory 217244 kb
Host smart-13de50c1-945e-4de8-a16b-837c6685a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563209911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.563209911
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.997070105
Short name T666
Test name
Test status
Simulation time 23366964 ps
CPU time 1.12 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:05 PM PDT 24
Peak memory 219824 kb
Host smart-a724de41-945b-4a81-9055-95ce8bf65c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997070105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.997070105
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2302532111
Short name T135
Test name
Test status
Simulation time 19609518 ps
CPU time 1.08 seconds
Started Jul 31 05:50:05 PM PDT 24
Finished Jul 31 05:50:07 PM PDT 24
Peak memory 218700 kb
Host smart-8340502e-b4ab-41ff-8171-376c8a847459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302532111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2302532111
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2311341216
Short name T687
Test name
Test status
Simulation time 293086878 ps
CPU time 1.2 seconds
Started Jul 31 05:49:56 PM PDT 24
Finished Jul 31 05:49:57 PM PDT 24
Peak memory 217588 kb
Host smart-a0652d48-7244-4e8c-afc5-52ab9c037f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311341216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2311341216
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.152406821
Short name T648
Test name
Test status
Simulation time 66934760 ps
CPU time 1.27 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:01 PM PDT 24
Peak memory 218992 kb
Host smart-3244d380-e6d8-458c-9946-008bfe93bee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152406821 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.152406821
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.1499284272
Short name T698
Test name
Test status
Simulation time 31236665 ps
CPU time 1 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 219852 kb
Host smart-a4056141-9d17-464c-8eff-186c1b54e02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499284272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1499284272
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3362055
Short name T317
Test name
Test status
Simulation time 40208514 ps
CPU time 1.23 seconds
Started Jul 31 05:49:54 PM PDT 24
Finished Jul 31 05:49:55 PM PDT 24
Peak memory 218880 kb
Host smart-b378ffda-dc5b-4235-9436-5f8a0af83169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3362055
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2143746620
Short name T833
Test name
Test status
Simulation time 29140517 ps
CPU time 1.25 seconds
Started Jul 31 05:48:50 PM PDT 24
Finished Jul 31 05:48:52 PM PDT 24
Peak memory 220832 kb
Host smart-814d97a8-22fc-40cc-a677-9216aa6fa002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143746620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2143746620
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3172216527
Short name T609
Test name
Test status
Simulation time 47955157 ps
CPU time 0.84 seconds
Started Jul 31 05:49:04 PM PDT 24
Finished Jul 31 05:49:05 PM PDT 24
Peak memory 206476 kb
Host smart-33db5c8e-edc7-47fd-8f60-0815fc1dea8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172216527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3172216527
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.965840719
Short name T187
Test name
Test status
Simulation time 21460758 ps
CPU time 0.83 seconds
Started Jul 31 05:49:04 PM PDT 24
Finished Jul 31 05:49:05 PM PDT 24
Peak memory 215296 kb
Host smart-7567d48e-aa39-4fc0-81a8-51c263470da3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965840719 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.965840719
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3126268395
Short name T658
Test name
Test status
Simulation time 70460126 ps
CPU time 1.07 seconds
Started Jul 31 05:49:00 PM PDT 24
Finished Jul 31 05:49:01 PM PDT 24
Peak memory 218376 kb
Host smart-24c5dcce-5e2c-4856-a76d-b2b84dfc7ad5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126268395 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3126268395
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1163901967
Short name T140
Test name
Test status
Simulation time 29817399 ps
CPU time 1.24 seconds
Started Jul 31 05:49:02 PM PDT 24
Finished Jul 31 05:49:04 PM PDT 24
Peak memory 219432 kb
Host smart-4654ecf1-61bb-41e6-a310-60d7acb05685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163901967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1163901967
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3712486526
Short name T297
Test name
Test status
Simulation time 83424708 ps
CPU time 2.74 seconds
Started Jul 31 05:48:58 PM PDT 24
Finished Jul 31 05:49:00 PM PDT 24
Peak memory 220248 kb
Host smart-0cac2ff1-773a-43ac-b9f6-b21f5833033b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712486526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3712486526
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1890769096
Short name T915
Test name
Test status
Simulation time 43199309 ps
CPU time 0.87 seconds
Started Jul 31 05:49:05 PM PDT 24
Finished Jul 31 05:49:06 PM PDT 24
Peak memory 215604 kb
Host smart-471a422e-3131-4d56-b675-ecc40f0fc67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890769096 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1890769096
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1639338159
Short name T953
Test name
Test status
Simulation time 16117344 ps
CPU time 0.95 seconds
Started Jul 31 05:48:58 PM PDT 24
Finished Jul 31 05:48:59 PM PDT 24
Peak memory 207052 kb
Host smart-47b73f89-d87b-4af6-ac2e-39af5efa27ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639338159 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1639338159
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1467248335
Short name T579
Test name
Test status
Simulation time 45496119 ps
CPU time 0.95 seconds
Started Jul 31 05:48:56 PM PDT 24
Finished Jul 31 05:48:57 PM PDT 24
Peak memory 215256 kb
Host smart-667fa468-5860-4382-8100-dc8bb6928454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467248335 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1467248335
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2724520334
Short name T875
Test name
Test status
Simulation time 333829578 ps
CPU time 6.33 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:14 PM PDT 24
Peak memory 217236 kb
Host smart-1da23779-a1d4-44b0-83ab-196c36a005c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724520334 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2724520334
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2453701472
Short name T903
Test name
Test status
Simulation time 271035807734 ps
CPU time 1791.54 seconds
Started Jul 31 05:48:51 PM PDT 24
Finished Jul 31 06:18:43 PM PDT 24
Peak memory 227004 kb
Host smart-bd6556c7-6e79-438d-9b70-72e6cfcc7027
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453701472 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2453701472
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2728574069
Short name T165
Test name
Test status
Simulation time 24503068 ps
CPU time 1.24 seconds
Started Jul 31 05:49:57 PM PDT 24
Finished Jul 31 05:49:58 PM PDT 24
Peak memory 219644 kb
Host smart-84de3ddb-c25b-4b73-b6f7-9ff6e1551346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728574069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2728574069
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.500770282
Short name T214
Test name
Test status
Simulation time 25949489 ps
CPU time 0.86 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 219300 kb
Host smart-5727fd5c-2c64-4ba1-b5f0-28a129e6f597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500770282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.500770282
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1988633524
Short name T506
Test name
Test status
Simulation time 96165502 ps
CPU time 1.17 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 217368 kb
Host smart-c4d8bfd8-39af-4d78-bbdf-43d859673f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988633524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1988633524
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.284871654
Short name T453
Test name
Test status
Simulation time 23722569 ps
CPU time 1.26 seconds
Started Jul 31 05:49:55 PM PDT 24
Finished Jul 31 05:49:57 PM PDT 24
Peak memory 219700 kb
Host smart-88956ebf-132f-44f0-9283-33449f89841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284871654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.284871654
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.33255567
Short name T204
Test name
Test status
Simulation time 18559417 ps
CPU time 1.12 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 224028 kb
Host smart-6b8c18db-401c-4ac0-99ad-07bc9434b4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33255567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.33255567
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.967432668
Short name T479
Test name
Test status
Simulation time 47738143 ps
CPU time 1.25 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 218604 kb
Host smart-ecfd076a-d754-460d-ba28-b66d6e614e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967432668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.967432668
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.208612602
Short name T884
Test name
Test status
Simulation time 114912048 ps
CPU time 1.31 seconds
Started Jul 31 05:50:06 PM PDT 24
Finished Jul 31 05:50:07 PM PDT 24
Peak memory 215640 kb
Host smart-3764721d-9549-4e32-bde1-3ebe1b584c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208612602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.208612602
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.124301002
Short name T125
Test name
Test status
Simulation time 44202054 ps
CPU time 1.08 seconds
Started Jul 31 05:49:50 PM PDT 24
Finished Jul 31 05:49:52 PM PDT 24
Peak memory 220732 kb
Host smart-f0ebd930-381d-4ddc-82b6-16e99510e743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124301002 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.124301002
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2353505553
Short name T738
Test name
Test status
Simulation time 56712786 ps
CPU time 1.27 seconds
Started Jul 31 05:50:14 PM PDT 24
Finished Jul 31 05:50:16 PM PDT 24
Peak memory 219624 kb
Host smart-ce309826-f1a1-4812-86bc-b16a2c1d23b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353505553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2353505553
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.896026036
Short name T871
Test name
Test status
Simulation time 48322307 ps
CPU time 1.15 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 220824 kb
Host smart-5eb8e61b-a237-4e0b-8737-eedfb0fdf9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896026036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.896026036
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1317517742
Short name T567
Test name
Test status
Simulation time 31203857 ps
CPU time 0.9 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 218396 kb
Host smart-f9fbb434-8e01-49dd-83ec-269ff141b49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317517742 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1317517742
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2761052234
Short name T424
Test name
Test status
Simulation time 38309440 ps
CPU time 1.27 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 217348 kb
Host smart-6c814fa2-04fb-4f0e-ab5d-d75c201dd2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761052234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2761052234
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2472006190
Short name T169
Test name
Test status
Simulation time 71019992 ps
CPU time 1.11 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 218340 kb
Host smart-cf4d4e4e-4616-4b65-ace2-4a9102416b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472006190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2472006190
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.849984581
Short name T600
Test name
Test status
Simulation time 20514994 ps
CPU time 1.23 seconds
Started Jul 31 05:50:02 PM PDT 24
Finished Jul 31 05:50:03 PM PDT 24
Peak memory 229596 kb
Host smart-03f99a27-e029-47c1-8b9b-a3d54c04ba5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849984581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.849984581
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1256142770
Short name T931
Test name
Test status
Simulation time 60870887 ps
CPU time 1.31 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:05 PM PDT 24
Peak memory 219924 kb
Host smart-3611c6fa-68b9-42e0-95fc-41512bb63991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256142770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1256142770
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2545683695
Short name T830
Test name
Test status
Simulation time 21679988 ps
CPU time 1.16 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 220704 kb
Host smart-b3e30813-f6e7-432a-af47-289fd28b3fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545683695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2545683695
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2777988622
Short name T553
Test name
Test status
Simulation time 112128375 ps
CPU time 1.39 seconds
Started Jul 31 05:50:02 PM PDT 24
Finished Jul 31 05:50:03 PM PDT 24
Peak memory 218892 kb
Host smart-be16c355-faba-4fae-99c9-4e81d7b3af81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777988622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2777988622
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.3116277286
Short name T202
Test name
Test status
Simulation time 323312036 ps
CPU time 1.13 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 218464 kb
Host smart-51259954-52b1-4b84-a2bb-f47d9b1416b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116277286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.3116277286
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_genbits.2939676811
Short name T762
Test name
Test status
Simulation time 367993179 ps
CPU time 3.87 seconds
Started Jul 31 05:49:55 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 218576 kb
Host smart-ea5cd0cc-8227-425f-8343-93f5ac3e4d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939676811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2939676811
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.439372752
Short name T729
Test name
Test status
Simulation time 103370097 ps
CPU time 1.31 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:01 PM PDT 24
Peak memory 215700 kb
Host smart-0e77eeb7-59fe-4c29-9ed7-814dee320bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439372752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.439372752
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.726505577
Short name T619
Test name
Test status
Simulation time 36582398 ps
CPU time 1.02 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 219708 kb
Host smart-7cc840aa-132e-4852-bd6e-21a1e14f4d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726505577 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.726505577
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.4185094053
Short name T300
Test name
Test status
Simulation time 24215912 ps
CPU time 1.32 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 218832 kb
Host smart-ede86cfb-7991-4106-bfbb-445a85e8b261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185094053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.4185094053
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.4056002515
Short name T331
Test name
Test status
Simulation time 75449434 ps
CPU time 1.16 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 218584 kb
Host smart-b29df01c-8a9d-42dd-b92d-4c34d90130eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056002515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.4056002515
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.639793001
Short name T552
Test name
Test status
Simulation time 23153930 ps
CPU time 0.99 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:01 PM PDT 24
Peak memory 218704 kb
Host smart-7531ea04-0466-4de0-a253-557fa99bd7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639793001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.639793001
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1201227265
Short name T403
Test name
Test status
Simulation time 188627583 ps
CPU time 1.15 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:01 PM PDT 24
Peak memory 217340 kb
Host smart-f0cb7c37-b8f6-40ea-bc7a-1c71b162bbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201227265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1201227265
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.3215220793
Short name T760
Test name
Test status
Simulation time 39261303 ps
CPU time 1.23 seconds
Started Jul 31 05:49:57 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 219804 kb
Host smart-a9287d00-a6e6-447b-b992-ad73bc77bf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215220793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.3215220793
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3324475736
Short name T49
Test name
Test status
Simulation time 24108186 ps
CPU time 1.28 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:01 PM PDT 24
Peak memory 229680 kb
Host smart-9ad2f37e-439a-44c9-8f5e-61f10a93f05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324475736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3324475736
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2137395996
Short name T663
Test name
Test status
Simulation time 94321618 ps
CPU time 3.18 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:03 PM PDT 24
Peak memory 215312 kb
Host smart-6cc6f927-f9f8-4a11-9de3-ef4e6eb0b5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137395996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2137395996
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1882510377
Short name T280
Test name
Test status
Simulation time 27732946 ps
CPU time 1.29 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 215696 kb
Host smart-269623e3-f846-482f-83e5-13ab1c944e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882510377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1882510377
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2167946896
Short name T902
Test name
Test status
Simulation time 18622727 ps
CPU time 0.92 seconds
Started Jul 31 05:49:00 PM PDT 24
Finished Jul 31 05:49:01 PM PDT 24
Peak memory 215124 kb
Host smart-0b6bab9e-8267-44dc-8fd3-a54e0f5be5ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167946896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2167946896
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3537859678
Short name T145
Test name
Test status
Simulation time 14138238 ps
CPU time 0.84 seconds
Started Jul 31 05:49:10 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 216340 kb
Host smart-70604060-0b4e-47cd-b66b-72b8ed26275a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537859678 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3537859678
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3675916760
Short name T172
Test name
Test status
Simulation time 104209270 ps
CPU time 1.19 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:09 PM PDT 24
Peak memory 216952 kb
Host smart-d323cd33-4660-4a41-9475-b2dd01c72f99
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675916760 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3675916760
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1590975375
Short name T615
Test name
Test status
Simulation time 20393572 ps
CPU time 1.2 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 223964 kb
Host smart-45ef746c-9987-4210-a508-b9cdb8a2b5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590975375 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1590975375
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3304287891
Short name T945
Test name
Test status
Simulation time 22185935 ps
CPU time 1.07 seconds
Started Jul 31 05:48:53 PM PDT 24
Finished Jul 31 05:48:55 PM PDT 24
Peak memory 217296 kb
Host smart-305d50a7-7049-4276-a039-7a0b858e18da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304287891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3304287891
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2278435322
Short name T99
Test name
Test status
Simulation time 20501734 ps
CPU time 1.09 seconds
Started Jul 31 05:48:56 PM PDT 24
Finished Jul 31 05:48:57 PM PDT 24
Peak memory 215340 kb
Host smart-ee0956ac-ca6a-4bdf-aa8c-feabea9783b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278435322 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2278435322
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3764316122
Short name T721
Test name
Test status
Simulation time 15770421 ps
CPU time 1.05 seconds
Started Jul 31 05:48:57 PM PDT 24
Finished Jul 31 05:48:58 PM PDT 24
Peak memory 207112 kb
Host smart-0dfc9bfc-2d7f-42da-8ae7-cd815db09fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764316122 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3764316122
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1744118900
Short name T669
Test name
Test status
Simulation time 26307516 ps
CPU time 0.94 seconds
Started Jul 31 05:48:52 PM PDT 24
Finished Jul 31 05:48:53 PM PDT 24
Peak memory 215288 kb
Host smart-612ddc70-5f1c-482d-aec8-966f3b1433ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744118900 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1744118900
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3717470357
Short name T499
Test name
Test status
Simulation time 278779552 ps
CPU time 5.36 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:15 PM PDT 24
Peak memory 215308 kb
Host smart-86c4769d-ae9b-4a6e-8f04-2102d5e945e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717470357 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3717470357
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2611338736
Short name T590
Test name
Test status
Simulation time 57102775567 ps
CPU time 1235 seconds
Started Jul 31 05:48:54 PM PDT 24
Finished Jul 31 06:09:30 PM PDT 24
Peak memory 223616 kb
Host smart-4ea7808f-5d2b-4f9f-9ebc-e140072b8420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611338736 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2611338736
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.695276100
Short name T629
Test name
Test status
Simulation time 45581596 ps
CPU time 1.23 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 219544 kb
Host smart-2d97b832-c1a4-419f-b924-7ef082af62e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695276100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.695276100
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.549393393
Short name T170
Test name
Test status
Simulation time 27611640 ps
CPU time 1.3 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 05:50:03 PM PDT 24
Peak memory 220516 kb
Host smart-039f881c-5a45-4d67-a044-25d30d2de98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549393393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.549393393
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.83953630
Short name T71
Test name
Test status
Simulation time 152037203 ps
CPU time 1.68 seconds
Started Jul 31 05:50:05 PM PDT 24
Finished Jul 31 05:50:06 PM PDT 24
Peak memory 219060 kb
Host smart-08125abf-58ec-4e36-81b6-b391f2577d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83953630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.83953630
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2908397366
Short name T91
Test name
Test status
Simulation time 89504823 ps
CPU time 1.23 seconds
Started Jul 31 05:50:12 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 221564 kb
Host smart-1f78650b-9d2a-4fa1-b92b-ebe58c118b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908397366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2908397366
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2422616449
Short name T14
Test name
Test status
Simulation time 22762045 ps
CPU time 1.06 seconds
Started Jul 31 05:49:50 PM PDT 24
Finished Jul 31 05:49:51 PM PDT 24
Peak memory 224000 kb
Host smart-5e3e941a-8316-4668-902f-974a52a6efa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422616449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2422616449
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.98185516
Short name T624
Test name
Test status
Simulation time 87394622 ps
CPU time 1.21 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 217316 kb
Host smart-639ff2ea-da0d-4e08-a23c-8145e7d29a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98185516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.98185516
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1532390050
Short name T279
Test name
Test status
Simulation time 78659974 ps
CPU time 1.24 seconds
Started Jul 31 05:50:05 PM PDT 24
Finished Jul 31 05:50:06 PM PDT 24
Peak memory 218616 kb
Host smart-d4158af5-ebb2-45b7-a538-7794633a3b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532390050 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1532390050
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.779925670
Short name T15
Test name
Test status
Simulation time 36895706 ps
CPU time 0.92 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 223828 kb
Host smart-fd8dd09a-eb77-49af-bc92-720871b7e2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779925670 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.779925670
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3520455303
Short name T439
Test name
Test status
Simulation time 31967375 ps
CPU time 1.29 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 219416 kb
Host smart-53c8b3ca-9f2f-47c8-b845-f6addd571b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520455303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3520455303
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3798283499
Short name T828
Test name
Test status
Simulation time 29863269 ps
CPU time 1.35 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 05:50:03 PM PDT 24
Peak memory 219764 kb
Host smart-1907058a-abf6-4f79-ad81-326cd744a50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798283499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3798283499
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1136168356
Short name T831
Test name
Test status
Simulation time 17817602 ps
CPU time 1.01 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 218600 kb
Host smart-40cedf89-b599-4f0f-8653-e9ef903cb3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136168356 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1136168356
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.691354543
Short name T886
Test name
Test status
Simulation time 58128425 ps
CPU time 1.58 seconds
Started Jul 31 05:50:14 PM PDT 24
Finished Jul 31 05:50:16 PM PDT 24
Peak memory 218876 kb
Host smart-0067925b-810c-4d30-891b-f2912412a0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691354543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.691354543
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.2992257075
Short name T678
Test name
Test status
Simulation time 21562665 ps
CPU time 1.13 seconds
Started Jul 31 05:49:55 PM PDT 24
Finished Jul 31 05:49:56 PM PDT 24
Peak memory 219756 kb
Host smart-08ca8c94-1cd2-4552-872c-5bd15cac0044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992257075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2992257075
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3110027044
Short name T719
Test name
Test status
Simulation time 152349125 ps
CPU time 2.64 seconds
Started Jul 31 05:49:53 PM PDT 24
Finished Jul 31 05:49:56 PM PDT 24
Peak memory 217692 kb
Host smart-0dec2f6f-2c2b-4f5d-9634-f2aed8d2196e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110027044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3110027044
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.3636663969
Short name T844
Test name
Test status
Simulation time 69923873 ps
CPU time 1.08 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:01 PM PDT 24
Peak memory 218692 kb
Host smart-34e5faed-1072-4bac-bafa-b158d24f7303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636663969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.3636663969
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.955626409
Short name T192
Test name
Test status
Simulation time 18552092 ps
CPU time 1.18 seconds
Started Jul 31 05:50:13 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 224048 kb
Host smart-54ab7857-6b69-40a9-aedf-6bd14d1cbc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955626409 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.955626409
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3168066575
Short name T605
Test name
Test status
Simulation time 146028412 ps
CPU time 1.09 seconds
Started Jul 31 05:50:02 PM PDT 24
Finished Jul 31 05:50:03 PM PDT 24
Peak memory 217404 kb
Host smart-78de6ee1-1bad-4d43-b99d-765fa1c3b275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168066575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3168066575
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.14633856
Short name T455
Test name
Test status
Simulation time 42762072 ps
CPU time 1.18 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:01 PM PDT 24
Peak memory 219672 kb
Host smart-f53daf11-b8e8-44d0-9684-e3c865879f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14633856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.14633856
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.1365511082
Short name T207
Test name
Test status
Simulation time 21494546 ps
CPU time 0.93 seconds
Started Jul 31 05:50:11 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 218540 kb
Host smart-d4bce7fb-49e4-4399-8a2c-277582c1f481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365511082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1365511082
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3964565408
Short name T790
Test name
Test status
Simulation time 41960604 ps
CPU time 1.42 seconds
Started Jul 31 05:50:05 PM PDT 24
Finished Jul 31 05:50:07 PM PDT 24
Peak memory 217300 kb
Host smart-029da00b-07f2-4c95-a797-85b588d0427d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964565408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3964565408
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.504687605
Short name T960
Test name
Test status
Simulation time 23499651 ps
CPU time 1.14 seconds
Started Jul 31 05:50:12 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 218552 kb
Host smart-20c3a5ac-5d3d-44d3-8898-5e0e8746e852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504687605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.504687605
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3664068961
Short name T53
Test name
Test status
Simulation time 33700029 ps
CPU time 1.34 seconds
Started Jul 31 05:50:11 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 225724 kb
Host smart-77afeed5-3e65-42d4-92ac-eede4b8eb03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664068961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3664068961
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.341406658
Short name T309
Test name
Test status
Simulation time 124319917 ps
CPU time 1.45 seconds
Started Jul 31 05:50:13 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 218740 kb
Host smart-443f3590-600d-458f-baf7-c2cef3b0a041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341406658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.341406658
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.3089027440
Short name T662
Test name
Test status
Simulation time 103128787 ps
CPU time 1.11 seconds
Started Jul 31 05:50:11 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 219844 kb
Host smart-b787fd20-1d18-4cb9-9b6d-77736f035edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089027440 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.3089027440
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.3788224794
Short name T130
Test name
Test status
Simulation time 28794049 ps
CPU time 1.17 seconds
Started Jul 31 05:50:07 PM PDT 24
Finished Jul 31 05:50:08 PM PDT 24
Peak memory 218700 kb
Host smart-8de157cc-34f8-4bde-b425-9601884f8cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788224794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3788224794
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.4260250679
Short name T617
Test name
Test status
Simulation time 25560270 ps
CPU time 1.22 seconds
Started Jul 31 05:50:07 PM PDT 24
Finished Jul 31 05:50:08 PM PDT 24
Peak memory 218464 kb
Host smart-ea683f34-86e4-4216-ab17-5884d0ea11bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260250679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.4260250679
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.2135599766
Short name T286
Test name
Test status
Simulation time 26764696 ps
CPU time 1.23 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 219052 kb
Host smart-bdfca6ac-9c89-4f33-8411-59c8f3d93d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135599766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2135599766
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.716226626
Short name T801
Test name
Test status
Simulation time 54286200 ps
CPU time 1.08 seconds
Started Jul 31 05:50:11 PM PDT 24
Finished Jul 31 05:50:12 PM PDT 24
Peak memory 229636 kb
Host smart-f93bf3b1-fde7-4ef9-a580-b7e9116ab46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716226626 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.716226626
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2143878240
Short name T759
Test name
Test status
Simulation time 643772981 ps
CPU time 5.16 seconds
Started Jul 31 05:49:57 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 219356 kb
Host smart-4cdb1e53-cd36-4a3c-bca6-3e6bfb741876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143878240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2143878240
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3394811215
Short name T705
Test name
Test status
Simulation time 89129529 ps
CPU time 1.27 seconds
Started Jul 31 05:49:00 PM PDT 24
Finished Jul 31 05:49:02 PM PDT 24
Peak memory 218920 kb
Host smart-95c1da26-318c-424b-828f-4c793b4411d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394811215 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3394811215
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.321598031
Short name T660
Test name
Test status
Simulation time 42469644 ps
CPU time 0.94 seconds
Started Jul 31 05:49:05 PM PDT 24
Finished Jul 31 05:49:06 PM PDT 24
Peak memory 214880 kb
Host smart-e8c82047-1be8-44a8-94e7-096657a4eedd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321598031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.321598031
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1531024310
Short name T641
Test name
Test status
Simulation time 10631225 ps
CPU time 0.83 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:11 PM PDT 24
Peak memory 216192 kb
Host smart-17fef5fb-0ed4-41d5-a717-bde6a81f20e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531024310 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1531024310
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.415175621
Short name T968
Test name
Test status
Simulation time 105308255 ps
CPU time 1.2 seconds
Started Jul 31 05:48:59 PM PDT 24
Finished Jul 31 05:49:01 PM PDT 24
Peak memory 216796 kb
Host smart-b4fa0524-13ea-4d62-807c-f21b406d8a38
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415175621 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.415175621
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3604781406
Short name T457
Test name
Test status
Simulation time 28834412 ps
CPU time 1.11 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 229608 kb
Host smart-550be19c-f02b-41b4-8b56-108e5eafbce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604781406 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3604781406
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3568727379
Short name T429
Test name
Test status
Simulation time 86788246 ps
CPU time 2.16 seconds
Started Jul 31 05:48:57 PM PDT 24
Finished Jul 31 05:48:59 PM PDT 24
Peak memory 220112 kb
Host smart-d67eeaac-0b2a-41c0-8170-6fba05c336be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568727379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3568727379
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.611927281
Short name T914
Test name
Test status
Simulation time 27722683 ps
CPU time 0.96 seconds
Started Jul 31 05:49:05 PM PDT 24
Finished Jul 31 05:49:06 PM PDT 24
Peak memory 215496 kb
Host smart-68d7b664-d965-40c1-a040-1c2b4b9c92ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611927281 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.611927281
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.456737418
Short name T329
Test name
Test status
Simulation time 17138923 ps
CPU time 0.97 seconds
Started Jul 31 05:48:59 PM PDT 24
Finished Jul 31 05:49:00 PM PDT 24
Peak memory 207032 kb
Host smart-8bdf664f-8e1c-4ea9-ac83-bb2509530352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456737418 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.456737418
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.234490471
Short name T803
Test name
Test status
Simulation time 16170191 ps
CPU time 0.96 seconds
Started Jul 31 05:49:11 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 206992 kb
Host smart-98299208-1209-4c18-ae3e-5fc8198c99d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234490471 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.234490471
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2126039999
Short name T642
Test name
Test status
Simulation time 206808300 ps
CPU time 2.73 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:05 PM PDT 24
Peak memory 215264 kb
Host smart-cbae699f-7b1b-4017-98ec-80f20af1dfd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126039999 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2126039999
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/80.edn_alert.3903406426
Short name T210
Test name
Test status
Simulation time 35136918 ps
CPU time 1.26 seconds
Started Jul 31 05:50:12 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 218928 kb
Host smart-5ae7b274-1e25-4e31-803e-0f99d941b5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903406426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.3903406426
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_genbits.868949356
Short name T535
Test name
Test status
Simulation time 123606298 ps
CPU time 1.78 seconds
Started Jul 31 05:50:11 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 218672 kb
Host smart-ebe79e17-caaf-4beb-8eea-f8d59c188106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868949356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.868949356
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1354229439
Short name T44
Test name
Test status
Simulation time 44201249 ps
CPU time 1.13 seconds
Started Jul 31 05:49:57 PM PDT 24
Finished Jul 31 05:49:58 PM PDT 24
Peak memory 219616 kb
Host smart-cf7aa24f-992a-4db5-9c6b-23ae169282e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354229439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1354229439
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1190441408
Short name T120
Test name
Test status
Simulation time 21897675 ps
CPU time 1.14 seconds
Started Jul 31 05:50:08 PM PDT 24
Finished Jul 31 05:50:09 PM PDT 24
Peak memory 218352 kb
Host smart-596ba26e-69d0-4a7c-9ba3-f4c14e1f46ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190441408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1190441408
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3082978695
Short name T890
Test name
Test status
Simulation time 55025827 ps
CPU time 1.24 seconds
Started Jul 31 05:50:10 PM PDT 24
Finished Jul 31 05:50:12 PM PDT 24
Peak memory 217236 kb
Host smart-a6ebd79d-acdc-4c5e-8e76-a948910e81cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082978695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3082978695
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.1651346528
Short name T824
Test name
Test status
Simulation time 84970662 ps
CPU time 1.36 seconds
Started Jul 31 05:50:02 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 215656 kb
Host smart-ada6907d-6be8-4886-ae7e-589b560072ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651346528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.1651346528
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3226140541
Short name T148
Test name
Test status
Simulation time 18928735 ps
CPU time 1.14 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:01 PM PDT 24
Peak memory 224004 kb
Host smart-2c47a0e8-9bce-439d-9426-84d821428dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226140541 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3226140541
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.4054961664
Short name T482
Test name
Test status
Simulation time 44257555 ps
CPU time 1.15 seconds
Started Jul 31 05:50:11 PM PDT 24
Finished Jul 31 05:50:12 PM PDT 24
Peak memory 217532 kb
Host smart-24270332-14d0-4548-a3a4-fe8f1bb304f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054961664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.4054961664
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.2550626741
Short name T252
Test name
Test status
Simulation time 97651381 ps
CPU time 1.3 seconds
Started Jul 31 05:50:11 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 219680 kb
Host smart-09aaba30-ef33-4895-b386-5208b3edc251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550626741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.2550626741
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.4132172828
Short name T847
Test name
Test status
Simulation time 19442788 ps
CPU time 1.08 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 219656 kb
Host smart-705dca54-b0bf-491a-8296-64df7c794d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132172828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4132172828
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1905074231
Short name T709
Test name
Test status
Simulation time 581113846 ps
CPU time 5.24 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:05 PM PDT 24
Peak memory 220324 kb
Host smart-aac8e7d6-9063-4ee1-a3a0-46ef1d5ddc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905074231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1905074231
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2683166046
Short name T353
Test name
Test status
Simulation time 51170407 ps
CPU time 1.19 seconds
Started Jul 31 05:50:13 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 219612 kb
Host smart-842d51af-a08f-46eb-97b4-e6fd3531bf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683166046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2683166046
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3006462697
Short name T541
Test name
Test status
Simulation time 19425153 ps
CPU time 1.27 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 224044 kb
Host smart-d9740607-cc4f-414a-960b-8697b1cca8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006462697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3006462697
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1618750988
Short name T397
Test name
Test status
Simulation time 89078950 ps
CPU time 1.04 seconds
Started Jul 31 05:50:05 PM PDT 24
Finished Jul 31 05:50:06 PM PDT 24
Peak memory 217380 kb
Host smart-9d1b0f22-8000-4897-ae9e-75b983fed9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618750988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1618750988
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.1475742231
Short name T106
Test name
Test status
Simulation time 46015889 ps
CPU time 1.28 seconds
Started Jul 31 05:50:05 PM PDT 24
Finished Jul 31 05:50:06 PM PDT 24
Peak memory 218688 kb
Host smart-0cb5bab9-0e1e-44e1-a825-e3e16c28a8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475742231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.1475742231
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3343156582
Short name T469
Test name
Test status
Simulation time 23448082 ps
CPU time 1.16 seconds
Started Jul 31 05:50:06 PM PDT 24
Finished Jul 31 05:50:08 PM PDT 24
Peak memory 219612 kb
Host smart-2d52e87d-5ad3-4f18-9f85-cdb11dd140de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343156582 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3343156582
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.984526442
Short name T408
Test name
Test status
Simulation time 29617004 ps
CPU time 1.31 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 217208 kb
Host smart-a3a9027b-bb6c-49de-9e53-30d001760744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984526442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.984526442
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2478581830
Short name T254
Test name
Test status
Simulation time 28874083 ps
CPU time 1.26 seconds
Started Jul 31 05:50:13 PM PDT 24
Finished Jul 31 05:50:15 PM PDT 24
Peak memory 220572 kb
Host smart-6166e590-f6cb-489d-956d-bcd7d01daaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478581830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2478581830
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.3824079401
Short name T6
Test name
Test status
Simulation time 67374447 ps
CPU time 0.98 seconds
Started Jul 31 05:50:13 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 219664 kb
Host smart-215067fe-f852-42f1-85e7-75ef47a8accc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824079401 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3824079401
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.916114500
Short name T70
Test name
Test status
Simulation time 38926986 ps
CPU time 1.3 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 218368 kb
Host smart-d98158bf-a428-4f57-b601-3a16ef987513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916114500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.916114500
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.1110581110
Short name T518
Test name
Test status
Simulation time 21740801 ps
CPU time 1.12 seconds
Started Jul 31 05:50:05 PM PDT 24
Finished Jul 31 05:50:06 PM PDT 24
Peak memory 219972 kb
Host smart-47ef0316-b778-4a2f-a614-378c610ea8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110581110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.1110581110
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2620811849
Short name T153
Test name
Test status
Simulation time 19907021 ps
CPU time 1.13 seconds
Started Jul 31 05:50:13 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 219420 kb
Host smart-9ceea2b6-b969-457b-9fef-128bafdf52ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620811849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2620811849
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.4165631620
Short name T534
Test name
Test status
Simulation time 83329597 ps
CPU time 1.62 seconds
Started Jul 31 05:50:05 PM PDT 24
Finished Jul 31 05:50:07 PM PDT 24
Peak memory 220280 kb
Host smart-88dfb731-faa0-46d0-a45f-b181d9961ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165631620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.4165631620
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.1595369957
Short name T885
Test name
Test status
Simulation time 26800432 ps
CPU time 1.27 seconds
Started Jul 31 05:50:08 PM PDT 24
Finished Jul 31 05:50:10 PM PDT 24
Peak memory 218588 kb
Host smart-e8d131c8-4f42-4fd2-83ea-58984d7f0555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595369957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1595369957
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.3127700575
Short name T159
Test name
Test status
Simulation time 47470555 ps
CPU time 0.98 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 219488 kb
Host smart-f64cd616-91d9-43ba-904a-c7b276668401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127700575 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3127700575
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1462371623
Short name T627
Test name
Test status
Simulation time 54419069 ps
CPU time 2.09 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 220304 kb
Host smart-130cf8ce-858e-4943-ba18-50d73cb4a7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462371623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1462371623
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2786850172
Short name T205
Test name
Test status
Simulation time 44488867 ps
CPU time 1.15 seconds
Started Jul 31 05:50:04 PM PDT 24
Finished Jul 31 05:50:06 PM PDT 24
Peak memory 219168 kb
Host smart-94a7fbc7-3daf-47eb-8f36-b17a558d5ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786850172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2786850172
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2827085798
Short name T923
Test name
Test status
Simulation time 20486564 ps
CPU time 0.99 seconds
Started Jul 31 05:50:06 PM PDT 24
Finished Jul 31 05:50:07 PM PDT 24
Peak memory 224024 kb
Host smart-2a0dbd90-1a8c-4151-a8b1-eacb5f3a35b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827085798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2827085798
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2280110230
Short name T34
Test name
Test status
Simulation time 57595964 ps
CPU time 1.05 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 217356 kb
Host smart-ff5ded5f-cf68-42bd-8ca7-2fa13375996c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280110230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2280110230
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2222240485
Short name T970
Test name
Test status
Simulation time 34836250 ps
CPU time 1.38 seconds
Started Jul 31 05:49:11 PM PDT 24
Finished Jul 31 05:49:12 PM PDT 24
Peak memory 215684 kb
Host smart-19282a1d-e581-44a9-ad8e-347080464e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222240485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2222240485
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.205940373
Short name T545
Test name
Test status
Simulation time 36151561 ps
CPU time 0.8 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 206784 kb
Host smart-ed4dc8ba-c812-4ca7-aafe-19edb327e19b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205940373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.205940373
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3796437535
Short name T343
Test name
Test status
Simulation time 41909149 ps
CPU time 0.86 seconds
Started Jul 31 05:48:59 PM PDT 24
Finished Jul 31 05:49:00 PM PDT 24
Peak memory 215956 kb
Host smart-4bd5a1ce-9ee5-4925-a2ab-401d4886b6b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796437535 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3796437535
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1781523721
Short name T372
Test name
Test status
Simulation time 44829499 ps
CPU time 1.3 seconds
Started Jul 31 05:49:08 PM PDT 24
Finished Jul 31 05:49:09 PM PDT 24
Peak memory 216788 kb
Host smart-dcfdd091-88f8-41c3-90df-c5b1464d64ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781523721 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1781523721
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3140872928
Short name T758
Test name
Test status
Simulation time 46134147 ps
CPU time 1.07 seconds
Started Jul 31 05:49:09 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 219760 kb
Host smart-57479463-609f-48fa-9acd-ee12be4b4fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140872928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3140872928
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3640567217
Short name T32
Test name
Test status
Simulation time 264043461 ps
CPU time 1.07 seconds
Started Jul 31 05:49:07 PM PDT 24
Finished Jul 31 05:49:09 PM PDT 24
Peak memory 217152 kb
Host smart-7a4dc490-15db-423f-99cd-c567df7ffc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640567217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3640567217
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.784216718
Short name T277
Test name
Test status
Simulation time 49562802 ps
CPU time 0.91 seconds
Started Jul 31 05:49:03 PM PDT 24
Finished Jul 31 05:49:04 PM PDT 24
Peak memory 215320 kb
Host smart-7b5274c4-41d5-4474-a20b-858ce4f32f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784216718 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.784216718
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2020616903
Short name T78
Test name
Test status
Simulation time 53637536 ps
CPU time 0.96 seconds
Started Jul 31 05:49:01 PM PDT 24
Finished Jul 31 05:49:02 PM PDT 24
Peak memory 207052 kb
Host smart-2e6ebd0c-e4e1-4447-9c7c-a86d642c631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020616903 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2020616903
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.635756555
Short name T673
Test name
Test status
Simulation time 25428270 ps
CPU time 0.93 seconds
Started Jul 31 05:49:13 PM PDT 24
Finished Jul 31 05:49:14 PM PDT 24
Peak memory 215264 kb
Host smart-2d30f124-cdea-47b8-a6ee-7e2dd351a2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635756555 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.635756555
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3486081361
Short name T732
Test name
Test status
Simulation time 244581895 ps
CPU time 4.85 seconds
Started Jul 31 05:49:05 PM PDT 24
Finished Jul 31 05:49:10 PM PDT 24
Peak memory 217240 kb
Host smart-939b289d-02f4-4cee-baea-4e4d61235b50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486081361 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3486081361
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1452684995
Short name T431
Test name
Test status
Simulation time 39961455394 ps
CPU time 894.11 seconds
Started Jul 31 05:49:06 PM PDT 24
Finished Jul 31 06:04:00 PM PDT 24
Peak memory 220192 kb
Host smart-844a61ef-3165-48c0-b3f6-5e893374d3bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452684995 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1452684995
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.3588207597
Short name T253
Test name
Test status
Simulation time 31463326 ps
CPU time 1.35 seconds
Started Jul 31 05:50:15 PM PDT 24
Finished Jul 31 05:50:16 PM PDT 24
Peak memory 215704 kb
Host smart-e8824b2e-69f2-4825-b7b1-3ba2baafeddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588207597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.3588207597
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.4266028922
Short name T141
Test name
Test status
Simulation time 32805487 ps
CPU time 1.03 seconds
Started Jul 31 05:50:09 PM PDT 24
Finished Jul 31 05:50:10 PM PDT 24
Peak memory 219592 kb
Host smart-b67bd8ce-59ce-43ff-9a49-09e5d96f9df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266028922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.4266028922
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3311099468
Short name T645
Test name
Test status
Simulation time 144171766 ps
CPU time 1.84 seconds
Started Jul 31 05:50:04 PM PDT 24
Finished Jul 31 05:50:06 PM PDT 24
Peak memory 218768 kb
Host smart-2c84e73f-65a3-4725-9a92-7292952ad49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311099468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3311099468
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.408276158
Short name T328
Test name
Test status
Simulation time 40805118 ps
CPU time 1.06 seconds
Started Jul 31 05:50:08 PM PDT 24
Finished Jul 31 05:50:09 PM PDT 24
Peak memory 218556 kb
Host smart-8bc6e3ca-c990-4bdf-9f3f-50ce39a91254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408276158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.408276158
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.4135959997
Short name T406
Test name
Test status
Simulation time 35800118 ps
CPU time 1.1 seconds
Started Jul 31 05:50:10 PM PDT 24
Finished Jul 31 05:50:17 PM PDT 24
Peak memory 219132 kb
Host smart-7ff607f0-392d-40a0-9fcb-db0aa23ca45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135959997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.4135959997
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1636491262
Short name T477
Test name
Test status
Simulation time 123019104 ps
CPU time 1.52 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 218788 kb
Host smart-1710e288-95a8-458a-bc04-58e6990408d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636491262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1636491262
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.449118521
Short name T67
Test name
Test status
Simulation time 51345849 ps
CPU time 1.15 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 220124 kb
Host smart-4b966d15-c6e9-4500-8137-4951a734a03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449118521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.449118521
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3822508548
Short name T591
Test name
Test status
Simulation time 136869298 ps
CPU time 1.24 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 225620 kb
Host smart-45b9d203-61b3-42e1-b811-41e765151b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822508548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3822508548
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.4065895477
Short name T616
Test name
Test status
Simulation time 34663279 ps
CPU time 1.37 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 215300 kb
Host smart-f0490fff-9b59-4fb8-991b-22e59413ac50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065895477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.4065895477
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2740480582
Short name T917
Test name
Test status
Simulation time 44630046 ps
CPU time 1.15 seconds
Started Jul 31 05:50:11 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 219892 kb
Host smart-5c5897d2-1316-4044-84da-6cc1286276dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740480582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2740480582
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.1176341780
Short name T908
Test name
Test status
Simulation time 118037581 ps
CPU time 1.1 seconds
Started Jul 31 05:50:13 PM PDT 24
Finished Jul 31 05:50:14 PM PDT 24
Peak memory 219480 kb
Host smart-9e6a1304-dfb0-46b3-8042-ea9ecce037a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176341780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1176341780
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2404116917
Short name T707
Test name
Test status
Simulation time 63696537 ps
CPU time 1.29 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 217332 kb
Host smart-afeb06d5-ace3-4de6-bba4-def1f992c9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404116917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2404116917
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.2381957808
Short name T773
Test name
Test status
Simulation time 43362447 ps
CPU time 1.18 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 218484 kb
Host smart-979a0143-d39c-463a-8fb5-8a136fa565be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381957808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.2381957808
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1240164531
Short name T63
Test name
Test status
Simulation time 23181431 ps
CPU time 0.91 seconds
Started Jul 31 05:49:58 PM PDT 24
Finished Jul 31 05:49:59 PM PDT 24
Peak memory 218512 kb
Host smart-e4c7cd05-415b-47a0-a73a-e7698a825048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240164531 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1240164531
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2709511118
Short name T452
Test name
Test status
Simulation time 30204753 ps
CPU time 0.95 seconds
Started Jul 31 05:50:05 PM PDT 24
Finished Jul 31 05:50:07 PM PDT 24
Peak memory 217288 kb
Host smart-27a522b5-37ae-44ae-b404-451972266d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709511118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2709511118
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.389374249
Short name T957
Test name
Test status
Simulation time 56454764 ps
CPU time 1.29 seconds
Started Jul 31 05:50:02 PM PDT 24
Finished Jul 31 05:50:03 PM PDT 24
Peak memory 215652 kb
Host smart-181ce2ac-4433-4a13-8cbf-03fdf4281c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389374249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.389374249
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1660119338
Short name T752
Test name
Test status
Simulation time 107962236 ps
CPU time 0.97 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 219816 kb
Host smart-99213fff-f0e7-4411-bb55-1daedfdd8177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660119338 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1660119338
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3255515410
Short name T364
Test name
Test status
Simulation time 111176435 ps
CPU time 2.29 seconds
Started Jul 31 05:50:14 PM PDT 24
Finished Jul 31 05:50:16 PM PDT 24
Peak memory 220032 kb
Host smart-db557cdd-09ad-4d97-9c00-41d12406f2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255515410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3255515410
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.962562317
Short name T544
Test name
Test status
Simulation time 28341065 ps
CPU time 1.19 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 219876 kb
Host smart-bb8b7cf8-c045-46b7-a5f2-efef20464b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962562317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.962562317
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.939580066
Short name T987
Test name
Test status
Simulation time 31802471 ps
CPU time 1.06 seconds
Started Jul 31 05:50:04 PM PDT 24
Finished Jul 31 05:50:05 PM PDT 24
Peak memory 218596 kb
Host smart-1aa083e0-0c67-4ba0-98cd-2dd417700fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939580066 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.939580066
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1697562082
Short name T305
Test name
Test status
Simulation time 39621804 ps
CPU time 1.27 seconds
Started Jul 31 05:50:01 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 217276 kb
Host smart-b4240657-9a99-4825-8d60-6107bbdaee59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697562082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1697562082
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3095545806
Short name T523
Test name
Test status
Simulation time 62184868 ps
CPU time 1.07 seconds
Started Jul 31 05:50:07 PM PDT 24
Finished Jul 31 05:50:09 PM PDT 24
Peak memory 218580 kb
Host smart-248464ef-c0c6-451a-9b79-c8294eb74701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095545806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3095545806
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.879980499
Short name T215
Test name
Test status
Simulation time 19730997 ps
CPU time 1.06 seconds
Started Jul 31 05:50:04 PM PDT 24
Finished Jul 31 05:50:05 PM PDT 24
Peak memory 218340 kb
Host smart-d50ba178-4477-4461-813c-64579f47beac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879980499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.879980499
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.4080304802
Short name T935
Test name
Test status
Simulation time 206376557 ps
CPU time 1.74 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:01 PM PDT 24
Peak memory 219560 kb
Host smart-d2e8f9d9-3169-4db4-9b4b-eb35ece2e874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080304802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.4080304802
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2978851523
Short name T111
Test name
Test status
Simulation time 53976737 ps
CPU time 1.08 seconds
Started Jul 31 05:50:03 PM PDT 24
Finished Jul 31 05:50:04 PM PDT 24
Peak memory 218600 kb
Host smart-1945de77-c8be-42e6-86bf-fe8316eed393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978851523 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2978851523
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1236504559
Short name T65
Test name
Test status
Simulation time 21083090 ps
CPU time 1.04 seconds
Started Jul 31 05:50:12 PM PDT 24
Finished Jul 31 05:50:13 PM PDT 24
Peak memory 218552 kb
Host smart-e6bc40db-d668-4b5f-a738-a4633cf6f71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236504559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1236504559
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.4046117916
Short name T428
Test name
Test status
Simulation time 101580150 ps
CPU time 1.57 seconds
Started Jul 31 05:50:10 PM PDT 24
Finished Jul 31 05:50:12 PM PDT 24
Peak memory 218716 kb
Host smart-f26b3bf7-183b-4543-b607-ca7fd9f616ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046117916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.4046117916
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.1466310998
Short name T785
Test name
Test status
Simulation time 34226004 ps
CPU time 1.15 seconds
Started Jul 31 05:50:00 PM PDT 24
Finished Jul 31 05:50:02 PM PDT 24
Peak memory 218556 kb
Host smart-2e8e124d-574e-408d-8384-0dc8b31b1b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466310998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1466310998
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.635446270
Short name T22
Test name
Test status
Simulation time 25009076 ps
CPU time 0.98 seconds
Started Jul 31 05:49:59 PM PDT 24
Finished Jul 31 05:50:00 PM PDT 24
Peak memory 218540 kb
Host smart-c939352c-019e-4bb7-bb0e-c6d63c0a0a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635446270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.635446270
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3873822957
Short name T563
Test name
Test status
Simulation time 121869714 ps
CPU time 1.23 seconds
Started Jul 31 05:50:09 PM PDT 24
Finished Jul 31 05:50:10 PM PDT 24
Peak memory 217160 kb
Host smart-2e60d721-bb24-4f31-8878-0c15a9842803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873822957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3873822957
Directory /workspace/99.edn_genbits/latest
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