Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	2	0	2	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	8	0	8	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr_pin

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_pins[0]

106066

1

T1

56

T8

31

T20

63

all_pins[1]

106066

1

T1

56

T8

31

T20

63

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	200804	1			T1	112		T8	62		T20	126
values[0x1]	11328	1			T27	19		T41	33		T21	251
transitions[0x0=>0x1]	10484	1			T27	17		T41	23		T21	243
transitions[0x1=>0x0]	10498	1			T27	17		T41	24		T21	243

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	96548	1			T1	56		T8	31		T20	63
all_pins[0]	values[0x1]	9518	1			T27	12		T41	18		T21	226
all_pins[0]	transitions[0x0=>0x1]	9051	1			T27	10		T41	12		T21	220
all_pins[0]	transitions[0x1=>0x0]	1343	1			T27	5		T41	9		T21	19
all_pins[1]	values[0x0]	104256	1			T1	56		T8	31		T20	63
all_pins[1]	values[0x1]	1810	1			T27	7		T41	15		T21	25
all_pins[1]	transitions[0x0=>0x1]	1433	1			T27	7		T41	11		T21	23
all_pins[1]	transitions[0x1=>0x0]	9155	1			T27	12		T41	15		T21	224