Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.41 98.25 93.31 91.10 87.21 95.50 96.83 91.70


Total test records in report: 1125
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T1010 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3155915690 Aug 01 06:20:37 PM PDT 24 Aug 01 06:20:38 PM PDT 24 22666107 ps
T1011 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1073758633 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:48 PM PDT 24 347133841 ps
T1012 /workspace/coverage/cover_reg_top/10.edn_intr_test.1636959956 Aug 01 06:20:34 PM PDT 24 Aug 01 06:20:35 PM PDT 24 15984659 ps
T1013 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3523688423 Aug 01 06:20:38 PM PDT 24 Aug 01 06:20:39 PM PDT 24 33415671 ps
T1014 /workspace/coverage/cover_reg_top/19.edn_intr_test.326390312 Aug 01 06:20:45 PM PDT 24 Aug 01 06:20:46 PM PDT 24 61085844 ps
T1015 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3558580360 Aug 01 06:20:40 PM PDT 24 Aug 01 06:20:42 PM PDT 24 40377830 ps
T262 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3413039162 Aug 01 06:20:38 PM PDT 24 Aug 01 06:20:39 PM PDT 24 12058724 ps
T1016 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1195539738 Aug 01 06:20:28 PM PDT 24 Aug 01 06:20:29 PM PDT 24 12275775 ps
T1017 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3086091329 Aug 01 06:20:42 PM PDT 24 Aug 01 06:20:44 PM PDT 24 138580326 ps
T1018 /workspace/coverage/cover_reg_top/40.edn_intr_test.1544189209 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:48 PM PDT 24 21001106 ps
T1019 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3257643517 Aug 01 06:20:42 PM PDT 24 Aug 01 06:20:44 PM PDT 24 42174431 ps
T1020 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3046231665 Aug 01 06:20:30 PM PDT 24 Aug 01 06:20:31 PM PDT 24 12157529 ps
T1021 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3171026051 Aug 01 06:20:40 PM PDT 24 Aug 01 06:20:42 PM PDT 24 37236000 ps
T1022 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4078782399 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:49 PM PDT 24 49730508 ps
T1023 /workspace/coverage/cover_reg_top/49.edn_intr_test.4221237974 Aug 01 06:20:52 PM PDT 24 Aug 01 06:20:53 PM PDT 24 24105549 ps
T1024 /workspace/coverage/cover_reg_top/13.edn_intr_test.712290350 Aug 01 06:20:39 PM PDT 24 Aug 01 06:20:40 PM PDT 24 97309549 ps
T1025 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4144838102 Aug 01 06:20:37 PM PDT 24 Aug 01 06:20:39 PM PDT 24 130627367 ps
T1026 /workspace/coverage/cover_reg_top/2.edn_intr_test.2601091353 Aug 01 06:20:30 PM PDT 24 Aug 01 06:20:31 PM PDT 24 49601297 ps
T1027 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3557880811 Aug 01 06:20:44 PM PDT 24 Aug 01 06:20:46 PM PDT 24 164600702 ps
T1028 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1324843652 Aug 01 06:20:36 PM PDT 24 Aug 01 06:20:38 PM PDT 24 89960257 ps
T1029 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4242990495 Aug 01 06:20:34 PM PDT 24 Aug 01 06:20:36 PM PDT 24 387140495 ps
T1030 /workspace/coverage/cover_reg_top/29.edn_intr_test.3233948250 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:48 PM PDT 24 18894318 ps
T1031 /workspace/coverage/cover_reg_top/26.edn_intr_test.2755317702 Aug 01 06:20:46 PM PDT 24 Aug 01 06:20:47 PM PDT 24 25643485 ps
T1032 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3739436640 Aug 01 06:20:35 PM PDT 24 Aug 01 06:20:36 PM PDT 24 46292501 ps
T1033 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2134124651 Aug 01 06:20:31 PM PDT 24 Aug 01 06:20:35 PM PDT 24 93379125 ps
T1034 /workspace/coverage/cover_reg_top/25.edn_intr_test.3458753781 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:53 PM PDT 24 18128785 ps
T1035 /workspace/coverage/cover_reg_top/41.edn_intr_test.2300121791 Aug 01 06:20:41 PM PDT 24 Aug 01 06:20:42 PM PDT 24 26439216 ps
T1036 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2953209549 Aug 01 06:20:40 PM PDT 24 Aug 01 06:20:45 PM PDT 24 2458098400 ps
T1037 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1863238251 Aug 01 06:20:26 PM PDT 24 Aug 01 06:20:27 PM PDT 24 27619283 ps
T1038 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1320965814 Aug 01 06:20:37 PM PDT 24 Aug 01 06:20:38 PM PDT 24 42473675 ps
T1039 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1055086991 Aug 01 06:20:40 PM PDT 24 Aug 01 06:20:43 PM PDT 24 100030792 ps
T1040 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2631784249 Aug 01 06:20:35 PM PDT 24 Aug 01 06:20:39 PM PDT 24 175408628 ps
T1041 /workspace/coverage/cover_reg_top/4.edn_intr_test.1424414981 Aug 01 06:20:33 PM PDT 24 Aug 01 06:20:34 PM PDT 24 62578039 ps
T1042 /workspace/coverage/cover_reg_top/5.edn_intr_test.1300700463 Aug 01 06:20:36 PM PDT 24 Aug 01 06:20:37 PM PDT 24 25444572 ps
T1043 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1413163366 Aug 01 06:20:38 PM PDT 24 Aug 01 06:20:40 PM PDT 24 29196615 ps
T1044 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1583972713 Aug 01 06:20:38 PM PDT 24 Aug 01 06:20:40 PM PDT 24 43732225 ps
T1045 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.8440598 Aug 01 06:20:30 PM PDT 24 Aug 01 06:20:31 PM PDT 24 60896825 ps
T1046 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.783559883 Aug 01 06:20:29 PM PDT 24 Aug 01 06:20:30 PM PDT 24 137857975 ps
T1047 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3653698209 Aug 01 06:20:33 PM PDT 24 Aug 01 06:20:34 PM PDT 24 16950493 ps
T1048 /workspace/coverage/cover_reg_top/34.edn_intr_test.1900515252 Aug 01 06:20:40 PM PDT 24 Aug 01 06:20:42 PM PDT 24 29479457 ps
T263 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1405228731 Aug 01 06:20:45 PM PDT 24 Aug 01 06:20:46 PM PDT 24 21517664 ps
T1049 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1282820247 Aug 01 06:20:40 PM PDT 24 Aug 01 06:20:41 PM PDT 24 21575032 ps
T294 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2264240185 Aug 01 06:20:31 PM PDT 24 Aug 01 06:20:33 PM PDT 24 55661924 ps
T1050 /workspace/coverage/cover_reg_top/9.edn_intr_test.425441860 Aug 01 06:20:38 PM PDT 24 Aug 01 06:20:39 PM PDT 24 59149738 ps
T1051 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2041632551 Aug 01 06:20:49 PM PDT 24 Aug 01 06:20:52 PM PDT 24 148777083 ps
T1052 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3974583503 Aug 01 06:20:50 PM PDT 24 Aug 01 06:20:51 PM PDT 24 37407715 ps
T1053 /workspace/coverage/cover_reg_top/7.edn_intr_test.18706956 Aug 01 06:20:38 PM PDT 24 Aug 01 06:20:39 PM PDT 24 94022914 ps
T1054 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3803459261 Aug 01 06:20:31 PM PDT 24 Aug 01 06:20:33 PM PDT 24 207503756 ps
T1055 /workspace/coverage/cover_reg_top/15.edn_intr_test.311528974 Aug 01 06:20:39 PM PDT 24 Aug 01 06:20:40 PM PDT 24 38558870 ps
T1056 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2502373135 Aug 01 06:20:29 PM PDT 24 Aug 01 06:20:31 PM PDT 24 48165712 ps
T1057 /workspace/coverage/cover_reg_top/0.edn_intr_test.3476439987 Aug 01 06:20:33 PM PDT 24 Aug 01 06:20:34 PM PDT 24 17774695 ps
T1058 /workspace/coverage/cover_reg_top/42.edn_intr_test.1108803137 Aug 01 06:20:48 PM PDT 24 Aug 01 06:20:49 PM PDT 24 19119729 ps
T1059 /workspace/coverage/cover_reg_top/14.edn_intr_test.3139610577 Aug 01 06:20:46 PM PDT 24 Aug 01 06:20:47 PM PDT 24 30604196 ps
T1060 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1571880071 Aug 01 06:20:35 PM PDT 24 Aug 01 06:20:36 PM PDT 24 103401045 ps
T1061 /workspace/coverage/cover_reg_top/38.edn_intr_test.3751289563 Aug 01 06:20:49 PM PDT 24 Aug 01 06:20:50 PM PDT 24 40077020 ps
T1062 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2178636769 Aug 01 06:20:29 PM PDT 24 Aug 01 06:20:33 PM PDT 24 267129700 ps
T1063 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3880727573 Aug 01 06:20:27 PM PDT 24 Aug 01 06:20:29 PM PDT 24 95968219 ps
T1064 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.837546009 Aug 01 06:20:45 PM PDT 24 Aug 01 06:20:46 PM PDT 24 58009411 ps
T295 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2674871481 Aug 01 06:20:39 PM PDT 24 Aug 01 06:20:42 PM PDT 24 401863807 ps
T1065 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.622437225 Aug 01 06:20:27 PM PDT 24 Aug 01 06:20:29 PM PDT 24 141119787 ps
T1066 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4045062643 Aug 01 06:20:39 PM PDT 24 Aug 01 06:20:40 PM PDT 24 21158345 ps
T1067 /workspace/coverage/cover_reg_top/9.edn_tl_errors.697096610 Aug 01 06:20:38 PM PDT 24 Aug 01 06:20:41 PM PDT 24 298080354 ps
T1068 /workspace/coverage/cover_reg_top/1.edn_tl_errors.2580168257 Aug 01 06:20:25 PM PDT 24 Aug 01 06:20:28 PM PDT 24 67854435 ps
T1069 /workspace/coverage/cover_reg_top/23.edn_intr_test.3675643282 Aug 01 06:20:45 PM PDT 24 Aug 01 06:20:46 PM PDT 24 24833800 ps
T1070 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1815039864 Aug 01 06:20:27 PM PDT 24 Aug 01 06:20:28 PM PDT 24 41457110 ps
T1071 /workspace/coverage/cover_reg_top/1.edn_csr_rw.4267197595 Aug 01 06:20:32 PM PDT 24 Aug 01 06:20:33 PM PDT 24 89023461 ps
T1072 /workspace/coverage/cover_reg_top/44.edn_intr_test.2922649221 Aug 01 06:20:48 PM PDT 24 Aug 01 06:20:50 PM PDT 24 58367288 ps
T1073 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2353939854 Aug 01 06:20:40 PM PDT 24 Aug 01 06:20:43 PM PDT 24 122243550 ps
T1074 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3176946712 Aug 01 06:20:37 PM PDT 24 Aug 01 06:20:38 PM PDT 24 53373793 ps
T1075 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.106344795 Aug 01 06:20:45 PM PDT 24 Aug 01 06:20:46 PM PDT 24 29962882 ps
T1076 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.914269215 Aug 01 06:20:44 PM PDT 24 Aug 01 06:20:45 PM PDT 24 48283571 ps
T1077 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1580453462 Aug 01 06:20:43 PM PDT 24 Aug 01 06:20:45 PM PDT 24 13934529 ps
T1078 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3313299720 Aug 01 06:20:28 PM PDT 24 Aug 01 06:20:32 PM PDT 24 100608250 ps
T1079 /workspace/coverage/cover_reg_top/6.edn_intr_test.3967945299 Aug 01 06:20:40 PM PDT 24 Aug 01 06:20:41 PM PDT 24 75482976 ps
T1080 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1048311068 Aug 01 06:20:44 PM PDT 24 Aug 01 06:20:46 PM PDT 24 79018560 ps
T1081 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1002015132 Aug 01 06:20:35 PM PDT 24 Aug 01 06:20:36 PM PDT 24 41339019 ps
T1082 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2941280397 Aug 01 06:20:36 PM PDT 24 Aug 01 06:20:38 PM PDT 24 22778138 ps
T1083 /workspace/coverage/cover_reg_top/33.edn_intr_test.2652075198 Aug 01 06:20:46 PM PDT 24 Aug 01 06:20:47 PM PDT 24 88599150 ps
T1084 /workspace/coverage/cover_reg_top/5.edn_tl_errors.605726106 Aug 01 06:20:35 PM PDT 24 Aug 01 06:20:38 PM PDT 24 274918280 ps
T1085 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3339418526 Aug 01 06:20:49 PM PDT 24 Aug 01 06:20:50 PM PDT 24 74656254 ps
T1086 /workspace/coverage/cover_reg_top/35.edn_intr_test.1851205367 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:48 PM PDT 24 70374263 ps
T296 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.987696017 Aug 01 06:20:35 PM PDT 24 Aug 01 06:20:36 PM PDT 24 166130304 ps
T1087 /workspace/coverage/cover_reg_top/37.edn_intr_test.976740166 Aug 01 06:20:48 PM PDT 24 Aug 01 06:20:49 PM PDT 24 40436182 ps
T1088 /workspace/coverage/cover_reg_top/47.edn_intr_test.920450183 Aug 01 06:20:44 PM PDT 24 Aug 01 06:20:45 PM PDT 24 19638745 ps
T1089 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1144659983 Aug 01 06:20:39 PM PDT 24 Aug 01 06:20:40 PM PDT 24 32171942 ps
T1090 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3967745701 Aug 01 06:20:26 PM PDT 24 Aug 01 06:20:28 PM PDT 24 124291587 ps
T1091 /workspace/coverage/cover_reg_top/32.edn_intr_test.3298456565 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:48 PM PDT 24 45239091 ps
T1092 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1668021604 Aug 01 06:20:34 PM PDT 24 Aug 01 06:20:37 PM PDT 24 230266772 ps
T1093 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2136441825 Aug 01 06:20:40 PM PDT 24 Aug 01 06:20:43 PM PDT 24 257814391 ps
T1094 /workspace/coverage/cover_reg_top/36.edn_intr_test.2106152812 Aug 01 06:20:46 PM PDT 24 Aug 01 06:20:48 PM PDT 24 17291399 ps
T1095 /workspace/coverage/cover_reg_top/28.edn_intr_test.920835173 Aug 01 06:20:42 PM PDT 24 Aug 01 06:20:43 PM PDT 24 21315052 ps
T1096 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3875762546 Aug 01 06:20:39 PM PDT 24 Aug 01 06:20:41 PM PDT 24 139768349 ps
T1097 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3596613510 Aug 01 06:20:37 PM PDT 24 Aug 01 06:20:38 PM PDT 24 141675831 ps
T1098 /workspace/coverage/cover_reg_top/45.edn_intr_test.569755014 Aug 01 06:20:48 PM PDT 24 Aug 01 06:20:49 PM PDT 24 18424702 ps
T1099 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.381694990 Aug 01 06:20:38 PM PDT 24 Aug 01 06:20:40 PM PDT 24 24744235 ps
T1100 /workspace/coverage/cover_reg_top/18.edn_intr_test.840381615 Aug 01 06:20:45 PM PDT 24 Aug 01 06:20:46 PM PDT 24 46074488 ps
T1101 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.614622909 Aug 01 06:20:37 PM PDT 24 Aug 01 06:20:39 PM PDT 24 29428717 ps
T264 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3882130865 Aug 01 06:20:39 PM PDT 24 Aug 01 06:20:40 PM PDT 24 46495478 ps
T1102 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.206823291 Aug 01 06:20:41 PM PDT 24 Aug 01 06:20:43 PM PDT 24 30622416 ps
T1103 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3187538772 Aug 01 06:20:46 PM PDT 24 Aug 01 06:20:49 PM PDT 24 234464125 ps
T268 /workspace/coverage/cover_reg_top/9.edn_csr_rw.764628685 Aug 01 06:20:34 PM PDT 24 Aug 01 06:20:35 PM PDT 24 21817473 ps
T1104 /workspace/coverage/cover_reg_top/43.edn_intr_test.1784542877 Aug 01 06:20:50 PM PDT 24 Aug 01 06:20:51 PM PDT 24 22380791 ps
T1105 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1806858749 Aug 01 06:20:28 PM PDT 24 Aug 01 06:20:29 PM PDT 24 24605034 ps
T1106 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2048220004 Aug 01 06:20:42 PM PDT 24 Aug 01 06:20:46 PM PDT 24 323946891 ps
T1107 /workspace/coverage/cover_reg_top/24.edn_intr_test.3553631924 Aug 01 06:20:50 PM PDT 24 Aug 01 06:20:51 PM PDT 24 12724236 ps
T1108 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.43321767 Aug 01 06:20:39 PM PDT 24 Aug 01 06:20:40 PM PDT 24 15827567 ps
T1109 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1750420372 Aug 01 06:20:41 PM PDT 24 Aug 01 06:20:44 PM PDT 24 41034362 ps
T1110 /workspace/coverage/cover_reg_top/3.edn_intr_test.1712804797 Aug 01 06:20:28 PM PDT 24 Aug 01 06:20:29 PM PDT 24 45704437 ps
T1111 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2176950407 Aug 01 06:20:38 PM PDT 24 Aug 01 06:20:39 PM PDT 24 17428600 ps
T265 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1736525455 Aug 01 06:21:06 PM PDT 24 Aug 01 06:21:08 PM PDT 24 135570711 ps
T1112 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1892864663 Aug 01 06:20:33 PM PDT 24 Aug 01 06:20:35 PM PDT 24 164381022 ps
T1113 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2960294366 Aug 01 06:20:40 PM PDT 24 Aug 01 06:20:41 PM PDT 24 166932057 ps
T1114 /workspace/coverage/cover_reg_top/14.edn_csr_rw.636074772 Aug 01 06:20:40 PM PDT 24 Aug 01 06:20:42 PM PDT 24 23798707 ps
T1115 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2592071701 Aug 01 06:20:26 PM PDT 24 Aug 01 06:20:29 PM PDT 24 94722166 ps
T1116 /workspace/coverage/cover_reg_top/17.edn_intr_test.280627599 Aug 01 06:20:39 PM PDT 24 Aug 01 06:20:40 PM PDT 24 29680277 ps
T1117 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1071132615 Aug 01 06:20:31 PM PDT 24 Aug 01 06:20:33 PM PDT 24 182250192 ps
T1118 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3949974931 Aug 01 06:20:32 PM PDT 24 Aug 01 06:20:34 PM PDT 24 132560303 ps
T1119 /workspace/coverage/cover_reg_top/10.edn_tl_errors.118832777 Aug 01 06:20:35 PM PDT 24 Aug 01 06:20:38 PM PDT 24 270940948 ps
T1120 /workspace/coverage/cover_reg_top/46.edn_intr_test.3842642580 Aug 01 06:20:45 PM PDT 24 Aug 01 06:20:47 PM PDT 24 15964404 ps
T1121 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1066367009 Aug 01 06:20:38 PM PDT 24 Aug 01 06:20:40 PM PDT 24 72189410 ps
T1122 /workspace/coverage/cover_reg_top/12.edn_intr_test.3578772959 Aug 01 06:20:38 PM PDT 24 Aug 01 06:20:39 PM PDT 24 16839212 ps
T1123 /workspace/coverage/cover_reg_top/39.edn_intr_test.3883160128 Aug 01 06:20:47 PM PDT 24 Aug 01 06:20:48 PM PDT 24 70377775 ps
T1124 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1309540387 Aug 01 06:20:42 PM PDT 24 Aug 01 06:20:43 PM PDT 24 13040122 ps
T266 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3189886377 Aug 01 06:20:33 PM PDT 24 Aug 01 06:20:34 PM PDT 24 50867113 ps
T1125 /workspace/coverage/cover_reg_top/6.edn_csr_rw.207100131 Aug 01 06:20:36 PM PDT 24 Aug 01 06:20:37 PM PDT 24 12396106 ps

Test location /workspace/coverage/default/257.edn_genbits.2223412280
Short name T8
Test name
Test status
Simulation time 210506548 ps
CPU time 2.62 seconds
Started Aug 01 06:23:34 PM PDT 24
Finished Aug 01 06:23:37 PM PDT 24
Peak memory 219924 kb
Host smart-04993fb7-ed02-4976-a573-8ce8060abe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223412280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2223412280
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.263118880
Short name T21
Test name
Test status
Simulation time 119398218716 ps
CPU time 787.29 seconds
Started Aug 01 06:22:24 PM PDT 24
Finished Aug 01 06:35:32 PM PDT 24
Peak memory 223616 kb
Host smart-704d22f7-d824-4b37-80c1-95df479abaf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263118880 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.263118880
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.edn_err.4278477807
Short name T5
Test name
Test status
Simulation time 37340733 ps
CPU time 0.93 seconds
Started Aug 01 06:22:49 PM PDT 24
Finished Aug 01 06:22:50 PM PDT 24
Peak memory 218248 kb
Host smart-de78ddd8-1453-4a99-ac7b-92a5bd623983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278477807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.4278477807
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/107.edn_alert.1541953171
Short name T19
Test name
Test status
Simulation time 86117854 ps
CPU time 1.17 seconds
Started Aug 01 06:22:58 PM PDT 24
Finished Aug 01 06:22:59 PM PDT 24
Peak memory 220352 kb
Host smart-4f0ff1c7-2f5a-4673-8656-4612047d89d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541953171 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.1541953171
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/6.edn_err.3800051206
Short name T7
Test name
Test status
Simulation time 30843602 ps
CPU time 1.19 seconds
Started Aug 01 06:21:19 PM PDT 24
Finished Aug 01 06:21:21 PM PDT 24
Peak memory 229796 kb
Host smart-793f6d51-adba-4391-a392-08c1a5c78ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800051206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3800051206
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/32.edn_stress_all.1897968738
Short name T41
Test name
Test status
Simulation time 227181561 ps
CPU time 4.63 seconds
Started Aug 01 06:22:03 PM PDT 24
Finished Aug 01 06:22:07 PM PDT 24
Peak memory 215308 kb
Host smart-9d384577-4f0a-48c2-9aae-a06995e5e1ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897968738 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1897968738
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_genbits.155974085
Short name T62
Test name
Test status
Simulation time 125268255 ps
CPU time 1.51 seconds
Started Aug 01 06:22:01 PM PDT 24
Finished Aug 01 06:22:03 PM PDT 24
Peak memory 220068 kb
Host smart-59479965-c028-4a11-9c61-ab9ba0fcc8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155974085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.155974085
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_alert.1977289238
Short name T135
Test name
Test status
Simulation time 135930014 ps
CPU time 1.1 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 218912 kb
Host smart-61ea4623-d6ff-4340-bb64-23a67fe16485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977289238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1977289238
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3889188615
Short name T225
Test name
Test status
Simulation time 189872416685 ps
CPU time 813.96 seconds
Started Aug 01 06:21:42 PM PDT 24
Finished Aug 01 06:35:16 PM PDT 24
Peak memory 221584 kb
Host smart-ee5749a0-fda8-4d54-a151-20f23d452c0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889188615 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3889188615
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_intr.3309129983
Short name T82
Test name
Test status
Simulation time 27922630 ps
CPU time 0.98 seconds
Started Aug 01 06:22:16 PM PDT 24
Finished Aug 01 06:22:17 PM PDT 24
Peak memory 215916 kb
Host smart-28ad0bcb-252b-4ed9-9327-a90cd0eaa518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309129983 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3309129983
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/98.edn_alert.1351589478
Short name T211
Test name
Test status
Simulation time 29855940 ps
CPU time 1.28 seconds
Started Aug 01 06:22:48 PM PDT 24
Finished Aug 01 06:22:49 PM PDT 24
Peak memory 218536 kb
Host smart-a3878846-dbef-47d7-bf7a-6d939fda6c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351589478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.1351589478
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2500528022
Short name T51
Test name
Test status
Simulation time 27354102 ps
CPU time 1.12 seconds
Started Aug 01 06:21:59 PM PDT 24
Finished Aug 01 06:22:01 PM PDT 24
Peak memory 216764 kb
Host smart-5ff1375e-3a61-46a5-b5c3-c5fabaa890eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500528022 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2500528022
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_regwen.2075800941
Short name T76
Test name
Test status
Simulation time 21264058 ps
CPU time 0.94 seconds
Started Aug 01 06:21:10 PM PDT 24
Finished Aug 01 06:21:11 PM PDT 24
Peak memory 207064 kb
Host smart-74d24e6b-d6f6-4d7f-86bb-ae95850a500f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075800941 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2075800941
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2264240185
Short name T294
Test name
Test status
Simulation time 55661924 ps
CPU time 1.79 seconds
Started Aug 01 06:20:31 PM PDT 24
Finished Aug 01 06:20:33 PM PDT 24
Peak memory 206796 kb
Host smart-51ddb109-9a3e-431d-9716-f0e5f5309ac2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264240185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2264240185
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/22.edn_disable.2846655607
Short name T38
Test name
Test status
Simulation time 43443034 ps
CPU time 0.88 seconds
Started Aug 01 06:21:37 PM PDT 24
Finished Aug 01 06:21:38 PM PDT 24
Peak memory 216260 kb
Host smart-783dcb9c-85ac-4ee0-a38f-2d3a220586b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846655607 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2846655607
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/182.edn_alert.2533636968
Short name T59
Test name
Test status
Simulation time 269395829 ps
CPU time 1.09 seconds
Started Aug 01 06:23:07 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 219628 kb
Host smart-f6688101-f4ca-42e1-91d8-c8cd4e38c95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533636968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2533636968
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.620027582
Short name T261
Test name
Test status
Simulation time 30052497 ps
CPU time 0.88 seconds
Started Aug 01 06:20:36 PM PDT 24
Finished Aug 01 06:20:37 PM PDT 24
Peak memory 206420 kb
Host smart-aee92a6e-c705-436b-b6ac-f47061d89951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620027582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.620027582
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/default/5.edn_err.2673803245
Short name T128
Test name
Test status
Simulation time 32777779 ps
CPU time 0.95 seconds
Started Aug 01 06:21:16 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 215348 kb
Host smart-db51d466-027c-4f1d-8237-bbe90f5f7f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673803245 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2673803245
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/168.edn_alert.2108842208
Short name T212
Test name
Test status
Simulation time 40508634 ps
CPU time 1.14 seconds
Started Aug 01 06:23:12 PM PDT 24
Finished Aug 01 06:23:13 PM PDT 24
Peak memory 218744 kb
Host smart-3b6ff468-def1-484d-bc1e-38abbfa6faf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108842208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.2108842208
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/40.edn_disable.3069673660
Short name T94
Test name
Test status
Simulation time 94969459 ps
CPU time 0.89 seconds
Started Aug 01 06:22:12 PM PDT 24
Finished Aug 01 06:22:13 PM PDT 24
Peak memory 216288 kb
Host smart-56b2d54a-6e00-4848-9996-88bab5932234
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069673660 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3069673660
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.552621624
Short name T111
Test name
Test status
Simulation time 287882265 ps
CPU time 1.25 seconds
Started Aug 01 06:21:16 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 216984 kb
Host smart-0f948095-8345-43c7-8780-0efc54be307b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552621624 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.552621624
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.3555088680
Short name T56
Test name
Test status
Simulation time 23608960 ps
CPU time 0.96 seconds
Started Aug 01 06:21:05 PM PDT 24
Finished Aug 01 06:21:06 PM PDT 24
Peak memory 218552 kb
Host smart-ab11394d-0707-4366-beea-01dc97234fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555088680 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3555088680
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/1.edn_disable.619970355
Short name T123
Test name
Test status
Simulation time 14324451 ps
CPU time 0.92 seconds
Started Aug 01 06:21:14 PM PDT 24
Finished Aug 01 06:21:16 PM PDT 24
Peak memory 216384 kb
Host smart-a8a4491f-c8dd-4c92-8d77-f0f941bca48b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619970355 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.619970355
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1400570914
Short name T976
Test name
Test status
Simulation time 86393733 ps
CPU time 1.07 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:11 PM PDT 24
Peak memory 217012 kb
Host smart-b55ef8ab-3d7d-49bb-8f58-cc76fa527f56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400570914 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1400570914
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_intr.1222711754
Short name T91
Test name
Test status
Simulation time 32874284 ps
CPU time 0.89 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:21:36 PM PDT 24
Peak memory 215620 kb
Host smart-93117541-2de0-4eac-8d8e-b80790f6ccbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222711754 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1222711754
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/76.edn_alert.1305790144
Short name T186
Test name
Test status
Simulation time 23858031 ps
CPU time 1.12 seconds
Started Aug 01 06:22:30 PM PDT 24
Finished Aug 01 06:22:31 PM PDT 24
Peak memory 218424 kb
Host smart-802ad89a-425e-4686-9eab-6be29fc28eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305790144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1305790144
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/194.edn_alert.14541360
Short name T140
Test name
Test status
Simulation time 39319288 ps
CPU time 1.17 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 219560 kb
Host smart-836f4d0e-89d7-4217-b0df-fa3f97a8d81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14541360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.14541360
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert.3139755750
Short name T250
Test name
Test status
Simulation time 141498981 ps
CPU time 1.27 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:28 PM PDT 24
Peak memory 215656 kb
Host smart-9c8f28c5-2211-4442-944f-16a1650fbec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139755750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3139755750
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.431917379
Short name T154
Test name
Test status
Simulation time 108799705 ps
CPU time 1.23 seconds
Started Aug 01 06:21:22 PM PDT 24
Finished Aug 01 06:21:24 PM PDT 24
Peak memory 218084 kb
Host smart-66482d01-ff09-42d4-a90c-a57cffaa1535
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431917379 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.431917379
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/162.edn_genbits.269489913
Short name T1
Test name
Test status
Simulation time 41257512 ps
CPU time 1.19 seconds
Started Aug 01 06:23:01 PM PDT 24
Finished Aug 01 06:23:03 PM PDT 24
Peak memory 217288 kb
Host smart-0807ae81-67c4-4a30-990d-f95645b692ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269489913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.269489913
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_genbits.3686605563
Short name T358
Test name
Test status
Simulation time 20498096 ps
CPU time 1.18 seconds
Started Aug 01 06:22:46 PM PDT 24
Finished Aug 01 06:22:47 PM PDT 24
Peak memory 218748 kb
Host smart-69314f19-4c21-46b4-b401-71c0755c850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686605563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3686605563
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_alert.327165291
Short name T148
Test name
Test status
Simulation time 39194674 ps
CPU time 1.15 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:15 PM PDT 24
Peak memory 220360 kb
Host smart-05d541bb-5e8a-4840-9f86-4c6d8929ed2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327165291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.327165291
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/131.edn_alert.1184188213
Short name T193
Test name
Test status
Simulation time 55908941 ps
CPU time 1.26 seconds
Started Aug 01 06:22:53 PM PDT 24
Finished Aug 01 06:22:54 PM PDT 24
Peak memory 220796 kb
Host smart-acd17c6b-1c95-44c9-96ff-cab855c21d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184188213 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1184188213
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/151.edn_alert.1515555105
Short name T142
Test name
Test status
Simulation time 109807001 ps
CPU time 1.13 seconds
Started Aug 01 06:23:00 PM PDT 24
Finished Aug 01 06:23:01 PM PDT 24
Peak memory 218588 kb
Host smart-dacf111e-2bdd-4bfe-b83c-6653d481ce7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515555105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1515555105
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/153.edn_alert.1058329585
Short name T204
Test name
Test status
Simulation time 49780052 ps
CPU time 1.2 seconds
Started Aug 01 06:23:04 PM PDT 24
Finished Aug 01 06:23:06 PM PDT 24
Peak memory 218932 kb
Host smart-5f5d38cf-f4cd-49dc-a8a8-5a6b72b3c1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058329585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1058329585
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/177.edn_alert.2289502993
Short name T213
Test name
Test status
Simulation time 41302377 ps
CPU time 1.3 seconds
Started Aug 01 06:23:08 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 215672 kb
Host smart-70b45c21-f9e9-4870-b4c4-2ff372d506a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289502993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2289502993
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/79.edn_alert.2156662613
Short name T158
Test name
Test status
Simulation time 163322140 ps
CPU time 1.28 seconds
Started Aug 01 06:22:33 PM PDT 24
Finished Aug 01 06:22:35 PM PDT 24
Peak memory 217820 kb
Host smart-1f81dcd8-b6cc-4c39-9fac-7a6497bee9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156662613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2156662613
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/26.edn_disable.1717634414
Short name T101
Test name
Test status
Simulation time 11986703 ps
CPU time 0.91 seconds
Started Aug 01 06:21:53 PM PDT 24
Finished Aug 01 06:21:54 PM PDT 24
Peak memory 216424 kb
Host smart-e9cd30db-3748-46d1-bafd-affd9968de80
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717634414 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1717634414
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/5.edn_intr.3222173447
Short name T44
Test name
Test status
Simulation time 26388931 ps
CPU time 1.06 seconds
Started Aug 01 06:21:14 PM PDT 24
Finished Aug 01 06:21:16 PM PDT 24
Peak memory 223956 kb
Host smart-c920d2a6-baf2-4dea-937c-7b206544b5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222173447 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3222173447
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2498409933
Short name T109
Test name
Test status
Simulation time 41034318 ps
CPU time 1.31 seconds
Started Aug 01 06:21:04 PM PDT 24
Finished Aug 01 06:21:05 PM PDT 24
Peak memory 217076 kb
Host smart-2581c3e9-9b7a-4a48-bb8a-8f8ce99d2582
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498409933 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2498409933
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/109.edn_alert.3573910746
Short name T642
Test name
Test status
Simulation time 82915463 ps
CPU time 1.18 seconds
Started Aug 01 06:22:51 PM PDT 24
Finished Aug 01 06:22:52 PM PDT 24
Peak memory 219400 kb
Host smart-ba600955-6038-4f3a-91fc-2662a5c0a379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573910746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3573910746
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.637109299
Short name T97
Test name
Test status
Simulation time 19980529 ps
CPU time 0.86 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:28 PM PDT 24
Peak memory 216204 kb
Host smart-02678f1a-b5ae-4ce6-94a3-c42d4f5f4959
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637109299 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.637109299
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3640900757
Short name T178
Test name
Test status
Simulation time 44424820 ps
CPU time 1.35 seconds
Started Aug 01 06:21:38 PM PDT 24
Finished Aug 01 06:21:39 PM PDT 24
Peak memory 216780 kb
Host smart-c1250b64-3289-4abb-95f2-e2df38fe68a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640900757 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3640900757
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3933758948
Short name T206
Test name
Test status
Simulation time 18874215 ps
CPU time 1.13 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 223984 kb
Host smart-70cf12b3-beeb-463c-b09c-df02ee76389c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933758948 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3933758948
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/143.edn_alert.952328899
Short name T866
Test name
Test status
Simulation time 32614128 ps
CPU time 1.18 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 219524 kb
Host smart-6a18baf8-5ee9-48f9-ad12-c42883bbd40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952328899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.952328899
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.501360519
Short name T118
Test name
Test status
Simulation time 58815759 ps
CPU time 1.24 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:28 PM PDT 24
Peak memory 216944 kb
Host smart-cfbbf1c0-7ba3-494e-8903-730b4accebf7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501360519 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.501360519
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.679229031
Short name T121
Test name
Test status
Simulation time 25545968 ps
CPU time 0.94 seconds
Started Aug 01 06:21:20 PM PDT 24
Finished Aug 01 06:21:21 PM PDT 24
Peak memory 219424 kb
Host smart-2b4086d9-bc90-4384-85bd-20949e98f456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679229031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.679229031
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/33.edn_disable.1510792565
Short name T93
Test name
Test status
Simulation time 82435762 ps
CPU time 0.83 seconds
Started Aug 01 06:22:06 PM PDT 24
Finished Aug 01 06:22:07 PM PDT 24
Peak memory 216228 kb
Host smart-e846cee5-7026-46cd-87f7-cf8f87b93add
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510792565 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1510792565
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable.395491503
Short name T116
Test name
Test status
Simulation time 81884947 ps
CPU time 0.85 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:28 PM PDT 24
Peak memory 216196 kb
Host smart-484d3f64-2774-49a4-9e59-62be94f64012
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395491503 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.395491503
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/203.edn_genbits.3438770278
Short name T67
Test name
Test status
Simulation time 117029603 ps
CPU time 1.29 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:22 PM PDT 24
Peak memory 219956 kb
Host smart-0233f510-e3e4-4a5c-9be5-4092488eb359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438770278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3438770278
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert_test.2281089610
Short name T354
Test name
Test status
Simulation time 48941974 ps
CPU time 0.96 seconds
Started Aug 01 06:21:08 PM PDT 24
Finished Aug 01 06:21:09 PM PDT 24
Peak memory 206688 kb
Host smart-ee6c4e4b-b3d2-4809-8c13-9617c1f89da2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281089610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2281089610
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3033498401
Short name T230
Test name
Test status
Simulation time 342369400026 ps
CPU time 1355.6 seconds
Started Aug 01 06:21:15 PM PDT 24
Finished Aug 01 06:43:51 PM PDT 24
Peak memory 223644 kb
Host smart-1aab248a-1dd2-4236-a384-cc606ec69a64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033498401 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3033498401
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.edn_genbits.1478576630
Short name T313
Test name
Test status
Simulation time 72591353 ps
CPU time 1.08 seconds
Started Aug 01 06:22:54 PM PDT 24
Finished Aug 01 06:22:56 PM PDT 24
Peak memory 219892 kb
Host smart-ed64e6bb-496d-4a80-9955-a5cbf11c641c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478576630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1478576630
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.2034904041
Short name T304
Test name
Test status
Simulation time 46097370 ps
CPU time 1.35 seconds
Started Aug 01 06:23:01 PM PDT 24
Finished Aug 01 06:23:03 PM PDT 24
Peak memory 218692 kb
Host smart-e6422364-4d8d-4d01-a721-26e18c1f4404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034904041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2034904041
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.61991359
Short name T70
Test name
Test status
Simulation time 28153684 ps
CPU time 1.37 seconds
Started Aug 01 06:23:21 PM PDT 24
Finished Aug 01 06:23:22 PM PDT 24
Peak memory 218528 kb
Host smart-e1cf1d31-c27e-48ed-93fa-56efd17cd0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61991359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.61991359
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.208148536
Short name T90
Test name
Test status
Simulation time 21370106 ps
CPU time 1.11 seconds
Started Aug 01 06:21:24 PM PDT 24
Finished Aug 01 06:21:25 PM PDT 24
Peak memory 215700 kb
Host smart-ab835ef7-9142-4246-9caa-e0e00577b099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208148536 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.208148536
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/166.edn_genbits.730621245
Short name T16
Test name
Test status
Simulation time 171239810 ps
CPU time 3.23 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 219632 kb
Host smart-f0752a85-ab00-4478-9781-5c35560084c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730621245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.730621245
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_genbits.1675538608
Short name T568
Test name
Test status
Simulation time 178010262 ps
CPU time 1.63 seconds
Started Aug 01 06:21:15 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 217484 kb
Host smart-e47e40b9-147e-4502-a537-9b19c5e6c987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675538608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1675538608
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3760198992
Short name T519
Test name
Test status
Simulation time 28163727 ps
CPU time 1.31 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:22 PM PDT 24
Peak memory 219764 kb
Host smart-ec5a6783-b5b5-4718-b7c4-8d78c1fa8703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760198992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3760198992
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1003364414
Short name T366
Test name
Test status
Simulation time 71478667 ps
CPU time 0.88 seconds
Started Aug 01 06:21:36 PM PDT 24
Finished Aug 01 06:21:37 PM PDT 24
Peak memory 215300 kb
Host smart-f61c570a-c9a1-46ef-a6d2-86e059a37bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003364414 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1003364414
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2502373135
Short name T1056
Test name
Test status
Simulation time 48165712 ps
CPU time 1.77 seconds
Started Aug 01 06:20:29 PM PDT 24
Finished Aug 01 06:20:31 PM PDT 24
Peak memory 206704 kb
Host smart-85d47e95-b39e-4191-bd60-22a06b6204d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502373135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2502373135
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2388763432
Short name T293
Test name
Test status
Simulation time 152866795 ps
CPU time 1.66 seconds
Started Aug 01 06:20:34 PM PDT 24
Finished Aug 01 06:20:36 PM PDT 24
Peak memory 214904 kb
Host smart-6dd72a39-2386-449e-948f-d296eb332dbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388763432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2388763432
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3953858753
Short name T734
Test name
Test status
Simulation time 60728443 ps
CPU time 1.13 seconds
Started Aug 01 06:21:12 PM PDT 24
Finished Aug 01 06:21:13 PM PDT 24
Peak memory 217424 kb
Host smart-18866a25-15a7-43e0-ac5a-9376afb38e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953858753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3953858753
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.191544573
Short name T889
Test name
Test status
Simulation time 51195576 ps
CPU time 1.44 seconds
Started Aug 01 06:22:59 PM PDT 24
Finished Aug 01 06:23:01 PM PDT 24
Peak memory 218896 kb
Host smart-f19f94b9-fb44-4707-ad8a-a7a48d7e6249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191544573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.191544573
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1057215098
Short name T288
Test name
Test status
Simulation time 71588779 ps
CPU time 1.34 seconds
Started Aug 01 06:22:55 PM PDT 24
Finished Aug 01 06:22:56 PM PDT 24
Peak memory 219692 kb
Host smart-47edd206-dcea-4477-a8ed-989eb7151ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057215098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1057215098
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.1983287494
Short name T318
Test name
Test status
Simulation time 50371068 ps
CPU time 1.86 seconds
Started Aug 01 06:22:56 PM PDT 24
Finished Aug 01 06:22:58 PM PDT 24
Peak memory 220168 kb
Host smart-bc27f620-815f-449e-89c1-c64fc663ea22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983287494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1983287494
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1595606884
Short name T733
Test name
Test status
Simulation time 73882129648 ps
CPU time 1748.12 seconds
Started Aug 01 06:21:26 PM PDT 24
Finished Aug 01 06:50:35 PM PDT 24
Peak memory 224776 kb
Host smart-42e98a89-33ac-4c64-81f9-8258234d3449
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595606884 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1595606884
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.edn_genbits.3224872207
Short name T316
Test name
Test status
Simulation time 49570046 ps
CPU time 1.31 seconds
Started Aug 01 06:23:02 PM PDT 24
Finished Aug 01 06:23:03 PM PDT 24
Peak memory 219048 kb
Host smart-f41c2918-652b-4e89-a9ec-6a3da355d265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224872207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3224872207
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.858442134
Short name T311
Test name
Test status
Simulation time 53615374 ps
CPU time 1.49 seconds
Started Aug 01 06:23:07 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 218952 kb
Host smart-edf2544f-dfe7-4d52-8c28-99ebabca27a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858442134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.858442134
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_genbits.1798147979
Short name T853
Test name
Test status
Simulation time 38976096 ps
CPU time 1.21 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:33 PM PDT 24
Peak memory 218660 kb
Host smart-12eb04db-d56d-4684-bf10-c6955ea7329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798147979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1798147979
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1442877956
Short name T251
Test name
Test status
Simulation time 106002463 ps
CPU time 1.13 seconds
Started Aug 01 06:22:00 PM PDT 24
Finished Aug 01 06:22:01 PM PDT 24
Peak memory 218692 kb
Host smart-66967797-e8b4-4b53-adaf-3cb26c30836f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442877956 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1442877956
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_intr.3036142155
Short name T89
Test name
Test status
Simulation time 47530332 ps
CPU time 0.91 seconds
Started Aug 01 06:21:21 PM PDT 24
Finished Aug 01 06:21:22 PM PDT 24
Peak memory 215720 kb
Host smart-3a7482f5-9d36-4011-9d30-a8ed89ca11c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036142155 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3036142155
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1267054928
Short name T214
Test name
Test status
Simulation time 220389842 ps
CPU time 1.05 seconds
Started Aug 01 06:21:24 PM PDT 24
Finished Aug 01 06:21:25 PM PDT 24
Peak memory 219696 kb
Host smart-5cdf8712-d32c-466a-a2e5-fc953b7f757e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267054928 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1267054928
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/129.edn_alert.1289299386
Short name T563
Test name
Test status
Simulation time 25824560 ps
CPU time 1.19 seconds
Started Aug 01 06:22:54 PM PDT 24
Finished Aug 01 06:22:55 PM PDT 24
Peak memory 218784 kb
Host smart-5e9caf64-ebdc-49a7-87de-72ed5a67679e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289299386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.1289299386
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/138.edn_alert.3625634253
Short name T145
Test name
Test status
Simulation time 89107242 ps
CPU time 1.32 seconds
Started Aug 01 06:23:01 PM PDT 24
Finished Aug 01 06:23:02 PM PDT 24
Peak memory 218644 kb
Host smart-c8aa94d5-6cce-4337-a18f-1393941ad45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625634253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3625634253
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3189886377
Short name T266
Test name
Test status
Simulation time 50867113 ps
CPU time 1.05 seconds
Started Aug 01 06:20:33 PM PDT 24
Finished Aug 01 06:20:34 PM PDT 24
Peak memory 206592 kb
Host smart-398ae8df-152e-4e63-8ec7-ade0ef372010
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189886377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3189886377
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2134124651
Short name T1033
Test name
Test status
Simulation time 93379125 ps
CPU time 3.21 seconds
Started Aug 01 06:20:31 PM PDT 24
Finished Aug 01 06:20:35 PM PDT 24
Peak memory 206576 kb
Host smart-a8557468-5d7f-4af2-bd58-22d60872fb87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134124651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2134124651
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1002015132
Short name T1081
Test name
Test status
Simulation time 41339019 ps
CPU time 0.91 seconds
Started Aug 01 06:20:35 PM PDT 24
Finished Aug 01 06:20:36 PM PDT 24
Peak memory 206312 kb
Host smart-07c80dc3-f1f8-4e51-817f-00c4247fa8a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002015132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1002015132
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.380524596
Short name T995
Test name
Test status
Simulation time 22855586 ps
CPU time 1.19 seconds
Started Aug 01 06:20:33 PM PDT 24
Finished Aug 01 06:20:35 PM PDT 24
Peak memory 215020 kb
Host smart-0390d4d8-76dc-4b3f-80a5-54ebda3c5726
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380524596 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.380524596
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2176950407
Short name T1111
Test name
Test status
Simulation time 17428600 ps
CPU time 0.84 seconds
Started Aug 01 06:20:38 PM PDT 24
Finished Aug 01 06:20:39 PM PDT 24
Peak memory 206364 kb
Host smart-67e2f513-be69-4647-81e2-445a9cff0372
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176950407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2176950407
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3476439987
Short name T1057
Test name
Test status
Simulation time 17774695 ps
CPU time 0.83 seconds
Started Aug 01 06:20:33 PM PDT 24
Finished Aug 01 06:20:34 PM PDT 24
Peak memory 206448 kb
Host smart-c7436d41-8c41-43c2-98db-2f35bdab4520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476439987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3476439987
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.622437225
Short name T1065
Test name
Test status
Simulation time 141119787 ps
CPU time 1.13 seconds
Started Aug 01 06:20:27 PM PDT 24
Finished Aug 01 06:20:29 PM PDT 24
Peak memory 206776 kb
Host smart-bf70792a-0385-4320-910e-bc00e881fac9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622437225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.622437225
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3313299720
Short name T1078
Test name
Test status
Simulation time 100608250 ps
CPU time 3.75 seconds
Started Aug 01 06:20:28 PM PDT 24
Finished Aug 01 06:20:32 PM PDT 24
Peak memory 215028 kb
Host smart-d429ab3b-4e9b-4a39-8051-15bc06c3f422
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313299720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3313299720
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1736525455
Short name T265
Test name
Test status
Simulation time 135570711 ps
CPU time 1.48 seconds
Started Aug 01 06:21:06 PM PDT 24
Finished Aug 01 06:21:08 PM PDT 24
Peak memory 206488 kb
Host smart-07cf7be0-1bf2-4a2d-ae3d-28e4d4f25400
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736525455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1736525455
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2178636769
Short name T1062
Test name
Test status
Simulation time 267129700 ps
CPU time 3.57 seconds
Started Aug 01 06:20:29 PM PDT 24
Finished Aug 01 06:20:33 PM PDT 24
Peak memory 206524 kb
Host smart-32876853-1fbe-4894-b167-76bed80d728d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178636769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2178636769
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.8440598
Short name T1045
Test name
Test status
Simulation time 60896825 ps
CPU time 0.88 seconds
Started Aug 01 06:20:30 PM PDT 24
Finished Aug 01 06:20:31 PM PDT 24
Peak memory 206576 kb
Host smart-1cd0e7f8-8938-4dfb-8237-b4486c988c7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8440598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.8440598
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3980770973
Short name T1004
Test name
Test status
Simulation time 54550738 ps
CPU time 1.97 seconds
Started Aug 01 06:20:31 PM PDT 24
Finished Aug 01 06:20:34 PM PDT 24
Peak memory 219868 kb
Host smart-37026ce8-b6bd-4d6e-a7c2-0d28031a7f3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980770973 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3980770973
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.4267197595
Short name T1071
Test name
Test status
Simulation time 89023461 ps
CPU time 0.86 seconds
Started Aug 01 06:20:32 PM PDT 24
Finished Aug 01 06:20:33 PM PDT 24
Peak memory 206404 kb
Host smart-982fe724-9380-45f5-86a5-72e1a3c8dc50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267197595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.4267197595
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2419919268
Short name T996
Test name
Test status
Simulation time 12565844 ps
CPU time 0.87 seconds
Started Aug 01 06:20:28 PM PDT 24
Finished Aug 01 06:20:29 PM PDT 24
Peak memory 206596 kb
Host smart-e714de75-080d-4c94-aced-3835ece1b498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419919268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2419919268
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.783559883
Short name T1046
Test name
Test status
Simulation time 137857975 ps
CPU time 1.12 seconds
Started Aug 01 06:20:29 PM PDT 24
Finished Aug 01 06:20:30 PM PDT 24
Peak memory 206956 kb
Host smart-688d48ed-c681-4f2f-bdcd-7ef871783b35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783559883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.783559883
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2580168257
Short name T1068
Test name
Test status
Simulation time 67854435 ps
CPU time 2.75 seconds
Started Aug 01 06:20:25 PM PDT 24
Finished Aug 01 06:20:28 PM PDT 24
Peak memory 215032 kb
Host smart-de17efe1-bd8c-4301-992d-62b41e333fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580168257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2580168257
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4242990495
Short name T1029
Test name
Test status
Simulation time 387140495 ps
CPU time 1.23 seconds
Started Aug 01 06:20:34 PM PDT 24
Finished Aug 01 06:20:36 PM PDT 24
Peak memory 214940 kb
Host smart-eafa9ac5-f67a-4a84-89b3-5808ba4d7175
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242990495 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.4242990495
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1309540387
Short name T1124
Test name
Test status
Simulation time 13040122 ps
CPU time 0.88 seconds
Started Aug 01 06:20:42 PM PDT 24
Finished Aug 01 06:20:43 PM PDT 24
Peak memory 206572 kb
Host smart-f6622410-2bbe-4709-90ba-5b6f1d1af3c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309540387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1309540387
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1636959956
Short name T1012
Test name
Test status
Simulation time 15984659 ps
CPU time 0.8 seconds
Started Aug 01 06:20:34 PM PDT 24
Finished Aug 01 06:20:35 PM PDT 24
Peak memory 206780 kb
Host smart-e1a996bd-5d6a-43b7-bb2d-0df12deeded6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636959956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1636959956
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1171525237
Short name T270
Test name
Test status
Simulation time 31195757 ps
CPU time 1.34 seconds
Started Aug 01 06:20:42 PM PDT 24
Finished Aug 01 06:20:44 PM PDT 24
Peak memory 206784 kb
Host smart-e7ee1f2c-a47f-409c-b515-b8a849e5b20e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171525237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1171525237
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.118832777
Short name T1119
Test name
Test status
Simulation time 270940948 ps
CPU time 2.3 seconds
Started Aug 01 06:20:35 PM PDT 24
Finished Aug 01 06:20:38 PM PDT 24
Peak memory 214980 kb
Host smart-341fe9f5-30ba-4b69-8d5a-2a381c6cdc52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118832777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.118832777
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.987696017
Short name T296
Test name
Test status
Simulation time 166130304 ps
CPU time 1.47 seconds
Started Aug 01 06:20:35 PM PDT 24
Finished Aug 01 06:20:36 PM PDT 24
Peak memory 207028 kb
Host smart-c1f28e66-f71f-4c6d-a0e8-aec244ca5707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987696017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.987696017
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.914269215
Short name T1076
Test name
Test status
Simulation time 48283571 ps
CPU time 1.4 seconds
Started Aug 01 06:20:44 PM PDT 24
Finished Aug 01 06:20:45 PM PDT 24
Peak memory 218988 kb
Host smart-1daaad9f-9ee6-42a4-98dd-c58e3a2e76d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914269215 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.914269215
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1571880071
Short name T1060
Test name
Test status
Simulation time 103401045 ps
CPU time 0.83 seconds
Started Aug 01 06:20:35 PM PDT 24
Finished Aug 01 06:20:36 PM PDT 24
Peak memory 206392 kb
Host smart-29e61700-1862-4851-b4ef-c6685790685b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571880071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1571880071
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.413760384
Short name T1007
Test name
Test status
Simulation time 14980827 ps
CPU time 0.9 seconds
Started Aug 01 06:20:38 PM PDT 24
Finished Aug 01 06:20:39 PM PDT 24
Peak memory 206544 kb
Host smart-46cbe7f5-ef5f-45b3-826c-a14e61797c18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413760384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.413760384
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3176946712
Short name T1074
Test name
Test status
Simulation time 53373793 ps
CPU time 1.25 seconds
Started Aug 01 06:20:37 PM PDT 24
Finished Aug 01 06:20:38 PM PDT 24
Peak memory 206664 kb
Host smart-545a21be-2820-4f86-b79b-6be73d4d4dbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176946712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3176946712
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2136441825
Short name T1093
Test name
Test status
Simulation time 257814391 ps
CPU time 2.01 seconds
Started Aug 01 06:20:40 PM PDT 24
Finished Aug 01 06:20:43 PM PDT 24
Peak memory 214908 kb
Host smart-6a5100ff-f036-4459-9135-778fd368a44b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136441825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2136441825
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3803459261
Short name T1054
Test name
Test status
Simulation time 207503756 ps
CPU time 1.65 seconds
Started Aug 01 06:20:31 PM PDT 24
Finished Aug 01 06:20:33 PM PDT 24
Peak memory 214984 kb
Host smart-3644a4a3-42f0-4def-ae91-4e93ff4e3e1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803459261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3803459261
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2440766974
Short name T1000
Test name
Test status
Simulation time 42224617 ps
CPU time 1.1 seconds
Started Aug 01 06:20:52 PM PDT 24
Finished Aug 01 06:20:53 PM PDT 24
Peak memory 217680 kb
Host smart-6f26c3cb-3a16-4c3d-945d-0602838af1ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440766974 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2440766974
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2775659842
Short name T272
Test name
Test status
Simulation time 46349986 ps
CPU time 0.83 seconds
Started Aug 01 06:20:38 PM PDT 24
Finished Aug 01 06:20:39 PM PDT 24
Peak memory 206388 kb
Host smart-51570705-706b-4248-bb96-710297425ff3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775659842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2775659842
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3578772959
Short name T1122
Test name
Test status
Simulation time 16839212 ps
CPU time 0.88 seconds
Started Aug 01 06:20:38 PM PDT 24
Finished Aug 01 06:20:39 PM PDT 24
Peak memory 206564 kb
Host smart-e801c130-06ff-4dd9-a044-4bb7d8f2f06e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578772959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3578772959
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.206823291
Short name T1102
Test name
Test status
Simulation time 30622416 ps
CPU time 1.41 seconds
Started Aug 01 06:20:41 PM PDT 24
Finished Aug 01 06:20:43 PM PDT 24
Peak memory 206684 kb
Host smart-897f7d3f-4e96-4e74-98ac-3f89514670eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206823291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.206823291
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3187538772
Short name T1103
Test name
Test status
Simulation time 234464125 ps
CPU time 2.97 seconds
Started Aug 01 06:20:46 PM PDT 24
Finished Aug 01 06:20:49 PM PDT 24
Peak memory 214956 kb
Host smart-34ce80f2-4532-4095-92aa-0c43e5764388
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187538772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3187538772
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3523688423
Short name T1013
Test name
Test status
Simulation time 33415671 ps
CPU time 1.08 seconds
Started Aug 01 06:20:38 PM PDT 24
Finished Aug 01 06:20:39 PM PDT 24
Peak memory 217140 kb
Host smart-21d876b1-ba50-486e-a4f1-522e0b6c9f95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523688423 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3523688423
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3413039162
Short name T262
Test name
Test status
Simulation time 12058724 ps
CPU time 0.89 seconds
Started Aug 01 06:20:38 PM PDT 24
Finished Aug 01 06:20:39 PM PDT 24
Peak memory 206552 kb
Host smart-aefe9888-fe97-4d5c-8edc-b5fde01309a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413039162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3413039162
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.712290350
Short name T1024
Test name
Test status
Simulation time 97309549 ps
CPU time 0.8 seconds
Started Aug 01 06:20:39 PM PDT 24
Finished Aug 01 06:20:40 PM PDT 24
Peak memory 206600 kb
Host smart-e94979e6-7543-4052-9553-c7f28ae01ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712290350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.712290350
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2546772533
Short name T254
Test name
Test status
Simulation time 110738107 ps
CPU time 1.2 seconds
Started Aug 01 06:20:35 PM PDT 24
Finished Aug 01 06:20:36 PM PDT 24
Peak memory 206692 kb
Host smart-719211e0-3262-4dba-8376-3992cb6399d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546772533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2546772533
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2048220004
Short name T1106
Test name
Test status
Simulation time 323946891 ps
CPU time 3.15 seconds
Started Aug 01 06:20:42 PM PDT 24
Finished Aug 01 06:20:46 PM PDT 24
Peak memory 215040 kb
Host smart-ac5104a4-ba7a-4b87-aa68-9bfae55ed5e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048220004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2048220004
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3086091329
Short name T1017
Test name
Test status
Simulation time 138580326 ps
CPU time 1.43 seconds
Started Aug 01 06:20:42 PM PDT 24
Finished Aug 01 06:20:44 PM PDT 24
Peak memory 207032 kb
Host smart-ba7bf44c-4876-4294-8b4f-263858f5d04d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086091329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3086091329
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3558580360
Short name T1015
Test name
Test status
Simulation time 40377830 ps
CPU time 1.15 seconds
Started Aug 01 06:20:40 PM PDT 24
Finished Aug 01 06:20:42 PM PDT 24
Peak memory 215032 kb
Host smart-445d44b0-e451-4c0f-93f4-0d6e5ee09054
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558580360 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3558580360
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.636074772
Short name T1114
Test name
Test status
Simulation time 23798707 ps
CPU time 0.86 seconds
Started Aug 01 06:20:40 PM PDT 24
Finished Aug 01 06:20:42 PM PDT 24
Peak memory 206580 kb
Host smart-8ab69c1f-ba8f-42c2-a537-91fb62a9b808
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636074772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.636074772
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3139610577
Short name T1059
Test name
Test status
Simulation time 30604196 ps
CPU time 0.79 seconds
Started Aug 01 06:20:46 PM PDT 24
Finished Aug 01 06:20:47 PM PDT 24
Peak memory 206380 kb
Host smart-722cbe1c-6df8-495d-a39a-992ba36c190b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139610577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3139610577
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4036778910
Short name T275
Test name
Test status
Simulation time 65199447 ps
CPU time 1.22 seconds
Started Aug 01 06:20:39 PM PDT 24
Finished Aug 01 06:20:41 PM PDT 24
Peak memory 206760 kb
Host smart-fa1852ce-5e0c-4623-9126-b0b5599af0de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036778910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.4036778910
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3171026051
Short name T1021
Test name
Test status
Simulation time 37236000 ps
CPU time 1.97 seconds
Started Aug 01 06:20:40 PM PDT 24
Finished Aug 01 06:20:42 PM PDT 24
Peak memory 214980 kb
Host smart-a8ae9783-4f3b-45d5-874c-fea25802de65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171026051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3171026051
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1332481680
Short name T220
Test name
Test status
Simulation time 77251562 ps
CPU time 1.48 seconds
Started Aug 01 06:20:34 PM PDT 24
Finished Aug 01 06:20:35 PM PDT 24
Peak memory 214968 kb
Host smart-87902470-f390-462c-a1c8-b0b62e639382
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332481680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1332481680
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.381694990
Short name T1099
Test name
Test status
Simulation time 24744235 ps
CPU time 1.27 seconds
Started Aug 01 06:20:38 PM PDT 24
Finished Aug 01 06:20:40 PM PDT 24
Peak memory 214968 kb
Host smart-df9bde02-059f-447f-b34e-2acebaefcdf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381694990 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.381694990
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.509668364
Short name T269
Test name
Test status
Simulation time 46913223 ps
CPU time 0.89 seconds
Started Aug 01 06:20:37 PM PDT 24
Finished Aug 01 06:20:38 PM PDT 24
Peak memory 206572 kb
Host smart-8722c3cb-f146-4159-a2d6-acef899487e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509668364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.509668364
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.311528974
Short name T1055
Test name
Test status
Simulation time 38558870 ps
CPU time 0.84 seconds
Started Aug 01 06:20:39 PM PDT 24
Finished Aug 01 06:20:40 PM PDT 24
Peak memory 206592 kb
Host smart-046f1e6d-273c-45e3-8da6-24945b5611d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311528974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.311528974
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3155915690
Short name T1010
Test name
Test status
Simulation time 22666107 ps
CPU time 1.1 seconds
Started Aug 01 06:20:37 PM PDT 24
Finished Aug 01 06:20:38 PM PDT 24
Peak memory 206692 kb
Host smart-f7bfdc55-29b6-49e6-a830-8c39084fc170
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155915690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3155915690
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1413163366
Short name T1043
Test name
Test status
Simulation time 29196615 ps
CPU time 2.08 seconds
Started Aug 01 06:20:38 PM PDT 24
Finished Aug 01 06:20:40 PM PDT 24
Peak memory 215060 kb
Host smart-c818626e-bb0f-4acc-9fbc-9abc3f790ace
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413163366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1413163366
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2674871481
Short name T295
Test name
Test status
Simulation time 401863807 ps
CPU time 2.58 seconds
Started Aug 01 06:20:39 PM PDT 24
Finished Aug 01 06:20:42 PM PDT 24
Peak memory 206788 kb
Host smart-833ed9d2-922e-4636-8be3-34d26a2c5086
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674871481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2674871481
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2960294366
Short name T1113
Test name
Test status
Simulation time 166932057 ps
CPU time 1.43 seconds
Started Aug 01 06:20:40 PM PDT 24
Finished Aug 01 06:20:41 PM PDT 24
Peak memory 214960 kb
Host smart-0da9bfa9-6976-40d2-bd0e-9d4f14b9653f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960294366 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2960294366
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2785187149
Short name T1005
Test name
Test status
Simulation time 44456046 ps
CPU time 0.89 seconds
Started Aug 01 06:20:35 PM PDT 24
Finished Aug 01 06:20:36 PM PDT 24
Peak memory 206572 kb
Host smart-d52f20f6-bceb-41f6-952a-bd67ca407c39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785187149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2785187149
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.210592587
Short name T994
Test name
Test status
Simulation time 14788287 ps
CPU time 0.86 seconds
Started Aug 01 06:20:40 PM PDT 24
Finished Aug 01 06:20:41 PM PDT 24
Peak memory 206508 kb
Host smart-5c98178f-533f-45ff-9bf1-0b0f68e348a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210592587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.210592587
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1580453462
Short name T1077
Test name
Test status
Simulation time 13934529 ps
CPU time 0.93 seconds
Started Aug 01 06:20:43 PM PDT 24
Finished Aug 01 06:20:45 PM PDT 24
Peak memory 206784 kb
Host smart-249c9bc2-d39b-4fb3-a66e-66194efe311d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580453462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1580453462
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2953209549
Short name T1036
Test name
Test status
Simulation time 2458098400 ps
CPU time 4.49 seconds
Started Aug 01 06:20:40 PM PDT 24
Finished Aug 01 06:20:45 PM PDT 24
Peak memory 215012 kb
Host smart-af93c9b4-579b-4529-a728-22b5eceb3a31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953209549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2953209549
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1055086991
Short name T1039
Test name
Test status
Simulation time 100030792 ps
CPU time 2.6 seconds
Started Aug 01 06:20:40 PM PDT 24
Finished Aug 01 06:20:43 PM PDT 24
Peak memory 214952 kb
Host smart-ea44ae6a-fb43-4487-a3fd-db70bc37546e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055086991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1055086991
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.106344795
Short name T1075
Test name
Test status
Simulation time 29962882 ps
CPU time 1.11 seconds
Started Aug 01 06:20:45 PM PDT 24
Finished Aug 01 06:20:46 PM PDT 24
Peak memory 215000 kb
Host smart-dcd4ede8-dd0d-40d8-95d8-f78f9bcf1834
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106344795 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.106344795
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1320965814
Short name T1038
Test name
Test status
Simulation time 42473675 ps
CPU time 0.86 seconds
Started Aug 01 06:20:37 PM PDT 24
Finished Aug 01 06:20:38 PM PDT 24
Peak memory 206596 kb
Host smart-57a0e99a-8234-41eb-8f9b-a4fc9cb22d35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320965814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1320965814
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.280627599
Short name T1116
Test name
Test status
Simulation time 29680277 ps
CPU time 0.86 seconds
Started Aug 01 06:20:39 PM PDT 24
Finished Aug 01 06:20:40 PM PDT 24
Peak memory 206608 kb
Host smart-a7b87854-a9a2-447a-8306-c5a0458c6f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280627599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.280627599
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.43321767
Short name T1108
Test name
Test status
Simulation time 15827567 ps
CPU time 1 seconds
Started Aug 01 06:20:39 PM PDT 24
Finished Aug 01 06:20:40 PM PDT 24
Peak memory 206788 kb
Host smart-18f1b65e-4ec0-4077-9729-5bcb0eb1fa4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43321767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_out
standing.43321767
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2631784249
Short name T1040
Test name
Test status
Simulation time 175408628 ps
CPU time 3.9 seconds
Started Aug 01 06:20:35 PM PDT 24
Finished Aug 01 06:20:39 PM PDT 24
Peak memory 214980 kb
Host smart-07479c61-cdc3-48f8-a5c6-9fa11d484cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631784249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2631784249
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2353939854
Short name T1073
Test name
Test status
Simulation time 122243550 ps
CPU time 2.64 seconds
Started Aug 01 06:20:40 PM PDT 24
Finished Aug 01 06:20:43 PM PDT 24
Peak memory 206872 kb
Host smart-b5a0d217-ef16-4542-a99e-ecde995c54b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353939854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2353939854
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4078782399
Short name T1022
Test name
Test status
Simulation time 49730508 ps
CPU time 1.3 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:49 PM PDT 24
Peak memory 217384 kb
Host smart-bb87cd57-dd09-4608-a67d-383e26338f32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078782399 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.4078782399
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1405228731
Short name T263
Test name
Test status
Simulation time 21517664 ps
CPU time 0.87 seconds
Started Aug 01 06:20:45 PM PDT 24
Finished Aug 01 06:20:46 PM PDT 24
Peak memory 206656 kb
Host smart-c15e5535-1b11-4327-b663-5cde9445e419
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405228731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1405228731
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.840381615
Short name T1100
Test name
Test status
Simulation time 46074488 ps
CPU time 0.9 seconds
Started Aug 01 06:20:45 PM PDT 24
Finished Aug 01 06:20:46 PM PDT 24
Peak memory 206424 kb
Host smart-0ebdf5d2-cdeb-45a6-9425-cd93cad928c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840381615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.840381615
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3974583503
Short name T1052
Test name
Test status
Simulation time 37407715 ps
CPU time 1.51 seconds
Started Aug 01 06:20:50 PM PDT 24
Finished Aug 01 06:20:51 PM PDT 24
Peak memory 206696 kb
Host smart-2592252f-1637-486a-aedf-b62f2559e2cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974583503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3974583503
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3257643517
Short name T1019
Test name
Test status
Simulation time 42174431 ps
CPU time 2.57 seconds
Started Aug 01 06:20:42 PM PDT 24
Finished Aug 01 06:20:44 PM PDT 24
Peak memory 214980 kb
Host smart-cc7d5c11-8888-4208-a624-46e3b23c7f3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257643517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3257643517
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1059749480
Short name T222
Test name
Test status
Simulation time 158127927 ps
CPU time 2.34 seconds
Started Aug 01 06:20:46 PM PDT 24
Finished Aug 01 06:20:49 PM PDT 24
Peak memory 214876 kb
Host smart-a604c555-8211-4842-9662-cf21f3d0c93c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059749480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1059749480
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1073758633
Short name T1011
Test name
Test status
Simulation time 347133841 ps
CPU time 1.16 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 215020 kb
Host smart-1d26ffbe-473c-413a-b886-c0b8fb06fa44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073758633 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1073758633
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.93007215
Short name T255
Test name
Test status
Simulation time 45986242 ps
CPU time 0.93 seconds
Started Aug 01 06:20:42 PM PDT 24
Finished Aug 01 06:20:43 PM PDT 24
Peak memory 206548 kb
Host smart-96d878bd-fe06-4fce-a9f7-e5760dbafbfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93007215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.93007215
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.326390312
Short name T1014
Test name
Test status
Simulation time 61085844 ps
CPU time 0.85 seconds
Started Aug 01 06:20:45 PM PDT 24
Finished Aug 01 06:20:46 PM PDT 24
Peak memory 206416 kb
Host smart-5a34aac1-93c6-401e-a43b-1d6fbb98fc85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326390312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.326390312
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.837546009
Short name T1064
Test name
Test status
Simulation time 58009411 ps
CPU time 1.1 seconds
Started Aug 01 06:20:45 PM PDT 24
Finished Aug 01 06:20:46 PM PDT 24
Peak memory 206764 kb
Host smart-56d48789-e71e-4fab-bf10-18cfe892941d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837546009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.837546009
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1750420372
Short name T1109
Test name
Test status
Simulation time 41034362 ps
CPU time 2.86 seconds
Started Aug 01 06:20:41 PM PDT 24
Finished Aug 01 06:20:44 PM PDT 24
Peak memory 214972 kb
Host smart-3fc00b07-7b2e-4bc9-b439-1154a9e0e5f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750420372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1750420372
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3557880811
Short name T1027
Test name
Test status
Simulation time 164600702 ps
CPU time 1.58 seconds
Started Aug 01 06:20:44 PM PDT 24
Finished Aug 01 06:20:46 PM PDT 24
Peak memory 206660 kb
Host smart-3a186abd-bc10-4a25-9f8a-cff7f02c235d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557880811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3557880811
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1806858749
Short name T1105
Test name
Test status
Simulation time 24605034 ps
CPU time 1.2 seconds
Started Aug 01 06:20:28 PM PDT 24
Finished Aug 01 06:20:29 PM PDT 24
Peak memory 206548 kb
Host smart-39b65ced-e6cc-4bbe-95bc-2bc7a3fcc294
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806858749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1806858749
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1668021604
Short name T1092
Test name
Test status
Simulation time 230266772 ps
CPU time 3.29 seconds
Started Aug 01 06:20:34 PM PDT 24
Finished Aug 01 06:20:37 PM PDT 24
Peak memory 206628 kb
Host smart-cc6ec6af-1fd4-4cc2-b7c9-2bdf124a0ae0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668021604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1668021604
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1020917162
Short name T259
Test name
Test status
Simulation time 84248653 ps
CPU time 0.9 seconds
Started Aug 01 06:20:30 PM PDT 24
Finished Aug 01 06:20:31 PM PDT 24
Peak memory 206500 kb
Host smart-0ddb97bc-3475-4f24-8207-08df4db30363
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020917162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1020917162
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4144838102
Short name T1025
Test name
Test status
Simulation time 130627367 ps
CPU time 1.6 seconds
Started Aug 01 06:20:37 PM PDT 24
Finished Aug 01 06:20:39 PM PDT 24
Peak memory 214948 kb
Host smart-40f3b233-9905-4b03-9200-bfca3a8124bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144838102 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.4144838102
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1195539738
Short name T1016
Test name
Test status
Simulation time 12275775 ps
CPU time 0.94 seconds
Started Aug 01 06:20:28 PM PDT 24
Finished Aug 01 06:20:29 PM PDT 24
Peak memory 206564 kb
Host smart-6d8d1872-b0c4-43ca-9d0b-e2454a1f988f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195539738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1195539738
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2601091353
Short name T1026
Test name
Test status
Simulation time 49601297 ps
CPU time 0.9 seconds
Started Aug 01 06:20:30 PM PDT 24
Finished Aug 01 06:20:31 PM PDT 24
Peak memory 206568 kb
Host smart-145cc199-c0b6-4440-ac6f-05c743c2d58c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601091353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2601091353
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1863238251
Short name T1037
Test name
Test status
Simulation time 27619283 ps
CPU time 1.01 seconds
Started Aug 01 06:20:26 PM PDT 24
Finished Aug 01 06:20:27 PM PDT 24
Peak memory 206748 kb
Host smart-20c1be6d-a410-4ee7-ba48-d26dedd76631
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863238251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1863238251
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2865268457
Short name T1009
Test name
Test status
Simulation time 201143744 ps
CPU time 2.14 seconds
Started Aug 01 06:20:26 PM PDT 24
Finished Aug 01 06:20:28 PM PDT 24
Peak memory 215016 kb
Host smart-f80e25af-84cf-4aff-b10b-e740aeec6b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865268457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2865268457
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1815039864
Short name T1070
Test name
Test status
Simulation time 41457110 ps
CPU time 1.53 seconds
Started Aug 01 06:20:27 PM PDT 24
Finished Aug 01 06:20:28 PM PDT 24
Peak memory 206872 kb
Host smart-d1ef1c2f-a95b-4ab4-a6a4-680072a956ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815039864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1815039864
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1330442166
Short name T997
Test name
Test status
Simulation time 19629877 ps
CPU time 0.77 seconds
Started Aug 01 06:20:43 PM PDT 24
Finished Aug 01 06:20:44 PM PDT 24
Peak memory 206408 kb
Host smart-05969656-9344-404a-9721-2edcafffe7fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330442166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1330442166
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.779051426
Short name T998
Test name
Test status
Simulation time 27044932 ps
CPU time 0.85 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 206588 kb
Host smart-afdc770c-087d-4251-a728-cd7d0234e6ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779051426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.779051426
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3060116804
Short name T992
Test name
Test status
Simulation time 14996451 ps
CPU time 0.87 seconds
Started Aug 01 06:20:45 PM PDT 24
Finished Aug 01 06:20:46 PM PDT 24
Peak memory 206432 kb
Host smart-84cd4171-e408-436d-b468-a1f8b2fafd9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060116804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3060116804
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3675643282
Short name T1069
Test name
Test status
Simulation time 24833800 ps
CPU time 0.86 seconds
Started Aug 01 06:20:45 PM PDT 24
Finished Aug 01 06:20:46 PM PDT 24
Peak memory 206520 kb
Host smart-a9191e30-8200-4324-82be-4ce1f2402478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675643282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3675643282
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3553631924
Short name T1107
Test name
Test status
Simulation time 12724236 ps
CPU time 0.86 seconds
Started Aug 01 06:20:50 PM PDT 24
Finished Aug 01 06:20:51 PM PDT 24
Peak memory 206556 kb
Host smart-cc3cfd59-732d-40a0-97ea-f6189526e81d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553631924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3553631924
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3458753781
Short name T1034
Test name
Test status
Simulation time 18128785 ps
CPU time 0.82 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:53 PM PDT 24
Peak memory 206392 kb
Host smart-b9a3142a-7bc7-4873-9316-ca92ec14c440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458753781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3458753781
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2755317702
Short name T1031
Test name
Test status
Simulation time 25643485 ps
CPU time 0.79 seconds
Started Aug 01 06:20:46 PM PDT 24
Finished Aug 01 06:20:47 PM PDT 24
Peak memory 206632 kb
Host smart-7ff1d81f-dbe4-4b58-9294-e3ac68df016f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755317702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2755317702
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3421918566
Short name T1001
Test name
Test status
Simulation time 31518772 ps
CPU time 0.8 seconds
Started Aug 01 06:20:52 PM PDT 24
Finished Aug 01 06:20:53 PM PDT 24
Peak memory 206564 kb
Host smart-23b20f16-04ae-48d7-9cfd-2572d6838c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421918566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3421918566
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.920835173
Short name T1095
Test name
Test status
Simulation time 21315052 ps
CPU time 0.88 seconds
Started Aug 01 06:20:42 PM PDT 24
Finished Aug 01 06:20:43 PM PDT 24
Peak memory 206580 kb
Host smart-0349b4e9-20d8-45e5-a692-6f66fb05c70b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920835173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.920835173
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3233948250
Short name T1030
Test name
Test status
Simulation time 18894318 ps
CPU time 0.84 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 206596 kb
Host smart-4ba3ee97-913a-4eaa-95df-b0618fcda9a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233948250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3233948250
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.4206755579
Short name T260
Test name
Test status
Simulation time 172830814 ps
CPU time 1.22 seconds
Started Aug 01 06:20:32 PM PDT 24
Finished Aug 01 06:20:34 PM PDT 24
Peak memory 206600 kb
Host smart-60ab12e1-4796-42ba-b5fc-7492b9078b46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206755579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.4206755579
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1366446815
Short name T267
Test name
Test status
Simulation time 134949455 ps
CPU time 3.54 seconds
Started Aug 01 06:20:30 PM PDT 24
Finished Aug 01 06:20:33 PM PDT 24
Peak memory 206664 kb
Host smart-aa2366be-60e6-417d-9ce6-35bf1282129c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366446815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1366446815
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2405475717
Short name T258
Test name
Test status
Simulation time 29735042 ps
CPU time 0.98 seconds
Started Aug 01 06:20:25 PM PDT 24
Finished Aug 01 06:20:26 PM PDT 24
Peak memory 206556 kb
Host smart-43a59860-2ad2-45d4-ad07-63bf8a92044d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405475717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2405475717
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3739436640
Short name T1032
Test name
Test status
Simulation time 46292501 ps
CPU time 1.03 seconds
Started Aug 01 06:20:35 PM PDT 24
Finished Aug 01 06:20:36 PM PDT 24
Peak memory 215180 kb
Host smart-4f43e9d9-90cc-4207-9880-a42005aff2c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739436640 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3739436640
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3647311043
Short name T273
Test name
Test status
Simulation time 20511239 ps
CPU time 0.8 seconds
Started Aug 01 06:20:34 PM PDT 24
Finished Aug 01 06:20:35 PM PDT 24
Peak memory 206392 kb
Host smart-cb6e6ec7-93e1-4f44-922c-c346cb3ac9bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647311043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3647311043
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1712804797
Short name T1110
Test name
Test status
Simulation time 45704437 ps
CPU time 0.87 seconds
Started Aug 01 06:20:28 PM PDT 24
Finished Aug 01 06:20:29 PM PDT 24
Peak memory 206596 kb
Host smart-e2518b64-df0d-4bbc-8b8c-4c383b1d74aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712804797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1712804797
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1892864663
Short name T1112
Test name
Test status
Simulation time 164381022 ps
CPU time 1.44 seconds
Started Aug 01 06:20:33 PM PDT 24
Finished Aug 01 06:20:35 PM PDT 24
Peak memory 206752 kb
Host smart-a2a28518-0d7a-4585-b15f-1a60a07c8454
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892864663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1892864663
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1324843652
Short name T1028
Test name
Test status
Simulation time 89960257 ps
CPU time 1.84 seconds
Started Aug 01 06:20:36 PM PDT 24
Finished Aug 01 06:20:38 PM PDT 24
Peak memory 215156 kb
Host smart-eb98b0fc-a4e7-427e-bfbc-38c3de90ba98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324843652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1324843652
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2592071701
Short name T1115
Test name
Test status
Simulation time 94722166 ps
CPU time 2.5 seconds
Started Aug 01 06:20:26 PM PDT 24
Finished Aug 01 06:20:29 PM PDT 24
Peak memory 206724 kb
Host smart-9f020c5b-5cff-4b57-82da-d1b503e1c944
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592071701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2592071701
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2321121874
Short name T1002
Test name
Test status
Simulation time 19255836 ps
CPU time 0.79 seconds
Started Aug 01 06:20:45 PM PDT 24
Finished Aug 01 06:20:45 PM PDT 24
Peak memory 206404 kb
Host smart-823747ef-afac-43e8-a982-d6045f48cee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321121874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2321121874
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.638565985
Short name T1003
Test name
Test status
Simulation time 22067383 ps
CPU time 0.84 seconds
Started Aug 01 06:20:41 PM PDT 24
Finished Aug 01 06:20:42 PM PDT 24
Peak memory 206596 kb
Host smart-ac7dc948-8436-4887-9efa-2526c3cdd25e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638565985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.638565985
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3298456565
Short name T1091
Test name
Test status
Simulation time 45239091 ps
CPU time 0.8 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 206364 kb
Host smart-5f2305fa-09be-41ed-bd24-c8d0aaa65630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298456565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3298456565
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2652075198
Short name T1083
Test name
Test status
Simulation time 88599150 ps
CPU time 0.86 seconds
Started Aug 01 06:20:46 PM PDT 24
Finished Aug 01 06:20:47 PM PDT 24
Peak memory 206596 kb
Host smart-c5a86562-e637-4aa9-89c1-37fa3a93f737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652075198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2652075198
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1900515252
Short name T1048
Test name
Test status
Simulation time 29479457 ps
CPU time 0.92 seconds
Started Aug 01 06:20:40 PM PDT 24
Finished Aug 01 06:20:42 PM PDT 24
Peak memory 206688 kb
Host smart-bb662c06-18ed-43eb-97c1-2ea4019e4bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900515252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1900515252
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1851205367
Short name T1086
Test name
Test status
Simulation time 70374263 ps
CPU time 0.79 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 206396 kb
Host smart-7c914a35-8f06-4531-89b3-b35c4a084529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851205367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1851205367
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2106152812
Short name T1094
Test name
Test status
Simulation time 17291399 ps
CPU time 1.03 seconds
Started Aug 01 06:20:46 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 206636 kb
Host smart-76e91400-d91b-47cf-85f7-3f4f68087747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106152812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2106152812
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.976740166
Short name T1087
Test name
Test status
Simulation time 40436182 ps
CPU time 0.8 seconds
Started Aug 01 06:20:48 PM PDT 24
Finished Aug 01 06:20:49 PM PDT 24
Peak memory 206588 kb
Host smart-6243a4fa-f77c-4260-ad75-568e4af1096a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976740166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.976740166
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3751289563
Short name T1061
Test name
Test status
Simulation time 40077020 ps
CPU time 0.81 seconds
Started Aug 01 06:20:49 PM PDT 24
Finished Aug 01 06:20:50 PM PDT 24
Peak memory 206364 kb
Host smart-fd0a219c-4d95-4d05-bf7f-6bbf3b58460d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751289563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3751289563
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3883160128
Short name T1123
Test name
Test status
Simulation time 70377775 ps
CPU time 0.92 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 206596 kb
Host smart-16339acd-20d0-4dc0-be3e-e524314d1380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883160128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3883160128
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3369725588
Short name T257
Test name
Test status
Simulation time 18647843 ps
CPU time 1.03 seconds
Started Aug 01 06:20:25 PM PDT 24
Finished Aug 01 06:20:26 PM PDT 24
Peak memory 206644 kb
Host smart-951edb22-51a7-4861-a94d-eb998c06575f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369725588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3369725588
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3967745701
Short name T1090
Test name
Test status
Simulation time 124291587 ps
CPU time 2.06 seconds
Started Aug 01 06:20:26 PM PDT 24
Finished Aug 01 06:20:28 PM PDT 24
Peak memory 206584 kb
Host smart-33638b89-231a-4eae-ae1d-fae8d276dbe0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967745701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3967745701
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3653698209
Short name T1047
Test name
Test status
Simulation time 16950493 ps
CPU time 0.89 seconds
Started Aug 01 06:20:33 PM PDT 24
Finished Aug 01 06:20:34 PM PDT 24
Peak memory 206764 kb
Host smart-ce1bb10c-a8b8-40fb-8500-f544f4e97247
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653698209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3653698209
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3880727573
Short name T1063
Test name
Test status
Simulation time 95968219 ps
CPU time 1.32 seconds
Started Aug 01 06:20:27 PM PDT 24
Finished Aug 01 06:20:29 PM PDT 24
Peak memory 215052 kb
Host smart-05177379-52d3-40ed-8f84-57a4402f8533
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880727573 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3880727573
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3046231665
Short name T1020
Test name
Test status
Simulation time 12157529 ps
CPU time 0.88 seconds
Started Aug 01 06:20:30 PM PDT 24
Finished Aug 01 06:20:31 PM PDT 24
Peak memory 206628 kb
Host smart-260c1183-bab9-4b00-87d0-e592046dceb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046231665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3046231665
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1424414981
Short name T1041
Test name
Test status
Simulation time 62578039 ps
CPU time 0.85 seconds
Started Aug 01 06:20:33 PM PDT 24
Finished Aug 01 06:20:34 PM PDT 24
Peak memory 206572 kb
Host smart-aa2448e3-ed43-4dd7-98ec-9742327f8d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424414981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1424414981
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2082444534
Short name T274
Test name
Test status
Simulation time 15098685 ps
CPU time 1.08 seconds
Started Aug 01 06:20:32 PM PDT 24
Finished Aug 01 06:20:33 PM PDT 24
Peak memory 206656 kb
Host smart-20996587-4567-4095-b0b4-44f735ec981a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082444534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2082444534
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1071132615
Short name T1117
Test name
Test status
Simulation time 182250192 ps
CPU time 1.67 seconds
Started Aug 01 06:20:31 PM PDT 24
Finished Aug 01 06:20:33 PM PDT 24
Peak memory 214984 kb
Host smart-b42e68e1-7b54-4c92-9b55-92611293415d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071132615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1071132615
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3954980692
Short name T292
Test name
Test status
Simulation time 273965072 ps
CPU time 5.07 seconds
Started Aug 01 06:20:25 PM PDT 24
Finished Aug 01 06:20:30 PM PDT 24
Peak memory 214904 kb
Host smart-c000f85d-01ed-4ffd-ac73-bfcd811656df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954980692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3954980692
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1544189209
Short name T1018
Test name
Test status
Simulation time 21001106 ps
CPU time 0.83 seconds
Started Aug 01 06:20:47 PM PDT 24
Finished Aug 01 06:20:48 PM PDT 24
Peak memory 206364 kb
Host smart-e4296f99-4077-4b65-8a56-86bc3702eb12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544189209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1544189209
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2300121791
Short name T1035
Test name
Test status
Simulation time 26439216 ps
CPU time 0.87 seconds
Started Aug 01 06:20:41 PM PDT 24
Finished Aug 01 06:20:42 PM PDT 24
Peak memory 206528 kb
Host smart-7e3e2ba2-dfc9-47f1-bb63-28a3447c3347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300121791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2300121791
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1108803137
Short name T1058
Test name
Test status
Simulation time 19119729 ps
CPU time 0.78 seconds
Started Aug 01 06:20:48 PM PDT 24
Finished Aug 01 06:20:49 PM PDT 24
Peak memory 206412 kb
Host smart-af16049a-a8e1-4b94-9ab1-3e63b03a2acf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108803137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1108803137
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1784542877
Short name T1104
Test name
Test status
Simulation time 22380791 ps
CPU time 0.92 seconds
Started Aug 01 06:20:50 PM PDT 24
Finished Aug 01 06:20:51 PM PDT 24
Peak memory 206560 kb
Host smart-00806544-1cbb-47cd-9a70-a03469430626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784542877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1784542877
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2922649221
Short name T1072
Test name
Test status
Simulation time 58367288 ps
CPU time 0.8 seconds
Started Aug 01 06:20:48 PM PDT 24
Finished Aug 01 06:20:50 PM PDT 24
Peak memory 206388 kb
Host smart-7af30f6f-b7b5-4f7f-bba1-9d434f7c6995
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922649221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2922649221
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.569755014
Short name T1098
Test name
Test status
Simulation time 18424702 ps
CPU time 0.84 seconds
Started Aug 01 06:20:48 PM PDT 24
Finished Aug 01 06:20:49 PM PDT 24
Peak memory 206400 kb
Host smart-5ab77afe-32b2-4062-915c-af0b7c5f15fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569755014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.569755014
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3842642580
Short name T1120
Test name
Test status
Simulation time 15964404 ps
CPU time 0.89 seconds
Started Aug 01 06:20:45 PM PDT 24
Finished Aug 01 06:20:47 PM PDT 24
Peak memory 206568 kb
Host smart-d01db15c-4132-4f76-904a-eca4e68a2781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842642580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3842642580
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.920450183
Short name T1088
Test name
Test status
Simulation time 19638745 ps
CPU time 0.81 seconds
Started Aug 01 06:20:44 PM PDT 24
Finished Aug 01 06:20:45 PM PDT 24
Peak memory 206352 kb
Host smart-15b596a9-9067-4a45-8aa6-4f6931c4fcd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920450183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.920450183
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3661226579
Short name T993
Test name
Test status
Simulation time 31697276 ps
CPU time 0.83 seconds
Started Aug 01 06:20:42 PM PDT 24
Finished Aug 01 06:20:43 PM PDT 24
Peak memory 206392 kb
Host smart-aeeae4bb-a40e-464d-a95f-c4251a0c0ab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661226579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3661226579
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.4221237974
Short name T1023
Test name
Test status
Simulation time 24105549 ps
CPU time 0.91 seconds
Started Aug 01 06:20:52 PM PDT 24
Finished Aug 01 06:20:53 PM PDT 24
Peak memory 206568 kb
Host smart-892096c2-d857-4caf-9b4b-a0f38d87a17e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221237974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.4221237974
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2941280397
Short name T1082
Test name
Test status
Simulation time 22778138 ps
CPU time 1.15 seconds
Started Aug 01 06:20:36 PM PDT 24
Finished Aug 01 06:20:38 PM PDT 24
Peak memory 216496 kb
Host smart-2078cfd4-f838-4787-a29b-ac1792714efb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941280397 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2941280397
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.591194887
Short name T256
Test name
Test status
Simulation time 25368294 ps
CPU time 0.84 seconds
Started Aug 01 06:20:53 PM PDT 24
Finished Aug 01 06:20:54 PM PDT 24
Peak memory 206556 kb
Host smart-4807e270-9acd-4568-aaf6-e01274efa648
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591194887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.591194887
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1300700463
Short name T1042
Test name
Test status
Simulation time 25444572 ps
CPU time 0.81 seconds
Started Aug 01 06:20:36 PM PDT 24
Finished Aug 01 06:20:37 PM PDT 24
Peak memory 206564 kb
Host smart-7ce1e562-98b0-4f1a-b819-78155e961f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300700463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1300700463
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1282820247
Short name T1049
Test name
Test status
Simulation time 21575032 ps
CPU time 1.05 seconds
Started Aug 01 06:20:40 PM PDT 24
Finished Aug 01 06:20:41 PM PDT 24
Peak memory 206764 kb
Host smart-745bad29-768f-4c9b-abdb-f87295cb9201
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282820247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1282820247
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.605726106
Short name T1084
Test name
Test status
Simulation time 274918280 ps
CPU time 2.66 seconds
Started Aug 01 06:20:35 PM PDT 24
Finished Aug 01 06:20:38 PM PDT 24
Peak memory 215040 kb
Host smart-67c6690a-246b-4756-b70a-0bd21bf2024f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605726106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.605726106
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1583972713
Short name T1044
Test name
Test status
Simulation time 43732225 ps
CPU time 1.6 seconds
Started Aug 01 06:20:38 PM PDT 24
Finished Aug 01 06:20:40 PM PDT 24
Peak memory 206820 kb
Host smart-b05310ad-3482-4e86-a782-794be39d3372
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583972713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1583972713
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1048311068
Short name T1080
Test name
Test status
Simulation time 79018560 ps
CPU time 1.28 seconds
Started Aug 01 06:20:44 PM PDT 24
Finished Aug 01 06:20:46 PM PDT 24
Peak memory 217540 kb
Host smart-b58e5903-dae9-40ea-b672-567ba575fba3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048311068 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1048311068
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.207100131
Short name T1125
Test name
Test status
Simulation time 12396106 ps
CPU time 0.88 seconds
Started Aug 01 06:20:36 PM PDT 24
Finished Aug 01 06:20:37 PM PDT 24
Peak memory 206548 kb
Host smart-58fdad53-79eb-4c54-98a4-449db949839c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207100131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.207100131
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3967945299
Short name T1079
Test name
Test status
Simulation time 75482976 ps
CPU time 0.89 seconds
Started Aug 01 06:20:40 PM PDT 24
Finished Aug 01 06:20:41 PM PDT 24
Peak memory 206520 kb
Host smart-2aefe383-1e27-4fb1-bf12-9ea9ce4dfeaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967945299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3967945299
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3731248221
Short name T276
Test name
Test status
Simulation time 131315562 ps
CPU time 1.47 seconds
Started Aug 01 06:20:42 PM PDT 24
Finished Aug 01 06:20:44 PM PDT 24
Peak memory 206652 kb
Host smart-b1141c9d-6718-4163-9845-8ed9596ebcb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731248221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3731248221
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3875762546
Short name T1096
Test name
Test status
Simulation time 139768349 ps
CPU time 1.52 seconds
Started Aug 01 06:20:39 PM PDT 24
Finished Aug 01 06:20:41 PM PDT 24
Peak memory 214988 kb
Host smart-f66fc0d7-6290-4079-a8e5-c7748a1bcf3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875762546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3875762546
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3339418526
Short name T1085
Test name
Test status
Simulation time 74656254 ps
CPU time 1.68 seconds
Started Aug 01 06:20:49 PM PDT 24
Finished Aug 01 06:20:50 PM PDT 24
Peak memory 206688 kb
Host smart-a1609da8-fc6e-4204-b705-b37acfdd3767
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339418526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3339418526
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3949974931
Short name T1118
Test name
Test status
Simulation time 132560303 ps
CPU time 1.35 seconds
Started Aug 01 06:20:32 PM PDT 24
Finished Aug 01 06:20:34 PM PDT 24
Peak memory 218896 kb
Host smart-9e61b32b-c3cc-44f0-88b9-ca10e07e7b17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949974931 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3949974931
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3882130865
Short name T264
Test name
Test status
Simulation time 46495478 ps
CPU time 0.9 seconds
Started Aug 01 06:20:39 PM PDT 24
Finished Aug 01 06:20:40 PM PDT 24
Peak memory 206528 kb
Host smart-256300af-f36f-4efc-a743-ba9317ea409f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882130865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3882130865
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.18706956
Short name T1053
Test name
Test status
Simulation time 94022914 ps
CPU time 0.9 seconds
Started Aug 01 06:20:38 PM PDT 24
Finished Aug 01 06:20:39 PM PDT 24
Peak memory 206588 kb
Host smart-905aa7d7-ffaf-48ee-867c-d863d30eed7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18706956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.18706956
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3038650396
Short name T271
Test name
Test status
Simulation time 164146451 ps
CPU time 1.04 seconds
Started Aug 01 06:20:37 PM PDT 24
Finished Aug 01 06:20:38 PM PDT 24
Peak memory 206696 kb
Host smart-3427ae35-dd2c-4bf2-a47a-491ca49ccfc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038650396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3038650396
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2041632551
Short name T1051
Test name
Test status
Simulation time 148777083 ps
CPU time 2.56 seconds
Started Aug 01 06:20:49 PM PDT 24
Finished Aug 01 06:20:52 PM PDT 24
Peak memory 215036 kb
Host smart-0d5d776a-5baf-493b-88ae-e074dbf11067
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041632551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2041632551
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3700391461
Short name T221
Test name
Test status
Simulation time 118213674 ps
CPU time 2.87 seconds
Started Aug 01 06:20:36 PM PDT 24
Finished Aug 01 06:20:39 PM PDT 24
Peak memory 206616 kb
Host smart-7a3f1099-0b4f-4374-9f64-33c6d8b45297
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700391461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3700391461
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.614622909
Short name T1101
Test name
Test status
Simulation time 29428717 ps
CPU time 1.81 seconds
Started Aug 01 06:20:37 PM PDT 24
Finished Aug 01 06:20:39 PM PDT 24
Peak memory 215072 kb
Host smart-2849e8bd-5a95-48be-b99c-c6d67e0458f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614622909 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.614622909
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.177936297
Short name T1006
Test name
Test status
Simulation time 30437079 ps
CPU time 0.8 seconds
Started Aug 01 06:20:40 PM PDT 24
Finished Aug 01 06:20:41 PM PDT 24
Peak memory 206408 kb
Host smart-1e3e86ba-fb6b-4b69-8659-aafa6376d138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177936297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.177936297
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1144659983
Short name T1089
Test name
Test status
Simulation time 32171942 ps
CPU time 1.14 seconds
Started Aug 01 06:20:39 PM PDT 24
Finished Aug 01 06:20:40 PM PDT 24
Peak memory 206652 kb
Host smart-ddde49ea-f24a-4c08-a6fd-761dc40f5dbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144659983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1144659983
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2001972498
Short name T1008
Test name
Test status
Simulation time 46103835 ps
CPU time 1.75 seconds
Started Aug 01 06:20:37 PM PDT 24
Finished Aug 01 06:20:39 PM PDT 24
Peak memory 218056 kb
Host smart-534222db-178b-41e0-91fc-88559baf9a5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001972498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2001972498
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3596613510
Short name T1097
Test name
Test status
Simulation time 141675831 ps
CPU time 1.4 seconds
Started Aug 01 06:20:37 PM PDT 24
Finished Aug 01 06:20:38 PM PDT 24
Peak memory 206984 kb
Host smart-443ff292-8c27-45bd-a087-a59d7b76bd98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596613510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3596613510
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3038135542
Short name T999
Test name
Test status
Simulation time 26771480 ps
CPU time 1.75 seconds
Started Aug 01 06:20:37 PM PDT 24
Finished Aug 01 06:20:39 PM PDT 24
Peak memory 215088 kb
Host smart-49f808b6-8be5-45ca-b463-5fcfd1cf585c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038135542 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3038135542
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.764628685
Short name T268
Test name
Test status
Simulation time 21817473 ps
CPU time 0.87 seconds
Started Aug 01 06:20:34 PM PDT 24
Finished Aug 01 06:20:35 PM PDT 24
Peak memory 206624 kb
Host smart-d8f20c50-b21e-4e88-8ea2-6843c55d6b34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764628685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.764628685
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.425441860
Short name T1050
Test name
Test status
Simulation time 59149738 ps
CPU time 0.87 seconds
Started Aug 01 06:20:38 PM PDT 24
Finished Aug 01 06:20:39 PM PDT 24
Peak memory 206576 kb
Host smart-244a6493-8891-4582-9207-2e727a2f9c83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425441860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.425441860
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4045062643
Short name T1066
Test name
Test status
Simulation time 21158345 ps
CPU time 0.9 seconds
Started Aug 01 06:20:39 PM PDT 24
Finished Aug 01 06:20:40 PM PDT 24
Peak memory 206704 kb
Host smart-4957f298-6801-4c73-b57e-73229beaf659
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045062643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.4045062643
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.697096610
Short name T1067
Test name
Test status
Simulation time 298080354 ps
CPU time 2.85 seconds
Started Aug 01 06:20:38 PM PDT 24
Finished Aug 01 06:20:41 PM PDT 24
Peak memory 215024 kb
Host smart-17a803b3-a14c-4a4b-b9fb-783704632322
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697096610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.697096610
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1066367009
Short name T1121
Test name
Test status
Simulation time 72189410 ps
CPU time 1.72 seconds
Started Aug 01 06:20:38 PM PDT 24
Finished Aug 01 06:20:40 PM PDT 24
Peak memory 214904 kb
Host smart-35460d0b-6b61-4350-a200-d800bfa1f681
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066367009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1066367009
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1411519948
Short name T829
Test name
Test status
Simulation time 87661042 ps
CPU time 1.25 seconds
Started Aug 01 06:21:07 PM PDT 24
Finished Aug 01 06:21:09 PM PDT 24
Peak memory 218600 kb
Host smart-29619c4a-3414-4336-9cc5-a0d2a2a7ae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411519948 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1411519948
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.1077237421
Short name T124
Test name
Test status
Simulation time 20624448 ps
CPU time 0.87 seconds
Started Aug 01 06:21:07 PM PDT 24
Finished Aug 01 06:21:08 PM PDT 24
Peak memory 216360 kb
Host smart-380f16c0-4315-45e2-adc8-1704d4000cbf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077237421 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1077237421
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_genbits.4104745098
Short name T305
Test name
Test status
Simulation time 57951419 ps
CPU time 1.61 seconds
Started Aug 01 06:21:19 PM PDT 24
Finished Aug 01 06:21:21 PM PDT 24
Peak memory 218632 kb
Host smart-3f1b7cc5-ffa8-4eaf-b813-984952c4cffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104745098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.4104745098
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.4223169940
Short name T369
Test name
Test status
Simulation time 38755921 ps
CPU time 0.95 seconds
Started Aug 01 06:21:04 PM PDT 24
Finished Aug 01 06:21:05 PM PDT 24
Peak memory 215260 kb
Host smart-dbb5b7d7-93a6-4d7c-a5be-6d941fb6d883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223169940 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.4223169940
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.80216818
Short name T331
Test name
Test status
Simulation time 37957352 ps
CPU time 0.9 seconds
Started Aug 01 06:21:15 PM PDT 24
Finished Aug 01 06:21:16 PM PDT 24
Peak memory 207084 kb
Host smart-630dba87-4229-44dc-9f5b-906953c607ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80216818 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.80216818
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.2873064519
Short name T514
Test name
Test status
Simulation time 15179605 ps
CPU time 0.98 seconds
Started Aug 01 06:21:16 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 215272 kb
Host smart-d0a18aa7-b82c-485a-8801-75b5c13337d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873064519 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2873064519
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1283309837
Short name T827
Test name
Test status
Simulation time 197553706 ps
CPU time 2.5 seconds
Started Aug 01 06:21:10 PM PDT 24
Finished Aug 01 06:21:13 PM PDT 24
Peak memory 217284 kb
Host smart-871874e6-32ec-4325-a91f-03f333571145
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283309837 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1283309837
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3055457060
Short name T907
Test name
Test status
Simulation time 38565035560 ps
CPU time 1009.86 seconds
Started Aug 01 06:21:00 PM PDT 24
Finished Aug 01 06:37:50 PM PDT 24
Peak memory 219292 kb
Host smart-cb4b4c3c-e36e-43c1-b6a9-e1b385240b53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055457060 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3055457060
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.948426485
Short name T532
Test name
Test status
Simulation time 16701137 ps
CPU time 0.93 seconds
Started Aug 01 06:21:15 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 206664 kb
Host smart-dbf0f19d-0db2-4a40-83be-eea0283276d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948426485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.948426485
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_err.2062208461
Short name T582
Test name
Test status
Simulation time 31753557 ps
CPU time 0.88 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:14 PM PDT 24
Peak memory 218012 kb
Host smart-2df9f092-e984-43a5-9e29-3535971b67d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062208461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2062208461
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_intr.2730575261
Short name T749
Test name
Test status
Simulation time 21317080 ps
CPU time 1.04 seconds
Started Aug 01 06:21:19 PM PDT 24
Finished Aug 01 06:21:20 PM PDT 24
Peak memory 215512 kb
Host smart-f91e98e2-ef32-4ede-a3e7-24d78242cec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730575261 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2730575261
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_smoke.721790914
Short name T660
Test name
Test status
Simulation time 25155988 ps
CPU time 0.93 seconds
Started Aug 01 06:20:59 PM PDT 24
Finished Aug 01 06:21:00 PM PDT 24
Peak memory 215272 kb
Host smart-e50179e3-12d6-4996-a27b-e177b11456dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721790914 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.721790914
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1190692670
Short name T503
Test name
Test status
Simulation time 57109307 ps
CPU time 1.69 seconds
Started Aug 01 06:20:56 PM PDT 24
Finished Aug 01 06:20:58 PM PDT 24
Peak memory 217232 kb
Host smart-2cf5d255-15d3-407b-8c29-cffb7c307536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190692670 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1190692670
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.845932000
Short name T708
Test name
Test status
Simulation time 60011459 ps
CPU time 1.16 seconds
Started Aug 01 06:21:23 PM PDT 24
Finished Aug 01 06:21:24 PM PDT 24
Peak memory 215656 kb
Host smart-32e2d56e-5c26-4909-9ec1-738723cdfb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845932000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.845932000
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2780376493
Short name T50
Test name
Test status
Simulation time 116987307 ps
CPU time 0.94 seconds
Started Aug 01 06:21:25 PM PDT 24
Finished Aug 01 06:21:26 PM PDT 24
Peak memory 206732 kb
Host smart-5f7d09f1-ca7f-4ef3-9988-364638842a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780376493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2780376493
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.4261792252
Short name T189
Test name
Test status
Simulation time 63178431 ps
CPU time 0.88 seconds
Started Aug 01 06:21:26 PM PDT 24
Finished Aug 01 06:21:27 PM PDT 24
Peak memory 216212 kb
Host smart-740e38a0-a8f9-4ef0-aa02-29ec0200dba3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261792252 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.4261792252
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.2288307358
Short name T978
Test name
Test status
Simulation time 42204871 ps
CPU time 0.8 seconds
Started Aug 01 06:21:21 PM PDT 24
Finished Aug 01 06:21:22 PM PDT 24
Peak memory 218304 kb
Host smart-539c0a99-a867-4c16-994b-15eb1f54d9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288307358 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2288307358
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.659687537
Short name T962
Test name
Test status
Simulation time 35305253 ps
CPU time 1.08 seconds
Started Aug 01 06:21:26 PM PDT 24
Finished Aug 01 06:21:27 PM PDT 24
Peak memory 215244 kb
Host smart-2de544cc-819a-46cb-a1a8-d80a7d85ef95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659687537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.659687537
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.1642648945
Short name T533
Test name
Test status
Simulation time 56339919 ps
CPU time 0.94 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:29 PM PDT 24
Peak memory 215292 kb
Host smart-f6a7efc4-42a9-41c4-81f2-11ec568d2f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642648945 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1642648945
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1475771516
Short name T581
Test name
Test status
Simulation time 197745327 ps
CPU time 4.03 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:31 PM PDT 24
Peak memory 220212 kb
Host smart-0bab309b-5cbd-4c71-80ee-c13dcae71b8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475771516 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1475771516
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.114116614
Short name T325
Test name
Test status
Simulation time 30662377502 ps
CPU time 767.79 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:34:15 PM PDT 24
Peak memory 223608 kb
Host smart-ba850062-b873-4170-a009-17c7f67d381d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114116614 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.114116614
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.1835948736
Short name T246
Test name
Test status
Simulation time 44976943 ps
CPU time 1.1 seconds
Started Aug 01 06:22:56 PM PDT 24
Finished Aug 01 06:22:57 PM PDT 24
Peak memory 218408 kb
Host smart-707bac46-c026-4d7d-9b0d-966d945ca0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835948736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.1835948736
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.440264707
Short name T497
Test name
Test status
Simulation time 28564610 ps
CPU time 1.19 seconds
Started Aug 01 06:22:40 PM PDT 24
Finished Aug 01 06:22:41 PM PDT 24
Peak memory 217296 kb
Host smart-83bd95a2-94a6-42d4-bc67-5039de528790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440264707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.440264707
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.4019432377
Short name T202
Test name
Test status
Simulation time 21429281 ps
CPU time 1.13 seconds
Started Aug 01 06:22:49 PM PDT 24
Finished Aug 01 06:22:50 PM PDT 24
Peak memory 218868 kb
Host smart-f36b63d5-9e0e-4727-9b51-aec45d232c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019432377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.4019432377
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.3420981492
Short name T738
Test name
Test status
Simulation time 231748898 ps
CPU time 1.14 seconds
Started Aug 01 06:22:48 PM PDT 24
Finished Aug 01 06:22:49 PM PDT 24
Peak memory 217272 kb
Host smart-5c4074b0-353a-4ceb-a19b-c71368b420cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420981492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3420981492
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.2222101042
Short name T603
Test name
Test status
Simulation time 40662932 ps
CPU time 1.21 seconds
Started Aug 01 06:22:52 PM PDT 24
Finished Aug 01 06:22:53 PM PDT 24
Peak memory 220228 kb
Host smart-d7b81a7d-6f1f-4109-ac54-637312827f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222101042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.2222101042
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2488888985
Short name T461
Test name
Test status
Simulation time 97660726 ps
CPU time 1.36 seconds
Started Aug 01 06:22:56 PM PDT 24
Finished Aug 01 06:22:57 PM PDT 24
Peak memory 217520 kb
Host smart-5a3c9702-0907-4edd-a29c-3b8318a20c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488888985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2488888985
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.825433325
Short name T297
Test name
Test status
Simulation time 236179330 ps
CPU time 1.32 seconds
Started Aug 01 06:22:51 PM PDT 24
Finished Aug 01 06:22:52 PM PDT 24
Peak memory 219016 kb
Host smart-e53fe8b6-63b1-4a57-b8a4-9044f9e208c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825433325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.825433325
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.572985810
Short name T399
Test name
Test status
Simulation time 169095365 ps
CPU time 3.41 seconds
Started Aug 01 06:22:35 PM PDT 24
Finished Aug 01 06:22:39 PM PDT 24
Peak memory 218580 kb
Host smart-6ce9dda2-8523-4202-bfce-f57d56c97e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572985810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.572985810
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.489175355
Short name T903
Test name
Test status
Simulation time 26226232 ps
CPU time 1.25 seconds
Started Aug 01 06:22:48 PM PDT 24
Finished Aug 01 06:22:50 PM PDT 24
Peak memory 219032 kb
Host smart-4f827361-0532-46d1-adbf-1572a3d5f5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489175355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.489175355
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.1404046509
Short name T712
Test name
Test status
Simulation time 35417244 ps
CPU time 1.6 seconds
Started Aug 01 06:22:40 PM PDT 24
Finished Aug 01 06:22:41 PM PDT 24
Peak memory 219412 kb
Host smart-6f3336cd-8542-49a6-9cca-a7d93e839ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404046509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1404046509
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.1794140645
Short name T901
Test name
Test status
Simulation time 48847987 ps
CPU time 1.16 seconds
Started Aug 01 06:22:52 PM PDT 24
Finished Aug 01 06:22:53 PM PDT 24
Peak memory 219588 kb
Host smart-8c608621-483a-48a9-a37e-f4c85224ef79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794140645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1794140645
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.1850756366
Short name T595
Test name
Test status
Simulation time 133603975 ps
CPU time 1.88 seconds
Started Aug 01 06:22:55 PM PDT 24
Finished Aug 01 06:22:57 PM PDT 24
Peak memory 218728 kb
Host smart-9463b25b-36d7-42fb-91fe-620242425a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850756366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1850756366
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.737517492
Short name T798
Test name
Test status
Simulation time 139273398 ps
CPU time 1.27 seconds
Started Aug 01 06:22:54 PM PDT 24
Finished Aug 01 06:22:55 PM PDT 24
Peak memory 215676 kb
Host smart-74410c07-e8c3-452d-b64c-ded6726b066d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737517492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.737517492
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.1387427510
Short name T335
Test name
Test status
Simulation time 78126109 ps
CPU time 1.37 seconds
Started Aug 01 06:22:53 PM PDT 24
Finished Aug 01 06:22:54 PM PDT 24
Peak memory 218712 kb
Host smart-2131ebc2-6246-429d-94a7-e0c2811844d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387427510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1387427510
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.3772262946
Short name T2
Test name
Test status
Simulation time 47323779 ps
CPU time 1.16 seconds
Started Aug 01 06:22:56 PM PDT 24
Finished Aug 01 06:22:58 PM PDT 24
Peak memory 219372 kb
Host smart-2168005b-9768-4c0b-b125-19c03118b65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772262946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3772262946
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.1762338516
Short name T359
Test name
Test status
Simulation time 94274231 ps
CPU time 1.35 seconds
Started Aug 01 06:22:57 PM PDT 24
Finished Aug 01 06:22:59 PM PDT 24
Peak memory 218720 kb
Host smart-5503f2a2-8f61-47a6-a009-34a2ea6a1dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762338516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1762338516
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.950388535
Short name T686
Test name
Test status
Simulation time 194204912 ps
CPU time 1.17 seconds
Started Aug 01 06:21:25 PM PDT 24
Finished Aug 01 06:21:26 PM PDT 24
Peak memory 219496 kb
Host smart-38f6c866-8548-4595-a7af-bcb0b92b000f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950388535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.950388535
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3394540310
Short name T700
Test name
Test status
Simulation time 50455392 ps
CPU time 0.82 seconds
Started Aug 01 06:21:26 PM PDT 24
Finished Aug 01 06:21:27 PM PDT 24
Peak memory 206308 kb
Host smart-5e14192a-0d94-4409-a2e6-1ea8327c9377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394540310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3394540310
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_err.62942951
Short name T3
Test name
Test status
Simulation time 23789486 ps
CPU time 0.94 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 218452 kb
Host smart-00847f21-c596-4ffc-8937-b4c925a43959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62942951 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.62942951
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1912095988
Short name T360
Test name
Test status
Simulation time 43129135 ps
CPU time 1.11 seconds
Started Aug 01 06:21:26 PM PDT 24
Finished Aug 01 06:21:27 PM PDT 24
Peak memory 219872 kb
Host smart-9f8260d0-22cf-49e0-a146-c7a83bdc9eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912095988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1912095988
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1621981843
Short name T48
Test name
Test status
Simulation time 49108894 ps
CPU time 0.96 seconds
Started Aug 01 06:21:24 PM PDT 24
Finished Aug 01 06:21:25 PM PDT 24
Peak memory 223808 kb
Host smart-65c6c116-1def-48a2-8d63-821320949826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621981843 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1621981843
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.18834948
Short name T423
Test name
Test status
Simulation time 24073501 ps
CPU time 0.9 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:21:34 PM PDT 24
Peak memory 215300 kb
Host smart-ba370041-45b8-4d80-b730-d257a5f817f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18834948 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.18834948
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1870173686
Short name T422
Test name
Test status
Simulation time 212767609 ps
CPU time 4.5 seconds
Started Aug 01 06:21:25 PM PDT 24
Finished Aug 01 06:21:30 PM PDT 24
Peak memory 217196 kb
Host smart-84adaab5-4ea3-4353-b629-c1f7b4030292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870173686 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1870173686
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.364190339
Short name T227
Test name
Test status
Simulation time 79909254584 ps
CPU time 875.83 seconds
Started Aug 01 06:21:24 PM PDT 24
Finished Aug 01 06:36:00 PM PDT 24
Peak memory 220096 kb
Host smart-43781dfe-26fc-4bb5-b46c-b136ab0377ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364190339 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.364190339
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.1401025198
Short name T698
Test name
Test status
Simulation time 102730696 ps
CPU time 1.16 seconds
Started Aug 01 06:22:55 PM PDT 24
Finished Aug 01 06:22:56 PM PDT 24
Peak memory 215660 kb
Host smart-3970f36f-b283-4bf5-8dd5-fcfc45ace1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401025198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1401025198
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.4123545701
Short name T378
Test name
Test status
Simulation time 71692317 ps
CPU time 1.51 seconds
Started Aug 01 06:22:53 PM PDT 24
Finished Aug 01 06:22:59 PM PDT 24
Peak memory 218304 kb
Host smart-d20a197c-a8b7-4d14-bacc-151c228915b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123545701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.4123545701
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.2572292534
Short name T771
Test name
Test status
Simulation time 46783677 ps
CPU time 1.16 seconds
Started Aug 01 06:22:54 PM PDT 24
Finished Aug 01 06:22:55 PM PDT 24
Peak memory 218436 kb
Host smart-0acbc788-992b-4c4e-aa47-64dea8eabb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572292534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2572292534
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.3057605633
Short name T510
Test name
Test status
Simulation time 29944098 ps
CPU time 1.22 seconds
Started Aug 01 06:22:52 PM PDT 24
Finished Aug 01 06:22:53 PM PDT 24
Peak memory 217264 kb
Host smart-da8b3454-cf79-4d10-9f0a-e19ce89456bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057605633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3057605633
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.2059977590
Short name T333
Test name
Test status
Simulation time 35353352 ps
CPU time 1.08 seconds
Started Aug 01 06:22:59 PM PDT 24
Finished Aug 01 06:23:00 PM PDT 24
Peak memory 218560 kb
Host smart-a5152854-b0d4-4bf7-80de-159c6bbf1df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059977590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2059977590
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3281903383
Short name T891
Test name
Test status
Simulation time 38729886 ps
CPU time 1.48 seconds
Started Aug 01 06:22:51 PM PDT 24
Finished Aug 01 06:22:53 PM PDT 24
Peak memory 218868 kb
Host smart-3b9154b2-31e6-41ca-8f0a-1d93c179d61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281903383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3281903383
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2615016979
Short name T517
Test name
Test status
Simulation time 56391604 ps
CPU time 1.07 seconds
Started Aug 01 06:22:58 PM PDT 24
Finished Aug 01 06:22:59 PM PDT 24
Peak memory 220964 kb
Host smart-ab088542-fa7e-40fe-9994-3f68b72e7807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615016979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2615016979
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.3754582555
Short name T629
Test name
Test status
Simulation time 170022721 ps
CPU time 1.32 seconds
Started Aug 01 06:23:01 PM PDT 24
Finished Aug 01 06:23:03 PM PDT 24
Peak memory 217244 kb
Host smart-08d663d0-3401-4429-82d0-ce475273bd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754582555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3754582555
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.528267109
Short name T60
Test name
Test status
Simulation time 33603558 ps
CPU time 1.36 seconds
Started Aug 01 06:23:02 PM PDT 24
Finished Aug 01 06:23:03 PM PDT 24
Peak memory 215672 kb
Host smart-93635da3-cc42-4ce4-8d4c-93892539cdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528267109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.528267109
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.1036080914
Short name T900
Test name
Test status
Simulation time 43139411 ps
CPU time 1.04 seconds
Started Aug 01 06:22:51 PM PDT 24
Finished Aug 01 06:22:52 PM PDT 24
Peak memory 217128 kb
Host smart-acb432ba-dee7-420f-8bd6-75cdcf6d4ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036080914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1036080914
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.585112384
Short name T508
Test name
Test status
Simulation time 110124956 ps
CPU time 1.31 seconds
Started Aug 01 06:22:52 PM PDT 24
Finished Aug 01 06:22:53 PM PDT 24
Peak memory 218804 kb
Host smart-b2af0c62-65a2-4e8a-b8de-97c11d5247c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585112384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.585112384
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3014907098
Short name T464
Test name
Test status
Simulation time 74895592 ps
CPU time 1.23 seconds
Started Aug 01 06:22:52 PM PDT 24
Finished Aug 01 06:22:53 PM PDT 24
Peak memory 217352 kb
Host smart-dab7033f-f548-4f65-8e15-4ca9bb0e82da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014907098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3014907098
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.2152077909
Short name T751
Test name
Test status
Simulation time 69227281 ps
CPU time 1.16 seconds
Started Aug 01 06:22:58 PM PDT 24
Finished Aug 01 06:23:00 PM PDT 24
Peak memory 218952 kb
Host smart-744ac13b-6194-42ea-a0cf-975315bb666c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152077909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.2152077909
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.3411509246
Short name T723
Test name
Test status
Simulation time 98147847 ps
CPU time 1.45 seconds
Started Aug 01 06:22:51 PM PDT 24
Finished Aug 01 06:22:53 PM PDT 24
Peak memory 218848 kb
Host smart-c63a7bb2-eaa4-43a9-be0d-ebb218933406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411509246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3411509246
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.432834058
Short name T196
Test name
Test status
Simulation time 22526359 ps
CPU time 1.21 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 218524 kb
Host smart-a2cf5ded-9809-46bf-8e6f-51a3e868fdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432834058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.432834058
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/118.edn_alert.941114767
Short name T643
Test name
Test status
Simulation time 103640970 ps
CPU time 1.31 seconds
Started Aug 01 06:22:56 PM PDT 24
Finished Aug 01 06:22:58 PM PDT 24
Peak memory 220736 kb
Host smart-5787c2b9-740f-4121-9a14-384310cae2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941114767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.941114767
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.34905301
Short name T502
Test name
Test status
Simulation time 49955748 ps
CPU time 1.83 seconds
Started Aug 01 06:22:55 PM PDT 24
Finished Aug 01 06:22:57 PM PDT 24
Peak memory 220064 kb
Host smart-9b7859c1-9e24-4b51-adde-75ff3241dd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34905301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.34905301
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3697551288
Short name T650
Test name
Test status
Simulation time 42355796 ps
CPU time 1.69 seconds
Started Aug 01 06:22:53 PM PDT 24
Finished Aug 01 06:22:55 PM PDT 24
Peak memory 218476 kb
Host smart-9914f806-d8b9-42e0-85f1-5f7b562e4062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697551288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3697551288
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2664974492
Short name T899
Test name
Test status
Simulation time 49224688 ps
CPU time 1.18 seconds
Started Aug 01 06:21:29 PM PDT 24
Finished Aug 01 06:21:30 PM PDT 24
Peak memory 219660 kb
Host smart-9c4e811d-64ff-4008-873a-a40eec3c5826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664974492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2664974492
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3192431949
Short name T494
Test name
Test status
Simulation time 50626924 ps
CPU time 0.93 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 214864 kb
Host smart-efd08450-fc0c-40e8-a4e5-099734d0a67c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192431949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3192431949
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2551760737
Short name T854
Test name
Test status
Simulation time 11617158 ps
CPU time 0.88 seconds
Started Aug 01 06:21:25 PM PDT 24
Finished Aug 01 06:21:26 PM PDT 24
Peak memory 215912 kb
Host smart-620e1f29-be17-445f-ade6-0b6e2161da63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551760737 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2551760737
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1162012392
Short name T534
Test name
Test status
Simulation time 85577116 ps
CPU time 1.15 seconds
Started Aug 01 06:21:20 PM PDT 24
Finished Aug 01 06:21:21 PM PDT 24
Peak memory 216872 kb
Host smart-14ea9a29-9e70-44d9-92c3-c4e8dbe7366e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162012392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1162012392
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1394959964
Short name T99
Test name
Test status
Simulation time 31190552 ps
CPU time 0.92 seconds
Started Aug 01 06:21:24 PM PDT 24
Finished Aug 01 06:21:25 PM PDT 24
Peak memory 218156 kb
Host smart-59c388d9-cd09-4efd-9131-dd0075b7065f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394959964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1394959964
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2502841914
Short name T375
Test name
Test status
Simulation time 52667316 ps
CPU time 1.15 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:28 PM PDT 24
Peak memory 217244 kb
Host smart-13f61edf-847d-4411-b508-f5078c3157eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502841914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2502841914
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3744599502
Short name T873
Test name
Test status
Simulation time 34174910 ps
CPU time 0.85 seconds
Started Aug 01 06:21:24 PM PDT 24
Finished Aug 01 06:21:24 PM PDT 24
Peak memory 215728 kb
Host smart-8ba311f0-96ce-48e6-ba97-36c788d69ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744599502 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3744599502
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.4099809707
Short name T714
Test name
Test status
Simulation time 18631805 ps
CPU time 1.01 seconds
Started Aug 01 06:21:24 PM PDT 24
Finished Aug 01 06:21:25 PM PDT 24
Peak memory 215288 kb
Host smart-772763d6-4149-4fb1-b16b-d9868f3a68f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099809707 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.4099809707
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2438326681
Short name T279
Test name
Test status
Simulation time 232531897 ps
CPU time 3.8 seconds
Started Aug 01 06:21:26 PM PDT 24
Finished Aug 01 06:21:30 PM PDT 24
Peak memory 215348 kb
Host smart-81b84403-4723-4177-8858-cc935138e304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438326681 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2438326681
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1819103928
Short name T233
Test name
Test status
Simulation time 423688135267 ps
CPU time 1671.12 seconds
Started Aug 01 06:21:26 PM PDT 24
Finished Aug 01 06:49:17 PM PDT 24
Peak memory 223860 kb
Host smart-690fdc96-d0af-4587-a562-5f550084326e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819103928 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1819103928
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.3783235859
Short name T412
Test name
Test status
Simulation time 173724686 ps
CPU time 1.23 seconds
Started Aug 01 06:22:54 PM PDT 24
Finished Aug 01 06:22:55 PM PDT 24
Peak memory 219300 kb
Host smart-d730ed8b-f5cc-4272-b343-064cf739c049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783235859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.3783235859
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.451628524
Short name T420
Test name
Test status
Simulation time 263264269 ps
CPU time 1.73 seconds
Started Aug 01 06:22:57 PM PDT 24
Finished Aug 01 06:22:59 PM PDT 24
Peak memory 218844 kb
Host smart-225d820d-0d4f-4939-ac0d-b7134306b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451628524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.451628524
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.1395834112
Short name T515
Test name
Test status
Simulation time 31945950 ps
CPU time 1.28 seconds
Started Aug 01 06:22:52 PM PDT 24
Finished Aug 01 06:22:53 PM PDT 24
Peak memory 218488 kb
Host smart-425f534f-0f09-4fa0-b8ef-39947416c594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395834112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1395834112
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.2810601467
Short name T456
Test name
Test status
Simulation time 246677997 ps
CPU time 0.99 seconds
Started Aug 01 06:22:59 PM PDT 24
Finished Aug 01 06:23:00 PM PDT 24
Peak memory 217352 kb
Host smart-df7543f7-839d-4d57-a935-78af470ecdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810601467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2810601467
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.3197819516
Short name T742
Test name
Test status
Simulation time 44494943 ps
CPU time 1.15 seconds
Started Aug 01 06:22:59 PM PDT 24
Finished Aug 01 06:23:01 PM PDT 24
Peak memory 215668 kb
Host smart-3fb3e01b-28b0-401e-a5de-5ca3d3f5ed6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197819516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3197819516
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.1978869820
Short name T388
Test name
Test status
Simulation time 50895625 ps
CPU time 1.45 seconds
Started Aug 01 06:22:58 PM PDT 24
Finished Aug 01 06:23:00 PM PDT 24
Peak memory 218932 kb
Host smart-b302117b-68fa-42be-82a1-3a8ef93a891c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978869820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1978869820
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.3084322425
Short name T951
Test name
Test status
Simulation time 45537261 ps
CPU time 1.22 seconds
Started Aug 01 06:22:53 PM PDT 24
Finished Aug 01 06:22:54 PM PDT 24
Peak memory 219692 kb
Host smart-d8d2aaee-fb65-41ad-b36b-46032e42ad2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084322425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.3084322425
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.4143257290
Short name T786
Test name
Test status
Simulation time 49826275 ps
CPU time 1.24 seconds
Started Aug 01 06:22:57 PM PDT 24
Finished Aug 01 06:22:59 PM PDT 24
Peak memory 218548 kb
Host smart-bbb294c9-02ef-4f59-a54b-d307cea457e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143257290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.4143257290
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.725831435
Short name T672
Test name
Test status
Simulation time 41742085 ps
CPU time 1.3 seconds
Started Aug 01 06:22:58 PM PDT 24
Finished Aug 01 06:22:59 PM PDT 24
Peak memory 215648 kb
Host smart-e164b11e-50a2-4486-858d-1361133da742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725831435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.725831435
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.2278015296
Short name T814
Test name
Test status
Simulation time 63856974 ps
CPU time 1.21 seconds
Started Aug 01 06:22:51 PM PDT 24
Finished Aug 01 06:22:53 PM PDT 24
Peak memory 217360 kb
Host smart-af5b9306-b905-4f84-aa25-0457b9e2997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278015296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2278015296
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.3989473709
Short name T253
Test name
Test status
Simulation time 384180580 ps
CPU time 1.14 seconds
Started Aug 01 06:22:53 PM PDT 24
Finished Aug 01 06:22:55 PM PDT 24
Peak memory 219448 kb
Host smart-16b4f63b-0de5-4a59-aa12-bb607a7f9905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989473709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3989473709
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/126.edn_alert.788719605
Short name T63
Test name
Test status
Simulation time 48406132 ps
CPU time 1.23 seconds
Started Aug 01 06:22:53 PM PDT 24
Finished Aug 01 06:22:54 PM PDT 24
Peak memory 220812 kb
Host smart-2f7e9e8c-6b8a-4c57-b949-c11308289318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788719605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.788719605
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.2146750676
Short name T720
Test name
Test status
Simulation time 55503735 ps
CPU time 1.92 seconds
Started Aug 01 06:22:53 PM PDT 24
Finished Aug 01 06:22:55 PM PDT 24
Peak memory 219220 kb
Host smart-dc3893a8-e55c-4e9b-9739-644d0dfff328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146750676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2146750676
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.3765601829
Short name T803
Test name
Test status
Simulation time 86738387 ps
CPU time 1.13 seconds
Started Aug 01 06:22:52 PM PDT 24
Finished Aug 01 06:22:53 PM PDT 24
Peak memory 220260 kb
Host smart-208a55ca-5615-4d2e-a6d0-2d2404990316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765601829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.3765601829
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.895258888
Short name T617
Test name
Test status
Simulation time 194820720 ps
CPU time 3.01 seconds
Started Aug 01 06:22:54 PM PDT 24
Finished Aug 01 06:22:57 PM PDT 24
Peak memory 219232 kb
Host smart-93493a22-9875-402b-b070-e250aa03cf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895258888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.895258888
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.1268222982
Short name T518
Test name
Test status
Simulation time 54817430 ps
CPU time 1.08 seconds
Started Aug 01 06:22:53 PM PDT 24
Finished Aug 01 06:22:54 PM PDT 24
Peak memory 220796 kb
Host smart-8bd45e49-aaf5-4d0b-9c56-2491bb8c3c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268222982 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.1268222982
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.1741764040
Short name T400
Test name
Test status
Simulation time 75292771 ps
CPU time 1.06 seconds
Started Aug 01 06:22:59 PM PDT 24
Finished Aug 01 06:23:00 PM PDT 24
Peak memory 219296 kb
Host smart-b2cbd0db-ac9e-4510-a580-659f15ac249b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741764040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1741764040
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3653147182
Short name T362
Test name
Test status
Simulation time 27142759 ps
CPU time 1.19 seconds
Started Aug 01 06:22:58 PM PDT 24
Finished Aug 01 06:22:59 PM PDT 24
Peak memory 217520 kb
Host smart-21b23396-d20d-462c-b725-67016d820738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653147182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3653147182
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3536456584
Short name T451
Test name
Test status
Simulation time 27137394 ps
CPU time 1.21 seconds
Started Aug 01 06:21:26 PM PDT 24
Finished Aug 01 06:21:27 PM PDT 24
Peak memory 219804 kb
Host smart-81fddce6-f47d-4752-bf25-0eba32762124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536456584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3536456584
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.624350882
Short name T801
Test name
Test status
Simulation time 25274040 ps
CPU time 0.91 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:28 PM PDT 24
Peak memory 206644 kb
Host smart-e95a24b7-99e9-4cc4-8f5d-9cfb109d5b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624350882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.624350882
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1720349714
Short name T766
Test name
Test status
Simulation time 19594257 ps
CPU time 0.82 seconds
Started Aug 01 06:21:24 PM PDT 24
Finished Aug 01 06:21:25 PM PDT 24
Peak memory 215400 kb
Host smart-29c5f907-c873-4a59-a6fd-594a7e0d01d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720349714 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1720349714
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.822056099
Short name T959
Test name
Test status
Simulation time 106084546 ps
CPU time 1.1 seconds
Started Aug 01 06:21:28 PM PDT 24
Finished Aug 01 06:21:29 PM PDT 24
Peak memory 217036 kb
Host smart-025e9182-1cd1-46f0-887f-54c885d25299
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822056099 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.822056099
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_genbits.1216672040
Short name T967
Test name
Test status
Simulation time 72419980 ps
CPU time 1.02 seconds
Started Aug 01 06:21:26 PM PDT 24
Finished Aug 01 06:21:28 PM PDT 24
Peak memory 217464 kb
Host smart-97b1dafb-a5b0-4db0-950f-e058dfc3caab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216672040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1216672040
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.2063490664
Short name T977
Test name
Test status
Simulation time 34006347 ps
CPU time 0.99 seconds
Started Aug 01 06:21:28 PM PDT 24
Finished Aug 01 06:21:29 PM PDT 24
Peak memory 215288 kb
Host smart-b20868e5-0b03-4dbd-a269-9ce56079e6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063490664 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2063490664
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.838063149
Short name T368
Test name
Test status
Simulation time 68462280 ps
CPU time 1.87 seconds
Started Aug 01 06:21:26 PM PDT 24
Finished Aug 01 06:21:29 PM PDT 24
Peak memory 215212 kb
Host smart-7ca65dc7-3a61-498d-b4a8-11de2cfa5671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838063149 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.838063149
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_alert.2857926570
Short name T929
Test name
Test status
Simulation time 65769441 ps
CPU time 1.1 seconds
Started Aug 01 06:23:04 PM PDT 24
Finished Aug 01 06:23:06 PM PDT 24
Peak memory 218564 kb
Host smart-6e430fe0-eee5-403f-a508-3646b043745b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857926570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2857926570
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2431727177
Short name T490
Test name
Test status
Simulation time 43564981 ps
CPU time 1.76 seconds
Started Aug 01 06:22:57 PM PDT 24
Finished Aug 01 06:22:59 PM PDT 24
Peak memory 220288 kb
Host smart-0366866d-c425-40fc-9498-7ad1c3d666d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431727177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2431727177
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3234685329
Short name T676
Test name
Test status
Simulation time 25369304 ps
CPU time 1.12 seconds
Started Aug 01 06:22:59 PM PDT 24
Finished Aug 01 06:23:01 PM PDT 24
Peak memory 218360 kb
Host smart-3032fbbe-a316-452d-9c0e-c710e05a320c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234685329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3234685329
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.1095442061
Short name T165
Test name
Test status
Simulation time 102859772 ps
CPU time 1.12 seconds
Started Aug 01 06:22:54 PM PDT 24
Finished Aug 01 06:22:55 PM PDT 24
Peak memory 219828 kb
Host smart-f7433698-2235-46ce-8565-421ca7bcca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095442061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1095442061
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2729344715
Short name T302
Test name
Test status
Simulation time 38091887 ps
CPU time 1.18 seconds
Started Aug 01 06:22:57 PM PDT 24
Finished Aug 01 06:22:58 PM PDT 24
Peak memory 217428 kb
Host smart-405641a8-8f9a-42f9-9d48-f4820b09bc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729344715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2729344715
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.3986538472
Short name T806
Test name
Test status
Simulation time 37691285 ps
CPU time 1.15 seconds
Started Aug 01 06:23:05 PM PDT 24
Finished Aug 01 06:23:06 PM PDT 24
Peak memory 219596 kb
Host smart-1a13ae80-16db-42b5-a855-cde1979910d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986538472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.3986538472
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.323181952
Short name T447
Test name
Test status
Simulation time 64674635 ps
CPU time 1.52 seconds
Started Aug 01 06:22:59 PM PDT 24
Finished Aug 01 06:23:00 PM PDT 24
Peak memory 220360 kb
Host smart-5f8425d8-82d2-4389-8486-5f807498470c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323181952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.323181952
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.2112427652
Short name T73
Test name
Test status
Simulation time 43616648 ps
CPU time 1.17 seconds
Started Aug 01 06:22:58 PM PDT 24
Finished Aug 01 06:22:59 PM PDT 24
Peak memory 220300 kb
Host smart-844b7deb-ce5b-4894-b6a3-e9a157ebc445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112427652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2112427652
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3130555565
Short name T715
Test name
Test status
Simulation time 69223648 ps
CPU time 1.41 seconds
Started Aug 01 06:22:58 PM PDT 24
Finished Aug 01 06:22:59 PM PDT 24
Peak memory 217312 kb
Host smart-79097e2b-1f3f-4290-b38e-73bf8fdf3496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130555565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3130555565
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.3000348719
Short name T523
Test name
Test status
Simulation time 159562143 ps
CPU time 1.59 seconds
Started Aug 01 06:22:55 PM PDT 24
Finished Aug 01 06:22:57 PM PDT 24
Peak memory 218492 kb
Host smart-bc54641a-7c6c-458c-b48c-ddffe953edde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000348719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3000348719
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.4247306149
Short name T809
Test name
Test status
Simulation time 103111370 ps
CPU time 2.49 seconds
Started Aug 01 06:22:53 PM PDT 24
Finished Aug 01 06:22:56 PM PDT 24
Peak memory 219560 kb
Host smart-c2063521-7112-4609-8797-36cca4963140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247306149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.4247306149
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.767095773
Short name T191
Test name
Test status
Simulation time 34602389 ps
CPU time 1.31 seconds
Started Aug 01 06:22:59 PM PDT 24
Finished Aug 01 06:23:01 PM PDT 24
Peak memory 221176 kb
Host smart-dda579b2-97b3-49bc-8461-2aee117f430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767095773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.767095773
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.653904486
Short name T661
Test name
Test status
Simulation time 82335999 ps
CPU time 1.3 seconds
Started Aug 01 06:23:01 PM PDT 24
Finished Aug 01 06:23:02 PM PDT 24
Peak memory 219120 kb
Host smart-30dc11d7-7600-4fa4-8480-bd26248a6221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653904486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.653904486
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.706274283
Short name T192
Test name
Test status
Simulation time 26097697 ps
CPU time 1.2 seconds
Started Aug 01 06:22:57 PM PDT 24
Finished Aug 01 06:22:58 PM PDT 24
Peak memory 218536 kb
Host smart-c054ba68-bfbc-4309-84cd-6f4c992550b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706274283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.706274283
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.2857684667
Short name T913
Test name
Test status
Simulation time 87186285 ps
CPU time 1.17 seconds
Started Aug 01 06:22:53 PM PDT 24
Finished Aug 01 06:22:54 PM PDT 24
Peak memory 219824 kb
Host smart-60a92b80-5f32-4de8-b11f-a9aaf7b051f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857684667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2857684667
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.1543693691
Short name T543
Test name
Test status
Simulation time 58312083 ps
CPU time 1.47 seconds
Started Aug 01 06:22:50 PM PDT 24
Finished Aug 01 06:22:52 PM PDT 24
Peak memory 218468 kb
Host smart-0fb79ee7-ce09-4c42-bcbc-73b8baecde84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543693691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1543693691
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.3497817769
Short name T203
Test name
Test status
Simulation time 106171254 ps
CPU time 1.18 seconds
Started Aug 01 06:23:03 PM PDT 24
Finished Aug 01 06:23:04 PM PDT 24
Peak memory 219092 kb
Host smart-54c7207a-3f65-4c97-9e94-39f8f0564732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497817769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.3497817769
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.3847023450
Short name T910
Test name
Test status
Simulation time 34314084 ps
CPU time 1.43 seconds
Started Aug 01 06:23:01 PM PDT 24
Finished Aug 01 06:23:03 PM PDT 24
Peak memory 218556 kb
Host smart-9214265e-c22c-4aaa-ae4d-d56ac33f3f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847023450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3847023450
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.974983655
Short name T281
Test name
Test status
Simulation time 28293212 ps
CPU time 1.24 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:29 PM PDT 24
Peak memory 219412 kb
Host smart-a01e8456-8f03-4720-bd76-c96caa63574a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974983655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.974983655
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.376992066
Short name T486
Test name
Test status
Simulation time 41903684 ps
CPU time 1.25 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:29 PM PDT 24
Peak memory 214940 kb
Host smart-0ba2344c-a118-4197-b2c7-40c0e039aa64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376992066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.376992066
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1027462099
Short name T943
Test name
Test status
Simulation time 22196851 ps
CPU time 0.86 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:21:34 PM PDT 24
Peak memory 215372 kb
Host smart-5b78e907-c187-4c0c-935a-7cdb2625a0f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027462099 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1027462099
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3099315800
Short name T401
Test name
Test status
Simulation time 38841454 ps
CPU time 1.32 seconds
Started Aug 01 06:21:29 PM PDT 24
Finished Aug 01 06:21:31 PM PDT 24
Peak memory 218628 kb
Host smart-aca08619-9a75-461c-89a4-f87d8d8a8835
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099315800 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3099315800
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1376916837
Short name T169
Test name
Test status
Simulation time 25440862 ps
CPU time 1.32 seconds
Started Aug 01 06:21:24 PM PDT 24
Finished Aug 01 06:21:26 PM PDT 24
Peak memory 232184 kb
Host smart-22314fda-160a-46bb-93c9-622f896d2f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376916837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1376916837
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.697566709
Short name T982
Test name
Test status
Simulation time 82275172 ps
CPU time 1.53 seconds
Started Aug 01 06:21:29 PM PDT 24
Finished Aug 01 06:21:31 PM PDT 24
Peak memory 218412 kb
Host smart-7ed91273-d862-4c30-b766-4589c674a67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697566709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.697566709
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1409011845
Short name T774
Test name
Test status
Simulation time 23893430 ps
CPU time 1.01 seconds
Started Aug 01 06:21:29 PM PDT 24
Finished Aug 01 06:21:30 PM PDT 24
Peak memory 215480 kb
Host smart-db2bc0e9-50e9-497f-8835-28e898f96015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409011845 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1409011845
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2377048625
Short name T985
Test name
Test status
Simulation time 104598609 ps
CPU time 0.9 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 215352 kb
Host smart-abc8c0ef-c3d7-41a0-803c-d0bf70feea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377048625 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2377048625
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2832881834
Short name T972
Test name
Test status
Simulation time 260154208 ps
CPU time 3.18 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:31 PM PDT 24
Peak memory 220152 kb
Host smart-5c87ab62-8f48-43e1-a5db-0ee7859c8b08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832881834 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2832881834
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2512487912
Short name T567
Test name
Test status
Simulation time 271095257120 ps
CPU time 1539.8 seconds
Started Aug 01 06:21:28 PM PDT 24
Finished Aug 01 06:47:13 PM PDT 24
Peak memory 224064 kb
Host smart-2ccda711-2da1-4048-86fd-39cadbff308b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512487912 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2512487912
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.809089751
Short name T902
Test name
Test status
Simulation time 23421699 ps
CPU time 1.1 seconds
Started Aug 01 06:23:10 PM PDT 24
Finished Aug 01 06:23:11 PM PDT 24
Peak memory 219212 kb
Host smart-4db543ea-b1a6-4243-bdf5-2644205b7fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809089751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.809089751
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.2604372470
Short name T328
Test name
Test status
Simulation time 39743549 ps
CPU time 1.66 seconds
Started Aug 01 06:23:08 PM PDT 24
Finished Aug 01 06:23:10 PM PDT 24
Peak memory 218652 kb
Host smart-2d043d8f-96c0-43a1-b0b5-3a27d2c0abdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604372470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2604372470
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.4289720328
Short name T298
Test name
Test status
Simulation time 129111499 ps
CPU time 1.31 seconds
Started Aug 01 06:23:05 PM PDT 24
Finished Aug 01 06:23:06 PM PDT 24
Peak memory 220320 kb
Host smart-65da8e70-0776-4b67-99fc-ad4f4c9fa28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289720328 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.4289720328
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.1941907024
Short name T616
Test name
Test status
Simulation time 95770291 ps
CPU time 1.21 seconds
Started Aug 01 06:23:02 PM PDT 24
Finished Aug 01 06:23:03 PM PDT 24
Peak memory 217388 kb
Host smart-c851c722-fd88-486f-ac04-191984132b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941907024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1941907024
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3112944988
Short name T969
Test name
Test status
Simulation time 25696091 ps
CPU time 1.18 seconds
Started Aug 01 06:23:12 PM PDT 24
Finished Aug 01 06:23:14 PM PDT 24
Peak memory 219732 kb
Host smart-28bb5c7c-39bd-497b-85e5-3aea7096118e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112944988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3112944988
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.3345826365
Short name T593
Test name
Test status
Simulation time 41302448 ps
CPU time 1.41 seconds
Started Aug 01 06:23:00 PM PDT 24
Finished Aug 01 06:23:01 PM PDT 24
Peak memory 218420 kb
Host smart-c6c2d095-ac05-431c-bf88-31473af4afb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345826365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3345826365
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.1991812460
Short name T30
Test name
Test status
Simulation time 71860340 ps
CPU time 1.31 seconds
Started Aug 01 06:23:01 PM PDT 24
Finished Aug 01 06:23:03 PM PDT 24
Peak memory 217372 kb
Host smart-5512e5ec-374a-48dc-8798-4876e3bdb1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991812460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1991812460
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.1478131592
Short name T72
Test name
Test status
Simulation time 23347691 ps
CPU time 1.21 seconds
Started Aug 01 06:23:05 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 215604 kb
Host smart-62a2d686-1ec3-4167-bb05-9b5e067ff16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478131592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1478131592
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.1175947158
Short name T521
Test name
Test status
Simulation time 36517927 ps
CPU time 1.24 seconds
Started Aug 01 06:23:03 PM PDT 24
Finished Aug 01 06:23:04 PM PDT 24
Peak memory 218784 kb
Host smart-a804ae4f-4cf5-4d18-baad-ac5b55e746f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175947158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1175947158
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.710659943
Short name T981
Test name
Test status
Simulation time 89631456 ps
CPU time 1.24 seconds
Started Aug 01 06:23:01 PM PDT 24
Finished Aug 01 06:23:03 PM PDT 24
Peak memory 218592 kb
Host smart-637ea265-d882-4e8c-8d19-92bb9a042963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710659943 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.710659943
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.3309692822
Short name T363
Test name
Test status
Simulation time 23114055 ps
CPU time 1.2 seconds
Started Aug 01 06:23:04 PM PDT 24
Finished Aug 01 06:23:05 PM PDT 24
Peak memory 217520 kb
Host smart-c7f9fa4b-0c6c-48aa-a5c7-ca262c816cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309692822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3309692822
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.2290131558
Short name T504
Test name
Test status
Simulation time 61130799 ps
CPU time 1.24 seconds
Started Aug 01 06:23:10 PM PDT 24
Finished Aug 01 06:23:11 PM PDT 24
Peak memory 215648 kb
Host smart-53e8dee3-015b-4e9e-a8cb-a97e7b05ad3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290131558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2290131558
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.3153540633
Short name T312
Test name
Test status
Simulation time 45236038 ps
CPU time 1.97 seconds
Started Aug 01 06:23:05 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 220188 kb
Host smart-c6a0d35a-3e42-4fff-892c-2d0f37fd1c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153540633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3153540633
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.2808129272
Short name T879
Test name
Test status
Simulation time 23567892 ps
CPU time 1.28 seconds
Started Aug 01 06:23:05 PM PDT 24
Finished Aug 01 06:23:06 PM PDT 24
Peak memory 220392 kb
Host smart-51781382-c60c-40ee-a653-c499f9ce3529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808129272 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.2808129272
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3576396812
Short name T337
Test name
Test status
Simulation time 67983133 ps
CPU time 1.64 seconds
Started Aug 01 06:23:05 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 218740 kb
Host smart-da1edac7-1188-428b-a7ec-8dcceccc5837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576396812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3576396812
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.924553868
Short name T18
Test name
Test status
Simulation time 23859691 ps
CPU time 1.17 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 218716 kb
Host smart-8ebb32df-a47c-4216-b40f-29faf0cdf99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924553868 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.924553868
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.263875090
Short name T882
Test name
Test status
Simulation time 37756288 ps
CPU time 1.73 seconds
Started Aug 01 06:23:07 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 217488 kb
Host smart-7a7875e9-1e8d-4d0a-a563-7459130f7683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263875090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.263875090
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3283552226
Short name T872
Test name
Test status
Simulation time 71584097 ps
CPU time 1.14 seconds
Started Aug 01 06:23:07 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 218932 kb
Host smart-cf96d67f-2adb-46da-bb7c-2239ed920c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283552226 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3283552226
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.2967607381
Short name T457
Test name
Test status
Simulation time 171419616 ps
CPU time 1.42 seconds
Started Aug 01 06:23:09 PM PDT 24
Finished Aug 01 06:23:11 PM PDT 24
Peak memory 219048 kb
Host smart-60735a5e-93ec-4167-add7-6f2220327a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967607381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2967607381
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.3906451130
Short name T460
Test name
Test status
Simulation time 18241523 ps
CPU time 0.98 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 206664 kb
Host smart-4824a4dd-1e99-49cc-97d1-b531f0047d06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906451130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3906451130
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1080406649
Short name T122
Test name
Test status
Simulation time 14246593 ps
CPU time 0.94 seconds
Started Aug 01 06:21:29 PM PDT 24
Finished Aug 01 06:21:30 PM PDT 24
Peak memory 216376 kb
Host smart-995af8f1-1b38-45f2-9485-7c3691988467
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080406649 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1080406649
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.2578761895
Short name T163
Test name
Test status
Simulation time 58131582 ps
CPU time 1.05 seconds
Started Aug 01 06:21:32 PM PDT 24
Finished Aug 01 06:21:34 PM PDT 24
Peak memory 220464 kb
Host smart-85d67d9b-3b90-48d8-a2da-23ea4fdf823d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578761895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2578761895
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1176102055
Short name T726
Test name
Test status
Simulation time 43017945 ps
CPU time 1.35 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:21:35 PM PDT 24
Peak memory 218700 kb
Host smart-019d93ec-854d-46b1-b112-02280d928ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176102055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1176102055
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.828139901
Short name T86
Test name
Test status
Simulation time 25590953 ps
CPU time 0.93 seconds
Started Aug 01 06:21:28 PM PDT 24
Finished Aug 01 06:21:29 PM PDT 24
Peak memory 215836 kb
Host smart-8e08a6f6-9f6b-40eb-b442-68e53bd110b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828139901 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.828139901
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3937567916
Short name T380
Test name
Test status
Simulation time 45641594 ps
CPU time 0.89 seconds
Started Aug 01 06:21:34 PM PDT 24
Finished Aug 01 06:21:35 PM PDT 24
Peak memory 207064 kb
Host smart-1a23386f-2b6e-4948-b068-39b632c90027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937567916 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3937567916
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2437390227
Short name T930
Test name
Test status
Simulation time 269657951 ps
CPU time 3.28 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:21:36 PM PDT 24
Peak memory 217248 kb
Host smart-4d91f7a9-2664-4d6a-85c6-bc243d399cdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437390227 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2437390227
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_alert.388763518
Short name T144
Test name
Test status
Simulation time 26425509 ps
CPU time 1.2 seconds
Started Aug 01 06:23:05 PM PDT 24
Finished Aug 01 06:23:06 PM PDT 24
Peak memory 219696 kb
Host smart-cf922112-bfd8-4c44-b2e8-f0b8715c927c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388763518 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.388763518
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.1667136798
Short name T724
Test name
Test status
Simulation time 46791035 ps
CPU time 1.66 seconds
Started Aug 01 06:23:03 PM PDT 24
Finished Aug 01 06:23:05 PM PDT 24
Peak memory 218676 kb
Host smart-a8077e99-62e7-4370-bb4b-c06df22ee4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667136798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1667136798
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1427093287
Short name T446
Test name
Test status
Simulation time 73572582 ps
CPU time 1.44 seconds
Started Aug 01 06:23:02 PM PDT 24
Finished Aug 01 06:23:04 PM PDT 24
Peak memory 218708 kb
Host smart-ad844c1c-b748-4633-88e6-bfd95557c94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427093287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1427093287
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.4182467480
Short name T627
Test name
Test status
Simulation time 94380167 ps
CPU time 1.18 seconds
Started Aug 01 06:23:05 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 219332 kb
Host smart-64ec3152-f07e-46f1-8ddf-3df820beef7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182467480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.4182467480
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.1261182645
Short name T950
Test name
Test status
Simulation time 106101353 ps
CPU time 1.54 seconds
Started Aug 01 06:23:00 PM PDT 24
Finished Aug 01 06:23:02 PM PDT 24
Peak memory 218972 kb
Host smart-7028e880-ac03-4a35-acb6-85f14783e343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261182645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1261182645
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.444362684
Short name T863
Test name
Test status
Simulation time 95869116 ps
CPU time 1.3 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 219760 kb
Host smart-8679f0a0-4b3d-4289-9d70-9db42a119ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444362684 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.444362684
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1254561774
Short name T506
Test name
Test status
Simulation time 61373264 ps
CPU time 1.82 seconds
Started Aug 01 06:23:07 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 217556 kb
Host smart-13a55b09-9de2-49df-b259-378614361a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254561774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1254561774
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.699865883
Short name T252
Test name
Test status
Simulation time 84995031 ps
CPU time 1.13 seconds
Started Aug 01 06:23:09 PM PDT 24
Finished Aug 01 06:23:10 PM PDT 24
Peak memory 218344 kb
Host smart-76605658-ca5c-4d59-81af-2c7f3bc05947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699865883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.699865883
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.885462984
Short name T11
Test name
Test status
Simulation time 71209552 ps
CPU time 1.37 seconds
Started Aug 01 06:23:07 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 219908 kb
Host smart-93e68277-04f7-434a-ba58-83d420bfaa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885462984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.885462984
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.2968303906
Short name T728
Test name
Test status
Simulation time 31290244 ps
CPU time 1.37 seconds
Started Aug 01 06:23:05 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 219412 kb
Host smart-90ba20e5-01ba-4ac4-9ba0-43317ce2f4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968303906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.2968303906
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3387211290
Short name T893
Test name
Test status
Simulation time 46714548 ps
CPU time 1.4 seconds
Started Aug 01 06:23:01 PM PDT 24
Finished Aug 01 06:23:03 PM PDT 24
Peak memory 218656 kb
Host smart-be5f1ef1-782b-4191-a066-32049a402062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387211290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3387211290
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.1596804689
Short name T880
Test name
Test status
Simulation time 250100138 ps
CPU time 1.38 seconds
Started Aug 01 06:23:07 PM PDT 24
Finished Aug 01 06:23:13 PM PDT 24
Peak memory 215604 kb
Host smart-e6f8a6af-c072-4c34-9564-825c93a80283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596804689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1596804689
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.3933822621
Short name T571
Test name
Test status
Simulation time 26291044 ps
CPU time 1.28 seconds
Started Aug 01 06:23:08 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 217472 kb
Host smart-bf659cab-de78-478d-85c7-da2a7e2fcaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933822621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3933822621
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3324346794
Short name T40
Test name
Test status
Simulation time 25986229 ps
CPU time 1.29 seconds
Started Aug 01 06:23:08 PM PDT 24
Finished Aug 01 06:23:10 PM PDT 24
Peak memory 220452 kb
Host smart-ad9dfdbc-5e49-4718-83d7-9026dd42115a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324346794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3324346794
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.2959213143
Short name T499
Test name
Test status
Simulation time 50466852 ps
CPU time 1.55 seconds
Started Aug 01 06:23:07 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 218452 kb
Host smart-c767d2a5-73c2-4516-9d37-654bb5244b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959213143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2959213143
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.4134741025
Short name T921
Test name
Test status
Simulation time 74896613 ps
CPU time 1.19 seconds
Started Aug 01 06:23:04 PM PDT 24
Finished Aug 01 06:23:05 PM PDT 24
Peak memory 219472 kb
Host smart-6366101e-a030-4b3c-a1d8-a6a7acf1af79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134741025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.4134741025
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1804551647
Short name T654
Test name
Test status
Simulation time 72885776 ps
CPU time 1.47 seconds
Started Aug 01 06:23:05 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 218820 kb
Host smart-ab8e5646-5709-43f2-886a-c92cb3022d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804551647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1804551647
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3035223572
Short name T957
Test name
Test status
Simulation time 52370554 ps
CPU time 1.22 seconds
Started Aug 01 06:21:39 PM PDT 24
Finished Aug 01 06:21:40 PM PDT 24
Peak memory 219824 kb
Host smart-32a23486-1531-4dbd-9b46-8b111c4eabd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035223572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3035223572
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2677866254
Short name T612
Test name
Test status
Simulation time 107828547 ps
CPU time 0.81 seconds
Started Aug 01 06:21:28 PM PDT 24
Finished Aug 01 06:21:29 PM PDT 24
Peak memory 206328 kb
Host smart-b64f07f5-2930-4868-ac82-cab063826172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677866254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2677866254
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3979516011
Short name T108
Test name
Test status
Simulation time 44270944 ps
CPU time 0.9 seconds
Started Aug 01 06:21:30 PM PDT 24
Finished Aug 01 06:21:31 PM PDT 24
Peak memory 215340 kb
Host smart-f261f291-07dd-42d8-b746-e16723b12869
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979516011 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3979516011
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2113842615
Short name T789
Test name
Test status
Simulation time 28321498 ps
CPU time 1.15 seconds
Started Aug 01 06:21:29 PM PDT 24
Finished Aug 01 06:21:31 PM PDT 24
Peak memory 217000 kb
Host smart-a5e55d21-4ec5-4208-a8cd-5d8d44880c9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113842615 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2113842615
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.182737478
Short name T495
Test name
Test status
Simulation time 235120547 ps
CPU time 1.16 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:21:34 PM PDT 24
Peak memory 219636 kb
Host smart-f7e5c439-4056-4479-b858-a073597a0346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182737478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.182737478
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2330533622
Short name T139
Test name
Test status
Simulation time 58494279 ps
CPU time 1.27 seconds
Started Aug 01 06:21:28 PM PDT 24
Finished Aug 01 06:21:29 PM PDT 24
Peak memory 218588 kb
Host smart-8cb9382d-9e8f-4ef1-a629-f0f1f26bddea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330533622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2330533622
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.652919330
Short name T545
Test name
Test status
Simulation time 26615328 ps
CPU time 1.04 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 223964 kb
Host smart-5e5cabce-374e-4fdb-b7a7-e1e3319e7d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652919330 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.652919330
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.14305527
Short name T739
Test name
Test status
Simulation time 44970419 ps
CPU time 0.92 seconds
Started Aug 01 06:21:32 PM PDT 24
Finished Aug 01 06:21:34 PM PDT 24
Peak memory 215268 kb
Host smart-d5b364d4-e500-4a04-8129-47e5439021e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14305527 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.14305527
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3555610924
Short name T843
Test name
Test status
Simulation time 168430620 ps
CPU time 2.42 seconds
Started Aug 01 06:21:38 PM PDT 24
Finished Aug 01 06:21:40 PM PDT 24
Peak memory 215252 kb
Host smart-388e8faa-bf62-4862-98f8-eaa9549faa78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555610924 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3555610924
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1439573669
Short name T231
Test name
Test status
Simulation time 74779936489 ps
CPU time 280.28 seconds
Started Aug 01 06:21:52 PM PDT 24
Finished Aug 01 06:26:33 PM PDT 24
Peak memory 219124 kb
Host smart-6c50016f-7b89-4c92-b495-639449f41096
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439573669 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1439573669
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.880821783
Short name T187
Test name
Test status
Simulation time 23072248 ps
CPU time 1.17 seconds
Started Aug 01 06:23:09 PM PDT 24
Finished Aug 01 06:23:10 PM PDT 24
Peak memory 219600 kb
Host smart-22e90cbf-d31f-46f5-9a9f-3cbb3e73596d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880821783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.880821783
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.2220464148
Short name T942
Test name
Test status
Simulation time 122269256 ps
CPU time 1.42 seconds
Started Aug 01 06:23:10 PM PDT 24
Finished Aug 01 06:23:11 PM PDT 24
Peak memory 218908 kb
Host smart-8155a446-e52b-4521-9851-ff256d700a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220464148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2220464148
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.1486920132
Short name T173
Test name
Test status
Simulation time 47412983 ps
CPU time 1.18 seconds
Started Aug 01 06:23:16 PM PDT 24
Finished Aug 01 06:23:17 PM PDT 24
Peak memory 218540 kb
Host smart-8267ca1f-aad8-44fb-b24f-89537acc6c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486920132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.1486920132
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.1154197561
Short name T480
Test name
Test status
Simulation time 114147728 ps
CPU time 1.29 seconds
Started Aug 01 06:23:10 PM PDT 24
Finished Aug 01 06:23:12 PM PDT 24
Peak memory 218460 kb
Host smart-1aa3794c-ebd9-4ebd-b9b4-7ce90248fc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154197561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1154197561
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.172724055
Short name T898
Test name
Test status
Simulation time 24172098 ps
CPU time 1.17 seconds
Started Aug 01 06:23:14 PM PDT 24
Finished Aug 01 06:23:15 PM PDT 24
Peak memory 219544 kb
Host smart-c62e3bf0-be0d-4b70-accd-bac4dd68fa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172724055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.172724055
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/163.edn_alert.1885544395
Short name T472
Test name
Test status
Simulation time 30042141 ps
CPU time 1.32 seconds
Started Aug 01 06:23:08 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 220252 kb
Host smart-b9ed40ec-0b4c-4d88-a4dc-ac35cca7c528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885544395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1885544395
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.2190595818
Short name T821
Test name
Test status
Simulation time 160150409 ps
CPU time 2.29 seconds
Started Aug 01 06:23:12 PM PDT 24
Finished Aug 01 06:23:14 PM PDT 24
Peak memory 219792 kb
Host smart-2961c6e0-ed1b-4302-aa01-2ba4b1321edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190595818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2190595818
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2064335738
Short name T138
Test name
Test status
Simulation time 24351494 ps
CPU time 1.24 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 218812 kb
Host smart-2943f00f-192e-4b21-b284-0419b15b8e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064335738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2064335738
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3563407092
Short name T535
Test name
Test status
Simulation time 32428296 ps
CPU time 1.39 seconds
Started Aug 01 06:23:14 PM PDT 24
Finished Aug 01 06:23:16 PM PDT 24
Peak memory 218732 kb
Host smart-6c77c586-8421-4200-80f5-2f4dca648742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563407092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3563407092
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3564877635
Short name T630
Test name
Test status
Simulation time 25861513 ps
CPU time 1.25 seconds
Started Aug 01 06:23:19 PM PDT 24
Finished Aug 01 06:23:20 PM PDT 24
Peak memory 219836 kb
Host smart-4cfc0c77-056e-4eab-9ded-02d38cf41126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564877635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3564877635
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1492339642
Short name T319
Test name
Test status
Simulation time 49361340 ps
CPU time 1.4 seconds
Started Aug 01 06:23:04 PM PDT 24
Finished Aug 01 06:23:06 PM PDT 24
Peak memory 218444 kb
Host smart-1a26c34f-d3c3-4aca-a6a6-22a7c2492c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492339642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1492339642
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.386341307
Short name T594
Test name
Test status
Simulation time 29871301 ps
CPU time 1.35 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 219872 kb
Host smart-e1e9a6f8-2f84-4b28-aae7-1b3645b56fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386341307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.386341307
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/167.edn_alert.1108412103
Short name T215
Test name
Test status
Simulation time 61653580 ps
CPU time 1.23 seconds
Started Aug 01 06:23:08 PM PDT 24
Finished Aug 01 06:23:10 PM PDT 24
Peak memory 221256 kb
Host smart-c6d326c9-53ce-4a87-88a4-50805af6fa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108412103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1108412103
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2094386672
Short name T498
Test name
Test status
Simulation time 148327168 ps
CPU time 1.09 seconds
Started Aug 01 06:23:02 PM PDT 24
Finished Aug 01 06:23:03 PM PDT 24
Peak memory 217292 kb
Host smart-790d4e72-e08d-4ff5-9d33-c1effe38fb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094386672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2094386672
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.3782499436
Short name T394
Test name
Test status
Simulation time 43574724 ps
CPU time 1.16 seconds
Started Aug 01 06:23:08 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 218552 kb
Host smart-cecae56d-d4f3-46e6-b645-97258db50d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782499436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3782499436
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2216239413
Short name T426
Test name
Test status
Simulation time 47800814 ps
CPU time 1.14 seconds
Started Aug 01 06:22:59 PM PDT 24
Finished Aug 01 06:23:00 PM PDT 24
Peak memory 215648 kb
Host smart-48877167-a6c4-47e8-a602-382fca1c5d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216239413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2216239413
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.322285977
Short name T688
Test name
Test status
Simulation time 115196491 ps
CPU time 1.25 seconds
Started Aug 01 06:23:12 PM PDT 24
Finished Aug 01 06:23:13 PM PDT 24
Peak memory 220024 kb
Host smart-863f6ae3-c8dd-4f2f-b27a-cffcf39ea271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322285977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.322285977
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.27759104
Short name T558
Test name
Test status
Simulation time 42140288 ps
CPU time 1.16 seconds
Started Aug 01 06:21:30 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 219540 kb
Host smart-c7e5848f-122c-4af1-8c1c-8e360dfc5602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27759104 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.27759104
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.473479794
Short name T474
Test name
Test status
Simulation time 66400530 ps
CPU time 1 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 206680 kb
Host smart-f57146a7-a833-406d-b34b-d2624a7cd90a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473479794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.473479794
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2914350739
Short name T839
Test name
Test status
Simulation time 26683442 ps
CPU time 0.82 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 216228 kb
Host smart-d6585112-a7b4-4fe4-a42b-d880b3ed271c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914350739 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2914350739
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2210299229
Short name T529
Test name
Test status
Simulation time 32950841 ps
CPU time 1.15 seconds
Started Aug 01 06:21:40 PM PDT 24
Finished Aug 01 06:21:41 PM PDT 24
Peak memory 218596 kb
Host smart-506af459-7dbe-4423-91a9-c99d5a6bcadb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210299229 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2210299229
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1422682856
Short name T605
Test name
Test status
Simulation time 72180270 ps
CPU time 1.03 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:21:34 PM PDT 24
Peak memory 219924 kb
Host smart-0de134a4-20bb-4b10-bd39-fb5e82b18f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422682856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1422682856
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3383800299
Short name T352
Test name
Test status
Simulation time 71069159 ps
CPU time 1.24 seconds
Started Aug 01 06:21:32 PM PDT 24
Finished Aug 01 06:21:33 PM PDT 24
Peak memory 219024 kb
Host smart-24248e83-2963-4b8f-b567-baa259b459af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383800299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3383800299
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_smoke.1142552739
Short name T476
Test name
Test status
Simulation time 67024669 ps
CPU time 0.96 seconds
Started Aug 01 06:21:53 PM PDT 24
Finished Aug 01 06:21:54 PM PDT 24
Peak memory 215244 kb
Host smart-366c22c2-7a00-4e1a-aeb2-6486c6b83b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142552739 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1142552739
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3936807043
Short name T131
Test name
Test status
Simulation time 221336111 ps
CPU time 4.27 seconds
Started Aug 01 06:21:29 PM PDT 24
Finished Aug 01 06:21:33 PM PDT 24
Peak memory 218484 kb
Host smart-b54b7528-7e95-4307-93d2-cb176d38b746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936807043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3936807043
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1626779437
Short name T54
Test name
Test status
Simulation time 48911123853 ps
CPU time 1194.72 seconds
Started Aug 01 06:21:36 PM PDT 24
Finished Aug 01 06:41:31 PM PDT 24
Peak memory 221416 kb
Host smart-d0ce62c4-6d05-455a-b4cd-8197a3a93875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626779437 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1626779437
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1478923159
Short name T961
Test name
Test status
Simulation time 274662239 ps
CPU time 1.24 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 219316 kb
Host smart-dbf99291-bb0d-485d-91d9-426d86f96216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478923159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1478923159
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.2542019975
Short name T644
Test name
Test status
Simulation time 107778745 ps
CPU time 1.67 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 218884 kb
Host smart-24217227-c29a-4e83-88f8-3797374d5efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542019975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2542019975
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1571774417
Short name T622
Test name
Test status
Simulation time 46090969 ps
CPU time 1.18 seconds
Started Aug 01 06:23:07 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 219836 kb
Host smart-a043e312-3039-4cf7-93e7-beb328fb04ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571774417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1571774417
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.510353056
Short name T824
Test name
Test status
Simulation time 41774933 ps
CPU time 1.57 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 217296 kb
Host smart-414ba8e8-7863-44d2-91df-23b9a890cf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510353056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.510353056
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1500766654
Short name T283
Test name
Test status
Simulation time 88454818 ps
CPU time 1.05 seconds
Started Aug 01 06:23:09 PM PDT 24
Finished Aug 01 06:23:11 PM PDT 24
Peak memory 218612 kb
Host smart-edca5865-9621-4869-8e69-8c161da542bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500766654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1500766654
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/173.edn_alert.3462949225
Short name T141
Test name
Test status
Simulation time 94062200 ps
CPU time 1.13 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 219360 kb
Host smart-ebc0562e-eaa9-4a8c-84c9-b94b2f98d1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462949225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3462949225
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.2665232785
Short name T505
Test name
Test status
Simulation time 55446241 ps
CPU time 1.31 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 218768 kb
Host smart-a1a774f0-251a-4048-8d65-7f708add08a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665232785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2665232785
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.2246630942
Short name T147
Test name
Test status
Simulation time 42788154 ps
CPU time 1.2 seconds
Started Aug 01 06:23:08 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 220360 kb
Host smart-0fcb0307-6c91-4259-85e3-b9af49dd234c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246630942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.2246630942
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.1280381935
Short name T306
Test name
Test status
Simulation time 180232171 ps
CPU time 1.22 seconds
Started Aug 01 06:23:05 PM PDT 24
Finished Aug 01 06:23:06 PM PDT 24
Peak memory 219000 kb
Host smart-3d5952ce-f914-4b94-a029-ebcd85a128b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280381935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1280381935
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.2507055884
Short name T188
Test name
Test status
Simulation time 83096590 ps
CPU time 1.04 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 218176 kb
Host smart-98955d52-509a-4583-80aa-8d48ada39862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507055884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.2507055884
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.3896159420
Short name T459
Test name
Test status
Simulation time 38410178 ps
CPU time 1.36 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 217164 kb
Host smart-6b69d890-ef95-4103-aaa5-9d7a7321aef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896159420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3896159420
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1118207980
Short name T170
Test name
Test status
Simulation time 32070766 ps
CPU time 1.31 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 220984 kb
Host smart-214d8c85-24f2-4877-829d-e94f315c2430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118207980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1118207980
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.1311681161
Short name T88
Test name
Test status
Simulation time 380641281 ps
CPU time 4.5 seconds
Started Aug 01 06:23:02 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 220260 kb
Host smart-dcd9ac76-d63a-4192-8725-0fc92b8780ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311681161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1311681161
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2167570716
Short name T462
Test name
Test status
Simulation time 72657371 ps
CPU time 1.67 seconds
Started Aug 01 06:23:07 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 218656 kb
Host smart-9ec2a3c8-82f6-4dc4-9b7c-b32f1d85265d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167570716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2167570716
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2604911060
Short name T483
Test name
Test status
Simulation time 47710332 ps
CPU time 1.13 seconds
Started Aug 01 06:23:11 PM PDT 24
Finished Aug 01 06:23:12 PM PDT 24
Peak memory 218640 kb
Host smart-09afc3d1-e1a2-4142-9bc1-2274b1ba38b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604911060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2604911060
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.2502392559
Short name T807
Test name
Test status
Simulation time 40540337 ps
CPU time 1.43 seconds
Started Aug 01 06:23:07 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 220032 kb
Host smart-45cf4fae-71dc-49d7-9441-acf218657046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502392559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2502392559
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2501117084
Short name T166
Test name
Test status
Simulation time 82079846 ps
CPU time 1.28 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 219608 kb
Host smart-71fa7361-8332-49fb-8b30-ba33de198637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501117084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2501117084
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.3251154172
Short name T883
Test name
Test status
Simulation time 42039820 ps
CPU time 1.44 seconds
Started Aug 01 06:23:07 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 218624 kb
Host smart-111212f7-316e-44f4-92ab-46bbc9aae57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251154172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3251154172
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3288860063
Short name T931
Test name
Test status
Simulation time 92268558 ps
CPU time 1.13 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:21:36 PM PDT 24
Peak memory 219876 kb
Host smart-e47c2bb6-958d-45c2-9ff0-602583f88e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288860063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3288860063
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.116321552
Short name T991
Test name
Test status
Simulation time 82706677 ps
CPU time 0.89 seconds
Started Aug 01 06:21:30 PM PDT 24
Finished Aug 01 06:21:31 PM PDT 24
Peak memory 214840 kb
Host smart-a7707092-b1d2-4c91-abc1-33097b8033d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116321552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.116321552
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.735018257
Short name T905
Test name
Test status
Simulation time 19981203 ps
CPU time 0.86 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:21:36 PM PDT 24
Peak memory 215376 kb
Host smart-2a0e88e1-facb-4f6a-a6af-7fefdca263ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735018257 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.735018257
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.711232046
Short name T566
Test name
Test status
Simulation time 59771099 ps
CPU time 1 seconds
Started Aug 01 06:21:30 PM PDT 24
Finished Aug 01 06:21:31 PM PDT 24
Peak memory 216888 kb
Host smart-c9eb52b2-5e09-42ef-9595-090a49b0b9c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711232046 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.711232046
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3626657771
Short name T205
Test name
Test status
Simulation time 23693084 ps
CPU time 0.89 seconds
Started Aug 01 06:21:24 PM PDT 24
Finished Aug 01 06:21:25 PM PDT 24
Peak memory 218576 kb
Host smart-e08a77cf-af87-43fa-a0c6-a69e9b1a5e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626657771 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3626657771
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3398176343
Short name T623
Test name
Test status
Simulation time 39414050 ps
CPU time 1.11 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:21:34 PM PDT 24
Peak memory 217332 kb
Host smart-02044389-901b-4a59-88df-d25dc77e7692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398176343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3398176343
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.969601387
Short name T58
Test name
Test status
Simulation time 76829626 ps
CPU time 0.86 seconds
Started Aug 01 06:21:40 PM PDT 24
Finished Aug 01 06:21:41 PM PDT 24
Peak memory 215112 kb
Host smart-18144093-040a-4df9-8ed0-0e4c294c4f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969601387 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.969601387
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2180164648
Short name T823
Test name
Test status
Simulation time 23881591 ps
CPU time 0.93 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:21:36 PM PDT 24
Peak memory 215296 kb
Host smart-fea81c74-bceb-4806-8292-9a9d19c02baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180164648 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2180164648
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3781034934
Short name T240
Test name
Test status
Simulation time 413076480 ps
CPU time 2.44 seconds
Started Aug 01 06:21:29 PM PDT 24
Finished Aug 01 06:21:31 PM PDT 24
Peak memory 217436 kb
Host smart-784f1b28-1676-4931-80d1-b1338f4d8935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781034934 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3781034934
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1408379005
Short name T736
Test name
Test status
Simulation time 38010418323 ps
CPU time 873.57 seconds
Started Aug 01 06:21:30 PM PDT 24
Finished Aug 01 06:36:04 PM PDT 24
Peak memory 219228 kb
Host smart-28c6e565-a52e-44fb-8742-a01d0cbb5667
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408379005 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1408379005
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1158986057
Short name T219
Test name
Test status
Simulation time 65497147 ps
CPU time 1.09 seconds
Started Aug 01 06:23:14 PM PDT 24
Finished Aug 01 06:23:20 PM PDT 24
Peak memory 218488 kb
Host smart-ff7a1758-f29f-4580-871b-c3180407dea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158986057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1158986057
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2683576386
Short name T530
Test name
Test status
Simulation time 51483639 ps
CPU time 1.29 seconds
Started Aug 01 06:23:03 PM PDT 24
Finished Aug 01 06:23:04 PM PDT 24
Peak memory 219828 kb
Host smart-58733fdf-f140-487e-b4a3-172cc058663a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683576386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2683576386
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.3861781614
Short name T171
Test name
Test status
Simulation time 22114675 ps
CPU time 1.11 seconds
Started Aug 01 06:23:14 PM PDT 24
Finished Aug 01 06:23:15 PM PDT 24
Peak memory 218516 kb
Host smart-8322d9b2-efcb-4f78-9a74-429ca74dbc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861781614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.3861781614
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3726990559
Short name T431
Test name
Test status
Simulation time 61998249 ps
CPU time 2.24 seconds
Started Aug 01 06:23:08 PM PDT 24
Finished Aug 01 06:23:10 PM PDT 24
Peak memory 220208 kb
Host smart-2226d4f8-aebd-4df7-9d65-143561315e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726990559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3726990559
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.2186491144
Short name T592
Test name
Test status
Simulation time 40706594 ps
CPU time 1.12 seconds
Started Aug 01 06:23:07 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 219832 kb
Host smart-7f678b57-5700-495a-9d1c-fb7a270482ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186491144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2186491144
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1833817788
Short name T813
Test name
Test status
Simulation time 42460881 ps
CPU time 1.14 seconds
Started Aug 01 06:23:18 PM PDT 24
Finished Aug 01 06:23:19 PM PDT 24
Peak memory 221144 kb
Host smart-7fd93d12-1ebd-45ee-bfc8-20caddbf953a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833817788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1833817788
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.3561807865
Short name T769
Test name
Test status
Simulation time 95366591 ps
CPU time 1.21 seconds
Started Aug 01 06:23:14 PM PDT 24
Finished Aug 01 06:23:16 PM PDT 24
Peak memory 217356 kb
Host smart-871fdd3d-db4c-4202-8358-a336adf94f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561807865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3561807865
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.2600891005
Short name T747
Test name
Test status
Simulation time 39478339 ps
CPU time 1.18 seconds
Started Aug 01 06:23:07 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 219784 kb
Host smart-68b84049-4635-4a79-a919-870f9692e21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600891005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2600891005
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.1423855483
Short name T429
Test name
Test status
Simulation time 165089189 ps
CPU time 2.4 seconds
Started Aug 01 06:23:10 PM PDT 24
Finished Aug 01 06:23:13 PM PDT 24
Peak memory 220064 kb
Host smart-e4c742c2-41d4-4a77-ac76-922b338c9643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423855483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1423855483
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.853691920
Short name T179
Test name
Test status
Simulation time 24585569 ps
CPU time 1.18 seconds
Started Aug 01 06:23:14 PM PDT 24
Finished Aug 01 06:23:15 PM PDT 24
Peak memory 219260 kb
Host smart-e9372139-941b-4471-a9b1-9891e03b2507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853691920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.853691920
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.3852556352
Short name T439
Test name
Test status
Simulation time 38319173 ps
CPU time 1.39 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:08 PM PDT 24
Peak memory 218388 kb
Host smart-dd9a0a17-654e-4586-8c5d-2717149bf300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852556352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3852556352
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.717978438
Short name T735
Test name
Test status
Simulation time 26908018 ps
CPU time 1.21 seconds
Started Aug 01 06:23:05 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 215628 kb
Host smart-a3df5bec-d33c-42b7-841d-d50f410a182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717978438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.717978438
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.3015509407
Short name T619
Test name
Test status
Simulation time 46084725 ps
CPU time 1.2 seconds
Started Aug 01 06:23:13 PM PDT 24
Finished Aug 01 06:23:15 PM PDT 24
Peak memory 220032 kb
Host smart-6272c76d-b09f-4de2-afde-529849b93cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015509407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3015509407
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1986953179
Short name T760
Test name
Test status
Simulation time 24712419 ps
CPU time 1.21 seconds
Started Aug 01 06:23:15 PM PDT 24
Finished Aug 01 06:23:16 PM PDT 24
Peak memory 220976 kb
Host smart-8f32e60e-8d2e-494b-a2f1-c7edcaaf9eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986953179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1986953179
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.844486503
Short name T531
Test name
Test status
Simulation time 40822380 ps
CPU time 1.42 seconds
Started Aug 01 06:23:10 PM PDT 24
Finished Aug 01 06:23:12 PM PDT 24
Peak memory 220308 kb
Host smart-b7fcf7bd-832a-46bd-99c8-433fd96d8556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844486503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.844486503
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.4139442666
Short name T710
Test name
Test status
Simulation time 65985826 ps
CPU time 1.19 seconds
Started Aug 01 06:23:08 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 219392 kb
Host smart-52dbbf31-ea51-428b-9f86-f1610943cfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139442666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.4139442666
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.14149057
Short name T381
Test name
Test status
Simulation time 77710752 ps
CPU time 1.31 seconds
Started Aug 01 06:23:12 PM PDT 24
Finished Aug 01 06:23:14 PM PDT 24
Peak memory 218528 kb
Host smart-76d5c683-471c-42bc-a30a-d8ac7fb6c9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14149057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.14149057
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3686597648
Short name T330
Test name
Test status
Simulation time 63094924 ps
CPU time 1.12 seconds
Started Aug 01 06:23:09 PM PDT 24
Finished Aug 01 06:23:20 PM PDT 24
Peak memory 219088 kb
Host smart-3c78cdb9-e126-4ad0-b67d-25646ebeac4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686597648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3686597648
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.1336444801
Short name T884
Test name
Test status
Simulation time 174237959 ps
CPU time 2.39 seconds
Started Aug 01 06:23:05 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 219592 kb
Host smart-ab58bf79-c0d3-409a-ab7f-7f8f4ce98323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336444801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1336444801
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.792656668
Short name T840
Test name
Test status
Simulation time 22038981 ps
CPU time 1.14 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:28 PM PDT 24
Peak memory 219964 kb
Host smart-c3ea9956-8d6c-4419-8e5a-edbfc92e7d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792656668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.792656668
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1510901307
Short name T968
Test name
Test status
Simulation time 24064439 ps
CPU time 0.89 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 206664 kb
Host smart-ca070609-763e-4f76-b189-222ed9f3f154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510901307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1510901307
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.237475140
Short name T781
Test name
Test status
Simulation time 46253318 ps
CPU time 0.82 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:21:36 PM PDT 24
Peak memory 216184 kb
Host smart-1ded1a40-525f-4280-b888-c390331f22eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237475140 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.237475140
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1101790099
Short name T17
Test name
Test status
Simulation time 38772034 ps
CPU time 1.03 seconds
Started Aug 01 06:21:34 PM PDT 24
Finished Aug 01 06:21:35 PM PDT 24
Peak memory 216716 kb
Host smart-d557c4c6-d7d6-46a0-820d-21497914432c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101790099 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1101790099
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3746160819
Short name T151
Test name
Test status
Simulation time 31694929 ps
CPU time 1.06 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:21:37 PM PDT 24
Peak memory 219700 kb
Host smart-bfd6fd5a-dab4-4eb9-96ba-9ab445a8a7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746160819 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3746160819
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_intr.2500100820
Short name T528
Test name
Test status
Simulation time 58066623 ps
CPU time 0.97 seconds
Started Aug 01 06:21:32 PM PDT 24
Finished Aug 01 06:21:33 PM PDT 24
Peak memory 223772 kb
Host smart-006c5771-99e1-48cb-b037-0463080c6f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500100820 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2500100820
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3782209247
Short name T833
Test name
Test status
Simulation time 14873185 ps
CPU time 0.94 seconds
Started Aug 01 06:21:44 PM PDT 24
Finished Aug 01 06:21:45 PM PDT 24
Peak memory 215296 kb
Host smart-ccb2008d-6a8d-4468-8e22-416ba3ac17df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782209247 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3782209247
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1492786851
Short name T349
Test name
Test status
Simulation time 280901515 ps
CPU time 3.19 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:21:36 PM PDT 24
Peak memory 218544 kb
Host smart-c85c9a9b-101a-49a6-9eb7-10f9ce300050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492786851 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1492786851
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1982897277
Short name T890
Test name
Test status
Simulation time 69487460875 ps
CPU time 1305.92 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:43:21 PM PDT 24
Peak memory 221556 kb
Host smart-ee910cf1-f758-4dcc-9e51-0dafdb0c3143
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982897277 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1982897277
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.1994254603
Short name T702
Test name
Test status
Simulation time 23347858 ps
CPU time 1.16 seconds
Started Aug 01 06:23:13 PM PDT 24
Finished Aug 01 06:23:14 PM PDT 24
Peak memory 219976 kb
Host smart-f996adc8-00dc-4aa7-b2d1-57f0b558d99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994254603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1994254603
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3231897678
Short name T507
Test name
Test status
Simulation time 60084969 ps
CPU time 1.62 seconds
Started Aug 01 06:23:05 PM PDT 24
Finished Aug 01 06:23:06 PM PDT 24
Peak memory 218832 kb
Host smart-5753a53e-da40-4b17-94b9-2c74bb54213d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231897678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3231897678
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.2585331485
Short name T195
Test name
Test status
Simulation time 65652841 ps
CPU time 1.1 seconds
Started Aug 01 06:23:09 PM PDT 24
Finished Aug 01 06:23:10 PM PDT 24
Peak memory 219632 kb
Host smart-76c1bc93-cbb2-49e1-a2af-99f84da251f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585331485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.2585331485
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.1932261934
Short name T537
Test name
Test status
Simulation time 77632192 ps
CPU time 1.18 seconds
Started Aug 01 06:23:12 PM PDT 24
Finished Aug 01 06:23:13 PM PDT 24
Peak memory 217380 kb
Host smart-38fcfbe4-9782-4fa7-bc14-a26482a1e5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932261934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1932261934
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.1448124004
Short name T562
Test name
Test status
Simulation time 48030825 ps
CPU time 1.16 seconds
Started Aug 01 06:22:59 PM PDT 24
Finished Aug 01 06:23:00 PM PDT 24
Peak memory 219372 kb
Host smart-c6c3dd3d-051e-4016-a5ef-fef7331ee756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448124004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.1448124004
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.1642459202
Short name T290
Test name
Test status
Simulation time 75726621 ps
CPU time 2.81 seconds
Started Aug 01 06:23:13 PM PDT 24
Finished Aug 01 06:23:16 PM PDT 24
Peak memory 218564 kb
Host smart-cd5a7447-5d1d-4a16-928b-52dcd85705c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642459202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1642459202
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.1177861872
Short name T965
Test name
Test status
Simulation time 49369418 ps
CPU time 1.14 seconds
Started Aug 01 06:23:10 PM PDT 24
Finished Aug 01 06:23:12 PM PDT 24
Peak memory 215648 kb
Host smart-645f74fe-731f-4ab7-a036-6db4bcefb15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177861872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.1177861872
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.357731568
Short name T32
Test name
Test status
Simulation time 71329007 ps
CPU time 1.37 seconds
Started Aug 01 06:23:09 PM PDT 24
Finished Aug 01 06:23:11 PM PDT 24
Peak memory 218816 kb
Host smart-d29eb89c-f462-489e-a392-909c35e3fd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357731568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.357731568
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3561053194
Short name T393
Test name
Test status
Simulation time 47077442 ps
CPU time 1.15 seconds
Started Aug 01 06:23:08 PM PDT 24
Finished Aug 01 06:23:09 PM PDT 24
Peak memory 217132 kb
Host smart-5657cfc7-1ca9-4cb2-a2a4-3e80e5f14ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561053194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3561053194
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.3042722402
Short name T334
Test name
Test status
Simulation time 63913900 ps
CPU time 1.15 seconds
Started Aug 01 06:23:10 PM PDT 24
Finished Aug 01 06:23:11 PM PDT 24
Peak memory 220032 kb
Host smart-c6bcc7dd-aee8-442b-8e0f-8c3f02b67a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042722402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3042722402
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.1489451395
Short name T307
Test name
Test status
Simulation time 232573801 ps
CPU time 3.01 seconds
Started Aug 01 06:23:09 PM PDT 24
Finished Aug 01 06:23:12 PM PDT 24
Peak memory 220292 kb
Host smart-b5a7f35b-8a74-485f-ba9b-f56432bae231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489451395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1489451395
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.1151379816
Short name T607
Test name
Test status
Simulation time 30686311 ps
CPU time 1.25 seconds
Started Aug 01 06:23:06 PM PDT 24
Finished Aug 01 06:23:07 PM PDT 24
Peak memory 220864 kb
Host smart-4a958139-2d14-49d8-89f5-8e661005330f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151379816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1151379816
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.1622433863
Short name T450
Test name
Test status
Simulation time 35050960 ps
CPU time 1.32 seconds
Started Aug 01 06:23:16 PM PDT 24
Finished Aug 01 06:23:17 PM PDT 24
Peak memory 217312 kb
Host smart-e8d88ef3-3705-400e-80c6-4ba06a1711db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622433863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1622433863
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3327424281
Short name T137
Test name
Test status
Simulation time 41344039 ps
CPU time 1.28 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 218708 kb
Host smart-469bc444-1a74-426c-aead-1342042321e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327424281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3327424281
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.270281309
Short name T858
Test name
Test status
Simulation time 79792398 ps
CPU time 1.11 seconds
Started Aug 01 06:23:18 PM PDT 24
Finished Aug 01 06:23:20 PM PDT 24
Peak memory 218816 kb
Host smart-3615c54b-cf8c-401a-bc30-2b4ad03d8051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270281309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.270281309
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.1529705611
Short name T748
Test name
Test status
Simulation time 29430049 ps
CPU time 1.24 seconds
Started Aug 01 06:23:32 PM PDT 24
Finished Aug 01 06:23:34 PM PDT 24
Peak memory 215664 kb
Host smart-dae19d1b-589b-4b89-bd9d-7c982901fed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529705611 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.1529705611
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3156302251
Short name T453
Test name
Test status
Simulation time 44963668 ps
CPU time 1.45 seconds
Started Aug 01 06:23:16 PM PDT 24
Finished Aug 01 06:23:17 PM PDT 24
Peak memory 218440 kb
Host smart-e5a6f152-f4e8-42ad-be2e-d30e7f4e6ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156302251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3156302251
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2576559276
Short name T647
Test name
Test status
Simulation time 23977098 ps
CPU time 1.22 seconds
Started Aug 01 06:23:17 PM PDT 24
Finished Aug 01 06:23:18 PM PDT 24
Peak memory 219552 kb
Host smart-ff27fd59-7569-4e82-929d-3b7c2f3eb224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576559276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2576559276
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.886009284
Short name T837
Test name
Test status
Simulation time 84836486 ps
CPU time 1.1 seconds
Started Aug 01 06:23:18 PM PDT 24
Finished Aug 01 06:23:19 PM PDT 24
Peak memory 217272 kb
Host smart-bcc970fc-b448-4e13-ae8e-ac71e1f93200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886009284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.886009284
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2927588750
Short name T683
Test name
Test status
Simulation time 69824654 ps
CPU time 1.02 seconds
Started Aug 01 06:21:16 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 218620 kb
Host smart-94edd684-7374-4e2b-8724-4ba59662f952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927588750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2927588750
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2519152745
Short name T804
Test name
Test status
Simulation time 36717792 ps
CPU time 0.83 seconds
Started Aug 01 06:21:19 PM PDT 24
Finished Aug 01 06:21:20 PM PDT 24
Peak memory 206712 kb
Host smart-69b984e7-b532-4165-b25f-34748d600b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519152745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2519152745
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.4189173945
Short name T665
Test name
Test status
Simulation time 33282673 ps
CPU time 0.87 seconds
Started Aug 01 06:21:16 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 215324 kb
Host smart-6c151b15-820f-4dc8-bc12-0b89d01aa7c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189173945 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.4189173945
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2109922845
Short name T177
Test name
Test status
Simulation time 48480572 ps
CPU time 1.43 seconds
Started Aug 01 06:21:16 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 216876 kb
Host smart-1baa23ab-5da1-443d-be63-9237a39e520a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109922845 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2109922845
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.202869767
Short name T47
Test name
Test status
Simulation time 20730360 ps
CPU time 1.23 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:15 PM PDT 24
Peak memory 229600 kb
Host smart-69bf0874-0e6f-430f-a887-1bf6abb2f2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202869767 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.202869767
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_intr.1656369696
Short name T522
Test name
Test status
Simulation time 20876913 ps
CPU time 1.06 seconds
Started Aug 01 06:21:24 PM PDT 24
Finished Aug 01 06:21:25 PM PDT 24
Peak memory 215264 kb
Host smart-1b4f1cc0-c343-4a0d-af46-b1d19c4d1a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656369696 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1656369696
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3170525835
Short name T925
Test name
Test status
Simulation time 38028944 ps
CPU time 0.9 seconds
Started Aug 01 06:21:14 PM PDT 24
Finished Aug 01 06:21:15 PM PDT 24
Peak memory 207024 kb
Host smart-39a81326-25d9-40cc-a975-0813e5960d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170525835 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3170525835
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.2644393076
Short name T475
Test name
Test status
Simulation time 28037990 ps
CPU time 0.9 seconds
Started Aug 01 06:21:14 PM PDT 24
Finished Aug 01 06:21:15 PM PDT 24
Peak memory 215256 kb
Host smart-493c5a3d-57da-4a2e-af08-879cec8bee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644393076 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2644393076
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1077825176
Short name T287
Test name
Test status
Simulation time 107462650 ps
CPU time 2.05 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:15 PM PDT 24
Peak memory 215232 kb
Host smart-7ada96f9-844f-4267-b6b0-0ef19578b3ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077825176 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1077825176
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.684706043
Short name T323
Test name
Test status
Simulation time 53788708535 ps
CPU time 877.77 seconds
Started Aug 01 06:21:16 PM PDT 24
Finished Aug 01 06:35:54 PM PDT 24
Peak memory 223620 kb
Host smart-fffb5906-c4a2-4642-a984-73cbe10541c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684706043 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.684706043
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3775840803
Short name T536
Test name
Test status
Simulation time 31846944 ps
CPU time 1.32 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:21:35 PM PDT 24
Peak memory 220280 kb
Host smart-e83cbed9-3386-4175-b385-17028d461d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775840803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3775840803
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.538909
Short name T371
Test name
Test status
Simulation time 16290481 ps
CPU time 0.98 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 215120 kb
Host smart-8f6e1439-1961-47f5-9ee1-3c6db7466b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.538909
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.411773724
Short name T719
Test name
Test status
Simulation time 13637513 ps
CPU time 0.85 seconds
Started Aug 01 06:21:37 PM PDT 24
Finished Aug 01 06:21:38 PM PDT 24
Peak memory 216164 kb
Host smart-8f2e8498-7ab1-44fd-a3d6-a192163165c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411773724 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.411773724
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3343855262
Short name T832
Test name
Test status
Simulation time 219893712 ps
CPU time 1.21 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:21:35 PM PDT 24
Peak memory 216776 kb
Host smart-998cab46-7a67-448f-95c2-48e098c4944f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343855262 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3343855262
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.42196566
Short name T699
Test name
Test status
Simulation time 26034243 ps
CPU time 1 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 219660 kb
Host smart-1730c16f-fe88-4333-87ef-04de4cd51a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42196566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.42196566
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1084213149
Short name T713
Test name
Test status
Simulation time 48332833 ps
CPU time 1.24 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:21:36 PM PDT 24
Peak memory 219952 kb
Host smart-52b8f5fd-c365-47f7-b068-a461a9dd789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084213149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1084213149
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.329226387
Short name T876
Test name
Test status
Simulation time 22730027 ps
CPU time 1.17 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:33 PM PDT 24
Peak memory 224004 kb
Host smart-e88dd1cd-fd79-4087-8773-cd9c61bfde89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329226387 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.329226387
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1336516501
Short name T611
Test name
Test status
Simulation time 25749630 ps
CPU time 0.9 seconds
Started Aug 01 06:21:34 PM PDT 24
Finished Aug 01 06:21:35 PM PDT 24
Peak memory 215276 kb
Host smart-8b3e5854-3ba8-42c3-b435-f3674c4274ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336516501 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1336516501
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2778617818
Short name T342
Test name
Test status
Simulation time 690672672 ps
CPU time 6.01 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:21:40 PM PDT 24
Peak memory 215296 kb
Host smart-896fb19f-7263-48ca-8ab4-2f2fd432b7de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778617818 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2778617818
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1472860058
Short name T22
Test name
Test status
Simulation time 77361715719 ps
CPU time 507.19 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:29:58 PM PDT 24
Peak memory 218320 kb
Host smart-80bd4ae3-b203-4331-9908-36fd2e60b0ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472860058 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1472860058
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3286615238
Short name T540
Test name
Test status
Simulation time 41085111 ps
CPU time 1 seconds
Started Aug 01 06:23:18 PM PDT 24
Finished Aug 01 06:23:19 PM PDT 24
Peak memory 217444 kb
Host smart-6bb5db33-b55d-4a86-bb70-e2dd444215d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286615238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3286615238
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1585931975
Short name T564
Test name
Test status
Simulation time 59455221 ps
CPU time 2.03 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:44 PM PDT 24
Peak memory 219840 kb
Host smart-af8ca427-4361-4f50-8a17-aabb05f71ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585931975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1585931975
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2020092250
Short name T573
Test name
Test status
Simulation time 45761652 ps
CPU time 0.91 seconds
Started Aug 01 06:23:17 PM PDT 24
Finished Aug 01 06:23:18 PM PDT 24
Peak memory 219268 kb
Host smart-e83971b2-f093-4b95-994b-7c72310e67ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020092250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2020092250
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.4112082318
Short name T945
Test name
Test status
Simulation time 103047973 ps
CPU time 1.52 seconds
Started Aug 01 06:23:34 PM PDT 24
Finished Aug 01 06:23:35 PM PDT 24
Peak memory 218812 kb
Host smart-c65e433e-42e1-4e7d-84c8-513aed4b9f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112082318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.4112082318
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3947276656
Short name T473
Test name
Test status
Simulation time 128447208 ps
CPU time 1.22 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 218908 kb
Host smart-c3c3f492-0e4f-4a7a-abe7-d992a9eae8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947276656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3947276656
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.818425603
Short name T320
Test name
Test status
Simulation time 65715962 ps
CPU time 2.04 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:22 PM PDT 24
Peak memory 217576 kb
Host smart-baed2633-feac-411e-a5ad-11cb61d88788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818425603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.818425603
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2901813812
Short name T471
Test name
Test status
Simulation time 44140688 ps
CPU time 1.63 seconds
Started Aug 01 06:23:19 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 218536 kb
Host smart-efa60a0f-d37c-4bb4-a3c0-2d769f64cba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901813812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2901813812
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.636013062
Short name T722
Test name
Test status
Simulation time 58778798 ps
CPU time 0.97 seconds
Started Aug 01 06:23:19 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 217196 kb
Host smart-d3e87fae-fd50-4999-8ee8-4004aab1c211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636013062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.636013062
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3168538870
Short name T703
Test name
Test status
Simulation time 52335717 ps
CPU time 1.17 seconds
Started Aug 01 06:21:30 PM PDT 24
Finished Aug 01 06:21:31 PM PDT 24
Peak memory 219540 kb
Host smart-6a0074dd-4a1d-4729-9561-58e4bb3773f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168538870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3168538870
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2433677531
Short name T690
Test name
Test status
Simulation time 51477826 ps
CPU time 1.05 seconds
Started Aug 01 06:21:30 PM PDT 24
Finished Aug 01 06:21:31 PM PDT 24
Peak memory 214928 kb
Host smart-c16c84c7-832b-48c0-99a3-72949bd2eb98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433677531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2433677531
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3413063767
Short name T463
Test name
Test status
Simulation time 21262476 ps
CPU time 0.85 seconds
Started Aug 01 06:21:36 PM PDT 24
Finished Aug 01 06:21:42 PM PDT 24
Peak memory 215908 kb
Host smart-84f707d8-ff1e-406c-aa66-125bd1975a08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413063767 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3413063767
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.4074997814
Short name T176
Test name
Test status
Simulation time 33133486 ps
CPU time 1.11 seconds
Started Aug 01 06:21:42 PM PDT 24
Finished Aug 01 06:21:43 PM PDT 24
Peak memory 216872 kb
Host smart-f92a3d5e-2a8d-4b38-9d26-be605638cae1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074997814 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.4074997814
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3402914836
Short name T197
Test name
Test status
Simulation time 97121977 ps
CPU time 0.84 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:21:34 PM PDT 24
Peak memory 218236 kb
Host smart-9a05f1b7-8a51-4c81-9b9f-07617a50d131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402914836 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3402914836
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.230697911
Short name T379
Test name
Test status
Simulation time 51545292 ps
CPU time 1.66 seconds
Started Aug 01 06:21:38 PM PDT 24
Finished Aug 01 06:21:40 PM PDT 24
Peak memory 218460 kb
Host smart-e79f0de4-705f-4721-b64d-017f9d29233f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230697911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.230697911
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2812016967
Short name T36
Test name
Test status
Simulation time 50407116 ps
CPU time 0.85 seconds
Started Aug 01 06:21:30 PM PDT 24
Finished Aug 01 06:21:31 PM PDT 24
Peak memory 214932 kb
Host smart-53739d9e-cb7d-4ff4-9221-5b7b48f37aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812016967 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2812016967
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3799803553
Short name T346
Test name
Test status
Simulation time 28002843 ps
CPU time 1 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:21:36 PM PDT 24
Peak memory 215240 kb
Host smart-7069769b-edcc-490d-a85f-b1b5f4544694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799803553 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3799803553
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.512271846
Short name T130
Test name
Test status
Simulation time 310641429 ps
CPU time 5.8 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:21:41 PM PDT 24
Peak memory 215236 kb
Host smart-775d0fa6-bd80-4dd7-86d7-2b16c04ede6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512271846 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.512271846
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.139509035
Short name T615
Test name
Test status
Simulation time 195466468484 ps
CPU time 1168.7 seconds
Started Aug 01 06:21:32 PM PDT 24
Finished Aug 01 06:41:01 PM PDT 24
Peak memory 223424 kb
Host smart-93c276a0-6fd6-4297-8a6c-e37ca77d2914
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139509035 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.139509035
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3799041515
Short name T69
Test name
Test status
Simulation time 166049609 ps
CPU time 2.09 seconds
Started Aug 01 06:23:16 PM PDT 24
Finished Aug 01 06:23:18 PM PDT 24
Peak memory 220476 kb
Host smart-578fe99c-de80-46d7-8651-88afbdd8205d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799041515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3799041515
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.493171313
Short name T818
Test name
Test status
Simulation time 67316102 ps
CPU time 1.08 seconds
Started Aug 01 06:23:19 PM PDT 24
Finished Aug 01 06:23:20 PM PDT 24
Peak memory 217280 kb
Host smart-60523c4c-187e-4809-bd45-64d5bfe9aed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493171313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.493171313
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1777349246
Short name T671
Test name
Test status
Simulation time 75485191 ps
CPU time 1.65 seconds
Started Aug 01 06:23:33 PM PDT 24
Finished Aug 01 06:23:35 PM PDT 24
Peak memory 220156 kb
Host smart-c8d48e84-0379-429b-ba38-6d9e90ac2b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777349246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1777349246
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2730811525
Short name T759
Test name
Test status
Simulation time 48031364 ps
CPU time 1.5 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:43 PM PDT 24
Peak memory 218176 kb
Host smart-747480e8-861c-414e-a50f-4560958716eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730811525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2730811525
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1138534283
Short name T717
Test name
Test status
Simulation time 25215688 ps
CPU time 1.27 seconds
Started Aug 01 06:23:39 PM PDT 24
Finished Aug 01 06:23:40 PM PDT 24
Peak memory 218384 kb
Host smart-24a0d5c0-a53c-4186-b2b1-59392cf8587f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138534283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1138534283
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2044840981
Short name T811
Test name
Test status
Simulation time 87818242 ps
CPU time 1.12 seconds
Started Aug 01 06:23:18 PM PDT 24
Finished Aug 01 06:23:20 PM PDT 24
Peak memory 217380 kb
Host smart-3a0e6352-8647-4a9c-a104-be3f07f29cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044840981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2044840981
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.4242141772
Short name T374
Test name
Test status
Simulation time 182455678 ps
CPU time 1.15 seconds
Started Aug 01 06:23:26 PM PDT 24
Finished Aug 01 06:23:27 PM PDT 24
Peak memory 219800 kb
Host smart-615ddea3-a9d0-4fb3-8df4-01d9d967a695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242141772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.4242141772
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.12749634
Short name T554
Test name
Test status
Simulation time 28054043 ps
CPU time 1.18 seconds
Started Aug 01 06:23:34 PM PDT 24
Finished Aug 01 06:23:35 PM PDT 24
Peak memory 217096 kb
Host smart-6b0222b2-c330-4a5d-9be5-f933f39e6ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12749634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.12749634
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2225249371
Short name T512
Test name
Test status
Simulation time 165288673 ps
CPU time 2.19 seconds
Started Aug 01 06:23:33 PM PDT 24
Finished Aug 01 06:23:36 PM PDT 24
Peak memory 220100 kb
Host smart-6a795e83-4192-4dfd-8506-0aeafaa1875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225249371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2225249371
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3172508187
Short name T785
Test name
Test status
Simulation time 121808285 ps
CPU time 1.48 seconds
Started Aug 01 06:23:37 PM PDT 24
Finished Aug 01 06:23:38 PM PDT 24
Peak memory 218948 kb
Host smart-47205deb-7898-464e-a91a-e541cedc4988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172508187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3172508187
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2354561502
Short name T548
Test name
Test status
Simulation time 72933421 ps
CPU time 1.08 seconds
Started Aug 01 06:21:40 PM PDT 24
Finished Aug 01 06:21:41 PM PDT 24
Peak memory 218376 kb
Host smart-bdbf653c-1fdd-4b26-89fc-8a80d79459ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354561502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2354561502
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2683606774
Short name T911
Test name
Test status
Simulation time 44660609 ps
CPU time 0.91 seconds
Started Aug 01 06:21:37 PM PDT 24
Finished Aug 01 06:21:39 PM PDT 24
Peak memory 214980 kb
Host smart-22df6037-37e0-41cb-bda1-956d990a3052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683606774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2683606774
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1791327219
Short name T249
Test name
Test status
Simulation time 102124606 ps
CPU time 1.07 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:21:36 PM PDT 24
Peak memory 219536 kb
Host smart-c2cdaaff-291e-4839-b716-10bb90abcb89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791327219 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1791327219
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3067978423
Short name T436
Test name
Test status
Simulation time 37469178 ps
CPU time 0.82 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 219176 kb
Host smart-e9621c2b-d199-4961-a7cc-6cd0b4729693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067978423 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3067978423
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2175968014
Short name T572
Test name
Test status
Simulation time 80901999 ps
CPU time 1.45 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:33 PM PDT 24
Peak memory 218560 kb
Host smart-ab59005c-a503-4a46-8f02-f5509831503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175968014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2175968014
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_smoke.1751782095
Short name T684
Test name
Test status
Simulation time 51846993 ps
CPU time 0.92 seconds
Started Aug 01 06:21:32 PM PDT 24
Finished Aug 01 06:21:34 PM PDT 24
Peak memory 215272 kb
Host smart-b1b719ff-34cc-483d-af15-be5d7e02d58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751782095 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1751782095
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2296282700
Short name T236
Test name
Test status
Simulation time 194116068 ps
CPU time 3.97 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:21:37 PM PDT 24
Peak memory 220108 kb
Host smart-47ca0b6d-a4a7-4ab5-82ec-3cd3f647cd1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296282700 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2296282700
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3105312829
Short name T954
Test name
Test status
Simulation time 101013560308 ps
CPU time 579.51 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:31:13 PM PDT 24
Peak memory 219616 kb
Host smart-80c33519-5c7d-4d64-aafe-173f9b99b568
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105312829 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3105312829
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1257197544
Short name T596
Test name
Test status
Simulation time 50832953 ps
CPU time 1.39 seconds
Started Aug 01 06:23:18 PM PDT 24
Finished Aug 01 06:23:19 PM PDT 24
Peak memory 218880 kb
Host smart-0d8409e8-8630-4330-b73a-fd5c3db446a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257197544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1257197544
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2417208900
Short name T20
Test name
Test status
Simulation time 18920871 ps
CPU time 1.04 seconds
Started Aug 01 06:23:19 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 217236 kb
Host smart-ed7388e2-8c4e-4706-8294-7a50c5334cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417208900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2417208900
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3091913626
Short name T819
Test name
Test status
Simulation time 67943659 ps
CPU time 1.05 seconds
Started Aug 01 06:23:19 PM PDT 24
Finished Aug 01 06:23:20 PM PDT 24
Peak memory 217468 kb
Host smart-840991d9-0d42-4fc3-8e1f-cf84e048bfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091913626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3091913626
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.897423209
Short name T361
Test name
Test status
Simulation time 83692323 ps
CPU time 1.12 seconds
Started Aug 01 06:23:18 PM PDT 24
Finished Aug 01 06:23:19 PM PDT 24
Peak memory 217292 kb
Host smart-f26a21d2-533f-4246-b00e-953fe4a861d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897423209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.897423209
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.426685171
Short name T805
Test name
Test status
Simulation time 79205245 ps
CPU time 1.16 seconds
Started Aug 01 06:23:16 PM PDT 24
Finished Aug 01 06:23:17 PM PDT 24
Peak memory 219956 kb
Host smart-add04266-166c-468a-8324-09943d39e38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426685171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.426685171
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.4107367885
Short name T424
Test name
Test status
Simulation time 48697735 ps
CPU time 1.42 seconds
Started Aug 01 06:23:19 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 218372 kb
Host smart-0ed77f4f-bda3-44db-b446-973ae50ae206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107367885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.4107367885
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3532060249
Short name T608
Test name
Test status
Simulation time 37281827 ps
CPU time 0.95 seconds
Started Aug 01 06:23:19 PM PDT 24
Finished Aug 01 06:23:20 PM PDT 24
Peak memory 215224 kb
Host smart-eb0128e3-c07c-4f19-923c-cfedc963cdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532060249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3532060249
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.925477169
Short name T934
Test name
Test status
Simulation time 43702290 ps
CPU time 1.41 seconds
Started Aug 01 06:23:15 PM PDT 24
Finished Aug 01 06:23:17 PM PDT 24
Peak memory 217476 kb
Host smart-5b78c2e0-3306-4bb9-8a7a-19c01a3eed28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925477169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.925477169
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3211230885
Short name T373
Test name
Test status
Simulation time 40479417 ps
CPU time 1.39 seconds
Started Aug 01 06:23:19 PM PDT 24
Finished Aug 01 06:23:20 PM PDT 24
Peak memory 218420 kb
Host smart-81519f22-5669-46c5-ad6b-75aa35a7dda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211230885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3211230885
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2688638851
Short name T609
Test name
Test status
Simulation time 63544186 ps
CPU time 2.19 seconds
Started Aug 01 06:23:24 PM PDT 24
Finished Aug 01 06:23:27 PM PDT 24
Peak memory 219920 kb
Host smart-cddd6876-52fa-4df3-99d4-7bb01338a6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688638851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2688638851
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1198256830
Short name T796
Test name
Test status
Simulation time 39962491 ps
CPU time 1.1 seconds
Started Aug 01 06:21:34 PM PDT 24
Finished Aug 01 06:21:35 PM PDT 24
Peak memory 218632 kb
Host smart-b401b8e7-fd9a-4d13-a8b1-4e1b7e39de5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198256830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1198256830
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3280847239
Short name T980
Test name
Test status
Simulation time 14174226 ps
CPU time 0.9 seconds
Started Aug 01 06:21:36 PM PDT 24
Finished Aug 01 06:21:38 PM PDT 24
Peak memory 206708 kb
Host smart-b9af9ee5-7ec6-4991-822a-cd3dc3b7fe11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280847239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3280847239
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2737879613
Short name T104
Test name
Test status
Simulation time 10280242 ps
CPU time 0.9 seconds
Started Aug 01 06:21:34 PM PDT 24
Finished Aug 01 06:21:35 PM PDT 24
Peak memory 216216 kb
Host smart-3cde50f7-2b96-4239-bfeb-5867f99419f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737879613 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2737879613
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3223536863
Short name T365
Test name
Test status
Simulation time 29525400 ps
CPU time 1.25 seconds
Started Aug 01 06:21:36 PM PDT 24
Finished Aug 01 06:21:37 PM PDT 24
Peak memory 218324 kb
Host smart-6c6872e7-5cf1-4029-a284-84b1d0c08ae9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223536863 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3223536863
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.70040339
Short name T865
Test name
Test status
Simulation time 20088415 ps
CPU time 1.08 seconds
Started Aug 01 06:21:32 PM PDT 24
Finished Aug 01 06:21:33 PM PDT 24
Peak memory 218496 kb
Host smart-ee23410f-023b-4c3e-a2e9-82aa9e032517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70040339 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.70040339
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1420578488
Short name T565
Test name
Test status
Simulation time 43646064 ps
CPU time 1.41 seconds
Started Aug 01 06:21:40 PM PDT 24
Finished Aug 01 06:21:41 PM PDT 24
Peak memory 217168 kb
Host smart-18a9d1a8-5903-49a0-ab1b-02a0565d141c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420578488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1420578488
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2672232908
Short name T896
Test name
Test status
Simulation time 22103577 ps
CPU time 1.1 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 06:21:34 PM PDT 24
Peak memory 215832 kb
Host smart-26447c9c-4c57-4c48-b738-c4718444d642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672232908 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2672232908
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2659164126
Short name T416
Test name
Test status
Simulation time 15644627 ps
CPU time 0.97 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:21:36 PM PDT 24
Peak memory 215288 kb
Host smart-c33b0448-2cb1-424e-9990-e732c98361f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659164126 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2659164126
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.4015277245
Short name T428
Test name
Test status
Simulation time 974789328 ps
CPU time 5.55 seconds
Started Aug 01 06:21:28 PM PDT 24
Finished Aug 01 06:21:33 PM PDT 24
Peak memory 217560 kb
Host smart-d50ea1b1-a840-49c8-8b52-a8adbc659147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015277245 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.4015277245
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2293153047
Short name T549
Test name
Test status
Simulation time 101311980379 ps
CPU time 2351.17 seconds
Started Aug 01 06:21:33 PM PDT 24
Finished Aug 01 07:00:45 PM PDT 24
Peak memory 228584 kb
Host smart-d057076a-3f96-4615-9fd2-2b79d55371f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293153047 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2293153047
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.550199567
Short name T235
Test name
Test status
Simulation time 95015950 ps
CPU time 2.18 seconds
Started Aug 01 06:23:38 PM PDT 24
Finished Aug 01 06:23:41 PM PDT 24
Peak memory 220112 kb
Host smart-3043cda4-1bc8-4b02-89ca-7ac20afc01f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550199567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.550199567
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2807490585
Short name T300
Test name
Test status
Simulation time 54960844 ps
CPU time 1 seconds
Started Aug 01 06:23:34 PM PDT 24
Finished Aug 01 06:23:35 PM PDT 24
Peak memory 217352 kb
Host smart-cc3c5a76-16fb-42b0-b811-84723c80c122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807490585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2807490585
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.396389978
Short name T635
Test name
Test status
Simulation time 46688845 ps
CPU time 1.61 seconds
Started Aug 01 06:23:32 PM PDT 24
Finished Aug 01 06:23:34 PM PDT 24
Peak memory 215280 kb
Host smart-aa31a13e-3c0a-4761-b54b-b729558e5873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396389978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.396389978
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.782122530
Short name T937
Test name
Test status
Simulation time 82949399 ps
CPU time 1 seconds
Started Aug 01 06:23:29 PM PDT 24
Finished Aug 01 06:23:30 PM PDT 24
Peak memory 217152 kb
Host smart-b20a1c37-f766-4b90-9305-f82e416fed92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782122530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.782122530
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2567817335
Short name T941
Test name
Test status
Simulation time 62774910 ps
CPU time 1.14 seconds
Started Aug 01 06:23:27 PM PDT 24
Finished Aug 01 06:23:28 PM PDT 24
Peak memory 217416 kb
Host smart-03371b37-f617-41ee-aaf0-92e663b2b254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567817335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2567817335
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2950979377
Short name T317
Test name
Test status
Simulation time 272547313 ps
CPU time 3.52 seconds
Started Aug 01 06:23:22 PM PDT 24
Finished Aug 01 06:23:25 PM PDT 24
Peak memory 219720 kb
Host smart-3fd82938-b4f8-4fe2-9d6a-b7b43e5e47c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950979377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2950979377
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3649103997
Short name T915
Test name
Test status
Simulation time 50406184 ps
CPU time 1.22 seconds
Started Aug 01 06:23:17 PM PDT 24
Finished Aug 01 06:23:18 PM PDT 24
Peak memory 218520 kb
Host smart-2b8b2280-fb6e-42c0-b9be-7080d5a2b926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649103997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3649103997
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1876095961
Short name T756
Test name
Test status
Simulation time 69521463 ps
CPU time 1.71 seconds
Started Aug 01 06:23:22 PM PDT 24
Finished Aug 01 06:23:24 PM PDT 24
Peak memory 218460 kb
Host smart-2ea260f2-22f2-42da-be4b-c715d6311125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876095961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1876095961
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.391643440
Short name T750
Test name
Test status
Simulation time 109730753 ps
CPU time 1.3 seconds
Started Aug 01 06:23:35 PM PDT 24
Finished Aug 01 06:23:37 PM PDT 24
Peak memory 219532 kb
Host smart-24f390fc-76ec-4147-90e5-cbf147532069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391643440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.391643440
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3429639861
Short name T780
Test name
Test status
Simulation time 45886822 ps
CPU time 1.17 seconds
Started Aug 01 06:21:56 PM PDT 24
Finished Aug 01 06:21:57 PM PDT 24
Peak memory 218676 kb
Host smart-1259d94b-4e1f-4965-959d-b74cf70d1984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429639861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3429639861
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.838631512
Short name T404
Test name
Test status
Simulation time 24269276 ps
CPU time 1.08 seconds
Started Aug 01 06:21:53 PM PDT 24
Finished Aug 01 06:21:55 PM PDT 24
Peak memory 215056 kb
Host smart-bec2a9ad-b3d2-4865-8d2c-cfd317cff34c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838631512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.838631512
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1778485850
Short name T117
Test name
Test status
Simulation time 12225618 ps
CPU time 0.9 seconds
Started Aug 01 06:21:57 PM PDT 24
Finished Aug 01 06:21:58 PM PDT 24
Peak memory 216388 kb
Host smart-1311009f-ba33-47b1-8c22-7249b7467cd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778485850 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1778485850
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2216781229
Short name T100
Test name
Test status
Simulation time 45337298 ps
CPU time 1.4 seconds
Started Aug 01 06:22:09 PM PDT 24
Finished Aug 01 06:22:10 PM PDT 24
Peak memory 216936 kb
Host smart-dc702b16-34c5-4f5d-9cf4-c743d9fc32e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216781229 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2216781229
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1573422667
Short name T936
Test name
Test status
Simulation time 17999906 ps
CPU time 1.18 seconds
Started Aug 01 06:21:57 PM PDT 24
Finished Aug 01 06:21:59 PM PDT 24
Peak memory 223920 kb
Host smart-858124f1-f08e-4eee-affa-4b4cffe0c1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573422667 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1573422667
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.842532996
Short name T963
Test name
Test status
Simulation time 25921299 ps
CPU time 1.17 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:21:36 PM PDT 24
Peak memory 217344 kb
Host smart-22a79d29-ebe6-465f-ae62-ca6aa92c8c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842532996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.842532996
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3296656696
Short name T84
Test name
Test status
Simulation time 49096898 ps
CPU time 0.81 seconds
Started Aug 01 06:21:42 PM PDT 24
Finished Aug 01 06:21:43 PM PDT 24
Peak memory 215748 kb
Host smart-7b59993e-a388-4930-bc34-43a37918d197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296656696 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3296656696
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3694575396
Short name T663
Test name
Test status
Simulation time 35165979 ps
CPU time 0.86 seconds
Started Aug 01 06:21:34 PM PDT 24
Finished Aug 01 06:21:35 PM PDT 24
Peak memory 215128 kb
Host smart-2f91dd2c-74c7-4dfb-8357-8ed6b9a64035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694575396 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3694575396
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3612659183
Short name T620
Test name
Test status
Simulation time 142436893 ps
CPU time 1.98 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:21:37 PM PDT 24
Peak memory 215272 kb
Host smart-ba49da83-6039-42fa-b933-554d33f8a44a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612659183 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3612659183
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3250621556
Short name T449
Test name
Test status
Simulation time 13432118209 ps
CPU time 340.08 seconds
Started Aug 01 06:21:35 PM PDT 24
Finished Aug 01 06:27:15 PM PDT 24
Peak memory 218528 kb
Host smart-84f05840-cd07-45b7-931b-d06ec9d159fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250621556 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3250621556
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3731563344
Short name T983
Test name
Test status
Simulation time 26728191 ps
CPU time 1.14 seconds
Started Aug 01 06:23:19 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 217308 kb
Host smart-76f0b9cb-96e9-46a0-89cc-71cce6d00c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731563344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3731563344
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1416426138
Short name T245
Test name
Test status
Simulation time 110385705 ps
CPU time 1.28 seconds
Started Aug 01 06:23:38 PM PDT 24
Finished Aug 01 06:23:39 PM PDT 24
Peak memory 218560 kb
Host smart-438235ea-bf2f-491e-bee1-29e764fcff70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416426138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1416426138
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2148395683
Short name T367
Test name
Test status
Simulation time 131801400 ps
CPU time 3.12 seconds
Started Aug 01 06:23:38 PM PDT 24
Finished Aug 01 06:23:42 PM PDT 24
Peak memory 218608 kb
Host smart-5c6e293f-a5d3-47e0-bbbb-b910bc2b1bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148395683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2148395683
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1978441535
Short name T524
Test name
Test status
Simulation time 52671761 ps
CPU time 1.18 seconds
Started Aug 01 06:23:19 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 217576 kb
Host smart-f7c99e64-97e0-46d9-b574-a53b615697fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978441535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1978441535
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3253942163
Short name T847
Test name
Test status
Simulation time 56978009 ps
CPU time 1.09 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 217268 kb
Host smart-0026440f-827e-4988-af67-9f4d9b4eea4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253942163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3253942163
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3326533197
Short name T410
Test name
Test status
Simulation time 106468700 ps
CPU time 1.42 seconds
Started Aug 01 06:23:32 PM PDT 24
Finished Aug 01 06:23:34 PM PDT 24
Peak memory 217340 kb
Host smart-601c2a1f-7556-4280-af8e-5d99361c9bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326533197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3326533197
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3046252920
Short name T922
Test name
Test status
Simulation time 60328086 ps
CPU time 1.79 seconds
Started Aug 01 06:23:37 PM PDT 24
Finished Aug 01 06:23:39 PM PDT 24
Peak memory 218500 kb
Host smart-94abdc0e-1e83-4925-88c1-72429084d4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046252920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3046252920
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2375038906
Short name T675
Test name
Test status
Simulation time 91604526 ps
CPU time 1.56 seconds
Started Aug 01 06:23:16 PM PDT 24
Finished Aug 01 06:23:18 PM PDT 24
Peak memory 218668 kb
Host smart-fcf27c94-f73d-41d4-b8f0-bd9d623f1441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375038906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2375038906
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1524371077
Short name T674
Test name
Test status
Simulation time 24848549 ps
CPU time 1.37 seconds
Started Aug 01 06:23:19 PM PDT 24
Finished Aug 01 06:23:20 PM PDT 24
Peak memory 217500 kb
Host smart-4fec7998-e3b5-4798-8ccb-828e05c5876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524371077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1524371077
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3709633742
Short name T479
Test name
Test status
Simulation time 105726685 ps
CPU time 1.47 seconds
Started Aug 01 06:23:22 PM PDT 24
Finished Aug 01 06:23:23 PM PDT 24
Peak memory 215332 kb
Host smart-b9d6b253-274a-4034-ac86-461fed35cf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709633742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3709633742
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3801415130
Short name T216
Test name
Test status
Simulation time 88429433 ps
CPU time 1.26 seconds
Started Aug 01 06:22:03 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 220620 kb
Host smart-c5fce682-c815-4b03-bdd4-29b2e12c96fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801415130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3801415130
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1306000055
Short name T916
Test name
Test status
Simulation time 26527599 ps
CPU time 0.89 seconds
Started Aug 01 06:21:54 PM PDT 24
Finished Aug 01 06:21:55 PM PDT 24
Peak memory 206680 kb
Host smart-0bfb427f-ed15-410b-aa36-d1de369f29b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306000055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1306000055
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2365022341
Short name T838
Test name
Test status
Simulation time 13084309 ps
CPU time 0.92 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:06 PM PDT 24
Peak memory 216452 kb
Host smart-dfe3eb69-885d-4e32-b8fa-cbaa2d5428de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365022341 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2365022341
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1262415347
Short name T875
Test name
Test status
Simulation time 30180018 ps
CPU time 1.22 seconds
Started Aug 01 06:22:03 PM PDT 24
Finished Aug 01 06:22:04 PM PDT 24
Peak memory 218144 kb
Host smart-a5c060fd-b1c9-40bc-adb6-0112296f13fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262415347 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1262415347
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.717642230
Short name T4
Test name
Test status
Simulation time 56118412 ps
CPU time 1.13 seconds
Started Aug 01 06:22:02 PM PDT 24
Finished Aug 01 06:22:03 PM PDT 24
Peak memory 229684 kb
Host smart-2dbd6945-15e1-4cc1-a58b-e0793177a936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717642230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.717642230
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1801329356
Short name T846
Test name
Test status
Simulation time 83040101 ps
CPU time 1.17 seconds
Started Aug 01 06:21:58 PM PDT 24
Finished Aug 01 06:21:59 PM PDT 24
Peak memory 218704 kb
Host smart-63706458-7ba3-4c0f-a334-a4e73dea0ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801329356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1801329356
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.212418472
Short name T85
Test name
Test status
Simulation time 40553119 ps
CPU time 0.9 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 215652 kb
Host smart-0bde751f-2573-4fb9-ba0b-7f390941cbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212418472 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.212418472
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.961981556
Short name T239
Test name
Test status
Simulation time 36884334 ps
CPU time 0.91 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 215240 kb
Host smart-b7b74f56-3c7a-49b2-8fe0-1141fb91dbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961981556 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.961981556
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.458234333
Short name T589
Test name
Test status
Simulation time 432024249 ps
CPU time 2.62 seconds
Started Aug 01 06:21:51 PM PDT 24
Finished Aug 01 06:21:53 PM PDT 24
Peak memory 215256 kb
Host smart-d3b5889e-a52e-407f-90bc-95659707fa58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458234333 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.458234333
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2235556662
Short name T935
Test name
Test status
Simulation time 205745867271 ps
CPU time 1250.49 seconds
Started Aug 01 06:21:50 PM PDT 24
Finished Aug 01 06:42:40 PM PDT 24
Peak memory 222796 kb
Host smart-bfe053f5-d749-4731-942c-133d2966e9cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235556662 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2235556662
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3252855463
Short name T731
Test name
Test status
Simulation time 70208763 ps
CPU time 1.63 seconds
Started Aug 01 06:23:17 PM PDT 24
Finished Aug 01 06:23:19 PM PDT 24
Peak memory 218504 kb
Host smart-354f308a-7555-4abd-ba34-2eb0dad5c186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252855463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3252855463
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2069989778
Short name T779
Test name
Test status
Simulation time 31969039 ps
CPU time 1.24 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:22 PM PDT 24
Peak memory 217364 kb
Host smart-61b56f80-59eb-4834-9664-b25ca3731af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069989778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2069989778
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1571931658
Short name T624
Test name
Test status
Simulation time 39927061 ps
CPU time 1.61 seconds
Started Aug 01 06:23:19 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 218464 kb
Host smart-3b760992-c058-4512-8d01-17d11b98aa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571931658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1571931658
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1972500560
Short name T351
Test name
Test status
Simulation time 58365840 ps
CPU time 1.01 seconds
Started Aug 01 06:23:19 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 217276 kb
Host smart-af22ab69-3ef8-4e3f-b085-d50956b72003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972500560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1972500560
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.888454188
Short name T492
Test name
Test status
Simulation time 37055072 ps
CPU time 1.04 seconds
Started Aug 01 06:23:36 PM PDT 24
Finished Aug 01 06:23:37 PM PDT 24
Peak memory 217244 kb
Host smart-6b7496fe-bf4c-4300-9ab7-8ddf51338a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888454188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.888454188
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2364798027
Short name T321
Test name
Test status
Simulation time 178837990 ps
CPU time 1.8 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:22 PM PDT 24
Peak memory 219184 kb
Host smart-9c990c08-b5d9-466f-9d3f-f638e0058dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364798027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2364798027
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1872032855
Short name T697
Test name
Test status
Simulation time 28856689 ps
CPU time 1.24 seconds
Started Aug 01 06:23:21 PM PDT 24
Finished Aug 01 06:23:22 PM PDT 24
Peak memory 217236 kb
Host smart-cae94a04-ef95-4470-a986-9e89c44cb97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872032855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1872032855
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.113174511
Short name T370
Test name
Test status
Simulation time 68555852 ps
CPU time 1.66 seconds
Started Aug 01 06:23:21 PM PDT 24
Finished Aug 01 06:23:23 PM PDT 24
Peak memory 218884 kb
Host smart-c0065fe4-416b-4fb8-8777-175017dd997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113174511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.113174511
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.208284312
Short name T326
Test name
Test status
Simulation time 88869116 ps
CPU time 1.54 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:22 PM PDT 24
Peak memory 218836 kb
Host smart-745cb62a-0b17-4103-93e3-29412e97a5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208284312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.208284312
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2397374302
Short name T132
Test name
Test status
Simulation time 28610254 ps
CPU time 1.24 seconds
Started Aug 01 06:22:01 PM PDT 24
Finished Aug 01 06:22:02 PM PDT 24
Peak memory 218628 kb
Host smart-e8f436da-31cf-4d61-a4be-3655e0319297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397374302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2397374302
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.378619149
Short name T353
Test name
Test status
Simulation time 25118104 ps
CPU time 1.04 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 206780 kb
Host smart-a4914515-d012-463b-8e2a-100b1eee12a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378619149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.378619149
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1446665874
Short name T707
Test name
Test status
Simulation time 357194961 ps
CPU time 1.12 seconds
Started Aug 01 06:21:52 PM PDT 24
Finished Aug 01 06:21:53 PM PDT 24
Peak memory 216940 kb
Host smart-b61880ab-d5fb-4e97-ae01-b2427de5411f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446665874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1446665874
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2067134698
Short name T960
Test name
Test status
Simulation time 26467592 ps
CPU time 0.87 seconds
Started Aug 01 06:21:43 PM PDT 24
Finished Aug 01 06:21:44 PM PDT 24
Peak memory 218320 kb
Host smart-e3320de0-7fde-46b7-869e-9837eba0227e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067134698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2067134698
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3779612944
Short name T441
Test name
Test status
Simulation time 39851552 ps
CPU time 1.56 seconds
Started Aug 01 06:22:00 PM PDT 24
Finished Aug 01 06:22:01 PM PDT 24
Peak memory 219688 kb
Host smart-334ecbf2-35e1-4453-b492-2b1f68dad444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779612944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3779612944
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1233246404
Short name T387
Test name
Test status
Simulation time 21640174 ps
CPU time 1.08 seconds
Started Aug 01 06:21:54 PM PDT 24
Finished Aug 01 06:21:55 PM PDT 24
Peak memory 215528 kb
Host smart-d95fbc45-2d85-4b93-a008-2a3ff992025d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233246404 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1233246404
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1621462466
Short name T467
Test name
Test status
Simulation time 29666409 ps
CPU time 0.93 seconds
Started Aug 01 06:21:55 PM PDT 24
Finished Aug 01 06:21:56 PM PDT 24
Peak memory 215260 kb
Host smart-8837727c-61f8-42c2-b193-49220c60c189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621462466 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1621462466
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3203295339
Short name T237
Test name
Test status
Simulation time 572436072 ps
CPU time 6.34 seconds
Started Aug 01 06:21:56 PM PDT 24
Finished Aug 01 06:22:02 PM PDT 24
Peak memory 217180 kb
Host smart-4776103c-f13d-4443-be97-349eb24a009b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203295339 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3203295339
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.181979107
Short name T433
Test name
Test status
Simulation time 50217807893 ps
CPU time 384.63 seconds
Started Aug 01 06:21:53 PM PDT 24
Finished Aug 01 06:28:18 PM PDT 24
Peak memory 223616 kb
Host smart-d9baf0ed-7b9c-4835-9a3b-21f240b159d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181979107 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.181979107
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.437432816
Short name T437
Test name
Test status
Simulation time 49788517 ps
CPU time 1.16 seconds
Started Aug 01 06:23:30 PM PDT 24
Finished Aug 01 06:23:31 PM PDT 24
Peak memory 217220 kb
Host smart-a0bd7bc1-bac6-4273-ba55-90765dc82c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437432816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.437432816
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.370828620
Short name T343
Test name
Test status
Simulation time 52741314 ps
CPU time 1.23 seconds
Started Aug 01 06:23:34 PM PDT 24
Finished Aug 01 06:23:36 PM PDT 24
Peak memory 219880 kb
Host smart-2e4eb049-4b34-4332-a7ba-904f112c4225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370828620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.370828620
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3339042385
Short name T599
Test name
Test status
Simulation time 80099297 ps
CPU time 1.12 seconds
Started Aug 01 06:23:34 PM PDT 24
Finished Aug 01 06:23:35 PM PDT 24
Peak memory 217408 kb
Host smart-4a33f97f-d7ad-4ede-9756-d05d1a50ca67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339042385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3339042385
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3249438652
Short name T9
Test name
Test status
Simulation time 498860687 ps
CPU time 3.94 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:25 PM PDT 24
Peak memory 220124 kb
Host smart-2920fdbf-6fca-4df8-82e5-6c7ad332f803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249438652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3249438652
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2646471824
Short name T705
Test name
Test status
Simulation time 23927807 ps
CPU time 1.1 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:22 PM PDT 24
Peak memory 217500 kb
Host smart-39125105-3a47-49f2-9c78-a27e57eb8fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646471824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2646471824
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1632317729
Short name T944
Test name
Test status
Simulation time 68150941 ps
CPU time 1.02 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:42 PM PDT 24
Peak memory 219212 kb
Host smart-b0d49d9b-422a-4a7c-ab53-7363e14495d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632317729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1632317729
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.430177865
Short name T33
Test name
Test status
Simulation time 75844705 ps
CPU time 1.25 seconds
Started Aug 01 06:23:22 PM PDT 24
Finished Aug 01 06:23:23 PM PDT 24
Peak memory 217352 kb
Host smart-e8278085-2220-423f-9446-36af68f88903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430177865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.430177865
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2905356597
Short name T511
Test name
Test status
Simulation time 49877128 ps
CPU time 1.25 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:22 PM PDT 24
Peak memory 217252 kb
Host smart-a306c4f8-61d7-4b44-853d-df2eeb1feab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905356597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2905356597
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.242592040
Short name T912
Test name
Test status
Simulation time 40484299 ps
CPU time 1.3 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 218464 kb
Host smart-f49f776f-ff09-4bba-aa2a-35f22efcb13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242592040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.242592040
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3635261487
Short name T908
Test name
Test status
Simulation time 29438333 ps
CPU time 1.36 seconds
Started Aug 01 06:23:34 PM PDT 24
Finished Aug 01 06:23:36 PM PDT 24
Peak memory 217464 kb
Host smart-ae724ea5-e109-4990-a3f3-12d0cd132fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635261487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3635261487
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3867908631
Short name T802
Test name
Test status
Simulation time 22808049 ps
CPU time 1.11 seconds
Started Aug 01 06:21:58 PM PDT 24
Finished Aug 01 06:21:59 PM PDT 24
Peak memory 219572 kb
Host smart-448cb254-bba8-4144-8807-14cc0ad7cfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867908631 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3867908631
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.463514209
Short name T234
Test name
Test status
Simulation time 53429473 ps
CPU time 0.97 seconds
Started Aug 01 06:21:53 PM PDT 24
Finished Aug 01 06:21:54 PM PDT 24
Peak memory 206720 kb
Host smart-22df5ef1-93cf-4d1e-b92b-0b9a6632c987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463514209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.463514209
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.4240879225
Short name T29
Test name
Test status
Simulation time 35211211 ps
CPU time 0.85 seconds
Started Aug 01 06:21:54 PM PDT 24
Finished Aug 01 06:21:54 PM PDT 24
Peak memory 215364 kb
Host smart-6f4b4974-f2ca-4964-90c8-3c25356f8fe9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240879225 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.4240879225
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3508354310
Short name T844
Test name
Test status
Simulation time 29114018 ps
CPU time 1.18 seconds
Started Aug 01 06:21:55 PM PDT 24
Finished Aug 01 06:21:56 PM PDT 24
Peak memory 218596 kb
Host smart-b9aa189b-8d09-4360-a63c-43a4c119276c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508354310 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3508354310
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3253046691
Short name T181
Test name
Test status
Simulation time 35650183 ps
CPU time 0.92 seconds
Started Aug 01 06:21:55 PM PDT 24
Finished Aug 01 06:21:56 PM PDT 24
Peak memory 218352 kb
Host smart-48feafbf-e6b6-4bcc-8875-b6d84ec2f939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253046691 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3253046691
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3857765129
Short name T301
Test name
Test status
Simulation time 100198252 ps
CPU time 2.21 seconds
Started Aug 01 06:21:51 PM PDT 24
Finished Aug 01 06:21:53 PM PDT 24
Peak memory 220004 kb
Host smart-4b6310d8-81a0-4a1e-b76a-a35fc4abc29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857765129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3857765129
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2415771752
Short name T634
Test name
Test status
Simulation time 21050465 ps
CPU time 1.06 seconds
Started Aug 01 06:21:52 PM PDT 24
Finished Aug 01 06:21:53 PM PDT 24
Peak memory 215532 kb
Host smart-3c0ab9e6-9bfd-42ca-bb19-bdaa2dedf5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415771752 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2415771752
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.238371423
Short name T636
Test name
Test status
Simulation time 44833196 ps
CPU time 0.91 seconds
Started Aug 01 06:22:07 PM PDT 24
Finished Aug 01 06:22:08 PM PDT 24
Peak memory 215020 kb
Host smart-63e8eb82-8e0f-4739-a322-e221e0e57723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238371423 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.238371423
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1805683103
Short name T324
Test name
Test status
Simulation time 535542111 ps
CPU time 3.31 seconds
Started Aug 01 06:22:05 PM PDT 24
Finished Aug 01 06:22:09 PM PDT 24
Peak memory 215372 kb
Host smart-c5c4857c-297c-409d-9f00-c9a4f3523a79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805683103 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1805683103
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1397552512
Short name T396
Test name
Test status
Simulation time 346853908953 ps
CPU time 679.24 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:33:30 PM PDT 24
Peak memory 221216 kb
Host smart-9048f338-dcfb-4406-affd-d420e669ea27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397552512 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1397552512
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2244104504
Short name T37
Test name
Test status
Simulation time 37295080 ps
CPU time 1.33 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 218448 kb
Host smart-850c94ce-a6a6-40ca-9653-dc5b7a464c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244104504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2244104504
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1709570430
Short name T291
Test name
Test status
Simulation time 94642479 ps
CPU time 1.27 seconds
Started Aug 01 06:23:36 PM PDT 24
Finished Aug 01 06:23:37 PM PDT 24
Peak memory 217432 kb
Host smart-04a4161c-1ef2-4f2b-8bac-33a97ff5edd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709570430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1709570430
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2491966130
Short name T892
Test name
Test status
Simulation time 46917848 ps
CPU time 1.79 seconds
Started Aug 01 06:23:21 PM PDT 24
Finished Aug 01 06:23:23 PM PDT 24
Peak memory 217344 kb
Host smart-cc258a7a-7682-4278-98f6-43bd4be82250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491966130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2491966130
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.470948777
Short name T598
Test name
Test status
Simulation time 52998702 ps
CPU time 1.07 seconds
Started Aug 01 06:23:20 PM PDT 24
Finished Aug 01 06:23:21 PM PDT 24
Peak memory 217348 kb
Host smart-72a6a6ac-d1f3-498c-9b01-690d0e4880a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470948777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.470948777
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1782002388
Short name T61
Test name
Test status
Simulation time 97371621 ps
CPU time 3.25 seconds
Started Aug 01 06:23:33 PM PDT 24
Finished Aug 01 06:23:36 PM PDT 24
Peak memory 220576 kb
Host smart-b117876d-93be-417c-8249-7ec88a61eb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782002388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1782002388
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1107581859
Short name T621
Test name
Test status
Simulation time 56389375 ps
CPU time 1.23 seconds
Started Aug 01 06:23:36 PM PDT 24
Finished Aug 01 06:23:37 PM PDT 24
Peak memory 217408 kb
Host smart-7bfd80cf-ffa0-4334-92d9-22e16c123483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107581859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1107581859
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1138880641
Short name T329
Test name
Test status
Simulation time 167213668 ps
CPU time 1.15 seconds
Started Aug 01 06:23:18 PM PDT 24
Finished Aug 01 06:23:20 PM PDT 24
Peak memory 219400 kb
Host smart-06da4501-27c6-4bc8-8bec-68c5de367e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138880641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1138880641
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3022681570
Short name T12
Test name
Test status
Simulation time 41356997 ps
CPU time 1.14 seconds
Started Aug 01 06:23:40 PM PDT 24
Finished Aug 01 06:23:41 PM PDT 24
Peak memory 217496 kb
Host smart-581340cd-acc3-4e7f-aaa5-8a11124e0fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022681570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3022681570
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1368973757
Short name T481
Test name
Test status
Simulation time 114973383 ps
CPU time 1.34 seconds
Started Aug 01 06:23:31 PM PDT 24
Finished Aug 01 06:23:33 PM PDT 24
Peak memory 218596 kb
Host smart-65be5324-1bf0-49d1-a276-78164d448417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368973757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1368973757
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1402760682
Short name T322
Test name
Test status
Simulation time 56475288 ps
CPU time 1.56 seconds
Started Aug 01 06:23:44 PM PDT 24
Finished Aug 01 06:23:45 PM PDT 24
Peak memory 218652 kb
Host smart-859e7f79-d5c0-4f26-a794-54493352ff16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402760682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1402760682
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3044418564
Short name T418
Test name
Test status
Simulation time 69399799 ps
CPU time 1.09 seconds
Started Aug 01 06:22:06 PM PDT 24
Finished Aug 01 06:22:07 PM PDT 24
Peak memory 218792 kb
Host smart-8946acf8-4ad0-43b4-be02-d74b12338de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044418564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3044418564
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3257731834
Short name T560
Test name
Test status
Simulation time 40025189 ps
CPU time 0.87 seconds
Started Aug 01 06:22:01 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 206556 kb
Host smart-183b8e29-adfd-400d-8246-87e226f9f5dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257731834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3257731834
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1880155138
Short name T974
Test name
Test status
Simulation time 27684193 ps
CPU time 0.8 seconds
Started Aug 01 06:21:54 PM PDT 24
Finished Aug 01 06:21:55 PM PDT 24
Peak memory 216268 kb
Host smart-ad8d0e07-ffd9-41bb-82a3-334a4115cd7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880155138 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1880155138
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2353801187
Short name T763
Test name
Test status
Simulation time 34351349 ps
CPU time 1.27 seconds
Started Aug 01 06:21:54 PM PDT 24
Finished Aug 01 06:21:55 PM PDT 24
Peak memory 216984 kb
Host smart-bb2681d0-ad75-43e3-90ac-d30b37ff8b8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353801187 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2353801187
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.405119186
Short name T737
Test name
Test status
Simulation time 27094493 ps
CPU time 1.25 seconds
Started Aug 01 06:21:57 PM PDT 24
Finished Aug 01 06:21:58 PM PDT 24
Peak memory 218688 kb
Host smart-3ecf5521-2a65-43d7-9c4a-3e3fe0a06b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405119186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.405119186
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2940573882
Short name T795
Test name
Test status
Simulation time 176395299 ps
CPU time 1.02 seconds
Started Aug 01 06:22:03 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 217244 kb
Host smart-2b3fc142-22a0-408f-806e-2171a26580d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940573882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2940573882
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2971124662
Short name T80
Test name
Test status
Simulation time 36756960 ps
CPU time 0.89 seconds
Started Aug 01 06:22:02 PM PDT 24
Finished Aug 01 06:22:03 PM PDT 24
Peak memory 215612 kb
Host smart-1fcade4b-0315-47f5-a1e2-10c1d06027e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971124662 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2971124662
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3973142807
Short name T641
Test name
Test status
Simulation time 27151979 ps
CPU time 0.95 seconds
Started Aug 01 06:21:51 PM PDT 24
Finished Aug 01 06:21:52 PM PDT 24
Peak memory 215224 kb
Host smart-10278de3-3c20-4275-8771-040067077fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973142807 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3973142807
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2114152320
Short name T704
Test name
Test status
Simulation time 243333418 ps
CPU time 1.97 seconds
Started Aug 01 06:21:59 PM PDT 24
Finished Aug 01 06:22:02 PM PDT 24
Peak memory 217468 kb
Host smart-f359eef1-f717-413e-b54e-9108bb44d279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114152320 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2114152320
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.594315641
Short name T224
Test name
Test status
Simulation time 40612491251 ps
CPU time 464.36 seconds
Started Aug 01 06:21:50 PM PDT 24
Finished Aug 01 06:29:35 PM PDT 24
Peak memory 223584 kb
Host smart-3da03342-ce5c-4eb9-be28-af0cdc20574e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594315641 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.594315641
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3329480215
Short name T979
Test name
Test status
Simulation time 73245211 ps
CPU time 2.53 seconds
Started Aug 01 06:23:46 PM PDT 24
Finished Aug 01 06:23:48 PM PDT 24
Peak memory 218668 kb
Host smart-d2530a89-9a83-4c7c-b141-aae71adaf2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329480215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3329480215
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2200291098
Short name T810
Test name
Test status
Simulation time 37097596 ps
CPU time 1.02 seconds
Started Aug 01 06:23:38 PM PDT 24
Finished Aug 01 06:23:39 PM PDT 24
Peak memory 217264 kb
Host smart-da2005ea-f9b1-49e6-8e05-2efef9a319df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200291098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2200291098
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.4085581937
Short name T597
Test name
Test status
Simulation time 369056365 ps
CPU time 4.36 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:46 PM PDT 24
Peak memory 218884 kb
Host smart-68f4b2b7-cfae-4845-a60d-41c4affd30ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085581937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.4085581937
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1611878420
Short name T966
Test name
Test status
Simulation time 83261151 ps
CPU time 1.39 seconds
Started Aug 01 06:23:45 PM PDT 24
Finished Aug 01 06:23:47 PM PDT 24
Peak memory 219092 kb
Host smart-d116adb6-c938-4f4c-bd23-94ae299af020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611878420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1611878420
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3434825385
Short name T407
Test name
Test status
Simulation time 89366173 ps
CPU time 1.21 seconds
Started Aug 01 06:23:38 PM PDT 24
Finished Aug 01 06:23:40 PM PDT 24
Peak memory 217496 kb
Host smart-bd5e935f-a33f-42bf-aa5d-50cb694f3043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434825385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3434825385
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3063228290
Short name T71
Test name
Test status
Simulation time 95051404 ps
CPU time 1.15 seconds
Started Aug 01 06:23:49 PM PDT 24
Finished Aug 01 06:23:51 PM PDT 24
Peak memory 217344 kb
Host smart-40ddc0a1-29a8-495e-9c95-6435a7f866c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063228290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3063228290
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.485758245
Short name T590
Test name
Test status
Simulation time 120606444 ps
CPU time 1.65 seconds
Started Aug 01 06:23:39 PM PDT 24
Finished Aug 01 06:23:41 PM PDT 24
Peak memory 219320 kb
Host smart-fb0ca6d7-cb9b-4c41-8428-4000a8d81098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485758245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.485758245
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1860775097
Short name T576
Test name
Test status
Simulation time 74396522 ps
CPU time 1.35 seconds
Started Aug 01 06:23:40 PM PDT 24
Finished Aug 01 06:23:41 PM PDT 24
Peak memory 218836 kb
Host smart-dde3da6f-9cc5-4988-8686-4c6419ad846c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860775097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1860775097
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2084469924
Short name T602
Test name
Test status
Simulation time 42425596 ps
CPU time 1.54 seconds
Started Aug 01 06:23:37 PM PDT 24
Finished Aug 01 06:23:39 PM PDT 24
Peak memory 217244 kb
Host smart-f4b5829f-f31a-41dc-9be1-d25e1f71487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084469924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2084469924
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2776482554
Short name T15
Test name
Test status
Simulation time 75915009 ps
CPU time 1.23 seconds
Started Aug 01 06:23:46 PM PDT 24
Finished Aug 01 06:23:48 PM PDT 24
Peak memory 219904 kb
Host smart-abe2364d-22dd-46d3-abb0-bfb533aead5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776482554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2776482554
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2510506428
Short name T755
Test name
Test status
Simulation time 25668017 ps
CPU time 1.17 seconds
Started Aug 01 06:22:05 PM PDT 24
Finished Aug 01 06:22:07 PM PDT 24
Peak memory 220896 kb
Host smart-c579f260-cd74-4c65-b50a-a39e9e70d7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510506428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2510506428
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2212507344
Short name T887
Test name
Test status
Simulation time 15179482 ps
CPU time 0.93 seconds
Started Aug 01 06:22:03 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 206692 kb
Host smart-4678b6ee-e9e4-404e-9004-434a88328ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212507344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2212507344
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3010342420
Short name T500
Test name
Test status
Simulation time 40560293 ps
CPU time 0.91 seconds
Started Aug 01 06:22:05 PM PDT 24
Finished Aug 01 06:22:07 PM PDT 24
Peak memory 215968 kb
Host smart-a749cfe2-95f5-47a5-838c-107eea192f8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010342420 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3010342420
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.4092553018
Short name T939
Test name
Test status
Simulation time 41054956 ps
CPU time 1.23 seconds
Started Aug 01 06:22:01 PM PDT 24
Finished Aug 01 06:22:03 PM PDT 24
Peak memory 219640 kb
Host smart-14014738-a063-4bc2-8edf-2f8c35fa4b53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092553018 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.4092553018
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2204367597
Short name T638
Test name
Test status
Simulation time 37258519 ps
CPU time 1.26 seconds
Started Aug 01 06:21:55 PM PDT 24
Finished Aug 01 06:21:57 PM PDT 24
Peak memory 225560 kb
Host smart-cc520aaa-4d2c-4acc-a7bb-8402c179f300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204367597 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2204367597
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.4230862252
Short name T308
Test name
Test status
Simulation time 57609434 ps
CPU time 0.96 seconds
Started Aug 01 06:21:55 PM PDT 24
Finished Aug 01 06:21:57 PM PDT 24
Peak memory 217356 kb
Host smart-1ba1a2b8-829b-4680-b4fc-52559e607514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230862252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.4230862252
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2321579303
Short name T242
Test name
Test status
Simulation time 24603400 ps
CPU time 0.98 seconds
Started Aug 01 06:21:56 PM PDT 24
Finished Aug 01 06:21:57 PM PDT 24
Peak memory 215316 kb
Host smart-90583909-ad09-471b-a960-c9c3c3feb75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321579303 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2321579303
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3627335948
Short name T417
Test name
Test status
Simulation time 16966500 ps
CPU time 0.98 seconds
Started Aug 01 06:21:59 PM PDT 24
Finished Aug 01 06:22:01 PM PDT 24
Peak memory 215248 kb
Host smart-49b7a729-9018-40b9-9013-51e9affc11e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627335948 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3627335948
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1854655057
Short name T640
Test name
Test status
Simulation time 473725474 ps
CPU time 6.88 seconds
Started Aug 01 06:21:56 PM PDT 24
Finished Aug 01 06:22:03 PM PDT 24
Peak memory 218472 kb
Host smart-fbab048a-0c62-45df-85cf-3eb0a8ad744e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854655057 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1854655057
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.786158744
Short name T797
Test name
Test status
Simulation time 8937807080 ps
CPU time 166.56 seconds
Started Aug 01 06:22:03 PM PDT 24
Finished Aug 01 06:24:49 PM PDT 24
Peak memory 218420 kb
Host smart-3078b2bb-2308-4ecd-b2ae-8799f435628e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786158744 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.786158744
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1523246046
Short name T25
Test name
Test status
Simulation time 35206776 ps
CPU time 1.35 seconds
Started Aug 01 06:23:31 PM PDT 24
Finished Aug 01 06:23:33 PM PDT 24
Peak memory 217440 kb
Host smart-d56b64c0-a61e-4edf-be65-910bac49618a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523246046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1523246046
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.412218697
Short name T315
Test name
Test status
Simulation time 126470346 ps
CPU time 1.52 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:42 PM PDT 24
Peak memory 218752 kb
Host smart-03b6b991-cfbd-433f-938d-9a42729766f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412218697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.412218697
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.175102404
Short name T364
Test name
Test status
Simulation time 43132360 ps
CPU time 1.2 seconds
Started Aug 01 06:23:31 PM PDT 24
Finished Aug 01 06:23:32 PM PDT 24
Peak memory 218488 kb
Host smart-33d6145d-dc1d-4bbd-9043-f8e3f5f0ab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175102404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.175102404
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2282389869
Short name T693
Test name
Test status
Simulation time 106869796 ps
CPU time 1.38 seconds
Started Aug 01 06:23:38 PM PDT 24
Finished Aug 01 06:23:40 PM PDT 24
Peak memory 217504 kb
Host smart-d2a3ce40-5dbd-4167-8291-ee8e6c8541b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282389869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2282389869
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1675565651
Short name T862
Test name
Test status
Simulation time 208180542 ps
CPU time 3.84 seconds
Started Aug 01 06:23:40 PM PDT 24
Finished Aug 01 06:23:44 PM PDT 24
Peak memory 218544 kb
Host smart-c11a33c9-5162-4234-9d88-785c1590b3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675565651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1675565651
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2712152073
Short name T600
Test name
Test status
Simulation time 64595045 ps
CPU time 0.97 seconds
Started Aug 01 06:23:42 PM PDT 24
Finished Aug 01 06:23:43 PM PDT 24
Peak memory 217248 kb
Host smart-68a7f79b-882e-417c-b3dc-99530e18cc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712152073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2712152073
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3222413315
Short name T652
Test name
Test status
Simulation time 162876383 ps
CPU time 1.84 seconds
Started Aug 01 06:23:49 PM PDT 24
Finished Aug 01 06:23:51 PM PDT 24
Peak memory 218860 kb
Host smart-e4ef6adb-9239-469e-84ae-7e16aa094893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222413315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3222413315
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2480580808
Short name T357
Test name
Test status
Simulation time 44158336 ps
CPU time 1.66 seconds
Started Aug 01 06:23:37 PM PDT 24
Finished Aug 01 06:23:39 PM PDT 24
Peak memory 219580 kb
Host smart-c4364977-35f7-4dc8-a385-c99c0607cb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480580808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2480580808
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2573869000
Short name T541
Test name
Test status
Simulation time 51636370 ps
CPU time 1.85 seconds
Started Aug 01 06:23:40 PM PDT 24
Finished Aug 01 06:23:42 PM PDT 24
Peak memory 218840 kb
Host smart-b06449cd-ceb4-4c11-8e9d-96f9440d14d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573869000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2573869000
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1705366834
Short name T39
Test name
Test status
Simulation time 73827018 ps
CPU time 1.1 seconds
Started Aug 01 06:23:34 PM PDT 24
Finished Aug 01 06:23:36 PM PDT 24
Peak memory 217212 kb
Host smart-0b10b6d8-3b43-4a39-975a-f2924470405f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705366834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1705366834
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1655758800
Short name T657
Test name
Test status
Simulation time 22391208 ps
CPU time 1.15 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:15 PM PDT 24
Peak memory 218596 kb
Host smart-e7277358-b176-4fb9-a624-a7c6d7475b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655758800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1655758800
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1975032948
Short name T746
Test name
Test status
Simulation time 31085637 ps
CPU time 0.94 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:14 PM PDT 24
Peak memory 215108 kb
Host smart-e7bc5ad3-0e42-43a1-95e6-ef4bc0d07ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975032948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1975032948
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2658326129
Short name T105
Test name
Test status
Simulation time 21145531 ps
CPU time 0.85 seconds
Started Aug 01 06:21:16 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 216220 kb
Host smart-c3927700-d1fe-4914-ab6e-b9337ab7e5fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658326129 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2658326129
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2591136749
Short name T753
Test name
Test status
Simulation time 213966076 ps
CPU time 1.13 seconds
Started Aug 01 06:21:18 PM PDT 24
Finished Aug 01 06:21:20 PM PDT 24
Peak memory 218496 kb
Host smart-c8a4f946-a63b-4388-9e1f-bb2ddbc6d4b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591136749 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2591136749
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_genbits.1322552450
Short name T539
Test name
Test status
Simulation time 37882688 ps
CPU time 1.21 seconds
Started Aug 01 06:21:15 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 219904 kb
Host smart-a5392eb6-084d-4760-b7dd-95145a8767c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322552450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1322552450
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3063935916
Short name T376
Test name
Test status
Simulation time 39482520 ps
CPU time 0.94 seconds
Started Aug 01 06:21:16 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 215532 kb
Host smart-9e5cf4d7-0e5b-4896-b557-7668dc41e9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063935916 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3063935916
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3843791784
Short name T709
Test name
Test status
Simulation time 19849790 ps
CPU time 1.08 seconds
Started Aug 01 06:21:17 PM PDT 24
Finished Aug 01 06:21:18 PM PDT 24
Peak memory 207088 kb
Host smart-0dd1c663-8d31-4d2c-871f-3481504caa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843791784 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3843791784
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.3638628004
Short name T762
Test name
Test status
Simulation time 55392722 ps
CPU time 0.83 seconds
Started Aug 01 06:21:16 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 215280 kb
Host smart-c09e96e8-1a03-4022-8029-d039c6119e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638628004 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3638628004
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3885812771
Short name T628
Test name
Test status
Simulation time 84681828 ps
CPU time 2.03 seconds
Started Aug 01 06:21:17 PM PDT 24
Finished Aug 01 06:21:19 PM PDT 24
Peak memory 215244 kb
Host smart-b01913b4-fa80-4f6c-82dc-f6d18feb27c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885812771 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3885812771
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2224359048
Short name T645
Test name
Test status
Simulation time 49242358224 ps
CPU time 557.95 seconds
Started Aug 01 06:21:17 PM PDT 24
Finished Aug 01 06:30:35 PM PDT 24
Peak memory 220916 kb
Host smart-9ebc4439-4561-46be-ba52-b57d7f5dac6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224359048 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2224359048
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.89648184
Short name T848
Test name
Test status
Simulation time 27317641 ps
CPU time 1.18 seconds
Started Aug 01 06:22:00 PM PDT 24
Finished Aug 01 06:22:01 PM PDT 24
Peak memory 220032 kb
Host smart-9d6c51dd-d6ac-4355-8cb2-98ca4dc22cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89648184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.89648184
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.719748347
Short name T745
Test name
Test status
Simulation time 115536040 ps
CPU time 1 seconds
Started Aug 01 06:22:02 PM PDT 24
Finished Aug 01 06:22:03 PM PDT 24
Peak memory 206676 kb
Host smart-db8c011a-ea7b-481b-a53a-ee40e8420eca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719748347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.719748347
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3984822478
Short name T112
Test name
Test status
Simulation time 22553810 ps
CPU time 0.93 seconds
Started Aug 01 06:22:05 PM PDT 24
Finished Aug 01 06:22:06 PM PDT 24
Peak memory 216268 kb
Host smart-0621199f-5997-4fcf-9b82-1519220b2647
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984822478 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3984822478
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.4273138601
Short name T664
Test name
Test status
Simulation time 66330186 ps
CPU time 1.21 seconds
Started Aug 01 06:21:59 PM PDT 24
Finished Aug 01 06:22:00 PM PDT 24
Peak memory 219580 kb
Host smart-de057b6a-4adb-487e-8f92-42264203a022
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273138601 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.4273138601
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2985693911
Short name T691
Test name
Test status
Simulation time 24551231 ps
CPU time 0.92 seconds
Started Aug 01 06:22:07 PM PDT 24
Finished Aug 01 06:22:13 PM PDT 24
Peak memory 218184 kb
Host smart-b7566bda-3671-40c6-946a-d9c8b671c0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985693911 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2985693911
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2898755321
Short name T752
Test name
Test status
Simulation time 50843562 ps
CPU time 1.32 seconds
Started Aug 01 06:22:01 PM PDT 24
Finished Aug 01 06:22:02 PM PDT 24
Peak memory 218408 kb
Host smart-97c7fcc9-ff4d-4574-a093-0cfe55ea7484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898755321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2898755321
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.60753375
Short name T79
Test name
Test status
Simulation time 22382172 ps
CPU time 0.94 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:06 PM PDT 24
Peak memory 215832 kb
Host smart-eb10e3d2-83de-42d8-a57f-964417f67093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60753375 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.60753375
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1703616306
Short name T666
Test name
Test status
Simulation time 63097519 ps
CPU time 0.86 seconds
Started Aug 01 06:21:57 PM PDT 24
Finished Aug 01 06:21:58 PM PDT 24
Peak memory 207096 kb
Host smart-ab6aed7c-c0da-4172-b0e5-5fde3e300c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703616306 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1703616306
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.449758779
Short name T350
Test name
Test status
Simulation time 229159287 ps
CPU time 1.67 seconds
Started Aug 01 06:21:58 PM PDT 24
Finished Aug 01 06:22:00 PM PDT 24
Peak memory 215332 kb
Host smart-6b1fd1a3-8837-4770-a092-d17c7ead86a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449758779 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.449758779
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1430494060
Short name T392
Test name
Test status
Simulation time 58489280520 ps
CPU time 1407.45 seconds
Started Aug 01 06:21:58 PM PDT 24
Finished Aug 01 06:45:25 PM PDT 24
Peak memory 223320 kb
Host smart-9d3292ad-11fe-4e49-ae0a-6e14d012128a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430494060 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1430494060
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3053210804
Short name T575
Test name
Test status
Simulation time 142148962 ps
CPU time 1.14 seconds
Started Aug 01 06:22:01 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 218712 kb
Host smart-dabed20e-19d4-4c89-97cc-5c2a62eea149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053210804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3053210804
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3162603316
Short name T730
Test name
Test status
Simulation time 69824931 ps
CPU time 0.84 seconds
Started Aug 01 06:21:51 PM PDT 24
Finished Aug 01 06:21:52 PM PDT 24
Peak memory 206456 kb
Host smart-9a4fb4f9-895c-4538-a1de-7018a5df82e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162603316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3162603316
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.150344792
Short name T777
Test name
Test status
Simulation time 20416707 ps
CPU time 0.84 seconds
Started Aug 01 06:21:55 PM PDT 24
Finished Aug 01 06:21:56 PM PDT 24
Peak memory 216220 kb
Host smart-dbaa7d3b-b225-447f-82ce-f70b968b5fdf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150344792 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.150344792
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3724775778
Short name T696
Test name
Test status
Simulation time 96024016 ps
CPU time 1.15 seconds
Started Aug 01 06:22:00 PM PDT 24
Finished Aug 01 06:22:01 PM PDT 24
Peak memory 216884 kb
Host smart-135554ae-e834-4de4-9e8e-4aadd68ddfb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724775778 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3724775778
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3225679301
Short name T152
Test name
Test status
Simulation time 68393595 ps
CPU time 1.06 seconds
Started Aug 01 06:22:06 PM PDT 24
Finished Aug 01 06:22:08 PM PDT 24
Peak memory 229592 kb
Host smart-c6263e92-8339-4869-8b05-8d3ebfcc8901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225679301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3225679301
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2185056198
Short name T940
Test name
Test status
Simulation time 107515379 ps
CPU time 1.09 seconds
Started Aug 01 06:22:01 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 217220 kb
Host smart-4caae992-80db-4773-bfb2-3ac63d5bf59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185056198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2185056198
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2679621451
Short name T867
Test name
Test status
Simulation time 23594367 ps
CPU time 0.89 seconds
Started Aug 01 06:22:02 PM PDT 24
Finished Aug 01 06:22:03 PM PDT 24
Peak memory 215936 kb
Host smart-fad054f1-52ce-483b-baa8-456d1a8a8168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679621451 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2679621451
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2203566265
Short name T341
Test name
Test status
Simulation time 16947034 ps
CPU time 0.97 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:11 PM PDT 24
Peak memory 215212 kb
Host smart-95db1d4f-b98f-434b-b12c-1c45ac91a3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203566265 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2203566265
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3785983049
Short name T347
Test name
Test status
Simulation time 131577154 ps
CPU time 1.41 seconds
Started Aug 01 06:21:52 PM PDT 24
Finished Aug 01 06:21:54 PM PDT 24
Peak memory 217456 kb
Host smart-d424207d-70ee-480b-8ceb-eb1e97fb6c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785983049 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3785983049
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1129388085
Short name T232
Test name
Test status
Simulation time 114575966500 ps
CPU time 1308.57 seconds
Started Aug 01 06:21:59 PM PDT 24
Finished Aug 01 06:43:48 PM PDT 24
Peak memory 223652 kb
Host smart-369a3552-ab3c-4c72-9f60-796f4a117f84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129388085 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1129388085
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.167218491
Short name T427
Test name
Test status
Simulation time 253851273 ps
CPU time 1.09 seconds
Started Aug 01 06:21:49 PM PDT 24
Finished Aug 01 06:21:50 PM PDT 24
Peak memory 219660 kb
Host smart-e3919010-f71a-4c47-bca9-b7be2d631695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167218491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.167218491
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3338005042
Short name T538
Test name
Test status
Simulation time 18037340 ps
CPU time 1 seconds
Started Aug 01 06:22:00 PM PDT 24
Finished Aug 01 06:22:01 PM PDT 24
Peak memory 215140 kb
Host smart-e1238e98-58ca-4616-ada9-8fb5aa917545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338005042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3338005042
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3675160686
Short name T491
Test name
Test status
Simulation time 21555296 ps
CPU time 0.86 seconds
Started Aug 01 06:21:56 PM PDT 24
Finished Aug 01 06:21:57 PM PDT 24
Peak memory 216440 kb
Host smart-3066baa2-6c1e-4982-80aa-649b07916f4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675160686 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3675160686
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.495278145
Short name T812
Test name
Test status
Simulation time 28771170 ps
CPU time 1.31 seconds
Started Aug 01 06:21:59 PM PDT 24
Finished Aug 01 06:22:00 PM PDT 24
Peak memory 225956 kb
Host smart-04af424b-f8b2-42ad-94c4-9870fdf34c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495278145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.495278145
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1797681120
Short name T547
Test name
Test status
Simulation time 61789606 ps
CPU time 1.07 seconds
Started Aug 01 06:21:57 PM PDT 24
Finished Aug 01 06:21:58 PM PDT 24
Peak memory 217204 kb
Host smart-75e41851-fef0-4fe4-b485-f9798bd88924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797681120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1797681120
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3972306654
Short name T859
Test name
Test status
Simulation time 27037395 ps
CPU time 1.05 seconds
Started Aug 01 06:21:59 PM PDT 24
Finished Aug 01 06:22:00 PM PDT 24
Peak memory 215864 kb
Host smart-0d1bd57a-31f9-4f27-baa7-abbfcefec2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972306654 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3972306654
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.877731409
Short name T816
Test name
Test status
Simulation time 38369805 ps
CPU time 0.94 seconds
Started Aug 01 06:22:03 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 215288 kb
Host smart-a289c350-a733-4bda-a1fa-192643242551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877731409 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.877731409
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.569768247
Short name T761
Test name
Test status
Simulation time 39303013325 ps
CPU time 252.54 seconds
Started Aug 01 06:22:01 PM PDT 24
Finished Aug 01 06:26:14 PM PDT 24
Peak memory 223652 kb
Host smart-e536c449-49ce-4676-af2a-9d8ac9681f58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569768247 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.569768247
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.4044044761
Short name T143
Test name
Test status
Simulation time 28820398 ps
CPU time 1.25 seconds
Started Aug 01 06:21:59 PM PDT 24
Finished Aug 01 06:22:00 PM PDT 24
Peak memory 215744 kb
Host smart-bebfad91-e6c9-4ca1-8b8f-7323103280ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044044761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.4044044761
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2478051413
Short name T765
Test name
Test status
Simulation time 26375340 ps
CPU time 0.86 seconds
Started Aug 01 06:22:02 PM PDT 24
Finished Aug 01 06:22:03 PM PDT 24
Peak memory 214892 kb
Host smart-defd4811-16ca-43c5-93ba-73c307bbd2e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478051413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2478051413
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_err.1418014625
Short name T682
Test name
Test status
Simulation time 18403468 ps
CPU time 1.02 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 218660 kb
Host smart-41e79619-9f3b-4d2e-857b-a82a3c7c073a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418014625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1418014625
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3613409960
Short name T419
Test name
Test status
Simulation time 19875553 ps
CPU time 1.17 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:11 PM PDT 24
Peak memory 217440 kb
Host smart-e6e4be66-fb6f-4cda-9c6f-6cc811fe7677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613409960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3613409960
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1446853602
Short name T443
Test name
Test status
Simulation time 49384796 ps
CPU time 0.97 seconds
Started Aug 01 06:22:00 PM PDT 24
Finished Aug 01 06:22:01 PM PDT 24
Peak memory 215000 kb
Host smart-c47b3571-9605-4861-8db3-fc8c057d467a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446853602 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1446853602
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.794785193
Short name T631
Test name
Test status
Simulation time 44519787 ps
CPU time 0.85 seconds
Started Aug 01 06:21:50 PM PDT 24
Finished Aug 01 06:21:51 PM PDT 24
Peak memory 215476 kb
Host smart-a6a82774-3f01-46d3-8c04-478a4bd1b678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794785193 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.794785193
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.94251690
Short name T578
Test name
Test status
Simulation time 197534079 ps
CPU time 3.99 seconds
Started Aug 01 06:22:02 PM PDT 24
Finished Aug 01 06:22:06 PM PDT 24
Peak memory 217276 kb
Host smart-d66a41c8-da30-4484-b00e-f1755823798a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94251690 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.94251690
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1866978745
Short name T550
Test name
Test status
Simulation time 35529200044 ps
CPU time 807.85 seconds
Started Aug 01 06:22:01 PM PDT 24
Finished Aug 01 06:35:31 PM PDT 24
Peak memory 218288 kb
Host smart-56737617-1798-430e-a749-c35a153afa4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866978745 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1866978745
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2311939526
Short name T828
Test name
Test status
Simulation time 27943633 ps
CPU time 1.26 seconds
Started Aug 01 06:22:11 PM PDT 24
Finished Aug 01 06:22:12 PM PDT 24
Peak memory 220264 kb
Host smart-51324478-081a-4828-a72a-3ba568d86fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311939526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2311939526
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3783691592
Short name T415
Test name
Test status
Simulation time 13187553 ps
CPU time 0.88 seconds
Started Aug 01 06:22:16 PM PDT 24
Finished Aug 01 06:22:17 PM PDT 24
Peak memory 215088 kb
Host smart-2ab9b5c7-17ea-43c7-b252-e6ba011589dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783691592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3783691592
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1867950275
Short name T190
Test name
Test status
Simulation time 85996147 ps
CPU time 0.84 seconds
Started Aug 01 06:22:17 PM PDT 24
Finished Aug 01 06:22:18 PM PDT 24
Peak memory 216308 kb
Host smart-02525a9a-fa22-48c7-8f75-e547787106bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867950275 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1867950275
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2999403713
Short name T701
Test name
Test status
Simulation time 312965942 ps
CPU time 1.09 seconds
Started Aug 01 06:22:03 PM PDT 24
Finished Aug 01 06:22:04 PM PDT 24
Peak memory 216848 kb
Host smart-a45c6042-17af-4978-bdb9-22c0b99b410a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999403713 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2999403713
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2309955770
Short name T817
Test name
Test status
Simulation time 18922158 ps
CPU time 1.2 seconds
Started Aug 01 06:22:06 PM PDT 24
Finished Aug 01 06:22:08 PM PDT 24
Peak memory 224036 kb
Host smart-822889be-f2e4-4a51-bd7f-c54d8cf77d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309955770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2309955770
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_intr.915963312
Short name T46
Test name
Test status
Simulation time 28027936 ps
CPU time 1.11 seconds
Started Aug 01 06:22:02 PM PDT 24
Finished Aug 01 06:22:04 PM PDT 24
Peak memory 223980 kb
Host smart-a1b2bb11-d7ba-4f67-98b8-0591841ece28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915963312 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.915963312
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1529317265
Short name T845
Test name
Test status
Simulation time 15598328 ps
CPU time 0.97 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:11 PM PDT 24
Peak memory 207296 kb
Host smart-89811ae3-3508-4ea2-b007-916d158ac787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529317265 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1529317265
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1756249077
Short name T588
Test name
Test status
Simulation time 36663360 ps
CPU time 1.1 seconds
Started Aug 01 06:22:01 PM PDT 24
Finished Aug 01 06:22:02 PM PDT 24
Peak memory 207300 kb
Host smart-b2751b2f-b555-407c-ab5b-6c1b2e47a383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756249077 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1756249077
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2086385773
Short name T445
Test name
Test status
Simulation time 51058379735 ps
CPU time 1136.89 seconds
Started Aug 01 06:22:08 PM PDT 24
Finished Aug 01 06:41:05 PM PDT 24
Peak memory 219728 kb
Host smart-c4ea505f-4fd8-413a-8550-a1ec01502740
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086385773 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2086385773
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2005080862
Short name T788
Test name
Test status
Simulation time 49840385 ps
CPU time 1.24 seconds
Started Aug 01 06:22:06 PM PDT 24
Finished Aug 01 06:22:07 PM PDT 24
Peak memory 219064 kb
Host smart-39d84272-9160-4fde-beb3-b768d29c6bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005080862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2005080862
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3494200459
Short name T989
Test name
Test status
Simulation time 94283713 ps
CPU time 1.41 seconds
Started Aug 01 06:22:06 PM PDT 24
Finished Aug 01 06:22:08 PM PDT 24
Peak memory 206744 kb
Host smart-061a8972-cb7c-4032-b2e0-3dd5939e8e7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494200459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3494200459
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.82062759
Short name T201
Test name
Test status
Simulation time 32964925 ps
CPU time 0.86 seconds
Started Aug 01 06:22:18 PM PDT 24
Finished Aug 01 06:22:19 PM PDT 24
Peak memory 216212 kb
Host smart-ee33cc78-6fdf-475a-a9f4-45a2327b10eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82062759 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.82062759
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3719240198
Short name T725
Test name
Test status
Simulation time 31911153 ps
CPU time 1.2 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:12 PM PDT 24
Peak memory 216932 kb
Host smart-c392b9fa-460e-4069-8ca4-39b3e0b141c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719240198 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3719240198
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3194124890
Short name T248
Test name
Test status
Simulation time 22931285 ps
CPU time 1.1 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 218524 kb
Host smart-fa4c3e28-1db3-4be1-b2cd-aac9f3d00650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194124890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3194124890
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3632847312
Short name T488
Test name
Test status
Simulation time 40651610 ps
CPU time 1.53 seconds
Started Aug 01 06:22:09 PM PDT 24
Finished Aug 01 06:22:11 PM PDT 24
Peak memory 219768 kb
Host smart-76000ba3-697d-4b4a-ae78-df1edf9e8ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632847312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3632847312
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.492176449
Short name T408
Test name
Test status
Simulation time 25966552 ps
CPU time 1.05 seconds
Started Aug 01 06:21:58 PM PDT 24
Finished Aug 01 06:21:59 PM PDT 24
Peak memory 215360 kb
Host smart-c2e413dd-da0c-4c74-bed3-d78cdc03f730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492176449 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.492176449
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1670681489
Short name T808
Test name
Test status
Simulation time 25417206 ps
CPU time 0.95 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:06 PM PDT 24
Peak memory 215244 kb
Host smart-feb65120-7fa2-4a88-b7ca-9f7c2c889548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670681489 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1670681489
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.621115353
Short name T386
Test name
Test status
Simulation time 241450707 ps
CPU time 1.87 seconds
Started Aug 01 06:22:14 PM PDT 24
Finished Aug 01 06:22:16 PM PDT 24
Peak memory 217112 kb
Host smart-6cad851e-2865-4647-a181-3347b46e8fe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621115353 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.621115353
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1091960190
Short name T677
Test name
Test status
Simulation time 57566496450 ps
CPU time 1326.4 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:44:11 PM PDT 24
Peak memory 221924 kb
Host smart-c461d82e-e378-4542-a73b-3ffa71ee8cda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091960190 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1091960190
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2494928512
Short name T434
Test name
Test status
Simulation time 68462371 ps
CPU time 1.16 seconds
Started Aug 01 06:22:02 PM PDT 24
Finished Aug 01 06:22:03 PM PDT 24
Peak memory 218504 kb
Host smart-eec4813b-3bbd-4fcd-b423-3b3dd86dc399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494928512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2494928512
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1808347509
Short name T52
Test name
Test status
Simulation time 37526466 ps
CPU time 0.92 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 214884 kb
Host smart-34573d77-a766-491f-aaf8-74d336952a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808347509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1808347509
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3042089220
Short name T470
Test name
Test status
Simulation time 62704233 ps
CPU time 0.92 seconds
Started Aug 01 06:21:58 PM PDT 24
Finished Aug 01 06:21:59 PM PDT 24
Peak memory 215868 kb
Host smart-d17c6ffb-4ae8-4ff7-bbc8-05a3f35330ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042089220 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3042089220
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3763229154
Short name T678
Test name
Test status
Simulation time 22512560 ps
CPU time 1.04 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:06 PM PDT 24
Peak memory 219704 kb
Host smart-b7140f6c-202a-447a-8b49-246ba4112260
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763229154 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3763229154
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1579382779
Short name T670
Test name
Test status
Simulation time 73440696 ps
CPU time 1.17 seconds
Started Aug 01 06:22:13 PM PDT 24
Finished Aug 01 06:22:15 PM PDT 24
Peak memory 225836 kb
Host smart-6f7fbadc-4750-4ba2-8c26-5fd47726ca49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579382779 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1579382779
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3504893436
Short name T513
Test name
Test status
Simulation time 36422834 ps
CPU time 1.35 seconds
Started Aug 01 06:22:02 PM PDT 24
Finished Aug 01 06:22:03 PM PDT 24
Peak memory 217576 kb
Host smart-89276293-3f4e-4956-baa2-77261d88a294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504893436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3504893436
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3651254947
Short name T914
Test name
Test status
Simulation time 24095730 ps
CPU time 0.9 seconds
Started Aug 01 06:22:05 PM PDT 24
Finished Aug 01 06:22:06 PM PDT 24
Peak memory 216188 kb
Host smart-c3cfb938-4606-4e69-9225-fd0342aa9089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651254947 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3651254947
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2365342560
Short name T639
Test name
Test status
Simulation time 16126559 ps
CPU time 1.02 seconds
Started Aug 01 06:22:06 PM PDT 24
Finished Aug 01 06:22:07 PM PDT 24
Peak memory 215204 kb
Host smart-5b6e29aa-e9d1-427b-b73e-446a8fae8310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365342560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2365342560
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3560002820
Short name T477
Test name
Test status
Simulation time 20916108 ps
CPU time 1.01 seconds
Started Aug 01 06:21:59 PM PDT 24
Finished Aug 01 06:22:00 PM PDT 24
Peak memory 206500 kb
Host smart-efd896c5-8f45-4904-ab4d-88fa8e82f582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560002820 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3560002820
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3016732317
Short name T223
Test name
Test status
Simulation time 1066230173 ps
CPU time 25.17 seconds
Started Aug 01 06:22:07 PM PDT 24
Finished Aug 01 06:22:33 PM PDT 24
Peak memory 220180 kb
Host smart-aebe7acc-8e47-459e-96ce-7720a330b6bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016732317 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3016732317
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2428345745
Short name T613
Test name
Test status
Simulation time 180533631 ps
CPU time 1.14 seconds
Started Aug 01 06:21:59 PM PDT 24
Finished Aug 01 06:22:00 PM PDT 24
Peak memory 219528 kb
Host smart-93107343-34fc-41dc-a3e4-f3d76008d7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428345745 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2428345745
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3163649859
Short name T970
Test name
Test status
Simulation time 166293419 ps
CPU time 0.87 seconds
Started Aug 01 06:22:08 PM PDT 24
Finished Aug 01 06:22:09 PM PDT 24
Peak memory 206504 kb
Host smart-f8ba5220-c66f-4049-85a2-b858e1b60820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163649859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3163649859
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3000688420
Short name T767
Test name
Test status
Simulation time 11198280 ps
CPU time 0.87 seconds
Started Aug 01 06:22:05 PM PDT 24
Finished Aug 01 06:22:06 PM PDT 24
Peak memory 216224 kb
Host smart-e4e86107-02bd-4b15-963d-0ae23d400770
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000688420 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3000688420
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.3738369205
Short name T555
Test name
Test status
Simulation time 27542186 ps
CPU time 0.97 seconds
Started Aug 01 06:22:02 PM PDT 24
Finished Aug 01 06:22:03 PM PDT 24
Peak memory 219612 kb
Host smart-7f61ece4-a3a3-461a-9058-6632d25454d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738369205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3738369205
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1696528880
Short name T432
Test name
Test status
Simulation time 40083539 ps
CPU time 1.42 seconds
Started Aug 01 06:22:03 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 218536 kb
Host smart-a4b4056e-f691-428f-b2e8-5d7b759e2228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696528880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1696528880
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2032242509
Short name T81
Test name
Test status
Simulation time 41837305 ps
CPU time 0.87 seconds
Started Aug 01 06:22:05 PM PDT 24
Finished Aug 01 06:22:06 PM PDT 24
Peak memory 215680 kb
Host smart-dd70de15-2e56-4fb7-af0c-2bf4f4b19d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032242509 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2032242509
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.897242065
Short name T277
Test name
Test status
Simulation time 18598986 ps
CPU time 0.98 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:11 PM PDT 24
Peak memory 207068 kb
Host smart-b35170d1-517c-4ffc-86ba-61a64312323a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897242065 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.897242065
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1546278613
Short name T885
Test name
Test status
Simulation time 116468590 ps
CPU time 2.56 seconds
Started Aug 01 06:21:56 PM PDT 24
Finished Aug 01 06:21:59 PM PDT 24
Peak memory 215308 kb
Host smart-f8a65a0d-c1f2-41c2-9628-f3c5377fd42d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546278613 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1546278613
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3011796858
Short name T228
Test name
Test status
Simulation time 160297420227 ps
CPU time 887.86 seconds
Started Aug 01 06:22:03 PM PDT 24
Finished Aug 01 06:36:52 PM PDT 24
Peak memory 221884 kb
Host smart-56635526-727c-4045-9f7b-9de8702a2683
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011796858 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3011796858
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert_test.1974374832
Short name T509
Test name
Test status
Simulation time 110345962 ps
CPU time 0.79 seconds
Started Aug 01 06:22:06 PM PDT 24
Finished Aug 01 06:22:07 PM PDT 24
Peak memory 206332 kb
Host smart-cfaa4747-822d-49a5-a366-81501a4571d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974374832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1974374832
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1553912740
Short name T923
Test name
Test status
Simulation time 17151666 ps
CPU time 0.85 seconds
Started Aug 01 06:22:14 PM PDT 24
Finished Aug 01 06:22:15 PM PDT 24
Peak memory 216296 kb
Host smart-904ae21a-b437-46b5-a1b2-5414439ee9b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553912740 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1553912740
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2041064556
Short name T405
Test name
Test status
Simulation time 42003717 ps
CPU time 1.11 seconds
Started Aug 01 06:22:05 PM PDT 24
Finished Aug 01 06:22:07 PM PDT 24
Peak memory 218576 kb
Host smart-edded5b1-7e55-4038-8942-17ed175a25f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041064556 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2041064556
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.373871620
Short name T207
Test name
Test status
Simulation time 27337674 ps
CPU time 0.94 seconds
Started Aug 01 06:22:07 PM PDT 24
Finished Aug 01 06:22:08 PM PDT 24
Peak memory 219524 kb
Host smart-f58f238b-b7de-40b2-b309-b46e68ceb53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373871620 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.373871620
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.424718071
Short name T278
Test name
Test status
Simulation time 44951735 ps
CPU time 1.08 seconds
Started Aug 01 06:22:12 PM PDT 24
Finished Aug 01 06:22:13 PM PDT 24
Peak memory 217212 kb
Host smart-5ef4dd09-b4e8-4219-a32a-d4be24292d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424718071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.424718071
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.4254146981
Short name T973
Test name
Test status
Simulation time 26533650 ps
CPU time 0.9 seconds
Started Aug 01 06:22:07 PM PDT 24
Finished Aug 01 06:22:09 PM PDT 24
Peak memory 215512 kb
Host smart-59be4efa-b5be-41ca-915b-a33981f81b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254146981 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.4254146981
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.4025927234
Short name T444
Test name
Test status
Simulation time 20177100 ps
CPU time 0.98 seconds
Started Aug 01 06:22:02 PM PDT 24
Finished Aug 01 06:22:03 PM PDT 24
Peak memory 215256 kb
Host smart-5599e22d-1f35-4e7c-874b-56868c829606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025927234 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.4025927234
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.799753287
Short name T706
Test name
Test status
Simulation time 2164946227 ps
CPU time 3.25 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:13 PM PDT 24
Peak memory 217308 kb
Host smart-d5d561c2-ca39-4cb6-aa25-c99b2704dabd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799753287 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.799753287
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1648896059
Short name T820
Test name
Test status
Simulation time 249172596796 ps
CPU time 1553.57 seconds
Started Aug 01 06:22:06 PM PDT 24
Finished Aug 01 06:48:00 PM PDT 24
Peak memory 223792 kb
Host smart-870cdf59-fd73-4793-9cc7-32f5a8f7759c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648896059 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1648896059
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.126222449
Short name T180
Test name
Test status
Simulation time 90335643 ps
CPU time 1.27 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:06 PM PDT 24
Peak memory 218540 kb
Host smart-d4ac0db3-33cd-4652-960e-dba5c7707ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126222449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.126222449
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.4171965611
Short name T673
Test name
Test status
Simulation time 18332411 ps
CPU time 0.94 seconds
Started Aug 01 06:22:06 PM PDT 24
Finished Aug 01 06:22:07 PM PDT 24
Peak memory 206724 kb
Host smart-242096a9-3cbe-46e6-b603-c1380cdb3e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171965611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.4171965611
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2027039283
Short name T92
Test name
Test status
Simulation time 10841450 ps
CPU time 0.88 seconds
Started Aug 01 06:22:07 PM PDT 24
Finished Aug 01 06:22:08 PM PDT 24
Peak memory 216184 kb
Host smart-d00c21bc-ca2e-4505-837d-688a0d99c100
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027039283 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2027039283
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2756351878
Short name T155
Test name
Test status
Simulation time 18027865 ps
CPU time 0.95 seconds
Started Aug 01 06:22:13 PM PDT 24
Finished Aug 01 06:22:15 PM PDT 24
Peak memory 216848 kb
Host smart-f6dbe0dd-ea4d-4922-b61b-a0d7764f1d75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756351878 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2756351878
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3789805388
Short name T98
Test name
Test status
Simulation time 23428980 ps
CPU time 0.94 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:05 PM PDT 24
Peak memory 218240 kb
Host smart-77191b26-f8f3-4396-b575-8435d2ffa10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789805388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3789805388
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2445880825
Short name T618
Test name
Test status
Simulation time 237422536 ps
CPU time 1.92 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:06 PM PDT 24
Peak memory 218516 kb
Host smart-32496974-2b2f-4d12-ac3f-6783fa56e46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445880825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2445880825
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3938950071
Short name T557
Test name
Test status
Simulation time 35300592 ps
CPU time 0.89 seconds
Started Aug 01 06:22:15 PM PDT 24
Finished Aug 01 06:22:16 PM PDT 24
Peak memory 215836 kb
Host smart-6a97405e-20c8-40a2-8226-bf49876da6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938950071 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3938950071
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3539721918
Short name T754
Test name
Test status
Simulation time 27582982 ps
CPU time 0.93 seconds
Started Aug 01 06:22:12 PM PDT 24
Finished Aug 01 06:22:13 PM PDT 24
Peak memory 215268 kb
Host smart-9bd5fd7c-b6bb-460d-9ab0-903d6145c40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539721918 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3539721918
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2357451036
Short name T768
Test name
Test status
Simulation time 71161195 ps
CPU time 1.42 seconds
Started Aug 01 06:22:04 PM PDT 24
Finished Aug 01 06:22:06 PM PDT 24
Peak memory 215256 kb
Host smart-bf53fc60-cf9a-4e40-914a-c6ea8cb4f786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357451036 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2357451036
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3495032261
Short name T229
Test name
Test status
Simulation time 297752951669 ps
CPU time 1869.96 seconds
Started Aug 01 06:22:01 PM PDT 24
Finished Aug 01 06:53:14 PM PDT 24
Peak memory 224568 kb
Host smart-cea9899f-22ce-425e-811e-ca25e3b00896
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495032261 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3495032261
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1557551558
Short name T465
Test name
Test status
Simulation time 36034291 ps
CPU time 1.18 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:15 PM PDT 24
Peak memory 218516 kb
Host smart-d0cc6ac0-57cf-4f5b-9342-68f21a3187e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557551558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1557551558
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2618982448
Short name T952
Test name
Test status
Simulation time 123077686 ps
CPU time 1.06 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:15 PM PDT 24
Peak memory 215208 kb
Host smart-e627fca6-e6ae-4706-8d3a-7e8d09e467fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618982448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2618982448
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3321513037
Short name T924
Test name
Test status
Simulation time 39864841 ps
CPU time 0.88 seconds
Started Aug 01 06:21:19 PM PDT 24
Finished Aug 01 06:21:20 PM PDT 24
Peak memory 215384 kb
Host smart-0f64a3f0-9e0a-4dc7-9bc0-aea0728dff1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321513037 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3321513037
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1865550771
Short name T946
Test name
Test status
Simulation time 39740429 ps
CPU time 1.29 seconds
Started Aug 01 06:21:20 PM PDT 24
Finished Aug 01 06:21:21 PM PDT 24
Peak memory 216768 kb
Host smart-98c04442-40b2-4f0a-ae35-0c8bce648d1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865550771 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1865550771
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2278921253
Short name T43
Test name
Test status
Simulation time 23020653 ps
CPU time 1.02 seconds
Started Aug 01 06:21:22 PM PDT 24
Finished Aug 01 06:21:23 PM PDT 24
Peak memory 223944 kb
Host smart-f083d277-604e-486c-9c65-63264f225af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278921253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2278921253
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.884911171
Short name T815
Test name
Test status
Simulation time 661133265 ps
CPU time 4.63 seconds
Started Aug 01 06:21:25 PM PDT 24
Finished Aug 01 06:21:30 PM PDT 24
Peak memory 218820 kb
Host smart-a8f6a672-98b6-4626-bb25-6a043b11bfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884911171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.884911171
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1678204
Short name T42
Test name
Test status
Simulation time 36204026 ps
CPU time 0.96 seconds
Started Aug 01 06:21:14 PM PDT 24
Finished Aug 01 06:21:15 PM PDT 24
Peak memory 223860 kb
Host smart-3f8155be-5b2c-4c29-9ddd-fb1b86c699ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678204 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1678204
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.819052176
Short name T74
Test name
Test status
Simulation time 37811049 ps
CPU time 0.87 seconds
Started Aug 01 06:21:14 PM PDT 24
Finished Aug 01 06:21:15 PM PDT 24
Peak memory 207104 kb
Host smart-c42b797d-5957-4652-8ddf-83b69275bfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819052176 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.819052176
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.3419978131
Short name T452
Test name
Test status
Simulation time 17363112 ps
CPU time 0.96 seconds
Started Aug 01 06:21:17 PM PDT 24
Finished Aug 01 06:21:18 PM PDT 24
Peak memory 207100 kb
Host smart-27f5cca1-c9c3-4188-821f-54f802d91095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419978131 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3419978131
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1687055658
Short name T520
Test name
Test status
Simulation time 360346996 ps
CPU time 6.79 seconds
Started Aug 01 06:21:14 PM PDT 24
Finished Aug 01 06:21:21 PM PDT 24
Peak memory 215284 kb
Host smart-37121d32-c5ba-415a-9c3e-981a51006ec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687055658 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1687055658
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2985573330
Short name T466
Test name
Test status
Simulation time 64002072865 ps
CPU time 1677.73 seconds
Started Aug 01 06:21:19 PM PDT 24
Finished Aug 01 06:49:17 PM PDT 24
Peak memory 225624 kb
Host smart-f2ddf342-3a24-4840-85e1-b9465946cd6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985573330 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2985573330
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.777452480
Short name T894
Test name
Test status
Simulation time 74022205 ps
CPU time 1.13 seconds
Started Aug 01 06:22:24 PM PDT 24
Finished Aug 01 06:22:25 PM PDT 24
Peak memory 218596 kb
Host smart-5fce997e-c9c0-446c-a411-d383b25668f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777452480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.777452480
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2370964015
Short name T799
Test name
Test status
Simulation time 27966805 ps
CPU time 0.85 seconds
Started Aug 01 06:22:07 PM PDT 24
Finished Aug 01 06:22:08 PM PDT 24
Peak memory 206720 kb
Host smart-c75c9053-30d2-4b64-a523-e01a598d1af6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370964015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2370964015
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3786463867
Short name T14
Test name
Test status
Simulation time 108233890 ps
CPU time 1.11 seconds
Started Aug 01 06:22:25 PM PDT 24
Finished Aug 01 06:22:26 PM PDT 24
Peak memory 216800 kb
Host smart-2274bd26-120d-4d73-aac2-79b704ce5f75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786463867 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3786463867
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2538827887
Short name T988
Test name
Test status
Simulation time 22263806 ps
CPU time 0.9 seconds
Started Aug 01 06:22:11 PM PDT 24
Finished Aug 01 06:22:12 PM PDT 24
Peak memory 218632 kb
Host smart-3bd6815f-14e7-45df-9fab-d74a7c5e1cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538827887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2538827887
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.342805929
Short name T790
Test name
Test status
Simulation time 77337431 ps
CPU time 1.17 seconds
Started Aug 01 06:22:09 PM PDT 24
Finished Aug 01 06:22:11 PM PDT 24
Peak memory 217336 kb
Host smart-e9e4a4ac-d0fd-4fc6-9b7d-273dd28e1c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342805929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.342805929
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2443231819
Short name T83
Test name
Test status
Simulation time 24106252 ps
CPU time 1.02 seconds
Started Aug 01 06:22:13 PM PDT 24
Finished Aug 01 06:22:14 PM PDT 24
Peak memory 215724 kb
Host smart-2feebcf2-3b43-4c95-98f6-aefba69d7230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443231819 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2443231819
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3700466296
Short name T339
Test name
Test status
Simulation time 57162291 ps
CPU time 0.91 seconds
Started Aug 01 06:22:14 PM PDT 24
Finished Aug 01 06:22:15 PM PDT 24
Peak memory 215272 kb
Host smart-033a93b1-2f50-4cf2-96e5-8caca79aff6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700466296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3700466296
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1007267481
Short name T53
Test name
Test status
Simulation time 288743554 ps
CPU time 4.13 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:14 PM PDT 24
Peak memory 217348 kb
Host smart-8b992360-9d91-4cec-b0a4-5abffd9e0bda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007267481 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1007267481
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2843887616
Short name T455
Test name
Test status
Simulation time 91733432726 ps
CPU time 2100.92 seconds
Started Aug 01 06:22:16 PM PDT 24
Finished Aug 01 06:57:18 PM PDT 24
Peak memory 226616 kb
Host smart-0d125511-5bb9-4fe4-bef1-ee9fa1ccb6aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843887616 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2843887616
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1840786917
Short name T711
Test name
Test status
Simulation time 24103075 ps
CPU time 1.16 seconds
Started Aug 01 06:22:13 PM PDT 24
Finished Aug 01 06:22:15 PM PDT 24
Peak memory 218760 kb
Host smart-d24ca766-ef5a-437a-a0d2-8e8bdc5dc3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840786917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1840786917
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1784702693
Short name T55
Test name
Test status
Simulation time 18728737 ps
CPU time 0.93 seconds
Started Aug 01 06:22:11 PM PDT 24
Finished Aug 01 06:22:12 PM PDT 24
Peak memory 206672 kb
Host smart-d86e6b66-7282-466e-a3d8-6d19fa7f211a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784702693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1784702693
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2258590241
Short name T516
Test name
Test status
Simulation time 13452489 ps
CPU time 0.92 seconds
Started Aug 01 06:22:22 PM PDT 24
Finished Aug 01 06:22:23 PM PDT 24
Peak memory 216484 kb
Host smart-a9163270-dc1d-4f54-87ac-9cbb6696a018
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258590241 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2258590241
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3028100042
Short name T115
Test name
Test status
Simulation time 41928063 ps
CPU time 1.3 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:11 PM PDT 24
Peak memory 216956 kb
Host smart-0389e99d-fc66-4ee6-a7d0-073bb067dfda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028100042 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3028100042
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2922939702
Short name T185
Test name
Test status
Simulation time 60095740 ps
CPU time 0.85 seconds
Started Aug 01 06:22:22 PM PDT 24
Finished Aug 01 06:22:23 PM PDT 24
Peak memory 218352 kb
Host smart-a8442180-e94e-47f8-8798-ab1fdcbc1372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922939702 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2922939702
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1038222455
Short name T65
Test name
Test status
Simulation time 76119209 ps
CPU time 2.6 seconds
Started Aug 01 06:22:13 PM PDT 24
Finished Aug 01 06:22:16 PM PDT 24
Peak memory 218920 kb
Host smart-6ad5077d-fa73-433c-a872-5e4b7cb1cf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038222455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1038222455
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.776542569
Short name T385
Test name
Test status
Simulation time 21595733 ps
CPU time 1.04 seconds
Started Aug 01 06:22:09 PM PDT 24
Finished Aug 01 06:22:10 PM PDT 24
Peak memory 215360 kb
Host smart-424b95ef-8058-444b-88b6-5ce979bc9a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776542569 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.776542569
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2236255624
Short name T49
Test name
Test status
Simulation time 39827014 ps
CPU time 0.89 seconds
Started Aug 01 06:22:12 PM PDT 24
Finished Aug 01 06:22:13 PM PDT 24
Peak memory 215236 kb
Host smart-3616b697-fb5c-413b-93ce-c3af4556cd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236255624 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2236255624
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2730301571
Short name T662
Test name
Test status
Simulation time 357803124 ps
CPU time 2.4 seconds
Started Aug 01 06:22:19 PM PDT 24
Finished Aug 01 06:22:22 PM PDT 24
Peak memory 215300 kb
Host smart-dab962c2-fe4f-45bb-ab37-3583af35f60a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730301571 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2730301571
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.714864346
Short name T658
Test name
Test status
Simulation time 139393607556 ps
CPU time 438.55 seconds
Started Aug 01 06:22:14 PM PDT 24
Finished Aug 01 06:29:33 PM PDT 24
Peak memory 219180 kb
Host smart-8d479ee2-000c-42ad-9c15-7f1348af9b91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714864346 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.714864346
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3128719412
Short name T174
Test name
Test status
Simulation time 83828873 ps
CPU time 1.17 seconds
Started Aug 01 06:22:23 PM PDT 24
Finished Aug 01 06:22:30 PM PDT 24
Peak memory 218516 kb
Host smart-ab6c5e33-27a0-4792-b1aa-b990fe271a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128719412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3128719412
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1910468681
Short name T579
Test name
Test status
Simulation time 49120778 ps
CPU time 0.94 seconds
Started Aug 01 06:22:11 PM PDT 24
Finished Aug 01 06:22:12 PM PDT 24
Peak memory 206668 kb
Host smart-09804e85-340f-4f81-9ecb-efd59281c4a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910468681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1910468681
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.655871518
Short name T402
Test name
Test status
Simulation time 39944587 ps
CPU time 0.87 seconds
Started Aug 01 06:22:13 PM PDT 24
Finished Aug 01 06:22:14 PM PDT 24
Peak memory 216224 kb
Host smart-bcff4696-bff9-41fe-9705-eb532814dc9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655871518 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.655871518
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2924149368
Short name T655
Test name
Test status
Simulation time 31246997 ps
CPU time 1.17 seconds
Started Aug 01 06:22:09 PM PDT 24
Finished Aug 01 06:22:11 PM PDT 24
Peak memory 216796 kb
Host smart-c092a8fa-c8df-49e1-893c-cc5932a8a44f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924149368 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2924149368
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3860793450
Short name T200
Test name
Test status
Simulation time 19497571 ps
CPU time 1.04 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:11 PM PDT 24
Peak memory 218124 kb
Host smart-fecac755-b956-4f63-acf9-3b725370d885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860793450 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3860793450
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.225629008
Short name T851
Test name
Test status
Simulation time 51262602 ps
CPU time 1.18 seconds
Started Aug 01 06:22:21 PM PDT 24
Finished Aug 01 06:22:22 PM PDT 24
Peak memory 220016 kb
Host smart-60afbce2-5460-489e-85ec-9c8ced30d21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225629008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.225629008
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1774714579
Short name T384
Test name
Test status
Simulation time 24844870 ps
CPU time 0.92 seconds
Started Aug 01 06:22:15 PM PDT 24
Finished Aug 01 06:22:17 PM PDT 24
Peak memory 215288 kb
Host smart-713a9a1b-510c-4752-95d3-3e6ec18108f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774714579 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1774714579
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3651808845
Short name T442
Test name
Test status
Simulation time 40063832 ps
CPU time 0.89 seconds
Started Aug 01 06:22:09 PM PDT 24
Finished Aug 01 06:22:10 PM PDT 24
Peak memory 207048 kb
Host smart-365bd24e-0537-4fd4-805f-0ad9671d3bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651808845 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3651808845
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.4063049972
Short name T238
Test name
Test status
Simulation time 826370638 ps
CPU time 4.56 seconds
Started Aug 01 06:22:07 PM PDT 24
Finished Aug 01 06:22:12 PM PDT 24
Peak memory 217112 kb
Host smart-95f4b167-d959-4d13-9e1b-dba36230aa7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063049972 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.4063049972
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1148094885
Short name T877
Test name
Test status
Simulation time 88007428647 ps
CPU time 817.27 seconds
Started Aug 01 06:22:16 PM PDT 24
Finished Aug 01 06:35:53 PM PDT 24
Peak memory 220820 kb
Host smart-7ca296f4-0475-4ac6-a577-8f25d73aa424
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148094885 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1148094885
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1022525560
Short name T551
Test name
Test status
Simulation time 75202026 ps
CPU time 1.13 seconds
Started Aug 01 06:22:11 PM PDT 24
Finished Aug 01 06:22:12 PM PDT 24
Peak memory 220568 kb
Host smart-12e1309c-91a7-4d21-a238-fc10d3c0bc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022525560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1022525560
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1803426449
Short name T919
Test name
Test status
Simulation time 16069264 ps
CPU time 0.9 seconds
Started Aug 01 06:22:17 PM PDT 24
Finished Aug 01 06:22:18 PM PDT 24
Peak memory 206712 kb
Host smart-298cd3b6-80c3-4542-bf62-038907bc54c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803426449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1803426449
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3043471946
Short name T66
Test name
Test status
Simulation time 34894831 ps
CPU time 0.85 seconds
Started Aug 01 06:22:09 PM PDT 24
Finished Aug 01 06:22:11 PM PDT 24
Peak memory 216164 kb
Host smart-105c5992-a7ac-4d44-b1b8-ab80265f24b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043471946 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3043471946
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1239735991
Short name T758
Test name
Test status
Simulation time 58872408 ps
CPU time 1.24 seconds
Started Aug 01 06:22:15 PM PDT 24
Finished Aug 01 06:22:16 PM PDT 24
Peak memory 216860 kb
Host smart-d2604405-8171-4a4b-939e-902f9c045c89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239735991 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1239735991
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.4250424781
Short name T580
Test name
Test status
Simulation time 21403065 ps
CPU time 0.93 seconds
Started Aug 01 06:22:06 PM PDT 24
Finished Aug 01 06:22:07 PM PDT 24
Peak memory 218488 kb
Host smart-82332326-ea49-4dc7-a833-99086c1cc574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250424781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.4250424781
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2442684233
Short name T825
Test name
Test status
Simulation time 79057022 ps
CPU time 0.99 seconds
Started Aug 01 06:22:12 PM PDT 24
Finished Aug 01 06:22:13 PM PDT 24
Peak memory 217396 kb
Host smart-243404bd-d29a-4df3-a864-fa2f0a52a1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442684233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2442684233
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.4124804392
Short name T544
Test name
Test status
Simulation time 22975020 ps
CPU time 1.22 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:12 PM PDT 24
Peak memory 224116 kb
Host smart-69456102-ef2a-4a0f-a0f2-9ecfde2a9730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124804392 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.4124804392
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.969520346
Short name T917
Test name
Test status
Simulation time 45785303 ps
CPU time 0.98 seconds
Started Aug 01 06:22:08 PM PDT 24
Finished Aug 01 06:22:09 PM PDT 24
Peak memory 215288 kb
Host smart-aea723a5-0478-422b-977b-25114871760f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969520346 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.969520346
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3068419996
Short name T906
Test name
Test status
Simulation time 650971159 ps
CPU time 2.86 seconds
Started Aug 01 06:22:16 PM PDT 24
Finished Aug 01 06:22:19 PM PDT 24
Peak memory 217192 kb
Host smart-23845105-a389-42d2-ab7c-0175fd58140d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068419996 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3068419996
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.876898277
Short name T484
Test name
Test status
Simulation time 175210064829 ps
CPU time 3058.65 seconds
Started Aug 01 06:22:37 PM PDT 24
Finished Aug 01 07:13:36 PM PDT 24
Peak memory 230496 kb
Host smart-cdc98df9-8e64-4ad1-b6de-03e9453d72e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876898277 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.876898277
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2451496403
Short name T881
Test name
Test status
Simulation time 168363163 ps
CPU time 1.09 seconds
Started Aug 01 06:22:32 PM PDT 24
Finished Aug 01 06:22:33 PM PDT 24
Peak memory 218532 kb
Host smart-3c2487f0-f8fe-4726-97ea-3131dc880b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451496403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2451496403
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.534703112
Short name T920
Test name
Test status
Simulation time 36967221 ps
CPU time 0.81 seconds
Started Aug 01 06:22:19 PM PDT 24
Finished Aug 01 06:22:20 PM PDT 24
Peak memory 206440 kb
Host smart-6d97f2c9-a390-4c17-9c0c-bdc9834c53b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534703112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.534703112
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1416065491
Short name T64
Test name
Test status
Simulation time 57450667 ps
CPU time 0.84 seconds
Started Aug 01 06:22:09 PM PDT 24
Finished Aug 01 06:22:10 PM PDT 24
Peak memory 215868 kb
Host smart-4674a9c7-cb50-4720-9155-b349374c227e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416065491 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1416065491
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3269324314
Short name T468
Test name
Test status
Simulation time 126730977 ps
CPU time 1.04 seconds
Started Aug 01 06:22:20 PM PDT 24
Finished Aug 01 06:22:21 PM PDT 24
Peak memory 218272 kb
Host smart-4471472c-d88f-48f7-80ba-e0ed41f5b382
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269324314 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3269324314
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2217184750
Short name T167
Test name
Test status
Simulation time 27521797 ps
CPU time 1.24 seconds
Started Aug 01 06:22:07 PM PDT 24
Finished Aug 01 06:22:08 PM PDT 24
Peak memory 218316 kb
Host smart-5d84b303-0351-4852-b6d5-afcf44b3fd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217184750 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2217184750
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1814818279
Short name T926
Test name
Test status
Simulation time 316062101 ps
CPU time 2.51 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:12 PM PDT 24
Peak memory 218640 kb
Host smart-a407af52-c6a9-44f4-ae69-0459e9a91212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814818279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1814818279
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.952251022
Short name T78
Test name
Test status
Simulation time 24684421 ps
CPU time 0.93 seconds
Started Aug 01 06:22:12 PM PDT 24
Finished Aug 01 06:22:14 PM PDT 24
Peak memory 215776 kb
Host smart-faf36601-90ee-49b3-9a2a-bed84c25e767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952251022 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.952251022
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3271943499
Short name T667
Test name
Test status
Simulation time 18949305 ps
CPU time 1.01 seconds
Started Aug 01 06:22:13 PM PDT 24
Finished Aug 01 06:22:15 PM PDT 24
Peak memory 215284 kb
Host smart-67288cd5-83ac-477f-a568-b1aa17b0050d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271943499 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3271943499
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3837263460
Short name T668
Test name
Test status
Simulation time 96858869 ps
CPU time 1.65 seconds
Started Aug 01 06:22:22 PM PDT 24
Finished Aug 01 06:22:23 PM PDT 24
Peak memory 217160 kb
Host smart-f7179782-0af0-4296-8479-67e5579fa157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837263460 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3837263460
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2605083396
Short name T23
Test name
Test status
Simulation time 155616788551 ps
CPU time 1012.9 seconds
Started Aug 01 06:22:07 PM PDT 24
Finished Aug 01 06:39:00 PM PDT 24
Peak memory 222876 kb
Host smart-8380f6f6-1e00-49fc-8691-827b92f0600f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605083396 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2605083396
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3113170303
Short name T870
Test name
Test status
Simulation time 100865317 ps
CPU time 1.16 seconds
Started Aug 01 06:22:11 PM PDT 24
Finished Aug 01 06:22:12 PM PDT 24
Peak memory 220280 kb
Host smart-a37d52e1-2424-4adf-aef5-45a548917f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113170303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3113170303
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2797371927
Short name T397
Test name
Test status
Simulation time 39499067 ps
CPU time 0.98 seconds
Started Aug 01 06:22:25 PM PDT 24
Finished Aug 01 06:22:26 PM PDT 24
Peak memory 206640 kb
Host smart-e4b703d0-d4d1-4441-8301-794f1c77d2cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797371927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2797371927
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3245085459
Short name T183
Test name
Test status
Simulation time 37547590 ps
CPU time 0.84 seconds
Started Aug 01 06:22:09 PM PDT 24
Finished Aug 01 06:22:10 PM PDT 24
Peak memory 215372 kb
Host smart-24467959-6ebe-43d4-be9a-fae6fbc16894
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245085459 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3245085459
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1080261486
Short name T822
Test name
Test status
Simulation time 134605619 ps
CPU time 1.19 seconds
Started Aug 01 06:22:21 PM PDT 24
Finished Aug 01 06:22:22 PM PDT 24
Peak memory 216796 kb
Host smart-7ff5233a-3481-47ba-901a-842d6b0b0525
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080261486 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1080261486
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2429489718
Short name T569
Test name
Test status
Simulation time 142957218 ps
CPU time 1.19 seconds
Started Aug 01 06:22:14 PM PDT 24
Finished Aug 01 06:22:15 PM PDT 24
Peak memory 219728 kb
Host smart-64ead16b-e5a5-4e56-a7db-3cd438af32d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429489718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2429489718
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.861967827
Short name T770
Test name
Test status
Simulation time 65704458 ps
CPU time 1.02 seconds
Started Aug 01 06:22:17 PM PDT 24
Finished Aug 01 06:22:18 PM PDT 24
Peak memory 217216 kb
Host smart-4d547197-4dfc-4b02-9651-ff0be404d9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861967827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.861967827
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3025019751
Short name T348
Test name
Test status
Simulation time 31130314 ps
CPU time 0.97 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:11 PM PDT 24
Peak memory 215532 kb
Host smart-b2b4c785-44ff-48e0-bdcc-8d62e9883c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025019751 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3025019751
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3244669984
Short name T895
Test name
Test status
Simulation time 39455556 ps
CPU time 0.86 seconds
Started Aug 01 06:22:18 PM PDT 24
Finished Aug 01 06:22:19 PM PDT 24
Peak memory 215240 kb
Host smart-e1f1c294-0368-4248-ab8c-7d59e9996f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244669984 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3244669984
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3827884810
Short name T897
Test name
Test status
Simulation time 36297281 ps
CPU time 1.26 seconds
Started Aug 01 06:22:15 PM PDT 24
Finished Aug 01 06:22:16 PM PDT 24
Peak memory 215280 kb
Host smart-1ef62950-b9d9-4abe-9fea-5c1e233bf1c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827884810 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3827884810
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.989268958
Short name T454
Test name
Test status
Simulation time 140123782960 ps
CPU time 1709.54 seconds
Started Aug 01 06:22:24 PM PDT 24
Finished Aug 01 06:50:54 PM PDT 24
Peak memory 225588 kb
Host smart-08e3321e-9e4f-4747-b448-268c00099e9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989268958 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.989268958
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3256304680
Short name T585
Test name
Test status
Simulation time 28086984 ps
CPU time 1.25 seconds
Started Aug 01 06:22:16 PM PDT 24
Finished Aug 01 06:22:18 PM PDT 24
Peak memory 218452 kb
Host smart-7c25f6ab-81c2-4da6-8c13-fd125630740a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256304680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3256304680
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2071502501
Short name T850
Test name
Test status
Simulation time 36882952 ps
CPU time 0.82 seconds
Started Aug 01 06:22:20 PM PDT 24
Finished Aug 01 06:22:21 PM PDT 24
Peak memory 206460 kb
Host smart-64cebcb8-44c9-4d2e-828e-7230cb736d06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071502501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2071502501
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.269316844
Short name T958
Test name
Test status
Simulation time 10736295 ps
CPU time 0.86 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:11 PM PDT 24
Peak memory 215156 kb
Host smart-1c9b8397-84fa-4499-9a64-7bdee05152bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269316844 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.269316844
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3619746148
Short name T874
Test name
Test status
Simulation time 35858887 ps
CPU time 1.29 seconds
Started Aug 01 06:22:26 PM PDT 24
Finished Aug 01 06:22:28 PM PDT 24
Peak memory 219364 kb
Host smart-de821f8b-1a2b-4775-84a1-3d2772ad2b08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619746148 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3619746148
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3350245683
Short name T162
Test name
Test status
Simulation time 34534156 ps
CPU time 0.92 seconds
Started Aug 01 06:22:07 PM PDT 24
Finished Aug 01 06:22:09 PM PDT 24
Peak memory 219836 kb
Host smart-a44e1ea2-91e4-4fd2-a608-21b77ef551bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350245683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3350245683
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2793640455
Short name T856
Test name
Test status
Simulation time 35450608 ps
CPU time 1.39 seconds
Started Aug 01 06:22:11 PM PDT 24
Finished Aug 01 06:22:13 PM PDT 24
Peak memory 218524 kb
Host smart-e8bf61a8-2ccd-4cf8-af9c-f0bac314e80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793640455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2793640455
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_smoke.1385494384
Short name T542
Test name
Test status
Simulation time 52505496 ps
CPU time 0.98 seconds
Started Aug 01 06:22:15 PM PDT 24
Finished Aug 01 06:22:16 PM PDT 24
Peak memory 215276 kb
Host smart-c6803c5b-c8b6-4fe2-a368-342f1d41ab41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385494384 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1385494384
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1947608509
Short name T27
Test name
Test status
Simulation time 280281769 ps
CPU time 4.92 seconds
Started Aug 01 06:22:10 PM PDT 24
Finished Aug 01 06:22:15 PM PDT 24
Peak memory 217168 kb
Host smart-af1e519a-3654-4b09-a49e-278fa06d175d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947608509 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1947608509
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_alert.3128606921
Short name T149
Test name
Test status
Simulation time 40137676 ps
CPU time 1.13 seconds
Started Aug 01 06:22:13 PM PDT 24
Finished Aug 01 06:22:15 PM PDT 24
Peak memory 218524 kb
Host smart-03563c8c-ef31-4cd7-916b-7157dc37d660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128606921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3128606921
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.4048031468
Short name T356
Test name
Test status
Simulation time 22238596 ps
CPU time 0.82 seconds
Started Aug 01 06:22:11 PM PDT 24
Finished Aug 01 06:22:12 PM PDT 24
Peak memory 206744 kb
Host smart-5c7c9611-5897-45f7-b3ce-16b750869324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048031468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.4048031468
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2493184884
Short name T35
Test name
Test status
Simulation time 23170849 ps
CPU time 0.93 seconds
Started Aug 01 06:22:18 PM PDT 24
Finished Aug 01 06:22:19 PM PDT 24
Peak memory 215548 kb
Host smart-86112052-352c-4673-a237-e6f688920760
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493184884 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2493184884
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.659202372
Short name T114
Test name
Test status
Simulation time 74969847 ps
CPU time 1.06 seconds
Started Aug 01 06:22:18 PM PDT 24
Finished Aug 01 06:22:20 PM PDT 24
Peak memory 216808 kb
Host smart-c1e116a3-26f9-4327-bf90-697197a99980
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659202372 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.659202372
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3369793462
Short name T448
Test name
Test status
Simulation time 35533158 ps
CPU time 1.11 seconds
Started Aug 01 06:22:15 PM PDT 24
Finished Aug 01 06:22:16 PM PDT 24
Peak memory 219620 kb
Host smart-45240d13-9539-4dd7-b25c-c9258d2051dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369793462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3369793462
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1666425562
Short name T637
Test name
Test status
Simulation time 70253401 ps
CPU time 1.1 seconds
Started Aug 01 06:22:27 PM PDT 24
Finished Aug 01 06:22:28 PM PDT 24
Peak memory 219880 kb
Host smart-85891efe-7026-43a8-af35-294978efad2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666425562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1666425562
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.905678118
Short name T77
Test name
Test status
Simulation time 25544301 ps
CPU time 0.97 seconds
Started Aug 01 06:22:19 PM PDT 24
Finished Aug 01 06:22:20 PM PDT 24
Peak memory 215788 kb
Host smart-977de265-3cad-4da0-96e0-082d6e39322f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905678118 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.905678118
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.278605345
Short name T584
Test name
Test status
Simulation time 170886500 ps
CPU time 0.93 seconds
Started Aug 01 06:22:19 PM PDT 24
Finished Aug 01 06:22:20 PM PDT 24
Peak memory 215244 kb
Host smart-e22148dd-4347-4bbf-b0da-9355b2c485f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278605345 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.278605345
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.386359707
Short name T377
Test name
Test status
Simulation time 792568747 ps
CPU time 4.92 seconds
Started Aug 01 06:22:17 PM PDT 24
Finished Aug 01 06:22:22 PM PDT 24
Peak memory 217348 kb
Host smart-00e99f8a-c764-4969-af06-5163296f1795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386359707 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.386359707
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3449071136
Short name T721
Test name
Test status
Simulation time 64627681767 ps
CPU time 1382.16 seconds
Started Aug 01 06:22:18 PM PDT 24
Finished Aug 01 06:45:21 PM PDT 24
Peak memory 221536 kb
Host smart-f9f39dd0-dc99-4c25-a019-7d8bbb973e8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449071136 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3449071136
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3169767294
Short name T953
Test name
Test status
Simulation time 30930329 ps
CPU time 1.22 seconds
Started Aug 01 06:22:18 PM PDT 24
Finished Aug 01 06:22:19 PM PDT 24
Peak memory 218680 kb
Host smart-9426d0af-63bb-4a77-81eb-7627cbb8a2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169767294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3169767294
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.994326391
Short name T933
Test name
Test status
Simulation time 17897770 ps
CPU time 0.92 seconds
Started Aug 01 06:22:23 PM PDT 24
Finished Aug 01 06:22:24 PM PDT 24
Peak memory 206684 kb
Host smart-6380af96-1374-4fc8-940b-0eae7f2b1462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994326391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.994326391
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3036840876
Short name T95
Test name
Test status
Simulation time 30716637 ps
CPU time 0.82 seconds
Started Aug 01 06:22:17 PM PDT 24
Finished Aug 01 06:22:23 PM PDT 24
Peak memory 216212 kb
Host smart-23701375-9ae5-4c95-8516-12a3b0e506a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036840876 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3036840876
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1628528281
Short name T772
Test name
Test status
Simulation time 51040959 ps
CPU time 1.13 seconds
Started Aug 01 06:22:39 PM PDT 24
Finished Aug 01 06:22:40 PM PDT 24
Peak memory 217032 kb
Host smart-fdabd803-d16c-4b6b-bf3e-cbad61a4dad6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628528281 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1628528281
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2005006647
Short name T659
Test name
Test status
Simulation time 30640608 ps
CPU time 1.33 seconds
Started Aug 01 06:22:17 PM PDT 24
Finished Aug 01 06:22:19 PM PDT 24
Peak memory 225612 kb
Host smart-2082943c-a699-494d-a233-5115f21142ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005006647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2005006647
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3512645915
Short name T552
Test name
Test status
Simulation time 103613265 ps
CPU time 1.23 seconds
Started Aug 01 06:22:17 PM PDT 24
Finished Aug 01 06:22:18 PM PDT 24
Peak memory 217448 kb
Host smart-e415e877-493d-4c15-9196-d2eaf08c5dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512645915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3512645915
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2396107091
Short name T87
Test name
Test status
Simulation time 21852879 ps
CPU time 1 seconds
Started Aug 01 06:22:18 PM PDT 24
Finished Aug 01 06:22:19 PM PDT 24
Peak memory 215864 kb
Host smart-0ffa690f-ca50-4a57-bd96-c8cda86ffafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396107091 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2396107091
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.832059585
Short name T778
Test name
Test status
Simulation time 20158799 ps
CPU time 1.07 seconds
Started Aug 01 06:22:17 PM PDT 24
Finished Aug 01 06:22:18 PM PDT 24
Peak memory 215248 kb
Host smart-6fe02db7-e873-426f-aa9f-54e3001956f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832059585 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.832059585
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3144311335
Short name T489
Test name
Test status
Simulation time 107271074 ps
CPU time 1.21 seconds
Started Aug 01 06:22:18 PM PDT 24
Finished Aug 01 06:22:19 PM PDT 24
Peak memory 218392 kb
Host smart-580c6612-8ac3-4a2e-9c05-5703f6274620
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144311335 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3144311335
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2216063991
Short name T784
Test name
Test status
Simulation time 62594997375 ps
CPU time 605.8 seconds
Started Aug 01 06:22:12 PM PDT 24
Finished Aug 01 06:32:18 PM PDT 24
Peak memory 218816 kb
Host smart-71cb94d5-80df-482b-8250-51e0e535fe4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216063991 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2216063991
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1879394534
Short name T990
Test name
Test status
Simulation time 26080272 ps
CPU time 1.28 seconds
Started Aug 01 06:22:31 PM PDT 24
Finished Aug 01 06:22:33 PM PDT 24
Peak memory 219556 kb
Host smart-694655c3-43eb-4148-b4cd-d3cc854ed653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879394534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1879394534
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.700623610
Short name T632
Test name
Test status
Simulation time 17078974 ps
CPU time 0.96 seconds
Started Aug 01 06:22:23 PM PDT 24
Finished Aug 01 06:22:24 PM PDT 24
Peak memory 214772 kb
Host smart-b97cf427-37ba-4ed9-9722-7e33671cb344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700623610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.700623610
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2490654480
Short name T932
Test name
Test status
Simulation time 14757614 ps
CPU time 0.95 seconds
Started Aug 01 06:22:39 PM PDT 24
Finished Aug 01 06:22:40 PM PDT 24
Peak memory 216140 kb
Host smart-51293437-4803-4ba7-87d0-02b05a0533af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490654480 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2490654480
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3939432375
Short name T553
Test name
Test status
Simulation time 47831215 ps
CPU time 1.04 seconds
Started Aug 01 06:22:32 PM PDT 24
Finished Aug 01 06:22:33 PM PDT 24
Peak memory 216908 kb
Host smart-e7140fc6-640d-4785-9f44-0ec051dbd5ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939432375 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3939432375
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1199572803
Short name T482
Test name
Test status
Simulation time 29627227 ps
CPU time 1.33 seconds
Started Aug 01 06:22:28 PM PDT 24
Finished Aug 01 06:22:29 PM PDT 24
Peak memory 225756 kb
Host smart-52dfde70-363f-44ce-a303-fd18cd1430de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199572803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1199572803
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1986165280
Short name T327
Test name
Test status
Simulation time 48712742 ps
CPU time 1.86 seconds
Started Aug 01 06:22:33 PM PDT 24
Finished Aug 01 06:22:35 PM PDT 24
Peak memory 218464 kb
Host smart-e637899f-c8e1-48b0-b352-dcc567bc86a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986165280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1986165280
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.564289708
Short name T782
Test name
Test status
Simulation time 22636286 ps
CPU time 1.07 seconds
Started Aug 01 06:22:37 PM PDT 24
Finished Aug 01 06:22:38 PM PDT 24
Peak memory 215352 kb
Host smart-150c8586-7853-425d-bb13-3e64666f8f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564289708 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.564289708
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1114206960
Short name T591
Test name
Test status
Simulation time 15185706 ps
CPU time 0.99 seconds
Started Aug 01 06:22:41 PM PDT 24
Finished Aug 01 06:22:43 PM PDT 24
Peak memory 215252 kb
Host smart-741b26d7-c00b-4498-ba81-0c5fd2ece5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114206960 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1114206960
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.787368599
Short name T577
Test name
Test status
Simulation time 666132070 ps
CPU time 4.07 seconds
Started Aug 01 06:22:29 PM PDT 24
Finished Aug 01 06:22:33 PM PDT 24
Peak memory 215348 kb
Host smart-c4014406-059a-4303-8847-c5a62a972d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787368599 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.787368599
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3236262095
Short name T956
Test name
Test status
Simulation time 124667706928 ps
CPU time 2592.59 seconds
Started Aug 01 06:22:22 PM PDT 24
Finished Aug 01 07:05:35 PM PDT 24
Peak memory 229420 kb
Host smart-db49e4fd-f9b9-42b9-a0bd-e4438f16ba26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236262095 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3236262095
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2098636840
Short name T909
Test name
Test status
Simulation time 336640565 ps
CPU time 1.42 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:15 PM PDT 24
Peak memory 219708 kb
Host smart-70af34ed-de4f-4b7f-b85d-64c1fb45bf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098636840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2098636840
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3494992309
Short name T732
Test name
Test status
Simulation time 13873951 ps
CPU time 0.84 seconds
Started Aug 01 06:21:22 PM PDT 24
Finished Aug 01 06:21:23 PM PDT 24
Peak memory 206672 kb
Host smart-29d29b1e-e7b6-4a17-8785-214ca51771d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494992309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3494992309
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1116477571
Short name T31
Test name
Test status
Simulation time 22938165 ps
CPU time 0.88 seconds
Started Aug 01 06:21:20 PM PDT 24
Finished Aug 01 06:21:21 PM PDT 24
Peak memory 216316 kb
Host smart-66cc6a64-bd64-4666-a2a3-4ea02f8b9f5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116477571 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1116477571
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3953159537
Short name T773
Test name
Test status
Simulation time 32905792 ps
CPU time 1.22 seconds
Started Aug 01 06:21:16 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 219712 kb
Host smart-6e97a265-4410-40b5-b802-6b0f90839928
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953159537 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3953159537
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_genbits.2793628733
Short name T783
Test name
Test status
Simulation time 29050125 ps
CPU time 1.24 seconds
Started Aug 01 06:21:17 PM PDT 24
Finished Aug 01 06:21:19 PM PDT 24
Peak memory 217336 kb
Host smart-b68aca40-b15b-4ce7-a0d6-0140d61ad910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793628733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2793628733
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_regwen.1084939516
Short name T556
Test name
Test status
Simulation time 44820733 ps
CPU time 0.92 seconds
Started Aug 01 06:21:25 PM PDT 24
Finished Aug 01 06:21:26 PM PDT 24
Peak memory 207060 kb
Host smart-6b74a7ef-35f2-43b4-9090-36f44bdac852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084939516 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1084939516
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3395288708
Short name T694
Test name
Test status
Simulation time 27672428 ps
CPU time 1 seconds
Started Aug 01 06:21:15 PM PDT 24
Finished Aug 01 06:21:16 PM PDT 24
Peak memory 215260 kb
Host smart-82888941-dab3-4dbd-8aa3-a6426cfb1055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395288708 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3395288708
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.207702632
Short name T669
Test name
Test status
Simulation time 265659523 ps
CPU time 4.52 seconds
Started Aug 01 06:21:21 PM PDT 24
Finished Aug 01 06:21:26 PM PDT 24
Peak memory 217352 kb
Host smart-71567ba8-aadb-496b-86b3-e93d29fe3260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207702632 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.207702632
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1872380156
Short name T226
Test name
Test status
Simulation time 363439863570 ps
CPU time 2702.84 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 07:06:16 PM PDT 24
Peak memory 232688 kb
Host smart-0e6e387f-7baf-4b6f-9db1-ad702c9a35e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872380156 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1872380156
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.3118648664
Short name T289
Test name
Test status
Simulation time 40962092 ps
CPU time 1.15 seconds
Started Aug 01 06:22:42 PM PDT 24
Finished Aug 01 06:22:43 PM PDT 24
Peak memory 218768 kb
Host smart-2eefdf07-b517-48d5-8750-3c49735e0be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118648664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.3118648664
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.418179261
Short name T172
Test name
Test status
Simulation time 24669580 ps
CPU time 1.26 seconds
Started Aug 01 06:22:43 PM PDT 24
Finished Aug 01 06:22:44 PM PDT 24
Peak memory 229752 kb
Host smart-652efd85-f171-4748-b399-19ff3ced7bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418179261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.418179261
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3230872214
Short name T561
Test name
Test status
Simulation time 41580483 ps
CPU time 1.57 seconds
Started Aug 01 06:22:37 PM PDT 24
Finished Aug 01 06:22:39 PM PDT 24
Peak memory 219344 kb
Host smart-784cad0f-48b9-4d6c-8b28-6af06cce8e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230872214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3230872214
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.2123285222
Short name T398
Test name
Test status
Simulation time 25668818 ps
CPU time 1.23 seconds
Started Aug 01 06:22:38 PM PDT 24
Finished Aug 01 06:22:39 PM PDT 24
Peak memory 218644 kb
Host smart-0a108848-9d0b-4a49-81b2-b2bf67f2d396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123285222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.2123285222
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.2942242344
Short name T110
Test name
Test status
Simulation time 49566957 ps
CPU time 0.83 seconds
Started Aug 01 06:22:41 PM PDT 24
Finished Aug 01 06:22:42 PM PDT 24
Peak memory 219000 kb
Host smart-e7d0881e-479f-4135-ad1d-7da21ab26777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942242344 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2942242344
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1367618888
Short name T525
Test name
Test status
Simulation time 183639164 ps
CPU time 1.44 seconds
Started Aug 01 06:22:43 PM PDT 24
Finished Aug 01 06:22:44 PM PDT 24
Peak memory 217236 kb
Host smart-97280f0f-cafd-4fc2-9cc6-f1514e1e8735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367618888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1367618888
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.232406753
Short name T918
Test name
Test status
Simulation time 53331302 ps
CPU time 1.23 seconds
Started Aug 01 06:22:26 PM PDT 24
Finished Aug 01 06:22:28 PM PDT 24
Peak memory 218716 kb
Host smart-6790fc74-cf7a-433f-81ca-e2ed80275a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232406753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.232406753
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.4105538478
Short name T175
Test name
Test status
Simulation time 27107064 ps
CPU time 1.2 seconds
Started Aug 01 06:22:29 PM PDT 24
Finished Aug 01 06:22:31 PM PDT 24
Peak memory 217316 kb
Host smart-ed8dda7e-fb32-4a74-9d07-c9f3e7afef1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105538478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.4105538478
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.770122112
Short name T478
Test name
Test status
Simulation time 45642187 ps
CPU time 1.43 seconds
Started Aug 01 06:22:27 PM PDT 24
Finished Aug 01 06:22:28 PM PDT 24
Peak memory 219848 kb
Host smart-c82089d2-bf30-4bb6-add1-db88ef8b0123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770122112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.770122112
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.858648320
Short name T210
Test name
Test status
Simulation time 28817493 ps
CPU time 1.13 seconds
Started Aug 01 06:22:46 PM PDT 24
Finished Aug 01 06:22:47 PM PDT 24
Peak memory 218716 kb
Host smart-856e4a6c-5c31-48fa-bf1d-13cb2a70c5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858648320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.858648320
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.25568608
Short name T6
Test name
Test status
Simulation time 90694943 ps
CPU time 1.16 seconds
Started Aug 01 06:22:45 PM PDT 24
Finished Aug 01 06:22:46 PM PDT 24
Peak memory 219780 kb
Host smart-48d08911-8e81-4f37-8ebd-9110afc90064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25568608 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.25568608
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3242023326
Short name T299
Test name
Test status
Simulation time 102224450 ps
CPU time 1.3 seconds
Started Aug 01 06:22:38 PM PDT 24
Finished Aug 01 06:22:39 PM PDT 24
Peak memory 218584 kb
Host smart-b8e7ae9f-6f8f-470e-9398-6e56730fedab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242023326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3242023326
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3816034136
Short name T244
Test name
Test status
Simulation time 242069841 ps
CPU time 1.37 seconds
Started Aug 01 06:22:23 PM PDT 24
Finished Aug 01 06:22:24 PM PDT 24
Peak memory 219084 kb
Host smart-9bd47c93-acc5-4bd7-a962-7c51a6304f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816034136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3816034136
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.3625683043
Short name T984
Test name
Test status
Simulation time 23014995 ps
CPU time 1.24 seconds
Started Aug 01 06:22:37 PM PDT 24
Finished Aug 01 06:22:38 PM PDT 24
Peak memory 218628 kb
Host smart-89b6a2fd-4f0b-4f53-9a9f-6eb14800cc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625683043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3625683043
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3139595202
Short name T340
Test name
Test status
Simulation time 39236535 ps
CPU time 1.38 seconds
Started Aug 01 06:22:26 PM PDT 24
Finished Aug 01 06:22:28 PM PDT 24
Peak memory 217272 kb
Host smart-4b5709e7-920d-4e86-a8e1-6f9fb1283038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139595202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3139595202
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1520956421
Short name T741
Test name
Test status
Simulation time 25522346 ps
CPU time 1.17 seconds
Started Aug 01 06:22:31 PM PDT 24
Finished Aug 01 06:22:32 PM PDT 24
Peak memory 219624 kb
Host smart-3277755b-dac4-4690-a2d2-c3d05a7d4a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520956421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1520956421
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.3685836361
Short name T160
Test name
Test status
Simulation time 47807768 ps
CPU time 0.98 seconds
Started Aug 01 06:22:23 PM PDT 24
Finished Aug 01 06:22:24 PM PDT 24
Peak memory 219608 kb
Host smart-c01288b8-3050-45c8-b4fb-17e24bec543a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685836361 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3685836361
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.310117630
Short name T310
Test name
Test status
Simulation time 28610276 ps
CPU time 1.45 seconds
Started Aug 01 06:22:43 PM PDT 24
Finished Aug 01 06:22:44 PM PDT 24
Peak memory 217456 kb
Host smart-cdfe1fe9-3a0b-4da4-999a-fdc32d271ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310117630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.310117630
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2146533844
Short name T28
Test name
Test status
Simulation time 97742187 ps
CPU time 1.25 seconds
Started Aug 01 06:22:25 PM PDT 24
Finished Aug 01 06:22:26 PM PDT 24
Peak memory 220228 kb
Host smart-1a7cfad6-7d86-4c84-af0d-24bed6dfd4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146533844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2146533844
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.2990455024
Short name T649
Test name
Test status
Simulation time 21415903 ps
CPU time 1.22 seconds
Started Aug 01 06:22:31 PM PDT 24
Finished Aug 01 06:22:32 PM PDT 24
Peak memory 229604 kb
Host smart-a71c3211-94e8-47d2-bd2c-a03c52b1c737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990455024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2990455024
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2025504772
Short name T757
Test name
Test status
Simulation time 36415205 ps
CPU time 1.42 seconds
Started Aug 01 06:22:23 PM PDT 24
Finished Aug 01 06:22:25 PM PDT 24
Peak memory 217360 kb
Host smart-26b9c028-8387-421e-b123-aa7a8a4b18cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025504772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2025504772
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.2637054813
Short name T435
Test name
Test status
Simulation time 117451628 ps
CPU time 1.24 seconds
Started Aug 01 06:22:23 PM PDT 24
Finished Aug 01 06:22:24 PM PDT 24
Peak memory 220740 kb
Host smart-e531df98-3304-4ad1-b743-3d88995ac4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637054813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2637054813
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.1836546394
Short name T886
Test name
Test status
Simulation time 46755231 ps
CPU time 1.06 seconds
Started Aug 01 06:22:43 PM PDT 24
Finished Aug 01 06:22:45 PM PDT 24
Peak memory 218720 kb
Host smart-85f90f45-91d7-4572-914e-71716e46696d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836546394 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1836546394
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1568442224
Short name T955
Test name
Test status
Simulation time 119311568 ps
CPU time 2.34 seconds
Started Aug 01 06:22:42 PM PDT 24
Finished Aug 01 06:22:45 PM PDT 24
Peak memory 215260 kb
Host smart-27d64234-6152-4068-bb3e-9e747ef51a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568442224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1568442224
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.481145549
Short name T218
Test name
Test status
Simulation time 79267665 ps
CPU time 1.11 seconds
Started Aug 01 06:22:31 PM PDT 24
Finished Aug 01 06:22:32 PM PDT 24
Peak memory 219656 kb
Host smart-df3bee73-9d69-4730-8a0a-fba9ebb36304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481145549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.481145549
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.3067779632
Short name T126
Test name
Test status
Simulation time 20017090 ps
CPU time 0.97 seconds
Started Aug 01 06:22:26 PM PDT 24
Finished Aug 01 06:22:27 PM PDT 24
Peak memory 218604 kb
Host smart-b15f2063-6024-43ca-8e6e-88ff67b9ef95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067779632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3067779632
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1222799801
Short name T586
Test name
Test status
Simulation time 100726694 ps
CPU time 1.91 seconds
Started Aug 01 06:22:26 PM PDT 24
Finished Aug 01 06:22:28 PM PDT 24
Peak memory 220120 kb
Host smart-faa6f6ef-3817-49b3-9e2a-c33ce8bfcdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222799801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1222799801
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.2101897744
Short name T414
Test name
Test status
Simulation time 54160242 ps
CPU time 1.22 seconds
Started Aug 01 06:22:48 PM PDT 24
Finished Aug 01 06:22:49 PM PDT 24
Peak memory 220048 kb
Host smart-5d3419c0-fbbe-4438-a7bf-c9bd5b01b9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101897744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2101897744
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.4115789223
Short name T344
Test name
Test status
Simulation time 23840873 ps
CPU time 1.17 seconds
Started Aug 01 06:22:27 PM PDT 24
Finished Aug 01 06:22:28 PM PDT 24
Peak memory 220536 kb
Host smart-ef430ae6-4218-4099-98e5-96934f566ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115789223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.4115789223
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2111828767
Short name T440
Test name
Test status
Simulation time 33930003 ps
CPU time 1.41 seconds
Started Aug 01 06:22:44 PM PDT 24
Finished Aug 01 06:22:45 PM PDT 24
Peak memory 218356 kb
Host smart-d39212c5-babf-47eb-9d4f-e1ba5644742a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111828767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2111828767
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1859305787
Short name T164
Test name
Test status
Simulation time 28534735 ps
CPU time 1.18 seconds
Started Aug 01 06:21:13 PM PDT 24
Finished Aug 01 06:21:14 PM PDT 24
Peak memory 219508 kb
Host smart-d40ddfdd-f916-4c45-a246-c805c5e0a14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859305787 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1859305787
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1668037531
Short name T409
Test name
Test status
Simulation time 26015655 ps
CPU time 0.87 seconds
Started Aug 01 06:21:28 PM PDT 24
Finished Aug 01 06:21:30 PM PDT 24
Peak memory 206660 kb
Host smart-01360ac2-6732-4e6a-a3f5-b6f2dff904f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668037531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1668037531
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3527652084
Short name T209
Test name
Test status
Simulation time 18295396 ps
CPU time 0.9 seconds
Started Aug 01 06:21:19 PM PDT 24
Finished Aug 01 06:21:20 PM PDT 24
Peak memory 216176 kb
Host smart-b3d37520-e5a5-4be0-9731-1fe6042c464e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527652084 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3527652084
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3774266686
Short name T153
Test name
Test status
Simulation time 36840397 ps
CPU time 1.25 seconds
Started Aug 01 06:21:32 PM PDT 24
Finished Aug 01 06:21:34 PM PDT 24
Peak memory 216864 kb
Host smart-2d6e2ebd-cb1d-433f-8ad6-3683b2f3ffec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774266686 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3774266686
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_genbits.2155498908
Short name T389
Test name
Test status
Simulation time 123212220 ps
CPU time 2.68 seconds
Started Aug 01 06:21:16 PM PDT 24
Finished Aug 01 06:21:19 PM PDT 24
Peak memory 219788 kb
Host smart-27c57ad1-4de5-4ebf-a4be-2e590cab72d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155498908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2155498908
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1616113668
Short name T243
Test name
Test status
Simulation time 38049211 ps
CPU time 0.91 seconds
Started Aug 01 06:21:18 PM PDT 24
Finished Aug 01 06:21:19 PM PDT 24
Peak memory 215268 kb
Host smart-64eb2b5e-c1ea-4881-ace9-35019331c3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616113668 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1616113668
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.763755393
Short name T403
Test name
Test status
Simulation time 15860673 ps
CPU time 1 seconds
Started Aug 01 06:21:16 PM PDT 24
Finished Aug 01 06:21:17 PM PDT 24
Peak memory 207060 kb
Host smart-94240841-d7db-4a6a-868e-4fa3a52ae2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763755393 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.763755393
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.691805420
Short name T587
Test name
Test status
Simulation time 14582379 ps
CPU time 0.97 seconds
Started Aug 01 06:21:23 PM PDT 24
Finished Aug 01 06:21:24 PM PDT 24
Peak memory 215212 kb
Host smart-6ed69aa1-8a30-4af4-824f-482ece72f068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691805420 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.691805420
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.585852472
Short name T793
Test name
Test status
Simulation time 334328294 ps
CPU time 3.56 seconds
Started Aug 01 06:21:22 PM PDT 24
Finished Aug 01 06:21:25 PM PDT 24
Peak memory 217264 kb
Host smart-9e753574-6e37-4574-80e8-c609ad6f7922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585852472 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.585852472
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.432031848
Short name T656
Test name
Test status
Simulation time 108474567254 ps
CPU time 1446.24 seconds
Started Aug 01 06:21:14 PM PDT 24
Finished Aug 01 06:45:21 PM PDT 24
Peak memory 225052 kb
Host smart-6b104874-663e-4d3a-a485-89eddb8057ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432031848 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.432031848
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2414967460
Short name T241
Test name
Test status
Simulation time 29886273 ps
CPU time 1.29 seconds
Started Aug 01 06:22:47 PM PDT 24
Finished Aug 01 06:22:48 PM PDT 24
Peak memory 218576 kb
Host smart-2fec15bd-f130-481d-98c8-da6df832cfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414967460 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2414967460
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3291949933
Short name T199
Test name
Test status
Simulation time 26547209 ps
CPU time 1 seconds
Started Aug 01 06:22:21 PM PDT 24
Finished Aug 01 06:22:22 PM PDT 24
Peak memory 218484 kb
Host smart-a1641eb3-f9b1-43c2-ae11-f38ed63f0c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291949933 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3291949933
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2836747425
Short name T406
Test name
Test status
Simulation time 76715296 ps
CPU time 1.58 seconds
Started Aug 01 06:22:26 PM PDT 24
Finished Aug 01 06:22:28 PM PDT 24
Peak memory 218836 kb
Host smart-fddafd0d-8ab9-42e3-9668-c6227987ca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836747425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2836747425
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1401146086
Short name T134
Test name
Test status
Simulation time 83514573 ps
CPU time 1.25 seconds
Started Aug 01 06:22:29 PM PDT 24
Finished Aug 01 06:22:30 PM PDT 24
Peak memory 218432 kb
Host smart-3a43ea69-b699-4d4b-bfec-d2a48f2ea846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401146086 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1401146086
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1407051621
Short name T651
Test name
Test status
Simulation time 21528763 ps
CPU time 0.91 seconds
Started Aug 01 06:22:44 PM PDT 24
Finished Aug 01 06:22:45 PM PDT 24
Peak memory 215380 kb
Host smart-6cc6e920-b72b-45b4-9bd6-14cdab05e07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407051621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1407051621
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2275664692
Short name T496
Test name
Test status
Simulation time 69085476 ps
CPU time 1.11 seconds
Started Aug 01 06:22:24 PM PDT 24
Finished Aug 01 06:22:25 PM PDT 24
Peak memory 218868 kb
Host smart-c8695fc7-d468-482a-81ee-43a1c25fcf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275664692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2275664692
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.1030418136
Short name T68
Test name
Test status
Simulation time 36193579 ps
CPU time 1.11 seconds
Started Aug 01 06:22:26 PM PDT 24
Finished Aug 01 06:22:27 PM PDT 24
Peak memory 218612 kb
Host smart-a8c4018b-5f0d-46cf-ab62-9ed18a565159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030418136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1030418136
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2256579087
Short name T546
Test name
Test status
Simulation time 65772180 ps
CPU time 0.83 seconds
Started Aug 01 06:22:37 PM PDT 24
Finished Aug 01 06:22:38 PM PDT 24
Peak memory 219260 kb
Host smart-0f9395d6-f97b-4d36-a929-15e8e09e2de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256579087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2256579087
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.163159754
Short name T830
Test name
Test status
Simulation time 116360807 ps
CPU time 1.17 seconds
Started Aug 01 06:22:36 PM PDT 24
Finished Aug 01 06:22:37 PM PDT 24
Peak memory 217268 kb
Host smart-751f010a-4350-4581-ae5f-ca6c9616ac82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163159754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.163159754
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.3489547985
Short name T136
Test name
Test status
Simulation time 39116945 ps
CPU time 1.14 seconds
Started Aug 01 06:22:26 PM PDT 24
Finished Aug 01 06:22:28 PM PDT 24
Peak memory 218436 kb
Host smart-d6b802ba-942b-4cbc-87fb-317eb95a43bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489547985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3489547985
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.4142931095
Short name T129
Test name
Test status
Simulation time 19663019 ps
CPU time 1.16 seconds
Started Aug 01 06:22:28 PM PDT 24
Finished Aug 01 06:22:30 PM PDT 24
Peak memory 223984 kb
Host smart-de0edf37-cd44-4bcd-b2a4-a6f19006c4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142931095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.4142931095
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.361930500
Short name T438
Test name
Test status
Simulation time 35145249 ps
CPU time 1.41 seconds
Started Aug 01 06:22:31 PM PDT 24
Finished Aug 01 06:22:33 PM PDT 24
Peak memory 218656 kb
Host smart-02398027-4f24-42b0-bc10-c23e2eb88631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361930500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.361930500
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.1934631755
Short name T826
Test name
Test status
Simulation time 25285552 ps
CPU time 1.2 seconds
Started Aug 01 06:22:23 PM PDT 24
Finished Aug 01 06:22:25 PM PDT 24
Peak memory 218368 kb
Host smart-93e59b30-0bd2-49b3-b583-9cc8b2370f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934631755 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1934631755
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.2373326162
Short name T469
Test name
Test status
Simulation time 23609177 ps
CPU time 1.11 seconds
Started Aug 01 06:22:41 PM PDT 24
Finished Aug 01 06:22:43 PM PDT 24
Peak memory 215528 kb
Host smart-85419a5a-bf1c-411f-8a06-fe67005645c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373326162 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2373326162
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2093039201
Short name T841
Test name
Test status
Simulation time 32077299 ps
CPU time 1.27 seconds
Started Aug 01 06:22:21 PM PDT 24
Finished Aug 01 06:22:22 PM PDT 24
Peak memory 218424 kb
Host smart-4e710032-dfd1-41cc-9a96-2920b28ba00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093039201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2093039201
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.1966464332
Short name T740
Test name
Test status
Simulation time 58175262 ps
CPU time 1.11 seconds
Started Aug 01 06:22:42 PM PDT 24
Finished Aug 01 06:22:44 PM PDT 24
Peak memory 219624 kb
Host smart-e7e49c85-d469-4c72-9158-26a8106545de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966464332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.1966464332
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.1836247568
Short name T687
Test name
Test status
Simulation time 63798747 ps
CPU time 0.84 seconds
Started Aug 01 06:22:23 PM PDT 24
Finished Aug 01 06:22:24 PM PDT 24
Peak memory 218296 kb
Host smart-cdde126e-762b-4332-9f1a-2b6720400844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836247568 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1836247568
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3510410220
Short name T527
Test name
Test status
Simulation time 86053570 ps
CPU time 1.46 seconds
Started Aug 01 06:22:36 PM PDT 24
Finished Aug 01 06:22:38 PM PDT 24
Peak memory 220192 kb
Host smart-3f11da77-1d7c-419a-a3f3-4b8163ce2dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510410220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3510410220
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.2924907205
Short name T835
Test name
Test status
Simulation time 72685029 ps
CPU time 1.17 seconds
Started Aug 01 06:22:30 PM PDT 24
Finished Aug 01 06:22:32 PM PDT 24
Peak memory 220344 kb
Host smart-1a5820b9-fc5f-46ac-a905-8982078b2870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924907205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.2924907205
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2252537609
Short name T45
Test name
Test status
Simulation time 32570609 ps
CPU time 0.97 seconds
Started Aug 01 06:22:30 PM PDT 24
Finished Aug 01 06:22:31 PM PDT 24
Peak memory 223772 kb
Host smart-0f29ee5b-3423-4229-a108-4e8ba6089b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252537609 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2252537609
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2187889985
Short name T614
Test name
Test status
Simulation time 33336923 ps
CPU time 1.24 seconds
Started Aug 01 06:22:27 PM PDT 24
Finished Aug 01 06:22:29 PM PDT 24
Peak memory 218312 kb
Host smart-fd9626c8-1fb7-4229-a6e2-5fcdb8eb8d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187889985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2187889985
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.3600388379
Short name T156
Test name
Test status
Simulation time 97301939 ps
CPU time 1.28 seconds
Started Aug 01 06:22:30 PM PDT 24
Finished Aug 01 06:22:32 PM PDT 24
Peak memory 215640 kb
Host smart-91910ab2-5f9a-43ed-9253-b9f923273d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600388379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.3600388379
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1145881196
Short name T646
Test name
Test status
Simulation time 24759236 ps
CPU time 1.01 seconds
Started Aug 01 06:22:49 PM PDT 24
Finished Aug 01 06:22:51 PM PDT 24
Peak memory 218716 kb
Host smart-61a9e26b-0ec6-457f-9a81-e36085c978de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145881196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1145881196
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3173428665
Short name T800
Test name
Test status
Simulation time 47534830 ps
CPU time 1.32 seconds
Started Aug 01 06:22:48 PM PDT 24
Finished Aug 01 06:22:50 PM PDT 24
Peak memory 218508 kb
Host smart-84ae2d53-22b9-48e1-a64c-792893da71d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173428665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3173428665
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.311132495
Short name T184
Test name
Test status
Simulation time 36620975 ps
CPU time 1.1 seconds
Started Aug 01 06:22:49 PM PDT 24
Finished Aug 01 06:22:50 PM PDT 24
Peak memory 220028 kb
Host smart-0d0775e4-9670-4103-bdea-64406dd977f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311132495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.311132495
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.3173463727
Short name T103
Test name
Test status
Simulation time 20270894 ps
CPU time 1.09 seconds
Started Aug 01 06:22:27 PM PDT 24
Finished Aug 01 06:22:28 PM PDT 24
Peak memory 219596 kb
Host smart-afd6b6fc-8332-408d-93a5-77e4d79d8ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173463727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3173463727
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2191740362
Short name T964
Test name
Test status
Simulation time 47876627 ps
CPU time 1.24 seconds
Started Aug 01 06:22:27 PM PDT 24
Finished Aug 01 06:22:28 PM PDT 24
Peak memory 218588 kb
Host smart-68a9072f-14c9-434d-80c6-f74a8c23827e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191740362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2191740362
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.1302918550
Short name T948
Test name
Test status
Simulation time 144958160 ps
CPU time 1.17 seconds
Started Aug 01 06:22:28 PM PDT 24
Finished Aug 01 06:22:30 PM PDT 24
Peak memory 220600 kb
Host smart-a99f57fe-bd0e-4ba0-b9c7-aae8e25fe2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302918550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.1302918550
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.355978198
Short name T120
Test name
Test status
Simulation time 69793729 ps
CPU time 1.18 seconds
Started Aug 01 06:22:30 PM PDT 24
Finished Aug 01 06:22:31 PM PDT 24
Peak memory 225504 kb
Host smart-0c86919d-0def-4d2e-9a41-09a923770573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355978198 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.355978198
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2804051328
Short name T787
Test name
Test status
Simulation time 81971300 ps
CPU time 1.7 seconds
Started Aug 01 06:22:36 PM PDT 24
Finished Aug 01 06:22:38 PM PDT 24
Peak memory 218440 kb
Host smart-44165e90-38b7-4027-acc2-3d32967987f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804051328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2804051328
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3778589469
Short name T878
Test name
Test status
Simulation time 62743812 ps
CPU time 1.16 seconds
Started Aug 01 06:21:28 PM PDT 24
Finished Aug 01 06:21:29 PM PDT 24
Peak memory 219212 kb
Host smart-b1934f64-3452-4b42-a955-ce533cce4b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778589469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3778589469
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3495781229
Short name T345
Test name
Test status
Simulation time 19711248 ps
CPU time 0.83 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:28 PM PDT 24
Peak memory 206476 kb
Host smart-389c5d4e-2074-432d-8bc4-c265294a9cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495781229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3495781229
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3113845562
Short name T971
Test name
Test status
Simulation time 16982194 ps
CPU time 0.84 seconds
Started Aug 01 06:21:25 PM PDT 24
Finished Aug 01 06:21:26 PM PDT 24
Peak memory 215376 kb
Host smart-946f1a5d-7919-4d71-afc1-64eb8e8e4e30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113845562 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3113845562
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.32426166
Short name T102
Test name
Test status
Simulation time 32160405 ps
CPU time 1.23 seconds
Started Aug 01 06:21:25 PM PDT 24
Finished Aug 01 06:21:26 PM PDT 24
Peak memory 216752 kb
Host smart-677c9819-7679-4c53-afc5-eb3f513e10a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32426166 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disa
ble_auto_req_mode.32426166
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1289535011
Short name T949
Test name
Test status
Simulation time 25585365 ps
CPU time 0.98 seconds
Started Aug 01 06:21:26 PM PDT 24
Finished Aug 01 06:21:27 PM PDT 24
Peak memory 219768 kb
Host smart-ae47d699-c3e2-4eab-a916-c71138b8c9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289535011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1289535011
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2271742193
Short name T280
Test name
Test status
Simulation time 40940498 ps
CPU time 1.54 seconds
Started Aug 01 06:21:30 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 218328 kb
Host smart-d744d518-ea44-497c-b2c8-74ec37acb91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271742193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2271742193
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.465145211
Short name T625
Test name
Test status
Simulation time 22502954 ps
CPU time 1.09 seconds
Started Aug 01 06:21:29 PM PDT 24
Finished Aug 01 06:21:31 PM PDT 24
Peak memory 215344 kb
Host smart-b56b7f16-44e5-41a5-b045-f2d12cf2532e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465145211 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.465145211
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.723693341
Short name T332
Test name
Test status
Simulation time 45106733 ps
CPU time 0.97 seconds
Started Aug 01 06:21:28 PM PDT 24
Finished Aug 01 06:21:30 PM PDT 24
Peak memory 207072 kb
Host smart-2711fd80-e1c5-4e54-abdf-a7ff56cb9d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723693341 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.723693341
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3935778496
Short name T947
Test name
Test status
Simulation time 20737188 ps
CPU time 0.94 seconds
Started Aug 01 06:21:18 PM PDT 24
Finished Aug 01 06:21:19 PM PDT 24
Peak memory 215272 kb
Host smart-72d6949e-1b11-47a5-9c32-7aaf68fc759c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935778496 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3935778496
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1456179185
Short name T493
Test name
Test status
Simulation time 1073911294 ps
CPU time 2.82 seconds
Started Aug 01 06:21:23 PM PDT 24
Finished Aug 01 06:21:26 PM PDT 24
Peak memory 217268 kb
Host smart-fea27806-aa2c-4473-8ff1-37249e3eed42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456179185 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1456179185
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2322252039
Short name T653
Test name
Test status
Simulation time 105845315137 ps
CPU time 1158.51 seconds
Started Aug 01 06:21:25 PM PDT 24
Finished Aug 01 06:40:44 PM PDT 24
Peak memory 222852 kb
Host smart-95e16687-5bec-4538-973c-c5d4f0288b72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322252039 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2322252039
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.60510691
Short name T285
Test name
Test status
Simulation time 56930492 ps
CPU time 1.29 seconds
Started Aug 01 06:22:31 PM PDT 24
Finished Aug 01 06:22:32 PM PDT 24
Peak memory 219772 kb
Host smart-2129e86d-bd6a-4154-8fa2-9cf1d3fd4efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60510691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.60510691
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.3609498829
Short name T113
Test name
Test status
Simulation time 47414367 ps
CPU time 1.13 seconds
Started Aug 01 06:22:40 PM PDT 24
Finished Aug 01 06:22:41 PM PDT 24
Peak memory 219836 kb
Host smart-c5edc7c9-6f17-4bc4-8d9c-6038c93dd9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609498829 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3609498829
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.4149598741
Short name T633
Test name
Test status
Simulation time 59088713 ps
CPU time 1.03 seconds
Started Aug 01 06:22:45 PM PDT 24
Finished Aug 01 06:22:46 PM PDT 24
Peak memory 220020 kb
Host smart-cd4f4d5e-3b68-406a-8e0f-cf58effc2301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149598741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.4149598741
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.594333463
Short name T34
Test name
Test status
Simulation time 57731785 ps
CPU time 1.16 seconds
Started Aug 01 06:22:51 PM PDT 24
Finished Aug 01 06:22:53 PM PDT 24
Peak memory 215764 kb
Host smart-fc350d7c-adda-4ce9-97a9-a94ad7b17651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594333463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.594333463
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.552723584
Short name T168
Test name
Test status
Simulation time 20822996 ps
CPU time 1.14 seconds
Started Aug 01 06:22:47 PM PDT 24
Finished Aug 01 06:22:48 PM PDT 24
Peak memory 218536 kb
Host smart-21fe2d22-2bd6-4c69-98ae-94604c68be06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552723584 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.552723584
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.4241268625
Short name T727
Test name
Test status
Simulation time 44850771 ps
CPU time 1.64 seconds
Started Aug 01 06:22:46 PM PDT 24
Finished Aug 01 06:22:47 PM PDT 24
Peak memory 218344 kb
Host smart-57d9e4e1-9a17-427c-b9de-0aa887ee3024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241268625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.4241268625
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1071377462
Short name T679
Test name
Test status
Simulation time 27551470 ps
CPU time 1.24 seconds
Started Aug 01 06:22:29 PM PDT 24
Finished Aug 01 06:22:30 PM PDT 24
Peak memory 218456 kb
Host smart-fd5a3616-a18e-4352-9e1d-d9d3de9685b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071377462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1071377462
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.2778887566
Short name T107
Test name
Test status
Simulation time 24790940 ps
CPU time 1 seconds
Started Aug 01 06:22:28 PM PDT 24
Finished Aug 01 06:22:29 PM PDT 24
Peak memory 219624 kb
Host smart-6af80e73-fc57-45c4-81ac-96cd9dadaca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778887566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2778887566
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.538414372
Short name T626
Test name
Test status
Simulation time 48082387 ps
CPU time 1.59 seconds
Started Aug 01 06:22:44 PM PDT 24
Finished Aug 01 06:22:46 PM PDT 24
Peak memory 218428 kb
Host smart-54b9b6bf-8943-477c-8d37-71eebbf3361b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538414372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.538414372
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.4076159033
Short name T559
Test name
Test status
Simulation time 29914784 ps
CPU time 1.25 seconds
Started Aug 01 06:22:47 PM PDT 24
Finished Aug 01 06:22:48 PM PDT 24
Peak memory 218692 kb
Host smart-cf3356a8-a829-4b7b-812b-c39662f13a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076159033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.4076159033
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.26136698
Short name T831
Test name
Test status
Simulation time 19174882 ps
CPU time 1.12 seconds
Started Aug 01 06:22:47 PM PDT 24
Finished Aug 01 06:22:48 PM PDT 24
Peak memory 224148 kb
Host smart-4c574963-35aa-48f7-be46-8f4d659f60cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26136698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.26136698
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1328467032
Short name T382
Test name
Test status
Simulation time 48385590 ps
CPU time 1.58 seconds
Started Aug 01 06:22:47 PM PDT 24
Finished Aug 01 06:22:49 PM PDT 24
Peak memory 220016 kb
Host smart-2c28907a-15b0-4ee2-bd78-04782e2a7179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328467032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1328467032
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.1157805474
Short name T421
Test name
Test status
Simulation time 34247770 ps
CPU time 1.33 seconds
Started Aug 01 06:22:51 PM PDT 24
Finished Aug 01 06:22:52 PM PDT 24
Peak memory 215684 kb
Host smart-0bef0ad8-ba02-4e37-a5e9-d0cf088daa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157805474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.1157805474
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2158112282
Short name T604
Test name
Test status
Simulation time 32641004 ps
CPU time 0.85 seconds
Started Aug 01 06:22:47 PM PDT 24
Finished Aug 01 06:22:48 PM PDT 24
Peak memory 219036 kb
Host smart-debe238a-88b4-4187-9af3-5d50dd449006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158112282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2158112282
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.4243429773
Short name T286
Test name
Test status
Simulation time 59435568 ps
CPU time 1 seconds
Started Aug 01 06:22:27 PM PDT 24
Finished Aug 01 06:22:29 PM PDT 24
Peak memory 217240 kb
Host smart-7d0ea2ec-4e9c-4e63-8558-876163ed6b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243429773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.4243429773
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.2267202892
Short name T860
Test name
Test status
Simulation time 24192713 ps
CPU time 1.24 seconds
Started Aug 01 06:22:51 PM PDT 24
Finished Aug 01 06:22:53 PM PDT 24
Peak memory 219964 kb
Host smart-59973807-c238-4657-b12a-fd6b20874912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267202892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.2267202892
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.2373153641
Short name T125
Test name
Test status
Simulation time 49981986 ps
CPU time 1 seconds
Started Aug 01 06:22:47 PM PDT 24
Finished Aug 01 06:22:48 PM PDT 24
Peak memory 218756 kb
Host smart-913528d5-fc40-4858-af66-dd1d7bab6d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373153641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2373153641
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.139018544
Short name T24
Test name
Test status
Simulation time 74330607 ps
CPU time 1.44 seconds
Started Aug 01 06:22:28 PM PDT 24
Finished Aug 01 06:22:30 PM PDT 24
Peak memory 217296 kb
Host smart-9f0aa214-c325-462d-a10e-d2a0fb32de44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139018544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.139018544
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3928166151
Short name T852
Test name
Test status
Simulation time 191556635 ps
CPU time 1.01 seconds
Started Aug 01 06:22:43 PM PDT 24
Finished Aug 01 06:22:44 PM PDT 24
Peak memory 218732 kb
Host smart-44c82f6b-d941-42fd-889e-e44df8a280b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928166151 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3928166151
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2031440776
Short name T309
Test name
Test status
Simulation time 39029939 ps
CPU time 1.53 seconds
Started Aug 01 06:22:47 PM PDT 24
Finished Aug 01 06:22:49 PM PDT 24
Peak memory 218588 kb
Host smart-901f04af-a79c-49f0-bdb8-9b70fbaafd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031440776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2031440776
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.1694415769
Short name T430
Test name
Test status
Simulation time 47731723 ps
CPU time 1.16 seconds
Started Aug 01 06:22:27 PM PDT 24
Finished Aug 01 06:22:28 PM PDT 24
Peak memory 219832 kb
Host smart-801e019c-9d03-4483-8bb0-de524423d866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694415769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.1694415769
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3482242313
Short name T744
Test name
Test status
Simulation time 23847260 ps
CPU time 1.16 seconds
Started Aug 01 06:22:31 PM PDT 24
Finished Aug 01 06:22:33 PM PDT 24
Peak memory 218672 kb
Host smart-9f1b2c5b-61d4-4d26-8312-13c5f51ca80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482242313 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3482242313
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3412379955
Short name T718
Test name
Test status
Simulation time 49061630 ps
CPU time 1.41 seconds
Started Aug 01 06:22:29 PM PDT 24
Finished Aug 01 06:22:30 PM PDT 24
Peak memory 218408 kb
Host smart-1006b470-0be6-48ae-ade0-eb4479956e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412379955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3412379955
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.1247583190
Short name T161
Test name
Test status
Simulation time 36277666 ps
CPU time 1.05 seconds
Started Aug 01 06:22:43 PM PDT 24
Finished Aug 01 06:22:44 PM PDT 24
Peak memory 219892 kb
Host smart-f325ec88-c2d7-43c8-89f7-38c483498fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247583190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.1247583190
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.4205293460
Short name T927
Test name
Test status
Simulation time 23518908 ps
CPU time 1.05 seconds
Started Aug 01 06:22:31 PM PDT 24
Finished Aug 01 06:22:32 PM PDT 24
Peak memory 223920 kb
Host smart-059d9a2e-ffac-4380-9428-c47302495250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205293460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.4205293460
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3663764633
Short name T583
Test name
Test status
Simulation time 68843584 ps
CPU time 1.15 seconds
Started Aug 01 06:22:39 PM PDT 24
Finished Aug 01 06:22:40 PM PDT 24
Peak memory 217948 kb
Host smart-523b9828-d1aa-4b18-a259-f91f4056102f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663764633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3663764633
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3882684480
Short name T871
Test name
Test status
Simulation time 52965619 ps
CPU time 1.08 seconds
Started Aug 01 06:22:22 PM PDT 24
Finished Aug 01 06:22:23 PM PDT 24
Peak memory 224068 kb
Host smart-70090739-d895-43ed-83e0-d41cbe353a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882684480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3882684480
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2855646134
Short name T888
Test name
Test status
Simulation time 52550481 ps
CPU time 1.3 seconds
Started Aug 01 06:22:32 PM PDT 24
Finished Aug 01 06:22:33 PM PDT 24
Peak memory 215308 kb
Host smart-5ec72b5e-d854-40ab-8fdd-571d0c7f37e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855646134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2855646134
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3356543850
Short name T282
Test name
Test status
Simulation time 389387014 ps
CPU time 1.25 seconds
Started Aug 01 06:21:22 PM PDT 24
Finished Aug 01 06:21:24 PM PDT 24
Peak memory 218628 kb
Host smart-febc9408-9e30-4094-8000-5fe2463e7b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356543850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3356543850
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.569197184
Short name T458
Test name
Test status
Simulation time 23006837 ps
CPU time 0.95 seconds
Started Aug 01 06:21:24 PM PDT 24
Finished Aug 01 06:21:26 PM PDT 24
Peak memory 214828 kb
Host smart-6a1df69a-8a4a-43ea-8ad4-09b421fa8714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569197184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.569197184
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2615473416
Short name T194
Test name
Test status
Simulation time 12286821 ps
CPU time 0.89 seconds
Started Aug 01 06:21:29 PM PDT 24
Finished Aug 01 06:21:30 PM PDT 24
Peak memory 216324 kb
Host smart-77984f99-437f-44bc-b449-3ec847878a48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615473416 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2615473416
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_err.284014725
Short name T425
Test name
Test status
Simulation time 32348094 ps
CPU time 0.9 seconds
Started Aug 01 06:21:22 PM PDT 24
Finished Aug 01 06:21:23 PM PDT 24
Peak memory 218308 kb
Host smart-61f81683-5e8e-44f0-9cba-e06d9ad8edbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284014725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.284014725
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.876273742
Short name T413
Test name
Test status
Simulation time 243027667 ps
CPU time 1.83 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:29 PM PDT 24
Peak memory 218800 kb
Host smart-c9ceb668-81e6-4b8d-a36d-601f3c1ec203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876273742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.876273742
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2444238181
Short name T685
Test name
Test status
Simulation time 22954819 ps
CPU time 0.99 seconds
Started Aug 01 06:21:28 PM PDT 24
Finished Aug 01 06:21:30 PM PDT 24
Peak memory 215872 kb
Host smart-2f1ca75e-74ce-499d-b29d-d8465f3eabbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444238181 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2444238181
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3860577930
Short name T247
Test name
Test status
Simulation time 24714835 ps
CPU time 0.93 seconds
Started Aug 01 06:21:25 PM PDT 24
Finished Aug 01 06:21:26 PM PDT 24
Peak memory 207088 kb
Host smart-9476335f-f48f-477d-912a-65b012ce6fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860577930 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3860577930
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1065083612
Short name T869
Test name
Test status
Simulation time 18911652 ps
CPU time 1.05 seconds
Started Aug 01 06:21:21 PM PDT 24
Finished Aug 01 06:21:22 PM PDT 24
Peak memory 215232 kb
Host smart-3c1b1521-c382-479b-9491-b9df629c5f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065083612 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1065083612
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.368735249
Short name T794
Test name
Test status
Simulation time 301504119 ps
CPU time 5.78 seconds
Started Aug 01 06:21:30 PM PDT 24
Finished Aug 01 06:21:36 PM PDT 24
Peak memory 215256 kb
Host smart-a51e9008-ee6d-4cb1-949c-b7ee030c3e2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368735249 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.368735249
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1243451352
Short name T928
Test name
Test status
Simulation time 34222535082 ps
CPU time 895.84 seconds
Started Aug 01 06:21:20 PM PDT 24
Finished Aug 01 06:36:16 PM PDT 24
Peak memory 219924 kb
Host smart-ee3c15de-f037-4c41-b370-e447797b262f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243451352 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1243451352
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1631659315
Short name T791
Test name
Test status
Simulation time 100932596 ps
CPU time 1.29 seconds
Started Aug 01 06:22:32 PM PDT 24
Finished Aug 01 06:22:34 PM PDT 24
Peak memory 218548 kb
Host smart-ffd83825-3226-4545-a805-622eef1e9718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631659315 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1631659315
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.2652124757
Short name T849
Test name
Test status
Simulation time 21598375 ps
CPU time 1.06 seconds
Started Aug 01 06:22:24 PM PDT 24
Finished Aug 01 06:22:25 PM PDT 24
Peak memory 219628 kb
Host smart-22cd738e-a93d-4872-9bc8-f4b69066816a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652124757 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2652124757
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3559016708
Short name T695
Test name
Test status
Simulation time 39419782 ps
CPU time 1.42 seconds
Started Aug 01 06:22:46 PM PDT 24
Finished Aug 01 06:22:48 PM PDT 24
Peak memory 219856 kb
Host smart-0c8d5e08-ee53-4c87-ac4e-a6208a7c3402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559016708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3559016708
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.230852640
Short name T716
Test name
Test status
Simulation time 39846068 ps
CPU time 1.13 seconds
Started Aug 01 06:22:21 PM PDT 24
Finished Aug 01 06:22:23 PM PDT 24
Peak memory 219980 kb
Host smart-b8823cf6-b066-43cd-9530-5796d9f84116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230852640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.230852640
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2624721415
Short name T574
Test name
Test status
Simulation time 28933280 ps
CPU time 0.83 seconds
Started Aug 01 06:22:23 PM PDT 24
Finished Aug 01 06:22:23 PM PDT 24
Peak memory 218316 kb
Host smart-3d7db9e7-56dc-49d9-ae3d-6ebbe3f0be4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624721415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2624721415
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1183875105
Short name T336
Test name
Test status
Simulation time 35491130 ps
CPU time 1.25 seconds
Started Aug 01 06:22:25 PM PDT 24
Finished Aug 01 06:22:27 PM PDT 24
Peak memory 218564 kb
Host smart-41530032-64da-493d-81ff-58af56a34228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183875105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1183875105
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.877902538
Short name T133
Test name
Test status
Simulation time 46787116 ps
CPU time 1.19 seconds
Started Aug 01 06:22:25 PM PDT 24
Finished Aug 01 06:22:26 PM PDT 24
Peak memory 218856 kb
Host smart-f6b2102e-480b-4fe6-a201-373f1519f611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877902538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.877902538
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.1429488580
Short name T96
Test name
Test status
Simulation time 184981489 ps
CPU time 1.04 seconds
Started Aug 01 06:22:27 PM PDT 24
Finished Aug 01 06:22:28 PM PDT 24
Peak memory 219776 kb
Host smart-33a92aed-cf24-47dc-ae0b-cc81bb264e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429488580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1429488580
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1653879413
Short name T303
Test name
Test status
Simulation time 33185227 ps
CPU time 1.33 seconds
Started Aug 01 06:22:37 PM PDT 24
Finished Aug 01 06:22:38 PM PDT 24
Peak memory 217552 kb
Host smart-4259db54-c09d-4e4f-966c-32642a7b5ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653879413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1653879413
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.320561869
Short name T764
Test name
Test status
Simulation time 72741308 ps
CPU time 1.12 seconds
Started Aug 01 06:22:33 PM PDT 24
Finished Aug 01 06:22:34 PM PDT 24
Peak memory 218736 kb
Host smart-d9e90cf0-2ca4-4c65-a697-1d8d5996f9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320561869 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.320561869
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.2182262054
Short name T648
Test name
Test status
Simulation time 44081995 ps
CPU time 0.93 seconds
Started Aug 01 06:22:29 PM PDT 24
Finished Aug 01 06:22:30 PM PDT 24
Peak memory 218608 kb
Host smart-0187a7ca-8da1-42fb-9442-6a939dbf1687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182262054 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2182262054
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_alert.2122423877
Short name T680
Test name
Test status
Simulation time 29520692 ps
CPU time 1.24 seconds
Started Aug 01 06:22:37 PM PDT 24
Finished Aug 01 06:22:39 PM PDT 24
Peak memory 218616 kb
Host smart-8f6a6858-3d86-4166-a047-b309a2a2b16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122423877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2122423877
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.1962320136
Short name T13
Test name
Test status
Simulation time 19585850 ps
CPU time 1.17 seconds
Started Aug 01 06:22:27 PM PDT 24
Finished Aug 01 06:22:29 PM PDT 24
Peak memory 223936 kb
Host smart-61f758c4-6dcf-4d8c-9bb6-2a5e5f6cf35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962320136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1962320136
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.4198768414
Short name T861
Test name
Test status
Simulation time 43877111 ps
CPU time 1.72 seconds
Started Aug 01 06:22:37 PM PDT 24
Finished Aug 01 06:22:39 PM PDT 24
Peak memory 217356 kb
Host smart-83adc50a-3d94-4ac9-8572-8e3a5fc97acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198768414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.4198768414
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3264197160
Short name T864
Test name
Test status
Simulation time 64601699 ps
CPU time 1.17 seconds
Started Aug 01 06:22:26 PM PDT 24
Finished Aug 01 06:22:27 PM PDT 24
Peak memory 220020 kb
Host smart-8f669165-f804-4aa6-8b6b-b1c7781a14e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264197160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3264197160
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1752612262
Short name T485
Test name
Test status
Simulation time 18763850 ps
CPU time 1.02 seconds
Started Aug 01 06:22:29 PM PDT 24
Finished Aug 01 06:22:35 PM PDT 24
Peak memory 218504 kb
Host smart-88104770-b51c-4b93-97da-aefee51a3616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752612262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1752612262
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1202860380
Short name T10
Test name
Test status
Simulation time 67225636 ps
CPU time 1.25 seconds
Started Aug 01 06:22:47 PM PDT 24
Finished Aug 01 06:22:49 PM PDT 24
Peak memory 220004 kb
Host smart-80c3cce5-c140-4d84-9cae-eb839f0229bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202860380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1202860380
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2194308669
Short name T217
Test name
Test status
Simulation time 132683832 ps
CPU time 1.21 seconds
Started Aug 01 06:22:29 PM PDT 24
Finished Aug 01 06:22:30 PM PDT 24
Peak memory 219448 kb
Host smart-73723644-b2a9-46f8-ae7b-189a2853055a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194308669 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2194308669
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.190219840
Short name T198
Test name
Test status
Simulation time 45587769 ps
CPU time 0.97 seconds
Started Aug 01 06:22:30 PM PDT 24
Finished Aug 01 06:22:32 PM PDT 24
Peak memory 223828 kb
Host smart-422b4974-7605-4336-ac29-012f816b9e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190219840 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.190219840
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3346532477
Short name T314
Test name
Test status
Simulation time 68924301 ps
CPU time 1.11 seconds
Started Aug 01 06:22:34 PM PDT 24
Finished Aug 01 06:22:35 PM PDT 24
Peak memory 217304 kb
Host smart-2a644886-c4eb-49be-95ce-fa95af596fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346532477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3346532477
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.2664219464
Short name T938
Test name
Test status
Simulation time 33650127 ps
CPU time 1.35 seconds
Started Aug 01 06:22:43 PM PDT 24
Finished Aug 01 06:22:45 PM PDT 24
Peak memory 219676 kb
Host smart-56a56c7f-0d82-4f7b-aa4d-93edcef39479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664219464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.2664219464
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.3162051037
Short name T127
Test name
Test status
Simulation time 18829363 ps
CPU time 1.17 seconds
Started Aug 01 06:22:31 PM PDT 24
Finished Aug 01 06:22:32 PM PDT 24
Peak memory 224020 kb
Host smart-1081ed7d-bee1-49a3-93c4-0e0996172e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162051037 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3162051037
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.126016203
Short name T391
Test name
Test status
Simulation time 54187606 ps
CPU time 1.03 seconds
Started Aug 01 06:22:31 PM PDT 24
Finished Aug 01 06:22:32 PM PDT 24
Peak memory 217280 kb
Host smart-e82152f0-4ea5-4733-8212-ced5b8f7efe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126016203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.126016203
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.1551495834
Short name T743
Test name
Test status
Simulation time 29097286 ps
CPU time 1.29 seconds
Started Aug 01 06:22:34 PM PDT 24
Finished Aug 01 06:22:35 PM PDT 24
Peak memory 219652 kb
Host smart-840e8024-deb9-4c7e-ada9-21db240a6213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551495834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1551495834
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2255942220
Short name T775
Test name
Test status
Simulation time 28329968 ps
CPU time 1.14 seconds
Started Aug 01 06:22:56 PM PDT 24
Finished Aug 01 06:22:57 PM PDT 24
Peak memory 219816 kb
Host smart-e9e62e4b-1c34-4eee-9eb9-c50a6fa89ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255942220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2255942220
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1608293855
Short name T975
Test name
Test status
Simulation time 40629596 ps
CPU time 1.52 seconds
Started Aug 01 06:22:31 PM PDT 24
Finished Aug 01 06:22:33 PM PDT 24
Peak memory 218624 kb
Host smart-6b272c56-b76b-459c-aea6-a96eda7f4122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608293855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1608293855
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.4117897107
Short name T411
Test name
Test status
Simulation time 87660970 ps
CPU time 1.15 seconds
Started Aug 01 06:22:48 PM PDT 24
Finished Aug 01 06:22:49 PM PDT 24
Peak memory 219884 kb
Host smart-3483955b-d10e-4dbc-804e-0a92f3110eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117897107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.4117897107
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.124848646
Short name T146
Test name
Test status
Simulation time 33099699 ps
CPU time 1.13 seconds
Started Aug 01 06:22:39 PM PDT 24
Finished Aug 01 06:22:41 PM PDT 24
Peak memory 229616 kb
Host smart-2ebefd7f-a29e-4639-9a53-1aff0c695c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124848646 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.124848646
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3786626287
Short name T487
Test name
Test status
Simulation time 62622791 ps
CPU time 1.69 seconds
Started Aug 01 06:22:32 PM PDT 24
Finished Aug 01 06:22:34 PM PDT 24
Peak memory 218636 kb
Host smart-816b5bf3-ae51-47f9-b975-9bb2bc1b8b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786626287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3786626287
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2328252899
Short name T372
Test name
Test status
Simulation time 29985199 ps
CPU time 1.26 seconds
Started Aug 01 06:21:24 PM PDT 24
Finished Aug 01 06:21:25 PM PDT 24
Peak memory 219508 kb
Host smart-cab887fc-3a6c-4895-a93b-c60264fb5f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328252899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2328252899
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3434345629
Short name T355
Test name
Test status
Simulation time 34724979 ps
CPU time 0.93 seconds
Started Aug 01 06:21:29 PM PDT 24
Finished Aug 01 06:21:31 PM PDT 24
Peak memory 206440 kb
Host smart-b05884ed-6799-472a-995b-06f1e1f7f7a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434345629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3434345629
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.4164053565
Short name T681
Test name
Test status
Simulation time 32180403 ps
CPU time 1.25 seconds
Started Aug 01 06:21:27 PM PDT 24
Finished Aug 01 06:21:29 PM PDT 24
Peak memory 219884 kb
Host smart-427da2e2-47ac-40fb-98a3-cfed886d4fc1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164053565 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.4164053565
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.557936560
Short name T834
Test name
Test status
Simulation time 55987705 ps
CPU time 1.03 seconds
Started Aug 01 06:21:20 PM PDT 24
Finished Aug 01 06:21:22 PM PDT 24
Peak memory 220688 kb
Host smart-ba95e3a9-e521-4396-a766-e314939b6429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557936560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.557936560
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1333155756
Short name T26
Test name
Test status
Simulation time 63319002 ps
CPU time 1.28 seconds
Started Aug 01 06:21:29 PM PDT 24
Finished Aug 01 06:21:30 PM PDT 24
Peak memory 217176 kb
Host smart-d00aae87-a7d9-4f42-9064-478fb87b034b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333155756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1333155756
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.59627336
Short name T57
Test name
Test status
Simulation time 29262909 ps
CPU time 0.92 seconds
Started Aug 01 06:21:21 PM PDT 24
Finished Aug 01 06:21:22 PM PDT 24
Peak memory 215448 kb
Host smart-f51fdae4-eac7-4838-87bf-4308126e2ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59627336 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.59627336
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2812250629
Short name T75
Test name
Test status
Simulation time 47990406 ps
CPU time 0.93 seconds
Started Aug 01 06:21:32 PM PDT 24
Finished Aug 01 06:21:33 PM PDT 24
Peak memory 207080 kb
Host smart-7e4bd408-9521-46a2-a1bc-36ce91d6e9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812250629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2812250629
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3760802325
Short name T729
Test name
Test status
Simulation time 33606200 ps
CPU time 0.9 seconds
Started Aug 01 06:21:31 PM PDT 24
Finished Aug 01 06:21:32 PM PDT 24
Peak memory 215188 kb
Host smart-a5006a2d-0302-400a-9a4a-eb7a5364e9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760802325 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3760802325
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.4233197700
Short name T610
Test name
Test status
Simulation time 81755220 ps
CPU time 2.17 seconds
Started Aug 01 06:21:28 PM PDT 24
Finished Aug 01 06:21:30 PM PDT 24
Peak memory 218432 kb
Host smart-0396f86b-0b74-4a33-a43f-1c3c6edb9e2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233197700 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.4233197700
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2958027255
Short name T390
Test name
Test status
Simulation time 77421405086 ps
CPU time 962 seconds
Started Aug 01 06:21:22 PM PDT 24
Finished Aug 01 06:37:24 PM PDT 24
Peak memory 223136 kb
Host smart-4d768a07-169f-4672-942e-6514a75484c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958027255 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2958027255
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.495915512
Short name T689
Test name
Test status
Simulation time 25584870 ps
CPU time 1.19 seconds
Started Aug 01 06:22:54 PM PDT 24
Finished Aug 01 06:22:56 PM PDT 24
Peak memory 219688 kb
Host smart-79f8cf8c-970c-4f90-a545-8dfc68646162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495915512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.495915512
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.487571449
Short name T606
Test name
Test status
Simulation time 29678724 ps
CPU time 1.24 seconds
Started Aug 01 06:22:40 PM PDT 24
Finished Aug 01 06:22:41 PM PDT 24
Peak memory 215484 kb
Host smart-b4779a3f-752e-4cf2-840b-c21ef2fb8a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487571449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.487571449
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2803482987
Short name T395
Test name
Test status
Simulation time 63661539 ps
CPU time 0.96 seconds
Started Aug 01 06:22:56 PM PDT 24
Finished Aug 01 06:22:57 PM PDT 24
Peak memory 217336 kb
Host smart-da6030b4-51b0-48cd-b1ba-ddc02888fb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803482987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2803482987
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1014958543
Short name T208
Test name
Test status
Simulation time 61455697 ps
CPU time 1.22 seconds
Started Aug 01 06:22:36 PM PDT 24
Finished Aug 01 06:22:37 PM PDT 24
Peak memory 218388 kb
Host smart-61e947a5-20d3-43f2-b6f4-4bb98dca8884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014958543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1014958543
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_genbits.3480859730
Short name T383
Test name
Test status
Simulation time 40472174 ps
CPU time 1.28 seconds
Started Aug 01 06:22:52 PM PDT 24
Finished Aug 01 06:22:53 PM PDT 24
Peak memory 217276 kb
Host smart-8bef00a5-de78-4d3b-9f0b-53dcc630e453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480859730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3480859730
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.775878357
Short name T284
Test name
Test status
Simulation time 78048466 ps
CPU time 1.15 seconds
Started Aug 01 06:22:33 PM PDT 24
Finished Aug 01 06:22:34 PM PDT 24
Peak memory 219316 kb
Host smart-ae2e7e7e-d895-419c-9e5e-6ea979c099b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775878357 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.775878357
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3053179371
Short name T150
Test name
Test status
Simulation time 26119855 ps
CPU time 1.01 seconds
Started Aug 01 06:22:54 PM PDT 24
Finished Aug 01 06:22:55 PM PDT 24
Peak memory 219676 kb
Host smart-954642b9-e7f0-4c60-91d9-4ccf0657dcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053179371 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3053179371
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3271914582
Short name T338
Test name
Test status
Simulation time 2223220726 ps
CPU time 74.02 seconds
Started Aug 01 06:22:33 PM PDT 24
Finished Aug 01 06:23:48 PM PDT 24
Peak memory 217708 kb
Host smart-e31b115c-78e6-48e8-8c12-85bfbff5cdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271914582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3271914582
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.1920699411
Short name T157
Test name
Test status
Simulation time 31882703 ps
CPU time 1.25 seconds
Started Aug 01 06:22:39 PM PDT 24
Finished Aug 01 06:22:40 PM PDT 24
Peak memory 220204 kb
Host smart-b27381f4-f73b-48e3-ab3b-309dc96295b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920699411 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.1920699411
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.4120560692
Short name T776
Test name
Test status
Simulation time 21100158 ps
CPU time 1.09 seconds
Started Aug 01 06:22:32 PM PDT 24
Finished Aug 01 06:22:34 PM PDT 24
Peak memory 224056 kb
Host smart-3e0e0cd5-8c29-416c-8f17-577cff8508b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120560692 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.4120560692
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1749590922
Short name T501
Test name
Test status
Simulation time 117164812 ps
CPU time 1.33 seconds
Started Aug 01 06:22:49 PM PDT 24
Finished Aug 01 06:22:51 PM PDT 24
Peak memory 218516 kb
Host smart-45c2ce23-b120-445c-82fd-e5b101b1d8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749590922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1749590922
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.3248129690
Short name T868
Test name
Test status
Simulation time 49110430 ps
CPU time 1.2 seconds
Started Aug 01 06:22:44 PM PDT 24
Finished Aug 01 06:22:45 PM PDT 24
Peak memory 220208 kb
Host smart-a83bb763-11fe-4342-a51d-11e572fa1015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248129690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.3248129690
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1746729877
Short name T601
Test name
Test status
Simulation time 33006102 ps
CPU time 0.86 seconds
Started Aug 01 06:22:49 PM PDT 24
Finished Aug 01 06:22:50 PM PDT 24
Peak memory 219440 kb
Host smart-09365027-3f9d-4d6c-b940-bf74e7ed10ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746729877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1746729877
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1300717740
Short name T570
Test name
Test status
Simulation time 56805739 ps
CPU time 1.23 seconds
Started Aug 01 06:22:32 PM PDT 24
Finished Aug 01 06:22:34 PM PDT 24
Peak memory 217456 kb
Host smart-d9500e70-9403-4aca-aa45-a5c0176e486f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300717740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1300717740
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3664089867
Short name T836
Test name
Test status
Simulation time 129424729 ps
CPU time 1.27 seconds
Started Aug 01 06:22:39 PM PDT 24
Finished Aug 01 06:22:40 PM PDT 24
Peak memory 218536 kb
Host smart-ae3b7375-10e8-4e83-992f-d0191aeb6cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664089867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3664089867
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1936991725
Short name T159
Test name
Test status
Simulation time 104342595 ps
CPU time 1.02 seconds
Started Aug 01 06:22:32 PM PDT 24
Finished Aug 01 06:22:34 PM PDT 24
Peak memory 220520 kb
Host smart-b3dcf358-9268-494b-91cc-3c9a8bc4b720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936991725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1936991725
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1542306774
Short name T986
Test name
Test status
Simulation time 65289613 ps
CPU time 1.15 seconds
Started Aug 01 06:22:53 PM PDT 24
Finished Aug 01 06:22:54 PM PDT 24
Peak memory 217192 kb
Host smart-27cf29a2-8928-4b05-a08d-95d784e345d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542306774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1542306774
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.4276114250
Short name T855
Test name
Test status
Simulation time 30449139 ps
CPU time 1.28 seconds
Started Aug 01 06:22:53 PM PDT 24
Finished Aug 01 06:22:54 PM PDT 24
Peak memory 214924 kb
Host smart-96275fdc-1d79-49e9-b45e-4361ed20464a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276114250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.4276114250
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3604204554
Short name T119
Test name
Test status
Simulation time 28039838 ps
CPU time 0.88 seconds
Started Aug 01 06:22:48 PM PDT 24
Finished Aug 01 06:22:49 PM PDT 24
Peak memory 218284 kb
Host smart-202062c6-bece-47a2-b225-479936fbd611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604204554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3604204554
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3114794053
Short name T987
Test name
Test status
Simulation time 41391170 ps
CPU time 1.52 seconds
Started Aug 01 06:22:49 PM PDT 24
Finished Aug 01 06:22:51 PM PDT 24
Peak memory 219952 kb
Host smart-5739b40a-edaa-44b7-9900-cb865a2ee3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114794053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3114794053
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.710633909
Short name T792
Test name
Test status
Simulation time 77752705 ps
CPU time 1.12 seconds
Started Aug 01 06:22:56 PM PDT 24
Finished Aug 01 06:22:57 PM PDT 24
Peak memory 218576 kb
Host smart-b11b92ec-8920-4932-be86-5c5806de361d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710633909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.710633909
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.696373383
Short name T106
Test name
Test status
Simulation time 31720240 ps
CPU time 1.23 seconds
Started Aug 01 06:22:39 PM PDT 24
Finished Aug 01 06:22:40 PM PDT 24
Peak memory 219696 kb
Host smart-59abe621-b021-4d28-b144-49a1ecbb4c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696373383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.696373383
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.533506559
Short name T692
Test name
Test status
Simulation time 34523704 ps
CPU time 1.37 seconds
Started Aug 01 06:22:44 PM PDT 24
Finished Aug 01 06:22:46 PM PDT 24
Peak memory 219960 kb
Host smart-49498929-9e42-4348-a071-86dbe31dda60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533506559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.533506559
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.184816751
Short name T842
Test name
Test status
Simulation time 18680802 ps
CPU time 1.2 seconds
Started Aug 01 06:22:49 PM PDT 24
Finished Aug 01 06:22:51 PM PDT 24
Peak memory 224056 kb
Host smart-3ad55aec-65dd-44c0-843b-643ca5257712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184816751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.184816751
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3378162576
Short name T526
Test name
Test status
Simulation time 61509814 ps
CPU time 1.07 seconds
Started Aug 01 06:22:33 PM PDT 24
Finished Aug 01 06:22:34 PM PDT 24
Peak memory 217240 kb
Host smart-d14056dc-5f56-4e38-9298-f8c53783939c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378162576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3378162576
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2165175
Short name T904
Test name
Test status
Simulation time 79358293 ps
CPU time 1.07 seconds
Started Aug 01 06:22:44 PM PDT 24
Finished Aug 01 06:22:45 PM PDT 24
Peak memory 221096 kb
Host smart-b7bf2526-3cc6-4969-b4a5-0709d013f93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2165175
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2433169961
Short name T182
Test name
Test status
Simulation time 21649133 ps
CPU time 0.91 seconds
Started Aug 01 06:22:34 PM PDT 24
Finished Aug 01 06:22:35 PM PDT 24
Peak memory 215356 kb
Host smart-69c9444c-ec9b-4e69-8dfe-5534b304da62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433169961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2433169961
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.4202865785
Short name T857
Test name
Test status
Simulation time 138584386 ps
CPU time 1.21 seconds
Started Aug 01 06:22:34 PM PDT 24
Finished Aug 01 06:22:35 PM PDT 24
Peak memory 220068 kb
Host smart-37c7d3a2-a296-4234-b060-34c076c48f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202865785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.4202865785
Directory /workspace/99.edn_genbits/latest
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