Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr
Bins
| | | | | | | | | | | | |
all_values[0] |
119281 |
1 |
|
|
T1 |
8 |
|
T7 |
22 |
|
T19 |
51 |
all_values[1] |
119281 |
1 |
|
|
T1 |
8 |
|
T7 |
22 |
|
T19 |
51 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
| | | | | | | | | | | | |
auto[0] |
174175 |
1 |
|
|
T1 |
16 |
|
T7 |
44 |
|
T19 |
102 |
auto[1] |
64387 |
1 |
|
|
T20 |
524 |
|
T21 |
798 |
|
T36 |
69 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
| | | | | | | | | | | | |
auto[0] |
208680 |
1 |
|
|
T1 |
14 |
|
T7 |
38 |
|
T19 |
96 |
auto[1] |
29882 |
1 |
|
|
T1 |
2 |
|
T7 |
6 |
|
T19 |
6 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
| | | | | | | | | | | | | | |
all_values[0] |
auto[0] |
auto[0] |
71882 |
1 |
|
|
T1 |
6 |
|
T7 |
16 |
|
T19 |
45 |
all_values[0] |
auto[0] |
auto[1] |
18554 |
1 |
|
|
T1 |
2 |
|
T7 |
6 |
|
T19 |
6 |
all_values[0] |
auto[1] |
auto[0] |
21221 |
1 |
|
|
T20 |
99 |
|
T21 |
257 |
|
T36 |
5 |
all_values[0] |
auto[1] |
auto[1] |
7624 |
1 |
|
|
T20 |
70 |
|
T21 |
169 |
|
T36 |
8 |
all_values[1] |
auto[0] |
auto[0] |
81830 |
1 |
|
|
T1 |
8 |
|
T7 |
22 |
|
T19 |
51 |
all_values[1] |
auto[0] |
auto[1] |
1909 |
1 |
|
|
T20 |
21 |
|
T21 |
24 |
|
T36 |
3 |
all_values[1] |
auto[1] |
auto[0] |
33747 |
1 |
|
|
T20 |
332 |
|
T21 |
353 |
|
T36 |
48 |
all_values[1] |
auto[1] |
auto[1] |
1795 |
1 |
|
|
T20 |
23 |
|
T21 |
19 |
|
T36 |
8 |