Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.51 98.25 93.25 91.05 87.79 95.50 96.83 91.89


Total test records in report: 1124
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T1021 /workspace/coverage/cover_reg_top/46.edn_intr_test.1467447965 Aug 02 06:15:00 PM PDT 24 Aug 02 06:15:01 PM PDT 24 15551119 ps
T1022 /workspace/coverage/cover_reg_top/14.edn_tl_errors.4206176009 Aug 02 06:14:20 PM PDT 24 Aug 02 06:14:22 PM PDT 24 262777724 ps
T268 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1481218620 Aug 02 06:13:36 PM PDT 24 Aug 02 06:13:37 PM PDT 24 76445886 ps
T1023 /workspace/coverage/cover_reg_top/45.edn_intr_test.1847800589 Aug 02 06:15:08 PM PDT 24 Aug 02 06:15:09 PM PDT 24 39913776 ps
T1024 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4023342447 Aug 02 06:12:55 PM PDT 24 Aug 02 06:12:56 PM PDT 24 22212965 ps
T1025 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1804755120 Aug 02 06:13:54 PM PDT 24 Aug 02 06:13:55 PM PDT 24 24003248 ps
T269 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1647421825 Aug 02 06:14:28 PM PDT 24 Aug 02 06:14:29 PM PDT 24 54043810 ps
T270 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1248752886 Aug 02 06:13:54 PM PDT 24 Aug 02 06:13:55 PM PDT 24 70828742 ps
T271 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.4073035581 Aug 02 06:14:38 PM PDT 24 Aug 02 06:14:40 PM PDT 24 73293986 ps
T1026 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1900020343 Aug 02 06:14:28 PM PDT 24 Aug 02 06:14:33 PM PDT 24 401605401 ps
T1027 /workspace/coverage/cover_reg_top/19.edn_intr_test.1265829026 Aug 02 06:14:40 PM PDT 24 Aug 02 06:14:41 PM PDT 24 44283029 ps
T1028 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1069287938 Aug 02 06:13:27 PM PDT 24 Aug 02 06:13:29 PM PDT 24 69211965 ps
T1029 /workspace/coverage/cover_reg_top/42.edn_intr_test.387388978 Aug 02 06:14:59 PM PDT 24 Aug 02 06:15:00 PM PDT 24 44176194 ps
T1030 /workspace/coverage/cover_reg_top/18.edn_intr_test.1119906687 Aug 02 06:14:42 PM PDT 24 Aug 02 06:14:43 PM PDT 24 37805069 ps
T294 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.473594756 Aug 02 06:14:21 PM PDT 24 Aug 02 06:14:23 PM PDT 24 234833025 ps
T1031 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3833536859 Aug 02 06:13:35 PM PDT 24 Aug 02 06:13:37 PM PDT 24 32167543 ps
T272 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3484806347 Aug 02 06:13:28 PM PDT 24 Aug 02 06:13:30 PM PDT 24 177523214 ps
T1032 /workspace/coverage/cover_reg_top/19.edn_csr_rw.246058005 Aug 02 06:14:39 PM PDT 24 Aug 02 06:14:40 PM PDT 24 21994524 ps
T296 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1495452940 Aug 02 06:12:47 PM PDT 24 Aug 02 06:12:49 PM PDT 24 334533301 ps
T297 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1742951358 Aug 02 06:14:38 PM PDT 24 Aug 02 06:14:40 PM PDT 24 76179101 ps
T1033 /workspace/coverage/cover_reg_top/9.edn_intr_test.2390690810 Aug 02 06:13:55 PM PDT 24 Aug 02 06:13:56 PM PDT 24 12568762 ps
T273 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4260763045 Aug 02 06:14:38 PM PDT 24 Aug 02 06:14:39 PM PDT 24 19290129 ps
T261 /workspace/coverage/cover_reg_top/11.edn_csr_rw.397168795 Aug 02 06:14:10 PM PDT 24 Aug 02 06:14:11 PM PDT 24 25159553 ps
T1034 /workspace/coverage/cover_reg_top/35.edn_intr_test.811380840 Aug 02 06:14:48 PM PDT 24 Aug 02 06:14:49 PM PDT 24 19664169 ps
T1035 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2367704823 Aug 02 06:14:38 PM PDT 24 Aug 02 06:14:39 PM PDT 24 66958771 ps
T1036 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1670816249 Aug 02 06:13:28 PM PDT 24 Aug 02 06:13:31 PM PDT 24 170081066 ps
T1037 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3482614910 Aug 02 06:13:54 PM PDT 24 Aug 02 06:13:55 PM PDT 24 19837999 ps
T1038 /workspace/coverage/cover_reg_top/25.edn_intr_test.1434799387 Aug 02 06:14:47 PM PDT 24 Aug 02 06:14:48 PM PDT 24 36133924 ps
T274 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2925702932 Aug 02 06:14:09 PM PDT 24 Aug 02 06:14:10 PM PDT 24 78990189 ps
T1039 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2384326731 Aug 02 06:13:38 PM PDT 24 Aug 02 06:13:40 PM PDT 24 80530630 ps
T1040 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.772377996 Aug 02 06:14:19 PM PDT 24 Aug 02 06:14:20 PM PDT 24 128776593 ps
T1041 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2818149618 Aug 02 06:13:55 PM PDT 24 Aug 02 06:13:57 PM PDT 24 83380369 ps
T1042 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1944472878 Aug 02 06:13:40 PM PDT 24 Aug 02 06:13:41 PM PDT 24 26259098 ps
T1043 /workspace/coverage/cover_reg_top/19.edn_tl_errors.955858255 Aug 02 06:14:39 PM PDT 24 Aug 02 06:14:41 PM PDT 24 63606418 ps
T1044 /workspace/coverage/cover_reg_top/0.edn_intr_test.885402969 Aug 02 06:12:30 PM PDT 24 Aug 02 06:12:30 PM PDT 24 11404454 ps
T1045 /workspace/coverage/cover_reg_top/2.edn_intr_test.506818620 Aug 02 06:13:02 PM PDT 24 Aug 02 06:13:03 PM PDT 24 20877270 ps
T1046 /workspace/coverage/cover_reg_top/4.edn_csr_rw.490219150 Aug 02 06:13:29 PM PDT 24 Aug 02 06:13:30 PM PDT 24 44391475 ps
T1047 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1398219103 Aug 02 06:13:54 PM PDT 24 Aug 02 06:13:55 PM PDT 24 21877105 ps
T1048 /workspace/coverage/cover_reg_top/39.edn_intr_test.849307871 Aug 02 06:15:00 PM PDT 24 Aug 02 06:15:01 PM PDT 24 12144095 ps
T1049 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1617079496 Aug 02 06:14:30 PM PDT 24 Aug 02 06:14:31 PM PDT 24 56795060 ps
T1050 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.443008743 Aug 02 06:12:48 PM PDT 24 Aug 02 06:12:49 PM PDT 24 51384438 ps
T1051 /workspace/coverage/cover_reg_top/36.edn_intr_test.3325301583 Aug 02 06:15:05 PM PDT 24 Aug 02 06:15:06 PM PDT 24 15279845 ps
T1052 /workspace/coverage/cover_reg_top/14.edn_intr_test.600477856 Aug 02 06:14:19 PM PDT 24 Aug 02 06:14:20 PM PDT 24 23070745 ps
T1053 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2202113162 Aug 02 06:13:56 PM PDT 24 Aug 02 06:13:57 PM PDT 24 27035515 ps
T1054 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3005314354 Aug 02 06:13:21 PM PDT 24 Aug 02 06:13:23 PM PDT 24 22248969 ps
T1055 /workspace/coverage/cover_reg_top/27.edn_intr_test.3007237748 Aug 02 06:14:49 PM PDT 24 Aug 02 06:14:50 PM PDT 24 13279752 ps
T1056 /workspace/coverage/cover_reg_top/7.edn_intr_test.2277241182 Aug 02 06:13:46 PM PDT 24 Aug 02 06:13:47 PM PDT 24 32084012 ps
T1057 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2610958623 Aug 02 06:14:09 PM PDT 24 Aug 02 06:14:11 PM PDT 24 43835904 ps
T1058 /workspace/coverage/cover_reg_top/23.edn_intr_test.801235759 Aug 02 06:14:47 PM PDT 24 Aug 02 06:14:48 PM PDT 24 12140133 ps
T1059 /workspace/coverage/cover_reg_top/3.edn_intr_test.2035665975 Aug 02 06:13:12 PM PDT 24 Aug 02 06:13:13 PM PDT 24 15357281 ps
T1060 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1009821501 Aug 02 06:12:54 PM PDT 24 Aug 02 06:12:55 PM PDT 24 33554585 ps
T1061 /workspace/coverage/cover_reg_top/11.edn_intr_test.3904983875 Aug 02 06:14:08 PM PDT 24 Aug 02 06:14:08 PM PDT 24 18872906 ps
T1062 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3243625018 Aug 02 06:13:52 PM PDT 24 Aug 02 06:13:54 PM PDT 24 155607779 ps
T1063 /workspace/coverage/cover_reg_top/30.edn_intr_test.3699376049 Aug 02 06:14:47 PM PDT 24 Aug 02 06:14:48 PM PDT 24 16318244 ps
T1064 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1927867618 Aug 02 06:14:10 PM PDT 24 Aug 02 06:14:11 PM PDT 24 23335309 ps
T1065 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3495578544 Aug 02 06:14:39 PM PDT 24 Aug 02 06:14:41 PM PDT 24 120084515 ps
T1066 /workspace/coverage/cover_reg_top/24.edn_intr_test.177861140 Aug 02 06:14:47 PM PDT 24 Aug 02 06:14:48 PM PDT 24 13045911 ps
T1067 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3179216496 Aug 02 06:13:12 PM PDT 24 Aug 02 06:13:15 PM PDT 24 146893774 ps
T1068 /workspace/coverage/cover_reg_top/32.edn_intr_test.1852191651 Aug 02 06:14:50 PM PDT 24 Aug 02 06:14:51 PM PDT 24 111826522 ps
T1069 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1775032035 Aug 02 06:12:48 PM PDT 24 Aug 02 06:12:50 PM PDT 24 71257132 ps
T1070 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3119751113 Aug 02 06:14:21 PM PDT 24 Aug 02 06:14:23 PM PDT 24 28681407 ps
T1071 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4149053581 Aug 02 06:14:18 PM PDT 24 Aug 02 06:14:19 PM PDT 24 21892513 ps
T1072 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.98607449 Aug 02 06:14:10 PM PDT 24 Aug 02 06:14:11 PM PDT 24 41125657 ps
T1073 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2092205848 Aug 02 06:12:38 PM PDT 24 Aug 02 06:12:42 PM PDT 24 115196658 ps
T1074 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.154727883 Aug 02 06:12:47 PM PDT 24 Aug 02 06:12:48 PM PDT 24 30972441 ps
T295 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1400605140 Aug 02 06:13:39 PM PDT 24 Aug 02 06:13:41 PM PDT 24 123726683 ps
T1075 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.416761018 Aug 02 06:13:20 PM PDT 24 Aug 02 06:13:24 PM PDT 24 225508815 ps
T298 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3225306830 Aug 02 06:14:29 PM PDT 24 Aug 02 06:14:31 PM PDT 24 294048008 ps
T1076 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1196472500 Aug 02 06:13:13 PM PDT 24 Aug 02 06:13:16 PM PDT 24 192102335 ps
T1077 /workspace/coverage/cover_reg_top/29.edn_intr_test.1588051966 Aug 02 06:14:47 PM PDT 24 Aug 02 06:14:48 PM PDT 24 30566962 ps
T1078 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3266704186 Aug 02 06:14:19 PM PDT 24 Aug 02 06:14:20 PM PDT 24 37877393 ps
T1079 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1695124542 Aug 02 06:14:18 PM PDT 24 Aug 02 06:14:20 PM PDT 24 108264890 ps
T1080 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1440074707 Aug 02 06:14:10 PM PDT 24 Aug 02 06:14:13 PM PDT 24 572107509 ps
T1081 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3108277473 Aug 02 06:13:44 PM PDT 24 Aug 02 06:13:47 PM PDT 24 64146695 ps
T1082 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1002751337 Aug 02 06:13:11 PM PDT 24 Aug 02 06:13:13 PM PDT 24 29886312 ps
T1083 /workspace/coverage/cover_reg_top/43.edn_intr_test.1101108294 Aug 02 06:15:00 PM PDT 24 Aug 02 06:15:01 PM PDT 24 124442408 ps
T1084 /workspace/coverage/cover_reg_top/26.edn_intr_test.3880121941 Aug 02 06:14:49 PM PDT 24 Aug 02 06:14:50 PM PDT 24 113079663 ps
T262 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.124943034 Aug 02 06:13:28 PM PDT 24 Aug 02 06:13:29 PM PDT 24 49138858 ps
T1085 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2546657952 Aug 02 06:13:46 PM PDT 24 Aug 02 06:13:47 PM PDT 24 175974446 ps
T1086 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4157138158 Aug 02 06:13:53 PM PDT 24 Aug 02 06:13:56 PM PDT 24 411814490 ps
T1087 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2929538209 Aug 02 06:14:21 PM PDT 24 Aug 02 06:14:23 PM PDT 24 283719778 ps
T1088 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.274777338 Aug 02 06:13:13 PM PDT 24 Aug 02 06:13:16 PM PDT 24 96745011 ps
T1089 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2793391929 Aug 02 06:14:39 PM PDT 24 Aug 02 06:14:41 PM PDT 24 93289262 ps
T1090 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4200335243 Aug 02 06:12:30 PM PDT 24 Aug 02 06:12:31 PM PDT 24 92539973 ps
T1091 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2374053127 Aug 02 06:14:21 PM PDT 24 Aug 02 06:14:22 PM PDT 24 18524644 ps
T1092 /workspace/coverage/cover_reg_top/44.edn_intr_test.42216694 Aug 02 06:15:00 PM PDT 24 Aug 02 06:15:01 PM PDT 24 39551723 ps
T1093 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1361760655 Aug 02 06:14:20 PM PDT 24 Aug 02 06:14:22 PM PDT 24 181942233 ps
T1094 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2601488305 Aug 02 06:12:57 PM PDT 24 Aug 02 06:12:58 PM PDT 24 33514761 ps
T1095 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3143954244 Aug 02 06:12:58 PM PDT 24 Aug 02 06:13:02 PM PDT 24 131929227 ps
T299 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1619196674 Aug 02 06:14:29 PM PDT 24 Aug 02 06:14:31 PM PDT 24 115018557 ps
T1096 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2627747645 Aug 02 06:13:46 PM PDT 24 Aug 02 06:13:47 PM PDT 24 41908344 ps
T1097 /workspace/coverage/cover_reg_top/21.edn_intr_test.2478076882 Aug 02 06:14:40 PM PDT 24 Aug 02 06:14:41 PM PDT 24 16309903 ps
T1098 /workspace/coverage/cover_reg_top/33.edn_intr_test.3682570650 Aug 02 06:14:48 PM PDT 24 Aug 02 06:14:49 PM PDT 24 81191300 ps
T263 /workspace/coverage/cover_reg_top/5.edn_csr_rw.39226884 Aug 02 06:13:37 PM PDT 24 Aug 02 06:13:38 PM PDT 24 12666926 ps
T1099 /workspace/coverage/cover_reg_top/20.edn_intr_test.163702071 Aug 02 06:14:39 PM PDT 24 Aug 02 06:14:40 PM PDT 24 24561051 ps
T1100 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.4223089819 Aug 02 06:13:46 PM PDT 24 Aug 02 06:13:47 PM PDT 24 34054396 ps
T264 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1098903505 Aug 02 06:13:12 PM PDT 24 Aug 02 06:13:13 PM PDT 24 13209298 ps
T1101 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1751942564 Aug 02 06:14:19 PM PDT 24 Aug 02 06:14:23 PM PDT 24 673174205 ps
T1102 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1232786412 Aug 02 06:14:39 PM PDT 24 Aug 02 06:14:41 PM PDT 24 64782624 ps
T1103 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3305495713 Aug 02 06:14:40 PM PDT 24 Aug 02 06:14:41 PM PDT 24 87203867 ps
T1104 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3241690702 Aug 02 06:12:54 PM PDT 24 Aug 02 06:12:55 PM PDT 24 24008620 ps
T1105 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3381463811 Aug 02 06:13:37 PM PDT 24 Aug 02 06:13:40 PM PDT 24 133717265 ps
T1106 /workspace/coverage/cover_reg_top/8.edn_intr_test.1321552265 Aug 02 06:13:55 PM PDT 24 Aug 02 06:13:56 PM PDT 24 33910964 ps
T1107 /workspace/coverage/cover_reg_top/5.edn_intr_test.2952225701 Aug 02 06:13:39 PM PDT 24 Aug 02 06:13:39 PM PDT 24 20938616 ps
T1108 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1251901246 Aug 02 06:14:42 PM PDT 24 Aug 02 06:14:43 PM PDT 24 13079719 ps
T1109 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.534708334 Aug 02 06:13:53 PM PDT 24 Aug 02 06:13:54 PM PDT 24 21953251 ps
T1110 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3815881168 Aug 02 06:12:31 PM PDT 24 Aug 02 06:12:33 PM PDT 24 549592479 ps
T1111 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3425567646 Aug 02 06:13:37 PM PDT 24 Aug 02 06:13:37 PM PDT 24 37714618 ps
T1112 /workspace/coverage/cover_reg_top/49.edn_intr_test.3945423916 Aug 02 06:15:06 PM PDT 24 Aug 02 06:15:07 PM PDT 24 62399177 ps
T1113 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1141070502 Aug 02 06:13:19 PM PDT 24 Aug 02 06:13:21 PM PDT 24 21585358 ps
T1114 /workspace/coverage/cover_reg_top/40.edn_intr_test.3371089817 Aug 02 06:15:06 PM PDT 24 Aug 02 06:15:08 PM PDT 24 17529422 ps
T1115 /workspace/coverage/cover_reg_top/17.edn_intr_test.18095393 Aug 02 06:14:28 PM PDT 24 Aug 02 06:14:29 PM PDT 24 32013996 ps
T265 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2877553430 Aug 02 06:12:56 PM PDT 24 Aug 02 06:12:57 PM PDT 24 37809220 ps
T1116 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2007574512 Aug 02 06:13:55 PM PDT 24 Aug 02 06:13:57 PM PDT 24 136070174 ps
T300 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.46354977 Aug 02 06:13:47 PM PDT 24 Aug 02 06:13:50 PM PDT 24 164503220 ps
T1117 /workspace/coverage/cover_reg_top/38.edn_intr_test.1583405933 Aug 02 06:14:58 PM PDT 24 Aug 02 06:14:59 PM PDT 24 13443534 ps
T1118 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.372505435 Aug 02 06:13:12 PM PDT 24 Aug 02 06:13:13 PM PDT 24 25882885 ps
T1119 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1147680485 Aug 02 06:14:09 PM PDT 24 Aug 02 06:14:11 PM PDT 24 162180392 ps
T1120 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2529483820 Aug 02 06:14:37 PM PDT 24 Aug 02 06:14:38 PM PDT 24 19605627 ps
T1121 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2205960841 Aug 02 06:14:09 PM PDT 24 Aug 02 06:14:10 PM PDT 24 22759333 ps
T1122 /workspace/coverage/cover_reg_top/37.edn_intr_test.3017860776 Aug 02 06:15:00 PM PDT 24 Aug 02 06:15:01 PM PDT 24 12901381 ps
T1123 /workspace/coverage/cover_reg_top/41.edn_intr_test.1545377240 Aug 02 06:15:00 PM PDT 24 Aug 02 06:15:01 PM PDT 24 17958898 ps
T1124 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1985946909 Aug 02 06:13:05 PM PDT 24 Aug 02 06:13:07 PM PDT 24 127346115 ps
T266 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1638072528 Aug 02 06:13:27 PM PDT 24 Aug 02 06:13:28 PM PDT 24 58660093 ps

Test location /workspace/coverage/default/140.edn_genbits.1867706357
Short name T14
Test name
Test status
Simulation time 98530405 ps
CPU time 1.77 seconds
Started Aug 02 06:42:24 PM PDT 24
Finished Aug 02 06:42:26 PM PDT 24
Peak memory 219976 kb
Host smart-3f13ca6b-ad51-4fa5-9918-856e5cda056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867706357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1867706357
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/170.edn_alert.2676207138
Short name T18
Test name
Test status
Simulation time 117060190 ps
CPU time 1.08 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:34 PM PDT 24
Peak memory 220536 kb
Host smart-b36ea906-9baf-4589-ade5-654f8b87f52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676207138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2676207138
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1312023124
Short name T21
Test name
Test status
Simulation time 30623039802 ps
CPU time 710.63 seconds
Started Aug 02 06:40:47 PM PDT 24
Finished Aug 02 06:52:38 PM PDT 24
Peak memory 218408 kb
Host smart-2ef77ffd-21e7-47f1-9485-65f0af9e063a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312023124 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1312023124
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_err.494868185
Short name T5
Test name
Test status
Simulation time 68407296 ps
CPU time 1.09 seconds
Started Aug 02 06:41:27 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 219776 kb
Host smart-69e223a0-3d23-41ff-bc11-3378ae834742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494868185 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.494868185
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/100.edn_alert.2010527407
Short name T69
Test name
Test status
Simulation time 46763348 ps
CPU time 1.41 seconds
Started Aug 02 06:41:55 PM PDT 24
Finished Aug 02 06:41:57 PM PDT 24
Peak memory 219272 kb
Host smart-0e2fa111-f6d7-462f-a754-c5d560f8958a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010527407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2010527407
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/4.edn_err.3750275464
Short name T9
Test name
Test status
Simulation time 23221905 ps
CPU time 1.34 seconds
Started Aug 02 06:40:02 PM PDT 24
Finished Aug 02 06:40:04 PM PDT 24
Peak memory 224052 kb
Host smart-5c9fe702-eb07-455f-9d89-7489834d7c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750275464 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3750275464
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/10.edn_stress_all.2696183321
Short name T112
Test name
Test status
Simulation time 95541103 ps
CPU time 2.47 seconds
Started Aug 02 06:40:09 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 217064 kb
Host smart-7c16a3b5-97e5-4704-a607-bb9e2874112a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696183321 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2696183321
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/251.edn_genbits.265536721
Short name T66
Test name
Test status
Simulation time 394389022 ps
CPU time 1.67 seconds
Started Aug 02 06:42:45 PM PDT 24
Finished Aug 02 06:42:47 PM PDT 24
Peak memory 220748 kb
Host smart-e77d9349-b60c-4d34-83d1-0e27b02ae4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265536721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.265536721
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/60.edn_alert.4009781520
Short name T74
Test name
Test status
Simulation time 38400877 ps
CPU time 1.15 seconds
Started Aug 02 06:41:29 PM PDT 24
Finished Aug 02 06:41:30 PM PDT 24
Peak memory 219844 kb
Host smart-d2a1d10d-129b-436c-a11d-000c2fcf04f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009781520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.4009781520
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/8.edn_intr.2419637575
Short name T88
Test name
Test status
Simulation time 22964922 ps
CPU time 1.01 seconds
Started Aug 02 06:40:09 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 216000 kb
Host smart-9c3b8468-a0e7-4fbe-829e-4f5153b37e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419637575 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2419637575
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.4151169026
Short name T224
Test name
Test status
Simulation time 122399201512 ps
CPU time 724.27 seconds
Started Aug 02 06:41:15 PM PDT 24
Finished Aug 02 06:53:19 PM PDT 24
Peak memory 219976 kb
Host smart-99704331-5f71-4bc4-8138-6360045ab938
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151169026 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.4151169026
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_regwen.2215828601
Short name T552
Test name
Test status
Simulation time 19308712 ps
CPU time 1.02 seconds
Started Aug 02 06:39:57 PM PDT 24
Finished Aug 02 06:39:58 PM PDT 24
Peak memory 207152 kb
Host smart-7845743d-d68b-472e-9b2d-2b48327a8c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215828601 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2215828601
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/98.edn_err.3758470546
Short name T51
Test name
Test status
Simulation time 31105079 ps
CPU time 1.06 seconds
Started Aug 02 06:41:59 PM PDT 24
Finished Aug 02 06:42:00 PM PDT 24
Peak memory 218192 kb
Host smart-bb127f0b-1281-4a96-9b7c-24302b7ef9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758470546 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3758470546
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.226027209
Short name T1
Test name
Test status
Simulation time 53392468 ps
CPU time 1.13 seconds
Started Aug 02 06:40:16 PM PDT 24
Finished Aug 02 06:40:18 PM PDT 24
Peak memory 218576 kb
Host smart-264f972f-c421-47a3-b156-e22e87115b52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226027209 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.226027209
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_disable.3495897446
Short name T23
Test name
Test status
Simulation time 11503815 ps
CPU time 0.92 seconds
Started Aug 02 06:40:46 PM PDT 24
Finished Aug 02 06:40:47 PM PDT 24
Peak memory 216240 kb
Host smart-add0e10b-b69d-4440-8530-d19bcdaa0ae5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495897446 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3495897446
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/43.edn_alert.1426004515
Short name T303
Test name
Test status
Simulation time 46792188 ps
CPU time 1.2 seconds
Started Aug 02 06:41:15 PM PDT 24
Finished Aug 02 06:41:16 PM PDT 24
Peak memory 219008 kb
Host smart-b66171ea-4ecf-4075-af23-fe745bad5ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426004515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1426004515
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.473594756
Short name T294
Test name
Test status
Simulation time 234833025 ps
CPU time 2.39 seconds
Started Aug 02 06:14:21 PM PDT 24
Finished Aug 02 06:14:23 PM PDT 24
Peak memory 206840 kb
Host smart-759039c8-04ba-4b11-9c11-ff9898617759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473594756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.473594756
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/default/45.edn_disable.2722364834
Short name T108
Test name
Test status
Simulation time 27993666 ps
CPU time 0.85 seconds
Started Aug 02 06:41:18 PM PDT 24
Finished Aug 02 06:41:19 PM PDT 24
Peak memory 216368 kb
Host smart-42cc07b8-ce08-419a-9c88-9ef186c8c2a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722364834 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2722364834
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/28.edn_alert.2828065635
Short name T178
Test name
Test status
Simulation time 86798717 ps
CPU time 1.34 seconds
Started Aug 02 06:40:47 PM PDT 24
Finished Aug 02 06:40:49 PM PDT 24
Peak memory 219680 kb
Host smart-ee954080-603e-4c69-bb12-bd6c63350567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828065635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2828065635
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.3804195621
Short name T106
Test name
Test status
Simulation time 33957880 ps
CPU time 0.91 seconds
Started Aug 02 06:40:10 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 216328 kb
Host smart-ece1f094-da66-461a-bc38-fd8e5c077f80
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804195621 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3804195621
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2442736813
Short name T124
Test name
Test status
Simulation time 47913346 ps
CPU time 1.49 seconds
Started Aug 02 06:40:18 PM PDT 24
Finished Aug 02 06:40:19 PM PDT 24
Peak memory 216780 kb
Host smart-4f92ce54-47a7-4125-8b55-5b40075d51aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442736813 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2442736813
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.676856809
Short name T130
Test name
Test status
Simulation time 132044081 ps
CPU time 1.14 seconds
Started Aug 02 06:41:30 PM PDT 24
Finished Aug 02 06:41:31 PM PDT 24
Peak memory 216900 kb
Host smart-93e6c072-ccb0-4eda-bae5-0342891f7479
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676856809 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.676856809
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.397168795
Short name T261
Test name
Test status
Simulation time 25159553 ps
CPU time 0.89 seconds
Started Aug 02 06:14:10 PM PDT 24
Finished Aug 02 06:14:11 PM PDT 24
Peak memory 206648 kb
Host smart-7c976e42-6998-4c62-8f12-1e3297ce8b9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397168795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.397168795
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/default/32.edn_intr.2049975540
Short name T92
Test name
Test status
Simulation time 28580116 ps
CPU time 0.96 seconds
Started Aug 02 06:40:56 PM PDT 24
Finished Aug 02 06:40:57 PM PDT 24
Peak memory 215908 kb
Host smart-62c1f710-6d43-4fe8-af1b-1ce83b04b199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049975540 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2049975540
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/248.edn_genbits.1294268290
Short name T12
Test name
Test status
Simulation time 44200193 ps
CPU time 1.23 seconds
Started Aug 02 06:42:50 PM PDT 24
Finished Aug 02 06:42:52 PM PDT 24
Peak memory 218968 kb
Host smart-71cc61b0-d7d6-4ec5-96a2-7d9692dc52f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294268290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1294268290
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3686368067
Short name T250
Test name
Test status
Simulation time 30355956 ps
CPU time 1.32 seconds
Started Aug 02 06:41:31 PM PDT 24
Finished Aug 02 06:41:33 PM PDT 24
Peak memory 220680 kb
Host smart-a6805037-6ed8-4898-b21f-6fdadc2abb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686368067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3686368067
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/152.edn_alert.860880893
Short name T73
Test name
Test status
Simulation time 26839682 ps
CPU time 1.22 seconds
Started Aug 02 06:42:23 PM PDT 24
Finished Aug 02 06:42:25 PM PDT 24
Peak memory 219704 kb
Host smart-3dd418d7-0041-4fa6-b97e-00eb84ecf899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860880893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.860880893
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert.295760674
Short name T281
Test name
Test status
Simulation time 191180582 ps
CPU time 1.32 seconds
Started Aug 02 06:41:04 PM PDT 24
Finished Aug 02 06:41:05 PM PDT 24
Peak memory 220648 kb
Host smart-c02f608c-7c94-460c-93df-88444b94ae9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295760674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.295760674
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/33.edn_genbits.3757570843
Short name T27
Test name
Test status
Simulation time 75086752 ps
CPU time 1.78 seconds
Started Aug 02 06:40:55 PM PDT 24
Finished Aug 02 06:40:57 PM PDT 24
Peak memory 218704 kb
Host smart-d32d9259-258b-45a9-b094-a0069d1b1c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757570843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3757570843
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_alert.1772772235
Short name T11
Test name
Test status
Simulation time 80807872 ps
CPU time 1.19 seconds
Started Aug 02 06:41:20 PM PDT 24
Finished Aug 02 06:41:22 PM PDT 24
Peak memory 218784 kb
Host smart-4eec5f6b-5b34-4699-b37d-201dff1c558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772772235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1772772235
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.1089455828
Short name T418
Test name
Test status
Simulation time 29717812 ps
CPU time 1.16 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:09 PM PDT 24
Peak memory 218356 kb
Host smart-2ff35069-0769-44b3-9ac6-365e2da0db5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089455828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1089455828
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_alert.3057336150
Short name T210
Test name
Test status
Simulation time 83534881 ps
CPU time 1.08 seconds
Started Aug 02 06:41:11 PM PDT 24
Finished Aug 02 06:41:12 PM PDT 24
Peak memory 219832 kb
Host smart-5e531bab-d4ad-477a-bf62-36f89282a932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057336150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3057336150
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.4177414528
Short name T228
Test name
Test status
Simulation time 95990416122 ps
CPU time 640.61 seconds
Started Aug 02 06:39:46 PM PDT 24
Finished Aug 02 06:50:27 PM PDT 24
Peak memory 220756 kb
Host smart-b7887a12-4663-4c76-8b58-044871d87a45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177414528 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.4177414528
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1787557526
Short name T153
Test name
Test status
Simulation time 60774844 ps
CPU time 1.14 seconds
Started Aug 02 06:39:48 PM PDT 24
Finished Aug 02 06:39:50 PM PDT 24
Peak memory 216836 kb
Host smart-4df248f0-3afc-490f-875a-1aee34737af7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787557526 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1787557526
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/111.edn_alert.6584656
Short name T188
Test name
Test status
Simulation time 23871179 ps
CPU time 1.19 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:09 PM PDT 24
Peak memory 219844 kb
Host smart-bb4bca0c-83ba-4be3-bb8a-7b8237c689b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6584656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.6584656
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/104.edn_alert.2197918119
Short name T102
Test name
Test status
Simulation time 23292441 ps
CPU time 1.21 seconds
Started Aug 02 06:41:57 PM PDT 24
Finished Aug 02 06:41:58 PM PDT 24
Peak memory 218788 kb
Host smart-55d3bb8a-8b16-4563-8285-0dbe63a34d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197918119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2197918119
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/26.edn_disable.4113547615
Short name T183
Test name
Test status
Simulation time 15327036 ps
CPU time 0.9 seconds
Started Aug 02 06:40:41 PM PDT 24
Finished Aug 02 06:40:42 PM PDT 24
Peak memory 215624 kb
Host smart-fab44162-f3d3-4acd-88f7-85b711e31371
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113547615 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4113547615
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/161.edn_alert.3068026219
Short name T205
Test name
Test status
Simulation time 24617523 ps
CPU time 1.19 seconds
Started Aug 02 06:42:26 PM PDT 24
Finished Aug 02 06:42:27 PM PDT 24
Peak memory 219932 kb
Host smart-0d18beff-404e-402d-8ea5-2558b4386403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068026219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3068026219
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert.787641111
Short name T939
Test name
Test status
Simulation time 50926013 ps
CPU time 1.28 seconds
Started Aug 02 06:39:48 PM PDT 24
Finished Aug 02 06:39:49 PM PDT 24
Peak memory 220668 kb
Host smart-074a90e9-6ca5-4e8b-af58-abb377fc1f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787641111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.787641111
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert.1178146144
Short name T469
Test name
Test status
Simulation time 35715586 ps
CPU time 1.3 seconds
Started Aug 02 06:39:52 PM PDT 24
Finished Aug 02 06:39:53 PM PDT 24
Peak memory 219128 kb
Host smart-e6f775e1-2f2d-4895-abf3-c3d73216b1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178146144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1178146144
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/14.edn_disable.1272970799
Short name T50
Test name
Test status
Simulation time 43326453 ps
CPU time 0.87 seconds
Started Aug 02 06:40:15 PM PDT 24
Finished Aug 02 06:40:16 PM PDT 24
Peak memory 216240 kb
Host smart-846c442a-b2c0-44ed-9382-d42d0a54d3d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272970799 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1272970799
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.285642243
Short name T177
Test name
Test status
Simulation time 31279663 ps
CPU time 1.43 seconds
Started Aug 02 06:39:54 PM PDT 24
Finished Aug 02 06:39:56 PM PDT 24
Peak memory 216932 kb
Host smart-1b8821a0-93c6-4c65-8bda-6f6b3da11f6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285642243 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.285642243
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_intr.2935784529
Short name T577
Test name
Test status
Simulation time 47471323 ps
CPU time 0.87 seconds
Started Aug 02 06:39:58 PM PDT 24
Finished Aug 02 06:39:59 PM PDT 24
Peak memory 215120 kb
Host smart-3e70bcd3-1d4f-40ae-b1af-884d81a31342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935784529 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2935784529
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/22.edn_disable.3092243944
Short name T121
Test name
Test status
Simulation time 39403697 ps
CPU time 0.87 seconds
Started Aug 02 06:40:40 PM PDT 24
Finished Aug 02 06:40:41 PM PDT 24
Peak memory 216252 kb
Host smart-f1de40dc-cd05-4719-8c55-55f663369a1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092243944 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3092243944
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.133798580
Short name T933
Test name
Test status
Simulation time 22376317 ps
CPU time 1.03 seconds
Started Aug 02 06:40:30 PM PDT 24
Finished Aug 02 06:40:31 PM PDT 24
Peak memory 218584 kb
Host smart-329e92a8-877c-454a-906f-e35e327b5ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133798580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.133798580
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/25.edn_disable.1627521989
Short name T199
Test name
Test status
Simulation time 57126460 ps
CPU time 1.02 seconds
Started Aug 02 06:40:41 PM PDT 24
Finished Aug 02 06:40:42 PM PDT 24
Peak memory 216292 kb
Host smart-5b884770-c80f-4197-bcd1-e8d64f825d3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627521989 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1627521989
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable.3467151384
Short name T137
Test name
Test status
Simulation time 20196005 ps
CPU time 0.89 seconds
Started Aug 02 06:40:46 PM PDT 24
Finished Aug 02 06:40:47 PM PDT 24
Peak memory 216316 kb
Host smart-e42c0c38-100d-45e2-a75b-1b2a1971dcd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467151384 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3467151384
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable.1262543246
Short name T133
Test name
Test status
Simulation time 11431311 ps
CPU time 0.85 seconds
Started Aug 02 06:40:56 PM PDT 24
Finished Aug 02 06:40:57 PM PDT 24
Peak memory 216260 kb
Host smart-6734b7c8-8f18-422c-9831-33f2f1189b25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262543246 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1262543246
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.594508283
Short name T139
Test name
Test status
Simulation time 19892649 ps
CPU time 1.01 seconds
Started Aug 02 06:40:55 PM PDT 24
Finished Aug 02 06:40:56 PM PDT 24
Peak memory 219800 kb
Host smart-e460fbb1-eea9-475d-8fba-1755918986a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594508283 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.594508283
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2155290963
Short name T212
Test name
Test status
Simulation time 19657494 ps
CPU time 1.07 seconds
Started Aug 02 06:40:56 PM PDT 24
Finished Aug 02 06:40:58 PM PDT 24
Peak memory 219424 kb
Host smart-25b968cf-bcc2-4929-bda9-928b436e0819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155290963 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2155290963
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/58.edn_alert.2420120741
Short name T720
Test name
Test status
Simulation time 25505184 ps
CPU time 1.17 seconds
Started Aug 02 06:41:30 PM PDT 24
Finished Aug 02 06:41:31 PM PDT 24
Peak memory 219736 kb
Host smart-171ee6ac-eb49-432a-b553-1fdb2f5f3954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420120741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.2420120741
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.3990637872
Short name T203
Test name
Test status
Simulation time 21205073 ps
CPU time 1.21 seconds
Started Aug 02 06:41:43 PM PDT 24
Finished Aug 02 06:41:45 PM PDT 24
Peak memory 224056 kb
Host smart-d107bde4-ea04-4f4b-a70b-a32df529b0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990637872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3990637872
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1720966745
Short name T30
Test name
Test status
Simulation time 78340809 ps
CPU time 2.57 seconds
Started Aug 02 06:40:41 PM PDT 24
Finished Aug 02 06:40:44 PM PDT 24
Peak memory 215308 kb
Host smart-e07f9ef3-6a40-4d90-bc73-c07e253e826a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720966745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1720966745
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert_test.3208987511
Short name T354
Test name
Test status
Simulation time 30614866 ps
CPU time 0.96 seconds
Started Aug 02 06:39:50 PM PDT 24
Finished Aug 02 06:39:51 PM PDT 24
Peak memory 206748 kb
Host smart-37f0a8df-1d35-4e3f-a13b-7d06bc2525c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208987511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3208987511
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/80.edn_genbits.1415639719
Short name T322
Test name
Test status
Simulation time 45142260 ps
CPU time 1.27 seconds
Started Aug 02 06:41:39 PM PDT 24
Finished Aug 02 06:41:40 PM PDT 24
Peak memory 220284 kb
Host smart-f1c55e39-e9f4-46db-8db6-ca7f347089a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415639719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1415639719
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/110.edn_alert.4007886482
Short name T301
Test name
Test status
Simulation time 102144945 ps
CPU time 1.25 seconds
Started Aug 02 06:41:57 PM PDT 24
Finished Aug 02 06:41:58 PM PDT 24
Peak memory 220628 kb
Host smart-79730dbb-befa-4f35-8355-4f4643890cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007886482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.4007886482
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3780944726
Short name T246
Test name
Test status
Simulation time 51889580 ps
CPU time 1.14 seconds
Started Aug 02 06:40:16 PM PDT 24
Finished Aug 02 06:40:17 PM PDT 24
Peak memory 218524 kb
Host smart-3d54cd18-8679-47b5-99c2-a2b92f868f13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780944726 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3780944726
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_intr.2212925166
Short name T84
Test name
Test status
Simulation time 26344461 ps
CPU time 0.92 seconds
Started Aug 02 06:41:11 PM PDT 24
Finished Aug 02 06:41:12 PM PDT 24
Peak memory 216004 kb
Host smart-a5f620d7-da19-4183-a0ea-884649bca2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212925166 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2212925166
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/61.edn_genbits.3372794436
Short name T319
Test name
Test status
Simulation time 44753639 ps
CPU time 1.48 seconds
Started Aug 02 06:41:28 PM PDT 24
Finished Aug 02 06:41:30 PM PDT 24
Peak memory 219948 kb
Host smart-26a4f560-91a6-4a25-a672-fe6670a80268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372794436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3372794436
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1363922468
Short name T325
Test name
Test status
Simulation time 92320441 ps
CPU time 1.24 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 217500 kb
Host smart-a8b3b09c-50de-4d66-b355-11f5699d52fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363922468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1363922468
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2925702932
Short name T274
Test name
Test status
Simulation time 78990189 ps
CPU time 1.13 seconds
Started Aug 02 06:14:09 PM PDT 24
Finished Aug 02 06:14:10 PM PDT 24
Peak memory 206784 kb
Host smart-67b2234d-4cb9-49cb-882b-c5d91cd26e8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925702932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2925702932
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3225306830
Short name T298
Test name
Test status
Simulation time 294048008 ps
CPU time 2.37 seconds
Started Aug 02 06:14:29 PM PDT 24
Finished Aug 02 06:14:31 PM PDT 24
Peak memory 206848 kb
Host smart-2a19cb76-71cd-448b-b286-d95ffbeb0815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225306830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3225306830
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1400605140
Short name T295
Test name
Test status
Simulation time 123726683 ps
CPU time 2.52 seconds
Started Aug 02 06:13:39 PM PDT 24
Finished Aug 02 06:13:41 PM PDT 24
Peak memory 206732 kb
Host smart-299eceb2-b6b8-410e-8f6e-2a6427934164
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400605140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1400605140
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.455565497
Short name T278
Test name
Test status
Simulation time 47037261 ps
CPU time 1.13 seconds
Started Aug 02 06:40:08 PM PDT 24
Finished Aug 02 06:40:09 PM PDT 24
Peak memory 219668 kb
Host smart-226ab30b-d93c-4173-9e23-f573dfd70d2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455565497 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.455565497
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/103.edn_genbits.2677427668
Short name T276
Test name
Test status
Simulation time 52141688 ps
CPU time 1.02 seconds
Started Aug 02 06:41:55 PM PDT 24
Finished Aug 02 06:41:56 PM PDT 24
Peak memory 217384 kb
Host smart-4f3fd57d-210a-4218-a557-eee624abacd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677427668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2677427668
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.289239735
Short name T709
Test name
Test status
Simulation time 47489791 ps
CPU time 1.48 seconds
Started Aug 02 06:41:56 PM PDT 24
Finished Aug 02 06:41:57 PM PDT 24
Peak memory 218368 kb
Host smart-f8f20ff6-b03c-4520-bb2b-b38faff1593c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289239735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.289239735
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.2736124736
Short name T324
Test name
Test status
Simulation time 357526317 ps
CPU time 1.4 seconds
Started Aug 02 06:42:11 PM PDT 24
Finished Aug 02 06:42:13 PM PDT 24
Peak memory 217264 kb
Host smart-817de41a-3f23-45db-a74a-f7994d6371ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736124736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2736124736
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/120.edn_alert.1563529101
Short name T288
Test name
Test status
Simulation time 78099191 ps
CPU time 1.14 seconds
Started Aug 02 06:42:06 PM PDT 24
Finished Aug 02 06:42:07 PM PDT 24
Peak memory 218416 kb
Host smart-b2f22940-b7a0-4fa5-b81a-bdaf1be2cb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563529101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1563529101
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.2578822400
Short name T341
Test name
Test status
Simulation time 46958127 ps
CPU time 1.46 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:09 PM PDT 24
Peak memory 218760 kb
Host smart-8fc547a7-4e4e-4222-af12-fd8fb1ac7fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578822400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2578822400
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2278376593
Short name T944
Test name
Test status
Simulation time 295460101 ps
CPU time 2.02 seconds
Started Aug 02 06:42:06 PM PDT 24
Finished Aug 02 06:42:09 PM PDT 24
Peak memory 218820 kb
Host smart-d861699c-b40e-46de-8874-c7600e6641d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278376593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2278376593
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_genbits.2246812424
Short name T337
Test name
Test status
Simulation time 45418003 ps
CPU time 1.04 seconds
Started Aug 02 06:40:20 PM PDT 24
Finished Aug 02 06:40:21 PM PDT 24
Peak memory 218708 kb
Host smart-6ac02ae6-9463-45cb-9a90-db1661b3c4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246812424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2246812424
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.152891395
Short name T306
Test name
Test status
Simulation time 45677758 ps
CPU time 1.12 seconds
Started Aug 02 06:42:23 PM PDT 24
Finished Aug 02 06:42:25 PM PDT 24
Peak memory 219432 kb
Host smart-2213e4b5-ac8e-42f4-8080-cfe840387016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152891395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.152891395
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.988859140
Short name T333
Test name
Test status
Simulation time 50839521 ps
CPU time 1.2 seconds
Started Aug 02 06:42:23 PM PDT 24
Finished Aug 02 06:42:24 PM PDT 24
Peak memory 220032 kb
Host smart-ffa5ae71-c107-46cf-89fc-992a674d9b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988859140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.988859140
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1131843172
Short name T320
Test name
Test status
Simulation time 23639220 ps
CPU time 1.19 seconds
Started Aug 02 06:42:31 PM PDT 24
Finished Aug 02 06:42:33 PM PDT 24
Peak memory 217420 kb
Host smart-8c89ab61-673b-495b-88c2-ef2a2c74fe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131843172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1131843172
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2915251490
Short name T87
Test name
Test status
Simulation time 20285093 ps
CPU time 1.1 seconds
Started Aug 02 06:40:32 PM PDT 24
Finished Aug 02 06:40:33 PM PDT 24
Peak memory 215948 kb
Host smart-1d54be64-7059-41b5-80ae-aac4a481a89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915251490 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2915251490
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/169.edn_alert.3925704661
Short name T220
Test name
Test status
Simulation time 71936368 ps
CPU time 1.16 seconds
Started Aug 02 06:42:23 PM PDT 24
Finished Aug 02 06:42:25 PM PDT 24
Peak memory 215756 kb
Host smart-cbcc968b-5b6b-42e0-97f2-8b4f49852638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925704661 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.3925704661
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.306816195
Short name T447
Test name
Test status
Simulation time 74644774 ps
CPU time 1.62 seconds
Started Aug 02 06:42:00 PM PDT 24
Finished Aug 02 06:42:02 PM PDT 24
Peak memory 218772 kb
Host smart-61b0bdfd-05bf-4686-899e-f2c3dc85bc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306816195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.306816195
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.443008743
Short name T1050
Test name
Test status
Simulation time 51384438 ps
CPU time 1.25 seconds
Started Aug 02 06:12:48 PM PDT 24
Finished Aug 02 06:12:49 PM PDT 24
Peak memory 206668 kb
Host smart-22c906dd-2330-4438-b742-0ea5a2371a98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443008743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.443008743
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2092205848
Short name T1073
Test name
Test status
Simulation time 115196658 ps
CPU time 3.25 seconds
Started Aug 02 06:12:38 PM PDT 24
Finished Aug 02 06:12:42 PM PDT 24
Peak memory 206664 kb
Host smart-ca777f97-5b7f-4e97-9ca8-0c1f2aa3ca13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092205848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2092205848
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2529397858
Short name T996
Test name
Test status
Simulation time 16111965 ps
CPU time 0.9 seconds
Started Aug 02 06:12:39 PM PDT 24
Finished Aug 02 06:12:39 PM PDT 24
Peak memory 206636 kb
Host smart-155a3b20-c1d5-42b5-b405-70bf06da6f40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529397858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2529397858
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3231135555
Short name T1007
Test name
Test status
Simulation time 36323768 ps
CPU time 1.35 seconds
Started Aug 02 06:12:48 PM PDT 24
Finished Aug 02 06:12:50 PM PDT 24
Peak memory 215036 kb
Host smart-d61516d8-5223-421c-8028-0ea4aaf28345
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231135555 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3231135555
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3237460238
Short name T258
Test name
Test status
Simulation time 15811019 ps
CPU time 0.88 seconds
Started Aug 02 06:12:38 PM PDT 24
Finished Aug 02 06:12:39 PM PDT 24
Peak memory 206640 kb
Host smart-cf6f2304-3fa6-492a-8efb-6eacc9a7fcbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237460238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3237460238
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.885402969
Short name T1044
Test name
Test status
Simulation time 11404454 ps
CPU time 0.85 seconds
Started Aug 02 06:12:30 PM PDT 24
Finished Aug 02 06:12:30 PM PDT 24
Peak memory 206552 kb
Host smart-72d98971-5605-4636-9f35-91041fb2d15a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885402969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.885402969
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.154727883
Short name T1074
Test name
Test status
Simulation time 30972441 ps
CPU time 1.35 seconds
Started Aug 02 06:12:47 PM PDT 24
Finished Aug 02 06:12:48 PM PDT 24
Peak memory 206788 kb
Host smart-f2f8f663-ca2b-4609-86e5-1d936b0c1932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154727883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.154727883
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3815881168
Short name T1110
Test name
Test status
Simulation time 549592479 ps
CPU time 2.45 seconds
Started Aug 02 06:12:31 PM PDT 24
Finished Aug 02 06:12:33 PM PDT 24
Peak memory 214932 kb
Host smart-a1b52250-1aa7-42bd-a075-ebaa5daccdcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815881168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3815881168
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4200335243
Short name T1090
Test name
Test status
Simulation time 92539973 ps
CPU time 1.57 seconds
Started Aug 02 06:12:30 PM PDT 24
Finished Aug 02 06:12:31 PM PDT 24
Peak memory 215016 kb
Host smart-43d6af19-5cfb-47c1-8f6f-be11ea814399
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200335243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4200335243
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4023342447
Short name T1024
Test name
Test status
Simulation time 22212965 ps
CPU time 1.18 seconds
Started Aug 02 06:12:55 PM PDT 24
Finished Aug 02 06:12:56 PM PDT 24
Peak memory 206572 kb
Host smart-e383a220-6f12-4a3b-a61e-1a8a8ace00bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023342447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.4023342447
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3143954244
Short name T1095
Test name
Test status
Simulation time 131929227 ps
CPU time 3.53 seconds
Started Aug 02 06:12:58 PM PDT 24
Finished Aug 02 06:13:02 PM PDT 24
Peak memory 206588 kb
Host smart-c03e2de2-39a9-4c7f-97b4-3710920e46b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143954244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3143954244
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2601488305
Short name T1094
Test name
Test status
Simulation time 33514761 ps
CPU time 1.04 seconds
Started Aug 02 06:12:57 PM PDT 24
Finished Aug 02 06:12:58 PM PDT 24
Peak memory 206604 kb
Host smart-900ccaf7-d9b6-4f2c-b4e9-7512c0518589
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601488305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2601488305
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1009821501
Short name T1060
Test name
Test status
Simulation time 33554585 ps
CPU time 1.3 seconds
Started Aug 02 06:12:54 PM PDT 24
Finished Aug 02 06:12:55 PM PDT 24
Peak memory 215192 kb
Host smart-600dd89a-5c48-4782-9690-215812559726
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009821501 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1009821501
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2877553430
Short name T265
Test name
Test status
Simulation time 37809220 ps
CPU time 0.83 seconds
Started Aug 02 06:12:56 PM PDT 24
Finished Aug 02 06:12:57 PM PDT 24
Peak memory 206620 kb
Host smart-2fb5025f-e9ae-44f4-a1a9-03d20eb6430f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877553430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2877553430
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.533890823
Short name T1004
Test name
Test status
Simulation time 16514516 ps
CPU time 0.92 seconds
Started Aug 02 06:12:45 PM PDT 24
Finished Aug 02 06:12:46 PM PDT 24
Peak memory 206620 kb
Host smart-fcb13135-8ecd-4f16-946d-4c58ee6e1343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533890823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.533890823
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3241690702
Short name T1104
Test name
Test status
Simulation time 24008620 ps
CPU time 0.93 seconds
Started Aug 02 06:12:54 PM PDT 24
Finished Aug 02 06:12:55 PM PDT 24
Peak memory 206732 kb
Host smart-5c23a4fb-5931-472f-aaeb-98c5aeff177e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241690702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3241690702
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1775032035
Short name T1069
Test name
Test status
Simulation time 71257132 ps
CPU time 2.65 seconds
Started Aug 02 06:12:48 PM PDT 24
Finished Aug 02 06:12:50 PM PDT 24
Peak memory 215008 kb
Host smart-ba1b75c4-72e8-4807-b80e-32a152a4c01a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775032035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1775032035
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1495452940
Short name T296
Test name
Test status
Simulation time 334533301 ps
CPU time 1.76 seconds
Started Aug 02 06:12:47 PM PDT 24
Finished Aug 02 06:12:49 PM PDT 24
Peak memory 206724 kb
Host smart-b3202b7b-8392-4c28-9b3e-1176b06c1e72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495452940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1495452940
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.98607449
Short name T1072
Test name
Test status
Simulation time 41125657 ps
CPU time 1.43 seconds
Started Aug 02 06:14:10 PM PDT 24
Finished Aug 02 06:14:11 PM PDT 24
Peak memory 215084 kb
Host smart-5a239bac-4b5a-463e-89dc-de0ef1ad4049
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98607449 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.98607449
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3482614910
Short name T1037
Test name
Test status
Simulation time 19837999 ps
CPU time 0.83 seconds
Started Aug 02 06:13:54 PM PDT 24
Finished Aug 02 06:13:55 PM PDT 24
Peak memory 206420 kb
Host smart-c92fe90f-643e-4636-b13a-9c4207641368
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482614910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3482614910
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2835204901
Short name T1001
Test name
Test status
Simulation time 31860209 ps
CPU time 0.88 seconds
Started Aug 02 06:13:54 PM PDT 24
Finished Aug 02 06:13:55 PM PDT 24
Peak memory 206580 kb
Host smart-9427eadd-a112-4aeb-94f7-cef6d39b4ffc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835204901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2835204901
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2650426126
Short name T1009
Test name
Test status
Simulation time 157036004 ps
CPU time 2.83 seconds
Started Aug 02 06:13:52 PM PDT 24
Finished Aug 02 06:13:55 PM PDT 24
Peak memory 214976 kb
Host smart-68c62903-b564-4b7c-ae70-e422279e2a08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650426126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2650426126
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2007574512
Short name T1116
Test name
Test status
Simulation time 136070174 ps
CPU time 2.27 seconds
Started Aug 02 06:13:55 PM PDT 24
Finished Aug 02 06:13:57 PM PDT 24
Peak memory 206840 kb
Host smart-c5c23367-7769-45b8-878a-0bb98e31fa64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007574512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2007574512
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.718780436
Short name T1017
Test name
Test status
Simulation time 217981559 ps
CPU time 1.37 seconds
Started Aug 02 06:14:09 PM PDT 24
Finished Aug 02 06:14:11 PM PDT 24
Peak memory 214980 kb
Host smart-95e9e9ef-4c5b-4c99-afcd-7ee2cd377b6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718780436 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.718780436
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3904983875
Short name T1061
Test name
Test status
Simulation time 18872906 ps
CPU time 0.8 seconds
Started Aug 02 06:14:08 PM PDT 24
Finished Aug 02 06:14:08 PM PDT 24
Peak memory 206440 kb
Host smart-5e6624be-4478-47c1-ae8e-ea7afb0bc562
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904983875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3904983875
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1927867618
Short name T1064
Test name
Test status
Simulation time 23335309 ps
CPU time 1.13 seconds
Started Aug 02 06:14:10 PM PDT 24
Finished Aug 02 06:14:11 PM PDT 24
Peak memory 206736 kb
Host smart-177adb6b-d90e-4d60-8a64-9f6f34814c82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927867618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1927867618
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1440074707
Short name T1080
Test name
Test status
Simulation time 572107509 ps
CPU time 3.22 seconds
Started Aug 02 06:14:10 PM PDT 24
Finished Aug 02 06:14:13 PM PDT 24
Peak memory 215028 kb
Host smart-6b6e783c-8cb1-450e-9556-6421544364ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440074707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1440074707
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1147680485
Short name T1119
Test name
Test status
Simulation time 162180392 ps
CPU time 1.49 seconds
Started Aug 02 06:14:09 PM PDT 24
Finished Aug 02 06:14:11 PM PDT 24
Peak memory 206772 kb
Host smart-211f7797-e178-4264-820c-35b3942540ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147680485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1147680485
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2929538209
Short name T1087
Test name
Test status
Simulation time 283719778 ps
CPU time 1.3 seconds
Started Aug 02 06:14:21 PM PDT 24
Finished Aug 02 06:14:23 PM PDT 24
Peak memory 215028 kb
Host smart-60fc0a70-f1b0-4e09-964f-cfad3113e8c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929538209 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2929538209
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2374053127
Short name T1091
Test name
Test status
Simulation time 18524644 ps
CPU time 0.82 seconds
Started Aug 02 06:14:21 PM PDT 24
Finished Aug 02 06:14:22 PM PDT 24
Peak memory 206468 kb
Host smart-9d656bc5-ed43-4bb0-9740-88b381571f08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374053127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2374053127
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.957653546
Short name T1008
Test name
Test status
Simulation time 38607139 ps
CPU time 0.79 seconds
Started Aug 02 06:14:09 PM PDT 24
Finished Aug 02 06:14:10 PM PDT 24
Peak memory 206416 kb
Host smart-8868c84e-45d3-4aef-9074-ed3a94f0404e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957653546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.957653546
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1361760655
Short name T1093
Test name
Test status
Simulation time 181942233 ps
CPU time 1.14 seconds
Started Aug 02 06:14:20 PM PDT 24
Finished Aug 02 06:14:22 PM PDT 24
Peak memory 206764 kb
Host smart-cb6cb94b-c28e-49d1-8d03-3bdfa4f15e61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361760655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1361760655
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2205960841
Short name T1121
Test name
Test status
Simulation time 22759333 ps
CPU time 1.61 seconds
Started Aug 02 06:14:09 PM PDT 24
Finished Aug 02 06:14:10 PM PDT 24
Peak memory 223108 kb
Host smart-258d99dc-90c8-4339-a61f-eebffe3e4167
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205960841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2205960841
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2610958623
Short name T1057
Test name
Test status
Simulation time 43835904 ps
CPU time 1.56 seconds
Started Aug 02 06:14:09 PM PDT 24
Finished Aug 02 06:14:11 PM PDT 24
Peak memory 214996 kb
Host smart-2d295ef5-2eb8-49da-88bd-31afdacad5d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610958623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2610958623
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.177277683
Short name T1014
Test name
Test status
Simulation time 34809823 ps
CPU time 1.01 seconds
Started Aug 02 06:14:20 PM PDT 24
Finished Aug 02 06:14:21 PM PDT 24
Peak memory 206800 kb
Host smart-c33d48e3-5ddf-4e83-b020-6b3cae8af9e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177277683 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.177277683
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3266704186
Short name T1078
Test name
Test status
Simulation time 37877393 ps
CPU time 0.85 seconds
Started Aug 02 06:14:19 PM PDT 24
Finished Aug 02 06:14:20 PM PDT 24
Peak memory 206404 kb
Host smart-12979ccc-4f28-4eb1-9156-c30b97e89ad9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266704186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3266704186
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3548928052
Short name T1010
Test name
Test status
Simulation time 12677074 ps
CPU time 0.86 seconds
Started Aug 02 06:14:20 PM PDT 24
Finished Aug 02 06:14:21 PM PDT 24
Peak memory 206584 kb
Host smart-079f61bc-b21d-4bc8-95f7-5474eeda0f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548928052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3548928052
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2621234199
Short name T267
Test name
Test status
Simulation time 85196516 ps
CPU time 1.06 seconds
Started Aug 02 06:14:18 PM PDT 24
Finished Aug 02 06:14:20 PM PDT 24
Peak memory 206724 kb
Host smart-285a9684-84b2-4612-96c4-fdbb71a0dfed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621234199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2621234199
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2951959807
Short name T999
Test name
Test status
Simulation time 182739467 ps
CPU time 2.03 seconds
Started Aug 02 06:14:22 PM PDT 24
Finished Aug 02 06:14:24 PM PDT 24
Peak memory 214996 kb
Host smart-44c23dfa-7e57-4619-927e-f064017721b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951959807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2951959807
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3590910951
Short name T222
Test name
Test status
Simulation time 51852866 ps
CPU time 1.66 seconds
Started Aug 02 06:14:19 PM PDT 24
Finished Aug 02 06:14:21 PM PDT 24
Peak memory 206732 kb
Host smart-554c635f-e886-451b-af10-777373082381
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590910951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3590910951
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2288512378
Short name T995
Test name
Test status
Simulation time 47016809 ps
CPU time 1.5 seconds
Started Aug 02 06:14:24 PM PDT 24
Finished Aug 02 06:14:25 PM PDT 24
Peak memory 215008 kb
Host smart-50c87f55-eef3-4a05-8612-007f0c192742
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288512378 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2288512378
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.345215891
Short name T259
Test name
Test status
Simulation time 18159932 ps
CPU time 0.8 seconds
Started Aug 02 06:14:19 PM PDT 24
Finished Aug 02 06:14:20 PM PDT 24
Peak memory 206344 kb
Host smart-bb969577-1c7c-4aae-83b2-821e14916784
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345215891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.345215891
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.600477856
Short name T1052
Test name
Test status
Simulation time 23070745 ps
CPU time 0.86 seconds
Started Aug 02 06:14:19 PM PDT 24
Finished Aug 02 06:14:20 PM PDT 24
Peak memory 206620 kb
Host smart-55292f4a-68a2-482b-ac77-16889ab239ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600477856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.600477856
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1695124542
Short name T1079
Test name
Test status
Simulation time 108264890 ps
CPU time 1.41 seconds
Started Aug 02 06:14:18 PM PDT 24
Finished Aug 02 06:14:20 PM PDT 24
Peak memory 206696 kb
Host smart-2e12bd8f-8a7b-49f0-98ea-636234da2fa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695124542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1695124542
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.4206176009
Short name T1022
Test name
Test status
Simulation time 262777724 ps
CPU time 2.41 seconds
Started Aug 02 06:14:20 PM PDT 24
Finished Aug 02 06:14:22 PM PDT 24
Peak memory 215096 kb
Host smart-8615f496-9d22-4c34-9d73-4eda0b937862
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206176009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.4206176009
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4149053581
Short name T1071
Test name
Test status
Simulation time 21892513 ps
CPU time 1.24 seconds
Started Aug 02 06:14:18 PM PDT 24
Finished Aug 02 06:14:19 PM PDT 24
Peak memory 215192 kb
Host smart-14f0b88d-6a6b-4f5b-bf4e-da294c2573b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149053581 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.4149053581
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1655705407
Short name T256
Test name
Test status
Simulation time 19194161 ps
CPU time 1.03 seconds
Started Aug 02 06:14:19 PM PDT 24
Finished Aug 02 06:14:20 PM PDT 24
Peak memory 206628 kb
Host smart-2e2e7f10-8aa3-45d3-8772-be519798b9c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655705407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1655705407
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3247336669
Short name T1005
Test name
Test status
Simulation time 12273115 ps
CPU time 0.83 seconds
Started Aug 02 06:14:19 PM PDT 24
Finished Aug 02 06:14:20 PM PDT 24
Peak memory 206604 kb
Host smart-0255c2e1-c063-4512-b5d2-f5c264b6dda4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247336669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3247336669
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.772377996
Short name T1040
Test name
Test status
Simulation time 128776593 ps
CPU time 1.33 seconds
Started Aug 02 06:14:19 PM PDT 24
Finished Aug 02 06:14:20 PM PDT 24
Peak memory 206816 kb
Host smart-05607022-647e-4091-9126-20d1f742a901
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772377996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.772377996
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1751942564
Short name T1101
Test name
Test status
Simulation time 673174205 ps
CPU time 3.88 seconds
Started Aug 02 06:14:19 PM PDT 24
Finished Aug 02 06:14:23 PM PDT 24
Peak memory 215088 kb
Host smart-4fa86d08-f8be-4089-9729-135d0ea8478e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751942564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1751942564
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.83502498
Short name T221
Test name
Test status
Simulation time 159065247 ps
CPU time 1.63 seconds
Started Aug 02 06:14:21 PM PDT 24
Finished Aug 02 06:14:23 PM PDT 24
Peak memory 206772 kb
Host smart-319f6a5b-4a4f-4b69-927f-92dd67ba637f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83502498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.83502498
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1756055127
Short name T994
Test name
Test status
Simulation time 16069751 ps
CPU time 1.03 seconds
Started Aug 02 06:14:30 PM PDT 24
Finished Aug 02 06:14:31 PM PDT 24
Peak memory 206992 kb
Host smart-3c47566b-417e-48e2-a1ea-5f8598cc8bf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756055127 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1756055127
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1647421825
Short name T269
Test name
Test status
Simulation time 54043810 ps
CPU time 0.91 seconds
Started Aug 02 06:14:28 PM PDT 24
Finished Aug 02 06:14:29 PM PDT 24
Peak memory 206608 kb
Host smart-f89460cd-7a5b-4801-ae0c-0e095fe8aeec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647421825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1647421825
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2098797748
Short name T1000
Test name
Test status
Simulation time 30203494 ps
CPU time 0.79 seconds
Started Aug 02 06:14:29 PM PDT 24
Finished Aug 02 06:14:30 PM PDT 24
Peak memory 206436 kb
Host smart-6327f694-34b1-4a20-ae51-ba49cb16c588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098797748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2098797748
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1617079496
Short name T1049
Test name
Test status
Simulation time 56795060 ps
CPU time 0.96 seconds
Started Aug 02 06:14:30 PM PDT 24
Finished Aug 02 06:14:31 PM PDT 24
Peak memory 206736 kb
Host smart-1d17ffd3-aa13-4d26-81b4-5d2c6f4488a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617079496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1617079496
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3119751113
Short name T1070
Test name
Test status
Simulation time 28681407 ps
CPU time 1.76 seconds
Started Aug 02 06:14:21 PM PDT 24
Finished Aug 02 06:14:23 PM PDT 24
Peak memory 215076 kb
Host smart-f1df0caf-ea5b-4ea6-ba79-85175ac5dea2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119751113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3119751113
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2529483820
Short name T1120
Test name
Test status
Simulation time 19605627 ps
CPU time 1.13 seconds
Started Aug 02 06:14:37 PM PDT 24
Finished Aug 02 06:14:38 PM PDT 24
Peak memory 215028 kb
Host smart-d7ab7a0c-c53b-4000-b73f-4909877d03dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529483820 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2529483820
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1251901246
Short name T1108
Test name
Test status
Simulation time 13079719 ps
CPU time 0.91 seconds
Started Aug 02 06:14:42 PM PDT 24
Finished Aug 02 06:14:43 PM PDT 24
Peak memory 206608 kb
Host smart-0f1a7c41-9e8e-46f3-898b-304ad8243ed4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251901246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1251901246
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.18095393
Short name T1115
Test name
Test status
Simulation time 32013996 ps
CPU time 0.8 seconds
Started Aug 02 06:14:28 PM PDT 24
Finished Aug 02 06:14:29 PM PDT 24
Peak memory 206452 kb
Host smart-9d124d3f-27c5-4ba1-b3cb-bc957da8ecd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18095393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.18095393
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.4073035581
Short name T271
Test name
Test status
Simulation time 73293986 ps
CPU time 1.08 seconds
Started Aug 02 06:14:38 PM PDT 24
Finished Aug 02 06:14:40 PM PDT 24
Peak memory 206740 kb
Host smart-34513971-56f7-48c4-8cc4-2cd95beebfd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073035581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.4073035581
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1900020343
Short name T1026
Test name
Test status
Simulation time 401605401 ps
CPU time 4.07 seconds
Started Aug 02 06:14:28 PM PDT 24
Finished Aug 02 06:14:33 PM PDT 24
Peak memory 215080 kb
Host smart-14d86575-36c0-4cdb-9323-3db44026435b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900020343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1900020343
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1619196674
Short name T299
Test name
Test status
Simulation time 115018557 ps
CPU time 1.53 seconds
Started Aug 02 06:14:29 PM PDT 24
Finished Aug 02 06:14:31 PM PDT 24
Peak memory 206752 kb
Host smart-d9c0d7a2-dce7-484c-a619-e5ff658d0bd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619196674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1619196674
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2793391929
Short name T1089
Test name
Test status
Simulation time 93289262 ps
CPU time 2.14 seconds
Started Aug 02 06:14:39 PM PDT 24
Finished Aug 02 06:14:41 PM PDT 24
Peak memory 215044 kb
Host smart-84ef5c20-f4b2-4811-b597-24447e597864
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793391929 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2793391929
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2367704823
Short name T1035
Test name
Test status
Simulation time 66958771 ps
CPU time 0.85 seconds
Started Aug 02 06:14:38 PM PDT 24
Finished Aug 02 06:14:39 PM PDT 24
Peak memory 206392 kb
Host smart-fa6c6623-e472-4c1c-bbbb-0f1e54084e87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367704823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2367704823
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1119906687
Short name T1030
Test name
Test status
Simulation time 37805069 ps
CPU time 0.83 seconds
Started Aug 02 06:14:42 PM PDT 24
Finished Aug 02 06:14:43 PM PDT 24
Peak memory 206348 kb
Host smart-43d4faf3-1788-4cf9-b57f-8b77f88110e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119906687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1119906687
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3305495713
Short name T1103
Test name
Test status
Simulation time 87203867 ps
CPU time 1.13 seconds
Started Aug 02 06:14:40 PM PDT 24
Finished Aug 02 06:14:41 PM PDT 24
Peak memory 206756 kb
Host smart-5dc5b16e-4f45-4a8c-8aba-1ff34c85492e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305495713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3305495713
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1232786412
Short name T1102
Test name
Test status
Simulation time 64782624 ps
CPU time 2.44 seconds
Started Aug 02 06:14:39 PM PDT 24
Finished Aug 02 06:14:41 PM PDT 24
Peak memory 215004 kb
Host smart-d0ef3fb5-b5f1-4e6f-b151-1b2d051b6f3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232786412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1232786412
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3495578544
Short name T1065
Test name
Test status
Simulation time 120084515 ps
CPU time 2.1 seconds
Started Aug 02 06:14:39 PM PDT 24
Finished Aug 02 06:14:41 PM PDT 24
Peak memory 214992 kb
Host smart-9df0c5df-aba2-4c63-8841-3f5f6d093521
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495578544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3495578544
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3660264311
Short name T1012
Test name
Test status
Simulation time 40573915 ps
CPU time 1.11 seconds
Started Aug 02 06:14:40 PM PDT 24
Finished Aug 02 06:14:41 PM PDT 24
Peak memory 223080 kb
Host smart-4ac2f289-071d-4937-87e2-d5357e654e52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660264311 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3660264311
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.246058005
Short name T1032
Test name
Test status
Simulation time 21994524 ps
CPU time 0.85 seconds
Started Aug 02 06:14:39 PM PDT 24
Finished Aug 02 06:14:40 PM PDT 24
Peak memory 206568 kb
Host smart-f7100aa1-cd97-4a33-a9f4-5da6f7cbf4aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246058005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.246058005
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1265829026
Short name T1027
Test name
Test status
Simulation time 44283029 ps
CPU time 0.82 seconds
Started Aug 02 06:14:40 PM PDT 24
Finished Aug 02 06:14:41 PM PDT 24
Peak memory 206516 kb
Host smart-3e5332a6-2f70-450a-847e-3db6ce1b54f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265829026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1265829026
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4260763045
Short name T273
Test name
Test status
Simulation time 19290129 ps
CPU time 1.09 seconds
Started Aug 02 06:14:38 PM PDT 24
Finished Aug 02 06:14:39 PM PDT 24
Peak memory 206792 kb
Host smart-47259446-61aa-4f24-b371-13d0fec7a505
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260763045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.4260763045
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.955858255
Short name T1043
Test name
Test status
Simulation time 63606418 ps
CPU time 1.91 seconds
Started Aug 02 06:14:39 PM PDT 24
Finished Aug 02 06:14:41 PM PDT 24
Peak memory 214984 kb
Host smart-f0171840-43ea-43de-b549-6ac3ed32f81d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955858255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.955858255
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1742951358
Short name T297
Test name
Test status
Simulation time 76179101 ps
CPU time 2.27 seconds
Started Aug 02 06:14:38 PM PDT 24
Finished Aug 02 06:14:40 PM PDT 24
Peak memory 206848 kb
Host smart-2a8a953e-4d80-4b2d-ba0a-af0f883c773a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742951358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1742951358
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.581719972
Short name T255
Test name
Test status
Simulation time 24996654 ps
CPU time 1.24 seconds
Started Aug 02 06:13:12 PM PDT 24
Finished Aug 02 06:13:13 PM PDT 24
Peak memory 206648 kb
Host smart-09c04870-4471-4a3a-aa16-69ac996ea8fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581719972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.581719972
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.274777338
Short name T1088
Test name
Test status
Simulation time 96745011 ps
CPU time 3.1 seconds
Started Aug 02 06:13:13 PM PDT 24
Finished Aug 02 06:13:16 PM PDT 24
Peak memory 206600 kb
Host smart-aa9b8aa6-bba2-4397-a29c-c8290b4b730b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274777338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.274777338
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.372505435
Short name T1118
Test name
Test status
Simulation time 25882885 ps
CPU time 0.86 seconds
Started Aug 02 06:13:12 PM PDT 24
Finished Aug 02 06:13:13 PM PDT 24
Peak memory 206620 kb
Host smart-f823408b-051f-45f6-804a-16bcf63c5892
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372505435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.372505435
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2720911444
Short name T993
Test name
Test status
Simulation time 126522766 ps
CPU time 1.15 seconds
Started Aug 02 06:13:13 PM PDT 24
Finished Aug 02 06:13:14 PM PDT 24
Peak memory 214984 kb
Host smart-1392302f-41b1-48af-bfd9-5379afb5d8b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720911444 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2720911444
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1098903505
Short name T264
Test name
Test status
Simulation time 13209298 ps
CPU time 0.86 seconds
Started Aug 02 06:13:12 PM PDT 24
Finished Aug 02 06:13:13 PM PDT 24
Peak memory 206400 kb
Host smart-28d0a75c-b057-4aae-8903-ca2a1f1d1bf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098903505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1098903505
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.506818620
Short name T1045
Test name
Test status
Simulation time 20877270 ps
CPU time 0.85 seconds
Started Aug 02 06:13:02 PM PDT 24
Finished Aug 02 06:13:03 PM PDT 24
Peak memory 206624 kb
Host smart-709580dd-f933-46c0-8e1c-107cf3373922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506818620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.506818620
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1002751337
Short name T1082
Test name
Test status
Simulation time 29886312 ps
CPU time 1.14 seconds
Started Aug 02 06:13:11 PM PDT 24
Finished Aug 02 06:13:13 PM PDT 24
Peak memory 206728 kb
Host smart-c6aa272b-173a-4e9b-806d-1d997405c30d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002751337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1002751337
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1325667247
Short name T1020
Test name
Test status
Simulation time 295111923 ps
CPU time 2.84 seconds
Started Aug 02 06:13:04 PM PDT 24
Finished Aug 02 06:13:07 PM PDT 24
Peak memory 215000 kb
Host smart-b5866ead-b95a-4268-b11f-3d433f7d0df0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325667247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1325667247
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1985946909
Short name T1124
Test name
Test status
Simulation time 127346115 ps
CPU time 1.84 seconds
Started Aug 02 06:13:05 PM PDT 24
Finished Aug 02 06:13:07 PM PDT 24
Peak memory 206832 kb
Host smart-dc20120a-4a43-4b8a-ad56-4eb9a6ba1469
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985946909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1985946909
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.163702071
Short name T1099
Test name
Test status
Simulation time 24561051 ps
CPU time 0.88 seconds
Started Aug 02 06:14:39 PM PDT 24
Finished Aug 02 06:14:40 PM PDT 24
Peak memory 206612 kb
Host smart-a236b858-c245-4ed5-871d-c141f0c37f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163702071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.163702071
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2478076882
Short name T1097
Test name
Test status
Simulation time 16309903 ps
CPU time 0.81 seconds
Started Aug 02 06:14:40 PM PDT 24
Finished Aug 02 06:14:41 PM PDT 24
Peak memory 206424 kb
Host smart-c4e77c00-ea0c-4ece-945d-d41562bc67ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478076882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2478076882
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.179530721
Short name T1016
Test name
Test status
Simulation time 32025673 ps
CPU time 0.84 seconds
Started Aug 02 06:14:39 PM PDT 24
Finished Aug 02 06:14:40 PM PDT 24
Peak memory 206448 kb
Host smart-ac3a1734-b327-465b-8060-9f09ef9dd993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179530721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.179530721
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.801235759
Short name T1058
Test name
Test status
Simulation time 12140133 ps
CPU time 0.86 seconds
Started Aug 02 06:14:47 PM PDT 24
Finished Aug 02 06:14:48 PM PDT 24
Peak memory 206604 kb
Host smart-c3de950c-48e0-457f-851f-8f10d35c9fac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801235759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.801235759
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.177861140
Short name T1066
Test name
Test status
Simulation time 13045911 ps
CPU time 0.83 seconds
Started Aug 02 06:14:47 PM PDT 24
Finished Aug 02 06:14:48 PM PDT 24
Peak memory 206428 kb
Host smart-36a869e6-8744-47cd-9374-37877cb9574c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177861140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.177861140
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1434799387
Short name T1038
Test name
Test status
Simulation time 36133924 ps
CPU time 0.78 seconds
Started Aug 02 06:14:47 PM PDT 24
Finished Aug 02 06:14:48 PM PDT 24
Peak memory 206416 kb
Host smart-3fd786f0-5baa-41c7-a11d-d27f07920948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434799387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1434799387
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3880121941
Short name T1084
Test name
Test status
Simulation time 113079663 ps
CPU time 0.93 seconds
Started Aug 02 06:14:49 PM PDT 24
Finished Aug 02 06:14:50 PM PDT 24
Peak memory 206560 kb
Host smart-bd8cef80-58e0-4c64-96e0-c529ff7fef17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880121941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3880121941
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3007237748
Short name T1055
Test name
Test status
Simulation time 13279752 ps
CPU time 0.88 seconds
Started Aug 02 06:14:49 PM PDT 24
Finished Aug 02 06:14:50 PM PDT 24
Peak memory 206604 kb
Host smart-26e56477-8169-462d-8215-3796ee21872c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007237748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3007237748
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3423808939
Short name T1011
Test name
Test status
Simulation time 13119805 ps
CPU time 0.9 seconds
Started Aug 02 06:14:48 PM PDT 24
Finished Aug 02 06:14:49 PM PDT 24
Peak memory 206584 kb
Host smart-dc84cda9-ab61-4af0-a8b1-78a3a2633b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423808939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3423808939
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1588051966
Short name T1077
Test name
Test status
Simulation time 30566962 ps
CPU time 0.79 seconds
Started Aug 02 06:14:47 PM PDT 24
Finished Aug 02 06:14:48 PM PDT 24
Peak memory 206476 kb
Host smart-8268edb3-5145-4273-8fe3-1de5af6e842d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588051966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1588051966
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1493560439
Short name T1003
Test name
Test status
Simulation time 103239064 ps
CPU time 1.2 seconds
Started Aug 02 06:13:20 PM PDT 24
Finished Aug 02 06:13:21 PM PDT 24
Peak memory 206696 kb
Host smart-cbc822e4-a2b5-4883-9738-795c2954133f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493560439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1493560439
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.416761018
Short name T1075
Test name
Test status
Simulation time 225508815 ps
CPU time 3.23 seconds
Started Aug 02 06:13:20 PM PDT 24
Finished Aug 02 06:13:24 PM PDT 24
Peak memory 206640 kb
Host smart-ec8e00e3-dd9c-4b9a-b538-003e6a95ed5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416761018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.416761018
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2942056426
Short name T257
Test name
Test status
Simulation time 46326133 ps
CPU time 0.88 seconds
Started Aug 02 06:13:21 PM PDT 24
Finished Aug 02 06:13:22 PM PDT 24
Peak memory 206604 kb
Host smart-1e486e15-b208-4ef6-aa56-d9976ab3dab8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942056426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2942056426
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3005314354
Short name T1054
Test name
Test status
Simulation time 22248969 ps
CPU time 1.53 seconds
Started Aug 02 06:13:21 PM PDT 24
Finished Aug 02 06:13:23 PM PDT 24
Peak memory 215060 kb
Host smart-1b0792d5-9079-49ee-af9a-8271c3e53e2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005314354 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3005314354
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2611379847
Short name T260
Test name
Test status
Simulation time 91934159 ps
CPU time 0.85 seconds
Started Aug 02 06:13:19 PM PDT 24
Finished Aug 02 06:13:20 PM PDT 24
Peak memory 206624 kb
Host smart-23482cb0-a79e-4584-8013-5d2e5901dacf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611379847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2611379847
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2035665975
Short name T1059
Test name
Test status
Simulation time 15357281 ps
CPU time 0.94 seconds
Started Aug 02 06:13:12 PM PDT 24
Finished Aug 02 06:13:13 PM PDT 24
Peak memory 206592 kb
Host smart-ce823cff-fe47-4d86-9e70-05cef9768f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035665975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2035665975
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1141070502
Short name T1113
Test name
Test status
Simulation time 21585358 ps
CPU time 1.12 seconds
Started Aug 02 06:13:19 PM PDT 24
Finished Aug 02 06:13:21 PM PDT 24
Peak memory 206752 kb
Host smart-bd92f63b-31ec-4c8d-9b70-cbbd9e07e8d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141070502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1141070502
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1196472500
Short name T1076
Test name
Test status
Simulation time 192102335 ps
CPU time 2.6 seconds
Started Aug 02 06:13:13 PM PDT 24
Finished Aug 02 06:13:16 PM PDT 24
Peak memory 214968 kb
Host smart-ef9c8eb2-7029-469b-8738-e8b9ae9dff88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196472500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1196472500
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3179216496
Short name T1067
Test name
Test status
Simulation time 146893774 ps
CPU time 2.31 seconds
Started Aug 02 06:13:12 PM PDT 24
Finished Aug 02 06:13:15 PM PDT 24
Peak memory 206808 kb
Host smart-c4203316-6250-4ec6-98b6-8a708b054d62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179216496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3179216496
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3699376049
Short name T1063
Test name
Test status
Simulation time 16318244 ps
CPU time 0.9 seconds
Started Aug 02 06:14:47 PM PDT 24
Finished Aug 02 06:14:48 PM PDT 24
Peak memory 206596 kb
Host smart-eb6fa213-1ffe-41ad-9470-9d14d625c408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699376049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3699376049
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.394213208
Short name T1018
Test name
Test status
Simulation time 41008470 ps
CPU time 0.79 seconds
Started Aug 02 06:14:47 PM PDT 24
Finished Aug 02 06:14:48 PM PDT 24
Peak memory 206392 kb
Host smart-2eb222ce-c5af-4e6a-bda1-8368aa4bf22c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394213208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.394213208
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1852191651
Short name T1068
Test name
Test status
Simulation time 111826522 ps
CPU time 0.93 seconds
Started Aug 02 06:14:50 PM PDT 24
Finished Aug 02 06:14:51 PM PDT 24
Peak memory 206596 kb
Host smart-6841172e-f72e-4fe8-a312-e923bad72978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852191651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1852191651
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3682570650
Short name T1098
Test name
Test status
Simulation time 81191300 ps
CPU time 0.83 seconds
Started Aug 02 06:14:48 PM PDT 24
Finished Aug 02 06:14:49 PM PDT 24
Peak memory 206420 kb
Host smart-dedbc1e1-c1b1-4084-a179-fe896dc5fd1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682570650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3682570650
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3867017589
Short name T1006
Test name
Test status
Simulation time 18458813 ps
CPU time 0.82 seconds
Started Aug 02 06:14:48 PM PDT 24
Finished Aug 02 06:14:49 PM PDT 24
Peak memory 206604 kb
Host smart-a1e7dbf5-d011-4567-91c4-371e8bed8698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867017589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3867017589
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.811380840
Short name T1034
Test name
Test status
Simulation time 19664169 ps
CPU time 0.86 seconds
Started Aug 02 06:14:48 PM PDT 24
Finished Aug 02 06:14:49 PM PDT 24
Peak memory 206632 kb
Host smart-98e8a0fd-10f6-4df1-aa8f-4f82a21509ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811380840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.811380840
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3325301583
Short name T1051
Test name
Test status
Simulation time 15279845 ps
CPU time 0.89 seconds
Started Aug 02 06:15:05 PM PDT 24
Finished Aug 02 06:15:06 PM PDT 24
Peak memory 206684 kb
Host smart-21e81b28-3da1-48fa-b413-000cb40c7f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325301583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3325301583
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3017860776
Short name T1122
Test name
Test status
Simulation time 12901381 ps
CPU time 0.84 seconds
Started Aug 02 06:15:00 PM PDT 24
Finished Aug 02 06:15:01 PM PDT 24
Peak memory 206584 kb
Host smart-db2a9652-2bb7-4e14-9c57-a443ebc386a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017860776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3017860776
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1583405933
Short name T1117
Test name
Test status
Simulation time 13443534 ps
CPU time 0.89 seconds
Started Aug 02 06:14:58 PM PDT 24
Finished Aug 02 06:14:59 PM PDT 24
Peak memory 206596 kb
Host smart-54746091-e233-49b3-be3f-5b0449c82056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583405933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1583405933
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.849307871
Short name T1048
Test name
Test status
Simulation time 12144095 ps
CPU time 0.84 seconds
Started Aug 02 06:15:00 PM PDT 24
Finished Aug 02 06:15:01 PM PDT 24
Peak memory 206608 kb
Host smart-7c5da6ee-ee7a-4ac4-b42f-16a02dbda915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849307871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.849307871
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1638072528
Short name T266
Test name
Test status
Simulation time 58660093 ps
CPU time 1.04 seconds
Started Aug 02 06:13:27 PM PDT 24
Finished Aug 02 06:13:28 PM PDT 24
Peak memory 206688 kb
Host smart-a35485ec-4e05-4c58-b00d-ce2cd54f83b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638072528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1638072528
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3023249070
Short name T991
Test name
Test status
Simulation time 44832202 ps
CPU time 2.06 seconds
Started Aug 02 06:13:28 PM PDT 24
Finished Aug 02 06:13:30 PM PDT 24
Peak memory 206680 kb
Host smart-72d3e2fd-a212-4916-9377-0dd902da1f75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023249070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3023249070
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.124943034
Short name T262
Test name
Test status
Simulation time 49138858 ps
CPU time 0.88 seconds
Started Aug 02 06:13:28 PM PDT 24
Finished Aug 02 06:13:29 PM PDT 24
Peak memory 206616 kb
Host smart-bfe714be-94a2-48c5-a28b-171424223fe6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124943034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.124943034
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1069287938
Short name T1028
Test name
Test status
Simulation time 69211965 ps
CPU time 1.16 seconds
Started Aug 02 06:13:27 PM PDT 24
Finished Aug 02 06:13:29 PM PDT 24
Peak memory 215004 kb
Host smart-1a9aa1b2-dbf7-4c69-b306-9e0615f5c44f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069287938 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1069287938
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.490219150
Short name T1046
Test name
Test status
Simulation time 44391475 ps
CPU time 0.86 seconds
Started Aug 02 06:13:29 PM PDT 24
Finished Aug 02 06:13:30 PM PDT 24
Peak memory 206540 kb
Host smart-06c431c0-bcc7-42a0-afab-820dcf85b0a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490219150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.490219150
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1981552881
Short name T997
Test name
Test status
Simulation time 15209242 ps
CPU time 0.82 seconds
Started Aug 02 06:13:30 PM PDT 24
Finished Aug 02 06:13:31 PM PDT 24
Peak memory 206432 kb
Host smart-ab071ffa-7169-4f5a-8e4e-d96152a74262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981552881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1981552881
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3484806347
Short name T272
Test name
Test status
Simulation time 177523214 ps
CPU time 1.03 seconds
Started Aug 02 06:13:28 PM PDT 24
Finished Aug 02 06:13:30 PM PDT 24
Peak memory 206784 kb
Host smart-acd5ad2d-b052-4282-ac6f-f3541505c4f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484806347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3484806347
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1670816249
Short name T1036
Test name
Test status
Simulation time 170081066 ps
CPU time 3.16 seconds
Started Aug 02 06:13:28 PM PDT 24
Finished Aug 02 06:13:31 PM PDT 24
Peak memory 215052 kb
Host smart-a8aa4b28-fe7a-4f9f-940b-af809fc573b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670816249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1670816249
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2286569163
Short name T293
Test name
Test status
Simulation time 86149877 ps
CPU time 2.44 seconds
Started Aug 02 06:13:27 PM PDT 24
Finished Aug 02 06:13:30 PM PDT 24
Peak memory 206968 kb
Host smart-19e6c684-624a-4dbb-a1d5-b1d396b56a0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286569163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2286569163
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3371089817
Short name T1114
Test name
Test status
Simulation time 17529422 ps
CPU time 0.97 seconds
Started Aug 02 06:15:06 PM PDT 24
Finished Aug 02 06:15:08 PM PDT 24
Peak memory 206604 kb
Host smart-2963a1f6-b7cc-429d-98b0-0c3010aa4676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371089817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3371089817
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1545377240
Short name T1123
Test name
Test status
Simulation time 17958898 ps
CPU time 0.84 seconds
Started Aug 02 06:15:00 PM PDT 24
Finished Aug 02 06:15:01 PM PDT 24
Peak memory 206432 kb
Host smart-855b5f8e-56ac-4189-a974-2f6ce1ab60ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545377240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1545377240
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.387388978
Short name T1029
Test name
Test status
Simulation time 44176194 ps
CPU time 0.83 seconds
Started Aug 02 06:14:59 PM PDT 24
Finished Aug 02 06:15:00 PM PDT 24
Peak memory 206644 kb
Host smart-86f5d64b-056a-4090-b2b5-170c40a4b5d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387388978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.387388978
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1101108294
Short name T1083
Test name
Test status
Simulation time 124442408 ps
CPU time 1 seconds
Started Aug 02 06:15:00 PM PDT 24
Finished Aug 02 06:15:01 PM PDT 24
Peak memory 206588 kb
Host smart-94bf316a-745c-4640-b709-d8d6c71daeba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101108294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1101108294
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.42216694
Short name T1092
Test name
Test status
Simulation time 39551723 ps
CPU time 0.8 seconds
Started Aug 02 06:15:00 PM PDT 24
Finished Aug 02 06:15:01 PM PDT 24
Peak memory 206428 kb
Host smart-bf4ec29d-53b1-4d9f-a661-03f1043321a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42216694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.42216694
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1847800589
Short name T1023
Test name
Test status
Simulation time 39913776 ps
CPU time 0.85 seconds
Started Aug 02 06:15:08 PM PDT 24
Finished Aug 02 06:15:09 PM PDT 24
Peak memory 206588 kb
Host smart-3758de9e-12fd-4529-8923-03debb58d061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847800589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1847800589
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1467447965
Short name T1021
Test name
Test status
Simulation time 15551119 ps
CPU time 0.91 seconds
Started Aug 02 06:15:00 PM PDT 24
Finished Aug 02 06:15:01 PM PDT 24
Peak memory 206544 kb
Host smart-e77900e9-1507-43fe-892b-3138fd32d35a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467447965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1467447965
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.641467559
Short name T992
Test name
Test status
Simulation time 34101760 ps
CPU time 0.79 seconds
Started Aug 02 06:14:58 PM PDT 24
Finished Aug 02 06:14:59 PM PDT 24
Peak memory 206440 kb
Host smart-4d1d46fb-eb05-446a-9e77-f47a8f341bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641467559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.641467559
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3392523877
Short name T1015
Test name
Test status
Simulation time 15678388 ps
CPU time 0.98 seconds
Started Aug 02 06:15:06 PM PDT 24
Finished Aug 02 06:15:07 PM PDT 24
Peak memory 206592 kb
Host smart-b345bea1-759f-42db-86eb-b880bc9f21fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392523877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3392523877
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3945423916
Short name T1112
Test name
Test status
Simulation time 62399177 ps
CPU time 0.86 seconds
Started Aug 02 06:15:06 PM PDT 24
Finished Aug 02 06:15:07 PM PDT 24
Peak memory 206620 kb
Host smart-3652699b-ffaf-420e-b73b-71e1453a8241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945423916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3945423916
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3833536859
Short name T1031
Test name
Test status
Simulation time 32167543 ps
CPU time 1.44 seconds
Started Aug 02 06:13:35 PM PDT 24
Finished Aug 02 06:13:37 PM PDT 24
Peak memory 215036 kb
Host smart-ab93a45c-9dc9-45e3-a566-65954a8ee48b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833536859 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3833536859
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.39226884
Short name T263
Test name
Test status
Simulation time 12666926 ps
CPU time 0.88 seconds
Started Aug 02 06:13:37 PM PDT 24
Finished Aug 02 06:13:38 PM PDT 24
Peak memory 206600 kb
Host smart-2ad0ab29-f00c-48ca-8a18-6b3be3943511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39226884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.39226884
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2952225701
Short name T1107
Test name
Test status
Simulation time 20938616 ps
CPU time 0.8 seconds
Started Aug 02 06:13:39 PM PDT 24
Finished Aug 02 06:13:39 PM PDT 24
Peak memory 206608 kb
Host smart-643848a7-6840-4d9f-a228-be0f955d53a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952225701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2952225701
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1481218620
Short name T268
Test name
Test status
Simulation time 76445886 ps
CPU time 1.32 seconds
Started Aug 02 06:13:36 PM PDT 24
Finished Aug 02 06:13:37 PM PDT 24
Peak memory 206756 kb
Host smart-87ffa3b8-7e7f-4135-9331-1c0f32d1a07c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481218620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1481218620
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3381463811
Short name T1105
Test name
Test status
Simulation time 133717265 ps
CPU time 3.03 seconds
Started Aug 02 06:13:37 PM PDT 24
Finished Aug 02 06:13:40 PM PDT 24
Peak memory 215060 kb
Host smart-65b4793b-4257-49dc-8067-1e336a331299
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381463811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3381463811
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2384326731
Short name T1039
Test name
Test status
Simulation time 80530630 ps
CPU time 2.22 seconds
Started Aug 02 06:13:38 PM PDT 24
Finished Aug 02 06:13:40 PM PDT 24
Peak memory 206784 kb
Host smart-9528a589-c654-4263-b509-24007fd568a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384326731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2384326731
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.600854888
Short name T998
Test name
Test status
Simulation time 27529415 ps
CPU time 1.32 seconds
Started Aug 02 06:13:38 PM PDT 24
Finished Aug 02 06:13:40 PM PDT 24
Peak memory 217576 kb
Host smart-ef7d023a-337d-4190-9902-13cf6a8958cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600854888 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.600854888
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3425567646
Short name T1111
Test name
Test status
Simulation time 37714618 ps
CPU time 0.88 seconds
Started Aug 02 06:13:37 PM PDT 24
Finished Aug 02 06:13:37 PM PDT 24
Peak memory 206572 kb
Host smart-2969bd55-459f-42f8-b839-d553dea69a1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425567646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3425567646
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3912356474
Short name T1013
Test name
Test status
Simulation time 11442275 ps
CPU time 0.85 seconds
Started Aug 02 06:13:38 PM PDT 24
Finished Aug 02 06:13:39 PM PDT 24
Peak memory 206612 kb
Host smart-6c5d9acd-ffe7-4d19-a4a1-2106dd48392a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912356474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3912356474
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1944472878
Short name T1042
Test name
Test status
Simulation time 26259098 ps
CPU time 0.95 seconds
Started Aug 02 06:13:40 PM PDT 24
Finished Aug 02 06:13:41 PM PDT 24
Peak memory 206756 kb
Host smart-67d14638-e477-4bdd-87fe-42b9563a8e88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944472878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1944472878
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2238471859
Short name T1002
Test name
Test status
Simulation time 253430859 ps
CPU time 4.66 seconds
Started Aug 02 06:13:38 PM PDT 24
Finished Aug 02 06:13:43 PM PDT 24
Peak memory 219236 kb
Host smart-dc4f2e75-3dc5-42ab-8411-eae6bc214c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238471859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2238471859
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.4223089819
Short name T1100
Test name
Test status
Simulation time 34054396 ps
CPU time 1.24 seconds
Started Aug 02 06:13:46 PM PDT 24
Finished Aug 02 06:13:47 PM PDT 24
Peak memory 215196 kb
Host smart-9a70ab24-4479-4fb9-a337-db796ff1c318
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223089819 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.4223089819
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2627747645
Short name T1096
Test name
Test status
Simulation time 41908344 ps
CPU time 0.93 seconds
Started Aug 02 06:13:46 PM PDT 24
Finished Aug 02 06:13:47 PM PDT 24
Peak memory 206648 kb
Host smart-cc67e708-3994-4bd4-957b-4aac40340a27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627747645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2627747645
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2277241182
Short name T1056
Test name
Test status
Simulation time 32084012 ps
CPU time 0.9 seconds
Started Aug 02 06:13:46 PM PDT 24
Finished Aug 02 06:13:47 PM PDT 24
Peak memory 206596 kb
Host smart-ab50673f-0843-4891-a640-31e5896b63bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277241182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2277241182
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2546657952
Short name T1085
Test name
Test status
Simulation time 175974446 ps
CPU time 1.26 seconds
Started Aug 02 06:13:46 PM PDT 24
Finished Aug 02 06:13:47 PM PDT 24
Peak memory 206776 kb
Host smart-256bfd30-cec0-4bee-97a3-75de2e7e5fdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546657952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2546657952
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2019137035
Short name T1019
Test name
Test status
Simulation time 54170535 ps
CPU time 2.01 seconds
Started Aug 02 06:13:46 PM PDT 24
Finished Aug 02 06:13:48 PM PDT 24
Peak memory 215008 kb
Host smart-25b451a3-2a5f-4290-b330-cff2fed37ff8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019137035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2019137035
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.46354977
Short name T300
Test name
Test status
Simulation time 164503220 ps
CPU time 3.56 seconds
Started Aug 02 06:13:47 PM PDT 24
Finished Aug 02 06:13:50 PM PDT 24
Peak memory 206728 kb
Host smart-8004cc64-f920-48a8-89f6-751075070567
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46354977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.46354977
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3243625018
Short name T1062
Test name
Test status
Simulation time 155607779 ps
CPU time 1.51 seconds
Started Aug 02 06:13:52 PM PDT 24
Finished Aug 02 06:13:54 PM PDT 24
Peak memory 215028 kb
Host smart-096b3662-2c7b-4bd9-bcf7-65d8375d0cc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243625018 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3243625018
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1804755120
Short name T1025
Test name
Test status
Simulation time 24003248 ps
CPU time 0.87 seconds
Started Aug 02 06:13:54 PM PDT 24
Finished Aug 02 06:13:55 PM PDT 24
Peak memory 206548 kb
Host smart-3fc8b7db-9346-4264-a996-0fc8949366b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804755120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1804755120
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1321552265
Short name T1106
Test name
Test status
Simulation time 33910964 ps
CPU time 0.82 seconds
Started Aug 02 06:13:55 PM PDT 24
Finished Aug 02 06:13:56 PM PDT 24
Peak memory 206448 kb
Host smart-17cd0db4-79c8-4416-8e82-043755a78192
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321552265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1321552265
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1248752886
Short name T270
Test name
Test status
Simulation time 70828742 ps
CPU time 1.03 seconds
Started Aug 02 06:13:54 PM PDT 24
Finished Aug 02 06:13:55 PM PDT 24
Peak memory 206788 kb
Host smart-8805620d-d3af-48c1-b9de-a131f88545ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248752886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1248752886
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3108277473
Short name T1081
Test name
Test status
Simulation time 64146695 ps
CPU time 2.27 seconds
Started Aug 02 06:13:44 PM PDT 24
Finished Aug 02 06:13:47 PM PDT 24
Peak memory 215084 kb
Host smart-3496ee46-7ce8-4f78-a0af-813f3b5ce063
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108277473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3108277473
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4157138158
Short name T1086
Test name
Test status
Simulation time 411814490 ps
CPU time 2.3 seconds
Started Aug 02 06:13:53 PM PDT 24
Finished Aug 02 06:13:56 PM PDT 24
Peak memory 206704 kb
Host smart-ee77ac4e-2f4d-4cbf-854a-67652bf0951b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157138158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.4157138158
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2202113162
Short name T1053
Test name
Test status
Simulation time 27035515 ps
CPU time 1.59 seconds
Started Aug 02 06:13:56 PM PDT 24
Finished Aug 02 06:13:57 PM PDT 24
Peak memory 215056 kb
Host smart-9e938604-608e-4119-af76-0aab95da57ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202113162 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2202113162
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1398219103
Short name T1047
Test name
Test status
Simulation time 21877105 ps
CPU time 0.82 seconds
Started Aug 02 06:13:54 PM PDT 24
Finished Aug 02 06:13:55 PM PDT 24
Peak memory 206556 kb
Host smart-8e2ae0be-c690-446d-9051-514f77f3eff4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398219103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1398219103
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2390690810
Short name T1033
Test name
Test status
Simulation time 12568762 ps
CPU time 0.85 seconds
Started Aug 02 06:13:55 PM PDT 24
Finished Aug 02 06:13:56 PM PDT 24
Peak memory 206588 kb
Host smart-9279565c-3303-4385-a455-bad6cec650c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390690810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2390690810
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.534708334
Short name T1109
Test name
Test status
Simulation time 21953251 ps
CPU time 1.05 seconds
Started Aug 02 06:13:53 PM PDT 24
Finished Aug 02 06:13:54 PM PDT 24
Peak memory 206836 kb
Host smart-fc71c991-d28c-4851-a946-81ad76d1cf73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534708334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.534708334
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2818149618
Short name T1041
Test name
Test status
Simulation time 83380369 ps
CPU time 2.14 seconds
Started Aug 02 06:13:55 PM PDT 24
Finished Aug 02 06:13:57 PM PDT 24
Peak memory 214968 kb
Host smart-066321b7-b63a-4cd2-80b4-4b88d713cdff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818149618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2818149618
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1961892898
Short name T223
Test name
Test status
Simulation time 45794772 ps
CPU time 1.68 seconds
Started Aug 02 06:13:55 PM PDT 24
Finished Aug 02 06:13:56 PM PDT 24
Peak memory 207144 kb
Host smart-c381c071-aa95-4358-a2c9-f694f5817e6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961892898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1961892898
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_disable.938853626
Short name T207
Test name
Test status
Simulation time 23158880 ps
CPU time 0.9 seconds
Started Aug 02 06:39:47 PM PDT 24
Finished Aug 02 06:39:48 PM PDT 24
Peak memory 216232 kb
Host smart-5f8cdd60-95f6-4239-9a3f-f80b7a25362b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938853626 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.938853626
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.1928961
Short name T172
Test name
Test status
Simulation time 25631615 ps
CPU time 1.03 seconds
Started Aug 02 06:39:49 PM PDT 24
Finished Aug 02 06:39:50 PM PDT 24
Peak memory 219720 kb
Host smart-d304032d-6053-4258-b5c9-0a3e696e2dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1928961
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1127856911
Short name T902
Test name
Test status
Simulation time 99444596 ps
CPU time 1.59 seconds
Started Aug 02 06:39:51 PM PDT 24
Finished Aug 02 06:39:53 PM PDT 24
Peak memory 219092 kb
Host smart-838da3db-906b-4afe-b3fa-bda7af537cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127856911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1127856911
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2044886857
Short name T872
Test name
Test status
Simulation time 26276701 ps
CPU time 1.1 seconds
Started Aug 02 06:39:47 PM PDT 24
Finished Aug 02 06:39:48 PM PDT 24
Peak memory 215540 kb
Host smart-79ad3c2f-8678-4e1a-a31b-5f82b5b5c3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044886857 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2044886857
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1795661527
Short name T80
Test name
Test status
Simulation time 17344006 ps
CPU time 1.02 seconds
Started Aug 02 06:39:48 PM PDT 24
Finished Aug 02 06:39:49 PM PDT 24
Peak memory 207092 kb
Host smart-1fbee00c-2d03-41b8-996c-fdef5d589e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795661527 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1795661527
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.1072027577
Short name T888
Test name
Test status
Simulation time 16091234 ps
CPU time 0.99 seconds
Started Aug 02 06:39:39 PM PDT 24
Finished Aug 02 06:39:40 PM PDT 24
Peak memory 215292 kb
Host smart-27720a7d-133e-458a-9cd6-0abd08fed86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072027577 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1072027577
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1886597842
Short name T36
Test name
Test status
Simulation time 421677632 ps
CPU time 7.94 seconds
Started Aug 02 06:39:46 PM PDT 24
Finished Aug 02 06:39:54 PM PDT 24
Peak memory 215380 kb
Host smart-a57c247f-97e9-43df-a41f-ef76ef0b9ca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886597842 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1886597842
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.697769861
Short name T415
Test name
Test status
Simulation time 282865184746 ps
CPU time 1744.19 seconds
Started Aug 02 06:39:52 PM PDT 24
Finished Aug 02 07:08:56 PM PDT 24
Peak memory 224312 kb
Host smart-27a1fdf2-2483-4867-bfa1-1eaee713af37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697769861 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.697769861
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.2281667876
Short name T53
Test name
Test status
Simulation time 22386180 ps
CPU time 0.88 seconds
Started Aug 02 06:39:49 PM PDT 24
Finished Aug 02 06:39:50 PM PDT 24
Peak memory 206744 kb
Host smart-01cab7ea-3313-4f43-a47e-ce5ca22782ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281667876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2281667876
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1807821380
Short name T454
Test name
Test status
Simulation time 12312616 ps
CPU time 0.94 seconds
Started Aug 02 06:39:47 PM PDT 24
Finished Aug 02 06:39:48 PM PDT 24
Peak memory 216152 kb
Host smart-039cc1b0-ffa5-4813-92ca-0a1d983ea906
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807821380 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1807821380
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3442858593
Short name T155
Test name
Test status
Simulation time 33534708 ps
CPU time 1.15 seconds
Started Aug 02 06:39:49 PM PDT 24
Finished Aug 02 06:39:50 PM PDT 24
Peak memory 217008 kb
Host smart-6a2c4de8-5d6b-4aca-9e1a-af6d71fe7a8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442858593 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3442858593
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.80022222
Short name T522
Test name
Test status
Simulation time 26843432 ps
CPU time 0.85 seconds
Started Aug 02 06:39:47 PM PDT 24
Finished Aug 02 06:39:48 PM PDT 24
Peak memory 218424 kb
Host smart-e736759c-d85d-4e5b-9e0a-c148152d626a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80022222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.80022222
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3314963610
Short name T502
Test name
Test status
Simulation time 38038493 ps
CPU time 1.42 seconds
Started Aug 02 06:39:52 PM PDT 24
Finished Aug 02 06:39:53 PM PDT 24
Peak memory 217332 kb
Host smart-be458496-5833-46ca-aabb-513a0ec26e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314963610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3314963610
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.552152511
Short name T551
Test name
Test status
Simulation time 39018778 ps
CPU time 0.95 seconds
Started Aug 02 06:39:52 PM PDT 24
Finished Aug 02 06:39:53 PM PDT 24
Peak memory 215648 kb
Host smart-1c7ba92c-ceba-4b03-95ef-5b796bb15201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552152511 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.552152511
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.2153711098
Short name T555
Test name
Test status
Simulation time 17462249 ps
CPU time 1.08 seconds
Started Aug 02 06:39:50 PM PDT 24
Finished Aug 02 06:39:51 PM PDT 24
Peak memory 207100 kb
Host smart-189b531f-a01e-44b9-8a0a-d310d1dd4ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153711098 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2153711098
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.355122148
Short name T372
Test name
Test status
Simulation time 58656938 ps
CPU time 0.94 seconds
Started Aug 02 06:39:47 PM PDT 24
Finished Aug 02 06:39:48 PM PDT 24
Peak memory 215248 kb
Host smart-4ab3441e-3c6d-41df-b550-95060ec9d238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355122148 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.355122148
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.278047548
Short name T721
Test name
Test status
Simulation time 86523107 ps
CPU time 1.19 seconds
Started Aug 02 06:39:47 PM PDT 24
Finished Aug 02 06:39:49 PM PDT 24
Peak memory 217220 kb
Host smart-cc293ed0-c45a-46f6-913d-8cd7297130d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278047548 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.278047548
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.1283258266
Short name T951
Test name
Test status
Simulation time 38152503 ps
CPU time 1.17 seconds
Started Aug 02 06:40:11 PM PDT 24
Finished Aug 02 06:40:13 PM PDT 24
Peak memory 219036 kb
Host smart-06045072-ff7f-45cb-ae79-f619f7261919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283258266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1283258266
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2767925792
Short name T391
Test name
Test status
Simulation time 16936728 ps
CPU time 0.96 seconds
Started Aug 02 06:40:12 PM PDT 24
Finished Aug 02 06:40:14 PM PDT 24
Peak memory 214836 kb
Host smart-30fa1c25-6af0-43d4-bd8a-da32c06613a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767925792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2767925792
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2931120416
Short name T952
Test name
Test status
Simulation time 10477643 ps
CPU time 0.89 seconds
Started Aug 02 06:40:08 PM PDT 24
Finished Aug 02 06:40:09 PM PDT 24
Peak memory 215972 kb
Host smart-f682eccc-01b5-4e9e-a329-21ae0602e2b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931120416 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2931120416
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.1649031636
Short name T865
Test name
Test status
Simulation time 25810879 ps
CPU time 0.94 seconds
Started Aug 02 06:40:08 PM PDT 24
Finished Aug 02 06:40:09 PM PDT 24
Peak memory 218496 kb
Host smart-23a40c39-0418-46bb-b755-2cc6df0d9f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649031636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1649031636
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2946955323
Short name T657
Test name
Test status
Simulation time 63514711 ps
CPU time 1.58 seconds
Started Aug 02 06:40:15 PM PDT 24
Finished Aug 02 06:40:17 PM PDT 24
Peak memory 218788 kb
Host smart-91442870-b02b-4c10-83ba-c671fffcc95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946955323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2946955323
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3558529159
Short name T779
Test name
Test status
Simulation time 38078150 ps
CPU time 1.01 seconds
Started Aug 02 06:40:10 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 224144 kb
Host smart-05c8de16-5f37-4af1-a1ff-c273c88547e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558529159 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3558529159
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3250250070
Short name T717
Test name
Test status
Simulation time 23720681 ps
CPU time 0.91 seconds
Started Aug 02 06:40:12 PM PDT 24
Finished Aug 02 06:40:13 PM PDT 24
Peak memory 215308 kb
Host smart-e5e42a47-f78f-40cd-8c3f-653c606ab742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250250070 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3250250070
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3778869473
Short name T738
Test name
Test status
Simulation time 61006810678 ps
CPU time 768.32 seconds
Started Aug 02 06:40:11 PM PDT 24
Finished Aug 02 06:53:00 PM PDT 24
Peak memory 223716 kb
Host smart-008f508f-a7d9-4350-80a4-b3d62e702f32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778869473 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3778869473
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2652122513
Short name T835
Test name
Test status
Simulation time 65269923 ps
CPU time 1.38 seconds
Started Aug 02 06:41:56 PM PDT 24
Finished Aug 02 06:41:57 PM PDT 24
Peak memory 218520 kb
Host smart-a25a7a87-4bfe-40c5-b37a-0a9fe2be535f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652122513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2652122513
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.983613635
Short name T967
Test name
Test status
Simulation time 40654379 ps
CPU time 1.15 seconds
Started Aug 02 06:41:57 PM PDT 24
Finished Aug 02 06:41:59 PM PDT 24
Peak memory 219660 kb
Host smart-90757dc1-e06e-4b46-bd88-adfd1a8521db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983613635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.983613635
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.2415822245
Short name T242
Test name
Test status
Simulation time 47177362 ps
CPU time 1.05 seconds
Started Aug 02 06:41:56 PM PDT 24
Finished Aug 02 06:41:57 PM PDT 24
Peak memory 217188 kb
Host smart-8ac15122-a95c-4f69-ab23-9dc6a7481bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415822245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2415822245
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.1768751474
Short name T935
Test name
Test status
Simulation time 65286024 ps
CPU time 1.36 seconds
Started Aug 02 06:42:02 PM PDT 24
Finished Aug 02 06:42:04 PM PDT 24
Peak memory 215840 kb
Host smart-61f05fda-e435-4bb0-9251-d303bad33b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768751474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1768751474
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2761989614
Short name T819
Test name
Test status
Simulation time 39492058 ps
CPU time 1.61 seconds
Started Aug 02 06:41:58 PM PDT 24
Finished Aug 02 06:42:00 PM PDT 24
Peak memory 218504 kb
Host smart-b3f31bd9-0f72-4d02-8c1c-98bf7ce47510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761989614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2761989614
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.2856236220
Short name T386
Test name
Test status
Simulation time 77426239 ps
CPU time 1.14 seconds
Started Aug 02 06:41:56 PM PDT 24
Finished Aug 02 06:41:57 PM PDT 24
Peak memory 219244 kb
Host smart-679874f6-53c4-486c-9e58-9c0f0427cd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856236220 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.2856236220
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.3707626026
Short name T340
Test name
Test status
Simulation time 39416279 ps
CPU time 1.34 seconds
Started Aug 02 06:42:00 PM PDT 24
Finished Aug 02 06:42:01 PM PDT 24
Peak memory 217268 kb
Host smart-2c32fb42-2b05-4ab9-8855-b45a605681c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707626026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3707626026
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.4133534071
Short name T239
Test name
Test status
Simulation time 24039839 ps
CPU time 1.2 seconds
Started Aug 02 06:42:02 PM PDT 24
Finished Aug 02 06:42:04 PM PDT 24
Peak memory 219012 kb
Host smart-b11239f8-e9cc-4657-8dbb-1fd279a7a81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133534071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.4133534071
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.4291743840
Short name T641
Test name
Test status
Simulation time 52788670 ps
CPU time 1.2 seconds
Started Aug 02 06:41:59 PM PDT 24
Finished Aug 02 06:42:01 PM PDT 24
Peak memory 217320 kb
Host smart-240c42e1-010c-4448-818e-8d1f00e2d4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291743840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.4291743840
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.1830015081
Short name T792
Test name
Test status
Simulation time 24755927 ps
CPU time 1.21 seconds
Started Aug 02 06:41:58 PM PDT 24
Finished Aug 02 06:41:59 PM PDT 24
Peak memory 219876 kb
Host smart-8e6835a5-c7a0-4ee7-9805-ed7497f9997e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830015081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.1830015081
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/107.edn_alert.2453839686
Short name T855
Test name
Test status
Simulation time 72008617 ps
CPU time 1.1 seconds
Started Aug 02 06:41:58 PM PDT 24
Finished Aug 02 06:41:59 PM PDT 24
Peak memory 218400 kb
Host smart-c2bea071-ffb6-4fe2-b7fd-a5668d94d553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453839686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2453839686
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.1183621173
Short name T526
Test name
Test status
Simulation time 57001318 ps
CPU time 1.69 seconds
Started Aug 02 06:41:59 PM PDT 24
Finished Aug 02 06:42:01 PM PDT 24
Peak memory 218368 kb
Host smart-ecb1e69d-5b32-4e6e-bb50-0452ab9a7153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183621173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1183621173
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.3343478085
Short name T899
Test name
Test status
Simulation time 21708828 ps
CPU time 1.17 seconds
Started Aug 02 06:41:55 PM PDT 24
Finished Aug 02 06:41:56 PM PDT 24
Peak memory 219892 kb
Host smart-36cb2f93-381b-41a6-8bd9-15d534d6657e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343478085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3343478085
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/109.edn_alert.2487228603
Short name T480
Test name
Test status
Simulation time 62295021 ps
CPU time 1.13 seconds
Started Aug 02 06:41:59 PM PDT 24
Finished Aug 02 06:42:01 PM PDT 24
Peak memory 218584 kb
Host smart-5e99e85b-66f7-47ae-b681-3fd1c5c00659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487228603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.2487228603
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.1419509380
Short name T492
Test name
Test status
Simulation time 55817357 ps
CPU time 1.26 seconds
Started Aug 02 06:41:56 PM PDT 24
Finished Aug 02 06:41:57 PM PDT 24
Peak memory 219864 kb
Host smart-c662eb8d-b3d8-430e-8008-1b98fbdee9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419509380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1419509380
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.538581761
Short name T160
Test name
Test status
Simulation time 143175288 ps
CPU time 1.29 seconds
Started Aug 02 06:40:10 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 219632 kb
Host smart-2f7215e6-61f3-4628-9190-5ebe5c31172b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538581761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.538581761
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3996089247
Short name T797
Test name
Test status
Simulation time 14337473 ps
CPU time 0.96 seconds
Started Aug 02 06:40:09 PM PDT 24
Finished Aug 02 06:40:10 PM PDT 24
Peak memory 214912 kb
Host smart-01fb8c38-b396-41d0-a8cc-98e25395daed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996089247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3996089247
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2093156296
Short name T169
Test name
Test status
Simulation time 47821479 ps
CPU time 1.44 seconds
Started Aug 02 06:40:12 PM PDT 24
Finished Aug 02 06:40:14 PM PDT 24
Peak memory 219472 kb
Host smart-cf7615af-ce60-498b-b45c-0573f5ddc7a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093156296 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2093156296
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1188624632
Short name T145
Test name
Test status
Simulation time 28391877 ps
CPU time 1.3 seconds
Started Aug 02 06:40:10 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 220456 kb
Host smart-058c6673-0ef3-4aee-ba2c-081a2d032fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188624632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1188624632
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2729343949
Short name T352
Test name
Test status
Simulation time 157152497 ps
CPU time 3.05 seconds
Started Aug 02 06:40:09 PM PDT 24
Finished Aug 02 06:40:13 PM PDT 24
Peak memory 215384 kb
Host smart-91e6dbbe-4c33-4c35-9496-096b7c083e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729343949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2729343949
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.602239342
Short name T82
Test name
Test status
Simulation time 22687794 ps
CPU time 1.03 seconds
Started Aug 02 06:40:09 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 215824 kb
Host smart-9d11b8b3-1832-4381-80e7-79b755d1fed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602239342 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.602239342
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.235176600
Short name T350
Test name
Test status
Simulation time 17474952 ps
CPU time 0.98 seconds
Started Aug 02 06:40:10 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 215356 kb
Host smart-e7f5938d-887d-4417-a3a7-f53dc6095336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235176600 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.235176600
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1896330735
Short name T440
Test name
Test status
Simulation time 456450984 ps
CPU time 3.17 seconds
Started Aug 02 06:40:10 PM PDT 24
Finished Aug 02 06:40:13 PM PDT 24
Peak memory 217448 kb
Host smart-424ab544-883a-4ccc-8156-4d63547276b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896330735 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1896330735
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3082193057
Short name T680
Test name
Test status
Simulation time 233660683153 ps
CPU time 1328.04 seconds
Started Aug 02 06:40:13 PM PDT 24
Finished Aug 02 07:02:21 PM PDT 24
Peak memory 224488 kb
Host smart-5bc9fd5f-41df-4bde-9dbb-ae3b8aade858
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082193057 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3082193057
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2741558868
Short name T67
Test name
Test status
Simulation time 136278608 ps
CPU time 1.45 seconds
Started Aug 02 06:41:56 PM PDT 24
Finished Aug 02 06:41:57 PM PDT 24
Peak memory 218764 kb
Host smart-f0121d50-1f38-4598-8a1f-84f5772a1f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741558868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2741558868
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.107133144
Short name T678
Test name
Test status
Simulation time 68535183 ps
CPU time 1.61 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:09 PM PDT 24
Peak memory 217388 kb
Host smart-9acda2fa-37cf-4bbb-ac71-8f37a5ca5c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107133144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.107133144
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.74804732
Short name T648
Test name
Test status
Simulation time 121597869 ps
CPU time 1.29 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:10 PM PDT 24
Peak memory 220088 kb
Host smart-d21b87c2-2983-4051-937b-0328da2780e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74804732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.74804732
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.2273330014
Short name T954
Test name
Test status
Simulation time 62464468 ps
CPU time 2.45 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:10 PM PDT 24
Peak memory 220188 kb
Host smart-28dfdcb9-ec03-441c-924b-0313a5eccee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273330014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2273330014
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2390568986
Short name T382
Test name
Test status
Simulation time 59272357 ps
CPU time 1.24 seconds
Started Aug 02 06:42:10 PM PDT 24
Finished Aug 02 06:42:11 PM PDT 24
Peak memory 218640 kb
Host smart-e6808c08-cdfa-4796-88ae-6d9d977c7eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390568986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2390568986
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.2758622770
Short name T371
Test name
Test status
Simulation time 30268165 ps
CPU time 1.09 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:09 PM PDT 24
Peak memory 218492 kb
Host smart-4183fb38-65c2-42ab-a748-09d7366df0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758622770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2758622770
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.668924254
Short name T193
Test name
Test status
Simulation time 45235746 ps
CPU time 1.22 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:09 PM PDT 24
Peak memory 219932 kb
Host smart-2e1764f4-49af-4add-a691-5e2e552ae837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668924254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.668924254
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.881689201
Short name T568
Test name
Test status
Simulation time 36560246 ps
CPU time 1.41 seconds
Started Aug 02 06:42:06 PM PDT 24
Finished Aug 02 06:42:07 PM PDT 24
Peak memory 217388 kb
Host smart-f831e064-0caf-4bef-a7dc-f577c367f25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881689201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.881689201
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.399349952
Short name T72
Test name
Test status
Simulation time 90528191 ps
CPU time 1.29 seconds
Started Aug 02 06:42:09 PM PDT 24
Finished Aug 02 06:42:11 PM PDT 24
Peak memory 215684 kb
Host smart-4cac78b2-d5af-4658-886b-f889fbc1809a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399349952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.399349952
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.1646900952
Short name T573
Test name
Test status
Simulation time 51257650 ps
CPU time 1.55 seconds
Started Aug 02 06:42:10 PM PDT 24
Finished Aug 02 06:42:12 PM PDT 24
Peak memory 218496 kb
Host smart-637f3383-a362-43b7-b4ae-ab2057ac69e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646900952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1646900952
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3203362491
Short name T185
Test name
Test status
Simulation time 52086394 ps
CPU time 1.21 seconds
Started Aug 02 06:42:09 PM PDT 24
Finished Aug 02 06:42:10 PM PDT 24
Peak memory 220968 kb
Host smart-df0300fa-17bf-44ce-9e10-f93f6fa63867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203362491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3203362491
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.79542023
Short name T378
Test name
Test status
Simulation time 100267113 ps
CPU time 1.94 seconds
Started Aug 02 06:42:11 PM PDT 24
Finished Aug 02 06:42:13 PM PDT 24
Peak memory 219692 kb
Host smart-aaa976cc-50ce-4e20-a0a5-349bf1c4e035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79542023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.79542023
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.2562755408
Short name T47
Test name
Test status
Simulation time 33005363 ps
CPU time 1.16 seconds
Started Aug 02 06:42:06 PM PDT 24
Finished Aug 02 06:42:07 PM PDT 24
Peak memory 219908 kb
Host smart-38c323e4-3cbf-4d95-9bf6-d68ae2a01b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562755408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.2562755408
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.1412339618
Short name T655
Test name
Test status
Simulation time 49763389 ps
CPU time 1.36 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:10 PM PDT 24
Peak memory 218796 kb
Host smart-a454fd40-0248-41be-aef5-bc92c74d8ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412339618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1412339618
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.847326166
Short name T208
Test name
Test status
Simulation time 247620850 ps
CPU time 1.24 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:10 PM PDT 24
Peak memory 219704 kb
Host smart-2639a5b9-5f16-434a-aa55-d9b6a7e596f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847326166 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.847326166
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.3703578643
Short name T842
Test name
Test status
Simulation time 75541636 ps
CPU time 1.22 seconds
Started Aug 02 06:42:06 PM PDT 24
Finished Aug 02 06:42:08 PM PDT 24
Peak memory 217176 kb
Host smart-19697712-57a5-4410-b75b-ec1d99dcd971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703578643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3703578643
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.656168112
Short name T660
Test name
Test status
Simulation time 77494755 ps
CPU time 1.17 seconds
Started Aug 02 06:42:10 PM PDT 24
Finished Aug 02 06:42:11 PM PDT 24
Peak memory 215680 kb
Host smart-537353ec-69a9-4b80-8c4d-9781e7a5b2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656168112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.656168112
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert.3770678598
Short name T896
Test name
Test status
Simulation time 103739250 ps
CPU time 1.14 seconds
Started Aug 02 06:40:15 PM PDT 24
Finished Aug 02 06:40:17 PM PDT 24
Peak memory 221868 kb
Host smart-3a269dc7-a211-446d-bd17-41ab32c27070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770678598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3770678598
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.36074686
Short name T426
Test name
Test status
Simulation time 19618305 ps
CPU time 1.01 seconds
Started Aug 02 06:40:17 PM PDT 24
Finished Aug 02 06:40:19 PM PDT 24
Peak memory 206724 kb
Host smart-9acf182d-fd0b-4f4a-9ab9-0df519892af7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36074686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.36074686
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2452828724
Short name T109
Test name
Test status
Simulation time 36253107 ps
CPU time 0.89 seconds
Started Aug 02 06:40:16 PM PDT 24
Finished Aug 02 06:40:17 PM PDT 24
Peak memory 216216 kb
Host smart-1dc6ad83-a87e-4123-9af0-e87d672538bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452828724 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2452828724
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.3584186481
Short name T893
Test name
Test status
Simulation time 20923131 ps
CPU time 1.11 seconds
Started Aug 02 06:40:15 PM PDT 24
Finished Aug 02 06:40:16 PM PDT 24
Peak memory 219456 kb
Host smart-05779c15-6f18-48d8-9837-0f559589434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584186481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3584186481
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2444713296
Short name T734
Test name
Test status
Simulation time 77709393 ps
CPU time 2.3 seconds
Started Aug 02 06:40:11 PM PDT 24
Finished Aug 02 06:40:13 PM PDT 24
Peak memory 217548 kb
Host smart-17e22743-5fb8-4607-aaa3-6b29021a027f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444713296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2444713296
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.343363309
Short name T95
Test name
Test status
Simulation time 30995847 ps
CPU time 0.87 seconds
Started Aug 02 06:40:15 PM PDT 24
Finished Aug 02 06:40:15 PM PDT 24
Peak memory 215984 kb
Host smart-bf51465d-2227-4228-803c-10afa7ae16c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343363309 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.343363309
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2090200067
Short name T919
Test name
Test status
Simulation time 30040755 ps
CPU time 0.97 seconds
Started Aug 02 06:40:10 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 215280 kb
Host smart-2b98affa-a4ab-47ea-ba58-7ea1c7330a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090200067 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2090200067
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3325237569
Short name T764
Test name
Test status
Simulation time 701165551 ps
CPU time 4.76 seconds
Started Aug 02 06:40:19 PM PDT 24
Finished Aug 02 06:40:24 PM PDT 24
Peak memory 215260 kb
Host smart-5ad57e8f-deea-42d7-9819-c06411a584ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325237569 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3325237569
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2674317987
Short name T22
Test name
Test status
Simulation time 407697688381 ps
CPU time 2603.95 seconds
Started Aug 02 06:40:15 PM PDT 24
Finished Aug 02 07:23:39 PM PDT 24
Peak memory 232920 kb
Host smart-31442062-1f00-4ae2-9d05-e8e3f07d3e79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674317987 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2674317987
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.1771119671
Short name T788
Test name
Test status
Simulation time 27817600 ps
CPU time 1.08 seconds
Started Aug 02 06:42:07 PM PDT 24
Finished Aug 02 06:42:09 PM PDT 24
Peak memory 217248 kb
Host smart-04cf9e4c-4f64-43b4-8e61-c86013facb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771119671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1771119671
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.464372620
Short name T558
Test name
Test status
Simulation time 27688521 ps
CPU time 1.22 seconds
Started Aug 02 06:42:12 PM PDT 24
Finished Aug 02 06:42:13 PM PDT 24
Peak memory 218584 kb
Host smart-32d13d2b-5019-4227-aab2-d8d00b4ff260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464372620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.464372620
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/122.edn_alert.774529622
Short name T926
Test name
Test status
Simulation time 44175759 ps
CPU time 1.14 seconds
Started Aug 02 06:42:07 PM PDT 24
Finished Aug 02 06:42:08 PM PDT 24
Peak memory 219588 kb
Host smart-02745179-b7ea-4674-b210-5a90cbf8fb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774529622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.774529622
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.879837274
Short name T882
Test name
Test status
Simulation time 28074863 ps
CPU time 1.15 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:09 PM PDT 24
Peak memory 217388 kb
Host smart-0e84ffed-745e-4ffc-aa46-ecdd9bd021b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879837274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.879837274
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.264670818
Short name T307
Test name
Test status
Simulation time 58978675 ps
CPU time 1.15 seconds
Started Aug 02 06:42:09 PM PDT 24
Finished Aug 02 06:42:10 PM PDT 24
Peak memory 219680 kb
Host smart-e046b17a-5713-4f8f-8300-f4960576e89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264670818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.264670818
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.2845503654
Short name T625
Test name
Test status
Simulation time 56811861 ps
CPU time 1.23 seconds
Started Aug 02 06:42:10 PM PDT 24
Finished Aug 02 06:42:11 PM PDT 24
Peak memory 218328 kb
Host smart-90b4244e-cdf1-4554-b54b-0163901b10f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845503654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2845503654
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.942866153
Short name T167
Test name
Test status
Simulation time 24128059 ps
CPU time 1.17 seconds
Started Aug 02 06:42:13 PM PDT 24
Finished Aug 02 06:42:15 PM PDT 24
Peak memory 220616 kb
Host smart-5f1b509d-77ad-402a-94b1-c397691c2a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942866153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.942866153
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.2509276297
Short name T561
Test name
Test status
Simulation time 93439665 ps
CPU time 1.22 seconds
Started Aug 02 06:42:06 PM PDT 24
Finished Aug 02 06:42:08 PM PDT 24
Peak memory 217468 kb
Host smart-4d00feb9-98bd-4376-ba10-85935b545e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509276297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2509276297
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.1989073928
Short name T575
Test name
Test status
Simulation time 47196737 ps
CPU time 1.17 seconds
Started Aug 02 06:42:12 PM PDT 24
Finished Aug 02 06:42:13 PM PDT 24
Peak memory 219724 kb
Host smart-62c79fac-8979-4dfa-8c59-78570a208158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989073928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1989073928
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.2523285068
Short name T985
Test name
Test status
Simulation time 147541941 ps
CPU time 1.16 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:09 PM PDT 24
Peak memory 217472 kb
Host smart-d9e0e1a5-e63e-4399-8b26-b6c66f7c6bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523285068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2523285068
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.1329020976
Short name T642
Test name
Test status
Simulation time 49703639 ps
CPU time 1.18 seconds
Started Aug 02 06:42:10 PM PDT 24
Finished Aug 02 06:42:11 PM PDT 24
Peak memory 220132 kb
Host smart-4c13081e-9bbf-4049-b332-831f6ceb89de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329020976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.1329020976
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.1633276440
Short name T402
Test name
Test status
Simulation time 127118306 ps
CPU time 1.81 seconds
Started Aug 02 06:42:09 PM PDT 24
Finished Aug 02 06:42:11 PM PDT 24
Peak memory 218568 kb
Host smart-e3c27f73-f98b-4003-8947-1472dcfd5298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633276440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1633276440
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.1332042167
Short name T593
Test name
Test status
Simulation time 23245430 ps
CPU time 1.25 seconds
Started Aug 02 06:42:10 PM PDT 24
Finished Aug 02 06:42:12 PM PDT 24
Peak memory 219632 kb
Host smart-87d6ccd7-b10c-4b73-987d-e8d72ebce8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332042167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.1332042167
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.592408026
Short name T328
Test name
Test status
Simulation time 86755541 ps
CPU time 1.38 seconds
Started Aug 02 06:42:07 PM PDT 24
Finished Aug 02 06:42:09 PM PDT 24
Peak memory 217576 kb
Host smart-48072a04-c121-4a52-862d-98e68059d1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592408026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.592408026
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2939672483
Short name T392
Test name
Test status
Simulation time 50665296 ps
CPU time 1.26 seconds
Started Aug 02 06:42:10 PM PDT 24
Finished Aug 02 06:42:11 PM PDT 24
Peak memory 220476 kb
Host smart-8f6fdbf0-1d79-4db7-9c66-20d3907d2f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939672483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2939672483
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.2852795576
Short name T814
Test name
Test status
Simulation time 64609183 ps
CPU time 1.36 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:09 PM PDT 24
Peak memory 217444 kb
Host smart-aa7dc089-af2f-44f8-b669-48f3eedb5272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852795576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2852795576
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.11558298
Short name T479
Test name
Test status
Simulation time 25798191 ps
CPU time 1.25 seconds
Started Aug 02 06:42:07 PM PDT 24
Finished Aug 02 06:42:09 PM PDT 24
Peak memory 218696 kb
Host smart-7f6b5be4-2b35-4e6b-afc1-ec14c3547963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11558298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.11558298
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.486583099
Short name T253
Test name
Test status
Simulation time 29091682 ps
CPU time 1.32 seconds
Started Aug 02 06:40:16 PM PDT 24
Finished Aug 02 06:40:18 PM PDT 24
Peak memory 220544 kb
Host smart-0177a028-f3f1-499d-a5a6-3440af4bd473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486583099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.486583099
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2536407725
Short name T465
Test name
Test status
Simulation time 55126668 ps
CPU time 0.96 seconds
Started Aug 02 06:40:16 PM PDT 24
Finished Aug 02 06:40:17 PM PDT 24
Peak memory 206740 kb
Host smart-8753c544-3ef8-46f4-a152-2bf7efaab374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536407725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2536407725
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2331054486
Short name T775
Test name
Test status
Simulation time 171058719 ps
CPU time 0.87 seconds
Started Aug 02 06:40:18 PM PDT 24
Finished Aug 02 06:40:19 PM PDT 24
Peak memory 215372 kb
Host smart-d7aa01ea-339c-4c96-af61-54f744cc3514
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331054486 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2331054486
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3568091214
Short name T91
Test name
Test status
Simulation time 71944304 ps
CPU time 1.3 seconds
Started Aug 02 06:40:21 PM PDT 24
Finished Aug 02 06:40:22 PM PDT 24
Peak memory 216836 kb
Host smart-aa7e223f-39f0-4322-b603-15e56e3675d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568091214 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3568091214
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3731249986
Short name T852
Test name
Test status
Simulation time 24624753 ps
CPU time 1.29 seconds
Started Aug 02 06:40:21 PM PDT 24
Finished Aug 02 06:40:23 PM PDT 24
Peak memory 229792 kb
Host smart-dc822b0d-5524-4b05-a52e-da8ff8d22883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731249986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3731249986
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_intr.20844615
Short name T699
Test name
Test status
Simulation time 27132495 ps
CPU time 0.96 seconds
Started Aug 02 06:40:16 PM PDT 24
Finished Aug 02 06:40:17 PM PDT 24
Peak memory 215532 kb
Host smart-33cd8e55-bf88-4c45-836a-28851991e5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20844615 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.20844615
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3745613748
Short name T693
Test name
Test status
Simulation time 16847248 ps
CPU time 1.03 seconds
Started Aug 02 06:40:18 PM PDT 24
Finished Aug 02 06:40:19 PM PDT 24
Peak memory 215324 kb
Host smart-cc9b6266-a9e0-4891-9069-3dcb82e34f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745613748 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3745613748
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3698418082
Short name T481
Test name
Test status
Simulation time 189759491 ps
CPU time 4.06 seconds
Started Aug 02 06:40:16 PM PDT 24
Finished Aug 02 06:40:20 PM PDT 24
Peak memory 217200 kb
Host smart-1a6cbee0-2131-4f48-966a-712e1345b504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698418082 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3698418082
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2776099873
Short name T836
Test name
Test status
Simulation time 1295899431450 ps
CPU time 1868.27 seconds
Started Aug 02 06:40:19 PM PDT 24
Finished Aug 02 07:11:27 PM PDT 24
Peak memory 227792 kb
Host smart-905c4342-1530-4ef2-9dcf-548920cd2885
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776099873 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2776099873
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.3138381009
Short name T894
Test name
Test status
Simulation time 35799814 ps
CPU time 1.37 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:10 PM PDT 24
Peak memory 220576 kb
Host smart-a9a2a84e-b0f0-4cf0-9741-4e5bf59fc1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138381009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3138381009
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.339460927
Short name T449
Test name
Test status
Simulation time 36495165 ps
CPU time 1.36 seconds
Started Aug 02 06:42:10 PM PDT 24
Finished Aug 02 06:42:12 PM PDT 24
Peak memory 218532 kb
Host smart-87121cfd-f0af-4c08-a258-31d1afd8dcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339460927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.339460927
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.1313610583
Short name T600
Test name
Test status
Simulation time 51857410 ps
CPU time 1.28 seconds
Started Aug 02 06:42:06 PM PDT 24
Finished Aug 02 06:42:08 PM PDT 24
Peak memory 218520 kb
Host smart-c82c5955-0f4a-43bf-9061-b072af2235fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313610583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1313610583
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.559110943
Short name T802
Test name
Test status
Simulation time 44788940 ps
CPU time 1.59 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:10 PM PDT 24
Peak memory 218756 kb
Host smart-323a4fd2-1d16-4240-be3e-2b176b200006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559110943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.559110943
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.2009891691
Short name T913
Test name
Test status
Simulation time 49949611 ps
CPU time 1.21 seconds
Started Aug 02 06:42:09 PM PDT 24
Finished Aug 02 06:42:11 PM PDT 24
Peak memory 219768 kb
Host smart-fe8f265f-1aa7-4830-96a2-fd755f236e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009891691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.2009891691
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.1673883956
Short name T826
Test name
Test status
Simulation time 49805178 ps
CPU time 1.02 seconds
Started Aug 02 06:42:08 PM PDT 24
Finished Aug 02 06:42:09 PM PDT 24
Peak memory 217540 kb
Host smart-ca16a878-5b4f-48dd-8194-1aaa29d9a1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673883956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1673883956
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.4283208265
Short name T986
Test name
Test status
Simulation time 24760321 ps
CPU time 1.21 seconds
Started Aug 02 06:42:05 PM PDT 24
Finished Aug 02 06:42:07 PM PDT 24
Peak memory 220396 kb
Host smart-d976c9da-fe46-4da2-a9a6-15bcdcd33db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283208265 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.4283208265
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/134.edn_alert.1688365127
Short name T283
Test name
Test status
Simulation time 50572991 ps
CPU time 1.26 seconds
Started Aug 02 06:42:23 PM PDT 24
Finished Aug 02 06:42:25 PM PDT 24
Peak memory 220044 kb
Host smart-ba8bbce7-d6b5-4af6-94c5-090af28f8e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688365127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1688365127
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.2642428232
Short name T458
Test name
Test status
Simulation time 48336293 ps
CPU time 1.87 seconds
Started Aug 02 06:42:21 PM PDT 24
Finished Aug 02 06:42:23 PM PDT 24
Peak memory 217556 kb
Host smart-31b28c48-d96c-4967-887b-78bec634ac80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642428232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2642428232
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.3391071175
Short name T599
Test name
Test status
Simulation time 47610357 ps
CPU time 1.2 seconds
Started Aug 02 06:42:20 PM PDT 24
Finished Aug 02 06:42:21 PM PDT 24
Peak memory 218664 kb
Host smart-42db46ab-f40e-410e-ba2e-97e289f852de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391071175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3391071175
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.3624432702
Short name T557
Test name
Test status
Simulation time 76091298 ps
CPU time 1.17 seconds
Started Aug 02 06:42:22 PM PDT 24
Finished Aug 02 06:42:24 PM PDT 24
Peak memory 217208 kb
Host smart-8b6a4d45-640b-489e-839c-6366d9558207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624432702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3624432702
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.2424734633
Short name T841
Test name
Test status
Simulation time 181950790 ps
CPU time 1.29 seconds
Started Aug 02 06:42:19 PM PDT 24
Finished Aug 02 06:42:21 PM PDT 24
Peak memory 215664 kb
Host smart-1a5bd26b-3631-4b11-94cc-3c7817aa2f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424734633 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.2424734633
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.540133633
Short name T755
Test name
Test status
Simulation time 193176823 ps
CPU time 1.25 seconds
Started Aug 02 06:42:22 PM PDT 24
Finished Aug 02 06:42:23 PM PDT 24
Peak memory 219772 kb
Host smart-28228da6-2774-4f20-8d2c-27be3b4b8da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540133633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.540133633
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.3430969064
Short name T976
Test name
Test status
Simulation time 68165609 ps
CPU time 1.17 seconds
Started Aug 02 06:42:20 PM PDT 24
Finished Aug 02 06:42:21 PM PDT 24
Peak memory 220448 kb
Host smart-603c017d-7baf-442f-8978-dff79d012307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430969064 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.3430969064
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.1045019380
Short name T666
Test name
Test status
Simulation time 94052597 ps
CPU time 1.35 seconds
Started Aug 02 06:42:18 PM PDT 24
Finished Aug 02 06:42:20 PM PDT 24
Peak memory 218808 kb
Host smart-07a47933-0063-4eb6-bfba-d54970566a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045019380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1045019380
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.1463726380
Short name T57
Test name
Test status
Simulation time 39550535 ps
CPU time 1.3 seconds
Started Aug 02 06:42:20 PM PDT 24
Finished Aug 02 06:42:21 PM PDT 24
Peak memory 220252 kb
Host smart-07d4e2fa-8be5-49f1-a518-7b442efb7203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463726380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.1463726380
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.129661980
Short name T435
Test name
Test status
Simulation time 34483836 ps
CPU time 1.29 seconds
Started Aug 02 06:42:25 PM PDT 24
Finished Aug 02 06:42:26 PM PDT 24
Peak memory 218596 kb
Host smart-033744cb-83a4-4c7f-a271-6705d083e2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129661980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.129661980
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2481277206
Short name T970
Test name
Test status
Simulation time 38624930 ps
CPU time 1.32 seconds
Started Aug 02 06:42:20 PM PDT 24
Finished Aug 02 06:42:21 PM PDT 24
Peak memory 215828 kb
Host smart-c0c4ca69-4b2d-4851-a07c-3af547dd1357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481277206 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2481277206
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.251181414
Short name T347
Test name
Test status
Simulation time 91299341 ps
CPU time 1.4 seconds
Started Aug 02 06:42:21 PM PDT 24
Finished Aug 02 06:42:23 PM PDT 24
Peak memory 218756 kb
Host smart-a6646576-8bf2-47f1-8233-ab3a82a419e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251181414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.251181414
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.157653856
Short name T831
Test name
Test status
Simulation time 26909219 ps
CPU time 1.28 seconds
Started Aug 02 06:40:16 PM PDT 24
Finished Aug 02 06:40:17 PM PDT 24
Peak memory 219640 kb
Host smart-5c9dc12f-d2e9-4df0-8f78-759600cbfdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157653856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.157653856
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1158943733
Short name T572
Test name
Test status
Simulation time 11078071 ps
CPU time 0.8 seconds
Started Aug 02 06:40:21 PM PDT 24
Finished Aug 02 06:40:22 PM PDT 24
Peak memory 206820 kb
Host smart-bf24e72f-e356-40ca-99f7-f62cefe6d6e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158943733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1158943733
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_err.2284465747
Short name T677
Test name
Test status
Simulation time 30862566 ps
CPU time 1.03 seconds
Started Aug 02 06:40:15 PM PDT 24
Finished Aug 02 06:40:16 PM PDT 24
Peak memory 218700 kb
Host smart-1a9bc1f5-0f01-4fdc-8fd1-a1a5fa782bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284465747 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2284465747
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3783782432
Short name T419
Test name
Test status
Simulation time 80396767 ps
CPU time 1.05 seconds
Started Aug 02 06:40:14 PM PDT 24
Finished Aug 02 06:40:16 PM PDT 24
Peak memory 217360 kb
Host smart-ff1ae590-3f1a-4e35-b536-ededce4ee554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783782432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3783782432
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1220907885
Short name T623
Test name
Test status
Simulation time 32247413 ps
CPU time 0.88 seconds
Started Aug 02 06:40:17 PM PDT 24
Finished Aug 02 06:40:19 PM PDT 24
Peak memory 215156 kb
Host smart-4c6dba14-b345-4d3c-bea3-9b20f5f1fc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220907885 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1220907885
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.307769442
Short name T981
Test name
Test status
Simulation time 18671813 ps
CPU time 1.04 seconds
Started Aug 02 06:40:16 PM PDT 24
Finished Aug 02 06:40:17 PM PDT 24
Peak memory 207168 kb
Host smart-15b0f057-090c-4e2a-a5a6-4ba0a2abb4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307769442 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.307769442
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1584354851
Short name T564
Test name
Test status
Simulation time 444395624 ps
CPU time 4.67 seconds
Started Aug 02 06:40:42 PM PDT 24
Finished Aug 02 06:40:47 PM PDT 24
Peak memory 217276 kb
Host smart-eaff5708-9fc1-44a2-a434-6a2957763b7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584354851 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1584354851
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3325099368
Short name T315
Test name
Test status
Simulation time 11126137918 ps
CPU time 137.44 seconds
Started Aug 02 06:40:18 PM PDT 24
Finished Aug 02 06:42:36 PM PDT 24
Peak memory 219976 kb
Host smart-48627c57-4a99-4cad-8101-e2cd2923c7c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325099368 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3325099368
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.3413409419
Short name T156
Test name
Test status
Simulation time 29400525 ps
CPU time 1.28 seconds
Started Aug 02 06:42:25 PM PDT 24
Finished Aug 02 06:42:26 PM PDT 24
Peak memory 219272 kb
Host smart-31316814-ad22-4d1c-9061-bb3577b5d0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413409419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.3413409419
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/141.edn_alert.2191964927
Short name T633
Test name
Test status
Simulation time 36193314 ps
CPU time 1.13 seconds
Started Aug 02 06:42:21 PM PDT 24
Finished Aug 02 06:42:23 PM PDT 24
Peak memory 218596 kb
Host smart-b23a6a59-7012-4923-9bba-41727561b0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191964927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2191964927
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.1184222131
Short name T284
Test name
Test status
Simulation time 54844224 ps
CPU time 1.09 seconds
Started Aug 02 06:42:20 PM PDT 24
Finished Aug 02 06:42:21 PM PDT 24
Peak memory 217256 kb
Host smart-7935ce39-a6d8-4908-85a0-b0cc2f816d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184222131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1184222131
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.2125618914
Short name T676
Test name
Test status
Simulation time 32067830 ps
CPU time 1.33 seconds
Started Aug 02 06:42:20 PM PDT 24
Finished Aug 02 06:42:22 PM PDT 24
Peak memory 215684 kb
Host smart-d29d3c40-a953-438e-b73a-30dd8deeb82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125618914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2125618914
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.2118514486
Short name T358
Test name
Test status
Simulation time 51890454 ps
CPU time 1.27 seconds
Started Aug 02 06:42:21 PM PDT 24
Finished Aug 02 06:42:22 PM PDT 24
Peak memory 220196 kb
Host smart-cc4e5904-903f-46b6-a0f5-89192c1d6457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118514486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2118514486
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.589236246
Short name T789
Test name
Test status
Simulation time 39258453 ps
CPU time 1.08 seconds
Started Aug 02 06:42:25 PM PDT 24
Finished Aug 02 06:42:26 PM PDT 24
Peak memory 218640 kb
Host smart-922d5540-e012-4846-9f36-f9bda4d654d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589236246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.589236246
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.2993845956
Short name T338
Test name
Test status
Simulation time 86512441 ps
CPU time 1.95 seconds
Started Aug 02 06:42:22 PM PDT 24
Finished Aug 02 06:42:24 PM PDT 24
Peak memory 219592 kb
Host smart-8957a3d4-8c0a-4cf3-9108-1c5188bb1c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993845956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2993845956
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.217232696
Short name T924
Test name
Test status
Simulation time 27157677 ps
CPU time 1.29 seconds
Started Aug 02 06:42:21 PM PDT 24
Finished Aug 02 06:42:22 PM PDT 24
Peak memory 221172 kb
Host smart-666abce2-d6a5-47dd-992f-ff2b836d9f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217232696 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.217232696
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.793240790
Short name T321
Test name
Test status
Simulation time 71517148 ps
CPU time 1.18 seconds
Started Aug 02 06:42:24 PM PDT 24
Finished Aug 02 06:42:25 PM PDT 24
Peak memory 220156 kb
Host smart-f551ae0a-e298-4f8d-82b4-c9e71f204e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793240790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.793240790
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.1411905724
Short name T866
Test name
Test status
Simulation time 34885627 ps
CPU time 1.07 seconds
Started Aug 02 06:42:22 PM PDT 24
Finished Aug 02 06:42:23 PM PDT 24
Peak memory 218432 kb
Host smart-f2b34fd3-bd51-44d7-b7fa-c3f86046bfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411905724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.1411905724
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.4165476097
Short name T512
Test name
Test status
Simulation time 83882954 ps
CPU time 1.24 seconds
Started Aug 02 06:42:24 PM PDT 24
Finished Aug 02 06:42:25 PM PDT 24
Peak memory 218840 kb
Host smart-5a78fbc0-5c5d-4dcd-921c-64f064ca33fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165476097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4165476097
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.895758021
Short name T630
Test name
Test status
Simulation time 47366604 ps
CPU time 1.15 seconds
Started Aug 02 06:42:25 PM PDT 24
Finished Aug 02 06:42:26 PM PDT 24
Peak memory 220612 kb
Host smart-d3a30fd4-02f5-4090-a181-7bb102b25bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895758021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.895758021
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2048085989
Short name T619
Test name
Test status
Simulation time 24287015 ps
CPU time 1.25 seconds
Started Aug 02 06:42:21 PM PDT 24
Finished Aug 02 06:42:22 PM PDT 24
Peak memory 218952 kb
Host smart-d0e53b15-c432-4e3d-8f4f-482ea57132eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048085989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2048085989
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.3436443821
Short name T880
Test name
Test status
Simulation time 41429827 ps
CPU time 1.22 seconds
Started Aug 02 06:42:24 PM PDT 24
Finished Aug 02 06:42:25 PM PDT 24
Peak memory 215684 kb
Host smart-b7252a0f-4096-483c-920e-ca211dfbef67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436443821 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.3436443821
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.1542700446
Short name T423
Test name
Test status
Simulation time 62866391 ps
CPU time 1.01 seconds
Started Aug 02 06:42:20 PM PDT 24
Finished Aug 02 06:42:21 PM PDT 24
Peak memory 217284 kb
Host smart-acb25f4f-ed58-4577-8e7c-fea0441563fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542700446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1542700446
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.944293054
Short name T783
Test name
Test status
Simulation time 46127372 ps
CPU time 1.18 seconds
Started Aug 02 06:42:22 PM PDT 24
Finished Aug 02 06:42:24 PM PDT 24
Peak memory 220348 kb
Host smart-767eea94-d98c-4bc8-abf4-e48863493a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944293054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.944293054
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.3223355910
Short name T661
Test name
Test status
Simulation time 48347246 ps
CPU time 1.31 seconds
Started Aug 02 06:42:21 PM PDT 24
Finished Aug 02 06:42:22 PM PDT 24
Peak memory 218876 kb
Host smart-13069a48-236f-4447-8ae7-1579f08aac9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223355910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3223355910
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1926295913
Short name T763
Test name
Test status
Simulation time 110088028 ps
CPU time 1.48 seconds
Started Aug 02 06:42:21 PM PDT 24
Finished Aug 02 06:42:22 PM PDT 24
Peak memory 218924 kb
Host smart-48bc2028-755b-4dfe-96c9-d269b96ca84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926295913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1926295913
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1932760487
Short name T654
Test name
Test status
Simulation time 83161493 ps
CPU time 1.2 seconds
Started Aug 02 06:40:19 PM PDT 24
Finished Aug 02 06:40:20 PM PDT 24
Peak memory 219824 kb
Host smart-3e4fae99-d876-4342-ac69-66bdb896238a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932760487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1932760487
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.996934516
Short name T52
Test name
Test status
Simulation time 16185549 ps
CPU time 0.88 seconds
Started Aug 02 06:40:18 PM PDT 24
Finished Aug 02 06:40:19 PM PDT 24
Peak memory 206776 kb
Host smart-eaf55f64-37ca-4650-872e-b1326bcd9c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996934516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.996934516
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1681719803
Short name T672
Test name
Test status
Simulation time 21522617 ps
CPU time 0.87 seconds
Started Aug 02 06:40:17 PM PDT 24
Finished Aug 02 06:40:18 PM PDT 24
Peak memory 216324 kb
Host smart-55e90f3f-7b39-4257-b1e0-6ef58d8259b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681719803 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1681719803
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.1090475228
Short name T173
Test name
Test status
Simulation time 31878380 ps
CPU time 1.06 seconds
Started Aug 02 06:40:16 PM PDT 24
Finished Aug 02 06:40:17 PM PDT 24
Peak memory 219728 kb
Host smart-be31f9ed-4025-4d3c-a8d0-952529d78e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090475228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1090475228
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.4188802030
Short name T553
Test name
Test status
Simulation time 33846565 ps
CPU time 1.31 seconds
Started Aug 02 06:40:17 PM PDT 24
Finished Aug 02 06:40:18 PM PDT 24
Peak memory 218412 kb
Host smart-51dc8031-735e-416b-a2ae-3bf2de92ee1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188802030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.4188802030
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3377764373
Short name T632
Test name
Test status
Simulation time 19819484 ps
CPU time 1.05 seconds
Started Aug 02 06:40:21 PM PDT 24
Finished Aug 02 06:40:23 PM PDT 24
Peak memory 215928 kb
Host smart-afa307fe-6715-47ff-bcd9-c81fc6c7db05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377764373 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3377764373
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3047729290
Short name T508
Test name
Test status
Simulation time 23067434 ps
CPU time 0.98 seconds
Started Aug 02 06:40:19 PM PDT 24
Finished Aug 02 06:40:20 PM PDT 24
Peak memory 215248 kb
Host smart-979d4c2f-4abc-453a-bbb5-587183e3363a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047729290 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3047729290
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3639061028
Short name T111
Test name
Test status
Simulation time 87735146 ps
CPU time 2.38 seconds
Started Aug 02 06:40:18 PM PDT 24
Finished Aug 02 06:40:20 PM PDT 24
Peak memory 217344 kb
Host smart-7177fd20-b0ed-4d58-be06-5583368588bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639061028 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3639061028
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.866966355
Short name T434
Test name
Test status
Simulation time 147163564418 ps
CPU time 1562 seconds
Started Aug 02 06:40:16 PM PDT 24
Finished Aug 02 07:06:19 PM PDT 24
Peak memory 226216 kb
Host smart-52229724-93ab-430f-b57d-560d0842287a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866966355 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.866966355
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.3967678222
Short name T214
Test name
Test status
Simulation time 26841185 ps
CPU time 1.24 seconds
Started Aug 02 06:42:25 PM PDT 24
Finished Aug 02 06:42:26 PM PDT 24
Peak memory 215768 kb
Host smart-fc8eb6ba-9b81-4775-a403-7d4133b16225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967678222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.3967678222
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.979418441
Short name T703
Test name
Test status
Simulation time 612624512 ps
CPU time 3.95 seconds
Started Aug 02 06:42:22 PM PDT 24
Finished Aug 02 06:42:27 PM PDT 24
Peak memory 220260 kb
Host smart-330c923a-6933-4145-bc8d-740228113938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979418441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.979418441
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.3605269515
Short name T279
Test name
Test status
Simulation time 68112127 ps
CPU time 1.17 seconds
Started Aug 02 06:42:24 PM PDT 24
Finished Aug 02 06:42:25 PM PDT 24
Peak memory 218732 kb
Host smart-9a6b5513-8e5b-47c0-87d4-07f37ae45bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605269515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.3605269515
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3310332037
Short name T879
Test name
Test status
Simulation time 35452812 ps
CPU time 1.48 seconds
Started Aug 02 06:42:24 PM PDT 24
Finished Aug 02 06:42:26 PM PDT 24
Peak memory 218488 kb
Host smart-2885e3d6-0133-43b4-b83d-422d38b9fae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310332037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3310332037
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.1944910089
Short name T631
Test name
Test status
Simulation time 41335120 ps
CPU time 1.45 seconds
Started Aug 02 06:42:21 PM PDT 24
Finished Aug 02 06:42:22 PM PDT 24
Peak memory 219504 kb
Host smart-6ea855f1-eacd-4e90-a004-de1ff55f8327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944910089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1944910089
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.3165138710
Short name T901
Test name
Test status
Simulation time 68482043 ps
CPU time 1.21 seconds
Started Aug 02 06:42:21 PM PDT 24
Finished Aug 02 06:42:22 PM PDT 24
Peak memory 218636 kb
Host smart-51b2f232-575b-4670-a679-24b0d7737d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165138710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3165138710
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.2150318428
Short name T366
Test name
Test status
Simulation time 69912608 ps
CPU time 1.17 seconds
Started Aug 02 06:42:21 PM PDT 24
Finished Aug 02 06:42:22 PM PDT 24
Peak memory 217312 kb
Host smart-84a51548-7fe3-447c-a9e5-4c0adf3ee868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150318428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2150318428
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.2094576585
Short name T549
Test name
Test status
Simulation time 86741155 ps
CPU time 1.23 seconds
Started Aug 02 06:42:20 PM PDT 24
Finished Aug 02 06:42:22 PM PDT 24
Peak memory 220800 kb
Host smart-8a5f3bc6-27a5-4bc5-9e1c-6319a129f630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094576585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.2094576585
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.2936343210
Short name T427
Test name
Test status
Simulation time 33358390 ps
CPU time 1.43 seconds
Started Aug 02 06:42:21 PM PDT 24
Finished Aug 02 06:42:22 PM PDT 24
Peak memory 219564 kb
Host smart-bc6f6ca1-8eec-4014-a991-5c7d39b25ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936343210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2936343210
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.4207699024
Short name T215
Test name
Test status
Simulation time 53881452 ps
CPU time 1.24 seconds
Started Aug 02 06:42:22 PM PDT 24
Finished Aug 02 06:42:24 PM PDT 24
Peak memory 221304 kb
Host smart-c1629893-7808-4666-b53d-18d152737945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207699024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.4207699024
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.2541905654
Short name T769
Test name
Test status
Simulation time 270293062 ps
CPU time 1.13 seconds
Started Aug 02 06:42:21 PM PDT 24
Finished Aug 02 06:42:23 PM PDT 24
Peak memory 217360 kb
Host smart-729469c6-7ddc-4a15-870d-f650b0bcfdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541905654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2541905654
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.2689608765
Short name T953
Test name
Test status
Simulation time 242658344 ps
CPU time 1.39 seconds
Started Aug 02 06:42:20 PM PDT 24
Finished Aug 02 06:42:22 PM PDT 24
Peak memory 220044 kb
Host smart-8a039ee3-d9b3-4575-b363-b1d2d8c87e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689608765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.2689608765
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.1259042768
Short name T373
Test name
Test status
Simulation time 72554759 ps
CPU time 1.1 seconds
Started Aug 02 06:42:23 PM PDT 24
Finished Aug 02 06:42:24 PM PDT 24
Peak memory 217560 kb
Host smart-8b7db41c-ea1e-4c90-b35a-a9eef56c6142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259042768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1259042768
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.1895122987
Short name T597
Test name
Test status
Simulation time 28511809 ps
CPU time 1.3 seconds
Started Aug 02 06:42:21 PM PDT 24
Finished Aug 02 06:42:22 PM PDT 24
Peak memory 219648 kb
Host smart-5e75808e-e005-4892-8a7c-5b9ce4cda7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895122987 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1895122987
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.4258482974
Short name T364
Test name
Test status
Simulation time 177337341 ps
CPU time 1.74 seconds
Started Aug 02 06:42:26 PM PDT 24
Finished Aug 02 06:42:28 PM PDT 24
Peak memory 218864 kb
Host smart-b688a06a-eacd-488a-88ab-d3617e62c13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258482974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.4258482974
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3736291079
Short name T948
Test name
Test status
Simulation time 26062213 ps
CPU time 1.16 seconds
Started Aug 02 06:42:25 PM PDT 24
Finished Aug 02 06:42:26 PM PDT 24
Peak memory 215760 kb
Host smart-28476995-74d7-4a96-98d7-3a4134b7f30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736291079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3736291079
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1615256176
Short name T416
Test name
Test status
Simulation time 49266635 ps
CPU time 1.78 seconds
Started Aug 02 06:42:22 PM PDT 24
Finished Aug 02 06:42:24 PM PDT 24
Peak memory 218632 kb
Host smart-bf6c5c1d-c63f-434b-b85e-8d54db38d008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615256176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1615256176
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.4077913004
Short name T496
Test name
Test status
Simulation time 22386730 ps
CPU time 1.15 seconds
Started Aug 02 06:42:25 PM PDT 24
Finished Aug 02 06:42:26 PM PDT 24
Peak memory 218888 kb
Host smart-ff503efa-640a-44bd-b7a5-66346446c8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077913004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.4077913004
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.168543778
Short name T770
Test name
Test status
Simulation time 109839401 ps
CPU time 2.48 seconds
Started Aug 02 06:42:25 PM PDT 24
Finished Aug 02 06:42:28 PM PDT 24
Peak memory 220184 kb
Host smart-4ebf6683-1cc2-4105-9af8-9f91bf003164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168543778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.168543778
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3508734695
Short name T884
Test name
Test status
Simulation time 64830537 ps
CPU time 1.1 seconds
Started Aug 02 06:40:29 PM PDT 24
Finished Aug 02 06:40:30 PM PDT 24
Peak memory 219684 kb
Host smart-e6aba6a7-3a96-4bf9-93db-4ed0aa17cec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508734695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3508734695
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.336115110
Short name T825
Test name
Test status
Simulation time 83036786 ps
CPU time 0.9 seconds
Started Aug 02 06:40:28 PM PDT 24
Finished Aug 02 06:40:29 PM PDT 24
Peak memory 206808 kb
Host smart-421432bc-5d21-4070-b72c-57bef12a3084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336115110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.336115110
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2057723380
Short name T927
Test name
Test status
Simulation time 10965150 ps
CPU time 0.9 seconds
Started Aug 02 06:40:31 PM PDT 24
Finished Aug 02 06:40:32 PM PDT 24
Peak memory 216236 kb
Host smart-c3a00cff-bf8c-42dc-bffa-24d30bcfa79c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057723380 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2057723380
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2077328068
Short name T359
Test name
Test status
Simulation time 54067903 ps
CPU time 0.97 seconds
Started Aug 02 06:40:24 PM PDT 24
Finished Aug 02 06:40:25 PM PDT 24
Peak memory 218436 kb
Host smart-0f116d94-ba69-4fd8-a389-d80625138177
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077328068 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2077328068
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2279094315
Short name T126
Test name
Test status
Simulation time 121538908 ps
CPU time 0.95 seconds
Started Aug 02 06:40:27 PM PDT 24
Finished Aug 02 06:40:28 PM PDT 24
Peak memory 219688 kb
Host smart-6496201b-be96-4824-b110-b00e03657ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279094315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2279094315
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.143732596
Short name T412
Test name
Test status
Simulation time 107805694 ps
CPU time 1.68 seconds
Started Aug 02 06:40:16 PM PDT 24
Finished Aug 02 06:40:18 PM PDT 24
Peak memory 218836 kb
Host smart-43b0410a-ebf5-49c5-bc7e-ca66ba94ab4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143732596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.143732596
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3130094096
Short name T504
Test name
Test status
Simulation time 23214624 ps
CPU time 1.09 seconds
Started Aug 02 06:40:27 PM PDT 24
Finished Aug 02 06:40:29 PM PDT 24
Peak memory 215536 kb
Host smart-97191372-d3da-45fd-bf8a-411580bfbbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130094096 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3130094096
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.951240295
Short name T689
Test name
Test status
Simulation time 32974463 ps
CPU time 0.96 seconds
Started Aug 02 06:40:20 PM PDT 24
Finished Aug 02 06:40:21 PM PDT 24
Peak memory 215268 kb
Host smart-2f475057-3f93-4384-b965-d4d29b56236c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951240295 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.951240295
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.4121331739
Short name T759
Test name
Test status
Simulation time 84521642 ps
CPU time 2.25 seconds
Started Aug 02 06:40:17 PM PDT 24
Finished Aug 02 06:40:20 PM PDT 24
Peak memory 215312 kb
Host smart-895e04ae-d1f3-435d-b12f-39673765ff62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121331739 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.4121331739
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.521855361
Short name T856
Test name
Test status
Simulation time 107212461278 ps
CPU time 1304.73 seconds
Started Aug 02 06:40:31 PM PDT 24
Finished Aug 02 07:02:15 PM PDT 24
Peak memory 224888 kb
Host smart-2b917e9d-7b69-4c51-98cd-727745933ce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521855361 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.521855361
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.2690571340
Short name T476
Test name
Test status
Simulation time 62144226 ps
CPU time 1.15 seconds
Started Aug 02 06:42:25 PM PDT 24
Finished Aug 02 06:42:26 PM PDT 24
Peak memory 218464 kb
Host smart-316513f2-9444-4f45-af16-c051dbef3a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690571340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.2690571340
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.3197176838
Short name T25
Test name
Test status
Simulation time 89095243 ps
CPU time 1.35 seconds
Started Aug 02 06:42:26 PM PDT 24
Finished Aug 02 06:42:28 PM PDT 24
Peak memory 217284 kb
Host smart-3d39f2d8-ff70-4e50-9d0f-fef27d77342e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197176838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3197176838
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.2218592273
Short name T317
Test name
Test status
Simulation time 59077999 ps
CPU time 1.63 seconds
Started Aug 02 06:42:22 PM PDT 24
Finished Aug 02 06:42:24 PM PDT 24
Peak memory 218620 kb
Host smart-49c8ba3b-49e0-470f-a63b-4183bf91e039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218592273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2218592273
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.337667745
Short name T576
Test name
Test status
Simulation time 23619499 ps
CPU time 1.18 seconds
Started Aug 02 06:42:23 PM PDT 24
Finished Aug 02 06:42:25 PM PDT 24
Peak memory 220792 kb
Host smart-9fa682d2-4797-490a-ada8-f8386ad01b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337667745 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.337667745
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.3288583813
Short name T718
Test name
Test status
Simulation time 30161413 ps
CPU time 1 seconds
Started Aug 02 06:42:23 PM PDT 24
Finished Aug 02 06:42:24 PM PDT 24
Peak memory 217372 kb
Host smart-8c8377ab-8aa6-418e-a933-a0f8390cb81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288583813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3288583813
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.2296791045
Short name T955
Test name
Test status
Simulation time 67886868 ps
CPU time 1.09 seconds
Started Aug 02 06:42:25 PM PDT 24
Finished Aug 02 06:42:26 PM PDT 24
Peak memory 219924 kb
Host smart-c049d9ad-4445-4520-a9ec-5bbac0e147a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296791045 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.2296791045
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.3069748036
Short name T727
Test name
Test status
Simulation time 27869985 ps
CPU time 1.3 seconds
Started Aug 02 06:42:23 PM PDT 24
Finished Aug 02 06:42:25 PM PDT 24
Peak memory 220224 kb
Host smart-b47c5979-f53e-44e1-8495-ba84409e60db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069748036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3069748036
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.4196060675
Short name T817
Test name
Test status
Simulation time 30747671 ps
CPU time 1.3 seconds
Started Aug 02 06:42:24 PM PDT 24
Finished Aug 02 06:42:25 PM PDT 24
Peak memory 219776 kb
Host smart-1971a65f-6a6f-4d0b-8f39-9f352b332905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196060675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.4196060675
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3825116823
Short name T622
Test name
Test status
Simulation time 96266261 ps
CPU time 1.17 seconds
Started Aug 02 06:42:23 PM PDT 24
Finished Aug 02 06:42:24 PM PDT 24
Peak memory 219340 kb
Host smart-1e5c07de-1be4-4cd7-884c-dfc3f3618c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825116823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3825116823
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.1736585705
Short name T690
Test name
Test status
Simulation time 104536857 ps
CPU time 1.17 seconds
Started Aug 02 06:42:22 PM PDT 24
Finished Aug 02 06:42:23 PM PDT 24
Peak memory 219188 kb
Host smart-56e51944-6553-4943-983a-cc47f1086ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736585705 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.1736585705
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.271544029
Short name T582
Test name
Test status
Simulation time 41833401 ps
CPU time 1.58 seconds
Started Aug 02 06:42:25 PM PDT 24
Finished Aug 02 06:42:27 PM PDT 24
Peak memory 218588 kb
Host smart-f524d008-2c7d-44da-a83a-624736fffae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271544029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.271544029
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.64142364
Short name T251
Test name
Test status
Simulation time 29185016 ps
CPU time 1.28 seconds
Started Aug 02 06:42:26 PM PDT 24
Finished Aug 02 06:42:27 PM PDT 24
Peak memory 219348 kb
Host smart-ab832227-8ed1-4a77-88ee-c1bdb122af76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64142364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.64142364
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/167.edn_alert.3452506787
Short name T943
Test name
Test status
Simulation time 135470522 ps
CPU time 1.31 seconds
Started Aug 02 06:42:23 PM PDT 24
Finished Aug 02 06:42:25 PM PDT 24
Peak memory 218892 kb
Host smart-2f8d74e1-c129-4a2d-8507-1c8f9188a6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452506787 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.3452506787
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2629878372
Short name T461
Test name
Test status
Simulation time 60248113 ps
CPU time 1.27 seconds
Started Aug 02 06:42:22 PM PDT 24
Finished Aug 02 06:42:24 PM PDT 24
Peak memory 217628 kb
Host smart-da980c9c-455b-46a1-9559-59ce5892f55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629878372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2629878372
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.3234716706
Short name T533
Test name
Test status
Simulation time 42551299 ps
CPU time 1.14 seconds
Started Aug 02 06:42:22 PM PDT 24
Finished Aug 02 06:42:23 PM PDT 24
Peak memory 218724 kb
Host smart-416dd2b0-064b-4f1e-9316-9c0fb9a9877d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234716706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3234716706
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.579424504
Short name T530
Test name
Test status
Simulation time 259701054 ps
CPU time 3.41 seconds
Started Aug 02 06:42:25 PM PDT 24
Finished Aug 02 06:42:28 PM PDT 24
Peak memory 220564 kb
Host smart-c28633fc-e087-4aeb-94ec-e9394aea2165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579424504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.579424504
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.560493299
Short name T726
Test name
Test status
Simulation time 75702573 ps
CPU time 1.5 seconds
Started Aug 02 06:42:25 PM PDT 24
Finished Aug 02 06:42:27 PM PDT 24
Peak memory 219012 kb
Host smart-e39ac792-92ac-47a7-bbe7-3d52ef75c774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560493299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.560493299
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3647512318
Short name T97
Test name
Test status
Simulation time 22984117 ps
CPU time 1.17 seconds
Started Aug 02 06:40:29 PM PDT 24
Finished Aug 02 06:40:31 PM PDT 24
Peak memory 218840 kb
Host smart-471afb48-b860-47ac-9dca-5639a64330bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647512318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3647512318
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3450449874
Short name T785
Test name
Test status
Simulation time 89329784 ps
CPU time 0.84 seconds
Started Aug 02 06:40:24 PM PDT 24
Finished Aug 02 06:40:25 PM PDT 24
Peak memory 215016 kb
Host smart-4f8c4bdd-b180-4bf8-a4c1-67e800fd8fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450449874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3450449874
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2084707572
Short name T906
Test name
Test status
Simulation time 21260521 ps
CPU time 0.88 seconds
Started Aug 02 06:40:26 PM PDT 24
Finished Aug 02 06:40:27 PM PDT 24
Peak memory 215976 kb
Host smart-2bfe4b89-b6b7-4cf2-a2b8-54912b84c634
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084707572 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2084707572
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3218974715
Short name T827
Test name
Test status
Simulation time 78754067 ps
CPU time 1.08 seconds
Started Aug 02 06:40:29 PM PDT 24
Finished Aug 02 06:40:30 PM PDT 24
Peak memory 216968 kb
Host smart-514f4a1b-f444-483d-9eac-0b919adde634
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218974715 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3218974715
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1389113055
Short name T143
Test name
Test status
Simulation time 21871897 ps
CPU time 1.05 seconds
Started Aug 02 06:40:28 PM PDT 24
Finished Aug 02 06:40:29 PM PDT 24
Peak memory 218700 kb
Host smart-4be0815e-ca3a-4d6c-8b4b-2916750cce08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389113055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1389113055
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3307861920
Short name T748
Test name
Test status
Simulation time 74772987 ps
CPU time 1.17 seconds
Started Aug 02 06:40:24 PM PDT 24
Finished Aug 02 06:40:25 PM PDT 24
Peak memory 217388 kb
Host smart-6f732754-61db-4fac-8954-7d0313bf7345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307861920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3307861920
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.2433686955
Short name T854
Test name
Test status
Simulation time 21668542 ps
CPU time 1.1 seconds
Started Aug 02 06:40:31 PM PDT 24
Finished Aug 02 06:40:32 PM PDT 24
Peak memory 224092 kb
Host smart-90fa6f8d-82a9-4bd1-9fab-7d2d0c0f55f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433686955 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2433686955
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2324917255
Short name T722
Test name
Test status
Simulation time 24170618 ps
CPU time 0.95 seconds
Started Aug 02 06:40:26 PM PDT 24
Finished Aug 02 06:40:27 PM PDT 24
Peak memory 215304 kb
Host smart-e564cd2a-d28e-4e86-90a6-7febe5341edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324917255 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2324917255
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2234559554
Short name T244
Test name
Test status
Simulation time 358288023 ps
CPU time 2.29 seconds
Started Aug 02 06:40:32 PM PDT 24
Finished Aug 02 06:40:34 PM PDT 24
Peak memory 219964 kb
Host smart-b38ce48f-5f1d-41e3-8983-8afe35e321fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234559554 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2234559554
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3775784418
Short name T230
Test name
Test status
Simulation time 698745046562 ps
CPU time 1118.13 seconds
Started Aug 02 06:40:23 PM PDT 24
Finished Aug 02 06:59:01 PM PDT 24
Peak memory 231852 kb
Host smart-a89d2c1b-912d-492a-959b-01df3246f44b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775784418 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3775784418
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.818384780
Short name T929
Test name
Test status
Simulation time 30039865 ps
CPU time 1.33 seconds
Started Aug 02 06:42:26 PM PDT 24
Finished Aug 02 06:42:28 PM PDT 24
Peak memory 217488 kb
Host smart-13cbce1b-f8ce-4ae1-bdd9-37fa3683ba60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818384780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.818384780
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1646596050
Short name T62
Test name
Test status
Simulation time 21666025 ps
CPU time 1.17 seconds
Started Aug 02 06:42:35 PM PDT 24
Finished Aug 02 06:42:37 PM PDT 24
Peak memory 220636 kb
Host smart-8452003d-67ea-468c-bd73-eab39847abb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646596050 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1646596050
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/172.edn_alert.4006695464
Short name T287
Test name
Test status
Simulation time 29197141 ps
CPU time 1.3 seconds
Started Aug 02 06:42:32 PM PDT 24
Finished Aug 02 06:42:34 PM PDT 24
Peak memory 219068 kb
Host smart-82ce7c9b-4a8a-407d-820a-0fac23c7c98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006695464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.4006695464
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.2015980989
Short name T711
Test name
Test status
Simulation time 47329708 ps
CPU time 1.59 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 218616 kb
Host smart-f4935f3f-1536-49bb-9fd9-553ca093ea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015980989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2015980989
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3419075840
Short name T863
Test name
Test status
Simulation time 46792074 ps
CPU time 1.24 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:34 PM PDT 24
Peak memory 220416 kb
Host smart-167cca7f-0082-4aac-b175-4fbb149a3fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419075840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3419075840
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.2646349249
Short name T644
Test name
Test status
Simulation time 506956819 ps
CPU time 4.09 seconds
Started Aug 02 06:42:32 PM PDT 24
Finished Aug 02 06:42:36 PM PDT 24
Peak memory 219856 kb
Host smart-b897c0f4-0226-4a62-af52-1c1485c847e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646349249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2646349249
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.1212293743
Short name T285
Test name
Test status
Simulation time 219533548 ps
CPU time 1.23 seconds
Started Aug 02 06:42:36 PM PDT 24
Finished Aug 02 06:42:38 PM PDT 24
Peak memory 219344 kb
Host smart-06a28363-094e-44c8-abe8-40f29c2ff702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212293743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.1212293743
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.1040021951
Short name T580
Test name
Test status
Simulation time 82470063 ps
CPU time 1.45 seconds
Started Aug 02 06:42:35 PM PDT 24
Finished Aug 02 06:42:37 PM PDT 24
Peak memory 218616 kb
Host smart-be2af9ca-1e70-4e60-b422-f78f260f271c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040021951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1040021951
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.692273273
Short name T640
Test name
Test status
Simulation time 42879958 ps
CPU time 1.14 seconds
Started Aug 02 06:42:32 PM PDT 24
Finished Aug 02 06:42:33 PM PDT 24
Peak memory 219412 kb
Host smart-fe1357ad-7c2c-4bb3-9108-c6aca855f0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692273273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.692273273
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.963940126
Short name T535
Test name
Test status
Simulation time 58910193 ps
CPU time 1.45 seconds
Started Aug 02 06:42:36 PM PDT 24
Finished Aug 02 06:42:38 PM PDT 24
Peak memory 218524 kb
Host smart-f3cb1348-d12d-41d5-9ddf-96eccd57f7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963940126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.963940126
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.947386070
Short name T959
Test name
Test status
Simulation time 140468955 ps
CPU time 1.24 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 215656 kb
Host smart-73d3d3b1-5e2b-487e-acc0-86e5a55ade84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947386070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.947386070
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.590102914
Short name T17
Test name
Test status
Simulation time 138483103 ps
CPU time 2.19 seconds
Started Aug 02 06:42:32 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 220140 kb
Host smart-2336e236-22d6-4134-8b5c-1edeafab55db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590102914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.590102914
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2123646273
Short name T204
Test name
Test status
Simulation time 85237981 ps
CPU time 1.21 seconds
Started Aug 02 06:42:32 PM PDT 24
Finished Aug 02 06:42:33 PM PDT 24
Peak memory 219016 kb
Host smart-df085278-b8af-4c8e-97b4-8c54ef292e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123646273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2123646273
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.2217118878
Short name T562
Test name
Test status
Simulation time 47290227 ps
CPU time 1.03 seconds
Started Aug 02 06:42:34 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 219988 kb
Host smart-3af703a8-0d8d-40d3-94d8-1a1f26916b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217118878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2217118878
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2619551369
Short name T517
Test name
Test status
Simulation time 102462957 ps
CPU time 1.31 seconds
Started Aug 02 06:42:35 PM PDT 24
Finished Aug 02 06:42:37 PM PDT 24
Peak memory 215648 kb
Host smart-d12be6e9-6113-4761-bdbc-f6cbdf950142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619551369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2619551369
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.228306617
Short name T754
Test name
Test status
Simulation time 44682152 ps
CPU time 1.39 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 215408 kb
Host smart-d5cd2e54-e776-48d8-8832-a8a5ceb99298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228306617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.228306617
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3469405572
Short name T791
Test name
Test status
Simulation time 27079879 ps
CPU time 1.23 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:34 PM PDT 24
Peak memory 219944 kb
Host smart-b7c62612-7fb8-4c1f-86a8-b71756b3ea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469405572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3469405572
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.3100391844
Short name T31
Test name
Test status
Simulation time 45294038 ps
CPU time 1.8 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 218664 kb
Host smart-fd193f83-9ae3-4191-95b7-fd195bee825c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100391844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3100391844
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1684008970
Short name T497
Test name
Test status
Simulation time 41743305 ps
CPU time 1.17 seconds
Started Aug 02 06:40:27 PM PDT 24
Finished Aug 02 06:40:28 PM PDT 24
Peak memory 220080 kb
Host smart-48a1a527-08c6-44a9-b5c0-1b4753c00ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684008970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1684008970
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2856249150
Short name T634
Test name
Test status
Simulation time 44126777 ps
CPU time 0.85 seconds
Started Aug 02 06:40:22 PM PDT 24
Finished Aug 02 06:40:23 PM PDT 24
Peak memory 206700 kb
Host smart-8d51b2e0-6677-4256-a16f-060c33828a0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856249150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2856249150
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.74411394
Short name T911
Test name
Test status
Simulation time 10954652 ps
CPU time 0.89 seconds
Started Aug 02 06:40:24 PM PDT 24
Finished Aug 02 06:40:25 PM PDT 24
Peak memory 216328 kb
Host smart-8d1fa112-3ae7-4a11-9616-12c26ac51b95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74411394 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.74411394
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1380064362
Short name T464
Test name
Test status
Simulation time 59763240 ps
CPU time 1.24 seconds
Started Aug 02 06:40:23 PM PDT 24
Finished Aug 02 06:40:24 PM PDT 24
Peak memory 216888 kb
Host smart-a5b1c7b6-3d56-4556-9080-7dabcca4c792
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380064362 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1380064362
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3499379178
Short name T936
Test name
Test status
Simulation time 22030243 ps
CPU time 0.9 seconds
Started Aug 02 06:40:25 PM PDT 24
Finished Aug 02 06:40:27 PM PDT 24
Peak memory 218292 kb
Host smart-7adab058-a65b-40c3-94b2-57bf08eca0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499379178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3499379178
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2298448301
Short name T75
Test name
Test status
Simulation time 71778994 ps
CPU time 1.4 seconds
Started Aug 02 06:40:25 PM PDT 24
Finished Aug 02 06:40:26 PM PDT 24
Peak memory 217296 kb
Host smart-608d0fb9-7b3e-415b-b64a-b3c043b28d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298448301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2298448301
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1965013078
Short name T81
Test name
Test status
Simulation time 25993326 ps
CPU time 1 seconds
Started Aug 02 06:40:25 PM PDT 24
Finished Aug 02 06:40:26 PM PDT 24
Peak memory 216040 kb
Host smart-26ee940e-9a83-402f-a3fa-3314172bef12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965013078 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1965013078
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.425491544
Short name T741
Test name
Test status
Simulation time 19287716 ps
CPU time 1.11 seconds
Started Aug 02 06:40:26 PM PDT 24
Finished Aug 02 06:40:27 PM PDT 24
Peak memory 215308 kb
Host smart-47d7864b-7d4a-4bbf-8c68-3cdc7a4ac65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425491544 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.425491544
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2352118212
Short name T920
Test name
Test status
Simulation time 387346809 ps
CPU time 3.4 seconds
Started Aug 02 06:40:26 PM PDT 24
Finished Aug 02 06:40:29 PM PDT 24
Peak memory 215252 kb
Host smart-74d87b4a-5f73-44a3-8d8e-a02906756062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352118212 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2352118212
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1695557076
Short name T232
Test name
Test status
Simulation time 391817169211 ps
CPU time 573.32 seconds
Started Aug 02 06:40:27 PM PDT 24
Finished Aug 02 06:50:00 PM PDT 24
Peak memory 219128 kb
Host smart-7977432a-f075-4875-a9ad-b77e3d73bbcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695557076 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1695557076
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.3790508503
Short name T171
Test name
Test status
Simulation time 107459962 ps
CPU time 1.26 seconds
Started Aug 02 06:42:36 PM PDT 24
Finished Aug 02 06:42:37 PM PDT 24
Peak memory 220384 kb
Host smart-a3a64fe8-5fab-43cd-be15-5375df182ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790508503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.3790508503
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2954020603
Short name T857
Test name
Test status
Simulation time 262438866 ps
CPU time 1.76 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 218864 kb
Host smart-060b2b48-3a19-4b2a-941c-db82d147f86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954020603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2954020603
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.4085321887
Short name T105
Test name
Test status
Simulation time 23207688 ps
CPU time 1.2 seconds
Started Aug 02 06:42:35 PM PDT 24
Finished Aug 02 06:42:36 PM PDT 24
Peak memory 219564 kb
Host smart-d2e77e9b-bd74-4763-82f6-f69be3d5715c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085321887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.4085321887
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.1874412985
Short name T383
Test name
Test status
Simulation time 31455765 ps
CPU time 0.95 seconds
Started Aug 02 06:42:34 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 217428 kb
Host smart-0d16ceeb-2cca-4fdc-b1d2-9459fb217103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874412985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1874412985
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3014345760
Short name T795
Test name
Test status
Simulation time 40921641 ps
CPU time 1.14 seconds
Started Aug 02 06:42:31 PM PDT 24
Finished Aug 02 06:42:32 PM PDT 24
Peak memory 219696 kb
Host smart-c3d411e3-c010-4612-9b5c-bbb2f2469749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014345760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3014345760
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.469201613
Short name T545
Test name
Test status
Simulation time 67575866 ps
CPU time 1.35 seconds
Started Aug 02 06:42:32 PM PDT 24
Finished Aug 02 06:42:34 PM PDT 24
Peak memory 218504 kb
Host smart-9563a665-0181-4a2f-b0fa-4643a0057a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469201613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.469201613
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.3379828924
Short name T816
Test name
Test status
Simulation time 146049040 ps
CPU time 1.1 seconds
Started Aug 02 06:42:31 PM PDT 24
Finished Aug 02 06:42:32 PM PDT 24
Peak memory 218532 kb
Host smart-e5a93eba-48dd-4e09-9dee-36485813e0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379828924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.3379828924
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.384905023
Short name T773
Test name
Test status
Simulation time 43363084 ps
CPU time 1.83 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 220096 kb
Host smart-81e4bf53-a4ab-4ca1-814e-2e356bbafb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384905023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.384905023
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.332418496
Short name T694
Test name
Test status
Simulation time 26029268 ps
CPU time 1.29 seconds
Started Aug 02 06:42:32 PM PDT 24
Finished Aug 02 06:42:34 PM PDT 24
Peak memory 219564 kb
Host smart-2fb572d0-3bf0-4f23-b53e-f8559bdf24f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332418496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.332418496
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/185.edn_alert.2298892761
Short name T217
Test name
Test status
Simulation time 71795200 ps
CPU time 1.1 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:34 PM PDT 24
Peak memory 219460 kb
Host smart-a4424fcd-fdc5-4a64-a64e-ae2821ce56f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298892761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2298892761
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.3184357751
Short name T13
Test name
Test status
Simulation time 43892995 ps
CPU time 1.55 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 217488 kb
Host smart-f9d821fd-69e4-4bd4-8b13-f90a0786eb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184357751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3184357751
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.4118254835
Short name T563
Test name
Test status
Simulation time 23671670 ps
CPU time 1.21 seconds
Started Aug 02 06:42:34 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 219544 kb
Host smart-8743f75b-6bbd-4457-96fd-908794ca4952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118254835 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.4118254835
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.3744047859
Short name T455
Test name
Test status
Simulation time 35380158 ps
CPU time 1.33 seconds
Started Aug 02 06:42:39 PM PDT 24
Finished Aug 02 06:42:40 PM PDT 24
Peak memory 220004 kb
Host smart-bf842fa3-860d-44cd-b405-cfbacb4f539b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744047859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3744047859
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.2398523755
Short name T651
Test name
Test status
Simulation time 52345929 ps
CPU time 1.3 seconds
Started Aug 02 06:42:35 PM PDT 24
Finished Aug 02 06:42:36 PM PDT 24
Peak memory 215648 kb
Host smart-e8a0459f-f57e-449e-9f62-a642f530726b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398523755 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.2398523755
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.4134277062
Short name T478
Test name
Test status
Simulation time 39315397 ps
CPU time 1.53 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 219784 kb
Host smart-4bc94641-cd53-4e1c-b7d7-01702d59b681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134277062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.4134277062
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2474228982
Short name T560
Test name
Test status
Simulation time 61481348 ps
CPU time 1.31 seconds
Started Aug 02 06:42:38 PM PDT 24
Finished Aug 02 06:42:39 PM PDT 24
Peak memory 215680 kb
Host smart-ee5d41b3-4dc3-420f-b9ea-2c402de867d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474228982 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2474228982
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.1100921670
Short name T445
Test name
Test status
Simulation time 31370958 ps
CPU time 1.51 seconds
Started Aug 02 06:42:35 PM PDT 24
Finished Aug 02 06:42:37 PM PDT 24
Peak memory 217796 kb
Host smart-0c613acb-e270-4690-bb6a-806464734bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100921670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1100921670
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3391894291
Short name T3
Test name
Test status
Simulation time 76776365 ps
CPU time 1.11 seconds
Started Aug 02 06:42:31 PM PDT 24
Finished Aug 02 06:42:32 PM PDT 24
Peak memory 215688 kb
Host smart-0e8feeb9-7190-4b27-a9b2-dddaca890abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391894291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3391894291
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.882118393
Short name T782
Test name
Test status
Simulation time 52037935 ps
CPU time 1.88 seconds
Started Aug 02 06:42:34 PM PDT 24
Finished Aug 02 06:42:36 PM PDT 24
Peak memory 218468 kb
Host smart-80aec2bb-4e33-422b-98a2-a1cf53aec925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882118393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.882118393
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.56613932
Short name T65
Test name
Test status
Simulation time 112966991 ps
CPU time 1.13 seconds
Started Aug 02 06:40:29 PM PDT 24
Finished Aug 02 06:40:31 PM PDT 24
Peak memory 218632 kb
Host smart-79c9ca9b-736a-4ab5-9a5e-e8137d88b70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56613932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.56613932
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2672736104
Short name T547
Test name
Test status
Simulation time 26751963 ps
CPU time 0.9 seconds
Started Aug 02 06:40:26 PM PDT 24
Finished Aug 02 06:40:27 PM PDT 24
Peak memory 206768 kb
Host smart-516acdea-e63d-4df4-a24b-bbeea370a7d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672736104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2672736104
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2103505425
Short name T596
Test name
Test status
Simulation time 12433341 ps
CPU time 0.98 seconds
Started Aug 02 06:40:24 PM PDT 24
Finished Aug 02 06:40:25 PM PDT 24
Peak memory 216112 kb
Host smart-20a815da-c177-4b7f-83f0-4b7f78a63e42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103505425 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2103505425
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.282822115
Short name T729
Test name
Test status
Simulation time 85464616 ps
CPU time 1.01 seconds
Started Aug 02 06:40:30 PM PDT 24
Finished Aug 02 06:40:31 PM PDT 24
Peak memory 218684 kb
Host smart-c42019b6-558b-4f4c-8510-a6f968d5ca2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282822115 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.282822115
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.978235057
Short name T152
Test name
Test status
Simulation time 27888335 ps
CPU time 1.28 seconds
Started Aug 02 06:40:27 PM PDT 24
Finished Aug 02 06:40:28 PM PDT 24
Peak memory 220548 kb
Host smart-eca3e38a-93fd-4d0d-9357-150f2e9ebb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978235057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.978235057
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1296616659
Short name T365
Test name
Test status
Simulation time 66844884 ps
CPU time 1.34 seconds
Started Aug 02 06:40:31 PM PDT 24
Finished Aug 02 06:40:33 PM PDT 24
Peak memory 218600 kb
Host smart-08f2e515-534a-4694-9fdf-87a1fc5f5606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296616659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1296616659
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2487897881
Short name T605
Test name
Test status
Simulation time 27907159 ps
CPU time 0.9 seconds
Started Aug 02 06:40:31 PM PDT 24
Finished Aug 02 06:40:32 PM PDT 24
Peak memory 215960 kb
Host smart-ac890ddd-e8a7-4032-9905-0087fdff2a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487897881 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2487897881
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3507710666
Short name T433
Test name
Test status
Simulation time 14147365 ps
CPU time 0.99 seconds
Started Aug 02 06:40:33 PM PDT 24
Finished Aug 02 06:40:35 PM PDT 24
Peak memory 215264 kb
Host smart-a2989329-155f-4aac-8ad6-5944081cdf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507710666 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3507710666
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1576140278
Short name T869
Test name
Test status
Simulation time 432737248 ps
CPU time 4.34 seconds
Started Aug 02 06:40:26 PM PDT 24
Finished Aug 02 06:40:30 PM PDT 24
Peak memory 217140 kb
Host smart-5744d600-f06c-42e6-aba5-5c80f41768d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576140278 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1576140278
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.684091340
Short name T529
Test name
Test status
Simulation time 42739199919 ps
CPU time 968.5 seconds
Started Aug 02 06:40:25 PM PDT 24
Finished Aug 02 06:56:34 PM PDT 24
Peak memory 219656 kb
Host smart-3309ea21-55aa-4872-a4c0-3edf1bc8a77c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684091340 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.684091340
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.2445460771
Short name T590
Test name
Test status
Simulation time 38374080 ps
CPU time 1.09 seconds
Started Aug 02 06:42:40 PM PDT 24
Finished Aug 02 06:42:41 PM PDT 24
Peak memory 220812 kb
Host smart-34562c30-1fae-4b36-b31a-03daadfefe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445460771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2445460771
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3118867928
Short name T813
Test name
Test status
Simulation time 68341655 ps
CPU time 2.23 seconds
Started Aug 02 06:42:32 PM PDT 24
Finished Aug 02 06:42:34 PM PDT 24
Peak memory 217488 kb
Host smart-701d2265-227a-4b3a-82fa-4f7a47e648f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118867928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3118867928
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.1781145208
Short name T282
Test name
Test status
Simulation time 225324718 ps
CPU time 1.31 seconds
Started Aug 02 06:42:31 PM PDT 24
Finished Aug 02 06:42:32 PM PDT 24
Peak memory 215824 kb
Host smart-bab212ab-9255-4abc-ac0e-cd414ac991c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781145208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.1781145208
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.2291528936
Short name T248
Test name
Test status
Simulation time 73661776 ps
CPU time 1.05 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:34 PM PDT 24
Peak memory 217216 kb
Host smart-57371bca-7702-4763-b501-bda7e7114bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291528936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2291528936
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.4161948541
Short name T280
Test name
Test status
Simulation time 54633711 ps
CPU time 1.24 seconds
Started Aug 02 06:42:36 PM PDT 24
Finished Aug 02 06:42:38 PM PDT 24
Peak memory 215676 kb
Host smart-b222260b-0e97-4640-bb6c-b2f2cf3ce5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161948541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.4161948541
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2676385704
Short name T346
Test name
Test status
Simulation time 49971847 ps
CPU time 1.11 seconds
Started Aug 02 06:42:36 PM PDT 24
Finished Aug 02 06:42:38 PM PDT 24
Peak memory 219032 kb
Host smart-b7f0ccd2-08f0-4d9f-85b2-466480dc7ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676385704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2676385704
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.1625021573
Short name T64
Test name
Test status
Simulation time 47056032 ps
CPU time 1.26 seconds
Started Aug 02 06:42:39 PM PDT 24
Finished Aug 02 06:42:40 PM PDT 24
Peak memory 218348 kb
Host smart-67905823-8563-4135-9345-c48886bc68dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625021573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.1625021573
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.2523433007
Short name T332
Test name
Test status
Simulation time 107686140 ps
CPU time 1.57 seconds
Started Aug 02 06:42:39 PM PDT 24
Finished Aug 02 06:42:41 PM PDT 24
Peak memory 218720 kb
Host smart-128d002d-7205-4a4d-9dd6-02510d239600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523433007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2523433007
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.1578563591
Short name T166
Test name
Test status
Simulation time 45881335 ps
CPU time 1.23 seconds
Started Aug 02 06:42:38 PM PDT 24
Finished Aug 02 06:42:39 PM PDT 24
Peak memory 219700 kb
Host smart-35c0d40e-36ca-460c-a03a-e1534bbcbb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578563591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.1578563591
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.908924175
Short name T766
Test name
Test status
Simulation time 157142629 ps
CPU time 1.2 seconds
Started Aug 02 06:42:37 PM PDT 24
Finished Aug 02 06:42:39 PM PDT 24
Peak memory 217156 kb
Host smart-4f6ef2ec-470f-4a5c-a6e6-13b4884a1cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908924175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.908924175
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.1546823569
Short name T667
Test name
Test status
Simulation time 263437735 ps
CPU time 1.13 seconds
Started Aug 02 06:42:38 PM PDT 24
Finished Aug 02 06:42:39 PM PDT 24
Peak memory 219652 kb
Host smart-f31abdac-afd5-4a8f-ba20-315c6aacae68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546823569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.1546823569
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3902434778
Short name T376
Test name
Test status
Simulation time 91314475 ps
CPU time 1.19 seconds
Started Aug 02 06:42:38 PM PDT 24
Finished Aug 02 06:42:39 PM PDT 24
Peak memory 217348 kb
Host smart-57866846-2c32-49df-84b9-0a94ebf6ce6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902434778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3902434778
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.3549001312
Short name T218
Test name
Test status
Simulation time 85998587 ps
CPU time 1.12 seconds
Started Aug 02 06:42:35 PM PDT 24
Finished Aug 02 06:42:36 PM PDT 24
Peak memory 219516 kb
Host smart-5f8f854a-f38d-4bb0-b79a-519461c57083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549001312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.3549001312
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.840107325
Short name T743
Test name
Test status
Simulation time 86052975 ps
CPU time 1.52 seconds
Started Aug 02 06:42:38 PM PDT 24
Finished Aug 02 06:42:40 PM PDT 24
Peak memory 218696 kb
Host smart-c27d3884-63cc-4f10-884f-5955a5598179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840107325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.840107325
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.1695917432
Short name T987
Test name
Test status
Simulation time 222380975 ps
CPU time 1.27 seconds
Started Aug 02 06:42:38 PM PDT 24
Finished Aug 02 06:42:40 PM PDT 24
Peak memory 219728 kb
Host smart-f81adbea-f30a-4181-b7a3-303629beec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695917432 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.1695917432
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.299213834
Short name T803
Test name
Test status
Simulation time 56584434 ps
CPU time 1.05 seconds
Started Aug 02 06:42:38 PM PDT 24
Finished Aug 02 06:42:39 PM PDT 24
Peak memory 219732 kb
Host smart-6b1f8a8f-bff8-476a-9ef0-00b2e198f3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299213834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.299213834
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.2847938927
Short name T988
Test name
Test status
Simulation time 36593037 ps
CPU time 1.35 seconds
Started Aug 02 06:42:32 PM PDT 24
Finished Aug 02 06:42:33 PM PDT 24
Peak memory 215668 kb
Host smart-f8e974f2-4497-4191-b26b-e2cb43338f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847938927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2847938927
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3563560939
Short name T624
Test name
Test status
Simulation time 27904289 ps
CPU time 1.25 seconds
Started Aug 02 06:42:42 PM PDT 24
Finished Aug 02 06:42:43 PM PDT 24
Peak memory 218620 kb
Host smart-6becb336-d4a7-4fe7-a47d-c4bff6809ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563560939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3563560939
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.3237979499
Short name T810
Test name
Test status
Simulation time 31017127 ps
CPU time 1.31 seconds
Started Aug 02 06:42:40 PM PDT 24
Finished Aug 02 06:42:42 PM PDT 24
Peak memory 219752 kb
Host smart-bd38e50b-b1ef-4299-bee4-30f5063da48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237979499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.3237979499
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.1172214693
Short name T974
Test name
Test status
Simulation time 52490968 ps
CPU time 1.15 seconds
Started Aug 02 06:42:41 PM PDT 24
Finished Aug 02 06:42:42 PM PDT 24
Peak memory 217200 kb
Host smart-012569f2-3138-41c8-bf9a-7db94cb69028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172214693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1172214693
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1097784942
Short name T149
Test name
Test status
Simulation time 83379952 ps
CPU time 1.16 seconds
Started Aug 02 06:39:58 PM PDT 24
Finished Aug 02 06:39:59 PM PDT 24
Peak memory 218536 kb
Host smart-9d25d3cd-427a-43cf-b6f3-15fe12329b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097784942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1097784942
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2153141255
Short name T868
Test name
Test status
Simulation time 21083396 ps
CPU time 1.03 seconds
Started Aug 02 06:39:52 PM PDT 24
Finished Aug 02 06:39:53 PM PDT 24
Peak memory 214868 kb
Host smart-be74d3a2-d365-4353-95ba-2a50dea46384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153141255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2153141255
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3912008048
Short name T191
Test name
Test status
Simulation time 22512438 ps
CPU time 0.88 seconds
Started Aug 02 06:39:54 PM PDT 24
Finished Aug 02 06:39:55 PM PDT 24
Peak memory 216288 kb
Host smart-3bdf1465-d7b2-44e8-b031-0874cc3adea2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912008048 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3912008048
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.1242668098
Short name T163
Test name
Test status
Simulation time 24423996 ps
CPU time 1.16 seconds
Started Aug 02 06:39:54 PM PDT 24
Finished Aug 02 06:39:55 PM PDT 24
Peak memory 219820 kb
Host smart-6a9de683-83c3-4780-927c-674b962f6841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242668098 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1242668098
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1595107155
Short name T342
Test name
Test status
Simulation time 57853337 ps
CPU time 1.49 seconds
Started Aug 02 06:39:48 PM PDT 24
Finished Aug 02 06:39:49 PM PDT 24
Peak memory 217524 kb
Host smart-b95669eb-2dd8-4b18-aebe-77804dabfa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595107155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1595107155
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.3557559817
Short name T862
Test name
Test status
Simulation time 19850194 ps
CPU time 1.05 seconds
Started Aug 02 06:39:48 PM PDT 24
Finished Aug 02 06:39:49 PM PDT 24
Peak memory 207140 kb
Host smart-56308169-76f0-4bc2-ab14-36ca5437aa6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557559817 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3557559817
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.249461732
Short name T671
Test name
Test status
Simulation time 111322337 ps
CPU time 0.91 seconds
Started Aug 02 06:39:47 PM PDT 24
Finished Aug 02 06:39:48 PM PDT 24
Peak memory 215348 kb
Host smart-62b3fb87-648f-445c-a75d-45d2cdfdacf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249461732 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.249461732
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2412638092
Short name T243
Test name
Test status
Simulation time 245033896 ps
CPU time 1.95 seconds
Started Aug 02 06:39:49 PM PDT 24
Finished Aug 02 06:39:51 PM PDT 24
Peak memory 215328 kb
Host smart-d20e2075-ab25-41be-ac0b-bfb415f4ae62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412638092 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2412638092
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2378609461
Short name T233
Test name
Test status
Simulation time 52615690352 ps
CPU time 1106.93 seconds
Started Aug 02 06:40:02 PM PDT 24
Finished Aug 02 06:58:29 PM PDT 24
Peak memory 223656 kb
Host smart-3d81e2ee-0ba5-4b8c-bf79-2a09b8a47a80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378609461 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2378609461
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1608954427
Short name T308
Test name
Test status
Simulation time 25552917 ps
CPU time 1.22 seconds
Started Aug 02 06:40:22 PM PDT 24
Finished Aug 02 06:40:24 PM PDT 24
Peak memory 220636 kb
Host smart-a663d6e8-ff46-4c3a-8022-504e425ca2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608954427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1608954427
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2182553880
Short name T410
Test name
Test status
Simulation time 34562036 ps
CPU time 0.88 seconds
Started Aug 02 06:40:26 PM PDT 24
Finished Aug 02 06:40:27 PM PDT 24
Peak memory 206564 kb
Host smart-b0378d21-8377-4a58-b69d-9ec01fb8f8fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182553880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2182553880
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3575691462
Short name T604
Test name
Test status
Simulation time 43892673 ps
CPU time 0.89 seconds
Started Aug 02 06:40:26 PM PDT 24
Finished Aug 02 06:40:27 PM PDT 24
Peak memory 216076 kb
Host smart-b689cf82-504a-4afb-a4d4-34af0bc6e8bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575691462 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3575691462
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2501437045
Short name T147
Test name
Test status
Simulation time 39995805 ps
CPU time 1.05 seconds
Started Aug 02 06:40:31 PM PDT 24
Finished Aug 02 06:40:32 PM PDT 24
Peak memory 216944 kb
Host smart-ceb1584a-a18e-4374-b15c-ce95200c4cab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501437045 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2501437045
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1726953364
Short name T190
Test name
Test status
Simulation time 93200964 ps
CPU time 0.88 seconds
Started Aug 02 06:40:26 PM PDT 24
Finished Aug 02 06:40:27 PM PDT 24
Peak memory 218228 kb
Host smart-af876781-98f6-4339-8afd-f37550f168d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726953364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1726953364
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3435064780
Short name T397
Test name
Test status
Simulation time 148075666 ps
CPU time 1.3 seconds
Started Aug 02 06:40:24 PM PDT 24
Finished Aug 02 06:40:25 PM PDT 24
Peak memory 220244 kb
Host smart-d92e281d-3f10-486f-bdb2-a3f33947ec8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435064780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3435064780
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.77260400
Short name T915
Test name
Test status
Simulation time 93574440 ps
CPU time 0.91 seconds
Started Aug 02 06:40:25 PM PDT 24
Finished Aug 02 06:40:26 PM PDT 24
Peak memory 215348 kb
Host smart-989c66d1-6587-4f91-b2be-7e661f0d2515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77260400 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.77260400
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1586606784
Short name T395
Test name
Test status
Simulation time 71873510 ps
CPU time 0.94 seconds
Started Aug 02 06:40:24 PM PDT 24
Finished Aug 02 06:40:25 PM PDT 24
Peak memory 215340 kb
Host smart-d1340937-f4e7-4afe-88ba-ef96f891d700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586606784 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1586606784
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2061596519
Short name T765
Test name
Test status
Simulation time 45130187 ps
CPU time 1.06 seconds
Started Aug 02 06:40:29 PM PDT 24
Finished Aug 02 06:40:30 PM PDT 24
Peak memory 215320 kb
Host smart-52df435b-c3fd-4ddf-b65e-fed060c3788b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061596519 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2061596519
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.645799447
Short name T602
Test name
Test status
Simulation time 40422798634 ps
CPU time 278.38 seconds
Started Aug 02 06:40:24 PM PDT 24
Finished Aug 02 06:45:02 PM PDT 24
Peak memory 223628 kb
Host smart-0b8fd7d1-230e-4480-b252-24494386b0bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645799447 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.645799447
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1467830426
Short name T781
Test name
Test status
Simulation time 105329382 ps
CPU time 1.7 seconds
Started Aug 02 06:42:38 PM PDT 24
Finished Aug 02 06:42:40 PM PDT 24
Peak memory 218852 kb
Host smart-35cefa5e-d761-4cc9-9951-924d1b8f2508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467830426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1467830426
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3887933540
Short name T431
Test name
Test status
Simulation time 95749848 ps
CPU time 1.13 seconds
Started Aug 02 06:42:40 PM PDT 24
Finished Aug 02 06:42:42 PM PDT 24
Peak memory 217264 kb
Host smart-721a8429-8aab-4efa-acf2-1998995a1d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887933540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3887933540
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1362587997
Short name T570
Test name
Test status
Simulation time 47180827 ps
CPU time 1.54 seconds
Started Aug 02 06:42:35 PM PDT 24
Finished Aug 02 06:42:36 PM PDT 24
Peak memory 217284 kb
Host smart-86af7f8f-353b-446e-8e59-7924c4a7ad44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362587997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1362587997
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.4213178151
Short name T858
Test name
Test status
Simulation time 275750784 ps
CPU time 3.89 seconds
Started Aug 02 06:42:41 PM PDT 24
Finished Aug 02 06:42:45 PM PDT 24
Peak memory 218956 kb
Host smart-294999f2-b819-4dc8-b8be-fca1a324b16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213178151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4213178151
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.666732605
Short name T921
Test name
Test status
Simulation time 45911883 ps
CPU time 1.37 seconds
Started Aug 02 06:42:40 PM PDT 24
Finished Aug 02 06:42:42 PM PDT 24
Peak memory 217468 kb
Host smart-5e8720f5-6dfa-417b-9181-26ec8176ff23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666732605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.666732605
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.285837239
Short name T491
Test name
Test status
Simulation time 40495414 ps
CPU time 1.62 seconds
Started Aug 02 06:42:41 PM PDT 24
Finished Aug 02 06:42:43 PM PDT 24
Peak memory 219940 kb
Host smart-434ef681-93c9-4d01-bc80-fd07c8759d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285837239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.285837239
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2643365280
Short name T49
Test name
Test status
Simulation time 27728121 ps
CPU time 1.14 seconds
Started Aug 02 06:42:41 PM PDT 24
Finished Aug 02 06:42:42 PM PDT 24
Peak memory 217336 kb
Host smart-39aeb563-439b-411e-a8d2-f08646ca585c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643365280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2643365280
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1292597285
Short name T586
Test name
Test status
Simulation time 94946687 ps
CPU time 1.47 seconds
Started Aug 02 06:42:39 PM PDT 24
Finished Aug 02 06:42:41 PM PDT 24
Peak memory 218796 kb
Host smart-6ace2c02-3d1e-482e-8fd9-bd70001d8f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292597285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1292597285
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1018175142
Short name T327
Test name
Test status
Simulation time 85460000 ps
CPU time 1.5 seconds
Started Aug 02 06:42:33 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 219036 kb
Host smart-7aa0bf52-f7ec-497c-bb7e-8199b8304eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018175142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1018175142
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3951078709
Short name T520
Test name
Test status
Simulation time 30283738 ps
CPU time 1.32 seconds
Started Aug 02 06:42:32 PM PDT 24
Finished Aug 02 06:42:34 PM PDT 24
Peak memory 220108 kb
Host smart-9f75e85e-bc2b-46d2-a434-a8c2f673b249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951078709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3951078709
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.701770640
Short name T598
Test name
Test status
Simulation time 86491653 ps
CPU time 1.19 seconds
Started Aug 02 06:40:39 PM PDT 24
Finished Aug 02 06:40:41 PM PDT 24
Peak memory 218508 kb
Host smart-94252568-aa6b-4474-83f3-757a2e6245bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701770640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.701770640
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2594085650
Short name T554
Test name
Test status
Simulation time 17658730 ps
CPU time 1 seconds
Started Aug 02 06:40:34 PM PDT 24
Finished Aug 02 06:40:35 PM PDT 24
Peak memory 214924 kb
Host smart-d8271eaf-facb-4d9b-8824-62c280960777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594085650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2594085650
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.254320625
Short name T687
Test name
Test status
Simulation time 18875697 ps
CPU time 0.9 seconds
Started Aug 02 06:40:33 PM PDT 24
Finished Aug 02 06:40:34 PM PDT 24
Peak memory 215760 kb
Host smart-f5a60fd2-9c91-43d1-9a2d-3d889980512f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254320625 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.254320625
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1404373131
Short name T154
Test name
Test status
Simulation time 61216001 ps
CPU time 1.16 seconds
Started Aug 02 06:40:33 PM PDT 24
Finished Aug 02 06:40:34 PM PDT 24
Peak memory 217020 kb
Host smart-c648f2d8-43b4-42a6-91f8-746a3c930e70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404373131 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1404373131
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3946975810
Short name T777
Test name
Test status
Simulation time 51024500 ps
CPU time 0.98 seconds
Started Aug 02 06:40:34 PM PDT 24
Finished Aug 02 06:40:35 PM PDT 24
Peak memory 223804 kb
Host smart-7c7ba065-c386-4b10-9ec8-6e18c0aeead0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946975810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3946975810
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1131567781
Short name T691
Test name
Test status
Simulation time 286405895 ps
CPU time 3.83 seconds
Started Aug 02 06:40:34 PM PDT 24
Finished Aug 02 06:40:38 PM PDT 24
Peak memory 220420 kb
Host smart-a7438807-28ad-4108-a38d-1ddbb293cbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131567781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1131567781
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.812025026
Short name T494
Test name
Test status
Simulation time 57505004 ps
CPU time 0.87 seconds
Started Aug 02 06:40:34 PM PDT 24
Finished Aug 02 06:40:35 PM PDT 24
Peak memory 215184 kb
Host smart-73260f1d-038e-40f2-a46a-d76dbe94b104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812025026 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.812025026
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.428822780
Short name T540
Test name
Test status
Simulation time 24534594 ps
CPU time 0.95 seconds
Started Aug 02 06:40:35 PM PDT 24
Finished Aug 02 06:40:37 PM PDT 24
Peak memory 215292 kb
Host smart-becb8bc0-c4b1-42d3-a92d-ef57d2f00d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428822780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.428822780
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1324939338
Short name T645
Test name
Test status
Simulation time 229987961 ps
CPU time 4.54 seconds
Started Aug 02 06:40:32 PM PDT 24
Finished Aug 02 06:40:36 PM PDT 24
Peak memory 217196 kb
Host smart-9e4f8700-1ee4-4fa1-9735-875ee6f495c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324939338 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1324939338
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.412438970
Short name T945
Test name
Test status
Simulation time 46907541671 ps
CPU time 268.85 seconds
Started Aug 02 06:40:29 PM PDT 24
Finished Aug 02 06:44:58 PM PDT 24
Peak memory 223596 kb
Host smart-49ba98ef-9186-483a-a300-4cdb50213dcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412438970 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.412438970
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1466741086
Short name T367
Test name
Test status
Simulation time 55387411 ps
CPU time 1.46 seconds
Started Aug 02 06:42:36 PM PDT 24
Finished Aug 02 06:42:37 PM PDT 24
Peak memory 218616 kb
Host smart-3ecf281d-d357-433e-a566-3438d71c109f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466741086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1466741086
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.844379561
Short name T407
Test name
Test status
Simulation time 194220410 ps
CPU time 1.25 seconds
Started Aug 02 06:42:36 PM PDT 24
Finished Aug 02 06:42:37 PM PDT 24
Peak memory 220160 kb
Host smart-42dd8a0c-e13d-45c6-b28b-cf5cd94315a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844379561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.844379561
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3480121894
Short name T629
Test name
Test status
Simulation time 54120651 ps
CPU time 1.78 seconds
Started Aug 02 06:42:40 PM PDT 24
Finished Aug 02 06:42:42 PM PDT 24
Peak memory 218760 kb
Host smart-06a67060-77e3-49d1-82da-287395715616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480121894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3480121894
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.273249438
Short name T731
Test name
Test status
Simulation time 57731805 ps
CPU time 1.09 seconds
Started Aug 02 06:42:40 PM PDT 24
Finished Aug 02 06:42:41 PM PDT 24
Peak memory 219976 kb
Host smart-e703a2bb-eb77-4762-9aa7-7c7006d52705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273249438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.273249438
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3081827464
Short name T837
Test name
Test status
Simulation time 60716300 ps
CPU time 1.3 seconds
Started Aug 02 06:42:40 PM PDT 24
Finished Aug 02 06:42:42 PM PDT 24
Peak memory 218884 kb
Host smart-fe7b517e-1f5b-40a1-b958-1e9c224d6519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081827464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3081827464
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3054670787
Short name T714
Test name
Test status
Simulation time 40771840 ps
CPU time 1.67 seconds
Started Aug 02 06:42:43 PM PDT 24
Finished Aug 02 06:42:45 PM PDT 24
Peak memory 217404 kb
Host smart-c65eac6d-d36a-41f6-9f33-7c751922ff5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054670787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3054670787
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.4216971436
Short name T728
Test name
Test status
Simulation time 99383919 ps
CPU time 1.61 seconds
Started Aug 02 06:42:43 PM PDT 24
Finished Aug 02 06:42:45 PM PDT 24
Peak memory 218848 kb
Host smart-8148e1cb-7dac-45d7-963f-0f80daeac57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216971436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.4216971436
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.430530019
Short name T291
Test name
Test status
Simulation time 220726421 ps
CPU time 1.06 seconds
Started Aug 02 06:42:34 PM PDT 24
Finished Aug 02 06:42:35 PM PDT 24
Peak memory 215284 kb
Host smart-055b4edf-b945-41f9-aeb8-cbffe344fe72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430530019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.430530019
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1781415524
Short name T523
Test name
Test status
Simulation time 63875601 ps
CPU time 1.49 seconds
Started Aug 02 06:42:36 PM PDT 24
Finished Aug 02 06:42:37 PM PDT 24
Peak memory 218876 kb
Host smart-cfd94794-c01c-4938-b585-1caee3814cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781415524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1781415524
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2467025290
Short name T698
Test name
Test status
Simulation time 27794332 ps
CPU time 1.37 seconds
Started Aug 02 06:42:35 PM PDT 24
Finished Aug 02 06:42:36 PM PDT 24
Peak memory 218572 kb
Host smart-998575f1-21b8-4893-a7e4-c37ce1abdee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467025290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2467025290
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.675136511
Short name T536
Test name
Test status
Simulation time 27622161 ps
CPU time 1.28 seconds
Started Aug 02 06:40:39 PM PDT 24
Finished Aug 02 06:40:41 PM PDT 24
Peak memory 219296 kb
Host smart-9a991a49-c58a-49f6-8d73-c0eeb0097386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675136511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.675136511
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.756407568
Short name T2
Test name
Test status
Simulation time 74783846 ps
CPU time 0.94 seconds
Started Aug 02 06:40:39 PM PDT 24
Finished Aug 02 06:40:41 PM PDT 24
Peak memory 206772 kb
Host smart-f40f59d8-df70-4fb2-8b61-1536b6c2d6fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756407568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.756407568
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3521214979
Short name T610
Test name
Test status
Simulation time 50243802 ps
CPU time 1.18 seconds
Started Aug 02 06:40:33 PM PDT 24
Finished Aug 02 06:40:34 PM PDT 24
Peak memory 217052 kb
Host smart-335746d2-da9f-4463-8321-be8d35025da6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521214979 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3521214979
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3418759002
Short name T113
Test name
Test status
Simulation time 23675837 ps
CPU time 0.93 seconds
Started Aug 02 06:40:30 PM PDT 24
Finished Aug 02 06:40:31 PM PDT 24
Peak memory 218672 kb
Host smart-e68f7b44-898e-4a6b-a532-7f1778ec4e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418759002 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3418759002
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2507371954
Short name T336
Test name
Test status
Simulation time 61707790 ps
CPU time 1.58 seconds
Started Aug 02 06:40:31 PM PDT 24
Finished Aug 02 06:40:33 PM PDT 24
Peak memory 218748 kb
Host smart-bec0b50a-2fb5-4fba-86d6-fa82da04da1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507371954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2507371954
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3501936313
Short name T94
Test name
Test status
Simulation time 63694723 ps
CPU time 0.91 seconds
Started Aug 02 06:40:31 PM PDT 24
Finished Aug 02 06:40:32 PM PDT 24
Peak memory 215396 kb
Host smart-0fbf33aa-2288-4816-b444-56984517be26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501936313 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3501936313
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3712925101
Short name T786
Test name
Test status
Simulation time 30480703 ps
CPU time 0.91 seconds
Started Aug 02 06:40:32 PM PDT 24
Finished Aug 02 06:40:33 PM PDT 24
Peak memory 207116 kb
Host smart-713195a6-4357-44da-b3cd-73ca4ed20764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712925101 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3712925101
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.4246001301
Short name T339
Test name
Test status
Simulation time 555396456 ps
CPU time 3.73 seconds
Started Aug 02 06:40:32 PM PDT 24
Finished Aug 02 06:40:36 PM PDT 24
Peak memory 217368 kb
Host smart-47f1d73f-27f4-4184-bbfd-2f97900c22a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246001301 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4246001301
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.682790113
Short name T550
Test name
Test status
Simulation time 113835204169 ps
CPU time 786.54 seconds
Started Aug 02 06:40:31 PM PDT 24
Finished Aug 02 06:53:38 PM PDT 24
Peak memory 223640 kb
Host smart-1c246b4f-363b-4317-8b0b-56589a25e763
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682790113 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.682790113
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.4134088079
Short name T565
Test name
Test status
Simulation time 77492981 ps
CPU time 1.59 seconds
Started Aug 02 06:42:43 PM PDT 24
Finished Aug 02 06:42:44 PM PDT 24
Peak memory 219048 kb
Host smart-67c632eb-4723-4fe1-8faf-b95f94da14a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134088079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.4134088079
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.108806599
Short name T32
Test name
Test status
Simulation time 40381755 ps
CPU time 1.46 seconds
Started Aug 02 06:42:39 PM PDT 24
Finished Aug 02 06:42:40 PM PDT 24
Peak memory 218644 kb
Host smart-ba56e880-8814-445c-9458-80019af361cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108806599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.108806599
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3225766160
Short name T808
Test name
Test status
Simulation time 50151042 ps
CPU time 1.17 seconds
Started Aug 02 06:42:34 PM PDT 24
Finished Aug 02 06:42:36 PM PDT 24
Peak memory 218632 kb
Host smart-92f668c5-5e7c-4577-822b-e898b058b9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225766160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3225766160
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3133767767
Short name T375
Test name
Test status
Simulation time 85744671 ps
CPU time 1.31 seconds
Started Aug 02 06:42:43 PM PDT 24
Finished Aug 02 06:42:44 PM PDT 24
Peak memory 218796 kb
Host smart-b2a9e98d-4a20-4888-87d4-843723ebf75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133767767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3133767767
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1212209302
Short name T918
Test name
Test status
Simulation time 125553357 ps
CPU time 1.19 seconds
Started Aug 02 06:42:38 PM PDT 24
Finished Aug 02 06:42:39 PM PDT 24
Peak memory 217220 kb
Host smart-b08cffbd-49c3-4b98-8973-d4ab39d7eb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212209302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1212209302
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.657996710
Short name T499
Test name
Test status
Simulation time 67078712 ps
CPU time 2.52 seconds
Started Aug 02 06:42:44 PM PDT 24
Finished Aug 02 06:42:47 PM PDT 24
Peak memory 220084 kb
Host smart-1c94e949-b1f6-42c6-a5cc-e786e2df52e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657996710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.657996710
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2741732570
Short name T579
Test name
Test status
Simulation time 83690282 ps
CPU time 1.01 seconds
Started Aug 02 06:42:48 PM PDT 24
Finished Aug 02 06:42:50 PM PDT 24
Peak memory 215344 kb
Host smart-9ed62bb3-0582-4b80-905c-59eb8638918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741732570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2741732570
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.794885306
Short name T881
Test name
Test status
Simulation time 23698700 ps
CPU time 1.33 seconds
Started Aug 02 06:42:46 PM PDT 24
Finished Aug 02 06:42:48 PM PDT 24
Peak memory 218668 kb
Host smart-6cc65977-ba9c-494f-bbf7-92d796bebd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794885306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.794885306
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2092686534
Short name T767
Test name
Test status
Simulation time 91273686 ps
CPU time 1.12 seconds
Started Aug 02 06:42:46 PM PDT 24
Finished Aug 02 06:42:48 PM PDT 24
Peak memory 217336 kb
Host smart-73c18f61-81ee-4c6b-a9cc-7beaa93b7535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092686534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2092686534
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1384827356
Short name T639
Test name
Test status
Simulation time 70862380 ps
CPU time 1.2 seconds
Started Aug 02 06:42:43 PM PDT 24
Finished Aug 02 06:42:45 PM PDT 24
Peak memory 219028 kb
Host smart-ed318a23-b9d0-4423-a043-79d88f38c84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384827356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1384827356
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.656100423
Short name T68
Test name
Test status
Simulation time 43612732 ps
CPU time 1.2 seconds
Started Aug 02 06:40:33 PM PDT 24
Finished Aug 02 06:40:34 PM PDT 24
Peak memory 218800 kb
Host smart-b7d5a953-50a9-4334-b50a-360f54602b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656100423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.656100423
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.202777396
Short name T524
Test name
Test status
Simulation time 40528488 ps
CPU time 0.83 seconds
Started Aug 02 06:40:34 PM PDT 24
Finished Aug 02 06:40:35 PM PDT 24
Peak memory 206812 kb
Host smart-c8f8e9ee-207f-48c0-8f97-1ea4409458a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202777396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.202777396
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2074771379
Short name T559
Test name
Test status
Simulation time 10535173 ps
CPU time 0.89 seconds
Started Aug 02 06:40:35 PM PDT 24
Finished Aug 02 06:40:36 PM PDT 24
Peak memory 216352 kb
Host smart-1b0fa1ed-eaaa-4710-ac43-eb1708a923be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074771379 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2074771379
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3178898078
Short name T398
Test name
Test status
Simulation time 24859337 ps
CPU time 1.03 seconds
Started Aug 02 06:40:31 PM PDT 24
Finished Aug 02 06:40:32 PM PDT 24
Peak memory 218468 kb
Host smart-e1a2fe0c-51c2-4ba4-9d7d-e1c7d721bf1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178898078 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3178898078
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_genbits.830274084
Short name T885
Test name
Test status
Simulation time 48195022 ps
CPU time 1.21 seconds
Started Aug 02 06:40:32 PM PDT 24
Finished Aug 02 06:40:34 PM PDT 24
Peak memory 218708 kb
Host smart-f8b0f455-df9f-44f8-bac5-c0918e859e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830274084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.830274084
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3725151498
Short name T505
Test name
Test status
Simulation time 51586526 ps
CPU time 0.91 seconds
Started Aug 02 06:40:31 PM PDT 24
Finished Aug 02 06:40:32 PM PDT 24
Peak memory 215172 kb
Host smart-5fcd1165-ae1f-46b5-b24c-dc0d840364f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725151498 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3725151498
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.384956589
Short name T390
Test name
Test status
Simulation time 107430281 ps
CPU time 0.92 seconds
Started Aug 02 06:40:37 PM PDT 24
Finished Aug 02 06:40:38 PM PDT 24
Peak memory 215260 kb
Host smart-0d39e9d3-c83b-429b-a77d-40f2aa080b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384956589 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.384956589
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.435042058
Short name T429
Test name
Test status
Simulation time 235602381 ps
CPU time 1.7 seconds
Started Aug 02 06:40:34 PM PDT 24
Finished Aug 02 06:40:36 PM PDT 24
Peak memory 217084 kb
Host smart-31bc0563-fd45-4998-a4fd-6e775e954e76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435042058 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.435042058
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1009971430
Short name T236
Test name
Test status
Simulation time 173158445077 ps
CPU time 1376.15 seconds
Started Aug 02 06:40:32 PM PDT 24
Finished Aug 02 07:03:28 PM PDT 24
Peak memory 223612 kb
Host smart-69ea1939-80cb-447e-8997-d2645d23b2b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009971430 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1009971430
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1916339780
Short name T679
Test name
Test status
Simulation time 333759881 ps
CPU time 1.89 seconds
Started Aug 02 06:42:45 PM PDT 24
Finished Aug 02 06:42:47 PM PDT 24
Peak memory 220164 kb
Host smart-633ce413-38ec-4c6c-a84e-fa1402edb924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916339780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1916339780
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3093279828
Short name T399
Test name
Test status
Simulation time 136347210 ps
CPU time 2.21 seconds
Started Aug 02 06:42:48 PM PDT 24
Finished Aug 02 06:42:50 PM PDT 24
Peak memory 217516 kb
Host smart-572f965f-b0a3-460e-a94a-0c08304ee740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093279828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3093279828
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.988616464
Short name T673
Test name
Test status
Simulation time 71820005 ps
CPU time 2.74 seconds
Started Aug 02 06:42:49 PM PDT 24
Finished Aug 02 06:42:52 PM PDT 24
Peak memory 215320 kb
Host smart-844a678e-7a8d-4382-92a9-d5488edf1cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988616464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.988616464
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2088711411
Short name T388
Test name
Test status
Simulation time 45748987 ps
CPU time 1.59 seconds
Started Aug 02 06:42:50 PM PDT 24
Finished Aug 02 06:42:51 PM PDT 24
Peak memory 218480 kb
Host smart-1ad3ed7e-cae4-41b2-a608-fd3076a2e2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088711411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2088711411
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1273359230
Short name T451
Test name
Test status
Simulation time 50779577 ps
CPU time 1.16 seconds
Started Aug 02 06:42:44 PM PDT 24
Finished Aug 02 06:42:45 PM PDT 24
Peak memory 218524 kb
Host smart-cde75a65-bd0b-49c2-8b8c-ee139e630b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273359230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1273359230
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2432475487
Short name T330
Test name
Test status
Simulation time 72689477 ps
CPU time 1.02 seconds
Started Aug 02 06:42:45 PM PDT 24
Finished Aug 02 06:42:46 PM PDT 24
Peak memory 217280 kb
Host smart-1b00fe79-5110-4220-9b4f-3a11d87dd572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432475487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2432475487
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3758105430
Short name T683
Test name
Test status
Simulation time 70195768 ps
CPU time 1.58 seconds
Started Aug 02 06:42:45 PM PDT 24
Finished Aug 02 06:42:46 PM PDT 24
Peak memory 218588 kb
Host smart-08897a25-e5a2-4db1-8653-b616912c9a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758105430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3758105430
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2265348320
Short name T713
Test name
Test status
Simulation time 25606432 ps
CPU time 1.32 seconds
Started Aug 02 06:42:45 PM PDT 24
Finished Aug 02 06:42:47 PM PDT 24
Peak memory 217304 kb
Host smart-faf91fbb-4753-4d2d-b2f3-5ec58fcb910e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265348320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2265348320
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2692569431
Short name T70
Test name
Test status
Simulation time 75638085 ps
CPU time 1.17 seconds
Started Aug 02 06:42:45 PM PDT 24
Finished Aug 02 06:42:47 PM PDT 24
Peak memory 217236 kb
Host smart-71273cca-949d-452b-89e6-e4bb2ffaebe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692569431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2692569431
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3488633516
Short name T506
Test name
Test status
Simulation time 23671414 ps
CPU time 1.13 seconds
Started Aug 02 06:42:44 PM PDT 24
Finished Aug 02 06:42:45 PM PDT 24
Peak memory 219696 kb
Host smart-04a00ba4-d225-4be8-bf04-b853a5ee2629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488633516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3488633516
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2057807757
Short name T567
Test name
Test status
Simulation time 105353574 ps
CPU time 1.08 seconds
Started Aug 02 06:40:37 PM PDT 24
Finished Aug 02 06:40:38 PM PDT 24
Peak memory 219544 kb
Host smart-4ae246d7-93c3-4f0b-b790-45e11d072565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057807757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2057807757
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.62220619
Short name T381
Test name
Test status
Simulation time 46170482 ps
CPU time 0.92 seconds
Started Aug 02 06:40:40 PM PDT 24
Finished Aug 02 06:40:41 PM PDT 24
Peak memory 206768 kb
Host smart-fb577510-70bb-479d-9f14-93c7fe085384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62220619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.62220619
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1197741694
Short name T125
Test name
Test status
Simulation time 28506595 ps
CPU time 0.84 seconds
Started Aug 02 06:40:31 PM PDT 24
Finished Aug 02 06:40:32 PM PDT 24
Peak memory 216324 kb
Host smart-7bc7bc25-b5b5-4e05-b118-4269b14bf080
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197741694 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1197741694
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3132999048
Short name T175
Test name
Test status
Simulation time 96579794 ps
CPU time 1.08 seconds
Started Aug 02 06:40:32 PM PDT 24
Finished Aug 02 06:40:33 PM PDT 24
Peak memory 216804 kb
Host smart-37026e98-a0d6-4e4e-a7eb-8b4943da939b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132999048 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3132999048
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.840682222
Short name T745
Test name
Test status
Simulation time 31880537 ps
CPU time 0.99 seconds
Started Aug 02 06:40:33 PM PDT 24
Finished Aug 02 06:40:34 PM PDT 24
Peak memory 223768 kb
Host smart-91a85bd9-029f-4db4-904f-49e7a536f00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840682222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.840682222
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.468027758
Short name T658
Test name
Test status
Simulation time 58289583 ps
CPU time 1.17 seconds
Started Aug 02 06:40:29 PM PDT 24
Finished Aug 02 06:40:30 PM PDT 24
Peak memory 218896 kb
Host smart-5f616cf0-f084-4a9d-b9d2-466e2a32e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468027758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.468027758
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_smoke.562118388
Short name T7
Test name
Test status
Simulation time 17808167 ps
CPU time 1 seconds
Started Aug 02 06:40:33 PM PDT 24
Finished Aug 02 06:40:34 PM PDT 24
Peak memory 215316 kb
Host smart-81a42781-09ae-4508-8439-9f5f581fcdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562118388 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.562118388
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1228513186
Short name T681
Test name
Test status
Simulation time 204980339 ps
CPU time 4.21 seconds
Started Aug 02 06:40:39 PM PDT 24
Finished Aug 02 06:40:44 PM PDT 24
Peak memory 215476 kb
Host smart-d6f4d586-8c27-4eda-adcf-20e1ddb289f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228513186 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1228513186
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2261271689
Short name T742
Test name
Test status
Simulation time 67428133020 ps
CPU time 1527.11 seconds
Started Aug 02 06:40:30 PM PDT 24
Finished Aug 02 07:05:57 PM PDT 24
Peak memory 224792 kb
Host smart-142a21d0-7341-4b9d-9dd8-50a961f63bd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261271689 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2261271689
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.4215562566
Short name T538
Test name
Test status
Simulation time 103208669 ps
CPU time 1.34 seconds
Started Aug 02 06:42:44 PM PDT 24
Finished Aug 02 06:42:46 PM PDT 24
Peak memory 217248 kb
Host smart-adac505e-6843-484a-a23e-082f72aadb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215562566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.4215562566
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.21123616
Short name T833
Test name
Test status
Simulation time 95497167 ps
CPU time 1.48 seconds
Started Aug 02 06:42:45 PM PDT 24
Finished Aug 02 06:42:47 PM PDT 24
Peak memory 218652 kb
Host smart-b404a992-c45e-4e14-a7da-912fa4a6c7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21123616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.21123616
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1068071999
Short name T516
Test name
Test status
Simulation time 55987835 ps
CPU time 1.47 seconds
Started Aug 02 06:42:46 PM PDT 24
Finished Aug 02 06:42:47 PM PDT 24
Peak memory 217280 kb
Host smart-94a0c1b6-31d3-4354-aad7-11f1b54de7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068071999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1068071999
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1913473456
Short name T889
Test name
Test status
Simulation time 37899043 ps
CPU time 1.49 seconds
Started Aug 02 06:42:50 PM PDT 24
Finished Aug 02 06:42:52 PM PDT 24
Peak memory 218440 kb
Host smart-90e7fb48-35be-4704-894f-468daf7da262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913473456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1913473456
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.856709254
Short name T353
Test name
Test status
Simulation time 42583906 ps
CPU time 1.42 seconds
Started Aug 02 06:42:44 PM PDT 24
Finished Aug 02 06:42:45 PM PDT 24
Peak memory 218716 kb
Host smart-38d84c4a-2c20-4f63-9c8b-36d2d63e7532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856709254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.856709254
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.4011238557
Short name T531
Test name
Test status
Simulation time 77712857 ps
CPU time 1.83 seconds
Started Aug 02 06:42:44 PM PDT 24
Finished Aug 02 06:42:46 PM PDT 24
Peak memory 219820 kb
Host smart-3699b731-011b-496b-87f5-91a322cc487b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011238557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.4011238557
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2553334742
Short name T541
Test name
Test status
Simulation time 180664792 ps
CPU time 2.03 seconds
Started Aug 02 06:42:43 PM PDT 24
Finished Aug 02 06:42:46 PM PDT 24
Peak memory 220388 kb
Host smart-cc8fd740-9588-4d36-8ee2-384c47227c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553334742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2553334742
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.989934445
Short name T932
Test name
Test status
Simulation time 45955099 ps
CPU time 1.5 seconds
Started Aug 02 06:42:45 PM PDT 24
Finished Aug 02 06:42:47 PM PDT 24
Peak memory 218352 kb
Host smart-1b37479d-a046-449c-889b-8166773ddf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989934445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.989934445
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2227496777
Short name T316
Test name
Test status
Simulation time 34896925 ps
CPU time 1.25 seconds
Started Aug 02 06:42:51 PM PDT 24
Finished Aug 02 06:42:53 PM PDT 24
Peak memory 217392 kb
Host smart-0a04e85e-0616-4eaf-b019-2c8e793f6a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227496777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2227496777
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1933055304
Short name T636
Test name
Test status
Simulation time 96781503 ps
CPU time 1.27 seconds
Started Aug 02 06:40:40 PM PDT 24
Finished Aug 02 06:40:42 PM PDT 24
Peak memory 219756 kb
Host smart-12b05261-328b-4b09-9d8a-fe4de29c4628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933055304 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1933055304
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.397733394
Short name T613
Test name
Test status
Simulation time 38593814 ps
CPU time 0.83 seconds
Started Aug 02 06:40:38 PM PDT 24
Finished Aug 02 06:40:39 PM PDT 24
Peak memory 206748 kb
Host smart-1e4c2049-0adf-4930-829e-dfde75a5091f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397733394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.397733394
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1263950277
Short name T510
Test name
Test status
Simulation time 91991362 ps
CPU time 1.14 seconds
Started Aug 02 06:40:39 PM PDT 24
Finished Aug 02 06:40:40 PM PDT 24
Peak memory 218620 kb
Host smart-2a20cdff-5056-4cec-8fb4-a6f12b2e6483
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263950277 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1263950277
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.202182307
Short name T195
Test name
Test status
Simulation time 18247865 ps
CPU time 1 seconds
Started Aug 02 06:40:38 PM PDT 24
Finished Aug 02 06:40:40 PM PDT 24
Peak memory 218316 kb
Host smart-d3df0aa3-4665-4dd8-9c39-5cb59e17ec32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202182307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.202182307
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3894345980
Short name T29
Test name
Test status
Simulation time 58043748 ps
CPU time 2.15 seconds
Started Aug 02 06:40:41 PM PDT 24
Finished Aug 02 06:40:43 PM PDT 24
Peak memory 219060 kb
Host smart-4329b297-8d12-4117-908b-b720c6a5dc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894345980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3894345980
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3875736971
Short name T905
Test name
Test status
Simulation time 42316765 ps
CPU time 0.89 seconds
Started Aug 02 06:40:38 PM PDT 24
Finished Aug 02 06:40:39 PM PDT 24
Peak memory 215168 kb
Host smart-c3411e14-718a-4114-8079-0fd82d5abea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875736971 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3875736971
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3297448456
Short name T724
Test name
Test status
Simulation time 17922515 ps
CPU time 0.98 seconds
Started Aug 02 06:40:38 PM PDT 24
Finished Aug 02 06:40:39 PM PDT 24
Peak memory 215340 kb
Host smart-31a0ab62-1565-4b38-ab37-cf9f72f57fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297448456 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3297448456
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.195751137
Short name T548
Test name
Test status
Simulation time 303802776 ps
CPU time 6 seconds
Started Aug 02 06:40:39 PM PDT 24
Finished Aug 02 06:40:45 PM PDT 24
Peak memory 215360 kb
Host smart-37f6f86b-2181-4706-be43-8379be4720ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195751137 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.195751137
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.4198480508
Short name T543
Test name
Test status
Simulation time 3365755989 ps
CPU time 57.31 seconds
Started Aug 02 06:40:39 PM PDT 24
Finished Aug 02 06:41:36 PM PDT 24
Peak memory 221332 kb
Host smart-898e25ab-bfb5-4af1-a658-af9848658729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198480508 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.4198480508
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2899817869
Short name T377
Test name
Test status
Simulation time 42664880 ps
CPU time 1.2 seconds
Started Aug 02 06:42:52 PM PDT 24
Finished Aug 02 06:42:53 PM PDT 24
Peak memory 217248 kb
Host smart-420bfb66-590c-49ce-88b8-dd5ce7e492d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899817869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2899817869
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2513687253
Short name T10
Test name
Test status
Simulation time 223522903 ps
CPU time 1.29 seconds
Started Aug 02 06:42:49 PM PDT 24
Finished Aug 02 06:42:50 PM PDT 24
Peak memory 220164 kb
Host smart-6e7f57e9-4dcd-47f9-96c1-b02a7bce029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513687253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2513687253
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2037483538
Short name T534
Test name
Test status
Simulation time 103912873 ps
CPU time 1.17 seconds
Started Aug 02 06:42:46 PM PDT 24
Finished Aug 02 06:42:47 PM PDT 24
Peak memory 217240 kb
Host smart-a24304d9-7a1e-496b-a3eb-30d697b3ab0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037483538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2037483538
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.399310971
Short name T404
Test name
Test status
Simulation time 46802755 ps
CPU time 1.21 seconds
Started Aug 02 06:42:44 PM PDT 24
Finished Aug 02 06:42:45 PM PDT 24
Peak memory 219932 kb
Host smart-73f650c8-924c-437b-add9-7b5fed81ce54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399310971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.399310971
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1486774068
Short name T853
Test name
Test status
Simulation time 79413269 ps
CPU time 1.43 seconds
Started Aug 02 06:42:45 PM PDT 24
Finished Aug 02 06:42:46 PM PDT 24
Peak memory 218816 kb
Host smart-d0a02fe2-eb99-40b2-9fcf-7e65b8c1ee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486774068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1486774068
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2812259013
Short name T472
Test name
Test status
Simulation time 64640021 ps
CPU time 1.24 seconds
Started Aug 02 06:42:46 PM PDT 24
Finished Aug 02 06:42:47 PM PDT 24
Peak memory 217496 kb
Host smart-56122894-6596-4881-af17-e8b25859a548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812259013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2812259013
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3552897529
Short name T793
Test name
Test status
Simulation time 27968652 ps
CPU time 1.2 seconds
Started Aug 02 06:42:47 PM PDT 24
Finished Aug 02 06:42:49 PM PDT 24
Peak memory 219820 kb
Host smart-473e6993-8e1d-4bcb-a83a-5a8e9b13dcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552897529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3552897529
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.661512832
Short name T747
Test name
Test status
Simulation time 269010224 ps
CPU time 3.69 seconds
Started Aug 02 06:42:51 PM PDT 24
Finished Aug 02 06:42:55 PM PDT 24
Peak memory 217580 kb
Host smart-3361ce9e-3fd1-44b2-90d1-e8f61cfa525b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661512832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.661512832
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1160342291
Short name T776
Test name
Test status
Simulation time 80355890 ps
CPU time 1.15 seconds
Started Aug 02 06:42:48 PM PDT 24
Finished Aug 02 06:42:50 PM PDT 24
Peak memory 217504 kb
Host smart-b1144dbc-c643-4c5f-8b6c-207647238517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160342291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1160342291
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.383169889
Short name T209
Test name
Test status
Simulation time 53045241 ps
CPU time 1.22 seconds
Started Aug 02 06:40:39 PM PDT 24
Finished Aug 02 06:40:41 PM PDT 24
Peak memory 215680 kb
Host smart-93924087-0e4a-451f-a7f1-5c43a08ff67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383169889 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.383169889
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2985062920
Short name T238
Test name
Test status
Simulation time 44717206 ps
CPU time 0.87 seconds
Started Aug 02 06:40:40 PM PDT 24
Finished Aug 02 06:40:41 PM PDT 24
Peak memory 206704 kb
Host smart-5ddb016a-bc3a-4faa-a996-4d5aa39aad4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985062920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2985062920
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2317075088
Short name T886
Test name
Test status
Simulation time 81764208 ps
CPU time 1.07 seconds
Started Aug 02 06:40:38 PM PDT 24
Finished Aug 02 06:40:39 PM PDT 24
Peak memory 216904 kb
Host smart-f9465e18-b9c9-42dd-9c41-588649390143
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317075088 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2317075088
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.718626983
Short name T150
Test name
Test status
Simulation time 20594196 ps
CPU time 1.16 seconds
Started Aug 02 06:40:41 PM PDT 24
Finished Aug 02 06:40:42 PM PDT 24
Peak memory 219732 kb
Host smart-4e4d5abb-2320-4f3e-9dd5-0403f2b5bed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718626983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.718626983
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2946298095
Short name T240
Test name
Test status
Simulation time 67628477 ps
CPU time 2.58 seconds
Started Aug 02 06:40:41 PM PDT 24
Finished Aug 02 06:40:44 PM PDT 24
Peak memory 219120 kb
Host smart-e8539726-de6b-48c2-b89d-d5d696654091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946298095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2946298095
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3713579306
Short name T725
Test name
Test status
Simulation time 30001323 ps
CPU time 0.87 seconds
Started Aug 02 06:40:40 PM PDT 24
Finished Aug 02 06:40:41 PM PDT 24
Peak memory 215700 kb
Host smart-cf226d47-0693-4055-9fbd-e65f3797b9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713579306 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3713579306
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2148216482
Short name T275
Test name
Test status
Simulation time 33088716 ps
CPU time 0.9 seconds
Started Aug 02 06:40:38 PM PDT 24
Finished Aug 02 06:40:39 PM PDT 24
Peak memory 215360 kb
Host smart-494b68d7-f506-4fce-b2a9-1c1403320846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148216482 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2148216482
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3632599452
Short name T98
Test name
Test status
Simulation time 284850759 ps
CPU time 3.51 seconds
Started Aug 02 06:40:39 PM PDT 24
Finished Aug 02 06:40:43 PM PDT 24
Peak memory 217308 kb
Host smart-02613cd0-ade7-4289-92ba-2e5a4b2b6652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632599452 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3632599452
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.4069051577
Short name T442
Test name
Test status
Simulation time 62722645278 ps
CPU time 1576.33 seconds
Started Aug 02 06:40:40 PM PDT 24
Finished Aug 02 07:06:57 PM PDT 24
Peak memory 225508 kb
Host smart-c65cccfe-77fd-4337-aff5-15903190b085
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069051577 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.4069051577
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1703298583
Short name T710
Test name
Test status
Simulation time 50376422 ps
CPU time 1.43 seconds
Started Aug 02 06:42:46 PM PDT 24
Finished Aug 02 06:42:48 PM PDT 24
Peak memory 218484 kb
Host smart-1ea2ff12-9b1f-4fc2-9976-fd83523aa802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703298583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1703298583
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1845661891
Short name T406
Test name
Test status
Simulation time 115421640 ps
CPU time 1.53 seconds
Started Aug 02 06:42:46 PM PDT 24
Finished Aug 02 06:42:48 PM PDT 24
Peak memory 218668 kb
Host smart-e14ba92b-0f88-40ad-8c10-f360c69e4284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845661891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1845661891
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1398121316
Short name T428
Test name
Test status
Simulation time 61696640 ps
CPU time 1.22 seconds
Started Aug 02 06:42:52 PM PDT 24
Finished Aug 02 06:42:53 PM PDT 24
Peak memory 218548 kb
Host smart-b204c227-0f40-4585-92c3-3a71122cc2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398121316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1398121316
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3002864362
Short name T807
Test name
Test status
Simulation time 101475334 ps
CPU time 1.53 seconds
Started Aug 02 06:42:51 PM PDT 24
Finished Aug 02 06:42:53 PM PDT 24
Peak memory 218828 kb
Host smart-c250cd55-edab-42df-bd71-b2b740ff850a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002864362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3002864362
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1167676579
Short name T556
Test name
Test status
Simulation time 57899174 ps
CPU time 1.4 seconds
Started Aug 02 06:42:52 PM PDT 24
Finished Aug 02 06:42:53 PM PDT 24
Peak memory 217472 kb
Host smart-7bebee62-5b83-415b-8658-d7d3dbfa11df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167676579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1167676579
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2626508941
Short name T400
Test name
Test status
Simulation time 99791532 ps
CPU time 1.28 seconds
Started Aug 02 06:42:42 PM PDT 24
Finished Aug 02 06:42:44 PM PDT 24
Peak memory 218852 kb
Host smart-eacaddd1-0eb5-474d-975d-8eb447d838a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626508941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2626508941
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.351228898
Short name T736
Test name
Test status
Simulation time 79518764 ps
CPU time 2.71 seconds
Started Aug 02 06:42:55 PM PDT 24
Finished Aug 02 06:42:58 PM PDT 24
Peak memory 220268 kb
Host smart-a653de03-a761-4555-a11b-98a5877c7878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351228898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.351228898
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2803058317
Short name T323
Test name
Test status
Simulation time 61283377 ps
CPU time 1.41 seconds
Started Aug 02 06:42:50 PM PDT 24
Finished Aug 02 06:42:51 PM PDT 24
Peak memory 219840 kb
Host smart-2f9c177d-bb0e-47df-ba49-0d95a133eebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803058317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2803058317
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.747440457
Short name T700
Test name
Test status
Simulation time 249989838 ps
CPU time 3.42 seconds
Started Aug 02 06:42:55 PM PDT 24
Finished Aug 02 06:42:59 PM PDT 24
Peak memory 218540 kb
Host smart-17ca7fd3-c013-4f31-8d3b-949463a93b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747440457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.747440457
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1823194706
Short name T498
Test name
Test status
Simulation time 111927873 ps
CPU time 1.67 seconds
Started Aug 02 06:42:47 PM PDT 24
Finished Aug 02 06:42:49 PM PDT 24
Peak memory 218844 kb
Host smart-3b2ac089-4177-4d75-b811-2f46c8766208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823194706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1823194706
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1873495563
Short name T946
Test name
Test status
Simulation time 33852356 ps
CPU time 1.14 seconds
Started Aug 02 06:40:48 PM PDT 24
Finished Aug 02 06:40:49 PM PDT 24
Peak memory 220992 kb
Host smart-e7c88ec5-894a-4707-ab55-22427a7a33f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873495563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1873495563
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1369712599
Short name T54
Test name
Test status
Simulation time 14852226 ps
CPU time 0.91 seconds
Started Aug 02 06:40:48 PM PDT 24
Finished Aug 02 06:40:49 PM PDT 24
Peak memory 206712 kb
Host smart-f4d191ea-0478-4bd2-8e94-8c0ccc83703b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369712599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1369712599
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1056541346
Short name T122
Test name
Test status
Simulation time 51814290 ps
CPU time 0.87 seconds
Started Aug 02 06:40:46 PM PDT 24
Finished Aug 02 06:40:47 PM PDT 24
Peak memory 216324 kb
Host smart-c0cdf931-9b33-4c0d-8e2f-cd05ef4bfa14
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056541346 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1056541346
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3293453749
Short name T589
Test name
Test status
Simulation time 110418637 ps
CPU time 1.11 seconds
Started Aug 02 06:40:47 PM PDT 24
Finished Aug 02 06:40:49 PM PDT 24
Peak memory 218352 kb
Host smart-dcc57e5c-6c90-4888-85f8-534fa10a72f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293453749 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3293453749
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1917071701
Short name T614
Test name
Test status
Simulation time 29304101 ps
CPU time 1.39 seconds
Started Aug 02 06:40:45 PM PDT 24
Finished Aug 02 06:40:46 PM PDT 24
Peak memory 225724 kb
Host smart-399ffec1-4e83-4852-9387-eb6e2ac42412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917071701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1917071701
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_intr.2748671492
Short name T796
Test name
Test status
Simulation time 28361497 ps
CPU time 1.05 seconds
Started Aug 02 06:40:41 PM PDT 24
Finished Aug 02 06:40:42 PM PDT 24
Peak memory 215372 kb
Host smart-ddbcd061-9e57-49b4-975e-f17aed3c7e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748671492 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2748671492
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2794666527
Short name T859
Test name
Test status
Simulation time 27324489 ps
CPU time 0.96 seconds
Started Aug 02 06:40:39 PM PDT 24
Finished Aug 02 06:40:40 PM PDT 24
Peak memory 207088 kb
Host smart-ed668809-35d8-4497-8410-47bab1294571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794666527 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2794666527
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.736292674
Short name T584
Test name
Test status
Simulation time 1047293338 ps
CPU time 5.97 seconds
Started Aug 02 06:40:38 PM PDT 24
Finished Aug 02 06:40:44 PM PDT 24
Peak memory 217424 kb
Host smart-f91e802d-646e-42b3-a2c6-2c774021f6c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736292674 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.736292674
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.639610033
Short name T964
Test name
Test status
Simulation time 69264499261 ps
CPU time 1222.85 seconds
Started Aug 02 06:40:41 PM PDT 24
Finished Aug 02 07:01:04 PM PDT 24
Peak memory 220636 kb
Host smart-704805dd-b224-45e7-a60e-8a7a256e6676
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639610033 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.639610033
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2239361061
Short name T870
Test name
Test status
Simulation time 20521323 ps
CPU time 1.13 seconds
Started Aug 02 06:42:55 PM PDT 24
Finished Aug 02 06:42:56 PM PDT 24
Peak memory 217340 kb
Host smart-0e323f54-81ba-4260-949c-b1c112236bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239361061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2239361061
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2434121905
Short name T413
Test name
Test status
Simulation time 102954967 ps
CPU time 1.62 seconds
Started Aug 02 06:42:48 PM PDT 24
Finished Aug 02 06:42:50 PM PDT 24
Peak memory 218864 kb
Host smart-c5e9046d-59c6-459e-80b8-3f3666750489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434121905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2434121905
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3104476981
Short name T318
Test name
Test status
Simulation time 44976261 ps
CPU time 1.76 seconds
Started Aug 02 06:42:46 PM PDT 24
Finished Aug 02 06:42:48 PM PDT 24
Peak memory 218424 kb
Host smart-16d65fab-9722-42c5-9503-797905f9f217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104476981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3104476981
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.4008413218
Short name T28
Test name
Test status
Simulation time 51734396 ps
CPU time 1.54 seconds
Started Aug 02 06:42:47 PM PDT 24
Finished Aug 02 06:42:49 PM PDT 24
Peak memory 218604 kb
Host smart-0c33375b-ffde-477b-b465-046272d18e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008413218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.4008413218
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.377857911
Short name T663
Test name
Test status
Simulation time 147704077 ps
CPU time 3.13 seconds
Started Aug 02 06:42:47 PM PDT 24
Finished Aug 02 06:42:51 PM PDT 24
Peak memory 220384 kb
Host smart-2eb35ccf-264e-4fda-87fd-7571c862246d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377857911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.377857911
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.675131518
Short name T746
Test name
Test status
Simulation time 72801945 ps
CPU time 1.1 seconds
Started Aug 02 06:42:55 PM PDT 24
Finished Aug 02 06:42:56 PM PDT 24
Peak memory 215332 kb
Host smart-272ccf37-05b4-4183-9f6a-c9b3076c7c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675131518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.675131518
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3984640425
Short name T349
Test name
Test status
Simulation time 207865593 ps
CPU time 1.52 seconds
Started Aug 02 06:42:54 PM PDT 24
Finished Aug 02 06:42:56 PM PDT 24
Peak memory 218760 kb
Host smart-36fed9b6-000c-4350-b3c6-f93aaa520665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984640425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3984640425
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2801611978
Short name T345
Test name
Test status
Simulation time 89958608 ps
CPU time 1.15 seconds
Started Aug 02 06:42:46 PM PDT 24
Finished Aug 02 06:42:48 PM PDT 24
Peak memory 217372 kb
Host smart-cdbb7118-12fc-4c50-8eaf-dea90698d40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801611978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2801611978
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3826048242
Short name T441
Test name
Test status
Simulation time 104977473 ps
CPU time 1.04 seconds
Started Aug 02 06:42:44 PM PDT 24
Finished Aug 02 06:42:45 PM PDT 24
Peak memory 218772 kb
Host smart-09571f3d-8e22-439c-aee3-21d06822507b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826048242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3826048242
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3406975699
Short name T468
Test name
Test status
Simulation time 22944194 ps
CPU time 1.22 seconds
Started Aug 02 06:42:55 PM PDT 24
Finished Aug 02 06:42:57 PM PDT 24
Peak memory 217400 kb
Host smart-93662108-416a-4579-b0fd-adc8794d030b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406975699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3406975699
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.3645791937
Short name T501
Test name
Test status
Simulation time 52981165 ps
CPU time 1.15 seconds
Started Aug 02 06:40:46 PM PDT 24
Finished Aug 02 06:40:47 PM PDT 24
Peak memory 206852 kb
Host smart-52d82833-f4d1-4860-b151-1d9c91e6fb30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645791937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3645791937
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2422731031
Short name T115
Test name
Test status
Simulation time 69206096 ps
CPU time 1.1 seconds
Started Aug 02 06:40:52 PM PDT 24
Finished Aug 02 06:40:54 PM PDT 24
Peak memory 216956 kb
Host smart-8899d2b0-39c5-403c-8586-07c8b37e787d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422731031 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2422731031
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.480353853
Short name T101
Test name
Test status
Simulation time 28244229 ps
CPU time 1 seconds
Started Aug 02 06:40:47 PM PDT 24
Finished Aug 02 06:40:48 PM PDT 24
Peak memory 219724 kb
Host smart-16fc0701-3a0a-4b53-9660-f33ea2e36fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480353853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.480353853
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3562572963
Short name T569
Test name
Test status
Simulation time 68771797 ps
CPU time 1.09 seconds
Started Aug 02 06:40:46 PM PDT 24
Finished Aug 02 06:40:47 PM PDT 24
Peak memory 217544 kb
Host smart-410647dc-74f1-43b6-bb6d-d1ad8b920b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562572963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3562572963
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.145411230
Short name T456
Test name
Test status
Simulation time 30349043 ps
CPU time 0.93 seconds
Started Aug 02 06:40:46 PM PDT 24
Finished Aug 02 06:40:48 PM PDT 24
Peak memory 215812 kb
Host smart-007831e7-f3b6-47ae-9726-fe55dacf9d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145411230 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.145411230
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1651488180
Short name T363
Test name
Test status
Simulation time 51455996 ps
CPU time 0.93 seconds
Started Aug 02 06:40:46 PM PDT 24
Finished Aug 02 06:40:47 PM PDT 24
Peak memory 215248 kb
Host smart-021d079e-2980-4c19-9979-f6347bb7e187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651488180 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1651488180
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.812831985
Short name T249
Test name
Test status
Simulation time 336746377 ps
CPU time 2.33 seconds
Started Aug 02 06:40:48 PM PDT 24
Finished Aug 02 06:40:50 PM PDT 24
Peak memory 215344 kb
Host smart-a0d1414d-771c-4d1b-a8c9-7f38032e6cf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812831985 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.812831985
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/280.edn_genbits.1240682708
Short name T875
Test name
Test status
Simulation time 65448617 ps
CPU time 1.37 seconds
Started Aug 02 06:42:54 PM PDT 24
Finished Aug 02 06:42:56 PM PDT 24
Peak memory 220112 kb
Host smart-7fa60852-a379-4fa2-a73a-f964ec49cc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240682708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1240682708
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3127950456
Short name T241
Test name
Test status
Simulation time 21161391 ps
CPU time 1.2 seconds
Started Aug 02 06:43:02 PM PDT 24
Finished Aug 02 06:43:03 PM PDT 24
Peak memory 217372 kb
Host smart-fef04285-9763-4e4d-8d44-456176dcd123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127950456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3127950456
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2335759065
Short name T24
Test name
Test status
Simulation time 38279232 ps
CPU time 1.12 seconds
Started Aug 02 06:42:59 PM PDT 24
Finished Aug 02 06:43:01 PM PDT 24
Peak memory 220020 kb
Host smart-231dff0f-f6fb-4cb5-a25f-3dfd4afb0c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335759065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2335759065
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.659827508
Short name T910
Test name
Test status
Simulation time 93129669 ps
CPU time 3.02 seconds
Started Aug 02 06:43:03 PM PDT 24
Finished Aug 02 06:43:06 PM PDT 24
Peak memory 220008 kb
Host smart-ec46fa54-f3a7-4a2d-bb96-91195b2b6923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659827508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.659827508
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.4232468295
Short name T430
Test name
Test status
Simulation time 44096259 ps
CPU time 1.62 seconds
Started Aug 02 06:42:58 PM PDT 24
Finished Aug 02 06:43:00 PM PDT 24
Peak memory 218692 kb
Host smart-66120dfa-23c9-4acf-88a8-571acb09695a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232468295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.4232468295
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3839098423
Short name T401
Test name
Test status
Simulation time 66330665 ps
CPU time 1.24 seconds
Started Aug 02 06:42:57 PM PDT 24
Finished Aug 02 06:42:58 PM PDT 24
Peak memory 218388 kb
Host smart-e3eabbc2-1f0c-4954-b7ee-c30119030dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839098423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3839098423
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.89377568
Short name T482
Test name
Test status
Simulation time 79521904 ps
CPU time 1.11 seconds
Started Aug 02 06:42:59 PM PDT 24
Finished Aug 02 06:43:00 PM PDT 24
Peak memory 217476 kb
Host smart-a1949f65-592b-41ed-92f8-b02fe1e3e879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89377568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.89377568
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1812094231
Short name T887
Test name
Test status
Simulation time 89430335 ps
CPU time 1.3 seconds
Started Aug 02 06:43:00 PM PDT 24
Finished Aug 02 06:43:01 PM PDT 24
Peak memory 217284 kb
Host smart-9d9ccbe1-f8b6-4e24-80a4-306fd2af173d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812094231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1812094231
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3147812194
Short name T488
Test name
Test status
Simulation time 67561211 ps
CPU time 1.17 seconds
Started Aug 02 06:43:02 PM PDT 24
Finished Aug 02 06:43:03 PM PDT 24
Peak memory 217544 kb
Host smart-c6cd4bd0-c67f-41f7-988a-2d3377c2ea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147812194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3147812194
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2584031377
Short name T909
Test name
Test status
Simulation time 37310307 ps
CPU time 1.67 seconds
Started Aug 02 06:43:00 PM PDT 24
Finished Aug 02 06:43:02 PM PDT 24
Peak memory 218796 kb
Host smart-440fbd37-c59a-4a1d-800e-31188b891479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584031377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2584031377
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.75338072
Short name T705
Test name
Test status
Simulation time 54136407 ps
CPU time 1.11 seconds
Started Aug 02 06:40:52 PM PDT 24
Finished Aug 02 06:40:53 PM PDT 24
Peak memory 219108 kb
Host smart-ce268ba5-75cf-45c7-802a-b426516a0560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75338072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.75338072
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1660960849
Short name T411
Test name
Test status
Simulation time 27146115 ps
CPU time 0.91 seconds
Started Aug 02 06:40:45 PM PDT 24
Finished Aug 02 06:40:46 PM PDT 24
Peak memory 206756 kb
Host smart-f1109bf8-0bf4-4b86-a1ea-9210f6dfa60b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660960849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1660960849
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2940036848
Short name T670
Test name
Test status
Simulation time 72724754 ps
CPU time 1.06 seconds
Started Aug 02 06:40:48 PM PDT 24
Finished Aug 02 06:40:49 PM PDT 24
Peak memory 216952 kb
Host smart-1f730999-63a4-48da-9004-bec163a923a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940036848 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2940036848
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2082390587
Short name T118
Test name
Test status
Simulation time 52958970 ps
CPU time 1.22 seconds
Started Aug 02 06:40:51 PM PDT 24
Finished Aug 02 06:40:53 PM PDT 24
Peak memory 219692 kb
Host smart-29b28281-ba22-4256-986d-e85a96bbfbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082390587 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2082390587
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1607644507
Short name T46
Test name
Test status
Simulation time 64926291 ps
CPU time 1.73 seconds
Started Aug 02 06:40:45 PM PDT 24
Finished Aug 02 06:40:47 PM PDT 24
Peak memory 220088 kb
Host smart-2509fc28-edeb-4860-970d-c723289a0378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607644507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1607644507
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1567756263
Short name T608
Test name
Test status
Simulation time 37915563 ps
CPU time 0.98 seconds
Started Aug 02 06:40:46 PM PDT 24
Finished Aug 02 06:40:47 PM PDT 24
Peak memory 224076 kb
Host smart-11573b63-8a60-4e37-a18b-187f7cab9c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567756263 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1567756263
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.229607506
Short name T587
Test name
Test status
Simulation time 15721318 ps
CPU time 1 seconds
Started Aug 02 06:40:51 PM PDT 24
Finished Aug 02 06:40:52 PM PDT 24
Peak memory 215312 kb
Host smart-f22bbe61-6d7c-480c-b17d-43bf89c0e8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229607506 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.229607506
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2424442046
Short name T772
Test name
Test status
Simulation time 137841173 ps
CPU time 2.64 seconds
Started Aug 02 06:40:48 PM PDT 24
Finished Aug 02 06:40:51 PM PDT 24
Peak memory 217204 kb
Host smart-52b25207-c3a8-442b-b5f7-147d3ba515c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424442046 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2424442046
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2304823528
Short name T226
Test name
Test status
Simulation time 61782584828 ps
CPU time 391.76 seconds
Started Aug 02 06:40:47 PM PDT 24
Finished Aug 02 06:47:19 PM PDT 24
Peak memory 223744 kb
Host smart-ee82a63a-59af-463a-9b90-169a5e122414
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304823528 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2304823528
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3119676228
Short name T471
Test name
Test status
Simulation time 72366525 ps
CPU time 1.09 seconds
Started Aug 02 06:42:59 PM PDT 24
Finished Aug 02 06:43:01 PM PDT 24
Peak memory 217392 kb
Host smart-e7e22057-1f94-43b4-8410-a7aa48e1f4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119676228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3119676228
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.11801448
Short name T846
Test name
Test status
Simulation time 46507768 ps
CPU time 1.52 seconds
Started Aug 02 06:43:01 PM PDT 24
Finished Aug 02 06:43:03 PM PDT 24
Peak memory 218464 kb
Host smart-94619e53-61d2-4830-b067-6fe98d0ea347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11801448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.11801448
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1576007483
Short name T638
Test name
Test status
Simulation time 82381686 ps
CPU time 1.57 seconds
Started Aug 02 06:43:01 PM PDT 24
Finished Aug 02 06:43:02 PM PDT 24
Peak memory 218980 kb
Host smart-475924d1-8b9d-4313-8e70-87140339fbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576007483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1576007483
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3706079620
Short name T957
Test name
Test status
Simulation time 28022326 ps
CPU time 1.21 seconds
Started Aug 02 06:42:59 PM PDT 24
Finished Aug 02 06:43:00 PM PDT 24
Peak memory 217300 kb
Host smart-77669aff-3b86-403f-8067-fde07b0280fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706079620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3706079620
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2640300704
Short name T34
Test name
Test status
Simulation time 50831621 ps
CPU time 1.6 seconds
Started Aug 02 06:42:59 PM PDT 24
Finished Aug 02 06:43:00 PM PDT 24
Peak memory 218712 kb
Host smart-5a7b2851-858b-43d7-a172-f68ea82d938b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640300704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2640300704
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2610103401
Short name T539
Test name
Test status
Simulation time 95623809 ps
CPU time 1.1 seconds
Started Aug 02 06:42:57 PM PDT 24
Finished Aug 02 06:42:58 PM PDT 24
Peak memory 217436 kb
Host smart-5236d522-8e7f-472a-a908-cf81d0ae6225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610103401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2610103401
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3366940901
Short name T466
Test name
Test status
Simulation time 68839730 ps
CPU time 1.37 seconds
Started Aug 02 06:43:00 PM PDT 24
Finished Aug 02 06:43:02 PM PDT 24
Peak memory 220036 kb
Host smart-87f77d9e-68b8-4a2d-869c-1b2f2d31e003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366940901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3366940901
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.154623677
Short name T331
Test name
Test status
Simulation time 42110918 ps
CPU time 1.69 seconds
Started Aug 02 06:43:03 PM PDT 24
Finished Aug 02 06:43:04 PM PDT 24
Peak memory 218568 kb
Host smart-93cc294f-caf5-4496-9013-07788899240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154623677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.154623677
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1003584932
Short name T453
Test name
Test status
Simulation time 43406809 ps
CPU time 1.49 seconds
Started Aug 02 06:43:01 PM PDT 24
Finished Aug 02 06:43:03 PM PDT 24
Peak memory 217528 kb
Host smart-f7838f77-b393-4779-a8fb-ce870e330bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003584932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1003584932
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2398608308
Short name T628
Test name
Test status
Simulation time 73767863 ps
CPU time 1.32 seconds
Started Aug 02 06:43:01 PM PDT 24
Finished Aug 02 06:43:02 PM PDT 24
Peak memory 217324 kb
Host smart-a0cf4c56-97df-4a35-8a66-988c0a86110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398608308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2398608308
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.230980717
Short name T302
Test name
Test status
Simulation time 22508954 ps
CPU time 1.15 seconds
Started Aug 02 06:39:53 PM PDT 24
Finished Aug 02 06:39:55 PM PDT 24
Peak memory 218712 kb
Host smart-9537413c-737e-429c-9fc2-c286d303e7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230980717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.230980717
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1676629277
Short name T408
Test name
Test status
Simulation time 39547497 ps
CPU time 0.83 seconds
Started Aug 02 06:39:54 PM PDT 24
Finished Aug 02 06:39:55 PM PDT 24
Peak memory 206068 kb
Host smart-fc1d118b-dcee-446d-b6a1-2ebe72856db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676629277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1676629277
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3396119285
Short name T26
Test name
Test status
Simulation time 12200624 ps
CPU time 0.91 seconds
Started Aug 02 06:39:54 PM PDT 24
Finished Aug 02 06:39:55 PM PDT 24
Peak memory 215408 kb
Host smart-6d83815a-2456-473b-b7f7-1edb6e966fc9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396119285 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3396119285
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.4215785583
Short name T612
Test name
Test status
Simulation time 280133790 ps
CPU time 1.26 seconds
Started Aug 02 06:40:02 PM PDT 24
Finished Aug 02 06:40:04 PM PDT 24
Peak memory 216928 kb
Host smart-881d1c7e-3f79-4c66-862d-4e7464f15fec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215785583 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.4215785583
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2040229692
Short name T146
Test name
Test status
Simulation time 50668612 ps
CPU time 1.13 seconds
Started Aug 02 06:39:54 PM PDT 24
Finished Aug 02 06:39:56 PM PDT 24
Peak memory 229632 kb
Host smart-db80c4fe-914e-44d7-a276-dab67f5aeed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040229692 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2040229692
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.468008304
Short name T519
Test name
Test status
Simulation time 131784768 ps
CPU time 2.5 seconds
Started Aug 02 06:39:53 PM PDT 24
Finished Aug 02 06:39:56 PM PDT 24
Peak memory 217576 kb
Host smart-cc1b8db0-01a8-47a9-a74e-ac273c3e68a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468008304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.468008304
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3888362602
Short name T702
Test name
Test status
Simulation time 91557824 ps
CPU time 0.9 seconds
Started Aug 02 06:39:56 PM PDT 24
Finished Aug 02 06:39:57 PM PDT 24
Peak memory 215212 kb
Host smart-963a3446-9bc9-4f8d-bd54-3c05bb5030f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888362602 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3888362602
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_smoke.4246000709
Short name T798
Test name
Test status
Simulation time 146257255 ps
CPU time 0.97 seconds
Started Aug 02 06:39:57 PM PDT 24
Finished Aug 02 06:39:58 PM PDT 24
Peak memory 215288 kb
Host smart-608b9270-30dc-4f06-9b43-7b21b0eb35ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246000709 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.4246000709
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.333277345
Short name T537
Test name
Test status
Simulation time 210465493 ps
CPU time 4.74 seconds
Started Aug 02 06:39:55 PM PDT 24
Finished Aug 02 06:40:00 PM PDT 24
Peak memory 215280 kb
Host smart-9d2cfc33-39de-4334-ad8d-5b23f1ccc8aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333277345 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.333277345
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3630579312
Short name T756
Test name
Test status
Simulation time 100215230040 ps
CPU time 266.47 seconds
Started Aug 02 06:39:54 PM PDT 24
Finished Aug 02 06:44:21 PM PDT 24
Peak memory 218676 kb
Host smart-d29b2ee7-fba3-4414-a7c5-dc25edb74dec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630579312 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3630579312
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3446719462
Short name T822
Test name
Test status
Simulation time 37727772 ps
CPU time 1.14 seconds
Started Aug 02 06:40:45 PM PDT 24
Finished Aug 02 06:40:47 PM PDT 24
Peak memory 221032 kb
Host smart-18d03c1d-ccfc-44f2-be8f-82757e3eb361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446719462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3446719462
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3023514087
Short name T665
Test name
Test status
Simulation time 83564685 ps
CPU time 0.84 seconds
Started Aug 02 06:40:48 PM PDT 24
Finished Aug 02 06:40:49 PM PDT 24
Peak memory 206728 kb
Host smart-fa40589c-bd67-4222-a5d7-47ebab67ba55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023514087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3023514087
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1762813876
Short name T356
Test name
Test status
Simulation time 28755504 ps
CPU time 0.87 seconds
Started Aug 02 06:40:49 PM PDT 24
Finished Aug 02 06:40:50 PM PDT 24
Peak memory 215432 kb
Host smart-ee95bb15-799d-45cb-8ee9-f359010e9e37
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762813876 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1762813876
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1962064843
Short name T716
Test name
Test status
Simulation time 41134277 ps
CPU time 1.41 seconds
Started Aug 02 06:40:48 PM PDT 24
Finished Aug 02 06:40:49 PM PDT 24
Peak memory 216848 kb
Host smart-2b610f65-5786-435b-b071-4b16ac8bb10e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962064843 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1962064843
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2138429141
Short name T184
Test name
Test status
Simulation time 33977960 ps
CPU time 0.91 seconds
Started Aug 02 06:40:50 PM PDT 24
Finished Aug 02 06:40:52 PM PDT 24
Peak memory 218360 kb
Host smart-0ed0a83e-8d17-4400-a2e1-c5c60210f860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138429141 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2138429141
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3998951136
Short name T878
Test name
Test status
Simulation time 72312568 ps
CPU time 1.62 seconds
Started Aug 02 06:40:53 PM PDT 24
Finished Aug 02 06:40:54 PM PDT 24
Peak memory 218660 kb
Host smart-cd3bf9af-6224-4f0b-86ee-cfb6a12e6e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998951136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3998951136
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.4078117961
Short name T518
Test name
Test status
Simulation time 32968142 ps
CPU time 0.92 seconds
Started Aug 02 06:40:52 PM PDT 24
Finished Aug 02 06:40:53 PM PDT 24
Peak memory 215844 kb
Host smart-92a68955-cab2-4515-9973-104743159c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078117961 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.4078117961
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2296126295
Short name T979
Test name
Test status
Simulation time 16879325 ps
CPU time 1.02 seconds
Started Aug 02 06:40:52 PM PDT 24
Finished Aug 02 06:40:54 PM PDT 24
Peak memory 215248 kb
Host smart-5dc5b686-afe2-4c64-9a9e-d66b1d3d69ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296126295 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2296126295
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.246448519
Short name T475
Test name
Test status
Simulation time 463051053 ps
CPU time 5.46 seconds
Started Aug 02 06:40:48 PM PDT 24
Finished Aug 02 06:40:54 PM PDT 24
Peak memory 217264 kb
Host smart-de64d450-87dd-4269-b619-fbd9a45e6840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246448519 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.246448519
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.32146358
Short name T237
Test name
Test status
Simulation time 106627971176 ps
CPU time 1104.55 seconds
Started Aug 02 06:40:52 PM PDT 24
Finished Aug 02 06:59:17 PM PDT 24
Peak memory 221620 kb
Host smart-174945b8-f222-47c5-a48f-3c6161e4a208
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32146358 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.32146358
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2841333762
Short name T818
Test name
Test status
Simulation time 92750369 ps
CPU time 1.22 seconds
Started Aug 02 06:40:48 PM PDT 24
Finished Aug 02 06:40:49 PM PDT 24
Peak memory 218528 kb
Host smart-1ced1745-6b49-43ce-89a5-4bd05b4b524f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841333762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2841333762
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.591071478
Short name T850
Test name
Test status
Simulation time 26084571 ps
CPU time 0.95 seconds
Started Aug 02 06:40:57 PM PDT 24
Finished Aug 02 06:40:58 PM PDT 24
Peak memory 206756 kb
Host smart-7da864b7-65c5-496d-9020-5d2af30d04f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591071478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.591071478
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2807516086
Short name T107
Test name
Test status
Simulation time 19781944 ps
CPU time 0.95 seconds
Started Aug 02 06:40:51 PM PDT 24
Finished Aug 02 06:40:52 PM PDT 24
Peak memory 216212 kb
Host smart-c106d5c2-3e65-4fdf-b8c1-2fa93c13df44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807516086 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2807516086
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2144700461
Short name T931
Test name
Test status
Simulation time 25394556 ps
CPU time 1.18 seconds
Started Aug 02 06:40:57 PM PDT 24
Finished Aug 02 06:40:58 PM PDT 24
Peak memory 215620 kb
Host smart-e37489d8-7011-4eaf-9c43-cfab647de393
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144700461 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2144700461
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.50624225
Short name T151
Test name
Test status
Simulation time 25610089 ps
CPU time 1.05 seconds
Started Aug 02 06:40:47 PM PDT 24
Finished Aug 02 06:40:48 PM PDT 24
Peak memory 219776 kb
Host smart-300b89f8-651c-43b3-9063-2583fb49f51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50624225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.50624225
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.733238240
Short name T708
Test name
Test status
Simulation time 88531638 ps
CPU time 1.5 seconds
Started Aug 02 06:40:47 PM PDT 24
Finished Aug 02 06:40:49 PM PDT 24
Peak memory 218988 kb
Host smart-d74368cd-036d-4291-b0c5-1ed8a8fa7790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733238240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.733238240
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_smoke.2776902558
Short name T801
Test name
Test status
Simulation time 150049804 ps
CPU time 0.9 seconds
Started Aug 02 06:40:53 PM PDT 24
Finished Aug 02 06:40:54 PM PDT 24
Peak memory 215268 kb
Host smart-cf1378a0-525c-4299-8c06-9f8ae557123a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776902558 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2776902558
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.238936688
Short name T19
Test name
Test status
Simulation time 76854656 ps
CPU time 1.1 seconds
Started Aug 02 06:40:49 PM PDT 24
Finished Aug 02 06:40:50 PM PDT 24
Peak memory 207168 kb
Host smart-c1f0896f-1218-45a4-a36b-177750afad67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238936688 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.238936688
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_alert.398252916
Short name T446
Test name
Test status
Simulation time 39930451 ps
CPU time 1.16 seconds
Started Aug 02 06:40:53 PM PDT 24
Finished Aug 02 06:40:55 PM PDT 24
Peak memory 218520 kb
Host smart-cee4d3d5-1a7f-47fb-b09e-bb46287bb67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398252916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.398252916
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1631246193
Short name T389
Test name
Test status
Simulation time 12587093 ps
CPU time 0.9 seconds
Started Aug 02 06:40:56 PM PDT 24
Finished Aug 02 06:40:57 PM PDT 24
Peak memory 206684 kb
Host smart-844ac821-686a-46b4-80c0-c7f7bc73400b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631246193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1631246193
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1435120891
Short name T961
Test name
Test status
Simulation time 40829215 ps
CPU time 0.82 seconds
Started Aug 02 06:40:56 PM PDT 24
Finished Aug 02 06:40:57 PM PDT 24
Peak memory 215392 kb
Host smart-d42c9ede-35c5-453a-b103-1a7d799d9d4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435120891 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1435120891
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.770297102
Short name T618
Test name
Test status
Simulation time 55193051 ps
CPU time 1.21 seconds
Started Aug 02 06:40:53 PM PDT 24
Finished Aug 02 06:40:54 PM PDT 24
Peak memory 216976 kb
Host smart-1644b86f-e9c1-484d-ba26-b58cabbbebab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770297102 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.770297102
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.4124988789
Short name T114
Test name
Test status
Simulation time 22749357 ps
CPU time 1.1 seconds
Started Aug 02 06:40:52 PM PDT 24
Finished Aug 02 06:40:53 PM PDT 24
Peak memory 218568 kb
Host smart-20819572-bdc8-4dae-932f-d312d72feeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124988789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.4124988789
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1342810345
Short name T942
Test name
Test status
Simulation time 55897868 ps
CPU time 1.31 seconds
Started Aug 02 06:40:54 PM PDT 24
Finished Aug 02 06:40:55 PM PDT 24
Peak memory 218584 kb
Host smart-ae2ea25e-06c4-4321-a176-92cc822371b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342810345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1342810345
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_smoke.822774113
Short name T387
Test name
Test status
Simulation time 109795270 ps
CPU time 0.94 seconds
Started Aug 02 06:40:57 PM PDT 24
Finished Aug 02 06:40:58 PM PDT 24
Peak memory 214888 kb
Host smart-9a31a8d4-33ea-4e5c-ab6f-41641db673d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822774113 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.822774113
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3883693597
Short name T515
Test name
Test status
Simulation time 523775280 ps
CPU time 5.72 seconds
Started Aug 02 06:40:53 PM PDT 24
Finished Aug 02 06:40:59 PM PDT 24
Peak memory 220520 kb
Host smart-8c54f622-e968-49ff-8813-1af7d12e99e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883693597 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3883693597
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3598268711
Short name T234
Test name
Test status
Simulation time 30956342100 ps
CPU time 663.47 seconds
Started Aug 02 06:40:53 PM PDT 24
Finished Aug 02 06:51:57 PM PDT 24
Peak memory 223644 kb
Host smart-9f648001-cb77-49cf-9888-8a91fbca4572
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598268711 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3598268711
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.879951338
Short name T815
Test name
Test status
Simulation time 197593349 ps
CPU time 1.28 seconds
Started Aug 02 06:40:57 PM PDT 24
Finished Aug 02 06:40:58 PM PDT 24
Peak memory 219492 kb
Host smart-62b43825-b8e5-4592-802d-2a75ee3c9da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879951338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.879951338
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.166260350
Short name T871
Test name
Test status
Simulation time 125297488 ps
CPU time 0.9 seconds
Started Aug 02 06:40:55 PM PDT 24
Finished Aug 02 06:40:56 PM PDT 24
Peak memory 206672 kb
Host smart-377bb9cc-97f1-45e8-9c0b-9a4aa85db6d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166260350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.166260350
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_err.233298984
Short name T135
Test name
Test status
Simulation time 52218672 ps
CPU time 1.14 seconds
Started Aug 02 06:40:55 PM PDT 24
Finished Aug 02 06:40:56 PM PDT 24
Peak memory 229676 kb
Host smart-c3be9a85-3e90-4749-b178-eccd449ce8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233298984 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.233298984
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_intr.2715550525
Short name T42
Test name
Test status
Simulation time 22442348 ps
CPU time 1.29 seconds
Started Aug 02 06:40:55 PM PDT 24
Finished Aug 02 06:40:57 PM PDT 24
Peak memory 224140 kb
Host smart-c87b626f-1311-41d9-8880-3369c6768796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715550525 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2715550525
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.4264281750
Short name T245
Test name
Test status
Simulation time 16685047 ps
CPU time 1.02 seconds
Started Aug 02 06:40:56 PM PDT 24
Finished Aug 02 06:40:57 PM PDT 24
Peak memory 207108 kb
Host smart-30fdf50f-329e-490b-8b25-1bb4c2349036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264281750 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.4264281750
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3037964902
Short name T649
Test name
Test status
Simulation time 571171551 ps
CPU time 3.75 seconds
Started Aug 02 06:40:55 PM PDT 24
Finished Aug 02 06:40:59 PM PDT 24
Peak memory 217076 kb
Host smart-41aeecfe-65eb-41bc-85ce-f4f5ed6c1839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037964902 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3037964902
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3840327503
Short name T403
Test name
Test status
Simulation time 227694321433 ps
CPU time 1474.91 seconds
Started Aug 02 06:40:53 PM PDT 24
Finished Aug 02 07:05:29 PM PDT 24
Peak memory 226912 kb
Host smart-1d4cc2d4-9057-4cf0-9d2f-a75b80c21dc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840327503 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3840327503
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2048585160
Short name T978
Test name
Test status
Simulation time 42883768 ps
CPU time 1.18 seconds
Started Aug 02 06:40:54 PM PDT 24
Finished Aug 02 06:40:55 PM PDT 24
Peak memory 219796 kb
Host smart-0d8ba2c6-c280-4d51-be75-6e49e6c23146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048585160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2048585160
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1819939195
Short name T616
Test name
Test status
Simulation time 35805799 ps
CPU time 0.86 seconds
Started Aug 02 06:40:54 PM PDT 24
Finished Aug 02 06:40:55 PM PDT 24
Peak memory 206024 kb
Host smart-dc3da265-e309-4914-a008-d4fe99fa8adb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819939195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1819939195
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1096587984
Short name T138
Test name
Test status
Simulation time 40194223 ps
CPU time 0.86 seconds
Started Aug 02 06:40:53 PM PDT 24
Finished Aug 02 06:40:54 PM PDT 24
Peak memory 216284 kb
Host smart-3a7ee8e7-ac8c-4a24-b614-d3cdd4edb718
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096587984 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1096587984
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2108249047
Short name T477
Test name
Test status
Simulation time 37222243 ps
CPU time 1.17 seconds
Started Aug 02 06:40:56 PM PDT 24
Finished Aug 02 06:40:57 PM PDT 24
Peak memory 218680 kb
Host smart-67d84b23-4a67-4066-8ad6-03560e12f174
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108249047 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2108249047
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3671281838
Short name T669
Test name
Test status
Simulation time 20050976 ps
CPU time 1.07 seconds
Started Aug 02 06:40:55 PM PDT 24
Finished Aug 02 06:40:56 PM PDT 24
Peak memory 218532 kb
Host smart-24dcb617-f060-4e2d-abca-783511e13659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671281838 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3671281838
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2696661188
Short name T394
Test name
Test status
Simulation time 43992411 ps
CPU time 1.6 seconds
Started Aug 02 06:40:56 PM PDT 24
Finished Aug 02 06:40:57 PM PDT 24
Peak memory 215380 kb
Host smart-c6fcd847-93b1-43b8-ac51-b588431ec265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696661188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2696661188
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1683185418
Short name T38
Test name
Test status
Simulation time 24737145 ps
CPU time 1.07 seconds
Started Aug 02 06:40:56 PM PDT 24
Finished Aug 02 06:40:57 PM PDT 24
Peak memory 224096 kb
Host smart-fee26808-3533-4ad8-ad97-edb0bf8017f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683185418 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1683185418
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1417039458
Short name T583
Test name
Test status
Simulation time 30323920 ps
CPU time 0.94 seconds
Started Aug 02 06:40:54 PM PDT 24
Finished Aug 02 06:40:55 PM PDT 24
Peak memory 215292 kb
Host smart-377159c1-cd22-4803-961a-6758ce35cd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417039458 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1417039458
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3040950240
Short name T96
Test name
Test status
Simulation time 596114799 ps
CPU time 2.36 seconds
Started Aug 02 06:40:54 PM PDT 24
Finished Aug 02 06:40:56 PM PDT 24
Peak memory 217336 kb
Host smart-ec2a43c4-d379-40c6-89a4-7d18c9901fe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040950240 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3040950240
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.695030231
Short name T231
Test name
Test status
Simulation time 113773508318 ps
CPU time 677.37 seconds
Started Aug 02 06:40:54 PM PDT 24
Finished Aug 02 06:52:12 PM PDT 24
Peak memory 219364 kb
Host smart-df327b90-8a39-4ee1-b535-88647a75df4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695030231 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.695030231
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1401962248
Short name T860
Test name
Test status
Simulation time 80759810 ps
CPU time 1.2 seconds
Started Aug 02 06:40:57 PM PDT 24
Finished Aug 02 06:40:58 PM PDT 24
Peak memory 219732 kb
Host smart-190a238d-9ed1-4c31-8abc-abf3f1ae5715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401962248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1401962248
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1815998043
Short name T424
Test name
Test status
Simulation time 28332520 ps
CPU time 0.95 seconds
Started Aug 02 06:40:54 PM PDT 24
Finished Aug 02 06:40:55 PM PDT 24
Peak memory 206712 kb
Host smart-a0995276-1b83-4a82-b1f7-cb85133e1d1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815998043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1815998043
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2728563965
Short name T977
Test name
Test status
Simulation time 13434390 ps
CPU time 0.86 seconds
Started Aug 02 06:40:54 PM PDT 24
Finished Aug 02 06:40:55 PM PDT 24
Peak memory 216216 kb
Host smart-adc5e5ca-a855-43fa-8758-a7f5f0a9e005
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728563965 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2728563965
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2662987539
Short name T527
Test name
Test status
Simulation time 124501642 ps
CPU time 1.15 seconds
Started Aug 02 06:40:53 PM PDT 24
Finished Aug 02 06:40:55 PM PDT 24
Peak memory 219412 kb
Host smart-3dee3403-ea7f-40ce-b6f9-ec85b1cfe861
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662987539 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2662987539
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_genbits.2144848560
Short name T824
Test name
Test status
Simulation time 36597929 ps
CPU time 1.36 seconds
Started Aug 02 06:40:55 PM PDT 24
Finished Aug 02 06:40:57 PM PDT 24
Peak memory 217248 kb
Host smart-dcf71168-27b8-4018-a5fa-2ec372858db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144848560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2144848560
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1910162672
Short name T83
Test name
Test status
Simulation time 51488335 ps
CPU time 0.84 seconds
Started Aug 02 06:40:56 PM PDT 24
Finished Aug 02 06:40:57 PM PDT 24
Peak memory 215676 kb
Host smart-f9254f0b-f8c0-4af1-8613-6ffcb59a7281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910162672 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1910162672
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2415915928
Short name T487
Test name
Test status
Simulation time 21218767 ps
CPU time 0.94 seconds
Started Aug 02 06:40:55 PM PDT 24
Finished Aug 02 06:40:56 PM PDT 24
Peak memory 215364 kb
Host smart-16e92843-e10c-4a81-9f13-d1cbf1a0828d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415915928 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2415915928
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.58757113
Short name T812
Test name
Test status
Simulation time 296174541 ps
CPU time 2.22 seconds
Started Aug 02 06:40:55 PM PDT 24
Finished Aug 02 06:40:57 PM PDT 24
Peak memory 220340 kb
Host smart-1393ba09-9570-4190-9900-f431984dbeea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58757113 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.58757113
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3162034940
Short name T925
Test name
Test status
Simulation time 173130776755 ps
CPU time 1835.06 seconds
Started Aug 02 06:40:56 PM PDT 24
Finished Aug 02 07:11:31 PM PDT 24
Peak memory 225960 kb
Host smart-4729c122-e4cd-446d-af37-288fcc824ccc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162034940 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3162034940
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3084016971
Short name T189
Test name
Test status
Simulation time 28751495 ps
CPU time 1.29 seconds
Started Aug 02 06:41:03 PM PDT 24
Finished Aug 02 06:41:05 PM PDT 24
Peak memory 220740 kb
Host smart-123ad093-e419-42eb-8ce4-d279f0bf0e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084016971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3084016971
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1951461238
Short name T566
Test name
Test status
Simulation time 14142088 ps
CPU time 0.88 seconds
Started Aug 02 06:41:00 PM PDT 24
Finished Aug 02 06:41:01 PM PDT 24
Peak memory 206912 kb
Host smart-99f31239-fb56-447f-92c8-63c58e052962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951461238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1951461238
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.552449624
Short name T828
Test name
Test status
Simulation time 38023737 ps
CPU time 0.84 seconds
Started Aug 02 06:41:03 PM PDT 24
Finished Aug 02 06:41:04 PM PDT 24
Peak memory 216356 kb
Host smart-a6b1b060-af68-49e8-9e35-7f0c31e139e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552449624 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.552449624
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2949204946
Short name T891
Test name
Test status
Simulation time 103555949 ps
CPU time 1.08 seconds
Started Aug 02 06:41:05 PM PDT 24
Finished Aug 02 06:41:06 PM PDT 24
Peak memory 218192 kb
Host smart-c4fab7d7-43e6-476e-89ef-5151a56861cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949204946 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2949204946
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2778664368
Short name T804
Test name
Test status
Simulation time 30518300 ps
CPU time 1.01 seconds
Started Aug 02 06:41:03 PM PDT 24
Finished Aug 02 06:41:04 PM PDT 24
Peak memory 223852 kb
Host smart-b2f20163-d1ad-4cde-b661-01d445a023d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778664368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2778664368
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.4026982817
Short name T76
Test name
Test status
Simulation time 80278559 ps
CPU time 2.94 seconds
Started Aug 02 06:40:56 PM PDT 24
Finished Aug 02 06:40:59 PM PDT 24
Peak memory 220216 kb
Host smart-5be5abd5-db95-473d-abb0-a6ba0b6e5e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026982817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.4026982817
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.4050376143
Short name T637
Test name
Test status
Simulation time 38766688 ps
CPU time 0.91 seconds
Started Aug 02 06:41:03 PM PDT 24
Finished Aug 02 06:41:04 PM PDT 24
Peak memory 215488 kb
Host smart-7ed2245f-2e64-44c8-b66c-d6a286670a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050376143 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.4050376143
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.826443811
Short name T489
Test name
Test status
Simulation time 25603964 ps
CPU time 0.96 seconds
Started Aug 02 06:40:53 PM PDT 24
Finished Aug 02 06:40:54 PM PDT 24
Peak memory 215304 kb
Host smart-69e15906-e396-483e-9740-fd3bf5fb80d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826443811 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.826443811
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.140183375
Short name T675
Test name
Test status
Simulation time 105238205 ps
CPU time 2.9 seconds
Started Aug 02 06:40:54 PM PDT 24
Finished Aug 02 06:40:57 PM PDT 24
Peak memory 218636 kb
Host smart-ea557585-1ef6-4609-b91b-38385b30f6a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140183375 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.140183375
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2324780062
Short name T983
Test name
Test status
Simulation time 167408549536 ps
CPU time 1236.19 seconds
Started Aug 02 06:40:56 PM PDT 24
Finished Aug 02 07:01:33 PM PDT 24
Peak memory 223524 kb
Host smart-7c31ef36-3908-420c-af06-8840c0b11d80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324780062 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2324780062
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert_test.4096109885
Short name T509
Test name
Test status
Simulation time 14956958 ps
CPU time 0.92 seconds
Started Aug 02 06:41:05 PM PDT 24
Finished Aug 02 06:41:06 PM PDT 24
Peak memory 206688 kb
Host smart-ba48cab0-804c-43a4-92e3-11fffc64efcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096109885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.4096109885
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1941417866
Short name T197
Test name
Test status
Simulation time 17758567 ps
CPU time 0.98 seconds
Started Aug 02 06:41:04 PM PDT 24
Finished Aug 02 06:41:05 PM PDT 24
Peak memory 216416 kb
Host smart-b6567e97-3b8a-4862-bbc4-e98d8851968d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941417866 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1941417866
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.31818946
Short name T120
Test name
Test status
Simulation time 50013355 ps
CPU time 1.2 seconds
Started Aug 02 06:41:03 PM PDT 24
Finished Aug 02 06:41:05 PM PDT 24
Peak memory 217008 kb
Host smart-63eef285-b2be-42de-bc97-364a436f2471
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31818946 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_dis
able_auto_req_mode.31818946
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3773639213
Short name T44
Test name
Test status
Simulation time 29772530 ps
CPU time 1.09 seconds
Started Aug 02 06:41:07 PM PDT 24
Finished Aug 02 06:41:08 PM PDT 24
Peak memory 223868 kb
Host smart-4e0ba001-e50c-489d-bb85-0e5bf20abd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773639213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3773639213
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1417605941
Short name T360
Test name
Test status
Simulation time 55187094 ps
CPU time 1 seconds
Started Aug 02 06:41:02 PM PDT 24
Finished Aug 02 06:41:03 PM PDT 24
Peak memory 217272 kb
Host smart-71c0a61b-2b89-45b9-b471-4649eaf45514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417605941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1417605941
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2973646348
Short name T93
Test name
Test status
Simulation time 27665139 ps
CPU time 0.84 seconds
Started Aug 02 06:41:03 PM PDT 24
Finished Aug 02 06:41:04 PM PDT 24
Peak memory 215692 kb
Host smart-b96bfc53-e097-4fce-ba6a-30f2634228c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973646348 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2973646348
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.346176059
Short name T247
Test name
Test status
Simulation time 34536408 ps
CPU time 0.97 seconds
Started Aug 02 06:41:02 PM PDT 24
Finished Aug 02 06:41:03 PM PDT 24
Peak memory 215360 kb
Host smart-41810546-5eb0-4c7f-99e6-4d21427739b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346176059 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.346176059
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2261573043
Short name T674
Test name
Test status
Simulation time 28474843 ps
CPU time 1.24 seconds
Started Aug 02 06:41:03 PM PDT 24
Finished Aug 02 06:41:04 PM PDT 24
Peak memory 215344 kb
Host smart-5cc79f7f-b960-4f28-8b50-f0400786a9ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261573043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2261573043
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1513961218
Short name T514
Test name
Test status
Simulation time 18806260329 ps
CPU time 413.55 seconds
Started Aug 02 06:41:03 PM PDT 24
Finished Aug 02 06:47:56 PM PDT 24
Peak memory 220272 kb
Host smart-36204360-a78b-4ce4-975a-6e1469ec712d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513961218 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1513961218
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1701411396
Short name T664
Test name
Test status
Simulation time 96027657 ps
CPU time 1.17 seconds
Started Aug 02 06:41:03 PM PDT 24
Finished Aug 02 06:41:04 PM PDT 24
Peak memory 220564 kb
Host smart-7f9552ce-8f59-468b-a8b6-8a26c39a04b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701411396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1701411396
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.448305030
Short name T355
Test name
Test status
Simulation time 69063638 ps
CPU time 0.78 seconds
Started Aug 02 06:41:03 PM PDT 24
Finished Aug 02 06:41:04 PM PDT 24
Peak memory 206860 kb
Host smart-25b660fe-4cff-4c38-9ec6-a980a429095b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448305030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.448305030
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.960040781
Short name T182
Test name
Test status
Simulation time 11408385 ps
CPU time 0.9 seconds
Started Aug 02 06:41:01 PM PDT 24
Finished Aug 02 06:41:02 PM PDT 24
Peak memory 215416 kb
Host smart-4cd3fabc-8a9d-441b-abd0-c9984d4b9fe6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960040781 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.960040781
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.654210380
Short name T409
Test name
Test status
Simulation time 67321297 ps
CPU time 1.1 seconds
Started Aug 02 06:41:02 PM PDT 24
Finished Aug 02 06:41:03 PM PDT 24
Peak memory 216860 kb
Host smart-06cd617b-4de5-41c5-9da1-120f133cdded
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654210380 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.654210380
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3925260241
Short name T719
Test name
Test status
Simulation time 47776751 ps
CPU time 1.18 seconds
Started Aug 02 06:41:04 PM PDT 24
Finished Aug 02 06:41:06 PM PDT 24
Peak memory 219772 kb
Host smart-525ce7e5-2bbe-4037-a311-5e51cc0a41d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925260241 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3925260241
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1679413843
Short name T787
Test name
Test status
Simulation time 55395698 ps
CPU time 1.91 seconds
Started Aug 02 06:41:00 PM PDT 24
Finished Aug 02 06:41:02 PM PDT 24
Peak memory 218636 kb
Host smart-daa71312-705c-415f-b3e5-fb408858ef49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679413843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1679413843
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2258374429
Short name T758
Test name
Test status
Simulation time 32684321 ps
CPU time 1.01 seconds
Started Aug 02 06:41:04 PM PDT 24
Finished Aug 02 06:41:05 PM PDT 24
Peak memory 224060 kb
Host smart-8a4372ea-c249-4f69-9ab5-9cc0567a07d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258374429 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2258374429
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.2350716526
Short name T904
Test name
Test status
Simulation time 32280031 ps
CPU time 0.89 seconds
Started Aug 02 06:41:02 PM PDT 24
Finished Aug 02 06:41:03 PM PDT 24
Peak memory 215312 kb
Host smart-30c1c9f8-30fe-45aa-ae6d-3b332215f200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350716526 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2350716526
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3532962006
Short name T448
Test name
Test status
Simulation time 789419100 ps
CPU time 5.22 seconds
Started Aug 02 06:41:00 PM PDT 24
Finished Aug 02 06:41:06 PM PDT 24
Peak memory 217428 kb
Host smart-bf8bdbe9-ce62-43a2-bbd7-adf1b3b1823a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532962006 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3532962006
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1402999049
Short name T229
Test name
Test status
Simulation time 621421252052 ps
CPU time 996.3 seconds
Started Aug 02 06:41:02 PM PDT 24
Finished Aug 02 06:57:39 PM PDT 24
Peak memory 223696 kb
Host smart-9a8a794e-a5d6-42c3-9e18-55a028e725d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402999049 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1402999049
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.634105699
Short name T436
Test name
Test status
Simulation time 119341406 ps
CPU time 1.17 seconds
Started Aug 02 06:41:03 PM PDT 24
Finished Aug 02 06:41:04 PM PDT 24
Peak memory 218628 kb
Host smart-a7401f6b-a30d-40b1-9160-41074a4b078c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634105699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.634105699
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.850728329
Short name T790
Test name
Test status
Simulation time 32895768 ps
CPU time 0.94 seconds
Started Aug 02 06:41:12 PM PDT 24
Finished Aug 02 06:41:13 PM PDT 24
Peak memory 206676 kb
Host smart-9071a724-4f35-4224-b2f0-0b8f49f979a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850728329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.850728329
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3480622549
Short name T989
Test name
Test status
Simulation time 20119863 ps
CPU time 0.89 seconds
Started Aug 02 06:41:12 PM PDT 24
Finished Aug 02 06:41:13 PM PDT 24
Peak memory 215420 kb
Host smart-31a40778-86d7-4a27-8e39-5ee28aef6c71
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480622549 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3480622549
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2466347160
Short name T290
Test name
Test status
Simulation time 107109783 ps
CPU time 1.16 seconds
Started Aug 02 06:41:11 PM PDT 24
Finished Aug 02 06:41:12 PM PDT 24
Peak memory 216784 kb
Host smart-c0d8ab42-0093-4001-92fc-c89ccfe012c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466347160 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2466347160
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.4158848226
Short name T119
Test name
Test status
Simulation time 51479135 ps
CPU time 0.81 seconds
Started Aug 02 06:41:10 PM PDT 24
Finished Aug 02 06:41:11 PM PDT 24
Peak memory 219348 kb
Host smart-60b6f467-9bdd-4f1f-9656-2e6de12fa7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158848226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.4158848226
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.685121303
Short name T344
Test name
Test status
Simulation time 47445462 ps
CPU time 1.97 seconds
Started Aug 02 06:41:04 PM PDT 24
Finished Aug 02 06:41:06 PM PDT 24
Peak memory 220132 kb
Host smart-600c937e-3821-42aa-8fee-8dd727058132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685121303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.685121303
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1764774592
Short name T864
Test name
Test status
Simulation time 21047795 ps
CPU time 1.13 seconds
Started Aug 02 06:41:04 PM PDT 24
Finished Aug 02 06:41:05 PM PDT 24
Peak memory 215548 kb
Host smart-24d4902d-04b4-45bd-817b-bad55914b9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764774592 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1764774592
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1216492334
Short name T635
Test name
Test status
Simulation time 157889029 ps
CPU time 0.88 seconds
Started Aug 02 06:41:03 PM PDT 24
Finished Aug 02 06:41:04 PM PDT 24
Peak memory 215124 kb
Host smart-ac10277b-1656-46ab-ac97-8d448892be6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216492334 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1216492334
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.612970549
Short name T990
Test name
Test status
Simulation time 254868307 ps
CPU time 3 seconds
Started Aug 02 06:41:00 PM PDT 24
Finished Aug 02 06:41:03 PM PDT 24
Peak memory 220124 kb
Host smart-5b07ddef-7438-4108-b8b3-da41221cf6f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612970549 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.612970549
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2155072228
Short name T235
Test name
Test status
Simulation time 80899779503 ps
CPU time 807.91 seconds
Started Aug 02 06:41:05 PM PDT 24
Finished Aug 02 06:54:33 PM PDT 24
Peak memory 223820 kb
Host smart-dff4b379-ba96-4ede-88d6-12c90554268d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155072228 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2155072228
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2168470716
Short name T462
Test name
Test status
Simulation time 67297891 ps
CPU time 1.21 seconds
Started Aug 02 06:39:56 PM PDT 24
Finished Aug 02 06:39:58 PM PDT 24
Peak memory 218508 kb
Host smart-6e965d9c-a004-48b8-a0c2-d7dea64bf170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168470716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2168470716
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3214282408
Short name T934
Test name
Test status
Simulation time 112496552 ps
CPU time 0.92 seconds
Started Aug 02 06:40:01 PM PDT 24
Finished Aug 02 06:40:02 PM PDT 24
Peak memory 215228 kb
Host smart-7f1ab59e-7d3c-414c-a4ca-7ec769be20a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214282408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3214282408
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.293206496
Short name T213
Test name
Test status
Simulation time 14620370 ps
CPU time 0.97 seconds
Started Aug 02 06:39:54 PM PDT 24
Finished Aug 02 06:39:56 PM PDT 24
Peak memory 215620 kb
Host smart-078fc41b-c06e-4453-ac1c-3c5a5b76fe25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293206496 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.293206496
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2144639713
Short name T216
Test name
Test status
Simulation time 90472063 ps
CPU time 1.17 seconds
Started Aug 02 06:39:53 PM PDT 24
Finished Aug 02 06:39:54 PM PDT 24
Peak memory 219700 kb
Host smart-fcd1b4c0-e8d8-499f-9c54-7df8bec98702
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144639713 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2144639713
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_genbits.3543679278
Short name T839
Test name
Test status
Simulation time 170811274 ps
CPU time 1.6 seconds
Started Aug 02 06:39:54 PM PDT 24
Finished Aug 02 06:39:56 PM PDT 24
Peak memory 218984 kb
Host smart-39d7dd64-b409-42e2-82fd-de770fbe57d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543679278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3543679278
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3859777735
Short name T85
Test name
Test status
Simulation time 27534394 ps
CPU time 0.89 seconds
Started Aug 02 06:39:55 PM PDT 24
Finished Aug 02 06:39:56 PM PDT 24
Peak memory 215956 kb
Host smart-a73f32aa-749a-48df-8ca7-f81bf6a80f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859777735 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3859777735
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2941309628
Short name T571
Test name
Test status
Simulation time 52903672 ps
CPU time 0.94 seconds
Started Aug 02 06:39:55 PM PDT 24
Finished Aug 02 06:39:56 PM PDT 24
Peak memory 207108 kb
Host smart-bfa18e63-9bc3-44e6-89d7-c3bf60751ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941309628 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2941309628
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.3630112218
Short name T908
Test name
Test status
Simulation time 20621580 ps
CPU time 1.03 seconds
Started Aug 02 06:39:55 PM PDT 24
Finished Aug 02 06:39:56 PM PDT 24
Peak memory 215364 kb
Host smart-2619c47a-7f2c-40d1-a5da-910d18c07411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630112218 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3630112218
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1219861783
Short name T486
Test name
Test status
Simulation time 592358566 ps
CPU time 3.73 seconds
Started Aug 02 06:39:53 PM PDT 24
Finished Aug 02 06:39:57 PM PDT 24
Peak memory 217016 kb
Host smart-c41def84-8128-4089-aeb1-8e20d43e3926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219861783 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1219861783
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1461574044
Short name T692
Test name
Test status
Simulation time 233458508822 ps
CPU time 1665.72 seconds
Started Aug 02 06:39:53 PM PDT 24
Finished Aug 02 07:07:39 PM PDT 24
Peak memory 228216 kb
Host smart-a07b64b5-4cd9-4778-98e4-14f5b6384cac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461574044 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1461574044
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2435735776
Short name T179
Test name
Test status
Simulation time 40709170 ps
CPU time 1.19 seconds
Started Aug 02 06:41:12 PM PDT 24
Finished Aug 02 06:41:13 PM PDT 24
Peak memory 218648 kb
Host smart-ec403712-51af-44cf-8777-24dc61075476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435735776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2435735776
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1201223154
Short name T723
Test name
Test status
Simulation time 11245803 ps
CPU time 0.85 seconds
Started Aug 02 06:41:12 PM PDT 24
Finished Aug 02 06:41:13 PM PDT 24
Peak memory 206776 kb
Host smart-53fcb2b6-6b44-4f61-80de-4a8067002871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201223154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1201223154
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.646788935
Short name T484
Test name
Test status
Simulation time 72401581 ps
CPU time 0.92 seconds
Started Aug 02 06:41:13 PM PDT 24
Finished Aug 02 06:41:14 PM PDT 24
Peak memory 216340 kb
Host smart-e559df00-2df3-4d7b-abb9-7e30babec321
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646788935 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.646788935
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2382230181
Short name T56
Test name
Test status
Simulation time 198371698 ps
CPU time 1.1 seconds
Started Aug 02 06:41:12 PM PDT 24
Finished Aug 02 06:41:13 PM PDT 24
Peak memory 218604 kb
Host smart-4352ae69-145b-42a3-8c23-8e531ae6abcb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382230181 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2382230181
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.4231352913
Short name T963
Test name
Test status
Simulation time 19324545 ps
CPU time 1.06 seconds
Started Aug 02 06:41:13 PM PDT 24
Finished Aug 02 06:41:14 PM PDT 24
Peak memory 218288 kb
Host smart-760b4822-7779-4a0c-8bb2-00adeab6b256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231352913 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.4231352913
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.436976577
Short name T760
Test name
Test status
Simulation time 98017492 ps
CPU time 1.46 seconds
Started Aug 02 06:41:10 PM PDT 24
Finished Aug 02 06:41:11 PM PDT 24
Peak memory 219048 kb
Host smart-5fa17fa6-6344-4a62-9a43-e8f7f734b274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436976577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.436976577
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.166295003
Short name T474
Test name
Test status
Simulation time 21803630 ps
CPU time 1.09 seconds
Started Aug 02 06:41:12 PM PDT 24
Finished Aug 02 06:41:13 PM PDT 24
Peak memory 215588 kb
Host smart-9539c926-2451-448a-a31c-f2480650de17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166295003 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.166295003
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1125173481
Short name T588
Test name
Test status
Simulation time 16232137 ps
CPU time 0.99 seconds
Started Aug 02 06:41:11 PM PDT 24
Finished Aug 02 06:41:12 PM PDT 24
Peak memory 215292 kb
Host smart-a66b7779-8b6c-40b6-a526-056127081d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125173481 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1125173481
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1821821184
Short name T652
Test name
Test status
Simulation time 324253225 ps
CPU time 3.59 seconds
Started Aug 02 06:41:11 PM PDT 24
Finished Aug 02 06:41:14 PM PDT 24
Peak memory 215376 kb
Host smart-341622d5-7fd3-496c-ac26-2caa8a468751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821821184 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1821821184
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1910281125
Short name T227
Test name
Test status
Simulation time 154564792149 ps
CPU time 1700.04 seconds
Started Aug 02 06:41:13 PM PDT 24
Finished Aug 02 07:09:33 PM PDT 24
Peak memory 224256 kb
Host smart-4dfc15b9-5c1f-418a-bf29-adb0af14d002
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910281125 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1910281125
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert_test.1386542689
Short name T617
Test name
Test status
Simulation time 17073013 ps
CPU time 0.94 seconds
Started Aug 02 06:41:14 PM PDT 24
Finished Aug 02 06:41:15 PM PDT 24
Peak memory 206864 kb
Host smart-740ff5e1-8cd3-4f49-b705-3fa2ae2a4936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386542689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1386542689
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.62094396
Short name T129
Test name
Test status
Simulation time 18239345 ps
CPU time 0.85 seconds
Started Aug 02 06:41:15 PM PDT 24
Finished Aug 02 06:41:16 PM PDT 24
Peak memory 216292 kb
Host smart-3700aad3-08fd-4825-ae9f-71780c094c75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62094396 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.62094396
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1546447696
Short name T890
Test name
Test status
Simulation time 94754174 ps
CPU time 1.27 seconds
Started Aug 02 06:41:15 PM PDT 24
Finished Aug 02 06:41:16 PM PDT 24
Peak memory 216856 kb
Host smart-12dd15ab-5153-4aa4-a958-026cba6bb7a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546447696 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1546447696
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.936443283
Short name T8
Test name
Test status
Simulation time 71987477 ps
CPU time 1.07 seconds
Started Aug 02 06:41:14 PM PDT 24
Finished Aug 02 06:41:16 PM PDT 24
Peak memory 224068 kb
Host smart-e2de0941-4b0e-4377-a2b9-11f9464d1852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936443283 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.936443283
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.157843225
Short name T914
Test name
Test status
Simulation time 81959904 ps
CPU time 2.6 seconds
Started Aug 02 06:41:15 PM PDT 24
Finished Aug 02 06:41:18 PM PDT 24
Peak memory 219484 kb
Host smart-6c3744c1-1f6e-4e3f-9385-77940f7a0f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157843225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.157843225
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3060139716
Short name T425
Test name
Test status
Simulation time 25947062 ps
CPU time 0.95 seconds
Started Aug 02 06:41:13 PM PDT 24
Finished Aug 02 06:41:14 PM PDT 24
Peak memory 215388 kb
Host smart-f252726b-ebc1-4af7-b13c-a739e3b1a68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060139716 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3060139716
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3517679876
Short name T847
Test name
Test status
Simulation time 103688959 ps
CPU time 1.03 seconds
Started Aug 02 06:41:12 PM PDT 24
Finished Aug 02 06:41:14 PM PDT 24
Peak memory 215348 kb
Host smart-f84532d7-61e4-4161-8f38-3a952920df7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517679876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3517679876
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2020411953
Short name T688
Test name
Test status
Simulation time 40814614 ps
CPU time 1.04 seconds
Started Aug 02 06:41:15 PM PDT 24
Finished Aug 02 06:41:16 PM PDT 24
Peak memory 215392 kb
Host smart-ca2e5304-cfd9-47c9-ad8e-473ca18f4d06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020411953 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2020411953
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1154683970
Short name T930
Test name
Test status
Simulation time 179708044878 ps
CPU time 2038.48 seconds
Started Aug 02 06:41:12 PM PDT 24
Finished Aug 02 07:15:11 PM PDT 24
Peak memory 225988 kb
Host smart-6a230e13-5fd0-4db3-848a-ee9bba169b87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154683970 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1154683970
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1998748016
Short name T219
Test name
Test status
Simulation time 42988331 ps
CPU time 1.28 seconds
Started Aug 02 06:41:15 PM PDT 24
Finished Aug 02 06:41:17 PM PDT 24
Peak memory 218692 kb
Host smart-5fe566b0-99cc-44b2-9137-3c696c9580ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998748016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1998748016
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1360536924
Short name T627
Test name
Test status
Simulation time 15102164 ps
CPU time 0.92 seconds
Started Aug 02 06:41:14 PM PDT 24
Finished Aug 02 06:41:15 PM PDT 24
Peak memory 214836 kb
Host smart-736ab079-49aa-4b94-8d69-02e907600dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360536924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1360536924
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1347670747
Short name T750
Test name
Test status
Simulation time 19590977 ps
CPU time 0.91 seconds
Started Aug 02 06:41:13 PM PDT 24
Finished Aug 02 06:41:14 PM PDT 24
Peak memory 216260 kb
Host smart-eda5d0d8-a11b-459d-b089-91178f725bb8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347670747 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1347670747
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.164694613
Short name T304
Test name
Test status
Simulation time 261757456 ps
CPU time 1.25 seconds
Started Aug 02 06:41:16 PM PDT 24
Finished Aug 02 06:41:17 PM PDT 24
Peak memory 218328 kb
Host smart-5d18a76e-09da-46b1-9bd3-765ce3619c56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164694613 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.164694613
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.883455334
Short name T196
Test name
Test status
Simulation time 17971510 ps
CPU time 1.2 seconds
Started Aug 02 06:41:15 PM PDT 24
Finished Aug 02 06:41:16 PM PDT 24
Peak memory 224068 kb
Host smart-6cc2e6cf-75c2-4320-9750-dd063e6e5887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883455334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.883455334
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3574942232
Short name T528
Test name
Test status
Simulation time 42050743 ps
CPU time 1.16 seconds
Started Aug 02 06:41:13 PM PDT 24
Finished Aug 02 06:41:14 PM PDT 24
Peak memory 218500 kb
Host smart-a2d9d743-0827-4eb4-a9ab-3018302084cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574942232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3574942232
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.4028603802
Short name T86
Test name
Test status
Simulation time 43550129 ps
CPU time 0.87 seconds
Started Aug 02 06:41:15 PM PDT 24
Finished Aug 02 06:41:16 PM PDT 24
Peak memory 215652 kb
Host smart-305220d2-b87e-4161-9ba7-191b3810c80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028603802 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.4028603802
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.54679094
Short name T704
Test name
Test status
Simulation time 43894688 ps
CPU time 0.93 seconds
Started Aug 02 06:41:12 PM PDT 24
Finished Aug 02 06:41:13 PM PDT 24
Peak memory 215324 kb
Host smart-90516ecf-196f-4bbd-81d3-2aed878f072e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54679094 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.54679094
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2068268743
Short name T351
Test name
Test status
Simulation time 152846981 ps
CPU time 3.49 seconds
Started Aug 02 06:41:12 PM PDT 24
Finished Aug 02 06:41:16 PM PDT 24
Peak memory 217312 kb
Host smart-dde15534-11ec-4bbc-b458-8706a1c47e70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068268743 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2068268743
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1139288785
Short name T980
Test name
Test status
Simulation time 21873491288 ps
CPU time 545.1 seconds
Started Aug 02 06:41:15 PM PDT 24
Finished Aug 02 06:50:20 PM PDT 24
Peak memory 216476 kb
Host smart-9f0b7805-a33d-4a1a-9841-9ae03512b848
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139288785 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1139288785
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert_test.3817781488
Short name T682
Test name
Test status
Simulation time 29976808 ps
CPU time 1 seconds
Started Aug 02 06:41:15 PM PDT 24
Finished Aug 02 06:41:17 PM PDT 24
Peak memory 206856 kb
Host smart-8fd7626a-9909-4dfc-9b48-cbaa3f54ca61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817781488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3817781488
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2443775349
Short name T821
Test name
Test status
Simulation time 27076185 ps
CPU time 0.85 seconds
Started Aug 02 06:41:17 PM PDT 24
Finished Aug 02 06:41:19 PM PDT 24
Peak memory 216184 kb
Host smart-aa459cf0-f356-4b58-b017-0b7d2abf50a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443775349 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2443775349
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.4011702141
Short name T732
Test name
Test status
Simulation time 32172904 ps
CPU time 1.16 seconds
Started Aug 02 06:41:18 PM PDT 24
Finished Aug 02 06:41:19 PM PDT 24
Peak memory 216828 kb
Host smart-4eaaa81d-674c-4145-b5a2-e8e384ef57d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011702141 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.4011702141
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1435321102
Short name T211
Test name
Test status
Simulation time 18869924 ps
CPU time 1.07 seconds
Started Aug 02 06:41:16 PM PDT 24
Finished Aug 02 06:41:18 PM PDT 24
Peak memory 218516 kb
Host smart-bb900e4c-1f09-456d-b07a-1b725e68f240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435321102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1435321102
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.125112488
Short name T500
Test name
Test status
Simulation time 64410654 ps
CPU time 1.42 seconds
Started Aug 02 06:41:13 PM PDT 24
Finished Aug 02 06:41:15 PM PDT 24
Peak memory 217368 kb
Host smart-5ff06329-b6ed-4cb0-a4f4-d27c0f2223b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125112488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.125112488
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1845326856
Short name T61
Test name
Test status
Simulation time 40677168 ps
CPU time 0.86 seconds
Started Aug 02 06:41:15 PM PDT 24
Finished Aug 02 06:41:16 PM PDT 24
Peak memory 215620 kb
Host smart-5af87305-64e7-4347-b1e9-6aef0f33c94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845326856 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1845326856
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1573316916
Short name T437
Test name
Test status
Simulation time 15718640 ps
CPU time 1.01 seconds
Started Aug 02 06:41:13 PM PDT 24
Finished Aug 02 06:41:14 PM PDT 24
Peak memory 215316 kb
Host smart-52ff5b18-20b6-43b0-ba87-2c70d9e776b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573316916 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1573316916
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2951668002
Short name T712
Test name
Test status
Simulation time 1030377545 ps
CPU time 5.14 seconds
Started Aug 02 06:41:18 PM PDT 24
Finished Aug 02 06:41:23 PM PDT 24
Peak memory 217140 kb
Host smart-96fe9824-8b12-498d-abb7-0270051ebc74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951668002 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2951668002
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3710143642
Short name T594
Test name
Test status
Simulation time 200143004973 ps
CPU time 819.07 seconds
Started Aug 02 06:41:13 PM PDT 24
Finished Aug 02 06:54:53 PM PDT 24
Peak memory 223712 kb
Host smart-79035fd7-23ce-454b-9723-4a5305305635
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710143642 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3710143642
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.4244160825
Short name T960
Test name
Test status
Simulation time 51833508 ps
CPU time 1.33 seconds
Started Aug 02 06:41:25 PM PDT 24
Finished Aug 02 06:41:27 PM PDT 24
Peak memory 220404 kb
Host smart-f2112419-1195-4e0c-83a1-5a9e6e141386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244160825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.4244160825
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3471781646
Short name T357
Test name
Test status
Simulation time 15549170 ps
CPU time 0.94 seconds
Started Aug 02 06:41:26 PM PDT 24
Finished Aug 02 06:41:27 PM PDT 24
Peak memory 214864 kb
Host smart-eebc7588-ec0d-42f7-952c-445807c7d9f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471781646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3471781646
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.86567918
Short name T949
Test name
Test status
Simulation time 12138897 ps
CPU time 0.92 seconds
Started Aug 02 06:41:20 PM PDT 24
Finished Aug 02 06:41:21 PM PDT 24
Peak memory 216504 kb
Host smart-c1f6a21c-85d7-49fa-8029-36a51af5ff93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86567918 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.86567918
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2084649497
Short name T606
Test name
Test status
Simulation time 18581036 ps
CPU time 1.01 seconds
Started Aug 02 06:41:21 PM PDT 24
Finished Aug 02 06:41:22 PM PDT 24
Peak memory 216824 kb
Host smart-fa1ed29d-8d29-4adb-9c7e-8744cc13ecf6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084649497 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2084649497
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1732736750
Short name T615
Test name
Test status
Simulation time 20714592 ps
CPU time 1 seconds
Started Aug 02 06:41:18 PM PDT 24
Finished Aug 02 06:41:19 PM PDT 24
Peak memory 218348 kb
Host smart-f6bf2ea0-c3b7-4812-9bc6-12ac8a8f00de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732736750 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1732736750
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3397711106
Short name T33
Test name
Test status
Simulation time 74484746 ps
CPU time 1.35 seconds
Started Aug 02 06:41:17 PM PDT 24
Finished Aug 02 06:41:18 PM PDT 24
Peak memory 217408 kb
Host smart-c15392b1-b076-4300-b1af-0952656be07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397711106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3397711106
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1765537485
Short name T41
Test name
Test status
Simulation time 22339673 ps
CPU time 1.27 seconds
Started Aug 02 06:41:13 PM PDT 24
Finished Aug 02 06:41:14 PM PDT 24
Peak memory 224076 kb
Host smart-126ff27f-4cd9-48e9-bea6-c75f11adb56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765537485 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1765537485
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3572270421
Short name T370
Test name
Test status
Simulation time 17132779 ps
CPU time 0.97 seconds
Started Aug 02 06:41:19 PM PDT 24
Finished Aug 02 06:41:20 PM PDT 24
Peak memory 207080 kb
Host smart-44c9c48b-2146-419e-a838-2f73ba27a3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572270421 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3572270421
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2810789344
Short name T735
Test name
Test status
Simulation time 269918052 ps
CPU time 2.63 seconds
Started Aug 02 06:41:16 PM PDT 24
Finished Aug 02 06:41:19 PM PDT 24
Peak memory 215412 kb
Host smart-6d526635-cf60-4456-b163-eb93e31b8a97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810789344 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2810789344
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_alert.197069749
Short name T443
Test name
Test status
Simulation time 25899429 ps
CPU time 1.24 seconds
Started Aug 02 06:41:26 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 219832 kb
Host smart-3db02ca4-e30a-4790-8509-7229b039c169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197069749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.197069749
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3244908443
Short name T845
Test name
Test status
Simulation time 30470353 ps
CPU time 0.85 seconds
Started Aug 02 06:41:26 PM PDT 24
Finished Aug 02 06:41:27 PM PDT 24
Peak memory 206760 kb
Host smart-ef3d2476-ba0b-4774-8350-938e597175fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244908443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3244908443
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.969280459
Short name T16
Test name
Test status
Simulation time 235239008 ps
CPU time 1.15 seconds
Started Aug 02 06:41:27 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 216920 kb
Host smart-348a9b67-1f7b-4339-8e0e-4609dcb8a6df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969280459 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.969280459
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.714531950
Short name T140
Test name
Test status
Simulation time 26150513 ps
CPU time 1.17 seconds
Started Aug 02 06:41:22 PM PDT 24
Finished Aug 02 06:41:23 PM PDT 24
Peak memory 220440 kb
Host smart-b59155d6-6484-4e52-ad7f-9d46e90e2de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714531950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.714531950
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1375283028
Short name T940
Test name
Test status
Simulation time 79418047 ps
CPU time 1.17 seconds
Started Aug 02 06:41:20 PM PDT 24
Finished Aug 02 06:41:22 PM PDT 24
Peak memory 217348 kb
Host smart-fcf9bbd9-9665-4f8d-a875-d536c96c22ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375283028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1375283028
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2983945953
Short name T574
Test name
Test status
Simulation time 38215667 ps
CPU time 0.95 seconds
Started Aug 02 06:41:27 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 215352 kb
Host smart-3a7232f1-6fa1-4904-868a-f5d9f48ce7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983945953 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2983945953
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2859691519
Short name T432
Test name
Test status
Simulation time 19203073 ps
CPU time 1 seconds
Started Aug 02 06:41:19 PM PDT 24
Finished Aug 02 06:41:20 PM PDT 24
Peak memory 215304 kb
Host smart-6291fb8b-f841-4f94-b9aa-234923f43e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859691519 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2859691519
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.241537002
Short name T405
Test name
Test status
Simulation time 63797207 ps
CPU time 1.21 seconds
Started Aug 02 06:41:27 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 215320 kb
Host smart-9288642c-68ed-4109-a655-1129c95cd5ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241537002 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.241537002
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2218105653
Short name T739
Test name
Test status
Simulation time 19670396098 ps
CPU time 445.75 seconds
Started Aug 02 06:41:20 PM PDT 24
Finished Aug 02 06:48:46 PM PDT 24
Peak memory 217900 kb
Host smart-9f8f8a63-2018-459b-909a-a789c23d6827
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218105653 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2218105653
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert_test.1447466766
Short name T368
Test name
Test status
Simulation time 19247134 ps
CPU time 1.03 seconds
Started Aug 02 06:41:25 PM PDT 24
Finished Aug 02 06:41:26 PM PDT 24
Peak memory 215144 kb
Host smart-0f7b0ee1-cb55-4ab1-9640-7f7dc623d42e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447466766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1447466766
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.574446791
Short name T513
Test name
Test status
Simulation time 33348027 ps
CPU time 0.83 seconds
Started Aug 02 06:41:18 PM PDT 24
Finished Aug 02 06:41:19 PM PDT 24
Peak memory 215412 kb
Host smart-9c34a06d-4d82-4c75-82da-660ddbc6cc5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574446791 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.574446791
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1100432712
Short name T176
Test name
Test status
Simulation time 58852236 ps
CPU time 1.27 seconds
Started Aug 02 06:41:23 PM PDT 24
Finished Aug 02 06:41:24 PM PDT 24
Peak memory 217096 kb
Host smart-2b76e3af-ce57-4e9d-adeb-565f152fa275
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100432712 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1100432712
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_genbits.1831796136
Short name T794
Test name
Test status
Simulation time 118534297 ps
CPU time 1.13 seconds
Started Aug 02 06:41:19 PM PDT 24
Finished Aug 02 06:41:20 PM PDT 24
Peak memory 217452 kb
Host smart-65493a31-2ca2-40d1-a624-f38800341ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831796136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1831796136
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2322857377
Short name T941
Test name
Test status
Simulation time 27861679 ps
CPU time 0.95 seconds
Started Aug 02 06:41:27 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 215396 kb
Host smart-e611c77a-fe44-4359-af2b-62acaa1f6f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322857377 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2322857377
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2142870984
Short name T799
Test name
Test status
Simulation time 17724638 ps
CPU time 1.04 seconds
Started Aug 02 06:41:20 PM PDT 24
Finished Aug 02 06:41:21 PM PDT 24
Peak memory 215264 kb
Host smart-32d31f83-0ff5-4659-b8b3-35a36dac6939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142870984 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2142870984
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2552214561
Short name T444
Test name
Test status
Simulation time 349309392 ps
CPU time 2.74 seconds
Started Aug 02 06:41:22 PM PDT 24
Finished Aug 02 06:41:24 PM PDT 24
Peak memory 215376 kb
Host smart-89a0c467-6523-471d-9f29-21c1c04afb53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552214561 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2552214561
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1067870213
Short name T142
Test name
Test status
Simulation time 74595188427 ps
CPU time 1693.9 seconds
Started Aug 02 06:41:25 PM PDT 24
Finished Aug 02 07:09:39 PM PDT 24
Peak memory 225812 kb
Host smart-0b3cbf02-daf0-4fe9-8b33-a37877f64613
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067870213 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1067870213
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.253106963
Short name T706
Test name
Test status
Simulation time 64967860 ps
CPU time 1.22 seconds
Started Aug 02 06:41:23 PM PDT 24
Finished Aug 02 06:41:24 PM PDT 24
Peak memory 218580 kb
Host smart-f23ee672-8ee0-4ecc-a900-f869b4245d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253106963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.253106963
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2571804319
Short name T546
Test name
Test status
Simulation time 12609769 ps
CPU time 0.83 seconds
Started Aug 02 06:41:20 PM PDT 24
Finished Aug 02 06:41:21 PM PDT 24
Peak memory 206956 kb
Host smart-18b09e97-bccd-45fc-aa9c-e3e7331cbff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571804319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2571804319
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3154608551
Short name T450
Test name
Test status
Simulation time 11467928 ps
CPU time 0.91 seconds
Started Aug 02 06:41:27 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 216288 kb
Host smart-28094926-b2f9-42fa-8186-a202694afbec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154608551 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3154608551
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3021980973
Short name T701
Test name
Test status
Simulation time 58653595 ps
CPU time 1.19 seconds
Started Aug 02 06:41:27 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 218476 kb
Host smart-913ce6e3-09c0-43da-989f-12f665d50977
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021980973 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3021980973
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2540860201
Short name T684
Test name
Test status
Simulation time 50746854 ps
CPU time 1 seconds
Started Aug 02 06:41:20 PM PDT 24
Finished Aug 02 06:41:21 PM PDT 24
Peak memory 218872 kb
Host smart-50382123-b719-40c0-88a5-1163fd238060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540860201 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2540860201
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3520841833
Short name T595
Test name
Test status
Simulation time 55841333 ps
CPU time 1.53 seconds
Started Aug 02 06:41:26 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 218672 kb
Host smart-f2465fca-baad-4b39-82ee-3f146684818e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520841833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3520841833
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.188317142
Short name T417
Test name
Test status
Simulation time 47343702 ps
CPU time 0.91 seconds
Started Aug 02 06:41:28 PM PDT 24
Finished Aug 02 06:41:29 PM PDT 24
Peak memory 215384 kb
Host smart-bd8723f1-4a42-4f5c-99b1-89d905282da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188317142 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.188317142
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1181780745
Short name T581
Test name
Test status
Simulation time 31253063 ps
CPU time 0.96 seconds
Started Aug 02 06:41:27 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 215264 kb
Host smart-c94cb880-7b67-43eb-8479-262b46a36567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181780745 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1181780745
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.266300619
Short name T647
Test name
Test status
Simulation time 429358229 ps
CPU time 8.31 seconds
Started Aug 02 06:41:21 PM PDT 24
Finished Aug 02 06:41:29 PM PDT 24
Peak memory 215292 kb
Host smart-9ef218d3-9720-4192-94f6-ce6ab4230d18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266300619 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.266300619
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1065999579
Short name T973
Test name
Test status
Simulation time 132457198613 ps
CPU time 1634.44 seconds
Started Aug 02 06:41:25 PM PDT 24
Finished Aug 02 07:08:40 PM PDT 24
Peak memory 224036 kb
Host smart-b8dcd70e-1fd2-40a7-ba1b-4d5c14d136f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065999579 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1065999579
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.363881794
Short name T829
Test name
Test status
Simulation time 130880289 ps
CPU time 1.27 seconds
Started Aug 02 06:41:27 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 218512 kb
Host smart-a97e080c-881a-402a-90da-06f37f4013a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363881794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.363881794
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3053482535
Short name T778
Test name
Test status
Simulation time 34414956 ps
CPU time 0.98 seconds
Started Aug 02 06:41:19 PM PDT 24
Finished Aug 02 06:41:20 PM PDT 24
Peak memory 214872 kb
Host smart-069793a0-dab3-46f0-9a44-f6313357a207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053482535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3053482535
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3238345426
Short name T116
Test name
Test status
Simulation time 26936553 ps
CPU time 0.9 seconds
Started Aug 02 06:41:27 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 216300 kb
Host smart-f9b7a4ed-e5ae-4e1b-8842-803a4e344d30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238345426 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3238345426
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1118466771
Short name T898
Test name
Test status
Simulation time 24822863 ps
CPU time 1.02 seconds
Started Aug 02 06:41:23 PM PDT 24
Finished Aug 02 06:41:24 PM PDT 24
Peak memory 216908 kb
Host smart-2b565718-b38e-4908-99ff-52c30a6c5d83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118466771 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1118466771
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3033124650
Short name T4
Test name
Test status
Simulation time 27732061 ps
CPU time 0.82 seconds
Started Aug 02 06:41:19 PM PDT 24
Finished Aug 02 06:41:20 PM PDT 24
Peak memory 218292 kb
Host smart-a4314462-9dd9-4985-879b-afa6f792a131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033124650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3033124650
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.591651450
Short name T609
Test name
Test status
Simulation time 67489298 ps
CPU time 2.29 seconds
Started Aug 02 06:41:18 PM PDT 24
Finished Aug 02 06:41:21 PM PDT 24
Peak memory 219900 kb
Host smart-9cace9e6-e0e6-4805-8469-041522a23f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591651450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.591651450
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2374798163
Short name T656
Test name
Test status
Simulation time 26810218 ps
CPU time 1.11 seconds
Started Aug 02 06:41:27 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 224104 kb
Host smart-3680a706-4a4a-4acb-83e9-b305bed9e61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374798163 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2374798163
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1678143308
Short name T643
Test name
Test status
Simulation time 44656474 ps
CPU time 0.89 seconds
Started Aug 02 06:41:27 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 215348 kb
Host smart-659e06e6-142d-4cea-a5aa-34836c61359f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678143308 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1678143308
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3565919551
Short name T110
Test name
Test status
Simulation time 168173385 ps
CPU time 2.29 seconds
Started Aug 02 06:41:26 PM PDT 24
Finished Aug 02 06:41:29 PM PDT 24
Peak memory 215404 kb
Host smart-cb32ec9d-99a9-4421-bcf6-0f20576ccc87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565919551 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3565919551
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1730906241
Short name T912
Test name
Test status
Simulation time 143057120224 ps
CPU time 2225.91 seconds
Started Aug 02 06:41:25 PM PDT 24
Finished Aug 02 07:18:31 PM PDT 24
Peak memory 228264 kb
Host smart-aaf4837b-03f3-476a-bfa5-d93883294f30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730906241 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1730906241
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2042884477
Short name T310
Test name
Test status
Simulation time 83048021 ps
CPU time 1.25 seconds
Started Aug 02 06:41:26 PM PDT 24
Finished Aug 02 06:41:27 PM PDT 24
Peak memory 219644 kb
Host smart-a7844f23-3634-40a6-b8ad-7ce7034383ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042884477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2042884477
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3613443492
Short name T544
Test name
Test status
Simulation time 78589358 ps
CPU time 1.39 seconds
Started Aug 02 06:41:29 PM PDT 24
Finished Aug 02 06:41:31 PM PDT 24
Peak memory 214892 kb
Host smart-bbbad444-4805-488c-8617-4a49b0057da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613443492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3613443492
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2312476598
Short name T128
Test name
Test status
Simulation time 12692307 ps
CPU time 0.92 seconds
Started Aug 02 06:41:35 PM PDT 24
Finished Aug 02 06:41:36 PM PDT 24
Peak memory 216540 kb
Host smart-ac3c1aab-421a-40c7-a857-831281a982d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312476598 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2312476598
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_err.1213624676
Short name T895
Test name
Test status
Simulation time 19923277 ps
CPU time 1.04 seconds
Started Aug 02 06:41:19 PM PDT 24
Finished Aug 02 06:41:20 PM PDT 24
Peak memory 218528 kb
Host smart-62c3d6aa-22a7-420a-9ea8-215ad396b147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213624676 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1213624676
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2048303475
Short name T314
Test name
Test status
Simulation time 76941496 ps
CPU time 1.19 seconds
Started Aug 02 06:41:21 PM PDT 24
Finished Aug 02 06:41:22 PM PDT 24
Peak memory 218808 kb
Host smart-af49614d-84d7-483c-8175-efbcb4f73b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048303475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2048303475
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3686183517
Short name T459
Test name
Test status
Simulation time 78983794 ps
CPU time 0.83 seconds
Started Aug 02 06:41:21 PM PDT 24
Finished Aug 02 06:41:22 PM PDT 24
Peak memory 215204 kb
Host smart-80b4655d-fa08-49a2-88d4-2349060151bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686183517 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3686183517
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2608523045
Short name T99
Test name
Test status
Simulation time 19111818 ps
CPU time 1.06 seconds
Started Aug 02 06:41:23 PM PDT 24
Finished Aug 02 06:41:25 PM PDT 24
Peak memory 215308 kb
Host smart-ede8d14b-d13d-4950-846c-b17a0da38277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608523045 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2608523045
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.4042431467
Short name T984
Test name
Test status
Simulation time 244060940 ps
CPU time 1.41 seconds
Started Aug 02 06:41:21 PM PDT 24
Finished Aug 02 06:41:22 PM PDT 24
Peak memory 215292 kb
Host smart-a478b678-725c-4320-b556-a91539f4ef71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042431467 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.4042431467
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1110113971
Short name T225
Test name
Test status
Simulation time 43738630068 ps
CPU time 439.42 seconds
Started Aug 02 06:41:28 PM PDT 24
Finished Aug 02 06:48:47 PM PDT 24
Peak memory 218092 kb
Host smart-38be46a6-f807-4955-9de3-56e16e65de7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110113971 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1110113971
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.295540132
Short name T180
Test name
Test status
Simulation time 31635428 ps
CPU time 1.27 seconds
Started Aug 02 06:40:01 PM PDT 24
Finished Aug 02 06:40:02 PM PDT 24
Peak memory 220276 kb
Host smart-527b13e0-dfa0-482e-b71e-99e5959d5a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295540132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.295540132
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1993642773
Short name T511
Test name
Test status
Simulation time 64191726 ps
CPU time 1.02 seconds
Started Aug 02 06:40:08 PM PDT 24
Finished Aug 02 06:40:09 PM PDT 24
Peak memory 215032 kb
Host smart-2c4ab567-3da5-4b9a-9d30-a56487db6258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993642773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1993642773
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3709957229
Short name T396
Test name
Test status
Simulation time 19284640 ps
CPU time 0.9 seconds
Started Aug 02 06:40:05 PM PDT 24
Finished Aug 02 06:40:06 PM PDT 24
Peak memory 215948 kb
Host smart-eb42449d-611a-4878-96f0-db4f3108bb7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709957229 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3709957229
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.107653754
Short name T132
Test name
Test status
Simulation time 215523187 ps
CPU time 1.27 seconds
Started Aug 02 06:40:09 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 216920 kb
Host smart-1c28dc08-1238-4f8d-a55b-3e0a963cd0bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107653754 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.107653754
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3991192362
Short name T59
Test name
Test status
Simulation time 18603013 ps
CPU time 1.11 seconds
Started Aug 02 06:40:02 PM PDT 24
Finished Aug 02 06:40:04 PM PDT 24
Peak memory 218664 kb
Host smart-60698db4-a59b-4590-82d3-756294413585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991192362 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3991192362
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3419181461
Short name T361
Test name
Test status
Simulation time 146886254 ps
CPU time 3.06 seconds
Started Aug 02 06:40:03 PM PDT 24
Finished Aug 02 06:40:06 PM PDT 24
Peak memory 218700 kb
Host smart-2dc2bf25-aaa1-4a8e-a162-a1b287be6464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419181461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3419181461
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3413517681
Short name T89
Test name
Test status
Simulation time 33230796 ps
CPU time 0.89 seconds
Started Aug 02 06:40:04 PM PDT 24
Finished Aug 02 06:40:06 PM PDT 24
Peak memory 215700 kb
Host smart-c8f8ba5f-60fe-49e6-8efe-4863dc30638e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413517681 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3413517681
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3687328380
Short name T971
Test name
Test status
Simulation time 56623972 ps
CPU time 0.99 seconds
Started Aug 02 06:40:04 PM PDT 24
Finished Aug 02 06:40:05 PM PDT 24
Peak memory 207088 kb
Host smart-e7a896a1-7280-47c2-8f75-48c2e79d26f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687328380 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3687328380
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.69244438
Short name T832
Test name
Test status
Simulation time 24279470 ps
CPU time 0.92 seconds
Started Aug 02 06:40:09 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 215288 kb
Host smart-bba39a1d-5dd6-4243-b4d9-569e62cc3dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69244438 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.69244438
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1566021971
Short name T393
Test name
Test status
Simulation time 124306464 ps
CPU time 2.93 seconds
Started Aug 02 06:40:02 PM PDT 24
Finished Aug 02 06:40:05 PM PDT 24
Peak memory 217188 kb
Host smart-e64e81a2-75c0-4797-a0fa-5cc98d2f5b70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566021971 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1566021971
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1115469750
Short name T917
Test name
Test status
Simulation time 160229907338 ps
CPU time 1045.82 seconds
Started Aug 02 06:40:03 PM PDT 24
Finished Aug 02 06:57:29 PM PDT 24
Peak memory 223152 kb
Host smart-36bdacb4-c291-4570-9497-d57af5e2cec1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115469750 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1115469750
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.735390927
Short name T751
Test name
Test status
Simulation time 79776013 ps
CPU time 1.18 seconds
Started Aug 02 06:41:30 PM PDT 24
Finished Aug 02 06:41:32 PM PDT 24
Peak memory 220188 kb
Host smart-eea97691-cf2e-4aa4-bf19-7ffe1fc95057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735390927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.735390927
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.4089947171
Short name T937
Test name
Test status
Simulation time 28503395 ps
CPU time 0.93 seconds
Started Aug 02 06:41:29 PM PDT 24
Finished Aug 02 06:41:30 PM PDT 24
Peak memory 219456 kb
Host smart-090f64d9-5523-4c27-b019-3253533d2d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089947171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.4089947171
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2762301492
Short name T771
Test name
Test status
Simulation time 49880470 ps
CPU time 1.54 seconds
Started Aug 02 06:41:29 PM PDT 24
Finished Aug 02 06:41:30 PM PDT 24
Peak memory 218468 kb
Host smart-9a0b0ce2-18d4-4928-b3b9-f7e9324c6df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762301492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2762301492
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.903176014
Short name T148
Test name
Test status
Simulation time 222446089 ps
CPU time 1.18 seconds
Started Aug 02 06:41:29 PM PDT 24
Finished Aug 02 06:41:30 PM PDT 24
Peak memory 218392 kb
Host smart-1236c03e-3684-4af9-93e3-2eab84b38e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903176014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.903176014
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.1756384611
Short name T838
Test name
Test status
Simulation time 36061109 ps
CPU time 0.89 seconds
Started Aug 02 06:41:32 PM PDT 24
Finished Aug 02 06:41:33 PM PDT 24
Peak memory 219364 kb
Host smart-5ea01c87-0407-4fd1-a547-b09183a5e3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756384611 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1756384611
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3163134882
Short name T851
Test name
Test status
Simulation time 94287875 ps
CPU time 1.4 seconds
Started Aug 02 06:41:28 PM PDT 24
Finished Aug 02 06:41:30 PM PDT 24
Peak memory 218860 kb
Host smart-acc6eeb6-d10f-466c-836e-d1a14142f701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163134882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3163134882
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.3456112474
Short name T668
Test name
Test status
Simulation time 31071002 ps
CPU time 1.23 seconds
Started Aug 02 06:41:29 PM PDT 24
Finished Aug 02 06:41:31 PM PDT 24
Peak memory 215680 kb
Host smart-cfe71af8-06f6-48e3-bcb7-65b7c2e5feb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456112474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.3456112474
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.2281488297
Short name T123
Test name
Test status
Simulation time 52676679 ps
CPU time 0.91 seconds
Started Aug 02 06:41:29 PM PDT 24
Finished Aug 02 06:41:30 PM PDT 24
Peak memory 223888 kb
Host smart-cb9a986f-bdc0-40a2-960f-374d12f64c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281488297 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2281488297
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1004883477
Short name T380
Test name
Test status
Simulation time 167693807 ps
CPU time 1.54 seconds
Started Aug 02 06:41:30 PM PDT 24
Finished Aug 02 06:41:31 PM PDT 24
Peak memory 218720 kb
Host smart-b5b8aadf-01e6-4254-afe1-1c5a999b6a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004883477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1004883477
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2865948828
Short name T457
Test name
Test status
Simulation time 63199644 ps
CPU time 1.09 seconds
Started Aug 02 06:41:28 PM PDT 24
Finished Aug 02 06:41:29 PM PDT 24
Peak memory 219756 kb
Host smart-92f881e9-daae-4ef0-908d-67ecb25422d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865948828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2865948828
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2677185778
Short name T15
Test name
Test status
Simulation time 37587009 ps
CPU time 1 seconds
Started Aug 02 06:41:31 PM PDT 24
Finished Aug 02 06:41:33 PM PDT 24
Peak memory 229444 kb
Host smart-1a2104a5-f0d6-4fb6-8d5b-384a064e3029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677185778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2677185778
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2084335021
Short name T343
Test name
Test status
Simulation time 35747469 ps
CPU time 1.52 seconds
Started Aug 02 06:41:28 PM PDT 24
Finished Aug 02 06:41:30 PM PDT 24
Peak memory 219628 kb
Host smart-f687330d-a7ef-45e9-8cca-2fddf3e510f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084335021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2084335021
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.130145161
Short name T662
Test name
Test status
Simulation time 28205056 ps
CPU time 1.24 seconds
Started Aug 02 06:41:31 PM PDT 24
Finished Aug 02 06:41:32 PM PDT 24
Peak memory 219864 kb
Host smart-4837d1d6-7cf5-4920-9410-2ab94bdade64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130145161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.130145161
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.604955792
Short name T849
Test name
Test status
Simulation time 32041407 ps
CPU time 0.98 seconds
Started Aug 02 06:41:29 PM PDT 24
Finished Aug 02 06:41:30 PM PDT 24
Peak memory 223876 kb
Host smart-e3e89f98-0ccb-4e84-a607-34f9d89c5b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604955792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.604955792
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3090723761
Short name T867
Test name
Test status
Simulation time 45991075 ps
CPU time 1.47 seconds
Started Aug 02 06:41:28 PM PDT 24
Finished Aug 02 06:41:29 PM PDT 24
Peak memory 218384 kb
Host smart-31070f96-680d-4bbc-be65-4ab745dec1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090723761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3090723761
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.3783495234
Short name T922
Test name
Test status
Simulation time 167522603 ps
CPU time 1.22 seconds
Started Aug 02 06:41:31 PM PDT 24
Finished Aug 02 06:41:32 PM PDT 24
Peak memory 220384 kb
Host smart-5df706bf-c891-4aff-8104-5cfd58204680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783495234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.3783495234
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.3405026409
Short name T168
Test name
Test status
Simulation time 28665347 ps
CPU time 1.32 seconds
Started Aug 02 06:41:30 PM PDT 24
Finished Aug 02 06:41:31 PM PDT 24
Peak memory 229628 kb
Host smart-3e9b4f09-402b-4822-a171-65e238d53299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405026409 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3405026409
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1625424106
Short name T861
Test name
Test status
Simulation time 27900326 ps
CPU time 1.27 seconds
Started Aug 02 06:41:30 PM PDT 24
Finished Aug 02 06:41:31 PM PDT 24
Peak memory 218704 kb
Host smart-3562e879-48da-4a8d-ba07-d638de0c180a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625424106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1625424106
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2758352652
Short name T100
Test name
Test status
Simulation time 114430272 ps
CPU time 1.18 seconds
Started Aug 02 06:41:29 PM PDT 24
Finished Aug 02 06:41:31 PM PDT 24
Peak memory 220768 kb
Host smart-716f33e6-9a81-42bc-b35b-4915869baf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758352652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2758352652
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.561151259
Short name T659
Test name
Test status
Simulation time 23242696 ps
CPU time 0.94 seconds
Started Aug 02 06:41:28 PM PDT 24
Finished Aug 02 06:41:29 PM PDT 24
Peak memory 218724 kb
Host smart-6e157f73-8b17-49f6-a00b-02c0405f17f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561151259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.561151259
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3486848067
Short name T843
Test name
Test status
Simulation time 46951829 ps
CPU time 1.44 seconds
Started Aug 02 06:41:35 PM PDT 24
Finished Aug 02 06:41:37 PM PDT 24
Peak memory 218560 kb
Host smart-c1c28479-434c-4267-9d35-7270d1b2c994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486848067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3486848067
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.1562316230
Short name T206
Test name
Test status
Simulation time 85277842 ps
CPU time 1.14 seconds
Started Aug 02 06:41:27 PM PDT 24
Finished Aug 02 06:41:28 PM PDT 24
Peak memory 219724 kb
Host smart-ca13fb4e-3e93-41d9-998a-9424753e0b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562316230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.1562316230
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.218120203
Short name T646
Test name
Test status
Simulation time 46561998 ps
CPU time 0.89 seconds
Started Aug 02 06:41:31 PM PDT 24
Finished Aug 02 06:41:32 PM PDT 24
Peak memory 218532 kb
Host smart-600b2261-0604-4e87-91dd-3265e5c3a12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218120203 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.218120203
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3179276261
Short name T840
Test name
Test status
Simulation time 35267342 ps
CPU time 1.34 seconds
Started Aug 02 06:41:34 PM PDT 24
Finished Aug 02 06:41:35 PM PDT 24
Peak memory 217532 kb
Host smart-3bfe6c36-821d-4e13-88b7-71a9a09bb0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179276261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3179276261
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.3512256236
Short name T650
Test name
Test status
Simulation time 27524797 ps
CPU time 0.86 seconds
Started Aug 02 06:41:31 PM PDT 24
Finished Aug 02 06:41:32 PM PDT 24
Peak memory 218372 kb
Host smart-0c283d59-7a0a-4d33-9d8c-1684db059dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512256236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3512256236
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1017066980
Short name T975
Test name
Test status
Simulation time 89235780 ps
CPU time 1.13 seconds
Started Aug 02 06:41:31 PM PDT 24
Finished Aug 02 06:41:32 PM PDT 24
Peak memory 217328 kb
Host smart-6df4221f-cbaa-4823-9468-936256fc138d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017066980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1017066980
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.203559968
Short name T784
Test name
Test status
Simulation time 19574326 ps
CPU time 1.08 seconds
Started Aug 02 06:41:29 PM PDT 24
Finished Aug 02 06:41:30 PM PDT 24
Peak memory 218524 kb
Host smart-238cbbff-49b5-4ddd-ab7f-304da1cf4e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203559968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.203559968
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3468795084
Short name T90
Test name
Test status
Simulation time 23803872 ps
CPU time 1.16 seconds
Started Aug 02 06:41:30 PM PDT 24
Finished Aug 02 06:41:31 PM PDT 24
Peak memory 215396 kb
Host smart-0099b982-7ad9-41ea-994d-8af796db07e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468795084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3468795084
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1725530236
Short name T844
Test name
Test status
Simulation time 159856626 ps
CPU time 1.42 seconds
Started Aug 02 06:40:02 PM PDT 24
Finished Aug 02 06:40:03 PM PDT 24
Peak memory 219260 kb
Host smart-7f46b1cb-91c6-4e80-a0a4-1acb36b94012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725530236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1725530236
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3011747963
Short name T490
Test name
Test status
Simulation time 65940294 ps
CPU time 0.94 seconds
Started Aug 02 06:40:20 PM PDT 24
Finished Aug 02 06:40:21 PM PDT 24
Peak memory 206756 kb
Host smart-a3defd75-f747-40d0-8e68-0277c11b7e04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011747963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3011747963
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.91645707
Short name T876
Test name
Test status
Simulation time 32665283 ps
CPU time 0.86 seconds
Started Aug 02 06:40:03 PM PDT 24
Finished Aug 02 06:40:04 PM PDT 24
Peak memory 215396 kb
Host smart-6340e6db-3959-460c-9601-b61435c3be2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91645707 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.91645707
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2858298087
Short name T165
Test name
Test status
Simulation time 58268673 ps
CPU time 1.14 seconds
Started Aug 02 06:40:00 PM PDT 24
Finished Aug 02 06:40:02 PM PDT 24
Peak memory 217020 kb
Host smart-cd6d33f0-de13-467c-992e-ca31a9652061
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858298087 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2858298087
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3973009723
Short name T117
Test name
Test status
Simulation time 24407747 ps
CPU time 0.97 seconds
Started Aug 02 06:40:02 PM PDT 24
Finished Aug 02 06:40:03 PM PDT 24
Peak memory 218692 kb
Host smart-14fd3f57-4468-485a-983b-3938217d0fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973009723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3973009723
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.867158074
Short name T420
Test name
Test status
Simulation time 104635500 ps
CPU time 1.1 seconds
Started Aug 02 06:40:09 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 217284 kb
Host smart-ecbd55bc-e922-4cb9-8c7e-18b3f0fff3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867158074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.867158074
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1778568296
Short name T369
Test name
Test status
Simulation time 37269696 ps
CPU time 0.89 seconds
Started Aug 02 06:40:00 PM PDT 24
Finished Aug 02 06:40:01 PM PDT 24
Peak memory 215528 kb
Host smart-5002b0ef-01dc-4c93-b632-0a81434d9d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778568296 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1778568296
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.606366275
Short name T79
Test name
Test status
Simulation time 24979415 ps
CPU time 1 seconds
Started Aug 02 06:40:03 PM PDT 24
Finished Aug 02 06:40:04 PM PDT 24
Peak memory 207084 kb
Host smart-608a9949-551d-405b-a818-6bea746f3447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606366275 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.606366275
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2631842181
Short name T438
Test name
Test status
Simulation time 83164442 ps
CPU time 0.89 seconds
Started Aug 02 06:40:05 PM PDT 24
Finished Aug 02 06:40:06 PM PDT 24
Peak memory 215264 kb
Host smart-bca69236-6488-4c7e-b320-baeade7ba843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631842181 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2631842181
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.976607121
Short name T737
Test name
Test status
Simulation time 510209238 ps
CPU time 5.54 seconds
Started Aug 02 06:40:03 PM PDT 24
Finished Aug 02 06:40:09 PM PDT 24
Peak memory 215352 kb
Host smart-e84b13d7-26d2-43dc-95e7-53f081252f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976607121 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.976607121
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1118142448
Short name T20
Test name
Test status
Simulation time 21405669486 ps
CPU time 263.8 seconds
Started Aug 02 06:40:01 PM PDT 24
Finished Aug 02 06:44:25 PM PDT 24
Peak memory 218200 kb
Host smart-932e0058-6cc2-4f79-84ba-fdf2514f3d5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118142448 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1118142448
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2239374712
Short name T127
Test name
Test status
Simulation time 55413998 ps
CPU time 1.08 seconds
Started Aug 02 06:41:29 PM PDT 24
Finished Aug 02 06:41:30 PM PDT 24
Peak memory 219636 kb
Host smart-679d54df-43b3-453b-8f25-464dd310de07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239374712 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2239374712
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3157456895
Short name T697
Test name
Test status
Simulation time 73176992 ps
CPU time 1.17 seconds
Started Aug 02 06:41:32 PM PDT 24
Finished Aug 02 06:41:33 PM PDT 24
Peak memory 218588 kb
Host smart-f33d756f-2764-460a-9721-505930ebc483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157456895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3157456895
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.75161830
Short name T158
Test name
Test status
Simulation time 41616433 ps
CPU time 1.2 seconds
Started Aug 02 06:41:35 PM PDT 24
Finished Aug 02 06:41:37 PM PDT 24
Peak memory 219640 kb
Host smart-1d4214d8-e641-4d4c-9cde-9dd196bd12bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75161830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.75161830
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1020426865
Short name T58
Test name
Test status
Simulation time 44655086 ps
CPU time 1.15 seconds
Started Aug 02 06:41:38 PM PDT 24
Finished Aug 02 06:41:39 PM PDT 24
Peak memory 219668 kb
Host smart-94cc87d5-841e-4b94-ba1b-b0e0f725780e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020426865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1020426865
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/62.edn_alert.1006641430
Short name T956
Test name
Test status
Simulation time 126132451 ps
CPU time 1.1 seconds
Started Aug 02 06:41:34 PM PDT 24
Finished Aug 02 06:41:35 PM PDT 24
Peak memory 220904 kb
Host smart-cacd1e1c-19dc-4ead-87ed-42036b237558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006641430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1006641430
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1328981665
Short name T43
Test name
Test status
Simulation time 32491187 ps
CPU time 0.98 seconds
Started Aug 02 06:41:37 PM PDT 24
Finished Aug 02 06:41:38 PM PDT 24
Peak memory 223840 kb
Host smart-6c924e16-16b8-4249-8e52-8c0b3e997c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328981665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1328981665
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2168899225
Short name T77
Test name
Test status
Simulation time 35058431 ps
CPU time 1.5 seconds
Started Aug 02 06:41:38 PM PDT 24
Finished Aug 02 06:41:39 PM PDT 24
Peak memory 218744 kb
Host smart-30055745-498a-4d93-8342-3ede1b789b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168899225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2168899225
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2992405718
Short name T591
Test name
Test status
Simulation time 78687107 ps
CPU time 1.1 seconds
Started Aug 02 06:41:38 PM PDT 24
Finished Aug 02 06:41:39 PM PDT 24
Peak memory 217756 kb
Host smart-8510e9cb-6adc-4e2d-8f9d-da9c61df1e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992405718 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2992405718
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.2729982251
Short name T578
Test name
Test status
Simulation time 20508419 ps
CPU time 1.22 seconds
Started Aug 02 06:41:41 PM PDT 24
Finished Aug 02 06:41:43 PM PDT 24
Peak memory 229668 kb
Host smart-ca7f4c8d-ff4d-450c-98db-6de0b915f876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729982251 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2729982251
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.369945640
Short name T757
Test name
Test status
Simulation time 63824315 ps
CPU time 1.32 seconds
Started Aug 02 06:41:36 PM PDT 24
Finished Aug 02 06:41:38 PM PDT 24
Peak memory 218424 kb
Host smart-512fb45e-3d76-446d-9d99-8d0b9f9052f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369945640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.369945640
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2071394819
Short name T35
Test name
Test status
Simulation time 83161481 ps
CPU time 1.19 seconds
Started Aug 02 06:41:40 PM PDT 24
Finished Aug 02 06:41:41 PM PDT 24
Peak memory 218692 kb
Host smart-5224e881-247f-40e3-a3b4-a59e53390eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071394819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2071394819
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.929544717
Short name T374
Test name
Test status
Simulation time 31046777 ps
CPU time 0.94 seconds
Started Aug 02 06:41:36 PM PDT 24
Finished Aug 02 06:41:38 PM PDT 24
Peak memory 218336 kb
Host smart-774f99ec-6957-4f2c-a096-21604ba92327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929544717 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.929544717
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2465106799
Short name T620
Test name
Test status
Simulation time 60576610 ps
CPU time 1.18 seconds
Started Aug 02 06:41:35 PM PDT 24
Finished Aug 02 06:41:36 PM PDT 24
Peak memory 219868 kb
Host smart-eefa33f6-3c57-4e26-a5a8-c7899515b0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465106799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2465106799
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3323517250
Short name T811
Test name
Test status
Simulation time 325163548 ps
CPU time 1.06 seconds
Started Aug 02 06:41:36 PM PDT 24
Finished Aug 02 06:41:38 PM PDT 24
Peak memory 218284 kb
Host smart-163c8dd7-685c-4cc8-b3f1-8b2e55f48d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323517250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3323517250
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.4117869525
Short name T159
Test name
Test status
Simulation time 22026443 ps
CPU time 1.12 seconds
Started Aug 02 06:41:38 PM PDT 24
Finished Aug 02 06:41:39 PM PDT 24
Peak memory 219700 kb
Host smart-7354abd5-7288-4051-9858-35ed2eb9372a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117869525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4117869525
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1464243422
Short name T507
Test name
Test status
Simulation time 109113957 ps
CPU time 1.11 seconds
Started Aug 02 06:41:36 PM PDT 24
Finished Aug 02 06:41:37 PM PDT 24
Peak memory 217320 kb
Host smart-ba32a7ff-c7af-4c67-9149-c77520655f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464243422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1464243422
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.2742039895
Short name T313
Test name
Test status
Simulation time 31136765 ps
CPU time 1.33 seconds
Started Aug 02 06:41:41 PM PDT 24
Finished Aug 02 06:41:42 PM PDT 24
Peak memory 215708 kb
Host smart-049b30df-d708-499b-8f4c-9c129ab46ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742039895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.2742039895
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.3988222399
Short name T753
Test name
Test status
Simulation time 34404617 ps
CPU time 1.09 seconds
Started Aug 02 06:41:39 PM PDT 24
Finished Aug 02 06:41:41 PM PDT 24
Peak memory 220748 kb
Host smart-caf8186c-7ce8-4728-b3e3-1b47227564fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988222399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3988222399
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.96498363
Short name T965
Test name
Test status
Simulation time 52273257 ps
CPU time 1.13 seconds
Started Aug 02 06:41:38 PM PDT 24
Finished Aug 02 06:41:39 PM PDT 24
Peak memory 218888 kb
Host smart-632b18e5-982c-4f64-af7b-668f187c0985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96498363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.96498363
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.346134826
Short name T950
Test name
Test status
Simulation time 21739820 ps
CPU time 1.14 seconds
Started Aug 02 06:41:41 PM PDT 24
Finished Aug 02 06:41:42 PM PDT 24
Peak memory 219808 kb
Host smart-93587098-2a00-40d4-b48b-c51de1a09ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346134826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.346134826
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.2800071851
Short name T174
Test name
Test status
Simulation time 60525867 ps
CPU time 0.98 seconds
Started Aug 02 06:41:38 PM PDT 24
Finished Aug 02 06:41:39 PM PDT 24
Peak memory 219460 kb
Host smart-c370daf2-0e27-4f5d-89ad-68eb6bfa189f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800071851 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2800071851
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2329610465
Short name T289
Test name
Test status
Simulation time 44662121 ps
CPU time 1.18 seconds
Started Aug 02 06:41:38 PM PDT 24
Finished Aug 02 06:41:39 PM PDT 24
Peak memory 218600 kb
Host smart-1ddb0c47-e890-467d-9129-2288506835ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329610465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2329610465
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.3917662992
Short name T780
Test name
Test status
Simulation time 74861374 ps
CPU time 1.11 seconds
Started Aug 02 06:41:37 PM PDT 24
Finished Aug 02 06:41:38 PM PDT 24
Peak memory 218944 kb
Host smart-7cede296-7349-4cd1-8ab6-7ee9c7be42ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917662992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.3917662992
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.3773995572
Short name T938
Test name
Test status
Simulation time 22937257 ps
CPU time 1.25 seconds
Started Aug 02 06:41:39 PM PDT 24
Finished Aug 02 06:41:40 PM PDT 24
Peak memory 224056 kb
Host smart-3eed2701-b536-462a-88c4-6a64464d5cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773995572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3773995572
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1200771273
Short name T762
Test name
Test status
Simulation time 46995199 ps
CPU time 1.44 seconds
Started Aug 02 06:41:40 PM PDT 24
Finished Aug 02 06:41:42 PM PDT 24
Peak memory 218468 kb
Host smart-6966a8c0-1fe0-4705-bb7d-3d4bf7b8fa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200771273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1200771273
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.696274278
Short name T601
Test name
Test status
Simulation time 23336877 ps
CPU time 1.17 seconds
Started Aug 02 06:41:36 PM PDT 24
Finished Aug 02 06:41:37 PM PDT 24
Peak memory 219880 kb
Host smart-ed9ba7e9-f116-4e3e-a540-3399cb2dc33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696274278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.696274278
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3350377202
Short name T103
Test name
Test status
Simulation time 49133846 ps
CPU time 1.08 seconds
Started Aug 02 06:41:40 PM PDT 24
Finished Aug 02 06:41:41 PM PDT 24
Peak memory 220596 kb
Host smart-48fd63e6-1b35-444e-923b-2fac6036ddbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350377202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3350377202
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.4220729496
Short name T830
Test name
Test status
Simulation time 58222334 ps
CPU time 1.28 seconds
Started Aug 02 06:41:39 PM PDT 24
Finished Aug 02 06:41:40 PM PDT 24
Peak memory 218528 kb
Host smart-98755d55-60ca-4704-bb80-03d0cc5a2ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220729496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4220729496
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2917294519
Short name T202
Test name
Test status
Simulation time 71906102 ps
CPU time 1.17 seconds
Started Aug 02 06:40:03 PM PDT 24
Finished Aug 02 06:40:04 PM PDT 24
Peak memory 219612 kb
Host smart-c4c8c534-8a33-4488-8ad6-c6379483efb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917294519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2917294519
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1856629332
Short name T467
Test name
Test status
Simulation time 22846342 ps
CPU time 0.83 seconds
Started Aug 02 06:40:04 PM PDT 24
Finished Aug 02 06:40:05 PM PDT 24
Peak memory 206524 kb
Host smart-21082554-4bfc-4a17-b385-dbf760f5ba80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856629332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1856629332
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1616737289
Short name T198
Test name
Test status
Simulation time 10889551 ps
CPU time 0.89 seconds
Started Aug 02 06:40:02 PM PDT 24
Finished Aug 02 06:40:03 PM PDT 24
Peak memory 216328 kb
Host smart-7dd48dc6-2cae-4ce2-aec8-0660f2884c59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616737289 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1616737289
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3154797241
Short name T774
Test name
Test status
Simulation time 39062387 ps
CPU time 1.37 seconds
Started Aug 02 06:40:02 PM PDT 24
Finished Aug 02 06:40:03 PM PDT 24
Peak memory 217048 kb
Host smart-7fdebd18-d481-4bb5-96cc-29643a9743b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154797241 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3154797241
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.268898797
Short name T39
Test name
Test status
Simulation time 24840062 ps
CPU time 1.28 seconds
Started Aug 02 06:40:04 PM PDT 24
Finished Aug 02 06:40:05 PM PDT 24
Peak memory 229700 kb
Host smart-4338424a-8688-4a83-930e-52f4453d2f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268898797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.268898797
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2671007152
Short name T329
Test name
Test status
Simulation time 30242280 ps
CPU time 1.37 seconds
Started Aug 02 06:40:00 PM PDT 24
Finished Aug 02 06:40:02 PM PDT 24
Peak memory 220016 kb
Host smart-9a832797-84eb-4035-b9b5-a150ed084386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671007152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2671007152
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2867688545
Short name T928
Test name
Test status
Simulation time 47541255 ps
CPU time 0.89 seconds
Started Aug 02 06:40:01 PM PDT 24
Finished Aug 02 06:40:02 PM PDT 24
Peak memory 215612 kb
Host smart-edc99c46-30f7-4277-80ec-7c1ec097875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867688545 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2867688545
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3047412230
Short name T78
Test name
Test status
Simulation time 48200293 ps
CPU time 0.93 seconds
Started Aug 02 06:40:07 PM PDT 24
Finished Aug 02 06:40:08 PM PDT 24
Peak memory 207152 kb
Host smart-62222263-2a3a-418e-aaef-fdaf69928411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047412230 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3047412230
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2098370983
Short name T962
Test name
Test status
Simulation time 19368135 ps
CPU time 0.98 seconds
Started Aug 02 06:40:03 PM PDT 24
Finished Aug 02 06:40:04 PM PDT 24
Peak memory 215384 kb
Host smart-5e121039-a15a-468e-8003-19c6c6aae8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098370983 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2098370983
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3738117200
Short name T463
Test name
Test status
Simulation time 1699740375 ps
CPU time 5.12 seconds
Started Aug 02 06:40:01 PM PDT 24
Finished Aug 02 06:40:06 PM PDT 24
Peak memory 215344 kb
Host smart-7230dd4d-eb15-461a-b8e1-e9f723b743cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738117200 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3738117200
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3546485444
Short name T800
Test name
Test status
Simulation time 106450796106 ps
CPU time 1253.95 seconds
Started Aug 02 06:40:01 PM PDT 24
Finished Aug 02 07:00:55 PM PDT 24
Peak memory 224560 kb
Host smart-150d75f8-26ba-4e18-9d0d-fc59813f3ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546485444 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3546485444
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.2566146348
Short name T805
Test name
Test status
Simulation time 179987867 ps
CPU time 1.27 seconds
Started Aug 02 06:41:40 PM PDT 24
Finished Aug 02 06:41:42 PM PDT 24
Peak memory 218732 kb
Host smart-55314080-f907-47a4-af08-ad1f2d341625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566146348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2566146348
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.4268381710
Short name T715
Test name
Test status
Simulation time 23451428 ps
CPU time 1.14 seconds
Started Aug 02 06:41:36 PM PDT 24
Finished Aug 02 06:41:37 PM PDT 24
Peak memory 218636 kb
Host smart-b2c525fa-ccd3-4442-90be-eb2920659226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268381710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.4268381710
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.4246207502
Short name T335
Test name
Test status
Simulation time 47442364 ps
CPU time 1.36 seconds
Started Aug 02 06:41:38 PM PDT 24
Finished Aug 02 06:41:40 PM PDT 24
Peak memory 217516 kb
Host smart-85126fcf-a50b-46df-9045-8ec29d6a371a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246207502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.4246207502
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.659371955
Short name T286
Test name
Test status
Simulation time 25499090 ps
CPU time 1.23 seconds
Started Aug 02 06:41:36 PM PDT 24
Finished Aug 02 06:41:38 PM PDT 24
Peak memory 218552 kb
Host smart-b889cfd9-f295-4c38-ad59-cdcc3d13c2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659371955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.659371955
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.488058485
Short name T653
Test name
Test status
Simulation time 108949697 ps
CPU time 1.05 seconds
Started Aug 02 06:41:37 PM PDT 24
Finished Aug 02 06:41:38 PM PDT 24
Peak memory 220596 kb
Host smart-9967420e-a33e-4eb0-9f0c-186e0b755dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488058485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.488058485
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.4063060351
Short name T334
Test name
Test status
Simulation time 124204815 ps
CPU time 1.06 seconds
Started Aug 02 06:41:39 PM PDT 24
Finished Aug 02 06:41:40 PM PDT 24
Peak memory 217196 kb
Host smart-e0f62564-cf68-4407-a4d2-4dbacf98ac26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063060351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.4063060351
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.100315312
Short name T71
Test name
Test status
Simulation time 27653057 ps
CPU time 1.26 seconds
Started Aug 02 06:41:38 PM PDT 24
Finished Aug 02 06:41:40 PM PDT 24
Peak memory 221028 kb
Host smart-f5420274-a40c-4f3a-9743-d2c986006ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100315312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.100315312
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.421270806
Short name T707
Test name
Test status
Simulation time 27048653 ps
CPU time 1.38 seconds
Started Aug 02 06:41:40 PM PDT 24
Finished Aug 02 06:41:41 PM PDT 24
Peak memory 229616 kb
Host smart-18244a9a-cfee-4d96-b6e5-c06e06c2c28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421270806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.421270806
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2226937989
Short name T384
Test name
Test status
Simulation time 47729458 ps
CPU time 1.52 seconds
Started Aug 02 06:41:37 PM PDT 24
Finished Aug 02 06:41:39 PM PDT 24
Peak memory 218772 kb
Host smart-50197b2e-5079-4b53-a19d-c5edd94d75e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226937989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2226937989
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3305806442
Short name T187
Test name
Test status
Simulation time 23770786 ps
CPU time 1.17 seconds
Started Aug 02 06:41:39 PM PDT 24
Finished Aug 02 06:41:41 PM PDT 24
Peak memory 219832 kb
Host smart-08e5af60-1ed0-4902-994d-e0678731fdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305806442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3305806442
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3245000911
Short name T60
Test name
Test status
Simulation time 40665913 ps
CPU time 0.86 seconds
Started Aug 02 06:41:38 PM PDT 24
Finished Aug 02 06:41:39 PM PDT 24
Peak memory 218172 kb
Host smart-f076ca76-50f7-477a-8ff5-a3f783fb5e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245000911 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3245000911
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3830862072
Short name T626
Test name
Test status
Simulation time 259767171 ps
CPU time 4.01 seconds
Started Aug 02 06:41:37 PM PDT 24
Finished Aug 02 06:41:41 PM PDT 24
Peak memory 220080 kb
Host smart-e3edb2d8-138a-4d16-b1f6-31a4e640d810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830862072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3830862072
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.793827574
Short name T966
Test name
Test status
Simulation time 24837075 ps
CPU time 1.2 seconds
Started Aug 02 06:41:36 PM PDT 24
Finished Aug 02 06:41:38 PM PDT 24
Peak memory 218436 kb
Host smart-9eb44d5f-2272-48d1-a8db-5bd6aea3e645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793827574 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.793827574
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2292148187
Short name T134
Test name
Test status
Simulation time 20333104 ps
CPU time 1.26 seconds
Started Aug 02 06:41:41 PM PDT 24
Finished Aug 02 06:41:43 PM PDT 24
Peak memory 224216 kb
Host smart-8253a52c-1231-4a3f-bbed-563f979bc622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292148187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2292148187
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.928834015
Short name T305
Test name
Test status
Simulation time 63853287 ps
CPU time 1.59 seconds
Started Aug 02 06:41:40 PM PDT 24
Finished Aug 02 06:41:42 PM PDT 24
Peak memory 218584 kb
Host smart-9751d745-6684-4bc4-8298-35d29f47443c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928834015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.928834015
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.2669179366
Short name T104
Test name
Test status
Simulation time 44910003 ps
CPU time 1.26 seconds
Started Aug 02 06:41:41 PM PDT 24
Finished Aug 02 06:41:42 PM PDT 24
Peak memory 218520 kb
Host smart-63806e31-efb4-4cd6-9851-4ecdaafe5950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669179366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.2669179366
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.1325690966
Short name T186
Test name
Test status
Simulation time 28558269 ps
CPU time 0.89 seconds
Started Aug 02 06:41:40 PM PDT 24
Finished Aug 02 06:41:41 PM PDT 24
Peak memory 218552 kb
Host smart-4d47b50a-e10c-49c7-9f7d-97a31a5d8332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325690966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1325690966
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2414071749
Short name T277
Test name
Test status
Simulation time 113971278 ps
CPU time 2.55 seconds
Started Aug 02 06:41:38 PM PDT 24
Finished Aug 02 06:41:41 PM PDT 24
Peak memory 220040 kb
Host smart-8463ec36-d3d4-4fec-80bf-c76aa8cbb074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414071749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2414071749
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.3041823870
Short name T603
Test name
Test status
Simulation time 38694666 ps
CPU time 1.12 seconds
Started Aug 02 06:41:36 PM PDT 24
Finished Aug 02 06:41:38 PM PDT 24
Peak memory 218116 kb
Host smart-bde28e65-769c-43c8-8366-07c0d0d6cc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041823870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3041823870
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.4270299557
Short name T823
Test name
Test status
Simulation time 24284468 ps
CPU time 1.29 seconds
Started Aug 02 06:41:38 PM PDT 24
Finished Aug 02 06:41:40 PM PDT 24
Peak memory 224224 kb
Host smart-f3bfc181-243e-40bb-a459-55d7eda774e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270299557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.4270299557
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1752994545
Short name T874
Test name
Test status
Simulation time 135562435 ps
CPU time 2.96 seconds
Started Aug 02 06:41:41 PM PDT 24
Finished Aug 02 06:41:44 PM PDT 24
Peak memory 220288 kb
Host smart-eec6e46b-214f-42b4-8896-0f681cd036d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752994545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1752994545
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.332162992
Short name T696
Test name
Test status
Simulation time 40709454 ps
CPU time 1.06 seconds
Started Aug 02 06:41:43 PM PDT 24
Finished Aug 02 06:41:45 PM PDT 24
Peak memory 218628 kb
Host smart-c5b37fb3-7c47-4499-8805-7c13041bc3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332162992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.332162992
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.1752333243
Short name T542
Test name
Test status
Simulation time 23999132 ps
CPU time 1.17 seconds
Started Aug 02 06:41:40 PM PDT 24
Finished Aug 02 06:41:41 PM PDT 24
Peak memory 220640 kb
Host smart-84042108-3448-429f-96d8-7900d77ca933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752333243 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1752333243
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2341435704
Short name T730
Test name
Test status
Simulation time 50870513 ps
CPU time 1.87 seconds
Started Aug 02 06:41:41 PM PDT 24
Finished Aug 02 06:41:43 PM PDT 24
Peak memory 218696 kb
Host smart-f16506be-fabf-4549-9195-63c35eb68dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341435704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2341435704
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.332235725
Short name T162
Test name
Test status
Simulation time 27541744 ps
CPU time 1.28 seconds
Started Aug 02 06:41:40 PM PDT 24
Finished Aug 02 06:41:41 PM PDT 24
Peak memory 218692 kb
Host smart-0220b2e9-b9f2-4f41-b9f1-7a38b3583244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332235725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.332235725
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.3142552018
Short name T452
Test name
Test status
Simulation time 41389844 ps
CPU time 0.82 seconds
Started Aug 02 06:41:41 PM PDT 24
Finished Aug 02 06:41:42 PM PDT 24
Peak memory 218244 kb
Host smart-691af576-e19a-42d8-a9d3-def2551245c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142552018 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3142552018
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2745845411
Short name T685
Test name
Test status
Simulation time 35223555 ps
CPU time 1.64 seconds
Started Aug 02 06:41:38 PM PDT 24
Finished Aug 02 06:41:40 PM PDT 24
Peak memory 217028 kb
Host smart-3d5553cf-c70b-432d-b451-1a54ce57ace1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745845411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2745845411
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.4240207086
Short name T63
Test name
Test status
Simulation time 29116878 ps
CPU time 1.25 seconds
Started Aug 02 06:41:38 PM PDT 24
Finished Aug 02 06:41:39 PM PDT 24
Peak memory 220208 kb
Host smart-81fc9909-3f99-4c17-82fe-a7add3e0ef1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240207086 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.4240207086
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_genbits.1714495298
Short name T695
Test name
Test status
Simulation time 43772210 ps
CPU time 1.52 seconds
Started Aug 02 06:41:43 PM PDT 24
Finished Aug 02 06:41:44 PM PDT 24
Peak memory 218340 kb
Host smart-3c26eeef-38e9-4edf-8ea7-7b9dc752b16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714495298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1714495298
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.427091834
Short name T809
Test name
Test status
Simulation time 78172124 ps
CPU time 1.11 seconds
Started Aug 02 06:40:15 PM PDT 24
Finished Aug 02 06:40:16 PM PDT 24
Peak memory 219924 kb
Host smart-8c279fcb-829d-4746-a003-e7a1a42c1584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427091834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.427091834
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3489001292
Short name T55
Test name
Test status
Simulation time 47630197 ps
CPU time 0.87 seconds
Started Aug 02 06:40:09 PM PDT 24
Finished Aug 02 06:40:10 PM PDT 24
Peak memory 206604 kb
Host smart-7c745c3e-9eec-4b8e-bb20-cc9853640356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489001292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3489001292
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3620757142
Short name T768
Test name
Test status
Simulation time 85732687 ps
CPU time 0.81 seconds
Started Aug 02 06:40:09 PM PDT 24
Finished Aug 02 06:40:10 PM PDT 24
Peak memory 216248 kb
Host smart-aa9ff75f-5251-4775-b479-08c3e5d72111
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620757142 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3620757142
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1018725261
Short name T969
Test name
Test status
Simulation time 100593492 ps
CPU time 1.19 seconds
Started Aug 02 06:40:10 PM PDT 24
Finished Aug 02 06:40:12 PM PDT 24
Peak memory 217004 kb
Host smart-2c7e0123-d44b-4de6-8b28-9a2e59d7a1e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018725261 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1018725261
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.233722800
Short name T194
Test name
Test status
Simulation time 19188926 ps
CPU time 1.1 seconds
Started Aug 02 06:40:13 PM PDT 24
Finished Aug 02 06:40:14 PM PDT 24
Peak memory 218340 kb
Host smart-718dd1ea-fe0b-4d8e-8f27-493f2940328a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233722800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.233722800
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3978886421
Short name T740
Test name
Test status
Simulation time 50964891 ps
CPU time 0.96 seconds
Started Aug 02 06:40:08 PM PDT 24
Finished Aug 02 06:40:09 PM PDT 24
Peak memory 215316 kb
Host smart-aa25f722-13c3-4971-9c3c-38610e60ee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978886421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3978886421
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_regwen.1755538283
Short name T309
Test name
Test status
Simulation time 59048486 ps
CPU time 0.86 seconds
Started Aug 02 06:40:04 PM PDT 24
Finished Aug 02 06:40:05 PM PDT 24
Peak memory 207108 kb
Host smart-b1a2f2a3-a8e6-4f23-b4a3-58efde7005e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755538283 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1755538283
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.4144700416
Short name T414
Test name
Test status
Simulation time 52075721 ps
CPU time 0.98 seconds
Started Aug 02 06:40:02 PM PDT 24
Finished Aug 02 06:40:03 PM PDT 24
Peak memory 215292 kb
Host smart-beac5701-0d23-4d52-b75a-6bcb0bf175e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144700416 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.4144700416
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3070667734
Short name T982
Test name
Test status
Simulation time 153703747 ps
CPU time 3.52 seconds
Started Aug 02 06:40:13 PM PDT 24
Finished Aug 02 06:40:17 PM PDT 24
Peak memory 217164 kb
Host smart-e5cb0942-e35a-4a28-b613-6f0a108ebac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070667734 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3070667734
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3668315786
Short name T907
Test name
Test status
Simulation time 45743551748 ps
CPU time 273.43 seconds
Started Aug 02 06:40:15 PM PDT 24
Finished Aug 02 06:44:49 PM PDT 24
Peak memory 218484 kb
Host smart-74c8dad6-12f9-4184-ad0b-3745c058904e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668315786 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3668315786
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.3425820503
Short name T312
Test name
Test status
Simulation time 78794259 ps
CPU time 1.16 seconds
Started Aug 02 06:41:43 PM PDT 24
Finished Aug 02 06:41:44 PM PDT 24
Peak memory 219476 kb
Host smart-59d88612-16cb-42e6-9f19-64f9bf8e8cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425820503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.3425820503
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.3101770284
Short name T131
Test name
Test status
Simulation time 31502375 ps
CPU time 1.18 seconds
Started Aug 02 06:41:41 PM PDT 24
Finished Aug 02 06:41:43 PM PDT 24
Peak memory 224000 kb
Host smart-6f01bfc7-db9f-4680-9020-1a9d70d1d0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101770284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3101770284
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/81.edn_alert.1900050578
Short name T379
Test name
Test status
Simulation time 32323483 ps
CPU time 1.21 seconds
Started Aug 02 06:41:47 PM PDT 24
Finished Aug 02 06:41:48 PM PDT 24
Peak memory 219564 kb
Host smart-d50a6187-26d0-4024-a8db-09f31e5b5441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900050578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1900050578
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.3887688028
Short name T877
Test name
Test status
Simulation time 23760248 ps
CPU time 1.08 seconds
Started Aug 02 06:41:46 PM PDT 24
Finished Aug 02 06:41:48 PM PDT 24
Peak memory 224008 kb
Host smart-d06b7e3c-c313-4831-bdab-1b8597e1f6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887688028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3887688028
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2015913422
Short name T592
Test name
Test status
Simulation time 110314119 ps
CPU time 2.91 seconds
Started Aug 02 06:41:42 PM PDT 24
Finished Aug 02 06:41:45 PM PDT 24
Peak memory 220224 kb
Host smart-6beedb62-271d-4e65-9142-9d8e0c2d40ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015913422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2015913422
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.440498411
Short name T752
Test name
Test status
Simulation time 74394156 ps
CPU time 1.1 seconds
Started Aug 02 06:41:47 PM PDT 24
Finished Aug 02 06:41:48 PM PDT 24
Peak memory 220544 kb
Host smart-40d5e36e-efb8-4806-9eaa-017d3fa9eff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440498411 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.440498411
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3516022267
Short name T733
Test name
Test status
Simulation time 24194875 ps
CPU time 0.93 seconds
Started Aug 02 06:41:46 PM PDT 24
Finished Aug 02 06:41:47 PM PDT 24
Peak memory 218804 kb
Host smart-8398b1e4-77f9-4e06-a324-24a53a454333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516022267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3516022267
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.247119199
Short name T503
Test name
Test status
Simulation time 37932287 ps
CPU time 1.03 seconds
Started Aug 02 06:41:47 PM PDT 24
Finished Aug 02 06:41:48 PM PDT 24
Peak memory 217380 kb
Host smart-a42449a7-e3f4-4f01-8412-000e71e6f136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247119199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.247119199
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.3576414941
Short name T200
Test name
Test status
Simulation time 25740346 ps
CPU time 1.2 seconds
Started Aug 02 06:41:48 PM PDT 24
Finished Aug 02 06:41:50 PM PDT 24
Peak memory 218556 kb
Host smart-b5327010-aa82-4649-9987-0ab493661227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576414941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.3576414941
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.362263977
Short name T6
Test name
Test status
Simulation time 31165636 ps
CPU time 0.85 seconds
Started Aug 02 06:41:48 PM PDT 24
Finished Aug 02 06:41:49 PM PDT 24
Peak memory 219036 kb
Host smart-b7e5bb7e-42f9-4ce7-9c15-335923ef6ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362263977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.362263977
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3389843907
Short name T749
Test name
Test status
Simulation time 39157897 ps
CPU time 1.45 seconds
Started Aug 02 06:41:47 PM PDT 24
Finished Aug 02 06:41:48 PM PDT 24
Peak memory 218460 kb
Host smart-8220b333-ab3e-4f88-a5d4-f15f20d20efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389843907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3389843907
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.3769278957
Short name T470
Test name
Test status
Simulation time 34514276 ps
CPU time 1.06 seconds
Started Aug 02 06:41:49 PM PDT 24
Finished Aug 02 06:41:50 PM PDT 24
Peak memory 218332 kb
Host smart-96b38187-1e57-4e67-8688-86e6b78edf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769278957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.3769278957
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3631958897
Short name T141
Test name
Test status
Simulation time 32456468 ps
CPU time 0.9 seconds
Started Aug 02 06:41:48 PM PDT 24
Finished Aug 02 06:41:49 PM PDT 24
Peak memory 219516 kb
Host smart-f6e55d8e-a4b9-4a43-904b-73e3ed16a897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631958897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3631958897
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.4016297903
Short name T820
Test name
Test status
Simulation time 32689219 ps
CPU time 1.59 seconds
Started Aug 02 06:41:49 PM PDT 24
Finished Aug 02 06:41:51 PM PDT 24
Peak memory 218384 kb
Host smart-69b3196f-062c-4c61-9801-126bcb516f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016297903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.4016297903
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.1597918174
Short name T483
Test name
Test status
Simulation time 50997906 ps
CPU time 1.22 seconds
Started Aug 02 06:41:48 PM PDT 24
Finished Aug 02 06:41:50 PM PDT 24
Peak memory 219716 kb
Host smart-fcaf9142-c805-43ae-bdfd-38f2fb1d0146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597918174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.1597918174
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.4053657933
Short name T422
Test name
Test status
Simulation time 21205593 ps
CPU time 0.98 seconds
Started Aug 02 06:41:47 PM PDT 24
Finished Aug 02 06:41:48 PM PDT 24
Peak memory 219488 kb
Host smart-086b6be6-a20f-4a34-81c5-f17dc08e4afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053657933 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.4053657933
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1270083477
Short name T585
Test name
Test status
Simulation time 141643158 ps
CPU time 1.08 seconds
Started Aug 02 06:41:50 PM PDT 24
Finished Aug 02 06:41:52 PM PDT 24
Peak memory 217256 kb
Host smart-ac000bb3-4aee-430f-853e-7b6e91647dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270083477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1270083477
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2196270146
Short name T157
Test name
Test status
Simulation time 43492232 ps
CPU time 1.17 seconds
Started Aug 02 06:41:45 PM PDT 24
Finished Aug 02 06:41:46 PM PDT 24
Peak memory 219168 kb
Host smart-11ce41f9-1b8a-47b6-9e89-4720d5eeebc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196270146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2196270146
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.807883206
Short name T848
Test name
Test status
Simulation time 28231632 ps
CPU time 0.83 seconds
Started Aug 02 06:41:48 PM PDT 24
Finished Aug 02 06:41:49 PM PDT 24
Peak memory 218140 kb
Host smart-246a6dc9-1648-4d3d-9ed3-df387327632f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807883206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.807883206
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3637986283
Short name T292
Test name
Test status
Simulation time 80539389 ps
CPU time 2.73 seconds
Started Aug 02 06:41:50 PM PDT 24
Finished Aug 02 06:41:53 PM PDT 24
Peak memory 219476 kb
Host smart-7e687b22-e006-4914-84e7-79b395b4fa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637986283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3637986283
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.3064271023
Short name T947
Test name
Test status
Simulation time 67916579 ps
CPU time 1.12 seconds
Started Aug 02 06:41:47 PM PDT 24
Finished Aug 02 06:41:48 PM PDT 24
Peak memory 219752 kb
Host smart-5f8de015-c397-402b-bc67-263bc77b9f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064271023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.3064271023
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2047411454
Short name T834
Test name
Test status
Simulation time 19113412 ps
CPU time 1.08 seconds
Started Aug 02 06:41:46 PM PDT 24
Finished Aug 02 06:41:47 PM PDT 24
Peak memory 218432 kb
Host smart-44d84859-032b-41da-8831-647008f7f8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047411454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2047411454
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3120298520
Short name T362
Test name
Test status
Simulation time 136221954 ps
CPU time 2.52 seconds
Started Aug 02 06:41:49 PM PDT 24
Finished Aug 02 06:41:51 PM PDT 24
Peak memory 219816 kb
Host smart-149ce2f2-12ab-4c97-88e8-04d8e52a3029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120298520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3120298520
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.4255005888
Short name T744
Test name
Test status
Simulation time 48437685 ps
CPU time 1.16 seconds
Started Aug 02 06:41:48 PM PDT 24
Finished Aug 02 06:41:49 PM PDT 24
Peak memory 218880 kb
Host smart-2476a07b-7f75-40bd-b906-25a6ab3a14d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255005888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.4255005888
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.3701514600
Short name T439
Test name
Test status
Simulation time 49429080 ps
CPU time 0.89 seconds
Started Aug 02 06:41:47 PM PDT 24
Finished Aug 02 06:41:48 PM PDT 24
Peak memory 218444 kb
Host smart-68e5a7ca-ec7e-42c6-b578-d1d0327121a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701514600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3701514600
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2013262402
Short name T326
Test name
Test status
Simulation time 101989456 ps
CPU time 1.25 seconds
Started Aug 02 06:41:48 PM PDT 24
Finished Aug 02 06:41:49 PM PDT 24
Peak memory 218776 kb
Host smart-4715859e-9eea-472a-b64e-58ba6fefe3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013262402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2013262402
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.44378217
Short name T916
Test name
Test status
Simulation time 27312947 ps
CPU time 1.27 seconds
Started Aug 02 06:41:50 PM PDT 24
Finished Aug 02 06:41:52 PM PDT 24
Peak memory 219424 kb
Host smart-0f0db965-a103-4e1a-b674-d2153d00ffd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44378217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.44378217
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.75237581
Short name T164
Test name
Test status
Simulation time 42325142 ps
CPU time 0.94 seconds
Started Aug 02 06:41:52 PM PDT 24
Finished Aug 02 06:41:53 PM PDT 24
Peak memory 219820 kb
Host smart-8ba84b85-6e15-4ff1-8570-a5e0d9c81b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75237581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.75237581
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.83355801
Short name T883
Test name
Test status
Simulation time 76002652 ps
CPU time 1.23 seconds
Started Aug 02 06:41:48 PM PDT 24
Finished Aug 02 06:41:50 PM PDT 24
Peak memory 219836 kb
Host smart-2968daa3-1b52-454c-809a-af5a7ca4531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83355801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.83355801
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1737866661
Short name T611
Test name
Test status
Simulation time 77839673 ps
CPU time 1.13 seconds
Started Aug 02 06:40:08 PM PDT 24
Finished Aug 02 06:40:09 PM PDT 24
Peak memory 219856 kb
Host smart-4f3529fa-e9be-4bf9-ad67-55aef85e005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737866661 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1737866661
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1027303614
Short name T348
Test name
Test status
Simulation time 110469147 ps
CPU time 0.89 seconds
Started Aug 02 06:40:10 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 214924 kb
Host smart-beb4fc46-7188-4fff-aae8-f6d9099461de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027303614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1027303614
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1893985962
Short name T521
Test name
Test status
Simulation time 57005678 ps
CPU time 0.83 seconds
Started Aug 02 06:40:09 PM PDT 24
Finished Aug 02 06:40:10 PM PDT 24
Peak memory 215404 kb
Host smart-36547491-2fe0-45ea-ae2a-982e150da060
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893985962 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1893985962
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.4287865986
Short name T254
Test name
Test status
Simulation time 35834547 ps
CPU time 1.26 seconds
Started Aug 02 06:40:08 PM PDT 24
Finished Aug 02 06:40:09 PM PDT 24
Peak memory 215596 kb
Host smart-b8db7309-a3ad-4e46-a5de-b1ff63e4727e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287865986 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.4287865986
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.549792826
Short name T897
Test name
Test status
Simulation time 111870421 ps
CPU time 0.99 seconds
Started Aug 02 06:40:09 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 219960 kb
Host smart-2389f275-014d-4307-9a07-292d41833eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549792826 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.549792826
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.253521479
Short name T903
Test name
Test status
Simulation time 303666375 ps
CPU time 1.25 seconds
Started Aug 02 06:40:12 PM PDT 24
Finished Aug 02 06:40:14 PM PDT 24
Peak memory 217408 kb
Host smart-54bf358e-669e-4938-a178-049efdc0329e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253521479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.253521479
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1342276680
Short name T37
Test name
Test status
Simulation time 23014776 ps
CPU time 0.95 seconds
Started Aug 02 06:40:09 PM PDT 24
Finished Aug 02 06:40:11 PM PDT 24
Peak memory 215912 kb
Host smart-f2078eae-8f4d-4bc4-b5bb-7ab90e60d417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342276680 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1342276680
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1837850115
Short name T621
Test name
Test status
Simulation time 188050454 ps
CPU time 0.91 seconds
Started Aug 02 06:40:08 PM PDT 24
Finished Aug 02 06:40:09 PM PDT 24
Peak memory 207088 kb
Host smart-c29bcc20-4e81-4053-9e44-d34a5b751287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837850115 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1837850115
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2828254764
Short name T892
Test name
Test status
Simulation time 30640204 ps
CPU time 0.99 seconds
Started Aug 02 06:40:10 PM PDT 24
Finished Aug 02 06:40:12 PM PDT 24
Peak memory 215312 kb
Host smart-4abab81e-e021-48aa-82ae-2f7efb424b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828254764 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2828254764
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3993671968
Short name T958
Test name
Test status
Simulation time 364104470 ps
CPU time 3.93 seconds
Started Aug 02 06:40:08 PM PDT 24
Finished Aug 02 06:40:13 PM PDT 24
Peak memory 219912 kb
Host smart-8194a079-a826-41fc-a822-c961e20700cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993671968 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3993671968
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.636341192
Short name T495
Test name
Test status
Simulation time 422220180277 ps
CPU time 1315.87 seconds
Started Aug 02 06:40:12 PM PDT 24
Finished Aug 02 07:02:08 PM PDT 24
Peak memory 223364 kb
Host smart-24314f6a-d26d-4908-b0cb-92f494fe319c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636341192 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.636341192
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.999271464
Short name T161
Test name
Test status
Simulation time 31715244 ps
CPU time 1.33 seconds
Started Aug 02 06:41:48 PM PDT 24
Finished Aug 02 06:41:49 PM PDT 24
Peak memory 220704 kb
Host smart-dc4c0952-eab8-484d-b724-2c18e595d074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999271464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.999271464
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.1227204864
Short name T761
Test name
Test status
Simulation time 32352502 ps
CPU time 0.88 seconds
Started Aug 02 06:41:48 PM PDT 24
Finished Aug 02 06:41:49 PM PDT 24
Peak memory 219236 kb
Host smart-8fee705f-631e-420c-9018-6fe1504ec0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227204864 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1227204864
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1912039466
Short name T485
Test name
Test status
Simulation time 47448057 ps
CPU time 1.75 seconds
Started Aug 02 06:41:49 PM PDT 24
Finished Aug 02 06:41:51 PM PDT 24
Peak memory 218600 kb
Host smart-b2b86219-7456-4361-9bdc-0efb1f0778b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912039466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1912039466
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.2231711640
Short name T170
Test name
Test status
Simulation time 50892761 ps
CPU time 1.23 seconds
Started Aug 02 06:41:50 PM PDT 24
Finished Aug 02 06:41:51 PM PDT 24
Peak memory 218268 kb
Host smart-30f037e2-ac19-4ce6-a225-126f26f449d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231711640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.2231711640
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3245312452
Short name T144
Test name
Test status
Simulation time 188725962 ps
CPU time 1.13 seconds
Started Aug 02 06:41:49 PM PDT 24
Finished Aug 02 06:41:50 PM PDT 24
Peak memory 220436 kb
Host smart-79470c59-091a-4967-bcf6-c1f9765b2a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245312452 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3245312452
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2614274404
Short name T900
Test name
Test status
Simulation time 249481662 ps
CPU time 1.44 seconds
Started Aug 02 06:41:48 PM PDT 24
Finished Aug 02 06:41:50 PM PDT 24
Peak memory 218988 kb
Host smart-5dcbe3ed-d752-48ce-a7a2-783ad9b98719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614274404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2614274404
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.4057835642
Short name T532
Test name
Test status
Simulation time 24319569 ps
CPU time 1.16 seconds
Started Aug 02 06:41:58 PM PDT 24
Finished Aug 02 06:42:00 PM PDT 24
Peak memory 219764 kb
Host smart-38793097-dd01-4a8e-bf36-8252920f2720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057835642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.4057835642
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.1374924348
Short name T968
Test name
Test status
Simulation time 22614887 ps
CPU time 1.02 seconds
Started Aug 02 06:41:58 PM PDT 24
Finished Aug 02 06:41:59 PM PDT 24
Peak memory 224092 kb
Host smart-c5d07fa8-c792-4965-8cba-a05c1ecc16f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374924348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1374924348
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3212807358
Short name T686
Test name
Test status
Simulation time 61687396 ps
CPU time 1 seconds
Started Aug 02 06:41:49 PM PDT 24
Finished Aug 02 06:41:50 PM PDT 24
Peak memory 217256 kb
Host smart-b86c3057-6116-4925-9c7a-74ab30b7c470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212807358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3212807358
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2949407585
Short name T201
Test name
Test status
Simulation time 43198180 ps
CPU time 1.12 seconds
Started Aug 02 06:42:00 PM PDT 24
Finished Aug 02 06:42:01 PM PDT 24
Peak memory 219716 kb
Host smart-94b85bd1-0a3e-41a8-a916-7368e7f2d27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949407585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2949407585
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.2176108424
Short name T806
Test name
Test status
Simulation time 25130874 ps
CPU time 0.98 seconds
Started Aug 02 06:41:58 PM PDT 24
Finished Aug 02 06:41:59 PM PDT 24
Peak memory 219700 kb
Host smart-4cd25c74-95f2-4448-8502-628ac5c4088e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176108424 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2176108424
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.488919804
Short name T493
Test name
Test status
Simulation time 41778746 ps
CPU time 1.22 seconds
Started Aug 02 06:41:58 PM PDT 24
Finished Aug 02 06:41:59 PM PDT 24
Peak memory 218592 kb
Host smart-390f09fe-e2ee-42e0-a5d9-1af56e29a634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488919804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.488919804
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.2444265113
Short name T923
Test name
Test status
Simulation time 106640817 ps
CPU time 1.23 seconds
Started Aug 02 06:42:02 PM PDT 24
Finished Aug 02 06:42:04 PM PDT 24
Peak memory 215752 kb
Host smart-12f238f0-fd26-431b-bb05-149ccec86c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444265113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.2444265113
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1300498719
Short name T460
Test name
Test status
Simulation time 22753232 ps
CPU time 0.95 seconds
Started Aug 02 06:42:00 PM PDT 24
Finished Aug 02 06:42:01 PM PDT 24
Peak memory 218792 kb
Host smart-d30c401e-056e-495b-ad28-b41116ddfd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300498719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1300498719
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3525038744
Short name T421
Test name
Test status
Simulation time 34495410 ps
CPU time 1.34 seconds
Started Aug 02 06:41:57 PM PDT 24
Finished Aug 02 06:41:59 PM PDT 24
Peak memory 217476 kb
Host smart-1b7b3de9-84b1-4edd-b35f-ca90b1a0b769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525038744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3525038744
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.970152491
Short name T525
Test name
Test status
Simulation time 97111858 ps
CPU time 1.13 seconds
Started Aug 02 06:41:58 PM PDT 24
Finished Aug 02 06:41:59 PM PDT 24
Peak memory 219880 kb
Host smart-027b5d8e-0cb9-492b-87ca-473280fa93ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970152491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.970152491
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1956325245
Short name T40
Test name
Test status
Simulation time 19632431 ps
CPU time 1.19 seconds
Started Aug 02 06:41:56 PM PDT 24
Finished Aug 02 06:41:57 PM PDT 24
Peak memory 224060 kb
Host smart-0d9e2f53-bb72-4694-8d91-6ec6cda4e811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956325245 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1956325245
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3461564979
Short name T45
Test name
Test status
Simulation time 46395541 ps
CPU time 1.38 seconds
Started Aug 02 06:41:55 PM PDT 24
Finished Aug 02 06:41:57 PM PDT 24
Peak memory 218352 kb
Host smart-66176416-6fae-4add-b70b-878d9ab4af00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461564979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3461564979
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.2739175857
Short name T873
Test name
Test status
Simulation time 40226166 ps
CPU time 1.07 seconds
Started Aug 02 06:41:54 PM PDT 24
Finished Aug 02 06:41:55 PM PDT 24
Peak memory 218472 kb
Host smart-aa1de154-9e73-41a3-8f92-cafadeabd030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739175857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.2739175857
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.204762517
Short name T136
Test name
Test status
Simulation time 20660599 ps
CPU time 1 seconds
Started Aug 02 06:42:00 PM PDT 24
Finished Aug 02 06:42:01 PM PDT 24
Peak memory 219348 kb
Host smart-ea26ba8d-0d11-45ae-bef5-2b04baef2885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204762517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.204762517
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1992825279
Short name T48
Test name
Test status
Simulation time 52899801 ps
CPU time 1.53 seconds
Started Aug 02 06:41:58 PM PDT 24
Finished Aug 02 06:41:59 PM PDT 24
Peak memory 218888 kb
Host smart-c051ab0b-7d88-4d81-bf49-1c4e2454ccb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992825279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1992825279
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.496966647
Short name T192
Test name
Test status
Simulation time 76202503 ps
CPU time 1.1 seconds
Started Aug 02 06:41:54 PM PDT 24
Finished Aug 02 06:41:55 PM PDT 24
Peak memory 219588 kb
Host smart-ff1d2459-fde9-444f-a51f-df580b1764cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496966647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.496966647
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.822791662
Short name T972
Test name
Test status
Simulation time 23346396 ps
CPU time 1.08 seconds
Started Aug 02 06:41:58 PM PDT 24
Finished Aug 02 06:41:59 PM PDT 24
Peak memory 224192 kb
Host smart-ed0ce5f3-5a65-4d3b-b41e-3172f4d0423a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822791662 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.822791662
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3681430817
Short name T385
Test name
Test status
Simulation time 35949154 ps
CPU time 1.36 seconds
Started Aug 02 06:41:56 PM PDT 24
Finished Aug 02 06:41:57 PM PDT 24
Peak memory 218464 kb
Host smart-c8ee63d8-74e9-4511-ae8e-4fef3d655472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681430817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3681430817
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.1054716732
Short name T252
Test name
Test status
Simulation time 62364541 ps
CPU time 1.32 seconds
Started Aug 02 06:41:58 PM PDT 24
Finished Aug 02 06:41:59 PM PDT 24
Peak memory 215708 kb
Host smart-fb092dbc-a754-4d40-bd03-727c2809de5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054716732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.1054716732
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_genbits.35328246
Short name T473
Test name
Test status
Simulation time 130006167 ps
CPU time 1.85 seconds
Started Aug 02 06:41:57 PM PDT 24
Finished Aug 02 06:41:59 PM PDT 24
Peak memory 218804 kb
Host smart-231712ec-cc51-4ce1-8091-ccf7eb9d5133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35328246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.35328246
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.3453041492
Short name T311
Test name
Test status
Simulation time 24121073 ps
CPU time 1.25 seconds
Started Aug 02 06:41:56 PM PDT 24
Finished Aug 02 06:41:58 PM PDT 24
Peak memory 219564 kb
Host smart-86349cda-bbb6-40a5-8144-2295c3df3ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453041492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.3453041492
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3807140575
Short name T181
Test name
Test status
Simulation time 29550095 ps
CPU time 1.36 seconds
Started Aug 02 06:41:58 PM PDT 24
Finished Aug 02 06:41:59 PM PDT 24
Peak memory 225792 kb
Host smart-0b7153dd-2511-4398-b568-1f9b7cfdf205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807140575 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3807140575
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.4143359107
Short name T607
Test name
Test status
Simulation time 47091208 ps
CPU time 1.43 seconds
Started Aug 02 06:42:00 PM PDT 24
Finished Aug 02 06:42:01 PM PDT 24
Peak memory 218664 kb
Host smart-56c08bc4-3daa-4a25-aa23-21d1472e317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143359107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.4143359107
Directory /workspace/99.edn_genbits/latest
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