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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.46 98.25 93.31 90.85 87.79 95.50 96.83 91.70


Total test records in report: 1125
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T1016 /workspace/coverage/cover_reg_top/27.edn_intr_test.2784690187 Aug 03 04:36:57 PM PDT 24 Aug 03 04:36:58 PM PDT 24 20017950 ps
T1017 /workspace/coverage/cover_reg_top/3.edn_csr_rw.215363665 Aug 03 04:36:48 PM PDT 24 Aug 03 04:36:49 PM PDT 24 52910153 ps
T1018 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3569680928 Aug 03 04:36:46 PM PDT 24 Aug 03 04:36:48 PM PDT 24 62098880 ps
T1019 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2775098797 Aug 03 04:36:58 PM PDT 24 Aug 03 04:37:00 PM PDT 24 87085705 ps
T1020 /workspace/coverage/cover_reg_top/2.edn_intr_test.1141620413 Aug 03 04:36:46 PM PDT 24 Aug 03 04:36:47 PM PDT 24 12692425 ps
T1021 /workspace/coverage/cover_reg_top/35.edn_intr_test.2033060762 Aug 03 04:37:05 PM PDT 24 Aug 03 04:37:06 PM PDT 24 11291641 ps
T264 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4000685417 Aug 03 04:36:58 PM PDT 24 Aug 03 04:37:00 PM PDT 24 63417821 ps
T1022 /workspace/coverage/cover_reg_top/4.edn_tl_errors.315967647 Aug 03 04:36:50 PM PDT 24 Aug 03 04:36:53 PM PDT 24 418456537 ps
T1023 /workspace/coverage/cover_reg_top/32.edn_intr_test.2708066531 Aug 03 04:37:02 PM PDT 24 Aug 03 04:37:08 PM PDT 24 20918040 ps
T265 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3373064755 Aug 03 04:37:00 PM PDT 24 Aug 03 04:37:01 PM PDT 24 49440168 ps
T1024 /workspace/coverage/cover_reg_top/25.edn_intr_test.3686757078 Aug 03 04:36:58 PM PDT 24 Aug 03 04:36:59 PM PDT 24 20305093 ps
T1025 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1730048649 Aug 03 04:36:46 PM PDT 24 Aug 03 04:36:49 PM PDT 24 64130100 ps
T1026 /workspace/coverage/cover_reg_top/29.edn_intr_test.728202006 Aug 03 04:37:02 PM PDT 24 Aug 03 04:37:04 PM PDT 24 33509112 ps
T1027 /workspace/coverage/cover_reg_top/8.edn_intr_test.335590996 Aug 03 04:36:59 PM PDT 24 Aug 03 04:37:00 PM PDT 24 24898083 ps
T258 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2153836570 Aug 03 04:36:46 PM PDT 24 Aug 03 04:36:47 PM PDT 24 15388934 ps
T1028 /workspace/coverage/cover_reg_top/14.edn_intr_test.443456036 Aug 03 04:36:55 PM PDT 24 Aug 03 04:36:56 PM PDT 24 99679547 ps
T1029 /workspace/coverage/cover_reg_top/49.edn_intr_test.3246359095 Aug 03 04:37:00 PM PDT 24 Aug 03 04:37:01 PM PDT 24 29152954 ps
T1030 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2077901932 Aug 03 04:37:00 PM PDT 24 Aug 03 04:37:03 PM PDT 24 59829767 ps
T1031 /workspace/coverage/cover_reg_top/39.edn_intr_test.2334576129 Aug 03 04:37:00 PM PDT 24 Aug 03 04:37:01 PM PDT 24 12264084 ps
T1032 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2352577164 Aug 03 04:36:50 PM PDT 24 Aug 03 04:36:52 PM PDT 24 54185020 ps
T259 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3041677926 Aug 03 04:36:54 PM PDT 24 Aug 03 04:36:55 PM PDT 24 92670767 ps
T1033 /workspace/coverage/cover_reg_top/17.edn_intr_test.718952535 Aug 03 04:36:55 PM PDT 24 Aug 03 04:36:55 PM PDT 24 15123267 ps
T1034 /workspace/coverage/cover_reg_top/40.edn_intr_test.3620908611 Aug 03 04:37:08 PM PDT 24 Aug 03 04:37:09 PM PDT 24 12124580 ps
T272 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1582197299 Aug 03 04:36:50 PM PDT 24 Aug 03 04:36:52 PM PDT 24 42648190 ps
T273 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3183530770 Aug 03 04:37:10 PM PDT 24 Aug 03 04:37:11 PM PDT 24 19968653 ps
T1035 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3852364055 Aug 03 04:36:55 PM PDT 24 Aug 03 04:36:57 PM PDT 24 78792111 ps
T1036 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2809000801 Aug 03 04:36:44 PM PDT 24 Aug 03 04:36:46 PM PDT 24 73734331 ps
T1037 /workspace/coverage/cover_reg_top/12.edn_intr_test.3770948091 Aug 03 04:36:51 PM PDT 24 Aug 03 04:36:52 PM PDT 24 32496114 ps
T1038 /workspace/coverage/cover_reg_top/12.edn_tl_errors.4127225645 Aug 03 04:36:52 PM PDT 24 Aug 03 04:36:55 PM PDT 24 72963347 ps
T1039 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2506501486 Aug 03 04:36:58 PM PDT 24 Aug 03 04:37:00 PM PDT 24 38014138 ps
T260 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2674925411 Aug 03 04:36:49 PM PDT 24 Aug 03 04:36:50 PM PDT 24 34946620 ps
T1040 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2540028331 Aug 03 04:36:54 PM PDT 24 Aug 03 04:36:56 PM PDT 24 32402680 ps
T1041 /workspace/coverage/cover_reg_top/1.edn_csr_rw.851827463 Aug 03 04:36:52 PM PDT 24 Aug 03 04:36:53 PM PDT 24 17147368 ps
T1042 /workspace/coverage/cover_reg_top/48.edn_intr_test.3107589268 Aug 03 04:37:04 PM PDT 24 Aug 03 04:37:05 PM PDT 24 14264633 ps
T1043 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3435207864 Aug 03 04:36:56 PM PDT 24 Aug 03 04:36:59 PM PDT 24 150145701 ps
T1044 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1442010153 Aug 03 04:36:56 PM PDT 24 Aug 03 04:36:57 PM PDT 24 27011283 ps
T287 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.492555843 Aug 03 04:37:01 PM PDT 24 Aug 03 04:37:03 PM PDT 24 87578082 ps
T1045 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.159952755 Aug 03 04:37:02 PM PDT 24 Aug 03 04:37:04 PM PDT 24 31456338 ps
T283 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.487866247 Aug 03 04:36:55 PM PDT 24 Aug 03 04:36:57 PM PDT 24 160918006 ps
T1046 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1543159344 Aug 03 04:36:55 PM PDT 24 Aug 03 04:36:56 PM PDT 24 31010877 ps
T1047 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2098520416 Aug 03 04:36:55 PM PDT 24 Aug 03 04:36:57 PM PDT 24 137099589 ps
T1048 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3583674529 Aug 03 04:36:58 PM PDT 24 Aug 03 04:36:59 PM PDT 24 98813651 ps
T1049 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3579118215 Aug 03 04:36:46 PM PDT 24 Aug 03 04:36:50 PM PDT 24 548491230 ps
T1050 /workspace/coverage/cover_reg_top/9.edn_intr_test.3590709433 Aug 03 04:37:01 PM PDT 24 Aug 03 04:37:02 PM PDT 24 33101677 ps
T1051 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2408490735 Aug 03 04:36:59 PM PDT 24 Aug 03 04:37:02 PM PDT 24 195273057 ps
T284 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.454141882 Aug 03 04:36:59 PM PDT 24 Aug 03 04:37:00 PM PDT 24 44748031 ps
T1052 /workspace/coverage/cover_reg_top/4.edn_intr_test.2218390128 Aug 03 04:36:51 PM PDT 24 Aug 03 04:36:52 PM PDT 24 14205561 ps
T1053 /workspace/coverage/cover_reg_top/41.edn_intr_test.2369034502 Aug 03 04:36:59 PM PDT 24 Aug 03 04:37:09 PM PDT 24 22378194 ps
T1054 /workspace/coverage/cover_reg_top/43.edn_intr_test.2189749536 Aug 03 04:36:55 PM PDT 24 Aug 03 04:36:56 PM PDT 24 35619194 ps
T1055 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2500675220 Aug 03 04:36:58 PM PDT 24 Aug 03 04:37:01 PM PDT 24 302062731 ps
T1056 /workspace/coverage/cover_reg_top/8.edn_csr_rw.4026381582 Aug 03 04:36:57 PM PDT 24 Aug 03 04:36:58 PM PDT 24 14355389 ps
T1057 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.119847076 Aug 03 04:36:52 PM PDT 24 Aug 03 04:36:53 PM PDT 24 29741200 ps
T1058 /workspace/coverage/cover_reg_top/20.edn_intr_test.3441422965 Aug 03 04:36:59 PM PDT 24 Aug 03 04:37:00 PM PDT 24 19588257 ps
T1059 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3807758200 Aug 03 04:36:51 PM PDT 24 Aug 03 04:36:53 PM PDT 24 36162754 ps
T1060 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.919505327 Aug 03 04:36:50 PM PDT 24 Aug 03 04:36:53 PM PDT 24 161381396 ps
T1061 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1194192065 Aug 03 04:36:57 PM PDT 24 Aug 03 04:37:04 PM PDT 24 86422735 ps
T1062 /workspace/coverage/cover_reg_top/47.edn_intr_test.2751669363 Aug 03 04:36:57 PM PDT 24 Aug 03 04:36:58 PM PDT 24 15724020 ps
T1063 /workspace/coverage/cover_reg_top/11.edn_intr_test.1074425657 Aug 03 04:36:52 PM PDT 24 Aug 03 04:36:53 PM PDT 24 15527264 ps
T1064 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3619563560 Aug 03 04:36:52 PM PDT 24 Aug 03 04:36:54 PM PDT 24 74446559 ps
T1065 /workspace/coverage/cover_reg_top/19.edn_intr_test.732436148 Aug 03 04:37:01 PM PDT 24 Aug 03 04:37:02 PM PDT 24 27435769 ps
T1066 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.844114191 Aug 03 04:36:59 PM PDT 24 Aug 03 04:37:00 PM PDT 24 33972679 ps
T1067 /workspace/coverage/cover_reg_top/9.edn_tl_errors.757218084 Aug 03 04:36:50 PM PDT 24 Aug 03 04:36:52 PM PDT 24 46402467 ps
T1068 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3653755061 Aug 03 04:36:51 PM PDT 24 Aug 03 04:36:52 PM PDT 24 202945957 ps
T261 /workspace/coverage/cover_reg_top/0.edn_csr_rw.39074557 Aug 03 04:36:54 PM PDT 24 Aug 03 04:36:55 PM PDT 24 64175472 ps
T1069 /workspace/coverage/cover_reg_top/36.edn_intr_test.4291162303 Aug 03 04:37:00 PM PDT 24 Aug 03 04:37:01 PM PDT 24 153799363 ps
T1070 /workspace/coverage/cover_reg_top/1.edn_intr_test.550834157 Aug 03 04:36:51 PM PDT 24 Aug 03 04:36:52 PM PDT 24 19276585 ps
T1071 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2539948324 Aug 03 04:36:56 PM PDT 24 Aug 03 04:36:57 PM PDT 24 34596718 ps
T1072 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1820841642 Aug 03 04:36:54 PM PDT 24 Aug 03 04:36:55 PM PDT 24 217775899 ps
T1073 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.16944080 Aug 03 04:36:54 PM PDT 24 Aug 03 04:36:55 PM PDT 24 109509750 ps
T1074 /workspace/coverage/cover_reg_top/23.edn_intr_test.628760272 Aug 03 04:36:59 PM PDT 24 Aug 03 04:37:00 PM PDT 24 13627644 ps
T1075 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2981521932 Aug 03 04:36:56 PM PDT 24 Aug 03 04:36:57 PM PDT 24 308907307 ps
T1076 /workspace/coverage/cover_reg_top/8.edn_tl_errors.331376156 Aug 03 04:36:53 PM PDT 24 Aug 03 04:36:55 PM PDT 24 28076144 ps
T1077 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4103704794 Aug 03 04:36:45 PM PDT 24 Aug 03 04:36:47 PM PDT 24 53013432 ps
T1078 /workspace/coverage/cover_reg_top/18.edn_intr_test.4155496297 Aug 03 04:37:00 PM PDT 24 Aug 03 04:37:01 PM PDT 24 13188463 ps
T1079 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3463389624 Aug 03 04:36:55 PM PDT 24 Aug 03 04:36:56 PM PDT 24 97639897 ps
T1080 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3800675856 Aug 03 04:36:48 PM PDT 24 Aug 03 04:36:50 PM PDT 24 20615772 ps
T1081 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2249101439 Aug 03 04:36:49 PM PDT 24 Aug 03 04:36:50 PM PDT 24 34482588 ps
T1082 /workspace/coverage/cover_reg_top/26.edn_intr_test.1502462246 Aug 03 04:37:07 PM PDT 24 Aug 03 04:37:08 PM PDT 24 32492046 ps
T1083 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3278236725 Aug 03 04:36:57 PM PDT 24 Aug 03 04:36:58 PM PDT 24 18387812 ps
T1084 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3650157801 Aug 03 04:36:52 PM PDT 24 Aug 03 04:36:53 PM PDT 24 19164374 ps
T262 /workspace/coverage/cover_reg_top/15.edn_csr_rw.4140564157 Aug 03 04:36:58 PM PDT 24 Aug 03 04:37:04 PM PDT 24 40893672 ps
T285 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.187528734 Aug 03 04:36:55 PM PDT 24 Aug 03 04:36:57 PM PDT 24 143692201 ps
T1085 /workspace/coverage/cover_reg_top/33.edn_intr_test.3383690692 Aug 03 04:37:05 PM PDT 24 Aug 03 04:37:06 PM PDT 24 26824626 ps
T1086 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2308603982 Aug 03 04:37:03 PM PDT 24 Aug 03 04:37:05 PM PDT 24 72249168 ps
T1087 /workspace/coverage/cover_reg_top/15.edn_intr_test.4247927406 Aug 03 04:37:01 PM PDT 24 Aug 03 04:37:02 PM PDT 24 15363424 ps
T263 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3676983111 Aug 03 04:36:45 PM PDT 24 Aug 03 04:36:46 PM PDT 24 66095030 ps
T1088 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1985622791 Aug 03 04:36:51 PM PDT 24 Aug 03 04:36:53 PM PDT 24 137215986 ps
T1089 /workspace/coverage/cover_reg_top/34.edn_intr_test.2524149852 Aug 03 04:37:05 PM PDT 24 Aug 03 04:37:06 PM PDT 24 14466654 ps
T1090 /workspace/coverage/cover_reg_top/0.edn_intr_test.3410597601 Aug 03 04:36:48 PM PDT 24 Aug 03 04:36:49 PM PDT 24 33076911 ps
T1091 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2873087997 Aug 03 04:37:02 PM PDT 24 Aug 03 04:37:06 PM PDT 24 141909404 ps
T1092 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.563348590 Aug 03 04:36:51 PM PDT 24 Aug 03 04:36:53 PM PDT 24 106854087 ps
T1093 /workspace/coverage/cover_reg_top/45.edn_intr_test.61099899 Aug 03 04:37:01 PM PDT 24 Aug 03 04:37:02 PM PDT 24 14058218 ps
T1094 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1133863851 Aug 03 04:36:55 PM PDT 24 Aug 03 04:36:56 PM PDT 24 51032540 ps
T1095 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1397802369 Aug 03 04:36:52 PM PDT 24 Aug 03 04:36:53 PM PDT 24 39233955 ps
T1096 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3789259855 Aug 03 04:36:45 PM PDT 24 Aug 03 04:36:46 PM PDT 24 50075723 ps
T288 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1901737438 Aug 03 04:36:57 PM PDT 24 Aug 03 04:37:00 PM PDT 24 104552247 ps
T1097 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1580977174 Aug 03 04:36:53 PM PDT 24 Aug 03 04:36:54 PM PDT 24 28349846 ps
T1098 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1507384276 Aug 03 04:36:58 PM PDT 24 Aug 03 04:37:03 PM PDT 24 738232138 ps
T1099 /workspace/coverage/cover_reg_top/21.edn_intr_test.3348810748 Aug 03 04:36:58 PM PDT 24 Aug 03 04:36:59 PM PDT 24 16621838 ps
T1100 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2174715982 Aug 03 04:36:57 PM PDT 24 Aug 03 04:37:00 PM PDT 24 165071940 ps
T1101 /workspace/coverage/cover_reg_top/31.edn_intr_test.2786612358 Aug 03 04:37:02 PM PDT 24 Aug 03 04:37:03 PM PDT 24 25103993 ps
T1102 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1770549989 Aug 03 04:36:58 PM PDT 24 Aug 03 04:37:02 PM PDT 24 655282661 ps
T1103 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1528316885 Aug 03 04:36:48 PM PDT 24 Aug 03 04:36:50 PM PDT 24 107882925 ps
T1104 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.362627334 Aug 03 04:36:50 PM PDT 24 Aug 03 04:36:52 PM PDT 24 75036877 ps
T1105 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3594127153 Aug 03 04:36:46 PM PDT 24 Aug 03 04:36:48 PM PDT 24 36337610 ps
T1106 /workspace/coverage/cover_reg_top/5.edn_intr_test.70967597 Aug 03 04:36:57 PM PDT 24 Aug 03 04:36:58 PM PDT 24 51368185 ps
T1107 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.548137088 Aug 03 04:36:54 PM PDT 24 Aug 03 04:36:56 PM PDT 24 59849787 ps
T1108 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2295769039 Aug 03 04:36:58 PM PDT 24 Aug 03 04:36:59 PM PDT 24 34928218 ps
T1109 /workspace/coverage/cover_reg_top/13.edn_intr_test.1073819285 Aug 03 04:36:51 PM PDT 24 Aug 03 04:36:52 PM PDT 24 18457088 ps
T1110 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2562515229 Aug 03 04:37:00 PM PDT 24 Aug 03 04:37:02 PM PDT 24 30182085 ps
T1111 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3589191228 Aug 03 04:37:02 PM PDT 24 Aug 03 04:37:05 PM PDT 24 84059293 ps
T1112 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3487023823 Aug 03 04:36:54 PM PDT 24 Aug 03 04:36:55 PM PDT 24 18094171 ps
T1113 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1999344392 Aug 03 04:36:52 PM PDT 24 Aug 03 04:36:53 PM PDT 24 16536296 ps
T1114 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3736873412 Aug 03 04:36:57 PM PDT 24 Aug 03 04:37:03 PM PDT 24 28942403 ps
T1115 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2516058793 Aug 03 04:36:42 PM PDT 24 Aug 03 04:36:44 PM PDT 24 24691469 ps
T1116 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1065896272 Aug 03 04:36:49 PM PDT 24 Aug 03 04:36:50 PM PDT 24 28575969 ps
T1117 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3088995233 Aug 03 04:36:57 PM PDT 24 Aug 03 04:36:58 PM PDT 24 22120250 ps
T1118 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3645063586 Aug 03 04:36:50 PM PDT 24 Aug 03 04:36:52 PM PDT 24 35287225 ps
T1119 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2497564819 Aug 03 04:36:57 PM PDT 24 Aug 03 04:36:58 PM PDT 24 54157601 ps
T1120 /workspace/coverage/cover_reg_top/3.edn_intr_test.2781927498 Aug 03 04:36:58 PM PDT 24 Aug 03 04:36:59 PM PDT 24 12285459 ps
T1121 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.4070149445 Aug 03 04:36:48 PM PDT 24 Aug 03 04:36:50 PM PDT 24 37394059 ps
T1122 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3464719161 Aug 03 04:36:52 PM PDT 24 Aug 03 04:36:54 PM PDT 24 43479949 ps
T1123 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3067016820 Aug 03 04:36:53 PM PDT 24 Aug 03 04:36:54 PM PDT 24 45872824 ps
T1124 /workspace/coverage/cover_reg_top/30.edn_intr_test.582382930 Aug 03 04:37:05 PM PDT 24 Aug 03 04:37:06 PM PDT 24 17185145 ps
T1125 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3046391045 Aug 03 04:36:47 PM PDT 24 Aug 03 04:36:48 PM PDT 24 90654646 ps

Test location /workspace/coverage/default/176.edn_alert.2412369494
Short name T10
Test name
Test status
Simulation time 94996102 ps
CPU time 1.15 seconds
Started Aug 03 05:52:18 PM PDT 24
Finished Aug 03 05:52:20 PM PDT 24
Peak memory 218616 kb
Host smart-ff2e6ea1-341a-4577-979b-d3f3cc390236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412369494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2412369494
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/29.edn_genbits.1549192020
Short name T28
Test name
Test status
Simulation time 35336338 ps
CPU time 1.55 seconds
Started Aug 03 05:49:26 PM PDT 24
Finished Aug 03 05:49:27 PM PDT 24
Peak memory 218520 kb
Host smart-02ef6f97-7dae-402d-ab7d-f1ef2aab6ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549192020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1549192020
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_stress_all.1108454740
Short name T1
Test name
Test status
Simulation time 354051558 ps
CPU time 4.31 seconds
Started Aug 03 05:50:04 PM PDT 24
Finished Aug 03 05:50:09 PM PDT 24
Peak memory 217140 kb
Host smart-79a51f44-eb67-4029-8eae-b495f4a7d13f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108454740 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1108454740
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_intr.3931792644
Short name T31
Test name
Test status
Simulation time 39020310 ps
CPU time 0.93 seconds
Started Aug 03 05:48:57 PM PDT 24
Finished Aug 03 05:48:58 PM PDT 24
Peak memory 215556 kb
Host smart-8e118ca7-e749-4aac-a173-5dffceee880b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931792644 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3931792644
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.569284675
Short name T134
Test name
Test status
Simulation time 78702801646 ps
CPU time 1808.82 seconds
Started Aug 03 05:48:33 PM PDT 24
Finished Aug 03 06:18:42 PM PDT 24
Peak memory 225156 kb
Host smart-291dbf4a-cc31-4665-8372-2b2af81d2a70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569284675 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.569284675
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.4138697840
Short name T38
Test name
Test status
Simulation time 31145286 ps
CPU time 1.1 seconds
Started Aug 03 05:48:33 PM PDT 24
Finished Aug 03 05:48:34 PM PDT 24
Peak memory 218364 kb
Host smart-a10f3589-36bb-43e4-8863-1bdb9fcba28d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138697840 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.4138697840
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/57.edn_err.2403777642
Short name T46
Test name
Test status
Simulation time 23025146 ps
CPU time 1.03 seconds
Started Aug 03 05:50:52 PM PDT 24
Finished Aug 03 05:50:53 PM PDT 24
Peak memory 224056 kb
Host smart-d5f2562e-0a1d-410c-b10a-269d64894ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403777642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2403777642
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/174.edn_genbits.3016127560
Short name T13
Test name
Test status
Simulation time 40210996 ps
CPU time 1.46 seconds
Started Aug 03 05:52:15 PM PDT 24
Finished Aug 03 05:52:16 PM PDT 24
Peak memory 220052 kb
Host smart-22628e72-db2a-4f95-b84a-5d253df6588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016127560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3016127560
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2225790645
Short name T11
Test name
Test status
Simulation time 29545145 ps
CPU time 1.28 seconds
Started Aug 03 05:47:54 PM PDT 24
Finished Aug 03 05:47:55 PM PDT 24
Peak memory 219612 kb
Host smart-70b255a8-3ac5-493e-b82c-af492e016158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225790645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2225790645
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/100.edn_alert.2202091059
Short name T142
Test name
Test status
Simulation time 185237833 ps
CPU time 1.28 seconds
Started Aug 03 05:51:31 PM PDT 24
Finished Aug 03 05:51:32 PM PDT 24
Peak memory 219844 kb
Host smart-623ed740-5ee7-47b8-8886-e864f2533583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202091059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2202091059
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/39.edn_disable.2937150079
Short name T77
Test name
Test status
Simulation time 35200711 ps
CPU time 0.89 seconds
Started Aug 03 05:50:03 PM PDT 24
Finished Aug 03 05:50:04 PM PDT 24
Peak memory 216176 kb
Host smart-a24959e3-7d0f-4ee4-95cd-6fb96f27b5d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937150079 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2937150079
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/12.edn_intr.4180716688
Short name T93
Test name
Test status
Simulation time 22650807 ps
CPU time 0.99 seconds
Started Aug 03 05:48:07 PM PDT 24
Finished Aug 03 05:48:08 PM PDT 24
Peak memory 215808 kb
Host smart-1cd48462-2c80-4775-bd3c-faa9dcf7e936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180716688 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.4180716688
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.4137609746
Short name T86
Test name
Test status
Simulation time 16151085 ps
CPU time 1 seconds
Started Aug 03 05:47:00 PM PDT 24
Finished Aug 03 05:47:01 PM PDT 24
Peak memory 206956 kb
Host smart-69812f98-2345-4f07-b0b5-7fe268781203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137609746 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.4137609746
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/197.edn_alert.1251008836
Short name T138
Test name
Test status
Simulation time 27980813 ps
CPU time 1.26 seconds
Started Aug 03 05:52:37 PM PDT 24
Finished Aug 03 05:52:39 PM PDT 24
Peak memory 220860 kb
Host smart-dcbf07fc-cab0-4738-b255-a591fbb9e133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251008836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.1251008836
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.487866247
Short name T283
Test name
Test status
Simulation time 160918006 ps
CPU time 2.28 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 206708 kb
Host smart-924c023a-6fda-400e-b26b-00e5a356d452
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487866247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.487866247
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/17.edn_disable.4092379071
Short name T98
Test name
Test status
Simulation time 12394064 ps
CPU time 0.88 seconds
Started Aug 03 05:48:32 PM PDT 24
Finished Aug 03 05:48:33 PM PDT 24
Peak memory 216408 kb
Host smart-e426737c-4487-420b-83f0-b8f544363d7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092379071 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.4092379071
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/8.edn_intr.498926459
Short name T20
Test name
Test status
Simulation time 52029168 ps
CPU time 0.86 seconds
Started Aug 03 05:47:46 PM PDT 24
Finished Aug 03 05:47:47 PM PDT 24
Peak memory 215664 kb
Host smart-fbb93bcb-2d69-404b-b6d2-59a384f2da33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498926459 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.498926459
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/14.edn_disable.3709635232
Short name T109
Test name
Test status
Simulation time 26490465 ps
CPU time 0.84 seconds
Started Aug 03 05:48:16 PM PDT 24
Finished Aug 03 05:48:17 PM PDT 24
Peak memory 216300 kb
Host smart-5ea110de-abb0-4854-b30a-a02126128ad4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709635232 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3709635232
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/88.edn_alert.2696653918
Short name T164
Test name
Test status
Simulation time 83773131 ps
CPU time 1.32 seconds
Started Aug 03 05:51:22 PM PDT 24
Finished Aug 03 05:51:23 PM PDT 24
Peak memory 218472 kb
Host smart-175b0827-72a2-4b12-9ca0-30579b0d525e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696653918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.2696653918
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1892865
Short name T179
Test name
Test status
Simulation time 49739861 ps
CPU time 1.24 seconds
Started Aug 03 05:49:50 PM PDT 24
Finished Aug 03 05:49:51 PM PDT 24
Peak memory 216840 kb
Host smart-ff2833fc-e75d-454e-b970-9caa7e6c2d6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892865 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disab
le_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disa
ble_auto_req_mode.1892865
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_disable.2053965962
Short name T34
Test name
Test status
Simulation time 11324005 ps
CPU time 0.87 seconds
Started Aug 03 05:47:55 PM PDT 24
Finished Aug 03 05:47:56 PM PDT 24
Peak memory 215368 kb
Host smart-2bd8775a-3d1e-4e17-a01c-4ae523b8e62a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053965962 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2053965962
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/64.edn_genbits.4279120647
Short name T41
Test name
Test status
Simulation time 270324130 ps
CPU time 1.62 seconds
Started Aug 03 05:50:53 PM PDT 24
Finished Aug 03 05:50:55 PM PDT 24
Peak memory 220056 kb
Host smart-1ef6e52f-776b-4827-941a-0e95556fe507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279120647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.4279120647
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_err.1325951300
Short name T42
Test name
Test status
Simulation time 64070911 ps
CPU time 0.84 seconds
Started Aug 03 05:46:22 PM PDT 24
Finished Aug 03 05:46:24 PM PDT 24
Peak memory 219088 kb
Host smart-474fcf0a-8fc9-411f-8293-f6bb69aada41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325951300 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1325951300
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.934055941
Short name T23
Test name
Test status
Simulation time 45900647057 ps
CPU time 1266.31 seconds
Started Aug 03 05:47:28 PM PDT 24
Finished Aug 03 06:08:35 PM PDT 24
Peak memory 221196 kb
Host smart-74db8ac0-e276-4e51-978d-9302330b9c0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934055941 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.934055941
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.39074557
Short name T261
Test name
Test status
Simulation time 64175472 ps
CPU time 0.82 seconds
Started Aug 03 04:36:54 PM PDT 24
Finished Aug 03 04:36:55 PM PDT 24
Peak memory 206396 kb
Host smart-2e6f7c80-ff11-4102-8bf0-27f4c1dc1a11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39074557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.39074557
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/15.edn_alert.317554971
Short name T198
Test name
Test status
Simulation time 60399121 ps
CPU time 1.06 seconds
Started Aug 03 05:48:28 PM PDT 24
Finished Aug 03 05:48:30 PM PDT 24
Peak memory 220944 kb
Host smart-465d240a-ea4c-4a26-926f-9e6af0dc10dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317554971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.317554971
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/82.edn_alert.262070229
Short name T367
Test name
Test status
Simulation time 203552462 ps
CPU time 1.21 seconds
Started Aug 03 05:51:17 PM PDT 24
Finished Aug 03 05:51:18 PM PDT 24
Peak memory 219908 kb
Host smart-f3e7700b-9a53-4052-a6e1-b8c281f7742d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262070229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.262070229
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/130.edn_alert.2723990389
Short name T151
Test name
Test status
Simulation time 73734661 ps
CPU time 1.11 seconds
Started Aug 03 05:51:55 PM PDT 24
Finished Aug 03 05:51:56 PM PDT 24
Peak memory 219064 kb
Host smart-1f79df58-9a79-4907-9627-b7f5e6a91b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723990389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2723990389
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/204.edn_genbits.314923445
Short name T35
Test name
Test status
Simulation time 45855596 ps
CPU time 1.47 seconds
Started Aug 03 05:52:38 PM PDT 24
Finished Aug 03 05:52:40 PM PDT 24
Peak memory 218584 kb
Host smart-c1dc54b4-ad20-4dd6-8329-226b5c42bd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314923445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.314923445
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.2569513694
Short name T486
Test name
Test status
Simulation time 27638064 ps
CPU time 1.11 seconds
Started Aug 03 05:51:41 PM PDT 24
Finished Aug 03 05:51:42 PM PDT 24
Peak memory 220668 kb
Host smart-9ffb6c6f-73b8-4b32-bc55-522e2e967643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569513694 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2569513694
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert.3297799735
Short name T531
Test name
Test status
Simulation time 24855555 ps
CPU time 1.15 seconds
Started Aug 03 05:48:08 PM PDT 24
Finished Aug 03 05:48:09 PM PDT 24
Peak memory 218880 kb
Host smart-bcf1ad13-2287-4369-ac25-14d4ffacdbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297799735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3297799735
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/146.edn_alert.2239288709
Short name T904
Test name
Test status
Simulation time 25786402 ps
CPU time 1.24 seconds
Started Aug 03 05:52:00 PM PDT 24
Finished Aug 03 05:52:02 PM PDT 24
Peak memory 218612 kb
Host smart-d8682e57-52cf-4f0b-888e-7c2d9930e242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239288709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2239288709
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/162.edn_alert.329535471
Short name T139
Test name
Test status
Simulation time 27129551 ps
CPU time 1.31 seconds
Started Aug 03 05:52:11 PM PDT 24
Finished Aug 03 05:52:12 PM PDT 24
Peak memory 219912 kb
Host smart-57ae1713-5807-4dbd-921c-2cc2fc27e2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329535471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.329535471
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/23.edn_disable.1609766839
Short name T116
Test name
Test status
Simulation time 21568976 ps
CPU time 0.85 seconds
Started Aug 03 05:49:03 PM PDT 24
Finished Aug 03 05:49:04 PM PDT 24
Peak memory 216152 kb
Host smart-00dd848e-19ae-4705-980e-b864cdc82589
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609766839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1609766839
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/32.edn_intr.3055074283
Short name T45
Test name
Test status
Simulation time 38692860 ps
CPU time 0.99 seconds
Started Aug 03 05:49:36 PM PDT 24
Finished Aug 03 05:49:37 PM PDT 24
Peak memory 223972 kb
Host smart-f82b357e-7e53-4438-8153-c77a22bf3d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055074283 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3055074283
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3122413576
Short name T875
Test name
Test status
Simulation time 72660350 ps
CPU time 0.95 seconds
Started Aug 03 05:46:28 PM PDT 24
Finished Aug 03 05:46:29 PM PDT 24
Peak memory 216928 kb
Host smart-5790874a-4b3a-42ec-be25-7e8ee3a8abec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122413576 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3122413576
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.173686706
Short name T797
Test name
Test status
Simulation time 46405601 ps
CPU time 1.18 seconds
Started Aug 03 05:47:59 PM PDT 24
Finished Aug 03 05:48:01 PM PDT 24
Peak memory 216960 kb
Host smart-ad3e3edc-9a12-49d2-8444-bf32218fa9af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173686706 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.173686706
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/102.edn_alert.1409276678
Short name T174
Test name
Test status
Simulation time 30327388 ps
CPU time 1.3 seconds
Started Aug 03 05:51:37 PM PDT 24
Finished Aug 03 05:51:38 PM PDT 24
Peak memory 219720 kb
Host smart-9b6b4131-3f28-457e-82e9-09fab97701c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409276678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1409276678
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.1387769338
Short name T114
Test name
Test status
Simulation time 37002919 ps
CPU time 0.89 seconds
Started Aug 03 05:48:05 PM PDT 24
Finished Aug 03 05:48:06 PM PDT 24
Peak memory 216148 kb
Host smart-e35e6ede-6672-41fc-bf9e-c86c909d3e76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387769338 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1387769338
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/116.edn_alert.114514337
Short name T582
Test name
Test status
Simulation time 49637182 ps
CPU time 1.1 seconds
Started Aug 03 05:51:51 PM PDT 24
Finished Aug 03 05:51:52 PM PDT 24
Peak memory 219504 kb
Host smart-c3a4ea2e-0b75-4dae-b69d-c9aa21cb6a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114514337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.114514337
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1707634974
Short name T18
Test name
Test status
Simulation time 34430810 ps
CPU time 1.29 seconds
Started Aug 03 05:48:06 PM PDT 24
Finished Aug 03 05:48:07 PM PDT 24
Peak memory 216972 kb
Host smart-f06b2216-9f23-4353-8170-f351d68abec3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707634974 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1707634974
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/128.edn_alert.2819210885
Short name T783
Test name
Test status
Simulation time 22655378 ps
CPU time 1.17 seconds
Started Aug 03 05:51:53 PM PDT 24
Finished Aug 03 05:51:54 PM PDT 24
Peak memory 220896 kb
Host smart-31279eda-bb69-4c38-a752-7442587882fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819210885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2819210885
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/140.edn_alert.651394400
Short name T168
Test name
Test status
Simulation time 60490159 ps
CPU time 1.09 seconds
Started Aug 03 05:52:01 PM PDT 24
Finished Aug 03 05:52:02 PM PDT 24
Peak memory 219856 kb
Host smart-2ea5c1b3-0c0c-4db7-8031-eb6eb8cf188e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651394400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.651394400
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable.1411158672
Short name T118
Test name
Test status
Simulation time 11750219 ps
CPU time 0.91 seconds
Started Aug 03 05:48:29 PM PDT 24
Finished Aug 03 05:48:30 PM PDT 24
Peak memory 216420 kb
Host smart-9df60379-f712-49a8-8ce4-2513e1e75554
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411158672 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1411158672
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable.2257514007
Short name T105
Test name
Test status
Simulation time 33120224 ps
CPU time 0.88 seconds
Started Aug 03 05:48:41 PM PDT 24
Finished Aug 03 05:48:42 PM PDT 24
Peak memory 216224 kb
Host smart-71e6dc39-0fd5-4900-a408-5e5ced833dc9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257514007 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2257514007
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable.790241577
Short name T96
Test name
Test status
Simulation time 11359332 ps
CPU time 0.9 seconds
Started Aug 03 05:48:56 PM PDT 24
Finished Aug 03 05:48:57 PM PDT 24
Peak memory 216212 kb
Host smart-38ec574d-6907-4f48-a017-da9927ebb2e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790241577 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.790241577
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable.241033023
Short name T120
Test name
Test status
Simulation time 55821180 ps
CPU time 0.85 seconds
Started Aug 03 05:49:14 PM PDT 24
Finished Aug 03 05:49:15 PM PDT 24
Peak memory 216320 kb
Host smart-7d59342b-abbd-488e-8e84-55042a4c937d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241033023 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.241033023
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable.2037916386
Short name T202
Test name
Test status
Simulation time 16862925 ps
CPU time 0.84 seconds
Started Aug 03 05:49:23 PM PDT 24
Finished Aug 03 05:49:24 PM PDT 24
Peak memory 216180 kb
Host smart-39454e6b-819e-498e-9c30-fbdc637d214b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037916386 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2037916386
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3507130479
Short name T99
Test name
Test status
Simulation time 51814906 ps
CPU time 1.16 seconds
Started Aug 03 05:50:01 PM PDT 24
Finished Aug 03 05:50:02 PM PDT 24
Peak memory 216744 kb
Host smart-52322858-f97c-4c9a-9f81-616388529745
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507130479 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3507130479
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2888286557
Short name T215
Test name
Test status
Simulation time 23567407 ps
CPU time 0.9 seconds
Started Aug 03 05:50:13 PM PDT 24
Finished Aug 03 05:50:14 PM PDT 24
Peak memory 218456 kb
Host smart-20c018dd-d909-4ac9-b633-74053b8de509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888286557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2888286557
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/49.edn_err.3298185735
Short name T206
Test name
Test status
Simulation time 28797172 ps
CPU time 0.83 seconds
Started Aug 03 05:50:40 PM PDT 24
Finished Aug 03 05:50:41 PM PDT 24
Peak memory 218280 kb
Host smart-a2e5a7f0-d9e9-443b-a60a-40ab6952d835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298185735 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3298185735
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/219.edn_genbits.1525608444
Short name T320
Test name
Test status
Simulation time 93371951 ps
CPU time 1.28 seconds
Started Aug 03 05:52:39 PM PDT 24
Finished Aug 03 05:52:40 PM PDT 24
Peak memory 218588 kb
Host smart-9ebe2ba3-474f-4de1-924b-abae13cbb3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525608444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1525608444
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_alert_test.4135536381
Short name T43
Test name
Test status
Simulation time 24196741 ps
CPU time 0.9 seconds
Started Aug 03 05:46:43 PM PDT 24
Finished Aug 03 05:46:44 PM PDT 24
Peak memory 206712 kb
Host smart-b747df41-7e38-4bc3-a4f2-0c553e13de84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135536381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.4135536381
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/173.edn_genbits.1457992917
Short name T76
Test name
Test status
Simulation time 215926620 ps
CPU time 1.24 seconds
Started Aug 03 05:52:14 PM PDT 24
Finished Aug 03 05:52:15 PM PDT 24
Peak memory 217220 kb
Host smart-03bf3f56-0d4e-4996-90cd-ea370c62951a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457992917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1457992917
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3705449080
Short name T58
Test name
Test status
Simulation time 103646303 ps
CPU time 1.02 seconds
Started Aug 03 05:52:43 PM PDT 24
Finished Aug 03 05:52:44 PM PDT 24
Peak memory 217264 kb
Host smart-801673e9-90ae-49ad-a356-ea4618090535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705449080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3705449080
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1901737438
Short name T288
Test name
Test status
Simulation time 104552247 ps
CPU time 2.4 seconds
Started Aug 03 04:36:57 PM PDT 24
Finished Aug 03 04:37:00 PM PDT 24
Peak memory 206668 kb
Host smart-81c5aa87-0a6d-4b89-8453-256944b9ea5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901737438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1901737438
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3152427160
Short name T304
Test name
Test status
Simulation time 48945860 ps
CPU time 1.15 seconds
Started Aug 03 05:51:32 PM PDT 24
Finished Aug 03 05:51:34 PM PDT 24
Peak memory 217404 kb
Host smart-d462a810-a538-4e3d-a2a4-48622c331278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152427160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3152427160
Directory /workspace/99.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3655885003
Short name T95
Test name
Test status
Simulation time 95313820 ps
CPU time 0.81 seconds
Started Aug 03 05:49:59 PM PDT 24
Finished Aug 03 05:50:00 PM PDT 24
Peak memory 215540 kb
Host smart-7886c7d3-0665-486a-a4e4-8c748a60059d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655885003 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3655885003
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/71.edn_alert.903793154
Short name T145
Test name
Test status
Simulation time 37014498 ps
CPU time 1.14 seconds
Started Aug 03 05:51:06 PM PDT 24
Finished Aug 03 05:51:07 PM PDT 24
Peak memory 218536 kb
Host smart-363e8ee4-f92c-4102-94fe-28b5e92d200e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903793154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.903793154
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3439238917
Short name T268
Test name
Test status
Simulation time 25377689 ps
CPU time 0.95 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 206572 kb
Host smart-5c083d8d-bd03-4825-af66-738649e87bba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439238917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3439238917
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2592200947
Short name T257
Test name
Test status
Simulation time 11731339 ps
CPU time 0.9 seconds
Started Aug 03 04:36:52 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 206392 kb
Host smart-1ea80f7d-a4e9-43db-baa6-699886253343
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592200947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2592200947
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/default/106.edn_genbits.3200932545
Short name T312
Test name
Test status
Simulation time 39599753 ps
CPU time 1.58 seconds
Started Aug 03 05:51:36 PM PDT 24
Finished Aug 03 05:51:37 PM PDT 24
Peak memory 218544 kb
Host smart-174a8949-149f-4f07-b45d-6f8d62650308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200932545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3200932545
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.3474282550
Short name T306
Test name
Test status
Simulation time 38777810 ps
CPU time 1.22 seconds
Started Aug 03 05:51:43 PM PDT 24
Finished Aug 03 05:51:44 PM PDT 24
Peak memory 218568 kb
Host smart-e7038583-3358-43d5-92c2-4cea8cd2f85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474282550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3474282550
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/130.edn_genbits.1724052030
Short name T699
Test name
Test status
Simulation time 101290760 ps
CPU time 1.18 seconds
Started Aug 03 05:51:55 PM PDT 24
Finished Aug 03 05:51:56 PM PDT 24
Peak memory 217404 kb
Host smart-5e5ecf9f-06bc-4cbc-8f1e-887f31dfa099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724052030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1724052030
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.3434126560
Short name T316
Test name
Test status
Simulation time 33011623 ps
CPU time 1.37 seconds
Started Aug 03 05:52:08 PM PDT 24
Finished Aug 03 05:52:09 PM PDT 24
Peak memory 219856 kb
Host smart-7b21e2b4-22f7-4b94-a5f0-5b152d0bf589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434126560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3434126560
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3720218368
Short name T324
Test name
Test status
Simulation time 82827484 ps
CPU time 1.35 seconds
Started Aug 03 05:52:35 PM PDT 24
Finished Aug 03 05:52:37 PM PDT 24
Peak memory 218764 kb
Host smart-699024df-c68e-4e98-a922-45f38e055b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720218368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3720218368
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.319328444
Short name T314
Test name
Test status
Simulation time 42388524 ps
CPU time 1.69 seconds
Started Aug 03 05:52:49 PM PDT 24
Finished Aug 03 05:52:51 PM PDT 24
Peak memory 218584 kb
Host smart-f4b19717-ffe7-44fe-9e73-408f256d6794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319328444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.319328444
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3409628557
Short name T66
Test name
Test status
Simulation time 89361527 ps
CPU time 1.5 seconds
Started Aug 03 05:52:53 PM PDT 24
Finished Aug 03 05:52:54 PM PDT 24
Peak memory 218888 kb
Host smart-871ea865-cbad-4e8f-8f83-b8a8b8d5c626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409628557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3409628557
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1937258494
Short name T308
Test name
Test status
Simulation time 27589824 ps
CPU time 1.29 seconds
Started Aug 03 05:52:58 PM PDT 24
Finished Aug 03 05:52:59 PM PDT 24
Peak memory 218768 kb
Host smart-4fb8d35e-4b86-40ad-997c-4ea1bf093ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937258494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1937258494
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1798441437
Short name T94
Test name
Test status
Simulation time 30126598 ps
CPU time 0.9 seconds
Started Aug 03 05:48:11 PM PDT 24
Finished Aug 03 05:48:12 PM PDT 24
Peak memory 215800 kb
Host smart-7be00e6d-1747-40d7-bdd7-1bdda79dc6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798441437 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1798441437
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/22.edn_err.623256162
Short name T6
Test name
Test status
Simulation time 114219465 ps
CPU time 1.01 seconds
Started Aug 03 05:48:58 PM PDT 24
Finished Aug 03 05:48:59 PM PDT 24
Peak memory 218400 kb
Host smart-f483e336-08d2-46e4-87fa-14aff4ea5c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623256162 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.623256162
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3041677926
Short name T259
Test name
Test status
Simulation time 92670767 ps
CPU time 1.13 seconds
Started Aug 03 04:36:54 PM PDT 24
Finished Aug 03 04:36:55 PM PDT 24
Peak memory 206364 kb
Host smart-984c7a0c-69fc-478b-b1b2-675b27193a33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041677926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3041677926
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2257622620
Short name T1015
Test name
Test status
Simulation time 210468556 ps
CPU time 2.08 seconds
Started Aug 03 04:36:54 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 206380 kb
Host smart-555ebc62-05bc-43d9-9799-20e49c2dc351
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257622620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2257622620
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2516058793
Short name T1115
Test name
Test status
Simulation time 24691469 ps
CPU time 0.96 seconds
Started Aug 03 04:36:42 PM PDT 24
Finished Aug 03 04:36:44 PM PDT 24
Peak memory 206572 kb
Host smart-a632ed61-8283-4992-92c1-8bcbd1cf3ac8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516058793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2516058793
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1985622791
Short name T1088
Test name
Test status
Simulation time 137215986 ps
CPU time 1.54 seconds
Started Aug 03 04:36:51 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 215072 kb
Host smart-9390cfb0-d734-4c37-bd88-af6bb616048f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985622791 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1985622791
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3410597601
Short name T1090
Test name
Test status
Simulation time 33076911 ps
CPU time 0.79 seconds
Started Aug 03 04:36:48 PM PDT 24
Finished Aug 03 04:36:49 PM PDT 24
Peak memory 206400 kb
Host smart-d44966b3-e2d4-4a50-88d5-a621b0ca8094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410597601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3410597601
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2497564819
Short name T1119
Test name
Test status
Simulation time 54157601 ps
CPU time 1.29 seconds
Started Aug 03 04:36:57 PM PDT 24
Finished Aug 03 04:36:58 PM PDT 24
Peak memory 206780 kb
Host smart-4710deac-ace1-4229-94d3-7cdf302d6f54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497564819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2497564819
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2809000801
Short name T1036
Test name
Test status
Simulation time 73734331 ps
CPU time 2.55 seconds
Started Aug 03 04:36:44 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 214872 kb
Host smart-1abeb610-887b-4bf9-99d6-a9fae9c678a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809000801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2809000801
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3464719161
Short name T1122
Test name
Test status
Simulation time 43479949 ps
CPU time 1.17 seconds
Started Aug 03 04:36:52 PM PDT 24
Finished Aug 03 04:36:54 PM PDT 24
Peak memory 206540 kb
Host smart-c01e9417-6527-42ce-9e1e-95869a438324
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464719161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3464719161
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3579118215
Short name T1049
Test name
Test status
Simulation time 548491230 ps
CPU time 3.89 seconds
Started Aug 03 04:36:46 PM PDT 24
Finished Aug 03 04:36:50 PM PDT 24
Peak memory 206380 kb
Host smart-4f7f67dc-ba06-43cc-b729-234e36b951e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579118215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3579118215
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2153836570
Short name T258
Test name
Test status
Simulation time 15388934 ps
CPU time 0.92 seconds
Started Aug 03 04:36:46 PM PDT 24
Finished Aug 03 04:36:47 PM PDT 24
Peak memory 206588 kb
Host smart-6658be44-e084-4281-84ef-99d4a3e3c648
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153836570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2153836570
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4103704794
Short name T1077
Test name
Test status
Simulation time 53013432 ps
CPU time 1.64 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:47 PM PDT 24
Peak memory 215052 kb
Host smart-fd2e9cb3-cd0f-4ad6-9b87-444c43774d03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103704794 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.4103704794
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.851827463
Short name T1041
Test name
Test status
Simulation time 17147368 ps
CPU time 0.83 seconds
Started Aug 03 04:36:52 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 206460 kb
Host smart-8c8d9d8e-71fa-4cea-8817-91aed5f187c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851827463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.851827463
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.550834157
Short name T1070
Test name
Test status
Simulation time 19276585 ps
CPU time 0.94 seconds
Started Aug 03 04:36:51 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 206392 kb
Host smart-76fd6e14-8c0e-4dc1-83c8-1d1999d00eea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550834157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.550834157
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2295769039
Short name T1108
Test name
Test status
Simulation time 34928218 ps
CPU time 1.05 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:36:59 PM PDT 24
Peak memory 206620 kb
Host smart-156020ce-df0f-4293-9c06-c31b7b8708f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295769039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2295769039
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1730048649
Short name T1025
Test name
Test status
Simulation time 64130100 ps
CPU time 2.51 seconds
Started Aug 03 04:36:46 PM PDT 24
Finished Aug 03 04:36:49 PM PDT 24
Peak memory 214968 kb
Host smart-ac65c7ef-6377-4198-9526-531f97dec898
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730048649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1730048649
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3619563560
Short name T1064
Test name
Test status
Simulation time 74446559 ps
CPU time 1.94 seconds
Started Aug 03 04:36:52 PM PDT 24
Finished Aug 03 04:36:54 PM PDT 24
Peak memory 206760 kb
Host smart-270159a5-3824-4c50-b3c6-3886c8a19f05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619563560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3619563560
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3583674529
Short name T1048
Test name
Test status
Simulation time 98813651 ps
CPU time 1.42 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:36:59 PM PDT 24
Peak memory 223140 kb
Host smart-b5d59047-2060-48cf-8e60-ddd617ea06e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583674529 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3583674529
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1999344392
Short name T1113
Test name
Test status
Simulation time 16536296 ps
CPU time 0.98 seconds
Started Aug 03 04:36:52 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 206472 kb
Host smart-d4a58b40-9268-4031-9a5d-f943cc5dc774
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999344392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1999344392
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1961002927
Short name T997
Test name
Test status
Simulation time 13384959 ps
CPU time 0.84 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 206520 kb
Host smart-d1cfd6be-e58c-49ee-96bb-d2c07b052a76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961002927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1961002927
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.119847076
Short name T1057
Test name
Test status
Simulation time 29741200 ps
CPU time 1.01 seconds
Started Aug 03 04:36:52 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 206688 kb
Host smart-cd2d7685-a6d4-4018-9372-10389664b71e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119847076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.119847076
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1199334789
Short name T994
Test name
Test status
Simulation time 222572252 ps
CPU time 3.45 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:59 PM PDT 24
Peak memory 214904 kb
Host smart-4c3683bc-a290-4c8e-970b-e9cc7a8394b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199334789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1199334789
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.187528734
Short name T285
Test name
Test status
Simulation time 143692201 ps
CPU time 1.42 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 206700 kb
Host smart-c688289f-955a-4d26-879a-517ae6211e76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187528734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.187528734
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3800675856
Short name T1080
Test name
Test status
Simulation time 20615772 ps
CPU time 1.39 seconds
Started Aug 03 04:36:48 PM PDT 24
Finished Aug 03 04:36:50 PM PDT 24
Peak memory 214912 kb
Host smart-84cf11be-eb44-4417-9cdf-64e7a157dcd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800675856 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3800675856
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1074425657
Short name T1063
Test name
Test status
Simulation time 15527264 ps
CPU time 0.9 seconds
Started Aug 03 04:36:52 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 206600 kb
Host smart-54479771-55fb-4676-829c-39b2511d04e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074425657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1074425657
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2539948324
Short name T1071
Test name
Test status
Simulation time 34596718 ps
CPU time 1.02 seconds
Started Aug 03 04:36:56 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 206712 kb
Host smart-5a1ac86d-773a-4840-8610-8b5bbc521166
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539948324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2539948324
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.483006534
Short name T1003
Test name
Test status
Simulation time 122971140 ps
CPU time 2.62 seconds
Started Aug 03 04:37:00 PM PDT 24
Finished Aug 03 04:37:02 PM PDT 24
Peak memory 214988 kb
Host smart-f72dc1b2-b25b-41b0-892c-a8308e866438
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483006534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.483006534
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.454141882
Short name T284
Test name
Test status
Simulation time 44748031 ps
CPU time 1.51 seconds
Started Aug 03 04:36:59 PM PDT 24
Finished Aug 03 04:37:00 PM PDT 24
Peak memory 214800 kb
Host smart-9f9bdff3-6ed7-4624-ace3-b0737c4394ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454141882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.454141882
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4024249488
Short name T1010
Test name
Test status
Simulation time 39978083 ps
CPU time 1.21 seconds
Started Aug 03 04:37:01 PM PDT 24
Finished Aug 03 04:37:02 PM PDT 24
Peak memory 217260 kb
Host smart-849135a7-1155-48d3-b864-f1a1caa73ca9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024249488 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.4024249488
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.4003015487
Short name T998
Test name
Test status
Simulation time 80767919 ps
CPU time 0.9 seconds
Started Aug 03 04:36:56 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 206192 kb
Host smart-63fad2dd-b7ec-44c8-a695-8e43506a58cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003015487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.4003015487
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3770948091
Short name T1037
Test name
Test status
Simulation time 32496114 ps
CPU time 0.77 seconds
Started Aug 03 04:36:51 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 206404 kb
Host smart-6592a88d-8aaa-4755-b3af-f6065f8eae5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770948091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3770948091
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2098520416
Short name T1047
Test name
Test status
Simulation time 137099589 ps
CPU time 0.98 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 206756 kb
Host smart-2d693bfa-c31e-4c89-90be-92d5e00d011a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098520416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2098520416
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.4127225645
Short name T1038
Test name
Test status
Simulation time 72963347 ps
CPU time 2.57 seconds
Started Aug 03 04:36:52 PM PDT 24
Finished Aug 03 04:36:55 PM PDT 24
Peak memory 215060 kb
Host smart-7d080587-e544-499e-a5b3-711d0bac8336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127225645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.4127225645
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.450756053
Short name T282
Test name
Test status
Simulation time 250791964 ps
CPU time 3.92 seconds
Started Aug 03 04:36:44 PM PDT 24
Finished Aug 03 04:36:49 PM PDT 24
Peak memory 214744 kb
Host smart-bf297feb-b117-4cd1-a18a-f911bd3d2983
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450756053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.450756053
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2775098797
Short name T1019
Test name
Test status
Simulation time 87085705 ps
CPU time 1.38 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:37:00 PM PDT 24
Peak memory 214856 kb
Host smart-980fafb3-6c44-42da-bd94-c40f71920738
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775098797 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2775098797
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3463389624
Short name T1079
Test name
Test status
Simulation time 97639897 ps
CPU time 0.92 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:56 PM PDT 24
Peak memory 206544 kb
Host smart-8f5b3faa-93d9-4635-85e8-117a491bfe7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463389624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3463389624
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1073819285
Short name T1109
Test name
Test status
Simulation time 18457088 ps
CPU time 0.93 seconds
Started Aug 03 04:36:51 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 206596 kb
Host smart-6a2b2fbe-1bd6-4e08-81ae-bd4800544bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073819285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1073819285
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3852364055
Short name T1035
Test name
Test status
Simulation time 78792111 ps
CPU time 1.55 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 206740 kb
Host smart-109888f0-7faa-4fc8-9998-6050bb801cb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852364055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3852364055
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1194192065
Short name T1061
Test name
Test status
Simulation time 86422735 ps
CPU time 1.59 seconds
Started Aug 03 04:36:57 PM PDT 24
Finished Aug 03 04:37:04 PM PDT 24
Peak memory 223136 kb
Host smart-13248719-e2cb-401c-b3e1-19825dde7087
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194192065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1194192065
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.844114191
Short name T1066
Test name
Test status
Simulation time 33972679 ps
CPU time 1.03 seconds
Started Aug 03 04:36:59 PM PDT 24
Finished Aug 03 04:37:00 PM PDT 24
Peak memory 214816 kb
Host smart-05d41b5b-d91e-48a2-af56-790af46c0412
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844114191 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.844114191
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3088995233
Short name T1117
Test name
Test status
Simulation time 22120250 ps
CPU time 0.87 seconds
Started Aug 03 04:36:57 PM PDT 24
Finished Aug 03 04:36:58 PM PDT 24
Peak memory 206592 kb
Host smart-c3f65443-6f88-4526-af6e-bf61410987eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088995233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3088995233
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.443456036
Short name T1028
Test name
Test status
Simulation time 99679547 ps
CPU time 0.92 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:56 PM PDT 24
Peak memory 206468 kb
Host smart-e4a88215-d958-46ce-9082-96c5a53a67d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443456036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.443456036
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3487023823
Short name T1112
Test name
Test status
Simulation time 18094171 ps
CPU time 0.96 seconds
Started Aug 03 04:36:54 PM PDT 24
Finished Aug 03 04:36:55 PM PDT 24
Peak memory 206708 kb
Host smart-a2174a56-9db4-4aec-83ea-3f66981bcaac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487023823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3487023823
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2562515229
Short name T1110
Test name
Test status
Simulation time 30182085 ps
CPU time 1.94 seconds
Started Aug 03 04:37:00 PM PDT 24
Finished Aug 03 04:37:02 PM PDT 24
Peak memory 214884 kb
Host smart-921ee86c-f0f6-49b2-ac61-f77b6242271f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562515229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2562515229
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.238154081
Short name T223
Test name
Test status
Simulation time 113345212 ps
CPU time 1.89 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 214864 kb
Host smart-ea52e1bd-3a5b-44cd-9b52-253c2fc6b9f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238154081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.238154081
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1442010153
Short name T1044
Test name
Test status
Simulation time 27011283 ps
CPU time 1.45 seconds
Started Aug 03 04:36:56 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 215132 kb
Host smart-1a28cecd-9e2f-47b6-9dc2-a627e272062a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442010153 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1442010153
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.4140564157
Short name T262
Test name
Test status
Simulation time 40893672 ps
CPU time 0.79 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:37:04 PM PDT 24
Peak memory 206400 kb
Host smart-b03f68a1-3763-4ec3-8f61-acdad90b4347
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140564157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.4140564157
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.4247927406
Short name T1087
Test name
Test status
Simulation time 15363424 ps
CPU time 0.94 seconds
Started Aug 03 04:37:01 PM PDT 24
Finished Aug 03 04:37:02 PM PDT 24
Peak memory 206504 kb
Host smart-01807085-833f-4e41-b001-3b8e095e9644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247927406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.4247927406
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.120432548
Short name T269
Test name
Test status
Simulation time 117218755 ps
CPU time 1.33 seconds
Started Aug 03 04:36:56 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 206640 kb
Host smart-5dfff401-93c5-4148-b1a1-1d1b08405ead
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120432548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.120432548
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.4205322203
Short name T1001
Test name
Test status
Simulation time 436399301 ps
CPU time 3.92 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:37:02 PM PDT 24
Peak memory 214940 kb
Host smart-f8561f78-adb8-4551-8141-bd6f5ff89a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205322203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.4205322203
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2873087997
Short name T1091
Test name
Test status
Simulation time 141909404 ps
CPU time 3.15 seconds
Started Aug 03 04:37:02 PM PDT 24
Finished Aug 03 04:37:06 PM PDT 24
Peak memory 206776 kb
Host smart-837152ed-06b7-4ddc-bb06-420602980391
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873087997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2873087997
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3736873412
Short name T1114
Test name
Test status
Simulation time 28942403 ps
CPU time 0.99 seconds
Started Aug 03 04:36:57 PM PDT 24
Finished Aug 03 04:37:03 PM PDT 24
Peak memory 216196 kb
Host smart-7ef8a7af-82fe-4589-adb3-66ea54f5d020
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736873412 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3736873412
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.4292254629
Short name T270
Test name
Test status
Simulation time 13108027 ps
CPU time 0.91 seconds
Started Aug 03 04:37:01 PM PDT 24
Finished Aug 03 04:37:02 PM PDT 24
Peak memory 206472 kb
Host smart-1db520ca-1b6d-4601-84d3-a78b20879cd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292254629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.4292254629
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3089049822
Short name T995
Test name
Test status
Simulation time 34246204 ps
CPU time 0.87 seconds
Started Aug 03 04:36:57 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 206472 kb
Host smart-7a8f6073-de80-475b-8ad3-d91edc68ba81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089049822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3089049822
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3067016820
Short name T1123
Test name
Test status
Simulation time 45872824 ps
CPU time 1.46 seconds
Started Aug 03 04:36:53 PM PDT 24
Finished Aug 03 04:36:54 PM PDT 24
Peak memory 206708 kb
Host smart-59b09e23-d188-408c-a796-ebfcee6dd9be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067016820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3067016820
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2077901932
Short name T1030
Test name
Test status
Simulation time 59829767 ps
CPU time 2.42 seconds
Started Aug 03 04:37:00 PM PDT 24
Finished Aug 03 04:37:03 PM PDT 24
Peak memory 215040 kb
Host smart-6ab916e8-7b73-4b19-a4a2-7321085bf7c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077901932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2077901932
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2572639248
Short name T222
Test name
Test status
Simulation time 104319293 ps
CPU time 2.25 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 206804 kb
Host smart-540293c9-d538-4113-8e1f-9716c2384595
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572639248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2572639248
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2308603982
Short name T1086
Test name
Test status
Simulation time 72249168 ps
CPU time 1.24 seconds
Started Aug 03 04:37:03 PM PDT 24
Finished Aug 03 04:37:05 PM PDT 24
Peak memory 214948 kb
Host smart-1f5bd7ef-38c5-4342-852b-008b4f3b86c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308603982 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2308603982
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1397802369
Short name T1095
Test name
Test status
Simulation time 39233955 ps
CPU time 0.81 seconds
Started Aug 03 04:36:52 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 206396 kb
Host smart-d97543a3-a2eb-47ec-804b-af95e5fe5747
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397802369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1397802369
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.718952535
Short name T1033
Test name
Test status
Simulation time 15123267 ps
CPU time 0.88 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:55 PM PDT 24
Peak memory 206484 kb
Host smart-963f9303-5702-4967-94d3-7112794a7cf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718952535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.718952535
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2981521932
Short name T1075
Test name
Test status
Simulation time 308907307 ps
CPU time 1.26 seconds
Started Aug 03 04:36:56 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 206596 kb
Host smart-139aa9c9-73d4-4389-899e-293eda39a692
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981521932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2981521932
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3589191228
Short name T1111
Test name
Test status
Simulation time 84059293 ps
CPU time 3.02 seconds
Started Aug 03 04:37:02 PM PDT 24
Finished Aug 03 04:37:05 PM PDT 24
Peak memory 223176 kb
Host smart-9ae97d24-bb27-4c2e-adf3-3001817c57de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589191228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3589191228
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2408490735
Short name T1051
Test name
Test status
Simulation time 195273057 ps
CPU time 2.53 seconds
Started Aug 03 04:36:59 PM PDT 24
Finished Aug 03 04:37:02 PM PDT 24
Peak memory 206592 kb
Host smart-1fd5892e-473d-42dd-8467-3c4a8373b31f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408490735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2408490735
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3840026654
Short name T993
Test name
Test status
Simulation time 84309546 ps
CPU time 1.15 seconds
Started Aug 03 04:37:09 PM PDT 24
Finished Aug 03 04:37:10 PM PDT 24
Peak memory 217188 kb
Host smart-25602e9c-678c-4f64-8c24-c02c77345581
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840026654 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3840026654
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3183530770
Short name T273
Test name
Test status
Simulation time 19968653 ps
CPU time 0.88 seconds
Started Aug 03 04:37:10 PM PDT 24
Finished Aug 03 04:37:11 PM PDT 24
Peak memory 206572 kb
Host smart-eb8d8af4-5d39-48d5-9276-87eb62dc9b78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183530770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3183530770
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.4155496297
Short name T1078
Test name
Test status
Simulation time 13188463 ps
CPU time 0.88 seconds
Started Aug 03 04:37:00 PM PDT 24
Finished Aug 03 04:37:01 PM PDT 24
Peak memory 206484 kb
Host smart-bfead887-a048-4f14-83e7-c4fbc97888d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155496297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.4155496297
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2472153326
Short name T266
Test name
Test status
Simulation time 36929677 ps
CPU time 1.02 seconds
Started Aug 03 04:36:57 PM PDT 24
Finished Aug 03 04:36:58 PM PDT 24
Peak memory 206788 kb
Host smart-e8080008-7ece-482c-ae92-9650f727e6f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472153326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2472153326
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2596727591
Short name T999
Test name
Test status
Simulation time 128720601 ps
CPU time 2.57 seconds
Started Aug 03 04:37:15 PM PDT 24
Finished Aug 03 04:37:17 PM PDT 24
Peak memory 214936 kb
Host smart-2dca5890-cea8-4065-992e-5ac0824e8382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596727591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2596727591
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1203238818
Short name T224
Test name
Test status
Simulation time 50867270 ps
CPU time 1.66 seconds
Started Aug 03 04:36:59 PM PDT 24
Finished Aug 03 04:37:01 PM PDT 24
Peak memory 214804 kb
Host smart-b6f8c57a-34e3-4a43-b95a-5641ed3bff4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203238818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1203238818
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.159952755
Short name T1045
Test name
Test status
Simulation time 31456338 ps
CPU time 1.41 seconds
Started Aug 03 04:37:02 PM PDT 24
Finished Aug 03 04:37:04 PM PDT 24
Peak memory 215072 kb
Host smart-06847874-5a5a-41d9-9580-8a714e75059d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159952755 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.159952755
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3373064755
Short name T265
Test name
Test status
Simulation time 49440168 ps
CPU time 0.87 seconds
Started Aug 03 04:37:00 PM PDT 24
Finished Aug 03 04:37:01 PM PDT 24
Peak memory 206440 kb
Host smart-a29b9237-3613-4af1-a83e-4cef90184e57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373064755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3373064755
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.732436148
Short name T1065
Test name
Test status
Simulation time 27435769 ps
CPU time 0.89 seconds
Started Aug 03 04:37:01 PM PDT 24
Finished Aug 03 04:37:02 PM PDT 24
Peak memory 206588 kb
Host smart-b91b0d8c-8aa0-40db-9055-990acbce0405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732436148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.732436148
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1981308277
Short name T254
Test name
Test status
Simulation time 28544899 ps
CPU time 1.27 seconds
Started Aug 03 04:36:53 PM PDT 24
Finished Aug 03 04:36:55 PM PDT 24
Peak memory 206764 kb
Host smart-e483b14f-3231-4aef-91c1-e6d6a2538e2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981308277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1981308277
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2506501486
Short name T1039
Test name
Test status
Simulation time 38014138 ps
CPU time 2.56 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:37:00 PM PDT 24
Peak memory 218792 kb
Host smart-27890e11-6567-467f-8f4b-6ac8b57a4482
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506501486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2506501486
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.492555843
Short name T287
Test name
Test status
Simulation time 87578082 ps
CPU time 1.56 seconds
Started Aug 03 04:37:01 PM PDT 24
Finished Aug 03 04:37:03 PM PDT 24
Peak memory 206696 kb
Host smart-3a16edff-4b93-4f3b-aeef-86616aba623a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492555843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.492555843
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.403025720
Short name T255
Test name
Test status
Simulation time 34637067 ps
CPU time 1.55 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 206680 kb
Host smart-c466a052-5268-4af5-9681-1cb81e0575ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403025720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.403025720
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3308896167
Short name T1014
Test name
Test status
Simulation time 544449835 ps
CPU time 3.98 seconds
Started Aug 03 04:36:47 PM PDT 24
Finished Aug 03 04:36:51 PM PDT 24
Peak memory 206460 kb
Host smart-d28bbdaf-7a76-4215-b300-5b95f4335cea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308896167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3308896167
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3676983111
Short name T263
Test name
Test status
Simulation time 66095030 ps
CPU time 1.02 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 206728 kb
Host smart-45233884-2899-430a-b9db-901c236e6291
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676983111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3676983111
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2352577164
Short name T1032
Test name
Test status
Simulation time 54185020 ps
CPU time 1.31 seconds
Started Aug 03 04:36:50 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 223152 kb
Host smart-4b070a4d-ee68-4da6-bf68-aa86e13b2a11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352577164 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2352577164
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1141620413
Short name T1020
Test name
Test status
Simulation time 12692425 ps
CPU time 0.87 seconds
Started Aug 03 04:36:46 PM PDT 24
Finished Aug 03 04:36:47 PM PDT 24
Peak memory 206484 kb
Host smart-0353ad4c-46da-4aba-8761-9f89d48b51a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141620413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1141620413
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1582197299
Short name T272
Test name
Test status
Simulation time 42648190 ps
CPU time 1.01 seconds
Started Aug 03 04:36:50 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 206576 kb
Host smart-890f11d0-d914-4667-8fec-b7da0517ed54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582197299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1582197299
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1507384276
Short name T1098
Test name
Test status
Simulation time 738232138 ps
CPU time 3.73 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:37:03 PM PDT 24
Peak memory 214848 kb
Host smart-0e1fa077-9260-4cbe-a1e4-8b3486f776c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507384276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1507384276
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3653755061
Short name T1068
Test name
Test status
Simulation time 202945957 ps
CPU time 1.67 seconds
Started Aug 03 04:36:51 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 206496 kb
Host smart-8416e5ca-312f-44fd-b103-02f99ded95e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653755061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3653755061
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3441422965
Short name T1058
Test name
Test status
Simulation time 19588257 ps
CPU time 0.83 seconds
Started Aug 03 04:36:59 PM PDT 24
Finished Aug 03 04:37:00 PM PDT 24
Peak memory 206604 kb
Host smart-147f25ff-653f-4dcf-a603-63de042990e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441422965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3441422965
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3348810748
Short name T1099
Test name
Test status
Simulation time 16621838 ps
CPU time 0.96 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:36:59 PM PDT 24
Peak memory 206588 kb
Host smart-5204ec2d-3ca0-4d02-969d-1d033808ea4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348810748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3348810748
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.362973127
Short name T1009
Test name
Test status
Simulation time 15579104 ps
CPU time 0.88 seconds
Started Aug 03 04:36:59 PM PDT 24
Finished Aug 03 04:37:00 PM PDT 24
Peak memory 206576 kb
Host smart-1d23b490-b3a9-48ba-98a5-dfb98ab3ef02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362973127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.362973127
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.628760272
Short name T1074
Test name
Test status
Simulation time 13627644 ps
CPU time 0.86 seconds
Started Aug 03 04:36:59 PM PDT 24
Finished Aug 03 04:37:00 PM PDT 24
Peak memory 206464 kb
Host smart-285e10cb-6fdf-4eb5-ae2d-8d74a7911eaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628760272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.628760272
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2187770279
Short name T1007
Test name
Test status
Simulation time 33319752 ps
CPU time 0.82 seconds
Started Aug 03 04:37:04 PM PDT 24
Finished Aug 03 04:37:05 PM PDT 24
Peak memory 206484 kb
Host smart-b4497203-60ea-4773-b0b3-a026cbfc97dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187770279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2187770279
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3686757078
Short name T1024
Test name
Test status
Simulation time 20305093 ps
CPU time 0.86 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:36:59 PM PDT 24
Peak memory 206524 kb
Host smart-b7305616-f82b-4c9c-8865-087ea5c92098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686757078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3686757078
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1502462246
Short name T1082
Test name
Test status
Simulation time 32492046 ps
CPU time 0.81 seconds
Started Aug 03 04:37:07 PM PDT 24
Finished Aug 03 04:37:08 PM PDT 24
Peak memory 206496 kb
Host smart-9ea5433c-101f-464d-ac0d-936e75d6e665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502462246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1502462246
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2784690187
Short name T1016
Test name
Test status
Simulation time 20017950 ps
CPU time 0.79 seconds
Started Aug 03 04:36:57 PM PDT 24
Finished Aug 03 04:36:58 PM PDT 24
Peak memory 206192 kb
Host smart-fe1f8234-d8c5-433e-a036-635070c99013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784690187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2784690187
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3657502462
Short name T1002
Test name
Test status
Simulation time 14120855 ps
CPU time 0.85 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:36:59 PM PDT 24
Peak memory 206592 kb
Host smart-d0db27ec-8e6a-41ff-b434-8e3617ae0f57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657502462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3657502462
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.728202006
Short name T1026
Test name
Test status
Simulation time 33509112 ps
CPU time 0.97 seconds
Started Aug 03 04:37:02 PM PDT 24
Finished Aug 03 04:37:04 PM PDT 24
Peak memory 206600 kb
Host smart-bf553b80-e85b-4cb6-b007-bd0a4d555122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728202006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.728202006
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2604514253
Short name T991
Test name
Test status
Simulation time 88523278 ps
CPU time 1.17 seconds
Started Aug 03 04:36:51 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 206552 kb
Host smart-d9797249-9b88-4ecf-8c8a-617a9996d6c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604514253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2604514253
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4000685417
Short name T264
Test name
Test status
Simulation time 63417821 ps
CPU time 2 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:37:00 PM PDT 24
Peak memory 206564 kb
Host smart-bac077b6-d925-4706-b98a-34e96e2189bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000685417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.4000685417
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2249101439
Short name T1081
Test name
Test status
Simulation time 34482588 ps
CPU time 0.89 seconds
Started Aug 03 04:36:49 PM PDT 24
Finished Aug 03 04:36:50 PM PDT 24
Peak memory 206484 kb
Host smart-37181c3a-7291-4835-bd45-d72e248ed865
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249101439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2249101439
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2061804422
Short name T1000
Test name
Test status
Simulation time 61903974 ps
CPU time 1 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:36:59 PM PDT 24
Peak memory 206772 kb
Host smart-3d6383e6-9764-4824-8191-d2863a11c0c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061804422 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2061804422
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.215363665
Short name T1017
Test name
Test status
Simulation time 52910153 ps
CPU time 0.89 seconds
Started Aug 03 04:36:48 PM PDT 24
Finished Aug 03 04:36:49 PM PDT 24
Peak memory 206588 kb
Host smart-b335e0d2-0f29-49ce-af73-2b12dcb8985a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215363665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.215363665
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2781927498
Short name T1120
Test name
Test status
Simulation time 12285459 ps
CPU time 0.83 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:36:59 PM PDT 24
Peak memory 206492 kb
Host smart-dc446947-aa07-4963-94aa-cc8459917dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781927498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2781927498
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.16944080
Short name T1073
Test name
Test status
Simulation time 109509750 ps
CPU time 1.31 seconds
Started Aug 03 04:36:54 PM PDT 24
Finished Aug 03 04:36:55 PM PDT 24
Peak memory 206696 kb
Host smart-6b9e898f-ea49-4b64-84dc-2a29c6a9e06d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16944080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outs
tanding.16944080
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3569680928
Short name T1018
Test name
Test status
Simulation time 62098880 ps
CPU time 2.47 seconds
Started Aug 03 04:36:46 PM PDT 24
Finished Aug 03 04:36:48 PM PDT 24
Peak memory 215060 kb
Host smart-f1538f59-1f8f-49e7-8ee2-d3cfc787f8cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569680928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3569680928
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.919505327
Short name T1060
Test name
Test status
Simulation time 161381396 ps
CPU time 2.48 seconds
Started Aug 03 04:36:50 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 206660 kb
Host smart-1cfcc8d9-03d9-4fc6-862e-bb45dd79cf0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919505327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.919505327
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.582382930
Short name T1124
Test name
Test status
Simulation time 17185145 ps
CPU time 0.91 seconds
Started Aug 03 04:37:05 PM PDT 24
Finished Aug 03 04:37:06 PM PDT 24
Peak memory 206428 kb
Host smart-8b6067d3-5450-4eff-abb9-28ba16ee3882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582382930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.582382930
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2786612358
Short name T1101
Test name
Test status
Simulation time 25103993 ps
CPU time 0.87 seconds
Started Aug 03 04:37:02 PM PDT 24
Finished Aug 03 04:37:03 PM PDT 24
Peak memory 206596 kb
Host smart-1ca1de86-3227-49fe-8853-666ee28b96b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786612358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2786612358
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2708066531
Short name T1023
Test name
Test status
Simulation time 20918040 ps
CPU time 0.87 seconds
Started Aug 03 04:37:02 PM PDT 24
Finished Aug 03 04:37:08 PM PDT 24
Peak memory 206596 kb
Host smart-32c7959d-06c5-43d6-99d5-a0adb9260dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708066531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2708066531
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3383690692
Short name T1085
Test name
Test status
Simulation time 26824626 ps
CPU time 0.87 seconds
Started Aug 03 04:37:05 PM PDT 24
Finished Aug 03 04:37:06 PM PDT 24
Peak memory 206576 kb
Host smart-e9583932-fada-4bf7-ad5e-e74203189852
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383690692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3383690692
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2524149852
Short name T1089
Test name
Test status
Simulation time 14466654 ps
CPU time 0.89 seconds
Started Aug 03 04:37:05 PM PDT 24
Finished Aug 03 04:37:06 PM PDT 24
Peak memory 206576 kb
Host smart-6dc0cb8f-5b4f-46aa-a0fd-45660a135559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524149852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2524149852
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2033060762
Short name T1021
Test name
Test status
Simulation time 11291641 ps
CPU time 0.84 seconds
Started Aug 03 04:37:05 PM PDT 24
Finished Aug 03 04:37:06 PM PDT 24
Peak memory 206592 kb
Host smart-aab9b2ef-0a6d-4e81-8484-bb690530481c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033060762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2033060762
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.4291162303
Short name T1069
Test name
Test status
Simulation time 153799363 ps
CPU time 0.86 seconds
Started Aug 03 04:37:00 PM PDT 24
Finished Aug 03 04:37:01 PM PDT 24
Peak memory 206580 kb
Host smart-4c241ef8-1f0f-4104-be9f-5322c050c063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291162303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.4291162303
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1028422369
Short name T1013
Test name
Test status
Simulation time 39249580 ps
CPU time 0.85 seconds
Started Aug 03 04:37:03 PM PDT 24
Finished Aug 03 04:37:04 PM PDT 24
Peak memory 206308 kb
Host smart-4098ea00-261e-40a5-8aa9-6d8fc1e05e9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028422369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1028422369
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.515502000
Short name T1008
Test name
Test status
Simulation time 17225723 ps
CPU time 0.8 seconds
Started Aug 03 04:37:02 PM PDT 24
Finished Aug 03 04:37:03 PM PDT 24
Peak memory 206412 kb
Host smart-d500454d-3681-49c1-acde-3e5ce35ee0c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515502000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.515502000
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2334576129
Short name T1031
Test name
Test status
Simulation time 12264084 ps
CPU time 0.9 seconds
Started Aug 03 04:37:00 PM PDT 24
Finished Aug 03 04:37:01 PM PDT 24
Peak memory 206432 kb
Host smart-1f2d7603-e9b8-45d6-9be3-c945b2f3de45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334576129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2334576129
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2540028331
Short name T1040
Test name
Test status
Simulation time 32402680 ps
CPU time 1.45 seconds
Started Aug 03 04:36:54 PM PDT 24
Finished Aug 03 04:36:56 PM PDT 24
Peak memory 206364 kb
Host smart-f55883bb-c8fc-4361-a876-5693f9179707
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540028331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2540028331
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3807758200
Short name T1059
Test name
Test status
Simulation time 36162754 ps
CPU time 1.98 seconds
Started Aug 03 04:36:51 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 206524 kb
Host smart-d1595e5d-1d6e-4d0b-a4ca-8c4702ad5f66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807758200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3807758200
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2674925411
Short name T260
Test name
Test status
Simulation time 34946620 ps
CPU time 0.99 seconds
Started Aug 03 04:36:49 PM PDT 24
Finished Aug 03 04:36:50 PM PDT 24
Peak memory 206428 kb
Host smart-47e889d5-700b-43ab-8a73-88a2fc5667ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674925411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2674925411
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1528316885
Short name T1103
Test name
Test status
Simulation time 107882925 ps
CPU time 1.16 seconds
Started Aug 03 04:36:48 PM PDT 24
Finished Aug 03 04:36:50 PM PDT 24
Peak memory 214880 kb
Host smart-a5319a8a-67ab-40c5-9c6b-37926144017b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528316885 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1528316885
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3789259855
Short name T1096
Test name
Test status
Simulation time 50075723 ps
CPU time 0.93 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 206576 kb
Host smart-ba489b5b-9e0e-4585-93a4-a34bb9bc85c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789259855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3789259855
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2218390128
Short name T1052
Test name
Test status
Simulation time 14205561 ps
CPU time 0.89 seconds
Started Aug 03 04:36:51 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 206488 kb
Host smart-f578a05e-3262-4a18-89f0-07c130f9432f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218390128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2218390128
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3278236725
Short name T1083
Test name
Test status
Simulation time 18387812 ps
CPU time 0.99 seconds
Started Aug 03 04:36:57 PM PDT 24
Finished Aug 03 04:36:58 PM PDT 24
Peak memory 206704 kb
Host smart-6a316a27-8547-4c74-b09a-0c5e302169a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278236725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3278236725
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.315967647
Short name T1022
Test name
Test status
Simulation time 418456537 ps
CPU time 2.61 seconds
Started Aug 03 04:36:50 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 215036 kb
Host smart-ba2231e4-64c8-44a1-8950-b19c88583983
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315967647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.315967647
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.362627334
Short name T1104
Test name
Test status
Simulation time 75036877 ps
CPU time 1.58 seconds
Started Aug 03 04:36:50 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 206772 kb
Host smart-d6b9e3e7-4a83-4512-93b1-02abd07970a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362627334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.362627334
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3620908611
Short name T1034
Test name
Test status
Simulation time 12124580 ps
CPU time 0.81 seconds
Started Aug 03 04:37:08 PM PDT 24
Finished Aug 03 04:37:09 PM PDT 24
Peak memory 206436 kb
Host smart-5a0a191a-5fdc-4d5e-b213-6010371189f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620908611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3620908611
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2369034502
Short name T1053
Test name
Test status
Simulation time 22378194 ps
CPU time 0.84 seconds
Started Aug 03 04:36:59 PM PDT 24
Finished Aug 03 04:37:09 PM PDT 24
Peak memory 206576 kb
Host smart-1a74a4ef-6a21-4d33-a24f-dfb90e939377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369034502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2369034502
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3208597093
Short name T1005
Test name
Test status
Simulation time 26257049 ps
CPU time 0.88 seconds
Started Aug 03 04:36:59 PM PDT 24
Finished Aug 03 04:37:00 PM PDT 24
Peak memory 206600 kb
Host smart-a593c746-edd1-44a3-855c-104eb5304c8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208597093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3208597093
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2189749536
Short name T1054
Test name
Test status
Simulation time 35619194 ps
CPU time 0.92 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:56 PM PDT 24
Peak memory 206604 kb
Host smart-481f94e8-664d-4fbe-b240-cbd25d9a8f0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189749536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2189749536
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.285161839
Short name T1006
Test name
Test status
Simulation time 15343507 ps
CPU time 0.97 seconds
Started Aug 03 04:37:02 PM PDT 24
Finished Aug 03 04:37:04 PM PDT 24
Peak memory 206596 kb
Host smart-38ad95f4-74b6-49cc-8f03-d3a96985ca3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285161839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.285161839
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.61099899
Short name T1093
Test name
Test status
Simulation time 14058218 ps
CPU time 0.85 seconds
Started Aug 03 04:37:01 PM PDT 24
Finished Aug 03 04:37:02 PM PDT 24
Peak memory 206508 kb
Host smart-3ee100f9-8af0-47e9-a5ec-617891feff77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61099899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.61099899
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2324626113
Short name T1011
Test name
Test status
Simulation time 13655956 ps
CPU time 0.89 seconds
Started Aug 03 04:36:52 PM PDT 24
Finished Aug 03 04:36:54 PM PDT 24
Peak memory 206588 kb
Host smart-efb09331-bd45-4d65-b3d4-e50651b25c4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324626113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2324626113
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2751669363
Short name T1062
Test name
Test status
Simulation time 15724020 ps
CPU time 0.89 seconds
Started Aug 03 04:36:57 PM PDT 24
Finished Aug 03 04:36:58 PM PDT 24
Peak memory 206580 kb
Host smart-2677c84b-632d-4263-9754-6856999b84cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751669363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2751669363
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3107589268
Short name T1042
Test name
Test status
Simulation time 14264633 ps
CPU time 0.87 seconds
Started Aug 03 04:37:04 PM PDT 24
Finished Aug 03 04:37:05 PM PDT 24
Peak memory 206496 kb
Host smart-267e8e16-8450-45f0-ad7c-a7f09412290c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107589268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3107589268
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3246359095
Short name T1029
Test name
Test status
Simulation time 29152954 ps
CPU time 0.78 seconds
Started Aug 03 04:37:00 PM PDT 24
Finished Aug 03 04:37:01 PM PDT 24
Peak memory 206384 kb
Host smart-c0ae13fd-ead2-4e35-bf4f-4204ce676a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246359095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3246359095
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.8766117
Short name T992
Test name
Test status
Simulation time 50070995 ps
CPU time 0.99 seconds
Started Aug 03 04:36:53 PM PDT 24
Finished Aug 03 04:36:54 PM PDT 24
Peak memory 206776 kb
Host smart-8e7dadcd-cf3e-46cd-bce6-99b308d7af81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8766117 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.8766117
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.752182959
Short name T267
Test name
Test status
Simulation time 15058631 ps
CPU time 0.97 seconds
Started Aug 03 04:36:54 PM PDT 24
Finished Aug 03 04:36:55 PM PDT 24
Peak memory 206456 kb
Host smart-6d017995-01e8-4c5e-801a-fefe798f7945
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752182959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.752182959
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.70967597
Short name T1106
Test name
Test status
Simulation time 51368185 ps
CPU time 0.82 seconds
Started Aug 03 04:36:57 PM PDT 24
Finished Aug 03 04:36:58 PM PDT 24
Peak memory 206496 kb
Host smart-8bfe6cd6-ebcf-45a1-b87c-db974b5126bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70967597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.70967597
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.563348590
Short name T1092
Test name
Test status
Simulation time 106854087 ps
CPU time 1.28 seconds
Started Aug 03 04:36:51 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 206680 kb
Host smart-fc7739f6-7002-40bc-a5c9-4a2bc113ea19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563348590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.563348590
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2272383069
Short name T996
Test name
Test status
Simulation time 304955361 ps
CPU time 3.68 seconds
Started Aug 03 04:36:45 PM PDT 24
Finished Aug 03 04:36:49 PM PDT 24
Peak memory 214960 kb
Host smart-ea7a5a73-f6e2-4c05-8ad0-4997dba4d205
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272383069 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2272383069
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1820841642
Short name T1072
Test name
Test status
Simulation time 217775899 ps
CPU time 1.41 seconds
Started Aug 03 04:36:54 PM PDT 24
Finished Aug 03 04:36:55 PM PDT 24
Peak memory 206756 kb
Host smart-4cee5633-f9a4-4a5d-b473-fb9f553dec12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820841642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1820841642
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.4070149445
Short name T1121
Test name
Test status
Simulation time 37394059 ps
CPU time 1.48 seconds
Started Aug 03 04:36:48 PM PDT 24
Finished Aug 03 04:36:50 PM PDT 24
Peak memory 218500 kb
Host smart-08581068-64ca-4db6-ad13-1984d323167c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070149445 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.4070149445
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1065896272
Short name T1116
Test name
Test status
Simulation time 28575969 ps
CPU time 0.87 seconds
Started Aug 03 04:36:49 PM PDT 24
Finished Aug 03 04:36:50 PM PDT 24
Peak memory 206432 kb
Host smart-0fba6c15-f5a2-4979-9fc9-a841a8e39ce5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065896272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1065896272
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3547301257
Short name T1004
Test name
Test status
Simulation time 26925607 ps
CPU time 0.83 seconds
Started Aug 03 04:36:49 PM PDT 24
Finished Aug 03 04:36:50 PM PDT 24
Peak memory 206256 kb
Host smart-b899a1d7-5332-450a-bcc2-cdd57d9dd86d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547301257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3547301257
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.853176122
Short name T271
Test name
Test status
Simulation time 93578506 ps
CPU time 0.91 seconds
Started Aug 03 04:36:56 PM PDT 24
Finished Aug 03 04:36:57 PM PDT 24
Peak memory 206684 kb
Host smart-56da40ef-3794-4b58-8966-4f030e89a43e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853176122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.853176122
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1770549989
Short name T1102
Test name
Test status
Simulation time 655282661 ps
CPU time 3.84 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:37:02 PM PDT 24
Peak memory 215044 kb
Host smart-d36b5c7f-9cbf-48c6-83cd-adaf43f9fdba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770549989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1770549989
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.548137088
Short name T1107
Test name
Test status
Simulation time 59849787 ps
CPU time 1.7 seconds
Started Aug 03 04:36:54 PM PDT 24
Finished Aug 03 04:36:56 PM PDT 24
Peak memory 214756 kb
Host smart-3ca53e7a-f2f6-49ef-8916-b5ba89cc1dd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548137088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.548137088
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1133863851
Short name T1094
Test name
Test status
Simulation time 51032540 ps
CPU time 1.23 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:56 PM PDT 24
Peak memory 217336 kb
Host smart-1bd8c483-0e82-4524-80f3-041a3e9bd0e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133863851 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1133863851
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1301005466
Short name T256
Test name
Test status
Simulation time 25657301 ps
CPU time 0.89 seconds
Started Aug 03 04:36:49 PM PDT 24
Finished Aug 03 04:36:50 PM PDT 24
Peak memory 206432 kb
Host smart-2e3d8a33-2f93-4570-b7d3-81a09a222805
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301005466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1301005466
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.4062306905
Short name T1012
Test name
Test status
Simulation time 48147471 ps
CPU time 0.85 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:36:59 PM PDT 24
Peak memory 206476 kb
Host smart-5b1b2a64-63df-4d26-81df-59f3be680dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062306905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.4062306905
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1543159344
Short name T1046
Test name
Test status
Simulation time 31010877 ps
CPU time 1.37 seconds
Started Aug 03 04:36:55 PM PDT 24
Finished Aug 03 04:36:56 PM PDT 24
Peak memory 206864 kb
Host smart-f9f65404-ca90-4d3c-9a5d-b7767894ce7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543159344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1543159344
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3435207864
Short name T1043
Test name
Test status
Simulation time 150145701 ps
CPU time 2.81 seconds
Started Aug 03 04:36:56 PM PDT 24
Finished Aug 03 04:36:59 PM PDT 24
Peak memory 214972 kb
Host smart-50114ba8-28b3-4ddf-aa7e-30ad8945a873
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435207864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3435207864
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3046391045
Short name T1125
Test name
Test status
Simulation time 90654646 ps
CPU time 1.5 seconds
Started Aug 03 04:36:47 PM PDT 24
Finished Aug 03 04:36:48 PM PDT 24
Peak memory 214788 kb
Host smart-598cced3-b149-4bb2-8647-0e1b22c510ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046391045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3046391045
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1580977174
Short name T1097
Test name
Test status
Simulation time 28349846 ps
CPU time 1.12 seconds
Started Aug 03 04:36:53 PM PDT 24
Finished Aug 03 04:36:54 PM PDT 24
Peak memory 214868 kb
Host smart-82525b93-9784-4d05-b101-a6a1366f3590
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580977174 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1580977174
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.4026381582
Short name T1056
Test name
Test status
Simulation time 14355389 ps
CPU time 0.93 seconds
Started Aug 03 04:36:57 PM PDT 24
Finished Aug 03 04:36:58 PM PDT 24
Peak memory 206456 kb
Host smart-4e17d5c7-ec8c-48a5-9a51-00c84294ae3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026381582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.4026381582
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.335590996
Short name T1027
Test name
Test status
Simulation time 24898083 ps
CPU time 0.89 seconds
Started Aug 03 04:36:59 PM PDT 24
Finished Aug 03 04:37:00 PM PDT 24
Peak memory 206592 kb
Host smart-a9aca9d5-527b-4ff4-8670-fc5880957711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335590996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.335590996
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3594127153
Short name T1105
Test name
Test status
Simulation time 36337610 ps
CPU time 1.42 seconds
Started Aug 03 04:36:46 PM PDT 24
Finished Aug 03 04:36:48 PM PDT 24
Peak memory 206696 kb
Host smart-70c66880-cc80-4d45-916d-40b9ea1b59f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594127153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3594127153
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.331376156
Short name T1076
Test name
Test status
Simulation time 28076144 ps
CPU time 1.88 seconds
Started Aug 03 04:36:53 PM PDT 24
Finished Aug 03 04:36:55 PM PDT 24
Peak memory 214980 kb
Host smart-d7f1c47d-5fce-4be2-b211-927e3429be75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331376156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.331376156
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1970759939
Short name T286
Test name
Test status
Simulation time 1498912218 ps
CPU time 2.75 seconds
Started Aug 03 04:36:59 PM PDT 24
Finished Aug 03 04:37:01 PM PDT 24
Peak memory 214860 kb
Host smart-7e72e0b3-a0f9-4db6-a092-911402230126
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970759939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1970759939
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2500675220
Short name T1055
Test name
Test status
Simulation time 302062731 ps
CPU time 1.54 seconds
Started Aug 03 04:36:58 PM PDT 24
Finished Aug 03 04:37:01 PM PDT 24
Peak memory 215048 kb
Host smart-1965c19c-562b-4fcc-838a-dfcd4df32b4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500675220 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2500675220
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3645063586
Short name T1118
Test name
Test status
Simulation time 35287225 ps
CPU time 0.9 seconds
Started Aug 03 04:36:50 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 206272 kb
Host smart-950f250c-5607-4b32-ac6d-03ce5af7ea4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645063586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3645063586
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3590709433
Short name T1050
Test name
Test status
Simulation time 33101677 ps
CPU time 0.79 seconds
Started Aug 03 04:37:01 PM PDT 24
Finished Aug 03 04:37:02 PM PDT 24
Peak memory 206396 kb
Host smart-84a8b644-8259-48da-a596-bcf95cd27b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590709433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3590709433
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3650157801
Short name T1084
Test name
Test status
Simulation time 19164374 ps
CPU time 1.02 seconds
Started Aug 03 04:36:52 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 206748 kb
Host smart-f48f04c5-e18e-469c-a012-126ee99c0213
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650157801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3650157801
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.757218084
Short name T1067
Test name
Test status
Simulation time 46402467 ps
CPU time 1.94 seconds
Started Aug 03 04:36:50 PM PDT 24
Finished Aug 03 04:36:52 PM PDT 24
Peak memory 214876 kb
Host smart-5c77fea1-444a-4de1-a6c0-f7e4ce0cfb5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757218084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.757218084
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2174715982
Short name T1100
Test name
Test status
Simulation time 165071940 ps
CPU time 2.64 seconds
Started Aug 03 04:36:57 PM PDT 24
Finished Aug 03 04:37:00 PM PDT 24
Peak memory 206592 kb
Host smart-a3b49201-589e-4ce8-94a2-acea6f28db2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174715982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2174715982
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.902924725
Short name T446
Test name
Test status
Simulation time 25245595 ps
CPU time 1.26 seconds
Started Aug 03 05:46:24 PM PDT 24
Finished Aug 03 05:46:26 PM PDT 24
Peak memory 219624 kb
Host smart-3755852e-0518-49cb-b362-c18c4757d5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902924725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.902924725
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1672513982
Short name T842
Test name
Test status
Simulation time 36012642 ps
CPU time 0.82 seconds
Started Aug 03 05:46:32 PM PDT 24
Finished Aug 03 05:46:33 PM PDT 24
Peak memory 206476 kb
Host smart-2cf5ed00-058e-4a09-9b47-2102005c5528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672513982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1672513982
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2767836213
Short name T423
Test name
Test status
Simulation time 10072752 ps
CPU time 0.87 seconds
Started Aug 03 05:46:27 PM PDT 24
Finished Aug 03 05:46:28 PM PDT 24
Peak memory 216024 kb
Host smart-d7fc2e59-d30b-4be6-bce6-09ed4134b2e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767836213 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2767836213
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_genbits.4008973690
Short name T340
Test name
Test status
Simulation time 108611421 ps
CPU time 1.24 seconds
Started Aug 03 05:46:15 PM PDT 24
Finished Aug 03 05:46:17 PM PDT 24
Peak memory 217612 kb
Host smart-3fa92946-a237-42c6-89d7-7ff206f13865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008973690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.4008973690
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.764552513
Short name T900
Test name
Test status
Simulation time 22766497 ps
CPU time 1.17 seconds
Started Aug 03 05:46:22 PM PDT 24
Finished Aug 03 05:46:23 PM PDT 24
Peak memory 223992 kb
Host smart-fa216fb3-499c-4745-be17-a4ac84c85609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764552513 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.764552513
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.2848633632
Short name T704
Test name
Test status
Simulation time 17498843 ps
CPU time 0.97 seconds
Started Aug 03 05:46:19 PM PDT 24
Finished Aug 03 05:46:20 PM PDT 24
Peak memory 207076 kb
Host smart-bb180c4c-ba0d-46ea-a31f-85aba6fc8e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848633632 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2848633632
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.3535688336
Short name T659
Test name
Test status
Simulation time 28001574 ps
CPU time 0.93 seconds
Started Aug 03 05:46:16 PM PDT 24
Finished Aug 03 05:46:18 PM PDT 24
Peak memory 215288 kb
Host smart-4b2433d5-d997-4ca4-be8f-5689f3e77022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535688336 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3535688336
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3954382278
Short name T248
Test name
Test status
Simulation time 392443715 ps
CPU time 4.12 seconds
Started Aug 03 05:46:17 PM PDT 24
Finished Aug 03 05:46:21 PM PDT 24
Peak memory 217352 kb
Host smart-aee55f23-9c86-442a-8d6c-f30343e36690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954382278 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3954382278
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2029024899
Short name T761
Test name
Test status
Simulation time 143572160101 ps
CPU time 779.36 seconds
Started Aug 03 05:46:20 PM PDT 24
Finished Aug 03 05:59:20 PM PDT 24
Peak memory 223588 kb
Host smart-3e86d6a5-725b-404a-8628-837135ff2404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029024899 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2029024899
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.2841790528
Short name T889
Test name
Test status
Simulation time 70728864 ps
CPU time 1.07 seconds
Started Aug 03 05:46:36 PM PDT 24
Finished Aug 03 05:46:37 PM PDT 24
Peak memory 220640 kb
Host smart-3ccdede2-6ef9-4847-ba5e-682cb8d046ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841790528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2841790528
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.338399826
Short name T407
Test name
Test status
Simulation time 30171615 ps
CPU time 0.82 seconds
Started Aug 03 05:46:39 PM PDT 24
Finished Aug 03 05:46:39 PM PDT 24
Peak memory 216000 kb
Host smart-ab9d24d1-663c-4f2e-bcf4-792b622b6548
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338399826 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.338399826
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1257901599
Short name T913
Test name
Test status
Simulation time 25741884 ps
CPU time 1.1 seconds
Started Aug 03 05:46:40 PM PDT 24
Finished Aug 03 05:46:41 PM PDT 24
Peak memory 218572 kb
Host smart-ce6defbc-de48-4966-b8a7-c2e2a5d61e67
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257901599 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1257901599
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1105292798
Short name T160
Test name
Test status
Simulation time 79444638 ps
CPU time 1.13 seconds
Started Aug 03 05:46:37 PM PDT 24
Finished Aug 03 05:46:39 PM PDT 24
Peak memory 229840 kb
Host smart-6ffae2bd-a4f9-49f5-8c65-9d6143beddef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105292798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1105292798
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.814133871
Short name T669
Test name
Test status
Simulation time 37514143 ps
CPU time 1.37 seconds
Started Aug 03 05:46:38 PM PDT 24
Finished Aug 03 05:46:39 PM PDT 24
Peak memory 220032 kb
Host smart-b9f73021-e591-4c51-afa8-d99a0e6ebc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814133871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.814133871
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2904771715
Short name T460
Test name
Test status
Simulation time 22203829 ps
CPU time 1.1 seconds
Started Aug 03 05:46:38 PM PDT 24
Finished Aug 03 05:46:39 PM PDT 24
Peak memory 215464 kb
Host smart-6b05b885-ddc6-441c-859b-5b87a871916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904771715 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2904771715
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1378414918
Short name T616
Test name
Test status
Simulation time 20072160 ps
CPU time 0.93 seconds
Started Aug 03 05:46:36 PM PDT 24
Finished Aug 03 05:46:37 PM PDT 24
Peak memory 207116 kb
Host smart-1cec9072-a891-4519-bf7e-e8eb79cc5567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378414918 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1378414918
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.776515435
Short name T655
Test name
Test status
Simulation time 16950877 ps
CPU time 0.99 seconds
Started Aug 03 05:46:33 PM PDT 24
Finished Aug 03 05:46:34 PM PDT 24
Peak memory 207040 kb
Host smart-6d501a0a-6297-4913-b941-30298d69a1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776515435 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.776515435
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3110540918
Short name T844
Test name
Test status
Simulation time 411708637 ps
CPU time 2.43 seconds
Started Aug 03 05:46:38 PM PDT 24
Finished Aug 03 05:46:40 PM PDT 24
Peak memory 215356 kb
Host smart-75357305-aef1-4251-91d6-c8a661d9d4b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110540918 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3110540918
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1887134015
Short name T836
Test name
Test status
Simulation time 83313997730 ps
CPU time 254.76 seconds
Started Aug 03 05:46:39 PM PDT 24
Finished Aug 03 05:50:54 PM PDT 24
Peak memory 223724 kb
Host smart-2123faf0-0a5f-471e-8209-2154a583a403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887134015 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1887134015
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3831424090
Short name T888
Test name
Test status
Simulation time 26905948 ps
CPU time 1.28 seconds
Started Aug 03 05:47:54 PM PDT 24
Finished Aug 03 05:47:56 PM PDT 24
Peak memory 219860 kb
Host smart-fcc296d5-df34-4f2b-b197-8b720c452186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831424090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3831424090
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.480485879
Short name T343
Test name
Test status
Simulation time 114203040 ps
CPU time 0.91 seconds
Started Aug 03 05:48:02 PM PDT 24
Finished Aug 03 05:48:03 PM PDT 24
Peak memory 206712 kb
Host smart-e8af92b3-4ec9-4cd3-9bd4-3ccb026205ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480485879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.480485879
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2555202166
Short name T487
Test name
Test status
Simulation time 18229524 ps
CPU time 0.86 seconds
Started Aug 03 05:48:00 PM PDT 24
Finished Aug 03 05:48:01 PM PDT 24
Peak memory 215392 kb
Host smart-56f252b0-3fed-48c9-a949-3e0b5a367e9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555202166 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2555202166
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.605222416
Short name T188
Test name
Test status
Simulation time 72563303 ps
CPU time 1.18 seconds
Started Aug 03 05:48:02 PM PDT 24
Finished Aug 03 05:48:04 PM PDT 24
Peak memory 225684 kb
Host smart-b5d7f5d2-56ee-4edb-b8eb-5132f9786697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605222416 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.605222416
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2592425183
Short name T551
Test name
Test status
Simulation time 38045489 ps
CPU time 1.29 seconds
Started Aug 03 05:47:57 PM PDT 24
Finished Aug 03 05:47:58 PM PDT 24
Peak memory 217268 kb
Host smart-850d68ff-3311-46f3-ba41-a974e5b475a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592425183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2592425183
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1944667483
Short name T345
Test name
Test status
Simulation time 33215551 ps
CPU time 0.87 seconds
Started Aug 03 05:47:54 PM PDT 24
Finished Aug 03 05:47:55 PM PDT 24
Peak memory 215164 kb
Host smart-20ad5357-c555-481e-90db-a12c3f79f4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944667483 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1944667483
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1836221371
Short name T989
Test name
Test status
Simulation time 33086858 ps
CPU time 0.94 seconds
Started Aug 03 05:47:55 PM PDT 24
Finished Aug 03 05:47:56 PM PDT 24
Peak memory 215224 kb
Host smart-abd6c2cc-5547-4265-833d-9f5c0abd933e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836221371 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1836221371
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.4106682605
Short name T592
Test name
Test status
Simulation time 340758512 ps
CPU time 1.73 seconds
Started Aug 03 05:47:55 PM PDT 24
Finished Aug 03 05:47:57 PM PDT 24
Peak memory 215280 kb
Host smart-8548b2b3-8fa7-48ab-8d30-51804739a782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106682605 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.4106682605
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1218922304
Short name T429
Test name
Test status
Simulation time 55871061310 ps
CPU time 438.98 seconds
Started Aug 03 05:47:55 PM PDT 24
Finished Aug 03 05:55:15 PM PDT 24
Peak memory 218448 kb
Host smart-af2dfa61-60cd-438e-b8eb-6e7b357da22c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218922304 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1218922304
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.142489515
Short name T778
Test name
Test status
Simulation time 371166848 ps
CPU time 1.39 seconds
Started Aug 03 05:51:32 PM PDT 24
Finished Aug 03 05:51:34 PM PDT 24
Peak memory 220164 kb
Host smart-5ff7654c-ffe0-43de-94de-b15468fe9c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142489515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.142489515
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.3861709156
Short name T426
Test name
Test status
Simulation time 85148905 ps
CPU time 1.16 seconds
Started Aug 03 05:51:33 PM PDT 24
Finished Aug 03 05:51:34 PM PDT 24
Peak memory 218588 kb
Host smart-35514ee7-b224-4344-8d9f-f13a00f6b61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861709156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.3861709156
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.1949912525
Short name T882
Test name
Test status
Simulation time 82371517 ps
CPU time 1.03 seconds
Started Aug 03 05:51:34 PM PDT 24
Finished Aug 03 05:51:35 PM PDT 24
Peak memory 217304 kb
Host smart-af46745b-5e38-4433-bdaf-5181cded90e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949912525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1949912525
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.2060656119
Short name T333
Test name
Test status
Simulation time 112050489 ps
CPU time 1.59 seconds
Started Aug 03 05:51:31 PM PDT 24
Finished Aug 03 05:51:33 PM PDT 24
Peak memory 219888 kb
Host smart-589e1edb-c83d-4320-8021-5490e9258958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060656119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2060656119
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.3284435411
Short name T768
Test name
Test status
Simulation time 27346944 ps
CPU time 1.24 seconds
Started Aug 03 05:51:35 PM PDT 24
Finished Aug 03 05:51:36 PM PDT 24
Peak memory 219696 kb
Host smart-ef0b182e-7a8c-4967-8f57-6802fa38e662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284435411 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.3284435411
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.956704783
Short name T867
Test name
Test status
Simulation time 70285382 ps
CPU time 1.23 seconds
Started Aug 03 05:51:39 PM PDT 24
Finished Aug 03 05:51:40 PM PDT 24
Peak memory 217364 kb
Host smart-e141a544-516f-474d-9055-1d5fe35a4a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956704783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.956704783
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.4187656701
Short name T979
Test name
Test status
Simulation time 27234677 ps
CPU time 1.25 seconds
Started Aug 03 05:51:39 PM PDT 24
Finished Aug 03 05:51:40 PM PDT 24
Peak memory 215660 kb
Host smart-e6a804f6-f046-4434-aeb6-b32c0eb1fe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187656701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.4187656701
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.2529626933
Short name T33
Test name
Test status
Simulation time 62288922 ps
CPU time 1.89 seconds
Started Aug 03 05:51:41 PM PDT 24
Finished Aug 03 05:51:43 PM PDT 24
Peak memory 218952 kb
Host smart-02f34ae9-573e-4430-bd02-1184f7e1759d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529626933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2529626933
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.3122722264
Short name T300
Test name
Test status
Simulation time 240147387 ps
CPU time 1.18 seconds
Started Aug 03 05:51:40 PM PDT 24
Finished Aug 03 05:51:41 PM PDT 24
Peak memory 218620 kb
Host smart-7817d72b-8953-4720-9726-13ffd474dcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122722264 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.3122722264
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.7533853
Short name T488
Test name
Test status
Simulation time 45345805 ps
CPU time 1.24 seconds
Started Aug 03 05:51:36 PM PDT 24
Finished Aug 03 05:51:38 PM PDT 24
Peak memory 219676 kb
Host smart-fbb81a0c-4c80-48e0-bded-452aae74fc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7533853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.7533853
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.3294541185
Short name T694
Test name
Test status
Simulation time 24099454 ps
CPU time 1.1 seconds
Started Aug 03 05:51:37 PM PDT 24
Finished Aug 03 05:51:38 PM PDT 24
Peak memory 219700 kb
Host smart-063f4d25-06cb-4c0d-a893-cd0302648244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294541185 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3294541185
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.3393787521
Short name T530
Test name
Test status
Simulation time 32085991 ps
CPU time 1.39 seconds
Started Aug 03 05:51:40 PM PDT 24
Finished Aug 03 05:51:41 PM PDT 24
Peak memory 217896 kb
Host smart-715bfd2b-cce5-4c3b-aca1-1c27edc9a274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393787521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3393787521
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.868326883
Short name T737
Test name
Test status
Simulation time 45247671 ps
CPU time 1.22 seconds
Started Aug 03 05:51:37 PM PDT 24
Finished Aug 03 05:51:38 PM PDT 24
Peak memory 219696 kb
Host smart-05bad45e-6e8d-4718-988a-a04d937a2401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868326883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.868326883
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.223990083
Short name T980
Test name
Test status
Simulation time 81940692 ps
CPU time 1.21 seconds
Started Aug 03 05:51:39 PM PDT 24
Finished Aug 03 05:51:41 PM PDT 24
Peak memory 219040 kb
Host smart-722d5a09-92bb-47b6-becb-29a78f1b3a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223990083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.223990083
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.4175566444
Short name T277
Test name
Test status
Simulation time 29690195 ps
CPU time 1.31 seconds
Started Aug 03 05:51:38 PM PDT 24
Finished Aug 03 05:51:39 PM PDT 24
Peak memory 220816 kb
Host smart-d7c9de96-88c5-4a03-b5d1-d32f90434183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175566444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.4175566444
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.1411382074
Short name T810
Test name
Test status
Simulation time 20153022 ps
CPU time 1.06 seconds
Started Aug 03 05:51:36 PM PDT 24
Finished Aug 03 05:51:37 PM PDT 24
Peak memory 217344 kb
Host smart-db976a09-d389-4575-8841-1e76e392c656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411382074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1411382074
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.1709421458
Short name T463
Test name
Test status
Simulation time 21165679 ps
CPU time 0.84 seconds
Started Aug 03 05:48:09 PM PDT 24
Finished Aug 03 05:48:10 PM PDT 24
Peak memory 206744 kb
Host smart-3df08e0b-7bb9-4710-bf95-134216f46753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709421458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1709421458
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.385267793
Short name T766
Test name
Test status
Simulation time 290969855 ps
CPU time 1.07 seconds
Started Aug 03 05:48:07 PM PDT 24
Finished Aug 03 05:48:08 PM PDT 24
Peak memory 218356 kb
Host smart-e1f86098-4fa2-4381-bf03-09e265c9325c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385267793 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.385267793
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3440894685
Short name T569
Test name
Test status
Simulation time 69849612 ps
CPU time 1.1 seconds
Started Aug 03 05:48:08 PM PDT 24
Finished Aug 03 05:48:09 PM PDT 24
Peak memory 219732 kb
Host smart-5340d66c-2396-46b3-9eb6-9175662b9922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440894685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3440894685
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1304381660
Short name T759
Test name
Test status
Simulation time 140894937 ps
CPU time 1.35 seconds
Started Aug 03 05:48:04 PM PDT 24
Finished Aug 03 05:48:05 PM PDT 24
Peak memory 218884 kb
Host smart-39af91f4-dc5d-4560-ad8e-72cf74366c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304381660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1304381660
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3819763714
Short name T746
Test name
Test status
Simulation time 22050569 ps
CPU time 1.21 seconds
Started Aug 03 05:48:09 PM PDT 24
Finished Aug 03 05:48:11 PM PDT 24
Peak memory 215536 kb
Host smart-86956a46-a5f0-468c-8d8b-085ab1089598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819763714 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3819763714
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2304162460
Short name T923
Test name
Test status
Simulation time 117797606 ps
CPU time 0.89 seconds
Started Aug 03 05:48:02 PM PDT 24
Finished Aug 03 05:48:03 PM PDT 24
Peak memory 215100 kb
Host smart-155ef8f7-6e21-4b0e-92e2-92023da057bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304162460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2304162460
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1976536039
Short name T337
Test name
Test status
Simulation time 341979366 ps
CPU time 1.35 seconds
Started Aug 03 05:48:02 PM PDT 24
Finished Aug 03 05:48:04 PM PDT 24
Peak memory 215316 kb
Host smart-ecbe94d3-d4bc-4202-972b-a26b2e27a36e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976536039 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1976536039
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.325810471
Short name T622
Test name
Test status
Simulation time 224115468261 ps
CPU time 1298.41 seconds
Started Aug 03 05:48:02 PM PDT 24
Finished Aug 03 06:09:41 PM PDT 24
Peak memory 223728 kb
Host smart-f9cf0efa-8f74-4edb-a9f1-f23edf85ac59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325810471 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.325810471
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.2159646133
Short name T550
Test name
Test status
Simulation time 141451652 ps
CPU time 1.27 seconds
Started Aug 03 05:51:39 PM PDT 24
Finished Aug 03 05:51:40 PM PDT 24
Peak memory 220492 kb
Host smart-6f9439c7-f60c-4ab7-b4df-55cc11bb52e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159646133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2159646133
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.1850557057
Short name T354
Test name
Test status
Simulation time 30485881 ps
CPU time 1.47 seconds
Started Aug 03 05:51:38 PM PDT 24
Finished Aug 03 05:51:40 PM PDT 24
Peak memory 218772 kb
Host smart-b895042c-85aa-4be0-b8ba-f920402fe2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850557057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1850557057
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.3171905948
Short name T298
Test name
Test status
Simulation time 53269485 ps
CPU time 1.47 seconds
Started Aug 03 05:51:41 PM PDT 24
Finished Aug 03 05:51:43 PM PDT 24
Peak memory 221068 kb
Host smart-9c095332-ba39-4b39-bb12-c583a99fc522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171905948 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.3171905948
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.1238021946
Short name T635
Test name
Test status
Simulation time 129029833 ps
CPU time 1.13 seconds
Started Aug 03 05:51:42 PM PDT 24
Finished Aug 03 05:51:43 PM PDT 24
Peak memory 217388 kb
Host smart-ba323f08-2789-484a-8609-c578dff0406e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238021946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1238021946
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3731407292
Short name T977
Test name
Test status
Simulation time 25063589 ps
CPU time 1.18 seconds
Started Aug 03 05:51:40 PM PDT 24
Finished Aug 03 05:51:41 PM PDT 24
Peak memory 219788 kb
Host smart-ff0a2651-0a77-463d-a442-011139591dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731407292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3731407292
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/113.edn_alert.3726876814
Short name T733
Test name
Test status
Simulation time 41423921 ps
CPU time 1.08 seconds
Started Aug 03 05:51:41 PM PDT 24
Finished Aug 03 05:51:42 PM PDT 24
Peak memory 219588 kb
Host smart-9c3040ea-62a1-4583-953e-5207e1fa9283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726876814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3726876814
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.3211318481
Short name T755
Test name
Test status
Simulation time 22360980 ps
CPU time 1.12 seconds
Started Aug 03 05:51:40 PM PDT 24
Finished Aug 03 05:51:41 PM PDT 24
Peak memory 217232 kb
Host smart-2d95f29d-a3a4-4661-8a2a-bb25eec09336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211318481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3211318481
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.1364773157
Short name T898
Test name
Test status
Simulation time 25403620 ps
CPU time 1.12 seconds
Started Aug 03 05:51:41 PM PDT 24
Finished Aug 03 05:51:42 PM PDT 24
Peak memory 219832 kb
Host smart-cb3e47c1-b867-46e2-a49e-9bf2690e023b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364773157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.1364773157
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.4179344284
Short name T954
Test name
Test status
Simulation time 44920351 ps
CPU time 1.34 seconds
Started Aug 03 05:51:43 PM PDT 24
Finished Aug 03 05:51:44 PM PDT 24
Peak memory 217424 kb
Host smart-98471021-cd7b-4b55-a02a-89f2cfc903cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179344284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.4179344284
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.2331576941
Short name T146
Test name
Test status
Simulation time 69779281 ps
CPU time 1.15 seconds
Started Aug 03 05:51:46 PM PDT 24
Finished Aug 03 05:51:47 PM PDT 24
Peak memory 219752 kb
Host smart-eb27363f-3c4b-4419-9359-fe8883e3136e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331576941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.2331576941
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.2184922590
Short name T988
Test name
Test status
Simulation time 133529639 ps
CPU time 1.69 seconds
Started Aug 03 05:51:47 PM PDT 24
Finished Aug 03 05:51:48 PM PDT 24
Peak memory 220404 kb
Host smart-db05d7a3-fbb0-4abf-8c9d-553769d32ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184922590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2184922590
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.4282692424
Short name T843
Test name
Test status
Simulation time 59279406 ps
CPU time 1.5 seconds
Started Aug 03 05:51:47 PM PDT 24
Finished Aug 03 05:51:48 PM PDT 24
Peak memory 217432 kb
Host smart-22ae545c-53c3-4624-88d7-c76f0d7d83ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282692424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4282692424
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.453320516
Short name T713
Test name
Test status
Simulation time 25215471 ps
CPU time 1.23 seconds
Started Aug 03 05:51:51 PM PDT 24
Finished Aug 03 05:51:52 PM PDT 24
Peak memory 219584 kb
Host smart-c24cd206-9d12-492f-9956-910be509ed92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453320516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.453320516
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.3048970343
Short name T331
Test name
Test status
Simulation time 55798227 ps
CPU time 1.19 seconds
Started Aug 03 05:51:51 PM PDT 24
Finished Aug 03 05:51:52 PM PDT 24
Peak memory 218472 kb
Host smart-48bded24-344a-496d-84f7-074ce16bc06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048970343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3048970343
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.941384494
Short name T710
Test name
Test status
Simulation time 92306634 ps
CPU time 1.23 seconds
Started Aug 03 05:51:45 PM PDT 24
Finished Aug 03 05:51:47 PM PDT 24
Peak memory 218532 kb
Host smart-7e950527-e1e1-4802-a619-6e0c45622934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941384494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.941384494
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.3188260372
Short name T83
Test name
Test status
Simulation time 90665070 ps
CPU time 2.51 seconds
Started Aug 03 05:51:48 PM PDT 24
Finished Aug 03 05:51:50 PM PDT 24
Peak memory 217520 kb
Host smart-870a0dfc-73eb-4613-903b-598ea692a614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188260372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3188260372
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.131235167
Short name T499
Test name
Test status
Simulation time 29207252 ps
CPU time 1.33 seconds
Started Aug 03 05:51:46 PM PDT 24
Finished Aug 03 05:51:48 PM PDT 24
Peak memory 215664 kb
Host smart-9315521a-d3f3-4e31-8df7-a6ca97e533b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131235167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.131235167
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.565603571
Short name T341
Test name
Test status
Simulation time 249945008 ps
CPU time 3.3 seconds
Started Aug 03 05:51:51 PM PDT 24
Finished Aug 03 05:51:54 PM PDT 24
Peak memory 218828 kb
Host smart-598295c2-b3e2-4664-95ea-11368e6140b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565603571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.565603571
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2419552966
Short name T505
Test name
Test status
Simulation time 27201431 ps
CPU time 1.23 seconds
Started Aug 03 05:48:08 PM PDT 24
Finished Aug 03 05:48:10 PM PDT 24
Peak memory 220092 kb
Host smart-db286c51-1114-409d-ac36-652b64d9a5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419552966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2419552966
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2493453549
Short name T547
Test name
Test status
Simulation time 22220119 ps
CPU time 0.92 seconds
Started Aug 03 05:48:13 PM PDT 24
Finished Aug 03 05:48:14 PM PDT 24
Peak memory 214860 kb
Host smart-576f4a3a-83b1-4c17-9c7d-b105a332283a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493453549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2493453549
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.4249271279
Short name T834
Test name
Test status
Simulation time 13027021 ps
CPU time 0.9 seconds
Started Aug 03 05:48:06 PM PDT 24
Finished Aug 03 05:48:07 PM PDT 24
Peak memory 215528 kb
Host smart-4a02f2f3-c903-4dad-b3f7-cb51070576cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249271279 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.4249271279
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.1128938228
Short name T438
Test name
Test status
Simulation time 33096285 ps
CPU time 0.93 seconds
Started Aug 03 05:48:05 PM PDT 24
Finished Aug 03 05:48:06 PM PDT 24
Peak memory 219956 kb
Host smart-e31ef32a-999d-46c3-a646-eee782329b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128938228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1128938228
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2816403656
Short name T559
Test name
Test status
Simulation time 59218657 ps
CPU time 1.01 seconds
Started Aug 03 05:48:07 PM PDT 24
Finished Aug 03 05:48:08 PM PDT 24
Peak memory 217384 kb
Host smart-1e1e42b7-f26b-4ad7-9b0f-2c32eb3842ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816403656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2816403656
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.2904849012
Short name T680
Test name
Test status
Simulation time 81430185 ps
CPU time 0.95 seconds
Started Aug 03 05:48:07 PM PDT 24
Finished Aug 03 05:48:08 PM PDT 24
Peak memory 215236 kb
Host smart-27e229b9-64e0-4621-b07d-aa9d6350b946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904849012 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2904849012
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3249952880
Short name T640
Test name
Test status
Simulation time 507615162 ps
CPU time 4.89 seconds
Started Aug 03 05:48:07 PM PDT 24
Finished Aug 03 05:48:11 PM PDT 24
Peak memory 217252 kb
Host smart-6baad257-6d07-4dfd-9557-3a9507e70ad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249952880 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3249952880
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.902741703
Short name T908
Test name
Test status
Simulation time 206882593844 ps
CPU time 1249.6 seconds
Started Aug 03 05:48:07 PM PDT 24
Finished Aug 03 06:08:57 PM PDT 24
Peak memory 223828 kb
Host smart-72f8aa8e-ce46-4f5e-86b9-2b682e4db360
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902741703 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.902741703
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.896924497
Short name T147
Test name
Test status
Simulation time 24070052 ps
CPU time 1.18 seconds
Started Aug 03 05:51:49 PM PDT 24
Finished Aug 03 05:51:50 PM PDT 24
Peak memory 219772 kb
Host smart-9a066346-674b-4140-a700-5b4957621c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896924497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.896924497
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.1741374951
Short name T504
Test name
Test status
Simulation time 30035465 ps
CPU time 1.28 seconds
Started Aug 03 05:51:51 PM PDT 24
Finished Aug 03 05:51:52 PM PDT 24
Peak memory 218648 kb
Host smart-b1701187-9dda-4a68-94e3-58d3c85ad6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741374951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1741374951
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.3343892384
Short name T892
Test name
Test status
Simulation time 86338644 ps
CPU time 1.11 seconds
Started Aug 03 05:51:47 PM PDT 24
Finished Aug 03 05:51:48 PM PDT 24
Peak memory 218716 kb
Host smart-942e6744-5a97-43e1-a0cf-9f4d86734720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343892384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3343892384
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.3959356398
Short name T14
Test name
Test status
Simulation time 64864402 ps
CPU time 1.2 seconds
Started Aug 03 05:51:44 PM PDT 24
Finished Aug 03 05:51:46 PM PDT 24
Peak memory 219468 kb
Host smart-1ecb4095-5150-49d2-a526-35ee65ca3059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959356398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3959356398
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.1465052380
Short name T652
Test name
Test status
Simulation time 46286951 ps
CPU time 1.27 seconds
Started Aug 03 05:51:53 PM PDT 24
Finished Aug 03 05:51:54 PM PDT 24
Peak memory 220064 kb
Host smart-1e35fc98-eda3-4323-ba7d-8eb24ffd2484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465052380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1465052380
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.211579943
Short name T578
Test name
Test status
Simulation time 116697700 ps
CPU time 2.64 seconds
Started Aug 03 05:51:50 PM PDT 24
Finished Aug 03 05:51:53 PM PDT 24
Peak memory 219264 kb
Host smart-bfced829-903d-4ea8-b108-3cb3948d8ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211579943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.211579943
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.1885945657
Short name T902
Test name
Test status
Simulation time 72671753 ps
CPU time 1.14 seconds
Started Aug 03 05:51:54 PM PDT 24
Finished Aug 03 05:51:55 PM PDT 24
Peak memory 219384 kb
Host smart-aaa3998f-0564-4a34-98f8-0f66a0affd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885945657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.1885945657
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.1641929114
Short name T932
Test name
Test status
Simulation time 63338756 ps
CPU time 1.33 seconds
Started Aug 03 05:51:55 PM PDT 24
Finished Aug 03 05:51:57 PM PDT 24
Peak memory 217168 kb
Host smart-7ba3a4e1-cf42-4d3a-bd42-98d8f65994e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641929114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1641929114
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.1586348865
Short name T745
Test name
Test status
Simulation time 331408882 ps
CPU time 1.27 seconds
Started Aug 03 05:51:53 PM PDT 24
Finished Aug 03 05:51:54 PM PDT 24
Peak memory 218604 kb
Host smart-51269730-0687-42b8-bb80-5ca777d0cba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586348865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.1586348865
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.1234812431
Short name T498
Test name
Test status
Simulation time 61276968 ps
CPU time 1.29 seconds
Started Aug 03 05:51:53 PM PDT 24
Finished Aug 03 05:51:54 PM PDT 24
Peak memory 217340 kb
Host smart-dc1330ec-3623-41d6-81b1-b8625fc9cea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234812431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1234812431
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2017940551
Short name T443
Test name
Test status
Simulation time 88790242 ps
CPU time 1.18 seconds
Started Aug 03 05:51:54 PM PDT 24
Finished Aug 03 05:51:55 PM PDT 24
Peak memory 219576 kb
Host smart-8e63950e-477c-4e3b-9979-f6be66acf262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017940551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2017940551
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.1201148609
Short name T718
Test name
Test status
Simulation time 39279865 ps
CPU time 1.04 seconds
Started Aug 03 05:51:58 PM PDT 24
Finished Aug 03 05:51:59 PM PDT 24
Peak memory 217364 kb
Host smart-b2833ea3-ce76-4e1f-841e-e7a67fdd3ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201148609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1201148609
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.3482271208
Short name T509
Test name
Test status
Simulation time 26018764 ps
CPU time 1.28 seconds
Started Aug 03 05:51:55 PM PDT 24
Finished Aug 03 05:51:56 PM PDT 24
Peak memory 219712 kb
Host smart-0d4e1d8d-5207-4b7e-9d62-9a0d44259c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482271208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3482271208
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.2192002583
Short name T417
Test name
Test status
Simulation time 56927554 ps
CPU time 1.39 seconds
Started Aug 03 05:51:58 PM PDT 24
Finished Aug 03 05:51:59 PM PDT 24
Peak memory 219020 kb
Host smart-3eb0e18c-7403-4c26-848b-81e781505a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192002583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2192002583
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.66006208
Short name T421
Test name
Test status
Simulation time 59813357 ps
CPU time 1.13 seconds
Started Aug 03 05:51:52 PM PDT 24
Finished Aug 03 05:51:54 PM PDT 24
Peak memory 220020 kb
Host smart-2737391e-0ac5-465f-b616-c5b4a4fadb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66006208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.66006208
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.464384254
Short name T524
Test name
Test status
Simulation time 63770238 ps
CPU time 1.74 seconds
Started Aug 03 05:51:53 PM PDT 24
Finished Aug 03 05:51:55 PM PDT 24
Peak memory 218792 kb
Host smart-b946c68c-2f1b-4a7e-8c77-4ca0837ede6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464384254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.464384254
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.3499882509
Short name T459
Test name
Test status
Simulation time 45843618 ps
CPU time 1.52 seconds
Started Aug 03 05:51:52 PM PDT 24
Finished Aug 03 05:51:54 PM PDT 24
Peak memory 218604 kb
Host smart-8709abff-0db4-401a-8181-695c4e7abf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499882509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3499882509
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.3109082587
Short name T773
Test name
Test status
Simulation time 42772261 ps
CPU time 1.14 seconds
Started Aug 03 05:51:53 PM PDT 24
Finished Aug 03 05:51:55 PM PDT 24
Peak memory 220016 kb
Host smart-d677472a-054d-4490-9471-ebd9ec99cffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109082587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3109082587
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.1480465488
Short name T323
Test name
Test status
Simulation time 62662268 ps
CPU time 1.33 seconds
Started Aug 03 05:51:58 PM PDT 24
Finished Aug 03 05:51:59 PM PDT 24
Peak memory 218504 kb
Host smart-92575650-3015-4cc3-afa6-aa85050956e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480465488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1480465488
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1756029041
Short name T841
Test name
Test status
Simulation time 43687987 ps
CPU time 1.29 seconds
Started Aug 03 05:48:13 PM PDT 24
Finished Aug 03 05:48:14 PM PDT 24
Peak memory 218524 kb
Host smart-ffd8cdc6-289b-4d55-9126-2b70552c3765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756029041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1756029041
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1012066458
Short name T804
Test name
Test status
Simulation time 21442212 ps
CPU time 1.04 seconds
Started Aug 03 05:48:17 PM PDT 24
Finished Aug 03 05:48:18 PM PDT 24
Peak memory 206656 kb
Host smart-66ec8330-fe37-46c9-98c8-4c13d50b1f75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012066458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1012066458
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.854988556
Short name T100
Test name
Test status
Simulation time 14012768 ps
CPU time 0.94 seconds
Started Aug 03 05:48:18 PM PDT 24
Finished Aug 03 05:48:19 PM PDT 24
Peak memory 216392 kb
Host smart-d37fe46d-cf66-413b-a601-410570699cea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854988556 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.854988556
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1029822322
Short name T154
Test name
Test status
Simulation time 157626364 ps
CPU time 1.11 seconds
Started Aug 03 05:48:18 PM PDT 24
Finished Aug 03 05:48:19 PM PDT 24
Peak memory 218628 kb
Host smart-0de9d13d-223e-49d6-af4e-04bd86b474a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029822322 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1029822322
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1206294657
Short name T108
Test name
Test status
Simulation time 19905374 ps
CPU time 1.2 seconds
Started Aug 03 05:48:17 PM PDT 24
Finished Aug 03 05:48:18 PM PDT 24
Peak memory 224028 kb
Host smart-ae9ad631-6579-4f54-a7e9-403d9610c68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206294657 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1206294657
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1301447147
Short name T812
Test name
Test status
Simulation time 200157671 ps
CPU time 2.46 seconds
Started Aug 03 05:48:13 PM PDT 24
Finished Aug 03 05:48:15 PM PDT 24
Peak memory 217672 kb
Host smart-b28414f7-8b8e-4753-9d02-a5a39a1e525b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301447147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1301447147
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.3660196996
Short name T363
Test name
Test status
Simulation time 23117439 ps
CPU time 0.93 seconds
Started Aug 03 05:48:13 PM PDT 24
Finished Aug 03 05:48:14 PM PDT 24
Peak memory 215256 kb
Host smart-2862cbd4-4b47-4984-87b3-3edc2349bdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660196996 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3660196996
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.188956963
Short name T651
Test name
Test status
Simulation time 1476829060 ps
CPU time 4.43 seconds
Started Aug 03 05:48:12 PM PDT 24
Finished Aug 03 05:48:17 PM PDT 24
Peak memory 217136 kb
Host smart-2d70a2e5-bf8c-475e-a7c7-7257a333590d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188956963 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.188956963
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2657177477
Short name T232
Test name
Test status
Simulation time 30699352477 ps
CPU time 648.19 seconds
Started Aug 03 05:48:13 PM PDT 24
Finished Aug 03 05:59:01 PM PDT 24
Peak memory 223768 kb
Host smart-6e16a011-c306-46f7-8f50-1874b648bd6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657177477 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2657177477
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.edn_alert.1183243485
Short name T624
Test name
Test status
Simulation time 37322828 ps
CPU time 1.19 seconds
Started Aug 03 05:51:55 PM PDT 24
Finished Aug 03 05:51:56 PM PDT 24
Peak memory 220792 kb
Host smart-58c90796-1a3b-438f-ba35-f6f545763666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183243485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1183243485
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.2242535947
Short name T656
Test name
Test status
Simulation time 40103861 ps
CPU time 1.55 seconds
Started Aug 03 05:51:53 PM PDT 24
Finished Aug 03 05:51:54 PM PDT 24
Peak memory 217452 kb
Host smart-c32903ab-cdba-40d9-804f-0882b81a52a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242535947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2242535947
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.160170160
Short name T428
Test name
Test status
Simulation time 56417038 ps
CPU time 1.23 seconds
Started Aug 03 05:51:52 PM PDT 24
Finished Aug 03 05:51:54 PM PDT 24
Peak memory 215680 kb
Host smart-a9b6b6fe-e266-4562-826f-1b722fc0981f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160170160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.160170160
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.1415358795
Short name T724
Test name
Test status
Simulation time 79271121 ps
CPU time 1.42 seconds
Started Aug 03 05:51:53 PM PDT 24
Finished Aug 03 05:51:54 PM PDT 24
Peak memory 218692 kb
Host smart-aca9bf3b-c59e-452d-a4e0-22d9df46dad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415358795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1415358795
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.3585108990
Short name T692
Test name
Test status
Simulation time 25258372 ps
CPU time 1.21 seconds
Started Aug 03 05:51:53 PM PDT 24
Finished Aug 03 05:51:55 PM PDT 24
Peak memory 219900 kb
Host smart-f764287b-459e-4c9e-aa85-6e26f08cdeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585108990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.3585108990
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3734876713
Short name T677
Test name
Test status
Simulation time 53999381 ps
CPU time 1.45 seconds
Started Aug 03 05:51:54 PM PDT 24
Finished Aug 03 05:51:55 PM PDT 24
Peak memory 217440 kb
Host smart-3776558e-c6e1-4729-a1ce-2d4ea65ee481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734876713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3734876713
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.2633020506
Short name T197
Test name
Test status
Simulation time 27378283 ps
CPU time 1.26 seconds
Started Aug 03 05:52:05 PM PDT 24
Finished Aug 03 05:52:07 PM PDT 24
Peak memory 219824 kb
Host smart-0b479266-0bc4-4493-81be-af9addaff99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633020506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2633020506
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.1618881012
Short name T396
Test name
Test status
Simulation time 320682582 ps
CPU time 3.89 seconds
Started Aug 03 05:51:59 PM PDT 24
Finished Aug 03 05:52:03 PM PDT 24
Peak memory 220108 kb
Host smart-41e4db33-573a-4747-a715-b3043891e807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618881012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1618881012
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.3232598804
Short name T216
Test name
Test status
Simulation time 79349723 ps
CPU time 1.12 seconds
Started Aug 03 05:52:00 PM PDT 24
Finished Aug 03 05:52:01 PM PDT 24
Peak memory 219576 kb
Host smart-41cda52c-5d1f-43a9-a86a-46970d7b679d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232598804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3232598804
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.3549429171
Short name T432
Test name
Test status
Simulation time 40381908 ps
CPU time 1.09 seconds
Started Aug 03 05:51:59 PM PDT 24
Finished Aug 03 05:52:00 PM PDT 24
Peak memory 218500 kb
Host smart-ff0e887b-3f13-4ed8-868d-360a84cab02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549429171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3549429171
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.3344119525
Short name T213
Test name
Test status
Simulation time 25961208 ps
CPU time 1.26 seconds
Started Aug 03 05:52:02 PM PDT 24
Finished Aug 03 05:52:04 PM PDT 24
Peak memory 219952 kb
Host smart-7ba36655-0b03-4909-896e-99974446c466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344119525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.3344119525
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2182958873
Short name T780
Test name
Test status
Simulation time 92538904 ps
CPU time 1.54 seconds
Started Aug 03 05:51:58 PM PDT 24
Finished Aug 03 05:52:00 PM PDT 24
Peak memory 218600 kb
Host smart-ba6f5b54-92a9-49dc-9d28-bca8355866ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182958873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2182958873
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.1509947395
Short name T279
Test name
Test status
Simulation time 27757680 ps
CPU time 1.29 seconds
Started Aug 03 05:51:59 PM PDT 24
Finished Aug 03 05:52:01 PM PDT 24
Peak memory 218596 kb
Host smart-bf2e93aa-3045-4c19-866d-efac0739ce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509947395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1509947395
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.2432422914
Short name T852
Test name
Test status
Simulation time 33117108 ps
CPU time 1.04 seconds
Started Aug 03 05:52:05 PM PDT 24
Finished Aug 03 05:52:06 PM PDT 24
Peak memory 217204 kb
Host smart-b11a67df-7ed1-4676-97bf-4f7ff4f3bae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432422914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2432422914
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.2810657679
Short name T296
Test name
Test status
Simulation time 96436214 ps
CPU time 1.28 seconds
Started Aug 03 05:51:57 PM PDT 24
Finished Aug 03 05:51:59 PM PDT 24
Peak memory 218444 kb
Host smart-337ef74c-34ac-4c2e-8254-3286fd4311db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810657679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.2810657679
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.643994114
Short name T84
Test name
Test status
Simulation time 54360852 ps
CPU time 1.21 seconds
Started Aug 03 05:52:00 PM PDT 24
Finished Aug 03 05:52:01 PM PDT 24
Peak memory 219984 kb
Host smart-dcdd6153-a144-4650-bd19-b327c00e6b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643994114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.643994114
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.1484968591
Short name T644
Test name
Test status
Simulation time 37265591 ps
CPU time 1.08 seconds
Started Aug 03 05:52:01 PM PDT 24
Finished Aug 03 05:52:02 PM PDT 24
Peak memory 219844 kb
Host smart-79a0c3fc-b06d-4685-8ecd-41e11c8ae933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484968591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1484968591
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.3344279845
Short name T528
Test name
Test status
Simulation time 74839528 ps
CPU time 1.19 seconds
Started Aug 03 05:52:02 PM PDT 24
Finished Aug 03 05:52:03 PM PDT 24
Peak memory 218956 kb
Host smart-3fe581ff-a83f-496d-959c-25594f80e045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344279845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3344279845
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1502682077
Short name T716
Test name
Test status
Simulation time 109597053 ps
CPU time 1.17 seconds
Started Aug 03 05:48:16 PM PDT 24
Finished Aug 03 05:48:17 PM PDT 24
Peak memory 219248 kb
Host smart-46ae8a94-c9f6-4913-8527-131cf01e4692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502682077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1502682077
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.4081863595
Short name T427
Test name
Test status
Simulation time 187409317 ps
CPU time 0.9 seconds
Started Aug 03 05:48:24 PM PDT 24
Finished Aug 03 05:48:25 PM PDT 24
Peak memory 206704 kb
Host smart-df58b449-2d54-41e9-993e-afaa82d091a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081863595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.4081863595
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2048423609
Short name T838
Test name
Test status
Simulation time 85567777 ps
CPU time 1.08 seconds
Started Aug 03 05:48:23 PM PDT 24
Finished Aug 03 05:48:24 PM PDT 24
Peak memory 218488 kb
Host smart-0e49901d-dea6-4da1-ac3e-73c45b1ed16a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048423609 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2048423609
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.814463654
Short name T826
Test name
Test status
Simulation time 56863105 ps
CPU time 1.01 seconds
Started Aug 03 05:48:18 PM PDT 24
Finished Aug 03 05:48:19 PM PDT 24
Peak memory 219904 kb
Host smart-de37fa9e-57ac-4ae2-bd26-105c7eb2d855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814463654 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.814463654
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.800681717
Short name T391
Test name
Test status
Simulation time 52351443 ps
CPU time 1 seconds
Started Aug 03 05:48:19 PM PDT 24
Finished Aug 03 05:48:20 PM PDT 24
Peak memory 217124 kb
Host smart-c8addf29-a9ed-42d3-a115-a956b37c887d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800681717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.800681717
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.615100870
Short name T967
Test name
Test status
Simulation time 38234538 ps
CPU time 0.94 seconds
Started Aug 03 05:48:18 PM PDT 24
Finished Aug 03 05:48:19 PM PDT 24
Peak memory 215328 kb
Host smart-1829ae34-b98f-4c00-a018-41c985ff8fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615100870 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.615100870
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3637976150
Short name T848
Test name
Test status
Simulation time 28603002 ps
CPU time 0.96 seconds
Started Aug 03 05:48:18 PM PDT 24
Finished Aug 03 05:48:19 PM PDT 24
Peak memory 215280 kb
Host smart-ce47f185-cdeb-49fd-8a9f-ac396f6da414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637976150 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3637976150
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.27643525
Short name T420
Test name
Test status
Simulation time 398769969 ps
CPU time 1.63 seconds
Started Aug 03 05:48:19 PM PDT 24
Finished Aug 03 05:48:20 PM PDT 24
Peak memory 217528 kb
Host smart-efc06c7f-e304-4b36-beb7-a55154038d7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27643525 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.27643525
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.417817161
Short name T762
Test name
Test status
Simulation time 125404395720 ps
CPU time 796.83 seconds
Started Aug 03 05:48:19 PM PDT 24
Finished Aug 03 06:01:36 PM PDT 24
Peak memory 221704 kb
Host smart-2133b963-4b5e-426a-a21c-93c60b560639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417817161 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.417817161
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.216795424
Short name T849
Test name
Test status
Simulation time 100183078 ps
CPU time 1.34 seconds
Started Aug 03 05:51:59 PM PDT 24
Finished Aug 03 05:52:01 PM PDT 24
Peak memory 217636 kb
Host smart-8bd570db-76fa-42d6-9083-832697f9d4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216795424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.216795424
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.4219089303
Short name T758
Test name
Test status
Simulation time 36337178 ps
CPU time 1.28 seconds
Started Aug 03 05:52:00 PM PDT 24
Finished Aug 03 05:52:01 PM PDT 24
Peak memory 215680 kb
Host smart-1e9b5258-57e9-46d1-85f9-d8b8fa36c26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219089303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.4219089303
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.869291377
Short name T924
Test name
Test status
Simulation time 32337257 ps
CPU time 1.41 seconds
Started Aug 03 05:51:59 PM PDT 24
Finished Aug 03 05:52:01 PM PDT 24
Peak memory 218636 kb
Host smart-67bb1dd0-11e8-48bf-b4df-8c7ee80433e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869291377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.869291377
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.2248651806
Short name T682
Test name
Test status
Simulation time 75349844 ps
CPU time 1.2 seconds
Started Aug 03 05:51:58 PM PDT 24
Finished Aug 03 05:51:59 PM PDT 24
Peak memory 219712 kb
Host smart-58012333-cc8b-436d-b1f5-ab7b069f70d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248651806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2248651806
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.1633448345
Short name T439
Test name
Test status
Simulation time 162920484 ps
CPU time 0.94 seconds
Started Aug 03 05:51:57 PM PDT 24
Finished Aug 03 05:51:58 PM PDT 24
Peak memory 217448 kb
Host smart-1145c257-672c-4860-b75e-09c3ec256ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633448345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1633448345
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.2621284516
Short name T189
Test name
Test status
Simulation time 92906827 ps
CPU time 1.09 seconds
Started Aug 03 05:51:58 PM PDT 24
Finished Aug 03 05:51:59 PM PDT 24
Peak memory 219816 kb
Host smart-4d971a23-054b-448d-a6e0-873e7de16e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621284516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.2621284516
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.403739285
Short name T931
Test name
Test status
Simulation time 57587101 ps
CPU time 1.35 seconds
Started Aug 03 05:52:00 PM PDT 24
Finished Aug 03 05:52:02 PM PDT 24
Peak memory 217164 kb
Host smart-93ddf933-2d35-4c1a-95ee-44c609bd6c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403739285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.403739285
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.2626189597
Short name T203
Test name
Test status
Simulation time 76854953 ps
CPU time 1.12 seconds
Started Aug 03 05:51:58 PM PDT 24
Finished Aug 03 05:51:59 PM PDT 24
Peak memory 219540 kb
Host smart-6239bdf1-a157-4296-8d53-b761699facfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626189597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.2626189597
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.1204418031
Short name T356
Test name
Test status
Simulation time 29726876 ps
CPU time 1.37 seconds
Started Aug 03 05:52:02 PM PDT 24
Finished Aug 03 05:52:03 PM PDT 24
Peak memory 215264 kb
Host smart-4634aa24-c2ea-4f76-b53c-0377725a7b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204418031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1204418031
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.3158931389
Short name T70
Test name
Test status
Simulation time 27665067 ps
CPU time 1.31 seconds
Started Aug 03 05:52:01 PM PDT 24
Finished Aug 03 05:52:02 PM PDT 24
Peak memory 219592 kb
Host smart-c1534b5c-78f6-44e8-9f74-bc29554cb440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158931389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3158931389
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.2432125362
Short name T772
Test name
Test status
Simulation time 40233973 ps
CPU time 1.2 seconds
Started Aug 03 05:51:57 PM PDT 24
Finished Aug 03 05:51:58 PM PDT 24
Peak memory 217148 kb
Host smart-26c85808-859f-4c00-8c8b-3572a9b6b2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432125362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2432125362
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2485810240
Short name T12
Test name
Test status
Simulation time 44511103 ps
CPU time 1.05 seconds
Started Aug 03 05:51:57 PM PDT 24
Finished Aug 03 05:51:58 PM PDT 24
Peak memory 220000 kb
Host smart-1e300530-f8f7-4e82-876b-83b2c575a719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485810240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2485810240
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.2249320981
Short name T627
Test name
Test status
Simulation time 78838077 ps
CPU time 1.24 seconds
Started Aug 03 05:52:00 PM PDT 24
Finished Aug 03 05:52:01 PM PDT 24
Peak memory 218976 kb
Host smart-4e9e5f79-c3f5-4943-9bda-d5a824735150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249320981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.2249320981
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3997482174
Short name T927
Test name
Test status
Simulation time 39013027 ps
CPU time 1.29 seconds
Started Aug 03 05:52:00 PM PDT 24
Finished Aug 03 05:52:01 PM PDT 24
Peak memory 218676 kb
Host smart-c0abbfb8-dabd-4e2b-a535-cb4f15f72853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997482174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3997482174
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.26793427
Short name T523
Test name
Test status
Simulation time 145218936 ps
CPU time 1.12 seconds
Started Aug 03 05:52:02 PM PDT 24
Finished Aug 03 05:52:03 PM PDT 24
Peak memory 218796 kb
Host smart-ea6d2dfe-d1b5-42e2-9af8-df02a9aaaaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26793427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.26793427
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/149.edn_alert.1431005556
Short name T793
Test name
Test status
Simulation time 108402967 ps
CPU time 1.34 seconds
Started Aug 03 05:52:06 PM PDT 24
Finished Aug 03 05:52:08 PM PDT 24
Peak memory 218548 kb
Host smart-2af51c6c-acfe-4ba3-843b-68d1e921c9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431005556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1431005556
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.3076726067
Short name T454
Test name
Test status
Simulation time 33202639 ps
CPU time 1.05 seconds
Started Aug 03 05:52:03 PM PDT 24
Finished Aug 03 05:52:05 PM PDT 24
Peak memory 217260 kb
Host smart-5df6d2d5-af68-4426-83c0-dd7a63f060cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076726067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3076726067
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.2560405754
Short name T756
Test name
Test status
Simulation time 35697784 ps
CPU time 0.81 seconds
Started Aug 03 05:48:31 PM PDT 24
Finished Aug 03 05:48:32 PM PDT 24
Peak memory 206344 kb
Host smart-968937d8-2bf7-486d-8d3a-f876188d39ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560405754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2560405754
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3313425203
Short name T590
Test name
Test status
Simulation time 17526847 ps
CPU time 0.82 seconds
Started Aug 03 05:48:30 PM PDT 24
Finished Aug 03 05:48:31 PM PDT 24
Peak memory 215396 kb
Host smart-6bc360d7-13ef-4bf0-a603-9681b8420ee8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313425203 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3313425203
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1252954893
Short name T184
Test name
Test status
Simulation time 80431607 ps
CPU time 1.04 seconds
Started Aug 03 05:48:28 PM PDT 24
Finished Aug 03 05:48:29 PM PDT 24
Peak memory 216796 kb
Host smart-e7226092-cbeb-499e-abe6-1a91e28f72e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252954893 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1252954893
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3956666712
Short name T634
Test name
Test status
Simulation time 33676070 ps
CPU time 0.97 seconds
Started Aug 03 05:48:29 PM PDT 24
Finished Aug 03 05:48:31 PM PDT 24
Peak memory 219916 kb
Host smart-0e3b4eeb-ed70-4893-95c2-2526e065b476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956666712 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3956666712
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1529370842
Short name T928
Test name
Test status
Simulation time 53051835 ps
CPU time 1.56 seconds
Started Aug 03 05:48:23 PM PDT 24
Finished Aug 03 05:48:25 PM PDT 24
Peak memory 218544 kb
Host smart-46935906-55ed-4881-b216-0ea33b6eb9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529370842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1529370842
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.256521623
Short name T92
Test name
Test status
Simulation time 27915057 ps
CPU time 0.85 seconds
Started Aug 03 05:48:27 PM PDT 24
Finished Aug 03 05:48:28 PM PDT 24
Peak memory 215644 kb
Host smart-dea9e4b1-a918-4d05-9adf-79645f1e3284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256521623 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.256521623
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2312329101
Short name T936
Test name
Test status
Simulation time 23491102 ps
CPU time 0.9 seconds
Started Aug 03 05:48:22 PM PDT 24
Finished Aug 03 05:48:23 PM PDT 24
Peak memory 215252 kb
Host smart-3d183f15-bffd-497b-8d87-6e526229676e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312329101 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2312329101
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1080758
Short name T583
Test name
Test status
Simulation time 259217258 ps
CPU time 3.27 seconds
Started Aug 03 05:48:24 PM PDT 24
Finished Aug 03 05:48:27 PM PDT 24
Peak memory 217200 kb
Host smart-2bd49375-9845-4912-aeae-f671973cd2bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080758 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1080758
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2185290404
Short name T557
Test name
Test status
Simulation time 128869528740 ps
CPU time 1475.03 seconds
Started Aug 03 05:48:28 PM PDT 24
Finished Aug 03 06:13:03 PM PDT 24
Peak memory 223820 kb
Host smart-d2a9bdc8-4f94-48aa-af4c-2994d843c2ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185290404 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2185290404
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.1573220440
Short name T176
Test name
Test status
Simulation time 24072813 ps
CPU time 1.15 seconds
Started Aug 03 05:52:04 PM PDT 24
Finished Aug 03 05:52:05 PM PDT 24
Peak memory 218560 kb
Host smart-48ba426a-18d9-401f-bbf6-e861dc4dee20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573220440 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.1573220440
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.678958448
Short name T328
Test name
Test status
Simulation time 67339335 ps
CPU time 1.36 seconds
Started Aug 03 05:52:05 PM PDT 24
Finished Aug 03 05:52:06 PM PDT 24
Peak memory 217300 kb
Host smart-37940bb3-ad85-4528-a9f8-b2a69a0adbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678958448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.678958448
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.660468950
Short name T470
Test name
Test status
Simulation time 32953909 ps
CPU time 1.07 seconds
Started Aug 03 05:52:03 PM PDT 24
Finished Aug 03 05:52:05 PM PDT 24
Peak memory 218768 kb
Host smart-325410de-7ba4-49db-9f0f-1d7acb9f6ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660468950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.660468950
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.2899712440
Short name T525
Test name
Test status
Simulation time 46566110 ps
CPU time 1.27 seconds
Started Aug 03 05:52:06 PM PDT 24
Finished Aug 03 05:52:07 PM PDT 24
Peak memory 219740 kb
Host smart-4ff360a7-7d57-45cc-9f73-b77425dbf70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899712440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2899712440
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.2309591584
Short name T985
Test name
Test status
Simulation time 40110887 ps
CPU time 1.17 seconds
Started Aug 03 05:52:02 PM PDT 24
Finished Aug 03 05:52:03 PM PDT 24
Peak memory 218720 kb
Host smart-2c225b94-c731-49d2-ac4f-cd0c6aec787d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309591584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2309591584
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.666515355
Short name T452
Test name
Test status
Simulation time 21438298 ps
CPU time 1.19 seconds
Started Aug 03 05:52:04 PM PDT 24
Finished Aug 03 05:52:05 PM PDT 24
Peak memory 219552 kb
Host smart-3d4b9617-8968-4f17-8a1e-cc8b806f546b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666515355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.666515355
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.3921843630
Short name T974
Test name
Test status
Simulation time 31709433 ps
CPU time 1.36 seconds
Started Aug 03 05:52:04 PM PDT 24
Finished Aug 03 05:52:05 PM PDT 24
Peak memory 215684 kb
Host smart-1ad65c06-bf63-4f69-8cf9-b22d9f2038e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921843630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3921843630
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3114315646
Short name T881
Test name
Test status
Simulation time 56623099 ps
CPU time 1.5 seconds
Started Aug 03 05:52:06 PM PDT 24
Finished Aug 03 05:52:08 PM PDT 24
Peak memory 218540 kb
Host smart-c296548a-b047-4cb4-a37f-ec0e960fb7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114315646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3114315646
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.1499166341
Short name T748
Test name
Test status
Simulation time 54221665 ps
CPU time 1.34 seconds
Started Aug 03 05:52:03 PM PDT 24
Finished Aug 03 05:52:04 PM PDT 24
Peak memory 218744 kb
Host smart-4e2fa5ed-760e-41dd-a38b-de3d40dbb50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499166341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1499166341
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1185412946
Short name T377
Test name
Test status
Simulation time 41956201 ps
CPU time 1.06 seconds
Started Aug 03 05:52:04 PM PDT 24
Finished Aug 03 05:52:05 PM PDT 24
Peak memory 218412 kb
Host smart-fa76bdd2-0d0b-4eed-9586-083452233d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185412946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1185412946
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.1773087505
Short name T973
Test name
Test status
Simulation time 68233186 ps
CPU time 1.15 seconds
Started Aug 03 05:52:03 PM PDT 24
Finished Aug 03 05:52:05 PM PDT 24
Peak memory 219616 kb
Host smart-b2e39326-d903-44b9-bf49-62c44cce4f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773087505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.1773087505
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1337380282
Short name T934
Test name
Test status
Simulation time 100903156 ps
CPU time 1.61 seconds
Started Aug 03 05:52:08 PM PDT 24
Finished Aug 03 05:52:09 PM PDT 24
Peak memory 218972 kb
Host smart-c90277c9-cb98-49af-ac57-fb05c7044e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337380282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1337380282
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.2100801147
Short name T218
Test name
Test status
Simulation time 31418700 ps
CPU time 1.29 seconds
Started Aug 03 05:52:05 PM PDT 24
Finished Aug 03 05:52:06 PM PDT 24
Peak memory 215660 kb
Host smart-d0210747-1491-4d07-bea9-d8ff19ba9d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100801147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.2100801147
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3892046676
Short name T686
Test name
Test status
Simulation time 40728912 ps
CPU time 1.5 seconds
Started Aug 03 05:52:05 PM PDT 24
Finished Aug 03 05:52:06 PM PDT 24
Peak memory 220020 kb
Host smart-23db92f7-9d36-44be-8cdf-e81ed5d0dd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892046676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3892046676
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.1341170357
Short name T479
Test name
Test status
Simulation time 58570345 ps
CPU time 1.22 seconds
Started Aug 03 05:52:10 PM PDT 24
Finished Aug 03 05:52:11 PM PDT 24
Peak memory 218548 kb
Host smart-e93c20b1-a7b6-417f-8555-e44d4701129f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341170357 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1341170357
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.4186596575
Short name T808
Test name
Test status
Simulation time 81433276 ps
CPU time 1.08 seconds
Started Aug 03 05:52:06 PM PDT 24
Finished Aug 03 05:52:07 PM PDT 24
Peak memory 218856 kb
Host smart-d0deba71-3776-4470-b9a8-2f01267c9749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186596575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.4186596575
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3926125479
Short name T158
Test name
Test status
Simulation time 58342198 ps
CPU time 1.24 seconds
Started Aug 03 05:52:09 PM PDT 24
Finished Aug 03 05:52:11 PM PDT 24
Peak memory 219116 kb
Host smart-3441d68d-5cb7-48ca-ba1b-730aa8d902b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926125479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3926125479
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.2475581319
Short name T512
Test name
Test status
Simulation time 211005183 ps
CPU time 2.55 seconds
Started Aug 03 05:52:10 PM PDT 24
Finished Aug 03 05:52:12 PM PDT 24
Peak memory 217732 kb
Host smart-67a2b753-c3ed-4484-ad04-3cfb3a8b8fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475581319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2475581319
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.670798958
Short name T637
Test name
Test status
Simulation time 22673870 ps
CPU time 1.13 seconds
Started Aug 03 05:52:11 PM PDT 24
Finished Aug 03 05:52:12 PM PDT 24
Peak memory 218560 kb
Host smart-4f8798c7-e7bb-4f17-969b-6af145dd1b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670798958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.670798958
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1619865727
Short name T309
Test name
Test status
Simulation time 59688483 ps
CPU time 1.74 seconds
Started Aug 03 05:52:12 PM PDT 24
Finished Aug 03 05:52:14 PM PDT 24
Peak memory 220200 kb
Host smart-1312a38a-b7b2-4ff2-94ab-9c9b795d040e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619865727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1619865727
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2488880833
Short name T301
Test name
Test status
Simulation time 43066298 ps
CPU time 1.22 seconds
Started Aug 03 05:48:35 PM PDT 24
Finished Aug 03 05:48:36 PM PDT 24
Peak memory 220260 kb
Host smart-77909376-119f-4572-8f34-8eb4a12dabde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488880833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2488880833
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.33624241
Short name T55
Test name
Test status
Simulation time 14734504 ps
CPU time 0.96 seconds
Started Aug 03 05:48:37 PM PDT 24
Finished Aug 03 05:48:38 PM PDT 24
Peak memory 214884 kb
Host smart-15c1d926-84b6-4989-bcd8-240a9899c48d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33624241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.33624241
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1533993731
Short name T371
Test name
Test status
Simulation time 37625808 ps
CPU time 1.24 seconds
Started Aug 03 05:48:30 PM PDT 24
Finished Aug 03 05:48:32 PM PDT 24
Peak memory 218424 kb
Host smart-37c15166-f5bb-432e-8393-0f5f25ccc000
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533993731 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1533993731
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.4008649326
Short name T437
Test name
Test status
Simulation time 54442604 ps
CPU time 1.05 seconds
Started Aug 03 05:48:30 PM PDT 24
Finished Aug 03 05:48:31 PM PDT 24
Peak memory 218716 kb
Host smart-69eed570-5b1e-4cd2-b299-f292f608aefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008649326 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.4008649326
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.968298575
Short name T990
Test name
Test status
Simulation time 95122065 ps
CPU time 1.24 seconds
Started Aug 03 05:48:30 PM PDT 24
Finished Aug 03 05:48:32 PM PDT 24
Peak memory 217388 kb
Host smart-3fc8ad61-fcc8-4ac6-8d86-2d265255abd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968298575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.968298575
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2540497891
Short name T779
Test name
Test status
Simulation time 21304960 ps
CPU time 1.01 seconds
Started Aug 03 05:48:31 PM PDT 24
Finished Aug 03 05:48:32 PM PDT 24
Peak memory 215928 kb
Host smart-847ff98c-378f-4ed9-92e0-c73335336b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540497891 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2540497891
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2014838860
Short name T683
Test name
Test status
Simulation time 37550591 ps
CPU time 0.91 seconds
Started Aug 03 05:48:31 PM PDT 24
Finished Aug 03 05:48:32 PM PDT 24
Peak memory 215292 kb
Host smart-4a3c02a7-526a-4766-b4e2-f5950be4dc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014838860 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2014838860
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.401997227
Short name T456
Test name
Test status
Simulation time 108361393 ps
CPU time 1.61 seconds
Started Aug 03 05:48:31 PM PDT 24
Finished Aug 03 05:48:32 PM PDT 24
Peak memory 218460 kb
Host smart-08a9771b-fbac-4fdc-97e1-8b82d9328682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401997227 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.401997227
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2052836999
Short name T949
Test name
Test status
Simulation time 33433134857 ps
CPU time 414.88 seconds
Started Aug 03 05:48:28 PM PDT 24
Finished Aug 03 05:55:23 PM PDT 24
Peak memory 218156 kb
Host smart-f147bea3-1c68-4a27-89fc-16ee749e9c29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052836999 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2052836999
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3155414348
Short name T813
Test name
Test status
Simulation time 24038786 ps
CPU time 1.22 seconds
Started Aug 03 05:52:08 PM PDT 24
Finished Aug 03 05:52:10 PM PDT 24
Peak memory 219672 kb
Host smart-5752de4f-e6c4-46a5-a3db-a2e9ae7aeffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155414348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3155414348
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.4252130036
Short name T754
Test name
Test status
Simulation time 58999736 ps
CPU time 1.7 seconds
Started Aug 03 05:52:08 PM PDT 24
Finished Aug 03 05:52:10 PM PDT 24
Peak memory 218864 kb
Host smart-8246d16a-3f5d-4b10-8c48-765ac8f9f4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252130036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.4252130036
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.273949946
Short name T144
Test name
Test status
Simulation time 365037307 ps
CPU time 1.32 seconds
Started Aug 03 05:52:10 PM PDT 24
Finished Aug 03 05:52:11 PM PDT 24
Peak memory 218364 kb
Host smart-95a7a5f2-000a-4fb8-b851-28912c4acad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273949946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.273949946
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.1888613385
Short name T390
Test name
Test status
Simulation time 65438257 ps
CPU time 1.06 seconds
Started Aug 03 05:52:09 PM PDT 24
Finished Aug 03 05:52:10 PM PDT 24
Peak memory 217228 kb
Host smart-1209b479-2122-4d0e-90c0-76765db3e164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888613385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1888613385
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1159781325
Short name T920
Test name
Test status
Simulation time 148878749 ps
CPU time 1.99 seconds
Started Aug 03 05:52:10 PM PDT 24
Finished Aug 03 05:52:12 PM PDT 24
Peak memory 217452 kb
Host smart-641ff46f-ab24-47bd-b973-27cb2496a4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159781325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1159781325
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1099114327
Short name T526
Test name
Test status
Simulation time 82714012 ps
CPU time 1.38 seconds
Started Aug 03 05:52:09 PM PDT 24
Finished Aug 03 05:52:10 PM PDT 24
Peak memory 215688 kb
Host smart-f1f56926-448a-407d-a665-d7465a0160ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099114327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1099114327
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.3146857565
Short name T412
Test name
Test status
Simulation time 41257288 ps
CPU time 1.59 seconds
Started Aug 03 05:52:11 PM PDT 24
Finished Aug 03 05:52:13 PM PDT 24
Peak memory 220048 kb
Host smart-48abdf2c-63ea-4bdf-8565-15baff13016c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146857565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3146857565
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2265461277
Short name T19
Test name
Test status
Simulation time 33429578 ps
CPU time 1.39 seconds
Started Aug 03 05:52:10 PM PDT 24
Finished Aug 03 05:52:12 PM PDT 24
Peak memory 219836 kb
Host smart-a85fd272-de64-4d0f-95b4-f463f50525ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265461277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2265461277
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2259034145
Short name T327
Test name
Test status
Simulation time 89486097 ps
CPU time 1.34 seconds
Started Aug 03 05:52:09 PM PDT 24
Finished Aug 03 05:52:11 PM PDT 24
Peak memory 218532 kb
Host smart-9c6122bd-cc79-46d8-a617-013ed91edd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259034145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2259034145
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3754529919
Short name T571
Test name
Test status
Simulation time 76100272 ps
CPU time 1.22 seconds
Started Aug 03 05:52:15 PM PDT 24
Finished Aug 03 05:52:17 PM PDT 24
Peak memory 221544 kb
Host smart-18f20a5f-e83e-48b1-aae1-a707667758b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754529919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3754529919
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.2577113458
Short name T633
Test name
Test status
Simulation time 41171027 ps
CPU time 1.1 seconds
Started Aug 03 05:52:14 PM PDT 24
Finished Aug 03 05:52:15 PM PDT 24
Peak memory 217340 kb
Host smart-491015f1-3525-41d6-88d5-894ea2a1c1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577113458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2577113458
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.2095055225
Short name T585
Test name
Test status
Simulation time 22692744 ps
CPU time 1.1 seconds
Started Aug 03 05:52:14 PM PDT 24
Finished Aug 03 05:52:16 PM PDT 24
Peak memory 218628 kb
Host smart-f98ed140-7078-46e9-8ef1-d2c16ff95b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095055225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2095055225
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.2722907358
Short name T705
Test name
Test status
Simulation time 246111771 ps
CPU time 3.6 seconds
Started Aug 03 05:52:18 PM PDT 24
Finished Aug 03 05:52:21 PM PDT 24
Peak memory 220272 kb
Host smart-a7788198-a03a-4863-9433-cf6a744fd20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722907358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2722907358
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1396142929
Short name T36
Test name
Test status
Simulation time 164963911 ps
CPU time 1.27 seconds
Started Aug 03 05:52:17 PM PDT 24
Finished Aug 03 05:52:19 PM PDT 24
Peak memory 218424 kb
Host smart-0b4e56f2-514d-436e-bc10-8fe1c8ada66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396142929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1396142929
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.343589296
Short name T242
Test name
Test status
Simulation time 353279900 ps
CPU time 3.65 seconds
Started Aug 03 05:52:13 PM PDT 24
Finished Aug 03 05:52:17 PM PDT 24
Peak memory 218852 kb
Host smart-36c8bde9-e17d-417f-91e2-0ab4edd792c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343589296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.343589296
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.3945759678
Short name T814
Test name
Test status
Simulation time 98335155 ps
CPU time 1.3 seconds
Started Aug 03 05:52:15 PM PDT 24
Finished Aug 03 05:52:17 PM PDT 24
Peak memory 221608 kb
Host smart-5d2bf125-353a-4a3f-9c94-5b769b91e7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945759678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3945759678
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.4251026342
Short name T709
Test name
Test status
Simulation time 74231801 ps
CPU time 1.26 seconds
Started Aug 03 05:52:16 PM PDT 24
Finished Aug 03 05:52:17 PM PDT 24
Peak memory 218576 kb
Host smart-aeff4184-8dff-4f62-97b3-2a7da96d9fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251026342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.4251026342
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.1060133470
Short name T542
Test name
Test status
Simulation time 30622621 ps
CPU time 1.34 seconds
Started Aug 03 05:52:15 PM PDT 24
Finished Aug 03 05:52:17 PM PDT 24
Peak memory 218732 kb
Host smart-731b675d-139e-40ce-851f-cfcab32ebabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060133470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1060133470
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.2391135623
Short name T626
Test name
Test status
Simulation time 37394113 ps
CPU time 1.38 seconds
Started Aug 03 05:52:17 PM PDT 24
Finished Aug 03 05:52:19 PM PDT 24
Peak memory 219952 kb
Host smart-fc40c4e9-710b-4191-820f-296b5ae3d310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391135623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2391135623
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.4013153392
Short name T612
Test name
Test status
Simulation time 25917518 ps
CPU time 1.28 seconds
Started Aug 03 05:48:34 PM PDT 24
Finished Aug 03 05:48:35 PM PDT 24
Peak memory 219168 kb
Host smart-34591d7c-d022-4884-b933-6ce352e0cb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013153392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.4013153392
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3683446089
Short name T666
Test name
Test status
Simulation time 20908515 ps
CPU time 1 seconds
Started Aug 03 05:48:32 PM PDT 24
Finished Aug 03 05:48:33 PM PDT 24
Peak memory 206716 kb
Host smart-262342ee-0d87-4d2c-9d4d-c01e21f2165f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683446089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3683446089
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_err.961028449
Short name T61
Test name
Test status
Simulation time 98246265 ps
CPU time 0.84 seconds
Started Aug 03 05:48:32 PM PDT 24
Finished Aug 03 05:48:33 PM PDT 24
Peak memory 218224 kb
Host smart-79273233-e208-4fd5-ab85-0b01021d140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961028449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.961028449
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2596922141
Short name T508
Test name
Test status
Simulation time 100599912 ps
CPU time 1.19 seconds
Started Aug 03 05:48:35 PM PDT 24
Finished Aug 03 05:48:36 PM PDT 24
Peak memory 218356 kb
Host smart-f6b02ae1-25f2-42fb-9aad-e9be090e3d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596922141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2596922141
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1407564677
Short name T984
Test name
Test status
Simulation time 26821679 ps
CPU time 0.91 seconds
Started Aug 03 05:48:32 PM PDT 24
Finished Aug 03 05:48:33 PM PDT 24
Peak memory 215556 kb
Host smart-2255ba99-50f7-4e0f-911c-c58dbd9b90ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407564677 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1407564677
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3298641262
Short name T987
Test name
Test status
Simulation time 36844761 ps
CPU time 0.88 seconds
Started Aug 03 05:48:34 PM PDT 24
Finished Aug 03 05:48:35 PM PDT 24
Peak memory 215244 kb
Host smart-0536f445-4871-43c2-a07a-8fbae7703256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298641262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3298641262
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1426414903
Short name T135
Test name
Test status
Simulation time 236594545 ps
CPU time 2.65 seconds
Started Aug 03 05:48:33 PM PDT 24
Finished Aug 03 05:48:36 PM PDT 24
Peak memory 217164 kb
Host smart-a60ad364-56a2-4bbd-98d2-64d8f22be85f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426414903 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1426414903
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/170.edn_alert.2827677640
Short name T204
Test name
Test status
Simulation time 25157945 ps
CPU time 1.15 seconds
Started Aug 03 05:52:13 PM PDT 24
Finished Aug 03 05:52:14 PM PDT 24
Peak memory 218396 kb
Host smart-84c71872-b6a9-4ed2-8592-297df97b346b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827677640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2827677640
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.3916777914
Short name T702
Test name
Test status
Simulation time 56361999 ps
CPU time 1.6 seconds
Started Aug 03 05:52:18 PM PDT 24
Finished Aug 03 05:52:20 PM PDT 24
Peak memory 217228 kb
Host smart-368fda57-a040-4380-b03c-34e75b7dd079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916777914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3916777914
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.669393679
Short name T250
Test name
Test status
Simulation time 85840276 ps
CPU time 1.19 seconds
Started Aug 03 05:52:15 PM PDT 24
Finished Aug 03 05:52:17 PM PDT 24
Peak memory 219092 kb
Host smart-ea3467e0-e956-4e55-b3fd-aec52a79419d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669393679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.669393679
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.1551479750
Short name T791
Test name
Test status
Simulation time 85577852 ps
CPU time 3.06 seconds
Started Aug 03 05:52:14 PM PDT 24
Finished Aug 03 05:52:17 PM PDT 24
Peak memory 220180 kb
Host smart-794e7147-ccf2-4d37-9cd6-36041bdcd8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551479750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1551479750
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.3429884110
Short name T971
Test name
Test status
Simulation time 135933275 ps
CPU time 1.08 seconds
Started Aug 03 05:52:15 PM PDT 24
Finished Aug 03 05:52:16 PM PDT 24
Peak memory 218668 kb
Host smart-603d3c54-cbad-4e4e-84ed-1d693fa3f13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429884110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.3429884110
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.2597431894
Short name T587
Test name
Test status
Simulation time 39581300 ps
CPU time 1.11 seconds
Started Aug 03 05:52:18 PM PDT 24
Finished Aug 03 05:52:19 PM PDT 24
Peak memory 217232 kb
Host smart-f6fd9fe0-03fe-4ab9-9837-e406e0d36732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597431894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2597431894
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.52851345
Short name T696
Test name
Test status
Simulation time 64896323 ps
CPU time 1.04 seconds
Started Aug 03 05:52:14 PM PDT 24
Finished Aug 03 05:52:15 PM PDT 24
Peak memory 218332 kb
Host smart-6f3d9358-3100-4b41-87c5-748a30121d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52851345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.52851345
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/174.edn_alert.3856804902
Short name T207
Test name
Test status
Simulation time 144363719 ps
CPU time 1.15 seconds
Started Aug 03 05:52:15 PM PDT 24
Finished Aug 03 05:52:16 PM PDT 24
Peak memory 219808 kb
Host smart-2af5ddda-283d-4a60-8259-29d9e36a392b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856804902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3856804902
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/175.edn_alert.3058725986
Short name T78
Test name
Test status
Simulation time 87146785 ps
CPU time 1.25 seconds
Started Aug 03 05:52:23 PM PDT 24
Finished Aug 03 05:52:25 PM PDT 24
Peak memory 220364 kb
Host smart-b317f72d-8459-451f-b99b-948bec7e6e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058725986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3058725986
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.3727292435
Short name T315
Test name
Test status
Simulation time 103933603 ps
CPU time 1.18 seconds
Started Aug 03 05:52:19 PM PDT 24
Finished Aug 03 05:52:20 PM PDT 24
Peak memory 219808 kb
Host smart-7cd2b565-f850-41da-b4ed-474bb757798a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727292435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3727292435
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1503214014
Short name T594
Test name
Test status
Simulation time 32186498 ps
CPU time 1.07 seconds
Started Aug 03 05:52:19 PM PDT 24
Finished Aug 03 05:52:20 PM PDT 24
Peak memory 217340 kb
Host smart-09750a0a-0427-4eca-ba9b-76d59d6517cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503214014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1503214014
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.111612906
Short name T441
Test name
Test status
Simulation time 63370719 ps
CPU time 1.12 seconds
Started Aug 03 05:52:21 PM PDT 24
Finished Aug 03 05:52:23 PM PDT 24
Peak memory 220016 kb
Host smart-862783c5-cbb8-43de-afe2-01bdefd2da36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111612906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.111612906
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.1469656478
Short name T496
Test name
Test status
Simulation time 253572953 ps
CPU time 1.07 seconds
Started Aug 03 05:52:23 PM PDT 24
Finished Aug 03 05:52:25 PM PDT 24
Peak memory 217184 kb
Host smart-652fba24-b01d-45d2-9a98-a59f518cc164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469656478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1469656478
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.1269649877
Short name T529
Test name
Test status
Simulation time 55480618 ps
CPU time 1.25 seconds
Started Aug 03 05:52:19 PM PDT 24
Finished Aug 03 05:52:20 PM PDT 24
Peak memory 215712 kb
Host smart-329de71f-e8fd-47f2-b5c1-f79b162e4934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269649877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.1269649877
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.1691690519
Short name T527
Test name
Test status
Simulation time 171270709 ps
CPU time 1.09 seconds
Started Aug 03 05:52:19 PM PDT 24
Finished Aug 03 05:52:20 PM PDT 24
Peak memory 217396 kb
Host smart-23fd75ab-5b05-4ae4-961a-a25681323f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691690519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1691690519
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.1992244822
Short name T577
Test name
Test status
Simulation time 62339125 ps
CPU time 1.04 seconds
Started Aug 03 05:52:21 PM PDT 24
Finished Aug 03 05:52:22 PM PDT 24
Peak memory 219764 kb
Host smart-8ece3464-b0b9-4f14-9e29-deff7458ba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992244822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.1992244822
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2205782150
Short name T914
Test name
Test status
Simulation time 33442134 ps
CPU time 1.17 seconds
Started Aug 03 05:52:19 PM PDT 24
Finished Aug 03 05:52:20 PM PDT 24
Peak memory 217152 kb
Host smart-3ace4d0c-d8f9-47e7-924c-58ea3f25f967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205782150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2205782150
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.186460626
Short name T863
Test name
Test status
Simulation time 29484137 ps
CPU time 1.18 seconds
Started Aug 03 05:48:42 PM PDT 24
Finished Aug 03 05:48:43 PM PDT 24
Peak memory 218928 kb
Host smart-4ce1492b-3696-4721-9b9a-115a9322a939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186460626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.186460626
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2028941078
Short name T342
Test name
Test status
Simulation time 51532714 ps
CPU time 0.85 seconds
Started Aug 03 05:48:39 PM PDT 24
Finished Aug 03 05:48:40 PM PDT 24
Peak memory 214808 kb
Host smart-8e48b0a8-067e-420e-9d6e-0dced0f0b868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028941078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2028941078
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.852695551
Short name T619
Test name
Test status
Simulation time 79930941 ps
CPU time 1.03 seconds
Started Aug 03 05:48:40 PM PDT 24
Finished Aug 03 05:48:41 PM PDT 24
Peak memory 218372 kb
Host smart-891b692d-50ce-4e71-90b2-effda8b1b6a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852695551 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.852695551
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.4197889283
Short name T434
Test name
Test status
Simulation time 34565983 ps
CPU time 0.93 seconds
Started Aug 03 05:48:41 PM PDT 24
Finished Aug 03 05:48:42 PM PDT 24
Peak memory 223856 kb
Host smart-4e503b1e-3a3d-4a76-9428-4a9a2002c512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197889283 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.4197889283
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2983329475
Short name T846
Test name
Test status
Simulation time 95295243 ps
CPU time 1.06 seconds
Started Aug 03 05:48:39 PM PDT 24
Finished Aug 03 05:48:40 PM PDT 24
Peak memory 217296 kb
Host smart-c92401df-0725-489e-a149-3903d13937e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983329475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2983329475
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2619587833
Short name T728
Test name
Test status
Simulation time 25183171 ps
CPU time 0.97 seconds
Started Aug 03 05:48:41 PM PDT 24
Finished Aug 03 05:48:42 PM PDT 24
Peak memory 215524 kb
Host smart-b775a93e-da66-4993-bda3-677a863468b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619587833 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2619587833
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3206757659
Short name T442
Test name
Test status
Simulation time 18509299 ps
CPU time 1.06 seconds
Started Aug 03 05:48:33 PM PDT 24
Finished Aug 03 05:48:34 PM PDT 24
Peak memory 215272 kb
Host smart-a8db8972-1799-481e-85b7-271cc8e1d6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206757659 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3206757659
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2024173353
Short name T355
Test name
Test status
Simulation time 299414328 ps
CPU time 1.79 seconds
Started Aug 03 05:48:41 PM PDT 24
Finished Aug 03 05:48:43 PM PDT 24
Peak memory 217244 kb
Host smart-35f0978e-3a1d-4438-8f1c-05f86ea99627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024173353 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2024173353
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3327576012
Short name T930
Test name
Test status
Simulation time 96655704334 ps
CPU time 1180.1 seconds
Started Aug 03 05:48:39 PM PDT 24
Finished Aug 03 06:08:20 PM PDT 24
Peak memory 222852 kb
Host smart-bfcaf8fc-b2e1-4a1a-b0f8-bcee96496676
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327576012 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3327576012
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.2347080615
Short name T663
Test name
Test status
Simulation time 48572737 ps
CPU time 1.18 seconds
Started Aug 03 05:52:24 PM PDT 24
Finished Aug 03 05:52:26 PM PDT 24
Peak memory 220116 kb
Host smart-8db98f14-c3f4-4bd9-8f66-b22dac7af383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347080615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2347080615
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2866501047
Short name T929
Test name
Test status
Simulation time 168641541 ps
CPU time 2.1 seconds
Started Aug 03 05:52:25 PM PDT 24
Finished Aug 03 05:52:27 PM PDT 24
Peak memory 218844 kb
Host smart-6624a828-4520-4e3e-b607-a22968a0d43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866501047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2866501047
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.3685469320
Short name T252
Test name
Test status
Simulation time 50950202 ps
CPU time 1.23 seconds
Started Aug 03 05:52:27 PM PDT 24
Finished Aug 03 05:52:28 PM PDT 24
Peak memory 219404 kb
Host smart-8c53ef61-9ea4-465a-b092-c297862c3e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685469320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.3685469320
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.84521673
Short name T495
Test name
Test status
Simulation time 176192778 ps
CPU time 1.63 seconds
Started Aug 03 05:52:25 PM PDT 24
Finished Aug 03 05:52:26 PM PDT 24
Peak memory 218676 kb
Host smart-56abf1e8-4449-4bcc-9239-414c2319d246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84521673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.84521673
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3435108259
Short name T293
Test name
Test status
Simulation time 24453867 ps
CPU time 1.2 seconds
Started Aug 03 05:52:24 PM PDT 24
Finished Aug 03 05:52:26 PM PDT 24
Peak memory 219720 kb
Host smart-868b7673-b335-4886-9f55-effe385a8c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435108259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3435108259
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.1861037438
Short name T939
Test name
Test status
Simulation time 33872491 ps
CPU time 1.5 seconds
Started Aug 03 05:52:27 PM PDT 24
Finished Aug 03 05:52:29 PM PDT 24
Peak memory 218440 kb
Host smart-15296e98-8be5-4df6-a75d-43aa47ed125d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861037438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1861037438
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.2715277489
Short name T253
Test name
Test status
Simulation time 47422823 ps
CPU time 1.23 seconds
Started Aug 03 05:52:24 PM PDT 24
Finished Aug 03 05:52:25 PM PDT 24
Peak memory 219136 kb
Host smart-32484814-7a4f-4420-a526-93e7748b186b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715277489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.2715277489
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.1589291060
Short name T516
Test name
Test status
Simulation time 76990175 ps
CPU time 1.1 seconds
Started Aug 03 05:52:27 PM PDT 24
Finished Aug 03 05:52:28 PM PDT 24
Peak memory 217284 kb
Host smart-bf7da1e2-e7e6-4ef0-8ed6-b186bb41b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589291060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1589291060
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.3509846726
Short name T596
Test name
Test status
Simulation time 37480685 ps
CPU time 1.13 seconds
Started Aug 03 05:52:24 PM PDT 24
Finished Aug 03 05:52:25 PM PDT 24
Peak memory 219804 kb
Host smart-fc24fcb0-3000-4ad6-bd19-d04e0205034c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509846726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3509846726
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.3500349928
Short name T63
Test name
Test status
Simulation time 42033776 ps
CPU time 1.89 seconds
Started Aug 03 05:52:26 PM PDT 24
Finished Aug 03 05:52:28 PM PDT 24
Peak memory 220020 kb
Host smart-2cef74dc-1408-4b49-8add-de6371d31979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500349928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3500349928
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.2580023283
Short name T156
Test name
Test status
Simulation time 113853514 ps
CPU time 1.34 seconds
Started Aug 03 05:52:24 PM PDT 24
Finished Aug 03 05:52:25 PM PDT 24
Peak memory 218380 kb
Host smart-6fc54e22-d4a8-478c-9346-724ef32406ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580023283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2580023283
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.743772949
Short name T17
Test name
Test status
Simulation time 48087641 ps
CPU time 1.43 seconds
Started Aug 03 05:52:24 PM PDT 24
Finished Aug 03 05:52:26 PM PDT 24
Peak memory 219568 kb
Host smart-075c9a4f-8518-4d3f-bea6-7b8a8fd2008b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743772949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.743772949
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2163850645
Short name T675
Test name
Test status
Simulation time 103391012 ps
CPU time 1.24 seconds
Started Aug 03 05:52:31 PM PDT 24
Finished Aug 03 05:52:32 PM PDT 24
Peak memory 215672 kb
Host smart-a86596f7-9319-405c-a569-a6b164d71d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163850645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2163850645
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.3125983594
Short name T788
Test name
Test status
Simulation time 103287307 ps
CPU time 1.45 seconds
Started Aug 03 05:52:36 PM PDT 24
Finished Aug 03 05:52:37 PM PDT 24
Peak memory 218652 kb
Host smart-0a9b4d07-daa0-4651-81fb-34c77fda1504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125983594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3125983594
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1514015322
Short name T695
Test name
Test status
Simulation time 27921989 ps
CPU time 1.29 seconds
Started Aug 03 05:52:33 PM PDT 24
Finished Aug 03 05:52:35 PM PDT 24
Peak memory 218740 kb
Host smart-3d36b8db-59da-4136-a2a2-1ccf58c18b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514015322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1514015322
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.4116237810
Short name T444
Test name
Test status
Simulation time 90720213 ps
CPU time 1.29 seconds
Started Aug 03 05:52:33 PM PDT 24
Finished Aug 03 05:52:34 PM PDT 24
Peak memory 218332 kb
Host smart-df8f8c23-30aa-4c16-9971-ac4636b379c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116237810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.4116237810
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.3645294371
Short name T845
Test name
Test status
Simulation time 56779080 ps
CPU time 1.31 seconds
Started Aug 03 05:52:31 PM PDT 24
Finished Aug 03 05:52:33 PM PDT 24
Peak memory 215648 kb
Host smart-3dc04bf9-ee5c-4d93-b806-a76d4b5ddabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645294371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.3645294371
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.378535552
Short name T593
Test name
Test status
Simulation time 78515627 ps
CPU time 1.32 seconds
Started Aug 03 05:52:37 PM PDT 24
Finished Aug 03 05:52:39 PM PDT 24
Peak memory 218964 kb
Host smart-8efc2f0f-3875-4de4-94da-8d0ea637566d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378535552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.378535552
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3039715735
Short name T639
Test name
Test status
Simulation time 29239327 ps
CPU time 1.28 seconds
Started Aug 03 05:52:30 PM PDT 24
Finished Aug 03 05:52:31 PM PDT 24
Peak memory 218720 kb
Host smart-a7740495-d8d2-4667-a354-9f2eba3d5de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039715735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3039715735
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.1735437321
Short name T362
Test name
Test status
Simulation time 158659676 ps
CPU time 1.22 seconds
Started Aug 03 05:52:31 PM PDT 24
Finished Aug 03 05:52:32 PM PDT 24
Peak memory 217332 kb
Host smart-6bf3617b-77a1-4fd3-8b1b-623e319f0e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735437321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1735437321
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1423929244
Short name T763
Test name
Test status
Simulation time 53581714 ps
CPU time 1.28 seconds
Started Aug 03 05:48:47 PM PDT 24
Finished Aug 03 05:48:48 PM PDT 24
Peak memory 220212 kb
Host smart-9309cd63-e6da-4a42-b134-92f177659586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423929244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1423929244
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2414571602
Short name T435
Test name
Test status
Simulation time 23387425 ps
CPU time 0.86 seconds
Started Aug 03 05:48:45 PM PDT 24
Finished Aug 03 05:48:46 PM PDT 24
Peak memory 206684 kb
Host smart-9c2cb9f0-9b0e-407b-b898-81b9106d6dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414571602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2414571602
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2269181611
Short name T607
Test name
Test status
Simulation time 11281529 ps
CPU time 0.88 seconds
Started Aug 03 05:48:44 PM PDT 24
Finished Aug 03 05:48:45 PM PDT 24
Peak memory 215360 kb
Host smart-34d8ccc3-ffd7-44e2-b74c-49f78c1eb82f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269181611 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2269181611
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.549019711
Short name T172
Test name
Test status
Simulation time 261222942 ps
CPU time 1.15 seconds
Started Aug 03 05:48:46 PM PDT 24
Finished Aug 03 05:48:48 PM PDT 24
Peak memory 218748 kb
Host smart-a66a44c8-fe95-4920-b914-0e83befac354
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549019711 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.549019711
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2254822641
Short name T48
Test name
Test status
Simulation time 29982328 ps
CPU time 0.97 seconds
Started Aug 03 05:48:45 PM PDT 24
Finished Aug 03 05:48:46 PM PDT 24
Peak memory 223812 kb
Host smart-33e85b5c-b589-44b5-96b7-f376c872d463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254822641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2254822641
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3776036945
Short name T27
Test name
Test status
Simulation time 58829656 ps
CPU time 1.64 seconds
Started Aug 03 05:48:46 PM PDT 24
Finished Aug 03 05:48:48 PM PDT 24
Peak memory 218320 kb
Host smart-78007c75-81d8-4730-b5f8-830c53bc4623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776036945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3776036945
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3040831767
Short name T817
Test name
Test status
Simulation time 38411336 ps
CPU time 0.9 seconds
Started Aug 03 05:48:48 PM PDT 24
Finished Aug 03 05:48:48 PM PDT 24
Peak memory 215364 kb
Host smart-3fd5154a-9347-40c7-b2c1-6622b9e35660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040831767 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3040831767
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2325781594
Short name T534
Test name
Test status
Simulation time 23021381 ps
CPU time 0.92 seconds
Started Aug 03 05:48:41 PM PDT 24
Finished Aug 03 05:48:42 PM PDT 24
Peak memory 215292 kb
Host smart-80034da4-04e7-4f36-ab26-576bc8de449c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325781594 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2325781594
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.168095061
Short name T450
Test name
Test status
Simulation time 930274474 ps
CPU time 5.64 seconds
Started Aug 03 05:48:47 PM PDT 24
Finished Aug 03 05:48:53 PM PDT 24
Peak memory 219716 kb
Host smart-35011486-0cca-40de-b935-0e00739cb905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168095061 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.168095061
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.421217121
Short name T133
Test name
Test status
Simulation time 127023102924 ps
CPU time 897.42 seconds
Started Aug 03 05:48:44 PM PDT 24
Finished Aug 03 06:03:42 PM PDT 24
Peak memory 221700 kb
Host smart-d286639f-d62d-4b78-9a09-7af8be1ec0a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421217121 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.421217121
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.1446138814
Short name T792
Test name
Test status
Simulation time 45479463 ps
CPU time 1.28 seconds
Started Aug 03 05:52:33 PM PDT 24
Finished Aug 03 05:52:34 PM PDT 24
Peak memory 219740 kb
Host smart-b5d7cd8c-6f94-4c88-a07c-0279dc1535aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446138814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1446138814
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3934818423
Short name T230
Test name
Test status
Simulation time 104860729 ps
CPU time 1.2 seconds
Started Aug 03 05:52:31 PM PDT 24
Finished Aug 03 05:52:32 PM PDT 24
Peak memory 217288 kb
Host smart-1de9db31-260c-4405-b08f-e650efff0348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934818423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3934818423
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.2377142216
Short name T275
Test name
Test status
Simulation time 25816634 ps
CPU time 1.3 seconds
Started Aug 03 05:52:30 PM PDT 24
Finished Aug 03 05:52:32 PM PDT 24
Peak memory 218740 kb
Host smart-f2b24708-7c76-439a-8e43-856b6ab319b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377142216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.2377142216
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.3091367021
Short name T379
Test name
Test status
Simulation time 84428494 ps
CPU time 1.61 seconds
Started Aug 03 05:52:32 PM PDT 24
Finished Aug 03 05:52:33 PM PDT 24
Peak memory 219212 kb
Host smart-fd5f3cc7-d620-4740-855e-0eafc452eb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091367021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3091367021
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.2380991678
Short name T54
Test name
Test status
Simulation time 63513898 ps
CPU time 1.14 seconds
Started Aug 03 05:52:31 PM PDT 24
Finished Aug 03 05:52:32 PM PDT 24
Peak memory 218640 kb
Host smart-957fa9ee-3895-40ae-8cf3-e91544f6054a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380991678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2380991678
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.3941645254
Short name T700
Test name
Test status
Simulation time 37349488 ps
CPU time 1.14 seconds
Started Aug 03 05:52:36 PM PDT 24
Finished Aug 03 05:52:37 PM PDT 24
Peak memory 218480 kb
Host smart-c5318f58-c729-48a7-9024-0a9b4c89263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941645254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3941645254
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.2017652399
Short name T873
Test name
Test status
Simulation time 22777549 ps
CPU time 1.14 seconds
Started Aug 03 05:52:32 PM PDT 24
Finished Aug 03 05:52:33 PM PDT 24
Peak memory 219472 kb
Host smart-a8230d00-f73b-4156-8e6a-20dc4c979363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017652399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2017652399
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.1695790440
Short name T353
Test name
Test status
Simulation time 37541768 ps
CPU time 1.26 seconds
Started Aug 03 05:52:32 PM PDT 24
Finished Aug 03 05:52:34 PM PDT 24
Peak memory 217376 kb
Host smart-bfe903f0-174e-48b5-b25f-dd6e159153cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695790440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1695790440
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2944505342
Short name T662
Test name
Test status
Simulation time 68559408 ps
CPU time 1.09 seconds
Started Aug 03 05:52:30 PM PDT 24
Finished Aug 03 05:52:32 PM PDT 24
Peak memory 219588 kb
Host smart-bbc028e9-7f47-4553-a7db-8cd0236cf071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944505342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2944505342
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.3110222297
Short name T80
Test name
Test status
Simulation time 73758901 ps
CPU time 1.03 seconds
Started Aug 03 05:52:32 PM PDT 24
Finished Aug 03 05:52:34 PM PDT 24
Peak memory 217308 kb
Host smart-2503945c-1d5a-4ed0-967d-8c9ca22cb789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110222297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3110222297
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2900446884
Short name T140
Test name
Test status
Simulation time 69153070 ps
CPU time 1.02 seconds
Started Aug 03 05:52:30 PM PDT 24
Finished Aug 03 05:52:31 PM PDT 24
Peak memory 218500 kb
Host smart-17aa4e23-dea1-46ec-afd0-cb4cb51ac158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900446884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2900446884
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.297445809
Short name T856
Test name
Test status
Simulation time 44760302 ps
CPU time 1.21 seconds
Started Aug 03 05:52:32 PM PDT 24
Finished Aug 03 05:52:33 PM PDT 24
Peak memory 217320 kb
Host smart-3ee38d1a-af72-454c-b9f0-159319efe2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297445809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.297445809
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.958787416
Short name T177
Test name
Test status
Simulation time 58615373 ps
CPU time 1.25 seconds
Started Aug 03 05:52:32 PM PDT 24
Finished Aug 03 05:52:34 PM PDT 24
Peak memory 220696 kb
Host smart-fa57770f-0cd0-497a-80ec-8f49057c2f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958787416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.958787416
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.2097318018
Short name T620
Test name
Test status
Simulation time 46394448 ps
CPU time 1.63 seconds
Started Aug 03 05:52:32 PM PDT 24
Finished Aug 03 05:52:34 PM PDT 24
Peak memory 220244 kb
Host smart-1eb13167-69eb-4504-abab-ee5969235a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097318018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2097318018
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3230318823
Short name T403
Test name
Test status
Simulation time 140763592 ps
CPU time 1.61 seconds
Started Aug 03 05:52:31 PM PDT 24
Finished Aug 03 05:52:32 PM PDT 24
Peak memory 218564 kb
Host smart-3cebbeb6-0e85-4b95-9196-23a0b7ec3868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230318823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3230318823
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.1954992922
Short name T556
Test name
Test status
Simulation time 80203064 ps
CPU time 1.16 seconds
Started Aug 03 05:52:36 PM PDT 24
Finished Aug 03 05:52:37 PM PDT 24
Peak memory 218748 kb
Host smart-9224eef4-4905-43df-bbe7-b2d2830eb191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954992922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.1954992922
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3004104576
Short name T519
Test name
Test status
Simulation time 46475949 ps
CPU time 1.34 seconds
Started Aug 03 05:52:41 PM PDT 24
Finished Aug 03 05:52:42 PM PDT 24
Peak memory 220208 kb
Host smart-aebea5c1-f6d2-40f9-9549-b41d32a6d123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004104576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3004104576
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.495673647
Short name T302
Test name
Test status
Simulation time 37419243 ps
CPU time 1.17 seconds
Started Aug 03 05:52:39 PM PDT 24
Finished Aug 03 05:52:41 PM PDT 24
Peak memory 218752 kb
Host smart-759d2cfe-73a4-4b6a-b39e-4d4ed4fa715e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495673647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.495673647
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.1757037046
Short name T347
Test name
Test status
Simulation time 45628764 ps
CPU time 1.35 seconds
Started Aug 03 05:52:40 PM PDT 24
Finished Aug 03 05:52:42 PM PDT 24
Peak memory 217324 kb
Host smart-963fb964-c4f0-47d6-9202-1898593f8375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757037046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1757037046
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1173695569
Short name T411
Test name
Test status
Simulation time 98523616 ps
CPU time 1.12 seconds
Started Aug 03 05:46:53 PM PDT 24
Finished Aug 03 05:46:55 PM PDT 24
Peak memory 220332 kb
Host smart-80c2fbc6-cd05-4a04-a4ff-e65d5d45852c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173695569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1173695569
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2856960208
Short name T912
Test name
Test status
Simulation time 37956283 ps
CPU time 1.04 seconds
Started Aug 03 05:47:00 PM PDT 24
Finished Aug 03 05:47:01 PM PDT 24
Peak memory 206780 kb
Host smart-057ad054-06f0-427b-a4c4-8d0e04d69afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856960208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2856960208
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2775286439
Short name T364
Test name
Test status
Simulation time 15941444 ps
CPU time 0.8 seconds
Started Aug 03 05:46:53 PM PDT 24
Finished Aug 03 05:46:54 PM PDT 24
Peak memory 215392 kb
Host smart-40b46e77-9f2c-4d8d-804a-f3469e7a3430
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775286439 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2775286439
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.4092487750
Short name T565
Test name
Test status
Simulation time 27423943 ps
CPU time 0.97 seconds
Started Aug 03 05:46:59 PM PDT 24
Finished Aug 03 05:47:00 PM PDT 24
Peak memory 218520 kb
Host smart-411dc4aa-2358-43c9-a312-6dd726d3136d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092487750 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.4092487750
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3176249821
Short name T860
Test name
Test status
Simulation time 30539543 ps
CPU time 1.09 seconds
Started Aug 03 05:46:53 PM PDT 24
Finished Aug 03 05:46:54 PM PDT 24
Peak memory 224084 kb
Host smart-048d2f1b-f448-44f7-a3d0-655db3475e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176249821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3176249821
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3504347524
Short name T305
Test name
Test status
Simulation time 115400205 ps
CPU time 1.53 seconds
Started Aug 03 05:46:48 PM PDT 24
Finished Aug 03 05:46:50 PM PDT 24
Peak memory 218760 kb
Host smart-03016163-26c1-43c5-aa42-09521f0fab8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504347524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3504347524
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2564104722
Short name T401
Test name
Test status
Simulation time 25299758 ps
CPU time 0.93 seconds
Started Aug 03 05:46:54 PM PDT 24
Finished Aug 03 05:46:55 PM PDT 24
Peak memory 215852 kb
Host smart-5699b414-94cf-44f5-9834-44d94dccc0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564104722 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2564104722
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.451048968
Short name T964
Test name
Test status
Simulation time 17444536 ps
CPU time 0.97 seconds
Started Aug 03 05:46:49 PM PDT 24
Finished Aug 03 05:46:50 PM PDT 24
Peak memory 207060 kb
Host smart-bc54516f-a283-4b86-941c-6242ecd8165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451048968 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.451048968
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.1219510074
Short name T564
Test name
Test status
Simulation time 70784193 ps
CPU time 0.93 seconds
Started Aug 03 05:46:50 PM PDT 24
Finished Aug 03 05:46:51 PM PDT 24
Peak memory 215260 kb
Host smart-92c3bd4d-4dfc-40be-b904-a1dfe924ed05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219510074 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1219510074
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2185879698
Short name T566
Test name
Test status
Simulation time 184704985 ps
CPU time 1.6 seconds
Started Aug 03 05:46:54 PM PDT 24
Finished Aug 03 05:46:56 PM PDT 24
Peak memory 217308 kb
Host smart-df19feb6-f485-4567-b53d-be31561213f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185879698 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2185879698
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2610906228
Short name T602
Test name
Test status
Simulation time 86109927642 ps
CPU time 969.76 seconds
Started Aug 03 05:46:53 PM PDT 24
Finished Aug 03 06:03:03 PM PDT 24
Peak memory 221544 kb
Host smart-df753e04-8f7f-4df2-87f6-7315b27ab6fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610906228 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2610906228
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3171691531
Short name T674
Test name
Test status
Simulation time 234350567 ps
CPU time 1.43 seconds
Started Aug 03 05:48:45 PM PDT 24
Finished Aug 03 05:48:46 PM PDT 24
Peak memory 219716 kb
Host smart-30d1458d-d3d2-4e28-a534-0f2bfef36d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171691531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3171691531
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2904558607
Short name T708
Test name
Test status
Simulation time 138284136 ps
CPU time 0.92 seconds
Started Aug 03 05:48:49 PM PDT 24
Finished Aug 03 05:48:50 PM PDT 24
Peak memory 206720 kb
Host smart-a84fb2ee-9fae-4917-aba4-e750278f7597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904558607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2904558607
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.4238573109
Short name T123
Test name
Test status
Simulation time 21605361 ps
CPU time 0.81 seconds
Started Aug 03 05:48:45 PM PDT 24
Finished Aug 03 05:48:46 PM PDT 24
Peak memory 216220 kb
Host smart-e66830c1-3fe1-488e-828c-9702f11dcd9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238573109 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.4238573109
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2299352491
Short name T278
Test name
Test status
Simulation time 42617430 ps
CPU time 1 seconds
Started Aug 03 05:48:45 PM PDT 24
Finished Aug 03 05:48:46 PM PDT 24
Peak memory 218456 kb
Host smart-24a38b12-a54c-4aa1-86b0-27088446c836
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299352491 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2299352491
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.799894891
Short name T631
Test name
Test status
Simulation time 22904180 ps
CPU time 1.02 seconds
Started Aug 03 05:48:46 PM PDT 24
Finished Aug 03 05:48:47 PM PDT 24
Peak memory 219600 kb
Host smart-1a281d4e-b250-4d61-80c1-6eb8cf2222c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799894891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.799894891
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2485882409
Short name T731
Test name
Test status
Simulation time 104234968 ps
CPU time 1.02 seconds
Started Aug 03 05:48:46 PM PDT 24
Finished Aug 03 05:48:47 PM PDT 24
Peak memory 217308 kb
Host smart-151dce50-0160-42db-8fae-d303221bfc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485882409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2485882409
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3553706121
Short name T102
Test name
Test status
Simulation time 32304570 ps
CPU time 0.86 seconds
Started Aug 03 05:48:48 PM PDT 24
Finished Aug 03 05:48:49 PM PDT 24
Peak memory 215176 kb
Host smart-a92ae6aa-69d5-4fed-b658-ea448097e2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553706121 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3553706121
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.4147311053
Short name T712
Test name
Test status
Simulation time 20485647 ps
CPU time 0.91 seconds
Started Aug 03 05:48:46 PM PDT 24
Finished Aug 03 05:48:47 PM PDT 24
Peak memory 215304 kb
Host smart-faef76fc-de87-4a0b-9e6c-25fcb90ce251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147311053 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.4147311053
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3536112908
Short name T561
Test name
Test status
Simulation time 121617803 ps
CPU time 2.79 seconds
Started Aug 03 05:48:46 PM PDT 24
Finished Aug 03 05:48:49 PM PDT 24
Peak memory 217464 kb
Host smart-3fd787da-59cb-4a4c-b8ce-b21b9057005c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536112908 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3536112908
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1161814801
Short name T589
Test name
Test status
Simulation time 28873150680 ps
CPU time 589.59 seconds
Started Aug 03 05:48:44 PM PDT 24
Finished Aug 03 05:58:34 PM PDT 24
Peak memory 223696 kb
Host smart-b39c619f-791f-49b9-9504-41a6fa3607dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161814801 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1161814801
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.984344171
Short name T642
Test name
Test status
Simulation time 62541954 ps
CPU time 1.55 seconds
Started Aug 03 05:52:41 PM PDT 24
Finished Aug 03 05:52:42 PM PDT 24
Peak memory 218508 kb
Host smart-ef086d11-2d12-480e-9f96-a3517e515d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984344171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.984344171
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3364062191
Short name T803
Test name
Test status
Simulation time 37546439 ps
CPU time 1.54 seconds
Started Aug 03 05:52:36 PM PDT 24
Finished Aug 03 05:52:37 PM PDT 24
Peak memory 217424 kb
Host smart-e3fd3f6f-1d59-49a7-ba31-78b5826065bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364062191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3364062191
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3567056850
Short name T591
Test name
Test status
Simulation time 77772894 ps
CPU time 1.01 seconds
Started Aug 03 05:52:38 PM PDT 24
Finished Aug 03 05:52:39 PM PDT 24
Peak memory 219928 kb
Host smart-a54c9adc-3a51-4b33-9f12-6ff0e54e35fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567056850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3567056850
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2813110394
Short name T643
Test name
Test status
Simulation time 38395750 ps
CPU time 1.39 seconds
Started Aug 03 05:52:37 PM PDT 24
Finished Aug 03 05:52:38 PM PDT 24
Peak memory 218516 kb
Host smart-3e2ccd26-1c3d-4dd9-aa3d-b5b3e7bc2b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813110394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2813110394
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.2478781850
Short name T322
Test name
Test status
Simulation time 146096785 ps
CPU time 1.36 seconds
Started Aug 03 05:52:37 PM PDT 24
Finished Aug 03 05:52:38 PM PDT 24
Peak memory 217184 kb
Host smart-d0325497-18f5-427a-bffe-9dd22729f808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478781850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2478781850
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.4270219015
Short name T732
Test name
Test status
Simulation time 278874472 ps
CPU time 1.06 seconds
Started Aug 03 05:52:40 PM PDT 24
Finished Aug 03 05:52:41 PM PDT 24
Peak memory 217260 kb
Host smart-8cff8f95-d37f-44e3-bdce-85c531e2caae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270219015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.4270219015
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1666807443
Short name T862
Test name
Test status
Simulation time 46128162 ps
CPU time 1.58 seconds
Started Aug 03 05:52:40 PM PDT 24
Finished Aug 03 05:52:42 PM PDT 24
Peak memory 217344 kb
Host smart-dba2cd39-0c31-4045-97b3-e5065a15dccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666807443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1666807443
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3786749267
Short name T781
Test name
Test status
Simulation time 79147709 ps
CPU time 1.19 seconds
Started Aug 03 05:52:36 PM PDT 24
Finished Aug 03 05:52:37 PM PDT 24
Peak memory 217364 kb
Host smart-fd6a1108-d802-4148-8bf8-1ddd5afa25f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786749267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3786749267
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2874701135
Short name T701
Test name
Test status
Simulation time 118021927 ps
CPU time 1.94 seconds
Started Aug 03 05:52:38 PM PDT 24
Finished Aug 03 05:52:40 PM PDT 24
Peak memory 220344 kb
Host smart-1726474d-9bb6-4698-a1af-18d93618f061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874701135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2874701135
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2931204664
Short name T280
Test name
Test status
Simulation time 44591353 ps
CPU time 1.17 seconds
Started Aug 03 05:48:50 PM PDT 24
Finished Aug 03 05:48:52 PM PDT 24
Peak memory 219008 kb
Host smart-c57809c7-5d73-42ae-bbdd-32fa1b6354a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931204664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2931204664
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3783880078
Short name T453
Test name
Test status
Simulation time 44849108 ps
CPU time 0.89 seconds
Started Aug 03 05:48:54 PM PDT 24
Finished Aug 03 05:48:55 PM PDT 24
Peak memory 206796 kb
Host smart-90e2b95a-aa8f-4ba6-aabd-145205736bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783880078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3783880078
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.4119542703
Short name T425
Test name
Test status
Simulation time 11593869 ps
CPU time 0.89 seconds
Started Aug 03 05:48:51 PM PDT 24
Finished Aug 03 05:48:52 PM PDT 24
Peak memory 215884 kb
Host smart-422c903f-5321-4e24-8ecf-3e1e1d70196a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119542703 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4119542703
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.854411728
Short name T893
Test name
Test status
Simulation time 132613351 ps
CPU time 1.22 seconds
Started Aug 03 05:48:52 PM PDT 24
Finished Aug 03 05:48:53 PM PDT 24
Peak memory 217036 kb
Host smart-dda8efdc-2de3-4f11-88bb-602b9e1e91a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854411728 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.854411728
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1008655635
Short name T815
Test name
Test status
Simulation time 19032578 ps
CPU time 1.05 seconds
Started Aug 03 05:48:50 PM PDT 24
Finished Aug 03 05:48:51 PM PDT 24
Peak memory 218476 kb
Host smart-bd425987-d80f-4377-abf0-68ef8d489795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008655635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1008655635
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1230385278
Short name T859
Test name
Test status
Simulation time 58653359 ps
CPU time 1.44 seconds
Started Aug 03 05:48:51 PM PDT 24
Finished Aug 03 05:48:52 PM PDT 24
Peak memory 219824 kb
Host smart-5708d39f-f218-4116-8bf4-72aed9741913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230385278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1230385278
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2955546977
Short name T940
Test name
Test status
Simulation time 37801639 ps
CPU time 0.9 seconds
Started Aug 03 05:48:53 PM PDT 24
Finished Aug 03 05:48:54 PM PDT 24
Peak memory 215360 kb
Host smart-d673fc19-5a99-4d63-baed-88fe1ef47cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955546977 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2955546977
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.93216584
Short name T905
Test name
Test status
Simulation time 42244900 ps
CPU time 0.91 seconds
Started Aug 03 05:48:50 PM PDT 24
Finished Aug 03 05:48:51 PM PDT 24
Peak memory 215268 kb
Host smart-36b1d0e9-b5ac-4eb7-adc4-26936fd6b0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93216584 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.93216584
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.4042819652
Short name T494
Test name
Test status
Simulation time 389805682 ps
CPU time 4.17 seconds
Started Aug 03 05:48:51 PM PDT 24
Finished Aug 03 05:48:55 PM PDT 24
Peak memory 215248 kb
Host smart-2defdd90-fd18-4319-890e-f1df7202253f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042819652 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.4042819652
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1857057962
Short name T511
Test name
Test status
Simulation time 264375970113 ps
CPU time 1434.69 seconds
Started Aug 03 05:48:50 PM PDT 24
Finished Aug 03 06:12:45 PM PDT 24
Peak memory 223836 kb
Host smart-ebbc35fd-c404-4b9f-ba3a-cd7da620d114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857057962 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1857057962
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.4229546742
Short name T535
Test name
Test status
Simulation time 89567521 ps
CPU time 1.1 seconds
Started Aug 03 05:52:42 PM PDT 24
Finished Aug 03 05:52:43 PM PDT 24
Peak memory 218736 kb
Host smart-054e3f46-8f96-4257-b40f-a382386bab1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229546742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.4229546742
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3218959059
Short name T938
Test name
Test status
Simulation time 35050672 ps
CPU time 1.49 seconds
Started Aug 03 05:52:37 PM PDT 24
Finished Aug 03 05:52:38 PM PDT 24
Peak memory 215296 kb
Host smart-e3876fb5-3d9c-4807-95db-aace91040c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218959059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3218959059
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1081060626
Short name T975
Test name
Test status
Simulation time 25302328 ps
CPU time 1.23 seconds
Started Aug 03 05:52:38 PM PDT 24
Finished Aug 03 05:52:39 PM PDT 24
Peak memory 218740 kb
Host smart-5037abbb-2c80-40d9-b001-b5c2190c0036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081060626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1081060626
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2924549180
Short name T807
Test name
Test status
Simulation time 39614474 ps
CPU time 1.64 seconds
Started Aug 03 05:52:37 PM PDT 24
Finished Aug 03 05:52:38 PM PDT 24
Peak memory 217568 kb
Host smart-415f3ba0-6570-4a36-8d0b-183d774344a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924549180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2924549180
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1305462985
Short name T800
Test name
Test status
Simulation time 178367476 ps
CPU time 3.35 seconds
Started Aug 03 05:52:39 PM PDT 24
Finished Aug 03 05:52:43 PM PDT 24
Peak memory 220068 kb
Host smart-1ace14af-cf15-47e5-8689-b29657a7aece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305462985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1305462985
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2807113335
Short name T697
Test name
Test status
Simulation time 100283844 ps
CPU time 1.41 seconds
Started Aug 03 05:52:38 PM PDT 24
Finished Aug 03 05:52:39 PM PDT 24
Peak memory 220144 kb
Host smart-6f4bcaa9-0edc-4405-ab08-2d2fecb376ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807113335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2807113335
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.3908095106
Short name T870
Test name
Test status
Simulation time 73548680 ps
CPU time 0.97 seconds
Started Aug 03 05:52:37 PM PDT 24
Finished Aug 03 05:52:38 PM PDT 24
Peak memory 217436 kb
Host smart-56291cc7-648b-4031-b577-89dacd52e348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908095106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3908095106
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3646965459
Short name T240
Test name
Test status
Simulation time 58293652 ps
CPU time 1.32 seconds
Started Aug 03 05:52:38 PM PDT 24
Finished Aug 03 05:52:39 PM PDT 24
Peak memory 218584 kb
Host smart-7ccdecb5-3dd0-41ce-b80c-ea67fd9d9229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646965459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3646965459
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3261604835
Short name T921
Test name
Test status
Simulation time 21566278 ps
CPU time 1.22 seconds
Started Aug 03 05:52:39 PM PDT 24
Finished Aug 03 05:52:41 PM PDT 24
Peak memory 217424 kb
Host smart-48cc27dd-0370-4ab1-a51a-200d36dc64c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261604835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3261604835
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1776928627
Short name T918
Test name
Test status
Simulation time 86716858 ps
CPU time 1.25 seconds
Started Aug 03 05:48:58 PM PDT 24
Finished Aug 03 05:48:59 PM PDT 24
Peak memory 219652 kb
Host smart-8f647140-7468-4732-8c6a-ab5a1cf18019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776928627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1776928627
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1715446643
Short name T497
Test name
Test status
Simulation time 45325579 ps
CPU time 0.87 seconds
Started Aug 03 05:48:58 PM PDT 24
Finished Aug 03 05:48:59 PM PDT 24
Peak memory 214868 kb
Host smart-74a56d68-448b-4c24-aac4-1ebb96d4fefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715446643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1715446643
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2943658298
Short name T537
Test name
Test status
Simulation time 40470155 ps
CPU time 1.3 seconds
Started Aug 03 05:48:57 PM PDT 24
Finished Aug 03 05:48:58 PM PDT 24
Peak memory 217052 kb
Host smart-c429c976-c72d-40f1-929d-e1500c26ab7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943658298 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2943658298
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_genbits.1988859112
Short name T424
Test name
Test status
Simulation time 62662233 ps
CPU time 1.61 seconds
Started Aug 03 05:48:51 PM PDT 24
Finished Aug 03 05:48:52 PM PDT 24
Peak memory 218308 kb
Host smart-71fa8c12-ff55-4ad9-8751-a0d1ace863a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988859112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1988859112
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_smoke.3315187206
Short name T608
Test name
Test status
Simulation time 15509246 ps
CPU time 1 seconds
Started Aug 03 05:48:50 PM PDT 24
Finished Aug 03 05:48:52 PM PDT 24
Peak memory 215256 kb
Host smart-a8660d17-c92c-4774-82f6-0b9794364991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315187206 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3315187206
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.4179157132
Short name T458
Test name
Test status
Simulation time 89158078 ps
CPU time 1.5 seconds
Started Aug 03 05:48:57 PM PDT 24
Finished Aug 03 05:48:59 PM PDT 24
Peak memory 215220 kb
Host smart-0959c1b2-dd46-4a19-9d0c-ae8de9d4dcbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179157132 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4179157132
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.618998971
Short name T650
Test name
Test status
Simulation time 242264920105 ps
CPU time 1342.8 seconds
Started Aug 03 05:48:56 PM PDT 24
Finished Aug 03 06:11:19 PM PDT 24
Peak memory 224100 kb
Host smart-c7261620-b074-418e-ba7b-9680753fbab1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618998971 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.618998971
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2326942421
Short name T39
Test name
Test status
Simulation time 38146331 ps
CPU time 1.69 seconds
Started Aug 03 05:52:41 PM PDT 24
Finished Aug 03 05:52:43 PM PDT 24
Peak memory 218484 kb
Host smart-3e5f5b53-c78b-491f-b2ea-b631acd2321f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326942421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2326942421
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.634927945
Short name T552
Test name
Test status
Simulation time 71546487 ps
CPU time 1.38 seconds
Started Aug 03 05:52:36 PM PDT 24
Finished Aug 03 05:52:38 PM PDT 24
Peak memory 218428 kb
Host smart-f41d7231-ec27-4c75-b531-77d7893066ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634927945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.634927945
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3305599386
Short name T970
Test name
Test status
Simulation time 67801433 ps
CPU time 1.21 seconds
Started Aug 03 05:52:41 PM PDT 24
Finished Aug 03 05:52:43 PM PDT 24
Peak memory 219780 kb
Host smart-4f26bfff-dae2-465b-87b5-4e5472069605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305599386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3305599386
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.221716778
Short name T598
Test name
Test status
Simulation time 180286486 ps
CPU time 1.76 seconds
Started Aug 03 05:52:37 PM PDT 24
Finished Aug 03 05:52:39 PM PDT 24
Peak memory 218744 kb
Host smart-d7cdff65-8f6c-4f9d-8ce4-07a5cf9684eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221716778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.221716778
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.851661997
Short name T82
Test name
Test status
Simulation time 33896644 ps
CPU time 1.44 seconds
Started Aug 03 05:52:42 PM PDT 24
Finished Aug 03 05:52:44 PM PDT 24
Peak memory 217340 kb
Host smart-f083d715-f434-493a-bef1-66f498a6f493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851661997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.851661997
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3661674563
Short name T67
Test name
Test status
Simulation time 48102090 ps
CPU time 1.2 seconds
Started Aug 03 05:52:41 PM PDT 24
Finished Aug 03 05:52:42 PM PDT 24
Peak memory 217360 kb
Host smart-b86d6a3d-e7c2-400a-be2c-159431d804c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661674563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3661674563
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.4168202064
Short name T962
Test name
Test status
Simulation time 74499676 ps
CPU time 1.61 seconds
Started Aug 03 05:52:43 PM PDT 24
Finished Aug 03 05:52:45 PM PDT 24
Peak memory 218680 kb
Host smart-42fd75b2-3924-4042-b71f-7735ab8009ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168202064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.4168202064
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1990065193
Short name T830
Test name
Test status
Simulation time 202544908 ps
CPU time 2.94 seconds
Started Aug 03 05:52:45 PM PDT 24
Finished Aug 03 05:52:48 PM PDT 24
Peak memory 217480 kb
Host smart-f08b28d8-ee91-4411-8cae-e009a4ca1243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990065193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1990065193
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.543621646
Short name T501
Test name
Test status
Simulation time 188567772 ps
CPU time 1.09 seconds
Started Aug 03 05:52:44 PM PDT 24
Finished Aug 03 05:52:46 PM PDT 24
Peak memory 215312 kb
Host smart-7b91e4e4-2914-4ad0-bd92-9dc4b7cc4e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543621646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.543621646
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1410290370
Short name T384
Test name
Test status
Simulation time 87862142 ps
CPU time 1.17 seconds
Started Aug 03 05:48:56 PM PDT 24
Finished Aug 03 05:48:57 PM PDT 24
Peak memory 219728 kb
Host smart-48547bfc-89b0-4765-a817-10f9b76fdb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410290370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1410290370
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1594242028
Short name T543
Test name
Test status
Simulation time 17605383 ps
CPU time 0.97 seconds
Started Aug 03 05:49:07 PM PDT 24
Finished Aug 03 05:49:08 PM PDT 24
Peak memory 206672 kb
Host smart-f97787f8-d1aa-4345-96f7-8d78aa66dd2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594242028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1594242028
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1973598452
Short name T520
Test name
Test status
Simulation time 58328559 ps
CPU time 1.14 seconds
Started Aug 03 05:49:03 PM PDT 24
Finished Aug 03 05:49:04 PM PDT 24
Peak memory 215604 kb
Host smart-de1e4789-f21f-42e0-a9d4-b8cf41e9a50c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973598452 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1973598452
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.227654832
Short name T727
Test name
Test status
Simulation time 23626488 ps
CPU time 1.17 seconds
Started Aug 03 05:48:55 PM PDT 24
Finished Aug 03 05:48:56 PM PDT 24
Peak memory 220568 kb
Host smart-94dc00d6-4883-4959-8bc2-bd4035a36baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227654832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.227654832
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1480729609
Short name T820
Test name
Test status
Simulation time 53377028 ps
CPU time 1.47 seconds
Started Aug 03 05:48:57 PM PDT 24
Finished Aug 03 05:48:59 PM PDT 24
Peak memory 218688 kb
Host smart-8f4491a8-8ff4-486e-aae3-cc3feb8642cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480729609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1480729609
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.741324184
Short name T907
Test name
Test status
Simulation time 21137205 ps
CPU time 1.17 seconds
Started Aug 03 05:48:57 PM PDT 24
Finished Aug 03 05:48:59 PM PDT 24
Peak memory 224076 kb
Host smart-61a5278d-c5b7-4330-becb-4f37604410d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741324184 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.741324184
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3953848040
Short name T654
Test name
Test status
Simulation time 46824179 ps
CPU time 0.89 seconds
Started Aug 03 05:48:56 PM PDT 24
Finished Aug 03 05:48:57 PM PDT 24
Peak memory 215280 kb
Host smart-7b4b9936-8b0c-4cd3-8ce3-1425c6903119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953848040 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3953848040
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3682150119
Short name T890
Test name
Test status
Simulation time 432198162 ps
CPU time 2.75 seconds
Started Aug 03 05:48:57 PM PDT 24
Finished Aug 03 05:49:00 PM PDT 24
Peak memory 215360 kb
Host smart-fd7977ad-65da-4ae2-8d45-050343ecafc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682150119 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3682150119
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2972388974
Short name T329
Test name
Test status
Simulation time 287270579942 ps
CPU time 1757.02 seconds
Started Aug 03 05:48:56 PM PDT 24
Finished Aug 03 06:18:13 PM PDT 24
Peak memory 224348 kb
Host smart-d1d528ab-8646-4b1f-adbb-bbb507f5a611
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972388974 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2972388974
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1915964426
Short name T473
Test name
Test status
Simulation time 68281431 ps
CPU time 1.68 seconds
Started Aug 03 05:52:43 PM PDT 24
Finished Aug 03 05:52:44 PM PDT 24
Peak memory 218516 kb
Host smart-039ef2a4-2b63-454a-b082-49a39b6a05ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915964426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1915964426
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1084271513
Short name T52
Test name
Test status
Simulation time 78258875 ps
CPU time 1.41 seconds
Started Aug 03 05:52:42 PM PDT 24
Finished Aug 03 05:52:43 PM PDT 24
Peak memory 218512 kb
Host smart-fa96249a-bd9c-42ce-a5df-83d2a360d253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084271513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1084271513
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2311913607
Short name T510
Test name
Test status
Simulation time 30359130 ps
CPU time 1.33 seconds
Started Aug 03 05:52:42 PM PDT 24
Finished Aug 03 05:52:43 PM PDT 24
Peak memory 218484 kb
Host smart-62926986-a12b-490e-a137-5440c5a81d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311913607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2311913607
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3314633305
Short name T544
Test name
Test status
Simulation time 79155405 ps
CPU time 1.1 seconds
Started Aug 03 05:52:43 PM PDT 24
Finished Aug 03 05:52:44 PM PDT 24
Peak memory 217532 kb
Host smart-359e692d-0951-4af7-93ea-d6cb0ad6a11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314633305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3314633305
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1739225384
Short name T81
Test name
Test status
Simulation time 52413119 ps
CPU time 1.2 seconds
Started Aug 03 05:52:42 PM PDT 24
Finished Aug 03 05:52:44 PM PDT 24
Peak memory 217112 kb
Host smart-e205a523-cfe0-4ada-857a-671786b98022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739225384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1739225384
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3874989676
Short name T394
Test name
Test status
Simulation time 28734039 ps
CPU time 1.22 seconds
Started Aug 03 05:52:43 PM PDT 24
Finished Aug 03 05:52:45 PM PDT 24
Peak memory 215288 kb
Host smart-9985ba6f-7290-42f4-80d0-23555be64231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874989676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3874989676
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3832280211
Short name T831
Test name
Test status
Simulation time 74143331 ps
CPU time 1.07 seconds
Started Aug 03 05:52:45 PM PDT 24
Finished Aug 03 05:52:46 PM PDT 24
Peak memory 217316 kb
Host smart-afcc65a1-0007-434e-93c7-ba5ea1037694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832280211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3832280211
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2062727694
Short name T775
Test name
Test status
Simulation time 82615712 ps
CPU time 1.38 seconds
Started Aug 03 05:52:43 PM PDT 24
Finished Aug 03 05:52:44 PM PDT 24
Peak memory 220376 kb
Host smart-43d8f36f-7296-4f38-9f38-eb8d606cc193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062727694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2062727694
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.648308433
Short name T922
Test name
Test status
Simulation time 56816916 ps
CPU time 1.57 seconds
Started Aug 03 05:52:42 PM PDT 24
Finished Aug 03 05:52:44 PM PDT 24
Peak memory 217224 kb
Host smart-e8469b64-0948-4fd3-9170-c603f45b400c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648308433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.648308433
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.956377955
Short name T693
Test name
Test status
Simulation time 36108861 ps
CPU time 1.12 seconds
Started Aug 03 05:49:16 PM PDT 24
Finished Aug 03 05:49:18 PM PDT 24
Peak memory 218528 kb
Host smart-8e4ddde8-071a-4a4e-bfd1-95bf74b4927f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956377955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.956377955
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1452612247
Short name T540
Test name
Test status
Simulation time 20017633 ps
CPU time 0.94 seconds
Started Aug 03 05:49:17 PM PDT 24
Finished Aug 03 05:49:19 PM PDT 24
Peak memory 206696 kb
Host smart-f615b681-ee2a-4098-9666-1523fd26f968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452612247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1452612247
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.4007912496
Short name T707
Test name
Test status
Simulation time 26931925 ps
CPU time 0.85 seconds
Started Aug 03 05:49:15 PM PDT 24
Finished Aug 03 05:49:16 PM PDT 24
Peak memory 215996 kb
Host smart-1e523505-7ba6-4a1e-8b94-ba4ab5a53975
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007912496 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.4007912496
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.4018225809
Short name T163
Test name
Test status
Simulation time 76815129 ps
CPU time 1.13 seconds
Started Aug 03 05:49:12 PM PDT 24
Finished Aug 03 05:49:13 PM PDT 24
Peak memory 216796 kb
Host smart-5ab2e397-16f7-4546-aacd-4ac7693e2ab3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018225809 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.4018225809
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3754341639
Short name T8
Test name
Test status
Simulation time 26757804 ps
CPU time 1.07 seconds
Started Aug 03 05:49:13 PM PDT 24
Finished Aug 03 05:49:14 PM PDT 24
Peak memory 229564 kb
Host smart-694b923b-92ca-42ca-8826-9f8aff9c6403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754341639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3754341639
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1640257704
Short name T952
Test name
Test status
Simulation time 110192896 ps
CPU time 1.2 seconds
Started Aug 03 05:49:05 PM PDT 24
Finished Aug 03 05:49:06 PM PDT 24
Peak memory 217248 kb
Host smart-eb174329-657e-46fc-bb16-9177adf37461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640257704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1640257704
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2719317177
Short name T689
Test name
Test status
Simulation time 31082623 ps
CPU time 0.98 seconds
Started Aug 03 05:49:14 PM PDT 24
Finished Aug 03 05:49:15 PM PDT 24
Peak memory 215520 kb
Host smart-03c3cea4-5b39-4ed2-86f3-acdc49706541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719317177 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2719317177
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2102818309
Short name T648
Test name
Test status
Simulation time 31974940 ps
CPU time 0.98 seconds
Started Aug 03 05:49:06 PM PDT 24
Finished Aug 03 05:49:07 PM PDT 24
Peak memory 215312 kb
Host smart-9941f037-0ef9-4969-96a3-175c829c9fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102818309 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2102818309
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.314476824
Short name T606
Test name
Test status
Simulation time 284035679 ps
CPU time 3.26 seconds
Started Aug 03 05:49:07 PM PDT 24
Finished Aug 03 05:49:10 PM PDT 24
Peak memory 218352 kb
Host smart-456440ca-6b74-4528-812e-8112f78f3415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314476824 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.314476824
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.4079847664
Short name T226
Test name
Test status
Simulation time 162626904616 ps
CPU time 1675.6 seconds
Started Aug 03 05:49:05 PM PDT 24
Finished Aug 03 06:17:01 PM PDT 24
Peak memory 224140 kb
Host smart-d7dc6316-d015-43e3-8554-b41adbcc594f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079847664 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.4079847664
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.840396286
Short name T402
Test name
Test status
Simulation time 100403127 ps
CPU time 1.46 seconds
Started Aug 03 05:52:42 PM PDT 24
Finished Aug 03 05:52:44 PM PDT 24
Peak memory 220000 kb
Host smart-46f5d60f-41a8-4965-82ee-2bf2fce3c076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840396286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.840396286
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3139413956
Short name T599
Test name
Test status
Simulation time 90369848 ps
CPU time 1.17 seconds
Started Aug 03 05:52:41 PM PDT 24
Finished Aug 03 05:52:42 PM PDT 24
Peak memory 218520 kb
Host smart-c11f84d0-1702-4584-91e2-cdafe4e50dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139413956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3139413956
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2276840773
Short name T621
Test name
Test status
Simulation time 59124055 ps
CPU time 2.04 seconds
Started Aug 03 05:52:43 PM PDT 24
Finished Aug 03 05:52:45 PM PDT 24
Peak memory 218664 kb
Host smart-22c67cc8-e2ff-47b8-aed3-3edc9fd968bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276840773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2276840773
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1482311126
Short name T837
Test name
Test status
Simulation time 38165158 ps
CPU time 1.35 seconds
Started Aug 03 05:52:43 PM PDT 24
Finished Aug 03 05:52:45 PM PDT 24
Peak memory 218444 kb
Host smart-ce5e708e-ea3c-4386-9058-cdbf51c2f805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482311126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1482311126
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.465485910
Short name T757
Test name
Test status
Simulation time 58504663 ps
CPU time 1.07 seconds
Started Aug 03 05:52:42 PM PDT 24
Finished Aug 03 05:52:43 PM PDT 24
Peak memory 217272 kb
Host smart-e2373928-8f7c-436a-b246-5807235da090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465485910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.465485910
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.373804210
Short name T483
Test name
Test status
Simulation time 38469818 ps
CPU time 1.44 seconds
Started Aug 03 05:52:41 PM PDT 24
Finished Aug 03 05:52:42 PM PDT 24
Peak memory 218676 kb
Host smart-db526f3d-b572-49f7-b594-9881ddecd98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373804210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.373804210
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.4100773358
Short name T741
Test name
Test status
Simulation time 213379018 ps
CPU time 1.81 seconds
Started Aug 03 05:52:55 PM PDT 24
Finished Aug 03 05:52:57 PM PDT 24
Peak memory 218848 kb
Host smart-5c5f7468-cbb3-47d1-9c8f-180d8c8e6a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100773358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.4100773358
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.637893899
Short name T554
Test name
Test status
Simulation time 72275602 ps
CPU time 1.11 seconds
Started Aug 03 05:52:47 PM PDT 24
Finished Aug 03 05:52:48 PM PDT 24
Peak memory 217408 kb
Host smart-cc833e42-f51e-49c4-88eb-3f4e56a70577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637893899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.637893899
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.957975436
Short name T326
Test name
Test status
Simulation time 134787850 ps
CPU time 2.44 seconds
Started Aug 03 05:52:55 PM PDT 24
Finished Aug 03 05:52:58 PM PDT 24
Peak memory 220040 kb
Host smart-3c318004-dbc9-4283-a959-51f3e0b67542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957975436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.957975436
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2892992587
Short name T784
Test name
Test status
Simulation time 83235924 ps
CPU time 1.5 seconds
Started Aug 03 05:52:48 PM PDT 24
Finished Aug 03 05:52:50 PM PDT 24
Peak memory 218552 kb
Host smart-9d129ba5-fcbd-4303-adec-922e9f7beb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892992587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2892992587
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3219676224
Short name T628
Test name
Test status
Simulation time 83710277 ps
CPU time 1.13 seconds
Started Aug 03 05:49:17 PM PDT 24
Finished Aug 03 05:49:18 PM PDT 24
Peak memory 219548 kb
Host smart-f475611d-96b8-446d-a8b0-3b95b97b1a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219676224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3219676224
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3133686931
Short name T553
Test name
Test status
Simulation time 17453006 ps
CPU time 0.96 seconds
Started Aug 03 05:49:17 PM PDT 24
Finished Aug 03 05:49:18 PM PDT 24
Peak memory 206740 kb
Host smart-088311b9-d08c-44e8-8836-b2287ff330ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133686931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3133686931
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1170489497
Short name T827
Test name
Test status
Simulation time 38702470 ps
CPU time 0.87 seconds
Started Aug 03 05:49:15 PM PDT 24
Finished Aug 03 05:49:16 PM PDT 24
Peak memory 215996 kb
Host smart-65bad6c9-9a62-4e3b-82d9-4e5349ff0a6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170489497 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1170489497
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3442962132
Short name T764
Test name
Test status
Simulation time 34418255 ps
CPU time 1.18 seconds
Started Aug 03 05:49:13 PM PDT 24
Finished Aug 03 05:49:14 PM PDT 24
Peak memory 218716 kb
Host smart-548c91a1-8985-45f5-a5cf-cfdf5b8e8ab7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442962132 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3442962132
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2897574307
Short name T196
Test name
Test status
Simulation time 20273355 ps
CPU time 1.21 seconds
Started Aug 03 05:49:14 PM PDT 24
Finished Aug 03 05:49:15 PM PDT 24
Peak memory 224012 kb
Host smart-50099f1a-4c4f-4fc9-a38d-59b372effc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897574307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2897574307
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1417621349
Short name T415
Test name
Test status
Simulation time 87821836 ps
CPU time 1.52 seconds
Started Aug 03 05:49:13 PM PDT 24
Finished Aug 03 05:49:15 PM PDT 24
Peak memory 219084 kb
Host smart-560e62e7-50ab-46c2-8f9c-1e616b24b56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417621349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1417621349
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3750785661
Short name T88
Test name
Test status
Simulation time 33996947 ps
CPU time 0.83 seconds
Started Aug 03 05:49:17 PM PDT 24
Finished Aug 03 05:49:18 PM PDT 24
Peak memory 215576 kb
Host smart-8b0c3139-6598-4877-8a7f-bbc3f5fe4cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750785661 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3750785661
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2959711744
Short name T490
Test name
Test status
Simulation time 36753094 ps
CPU time 0.88 seconds
Started Aug 03 05:49:13 PM PDT 24
Finished Aug 03 05:49:14 PM PDT 24
Peak memory 215280 kb
Host smart-c33b9901-6754-446b-adb3-043062da50ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959711744 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2959711744
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1881280336
Short name T749
Test name
Test status
Simulation time 104885390 ps
CPU time 1.64 seconds
Started Aug 03 05:49:16 PM PDT 24
Finished Aug 03 05:49:17 PM PDT 24
Peak memory 217028 kb
Host smart-29bf7323-b650-4faa-b291-35e34386d0e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881280336 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1881280336
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.221871027
Short name T916
Test name
Test status
Simulation time 29081404927 ps
CPU time 335.39 seconds
Started Aug 03 05:49:15 PM PDT 24
Finished Aug 03 05:54:50 PM PDT 24
Peak memory 219056 kb
Host smart-9666b17d-dca8-452c-9d47-bdb7f7263d46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221871027 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.221871027
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3731615003
Short name T976
Test name
Test status
Simulation time 88477976 ps
CPU time 1.21 seconds
Started Aug 03 05:52:55 PM PDT 24
Finished Aug 03 05:52:57 PM PDT 24
Peak memory 217412 kb
Host smart-57af1152-2a45-49ac-a7fc-59fa4735ae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731615003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3731615003
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1885513665
Short name T369
Test name
Test status
Simulation time 93749069 ps
CPU time 1.22 seconds
Started Aug 03 05:52:54 PM PDT 24
Finished Aug 03 05:52:56 PM PDT 24
Peak memory 217444 kb
Host smart-eff87166-6336-42c9-a67a-45e3ed1c2b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885513665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1885513665
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1423389306
Short name T906
Test name
Test status
Simulation time 111727537 ps
CPU time 2.44 seconds
Started Aug 03 05:52:50 PM PDT 24
Finished Aug 03 05:52:53 PM PDT 24
Peak memory 220128 kb
Host smart-20f90f5f-efba-46b7-8654-1468d638dbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423389306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1423389306
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3539311125
Short name T966
Test name
Test status
Simulation time 85450314 ps
CPU time 1.16 seconds
Started Aug 03 05:52:49 PM PDT 24
Finished Aug 03 05:52:50 PM PDT 24
Peak memory 217532 kb
Host smart-0c08dee3-fd22-4cca-b6d8-ce16991f6049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539311125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3539311125
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2070280040
Short name T546
Test name
Test status
Simulation time 62453430 ps
CPU time 1.63 seconds
Started Aug 03 05:52:49 PM PDT 24
Finished Aug 03 05:52:50 PM PDT 24
Peak memory 218700 kb
Host smart-3e6bb7b0-8b9f-4e45-9093-2d05a41eea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070280040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2070280040
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3847178513
Short name T555
Test name
Test status
Simulation time 96114952 ps
CPU time 1.13 seconds
Started Aug 03 05:52:48 PM PDT 24
Finished Aug 03 05:52:49 PM PDT 24
Peak memory 217376 kb
Host smart-14c4fd4e-cb2c-4280-b4a0-410d3483dd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847178513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3847178513
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2698878037
Short name T71
Test name
Test status
Simulation time 46421836 ps
CPU time 1.25 seconds
Started Aug 03 05:52:54 PM PDT 24
Finished Aug 03 05:52:56 PM PDT 24
Peak memory 217516 kb
Host smart-16feba7b-ed8e-4d59-b848-d0895fa6b970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698878037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2698878037
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1717227254
Short name T482
Test name
Test status
Simulation time 358331602 ps
CPU time 3.75 seconds
Started Aug 03 05:52:49 PM PDT 24
Finished Aug 03 05:52:53 PM PDT 24
Peak memory 219528 kb
Host smart-6d6742f9-30f4-4328-91fb-a014ea4c9bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717227254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1717227254
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.4029344445
Short name T641
Test name
Test status
Simulation time 52460685 ps
CPU time 1.44 seconds
Started Aug 03 05:52:47 PM PDT 24
Finished Aug 03 05:52:49 PM PDT 24
Peak memory 219912 kb
Host smart-c257b25b-6481-4860-a09e-5d17c51125c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029344445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.4029344445
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2719625836
Short name T141
Test name
Test status
Simulation time 40579317 ps
CPU time 1.14 seconds
Started Aug 03 05:49:17 PM PDT 24
Finished Aug 03 05:49:19 PM PDT 24
Peak memory 218680 kb
Host smart-ce1ac1b8-4821-42b7-8ac8-f09904bcbbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719625836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2719625836
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2577757569
Short name T393
Test name
Test status
Simulation time 38538992 ps
CPU time 1.26 seconds
Started Aug 03 05:49:13 PM PDT 24
Finished Aug 03 05:49:14 PM PDT 24
Peak memory 206772 kb
Host smart-3c4a9a69-2918-4b1c-bd16-60dc168989a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577757569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2577757569
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1812621503
Short name T182
Test name
Test status
Simulation time 66145974 ps
CPU time 1.24 seconds
Started Aug 03 05:49:14 PM PDT 24
Finished Aug 03 05:49:15 PM PDT 24
Peak memory 216960 kb
Host smart-96ebc626-7fd3-4a9c-bafc-f3cbcdf084e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812621503 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1812621503
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1531351479
Short name T125
Test name
Test status
Simulation time 30448803 ps
CPU time 0.85 seconds
Started Aug 03 05:49:17 PM PDT 24
Finished Aug 03 05:49:18 PM PDT 24
Peak memory 219152 kb
Host smart-18006383-c07d-4f37-a4d4-bc063e2d89b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531351479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1531351479
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1362415126
Short name T532
Test name
Test status
Simulation time 105926446 ps
CPU time 2.4 seconds
Started Aug 03 05:49:13 PM PDT 24
Finished Aug 03 05:49:15 PM PDT 24
Peak memory 220184 kb
Host smart-6455cf18-1074-4e56-96a9-9cce5182ec60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362415126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1362415126
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.625176406
Short name T883
Test name
Test status
Simulation time 37754442 ps
CPU time 0.92 seconds
Started Aug 03 05:49:10 PM PDT 24
Finished Aug 03 05:49:11 PM PDT 24
Peak memory 215360 kb
Host smart-c50d34cf-a7e4-480a-91d0-5b95cafdb587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625176406 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.625176406
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1254080554
Short name T513
Test name
Test status
Simulation time 17014326 ps
CPU time 1.03 seconds
Started Aug 03 05:49:12 PM PDT 24
Finished Aug 03 05:49:13 PM PDT 24
Peak memory 215280 kb
Host smart-2be92ce3-2b81-46e6-be67-dd315b32e58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254080554 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1254080554
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1097543595
Short name T132
Test name
Test status
Simulation time 117884425 ps
CPU time 1.27 seconds
Started Aug 03 05:49:15 PM PDT 24
Finished Aug 03 05:49:16 PM PDT 24
Peak memory 215248 kb
Host smart-e02269dc-18ae-4a51-97ac-5dd7a8a97248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097543595 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1097543595
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1953713474
Short name T233
Test name
Test status
Simulation time 56808216099 ps
CPU time 1208.74 seconds
Started Aug 03 05:49:12 PM PDT 24
Finished Aug 03 06:09:21 PM PDT 24
Peak memory 220328 kb
Host smart-476fdf40-ec3c-464d-a977-52527c4deebf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953713474 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1953713474
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.169066064
Short name T57
Test name
Test status
Simulation time 39098377 ps
CPU time 1.06 seconds
Started Aug 03 05:52:49 PM PDT 24
Finished Aug 03 05:52:50 PM PDT 24
Peak memory 217472 kb
Host smart-ab63b951-772e-426d-a48c-ec480fc7d821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169066064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.169066064
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.4023545834
Short name T79
Test name
Test status
Simulation time 120540386 ps
CPU time 1.11 seconds
Started Aug 03 05:52:50 PM PDT 24
Finished Aug 03 05:52:51 PM PDT 24
Peak memory 217352 kb
Host smart-e1cbc04a-304b-4bf1-a725-228524a003a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023545834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.4023545834
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2643266929
Short name T969
Test name
Test status
Simulation time 83979746 ps
CPU time 1.2 seconds
Started Aug 03 05:52:54 PM PDT 24
Finished Aug 03 05:52:55 PM PDT 24
Peak memory 215316 kb
Host smart-d7d85ae7-7d2b-46a0-8d6f-a011265f8e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643266929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2643266929
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3982082538
Short name T950
Test name
Test status
Simulation time 61825769 ps
CPU time 1.8 seconds
Started Aug 03 05:52:55 PM PDT 24
Finished Aug 03 05:52:57 PM PDT 24
Peak memory 218396 kb
Host smart-65863edb-585a-4c88-a0e2-ab17794ab39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982082538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3982082538
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.4009825618
Short name T610
Test name
Test status
Simulation time 267642805 ps
CPU time 1.06 seconds
Started Aug 03 05:52:54 PM PDT 24
Finished Aug 03 05:52:55 PM PDT 24
Peak memory 217540 kb
Host smart-d1ce57d7-3882-466a-91af-8a63eb9b8053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009825618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.4009825618
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1069833439
Short name T833
Test name
Test status
Simulation time 216442667 ps
CPU time 2.99 seconds
Started Aug 03 05:52:54 PM PDT 24
Finished Aug 03 05:52:57 PM PDT 24
Peak memory 219844 kb
Host smart-0a55b5d9-7808-404a-b386-513b6c52c3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069833439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1069833439
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2215146604
Short name T351
Test name
Test status
Simulation time 86359411 ps
CPU time 1.06 seconds
Started Aug 03 05:52:53 PM PDT 24
Finished Aug 03 05:52:54 PM PDT 24
Peak memory 218812 kb
Host smart-be897618-d6f0-499d-ac9d-d733dc692925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215146604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2215146604
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.97848010
Short name T332
Test name
Test status
Simulation time 121300230 ps
CPU time 1.91 seconds
Started Aug 03 05:52:54 PM PDT 24
Finished Aug 03 05:52:57 PM PDT 24
Peak memory 218936 kb
Host smart-c0d85697-3382-4cf6-956d-90f952a61c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97848010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.97848010
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.738881866
Short name T601
Test name
Test status
Simulation time 46177960 ps
CPU time 1.38 seconds
Started Aug 03 05:52:58 PM PDT 24
Finished Aug 03 05:52:59 PM PDT 24
Peak memory 218860 kb
Host smart-25fb891d-d091-49fb-b6c1-00f24d9dcc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738881866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.738881866
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1071846362
Short name T244
Test name
Test status
Simulation time 56629781 ps
CPU time 1.2 seconds
Started Aug 03 05:52:53 PM PDT 24
Finished Aug 03 05:52:55 PM PDT 24
Peak memory 215324 kb
Host smart-73e06034-33bc-4517-aab4-ad02ba4e7070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071846362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1071846362
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3111069406
Short name T468
Test name
Test status
Simulation time 24859661 ps
CPU time 1.16 seconds
Started Aug 03 05:49:23 PM PDT 24
Finished Aug 03 05:49:24 PM PDT 24
Peak memory 219680 kb
Host smart-5e0134dd-e667-46b8-962a-936bd9417183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111069406 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3111069406
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2044080921
Short name T568
Test name
Test status
Simulation time 29036788 ps
CPU time 0.91 seconds
Started Aug 03 05:49:17 PM PDT 24
Finished Aug 03 05:49:18 PM PDT 24
Peak memory 206716 kb
Host smart-ed462f00-c10d-46eb-953b-28feafe97cf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044080921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2044080921
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.775494980
Short name T703
Test name
Test status
Simulation time 25027823 ps
CPU time 0.87 seconds
Started Aug 03 05:49:27 PM PDT 24
Finished Aug 03 05:49:28 PM PDT 24
Peak memory 215344 kb
Host smart-4d5a4cad-84cf-4d20-92df-9daa03199ba0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775494980 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.775494980
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3299482525
Short name T956
Test name
Test status
Simulation time 37035785 ps
CPU time 1.29 seconds
Started Aug 03 05:49:19 PM PDT 24
Finished Aug 03 05:49:20 PM PDT 24
Peak memory 216980 kb
Host smart-095cbb3a-e200-4d9b-a1a9-76cd6539da03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299482525 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3299482525
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.714357593
Short name T107
Test name
Test status
Simulation time 36362103 ps
CPU time 0.82 seconds
Started Aug 03 05:49:26 PM PDT 24
Finished Aug 03 05:49:27 PM PDT 24
Peak memory 218576 kb
Host smart-87f1ba30-7b4a-4e50-b5bc-4c28e346cfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714357593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.714357593
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3059096724
Short name T539
Test name
Test status
Simulation time 97504537 ps
CPU time 1.04 seconds
Started Aug 03 05:49:20 PM PDT 24
Finished Aug 03 05:49:22 PM PDT 24
Peak memory 217424 kb
Host smart-46a2cb1d-6d14-493c-a2d6-0ef77bcb6d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059096724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3059096724
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3156615745
Short name T91
Test name
Test status
Simulation time 26033221 ps
CPU time 0.94 seconds
Started Aug 03 05:49:26 PM PDT 24
Finished Aug 03 05:49:27 PM PDT 24
Peak memory 215828 kb
Host smart-fe348fc7-24fe-4dfe-afce-d8ad1cf5c30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156615745 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3156615745
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3298300376
Short name T475
Test name
Test status
Simulation time 16422728 ps
CPU time 1 seconds
Started Aug 03 05:49:17 PM PDT 24
Finished Aug 03 05:49:18 PM PDT 24
Peak memory 215268 kb
Host smart-394a041b-c9db-450d-993b-76a63643e114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298300376 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3298300376
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1576180794
Short name T75
Test name
Test status
Simulation time 413453885 ps
CPU time 2.5 seconds
Started Aug 03 05:49:19 PM PDT 24
Finished Aug 03 05:49:22 PM PDT 24
Peak memory 217204 kb
Host smart-a05e6659-422e-4ca1-9431-b78106d57764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576180794 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1576180794
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.4221981632
Short name T228
Test name
Test status
Simulation time 126372664872 ps
CPU time 1526.41 seconds
Started Aug 03 05:49:19 PM PDT 24
Finished Aug 03 06:14:46 PM PDT 24
Peak memory 226156 kb
Host smart-7ca90ee0-e16e-4e8c-bfb8-1ef1c825e58f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221981632 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.4221981632
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2868157967
Short name T313
Test name
Test status
Simulation time 54321895 ps
CPU time 1.46 seconds
Started Aug 03 05:52:54 PM PDT 24
Finished Aug 03 05:52:55 PM PDT 24
Peak memory 218816 kb
Host smart-7c0ac97a-ea13-4c2d-a2fa-1edd81db6bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868157967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2868157967
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3023014788
Short name T376
Test name
Test status
Simulation time 36415889 ps
CPU time 1.34 seconds
Started Aug 03 05:52:52 PM PDT 24
Finished Aug 03 05:52:53 PM PDT 24
Peak memory 219324 kb
Host smart-155a6b4d-8878-49f9-bf2f-87f845b3beb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023014788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3023014788
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.812329229
Short name T869
Test name
Test status
Simulation time 29687434 ps
CPU time 1.26 seconds
Started Aug 03 05:52:54 PM PDT 24
Finished Aug 03 05:52:55 PM PDT 24
Peak memory 218352 kb
Host smart-676790bd-09fd-4ab1-96e2-2d12dbf1a214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812329229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.812329229
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3812442186
Short name T613
Test name
Test status
Simulation time 74198519 ps
CPU time 1.27 seconds
Started Aug 03 05:52:53 PM PDT 24
Finished Aug 03 05:52:54 PM PDT 24
Peak memory 218740 kb
Host smart-23271cfe-3feb-4270-96fa-eaf3461c7dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812442186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3812442186
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.42783110
Short name T447
Test name
Test status
Simulation time 51679767 ps
CPU time 1.32 seconds
Started Aug 03 05:52:53 PM PDT 24
Finished Aug 03 05:52:55 PM PDT 24
Peak memory 218476 kb
Host smart-f811833b-41a3-446f-ae16-6c54d5f2f297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42783110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.42783110
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.282113066
Short name T515
Test name
Test status
Simulation time 167559124 ps
CPU time 1.12 seconds
Started Aug 03 05:52:53 PM PDT 24
Finished Aug 03 05:52:54 PM PDT 24
Peak memory 217144 kb
Host smart-d53c5cc9-e956-4d75-b971-5f500d412679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282113066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.282113066
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1719633933
Short name T684
Test name
Test status
Simulation time 38426728 ps
CPU time 1.04 seconds
Started Aug 03 05:52:52 PM PDT 24
Finished Aug 03 05:52:53 PM PDT 24
Peak memory 217352 kb
Host smart-f59f6766-d63d-46e2-8d84-a6686ae3e8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719633933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1719633933
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2460504970
Short name T965
Test name
Test status
Simulation time 51925685 ps
CPU time 1.03 seconds
Started Aug 03 05:52:58 PM PDT 24
Finished Aug 03 05:52:59 PM PDT 24
Peak memory 217456 kb
Host smart-24a071e6-1dd2-4507-b22c-fcf67dc6ca64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460504970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2460504970
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1847649774
Short name T961
Test name
Test status
Simulation time 63039859 ps
CPU time 1.26 seconds
Started Aug 03 05:52:55 PM PDT 24
Finished Aug 03 05:52:56 PM PDT 24
Peak memory 218384 kb
Host smart-477f5a53-92e2-48a3-9781-736a65fcbc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847649774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1847649774
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3743480318
Short name T167
Test name
Test status
Simulation time 74953810 ps
CPU time 1.09 seconds
Started Aug 03 05:49:18 PM PDT 24
Finished Aug 03 05:49:19 PM PDT 24
Peak memory 218764 kb
Host smart-7e7c971d-f011-46f2-97da-6758e4ba2c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743480318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3743480318
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.184117239
Short name T56
Test name
Test status
Simulation time 180727042 ps
CPU time 0.94 seconds
Started Aug 03 05:49:26 PM PDT 24
Finished Aug 03 05:49:27 PM PDT 24
Peak memory 206724 kb
Host smart-57a1514f-c8ff-4024-bcde-00c5c2f55aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184117239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.184117239
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.683436909
Short name T472
Test name
Test status
Simulation time 52598082 ps
CPU time 1.04 seconds
Started Aug 03 05:49:24 PM PDT 24
Finished Aug 03 05:49:25 PM PDT 24
Peak memory 216732 kb
Host smart-7c27706b-7d7a-48c2-b87e-85fb51b4a8af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683436909 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.683436909
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1816059114
Short name T152
Test name
Test status
Simulation time 46385937 ps
CPU time 1.02 seconds
Started Aug 03 05:49:20 PM PDT 24
Finished Aug 03 05:49:21 PM PDT 24
Peak memory 219780 kb
Host smart-ea3d9516-1641-4845-976e-2a8dd31f1273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816059114 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1816059114
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3024547236
Short name T586
Test name
Test status
Simulation time 88104855 ps
CPU time 1.41 seconds
Started Aug 03 05:49:23 PM PDT 24
Finished Aug 03 05:49:25 PM PDT 24
Peak memory 218760 kb
Host smart-e4dbb032-d615-4201-a0ba-4e5eaa425a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024547236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3024547236
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.675425579
Short name T983
Test name
Test status
Simulation time 25986473 ps
CPU time 0.95 seconds
Started Aug 03 05:49:27 PM PDT 24
Finished Aug 03 05:49:28 PM PDT 24
Peak memory 215908 kb
Host smart-fb717860-2027-479a-8a41-d9c76a510271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675425579 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.675425579
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3213270391
Short name T3
Test name
Test status
Simulation time 77706953 ps
CPU time 0.91 seconds
Started Aug 03 05:49:23 PM PDT 24
Finished Aug 03 05:49:24 PM PDT 24
Peak memory 215284 kb
Host smart-4bdaa779-cc28-446d-9b95-577cf5d7582c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213270391 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3213270391
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3123844702
Short name T503
Test name
Test status
Simulation time 218759117 ps
CPU time 4.68 seconds
Started Aug 03 05:49:19 PM PDT 24
Finished Aug 03 05:49:24 PM PDT 24
Peak memory 217384 kb
Host smart-5b9e1975-c674-4b86-a1e2-beb2984e5c62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123844702 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3123844702
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1605497586
Short name T877
Test name
Test status
Simulation time 29597987791 ps
CPU time 634.59 seconds
Started Aug 03 05:49:18 PM PDT 24
Finished Aug 03 05:59:53 PM PDT 24
Peak memory 223664 kb
Host smart-a98c2160-27f1-48b0-a792-d20be331cbf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605497586 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1605497586
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.104544060
Short name T690
Test name
Test status
Simulation time 32864875 ps
CPU time 1.25 seconds
Started Aug 03 05:52:54 PM PDT 24
Finished Aug 03 05:52:56 PM PDT 24
Peak memory 217268 kb
Host smart-98657987-abf6-4f39-9354-8a932967abca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104544060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.104544060
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2222937196
Short name T533
Test name
Test status
Simulation time 57068009 ps
CPU time 0.97 seconds
Started Aug 03 05:52:57 PM PDT 24
Finished Aug 03 05:52:59 PM PDT 24
Peak memory 217332 kb
Host smart-c3da370e-82f8-47b1-8a84-1b3868e5c910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222937196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2222937196
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3441467820
Short name T829
Test name
Test status
Simulation time 45022316 ps
CPU time 1.76 seconds
Started Aug 03 05:52:58 PM PDT 24
Finished Aug 03 05:53:00 PM PDT 24
Peak memory 218448 kb
Host smart-9a9ad58f-5f6c-4a4a-bf54-7143f0a2163a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441467820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3441467820
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3456255373
Short name T68
Test name
Test status
Simulation time 35762853 ps
CPU time 1.01 seconds
Started Aug 03 05:53:01 PM PDT 24
Finished Aug 03 05:53:02 PM PDT 24
Peak memory 217320 kb
Host smart-b2282542-896c-4b8b-90d6-0d6a6d340c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456255373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3456255373
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.696786253
Short name T374
Test name
Test status
Simulation time 68779300 ps
CPU time 1.14 seconds
Started Aug 03 05:52:57 PM PDT 24
Finished Aug 03 05:52:59 PM PDT 24
Peak memory 217276 kb
Host smart-48c1eec4-626e-4421-ae22-f6598cbe884b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696786253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.696786253
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.103158288
Short name T857
Test name
Test status
Simulation time 130610378 ps
CPU time 1.22 seconds
Started Aug 03 05:52:59 PM PDT 24
Finished Aug 03 05:53:00 PM PDT 24
Peak memory 219820 kb
Host smart-f9086d12-9c0e-41eb-8376-33f38789da7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103158288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.103158288
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.202545510
Short name T321
Test name
Test status
Simulation time 48790992 ps
CPU time 1.8 seconds
Started Aug 03 05:53:03 PM PDT 24
Finished Aug 03 05:53:05 PM PDT 24
Peak memory 220160 kb
Host smart-b25d4cf1-4b89-4161-9b3c-63011f8c9ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202545510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.202545510
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1047089541
Short name T9
Test name
Test status
Simulation time 151458015 ps
CPU time 2.42 seconds
Started Aug 03 05:52:56 PM PDT 24
Finished Aug 03 05:52:59 PM PDT 24
Peak memory 219068 kb
Host smart-e1a2f02e-3e41-4525-a53e-ee88063cc96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047089541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1047089541
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2671021057
Short name T711
Test name
Test status
Simulation time 65871795 ps
CPU time 1.28 seconds
Started Aug 03 05:52:59 PM PDT 24
Finished Aug 03 05:53:00 PM PDT 24
Peak memory 217444 kb
Host smart-5f0043a7-10a9-4bb7-bd80-33778992ed17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671021057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2671021057
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.4290526424
Short name T221
Test name
Test status
Simulation time 24064425 ps
CPU time 1.25 seconds
Started Aug 03 05:49:26 PM PDT 24
Finished Aug 03 05:49:27 PM PDT 24
Peak memory 218788 kb
Host smart-5903cc1a-80e8-4717-bf7f-ae78ab58199c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290526424 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.4290526424
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3908577615
Short name T765
Test name
Test status
Simulation time 41699394 ps
CPU time 0.89 seconds
Started Aug 03 05:49:25 PM PDT 24
Finished Aug 03 05:49:26 PM PDT 24
Peak memory 206504 kb
Host smart-d878f533-9bb0-4499-92a6-2bbd268c9b23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908577615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3908577615
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2663060104
Short name T112
Test name
Test status
Simulation time 61566644 ps
CPU time 0.84 seconds
Started Aug 03 05:49:26 PM PDT 24
Finished Aug 03 05:49:27 PM PDT 24
Peak memory 216144 kb
Host smart-a5282a06-788c-4bab-89bf-c13e97943a6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663060104 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2663060104
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2925306727
Short name T464
Test name
Test status
Simulation time 61936986 ps
CPU time 1.03 seconds
Started Aug 03 05:49:26 PM PDT 24
Finished Aug 03 05:49:27 PM PDT 24
Peak memory 218344 kb
Host smart-8b70d876-e07e-4dca-b20c-d86370d436cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925306727 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2925306727
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2742138360
Short name T365
Test name
Test status
Simulation time 23702882 ps
CPU time 0.97 seconds
Started Aug 03 05:49:24 PM PDT 24
Finished Aug 03 05:49:26 PM PDT 24
Peak memory 218268 kb
Host smart-12d5aa49-3c6e-469d-b7ce-c1b5feb41de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742138360 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2742138360
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_intr.1643771624
Short name T90
Test name
Test status
Simulation time 23324554 ps
CPU time 0.93 seconds
Started Aug 03 05:49:26 PM PDT 24
Finished Aug 03 05:49:27 PM PDT 24
Peak memory 216060 kb
Host smart-b894c05f-1d28-4da2-a350-a01e2907dd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643771624 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1643771624
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1395524917
Short name T647
Test name
Test status
Simulation time 43269188 ps
CPU time 0.92 seconds
Started Aug 03 05:49:26 PM PDT 24
Finished Aug 03 05:49:27 PM PDT 24
Peak memory 215408 kb
Host smart-7416d05a-f4b2-4ecd-b3df-d8bb5eacf2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395524917 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1395524917
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1073397335
Short name T4
Test name
Test status
Simulation time 496333380 ps
CPU time 2.92 seconds
Started Aug 03 05:49:26 PM PDT 24
Finished Aug 03 05:49:29 PM PDT 24
Peak memory 219916 kb
Host smart-9661dcd5-ed74-4cec-9d1d-d8d11b8e6ab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073397335 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1073397335
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3216613751
Short name T960
Test name
Test status
Simulation time 400650918079 ps
CPU time 2320.74 seconds
Started Aug 03 05:49:26 PM PDT 24
Finished Aug 03 06:28:07 PM PDT 24
Peak memory 227248 kb
Host smart-8cec0b62-c423-4878-86ea-17766e1856bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216613751 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3216613751
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2271202441
Short name T30
Test name
Test status
Simulation time 258628421 ps
CPU time 1.46 seconds
Started Aug 03 05:52:59 PM PDT 24
Finished Aug 03 05:53:01 PM PDT 24
Peak memory 217432 kb
Host smart-902673a9-7784-4568-a953-a39c10d26e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271202441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2271202441
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2372312268
Short name T445
Test name
Test status
Simulation time 48490555 ps
CPU time 1.19 seconds
Started Aug 03 05:52:59 PM PDT 24
Finished Aug 03 05:53:01 PM PDT 24
Peak memory 218680 kb
Host smart-d3e57a4b-f759-4ab4-a5ce-f04697f1f13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372312268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2372312268
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3463080202
Short name T406
Test name
Test status
Simulation time 39946245 ps
CPU time 1.56 seconds
Started Aug 03 05:52:58 PM PDT 24
Finished Aug 03 05:52:59 PM PDT 24
Peak memory 217560 kb
Host smart-67b85982-0fe4-4322-9c19-165ad8c9f7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463080202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3463080202
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3290205718
Short name T629
Test name
Test status
Simulation time 59061451 ps
CPU time 1.17 seconds
Started Aug 03 05:52:56 PM PDT 24
Finished Aug 03 05:52:57 PM PDT 24
Peak memory 218496 kb
Host smart-73211d4b-613b-4dbf-80f4-7f2cc3077cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290205718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3290205718
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1120705808
Short name T413
Test name
Test status
Simulation time 43383328 ps
CPU time 1.68 seconds
Started Aug 03 05:52:58 PM PDT 24
Finished Aug 03 05:53:00 PM PDT 24
Peak memory 220132 kb
Host smart-0798015a-ff2f-4dbb-956d-8553ec6c6586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120705808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1120705808
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.358567906
Short name T581
Test name
Test status
Simulation time 107496063 ps
CPU time 1.34 seconds
Started Aug 03 05:53:01 PM PDT 24
Finished Aug 03 05:53:02 PM PDT 24
Peak memory 218536 kb
Host smart-3f080317-fbb3-4c9f-b04a-fe0ad99c4acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358567906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.358567906
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2240100364
Short name T664
Test name
Test status
Simulation time 118848640 ps
CPU time 2.48 seconds
Started Aug 03 05:52:57 PM PDT 24
Finished Aug 03 05:53:00 PM PDT 24
Peak memory 215296 kb
Host smart-412acd68-36ef-4938-8df6-ea3014152e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240100364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2240100364
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3174776473
Short name T805
Test name
Test status
Simulation time 97748792 ps
CPU time 1.52 seconds
Started Aug 03 05:52:58 PM PDT 24
Finished Aug 03 05:53:00 PM PDT 24
Peak memory 218652 kb
Host smart-d7244d3a-c1e7-45f1-bddd-1a8781fe5cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174776473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3174776473
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3974394529
Short name T751
Test name
Test status
Simulation time 70230041 ps
CPU time 2.36 seconds
Started Aug 03 05:53:01 PM PDT 24
Finished Aug 03 05:53:03 PM PDT 24
Peak memory 220100 kb
Host smart-0c9730f8-49dd-4ea3-a50c-66318b54de0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974394529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3974394529
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1172008167
Short name T835
Test name
Test status
Simulation time 52405680 ps
CPU time 1.6 seconds
Started Aug 03 05:53:02 PM PDT 24
Finished Aug 03 05:53:04 PM PDT 24
Peak memory 219332 kb
Host smart-85af7146-db0d-47ce-916f-c8fd752baa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172008167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1172008167
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.292340071
Short name T251
Test name
Test status
Simulation time 167172212 ps
CPU time 1.23 seconds
Started Aug 03 05:47:05 PM PDT 24
Finished Aug 03 05:47:06 PM PDT 24
Peak memory 215724 kb
Host smart-37f18d6f-7dc4-463c-84c8-72c04b4d8c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292340071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.292340071
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.14038946
Short name T691
Test name
Test status
Simulation time 20811783 ps
CPU time 1.05 seconds
Started Aug 03 05:47:04 PM PDT 24
Finished Aug 03 05:47:06 PM PDT 24
Peak memory 206724 kb
Host smart-3bb9a148-aa41-4aee-8d1e-f47c021bb401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14038946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.14038946
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.4023535262
Short name T545
Test name
Test status
Simulation time 34037797 ps
CPU time 0.87 seconds
Started Aug 03 05:47:05 PM PDT 24
Finished Aug 03 05:47:06 PM PDT 24
Peak memory 215372 kb
Host smart-58a3d2cc-9210-45cb-ab00-06216d2ab1f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023535262 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.4023535262
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3893301187
Short name T782
Test name
Test status
Simulation time 154813988 ps
CPU time 1.17 seconds
Started Aug 03 05:47:06 PM PDT 24
Finished Aug 03 05:47:08 PM PDT 24
Peak memory 218564 kb
Host smart-31fd1ff0-5e05-46ec-9f98-cb31519194ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893301187 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3893301187
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1890024476
Short name T348
Test name
Test status
Simulation time 58884795 ps
CPU time 1.03 seconds
Started Aug 03 05:47:05 PM PDT 24
Finished Aug 03 05:47:06 PM PDT 24
Peak memory 219588 kb
Host smart-61eba7bd-e403-425d-97b1-3c902c373935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890024476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1890024476
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2306631044
Short name T603
Test name
Test status
Simulation time 35478470 ps
CPU time 1.31 seconds
Started Aug 03 05:46:59 PM PDT 24
Finished Aug 03 05:47:01 PM PDT 24
Peak memory 218492 kb
Host smart-94f4ffe1-5ea3-42b2-a49f-4fbcfbef8753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306631044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2306631044
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3338217020
Short name T478
Test name
Test status
Simulation time 35569759 ps
CPU time 0.93 seconds
Started Aug 03 05:47:05 PM PDT 24
Finished Aug 03 05:47:06 PM PDT 24
Peak memory 215708 kb
Host smart-7c20261f-fb29-47dd-96d1-9acedcff0db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338217020 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3338217020
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_smoke.4168706268
Short name T734
Test name
Test status
Simulation time 46732030 ps
CPU time 0.94 seconds
Started Aug 03 05:46:58 PM PDT 24
Finished Aug 03 05:47:00 PM PDT 24
Peak memory 215280 kb
Host smart-5e21349b-6a57-4c15-89bb-c193d5c25022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168706268 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.4168706268
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3849489997
Short name T241
Test name
Test status
Simulation time 337507202 ps
CPU time 3.56 seconds
Started Aug 03 05:47:12 PM PDT 24
Finished Aug 03 05:47:16 PM PDT 24
Peak memory 217200 kb
Host smart-b12975a6-6c27-482d-b58e-3e070d98c8ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849489997 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3849489997
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1072417482
Short name T687
Test name
Test status
Simulation time 261715566173 ps
CPU time 535.35 seconds
Started Aug 03 05:47:06 PM PDT 24
Finished Aug 03 05:56:02 PM PDT 24
Peak memory 219464 kb
Host smart-c7380880-1ab4-4cb2-b3a2-e00175277253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072417482 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1072417482
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1223068046
Short name T661
Test name
Test status
Simulation time 56198294 ps
CPU time 1.27 seconds
Started Aug 03 05:49:32 PM PDT 24
Finished Aug 03 05:49:33 PM PDT 24
Peak memory 215604 kb
Host smart-5670a3d6-bf89-4ff4-98bc-af5709f0e1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223068046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1223068046
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1583479326
Short name T595
Test name
Test status
Simulation time 49384969 ps
CPU time 0.91 seconds
Started Aug 03 05:49:32 PM PDT 24
Finished Aug 03 05:49:33 PM PDT 24
Peak memory 206728 kb
Host smart-875f3c46-bbed-43e3-ad3f-7f82d007ff03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583479326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1583479326
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3165661965
Short name T414
Test name
Test status
Simulation time 41975627 ps
CPU time 0.8 seconds
Started Aug 03 05:49:35 PM PDT 24
Finished Aug 03 05:49:36 PM PDT 24
Peak memory 216328 kb
Host smart-f73561bb-58ae-4358-a1c8-e94d77948634
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165661965 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3165661965
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2366079393
Short name T638
Test name
Test status
Simulation time 91720794 ps
CPU time 1.17 seconds
Started Aug 03 05:49:45 PM PDT 24
Finished Aug 03 05:49:47 PM PDT 24
Peak memory 216980 kb
Host smart-fa4209f2-db0f-4f3a-8eb4-6a9bd0304e77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366079393 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2366079393
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3744369393
Short name T186
Test name
Test status
Simulation time 26230325 ps
CPU time 1.02 seconds
Started Aug 03 05:49:31 PM PDT 24
Finished Aug 03 05:49:32 PM PDT 24
Peak memory 223868 kb
Host smart-054fd67c-eee8-4682-ab3f-e620645d4bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744369393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3744369393
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.545579292
Short name T243
Test name
Test status
Simulation time 49022657 ps
CPU time 1.27 seconds
Started Aug 03 05:49:26 PM PDT 24
Finished Aug 03 05:49:27 PM PDT 24
Peak memory 215228 kb
Host smart-f3322e2d-c428-4358-8730-b52795745f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545579292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.545579292
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2057174012
Short name T611
Test name
Test status
Simulation time 38119594 ps
CPU time 0.99 seconds
Started Aug 03 05:49:26 PM PDT 24
Finished Aug 03 05:49:28 PM PDT 24
Peak memory 224044 kb
Host smart-7dd04d29-25f8-43da-aefa-a558e1d2313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057174012 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2057174012
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1090608949
Short name T368
Test name
Test status
Simulation time 17167398 ps
CPU time 0.97 seconds
Started Aug 03 05:49:27 PM PDT 24
Finished Aug 03 05:49:28 PM PDT 24
Peak memory 215232 kb
Host smart-21b3085b-ec81-43c4-afd5-eeb677951fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090608949 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1090608949
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2287725471
Short name T809
Test name
Test status
Simulation time 179607556 ps
CPU time 1.51 seconds
Started Aug 03 05:49:25 PM PDT 24
Finished Aug 03 05:49:27 PM PDT 24
Peak memory 215304 kb
Host smart-98387166-6198-45c7-8e3e-62119da24fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287725471 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2287725471
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3687580849
Short name T879
Test name
Test status
Simulation time 84696185882 ps
CPU time 1703.96 seconds
Started Aug 03 05:49:25 PM PDT 24
Finished Aug 03 06:17:49 PM PDT 24
Peak memory 226400 kb
Host smart-429b29f2-d67f-4c76-9eb2-bc48b69bf8ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687580849 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3687580849
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2195080562
Short name T618
Test name
Test status
Simulation time 29316933 ps
CPU time 1.37 seconds
Started Aug 03 05:49:46 PM PDT 24
Finished Aug 03 05:49:47 PM PDT 24
Peak memory 218532 kb
Host smart-c5f250c2-5dbf-4c49-93cc-958be746c778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195080562 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2195080562
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.383779136
Short name T785
Test name
Test status
Simulation time 54011196 ps
CPU time 0.93 seconds
Started Aug 03 05:49:46 PM PDT 24
Finished Aug 03 05:49:47 PM PDT 24
Peak memory 206376 kb
Host smart-10ee05ba-2276-4860-afd8-d59c522a5114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383779136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.383779136
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3968647989
Short name T903
Test name
Test status
Simulation time 22732732 ps
CPU time 0.95 seconds
Started Aug 03 05:49:46 PM PDT 24
Finished Aug 03 05:49:47 PM PDT 24
Peak memory 216280 kb
Host smart-67eefd9b-2e4f-4d33-9d64-cf97731618ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968647989 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3968647989
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2699295551
Short name T481
Test name
Test status
Simulation time 86673514 ps
CPU time 1.14 seconds
Started Aug 03 05:49:32 PM PDT 24
Finished Aug 03 05:49:33 PM PDT 24
Peak memory 218152 kb
Host smart-b966de03-7032-48f0-ac2d-cb2c0ca58da2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699295551 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2699295551
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3206941837
Short name T872
Test name
Test status
Simulation time 34295983 ps
CPU time 0.92 seconds
Started Aug 03 05:49:46 PM PDT 24
Finished Aug 03 05:49:47 PM PDT 24
Peak memory 219176 kb
Host smart-549ed92f-5bc1-4297-b179-b1962f9b214a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206941837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3206941837
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2547439585
Short name T307
Test name
Test status
Simulation time 49356143 ps
CPU time 1.46 seconds
Started Aug 03 05:49:31 PM PDT 24
Finished Aug 03 05:49:32 PM PDT 24
Peak memory 218824 kb
Host smart-ccb27f69-fc48-4753-94ba-70b82c3fdbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547439585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2547439585
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.4113431942
Short name T855
Test name
Test status
Simulation time 22125737 ps
CPU time 1.19 seconds
Started Aug 03 05:49:34 PM PDT 24
Finished Aug 03 05:49:36 PM PDT 24
Peak memory 224012 kb
Host smart-bba25c2b-b8a6-4896-aa0e-380bbd376a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113431942 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.4113431942
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3451978287
Short name T558
Test name
Test status
Simulation time 40873505 ps
CPU time 0.94 seconds
Started Aug 03 05:49:46 PM PDT 24
Finished Aug 03 05:49:47 PM PDT 24
Peak memory 215256 kb
Host smart-87ccae02-84cc-443d-99a9-0f29a8ff4802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451978287 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3451978287
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.775141278
Short name T310
Test name
Test status
Simulation time 515684511 ps
CPU time 2.95 seconds
Started Aug 03 05:49:32 PM PDT 24
Finished Aug 03 05:49:35 PM PDT 24
Peak memory 217184 kb
Host smart-636b2dcd-a6af-4199-8efd-b599ac0140cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775141278 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.775141278
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2768568503
Short name T22
Test name
Test status
Simulation time 26930267460 ps
CPU time 327.75 seconds
Started Aug 03 05:49:32 PM PDT 24
Finished Aug 03 05:55:00 PM PDT 24
Peak memory 223624 kb
Host smart-c0092274-23ef-4bb4-b486-2a5233f8a2fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768568503 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2768568503
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.786250591
Short name T466
Test name
Test status
Simulation time 48194850 ps
CPU time 1.28 seconds
Started Aug 03 05:49:38 PM PDT 24
Finished Aug 03 05:49:39 PM PDT 24
Peak memory 219696 kb
Host smart-7bca0564-08f4-4fff-aba6-b7a306a544d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786250591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.786250591
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3789483683
Short name T400
Test name
Test status
Simulation time 24519795 ps
CPU time 1.12 seconds
Started Aug 03 05:49:35 PM PDT 24
Finished Aug 03 05:49:37 PM PDT 24
Peak memory 214884 kb
Host smart-0cb827ba-76d2-4b85-944e-80e7ea1a283e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789483683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3789483683
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.849919038
Short name T469
Test name
Test status
Simulation time 21157961 ps
CPU time 0.89 seconds
Started Aug 03 05:49:35 PM PDT 24
Finished Aug 03 05:49:36 PM PDT 24
Peak memory 215408 kb
Host smart-7c38ffba-1ef6-45cd-a036-0c06f2c1045c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849919038 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.849919038
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.925292883
Short name T909
Test name
Test status
Simulation time 78259197 ps
CPU time 1.24 seconds
Started Aug 03 05:49:36 PM PDT 24
Finished Aug 03 05:49:37 PM PDT 24
Peak memory 216756 kb
Host smart-b257fe42-3859-498f-a5ab-6ea11001295e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925292883 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.925292883
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.519690062
Short name T410
Test name
Test status
Simulation time 29925964 ps
CPU time 1.01 seconds
Started Aug 03 05:49:36 PM PDT 24
Finished Aug 03 05:49:37 PM PDT 24
Peak memory 218624 kb
Host smart-62e55591-ffd1-4acd-bf24-df9a8274ca93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519690062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.519690062
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3975470063
Short name T465
Test name
Test status
Simulation time 69775975 ps
CPU time 1.4 seconds
Started Aug 03 05:49:31 PM PDT 24
Finished Aug 03 05:49:33 PM PDT 24
Peak memory 217324 kb
Host smart-1a0360d8-c435-45ff-8ab9-612a08fe6e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975470063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3975470063
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_smoke.3834850632
Short name T380
Test name
Test status
Simulation time 27691635 ps
CPU time 0.85 seconds
Started Aug 03 05:49:36 PM PDT 24
Finished Aug 03 05:49:37 PM PDT 24
Peak memory 215304 kb
Host smart-0fd8f82c-4f54-4339-9a4e-b2940e519571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834850632 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3834850632
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3514840941
Short name T137
Test name
Test status
Simulation time 313026380 ps
CPU time 6.02 seconds
Started Aug 03 05:49:31 PM PDT 24
Finished Aug 03 05:49:37 PM PDT 24
Peak memory 217188 kb
Host smart-2855e5e8-5617-463f-b54b-462d3c928f4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514840941 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3514840941
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1063993978
Short name T947
Test name
Test status
Simulation time 773178210561 ps
CPU time 2462.05 seconds
Started Aug 03 05:49:30 PM PDT 24
Finished Aug 03 06:30:32 PM PDT 24
Peak memory 230812 kb
Host smart-b84a16b6-4516-4519-b597-33c2183d7602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063993978 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1063993978
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.4079839833
Short name T653
Test name
Test status
Simulation time 59809456 ps
CPU time 1.28 seconds
Started Aug 03 05:49:39 PM PDT 24
Finished Aug 03 05:49:40 PM PDT 24
Peak memory 219044 kb
Host smart-70644592-12a7-4d5c-b8ac-542aebb97be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079839833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.4079839833
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.647608123
Short name T729
Test name
Test status
Simulation time 13787847 ps
CPU time 0.9 seconds
Started Aug 03 05:49:45 PM PDT 24
Finished Aug 03 05:49:46 PM PDT 24
Peak memory 215088 kb
Host smart-302b82d3-b192-4df3-9723-8ad76ea5584a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647608123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.647608123
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2310261986
Short name T119
Test name
Test status
Simulation time 12399900 ps
CPU time 0.88 seconds
Started Aug 03 05:49:42 PM PDT 24
Finished Aug 03 05:49:43 PM PDT 24
Peak memory 216492 kb
Host smart-c634c93f-a743-4bcb-843c-2839a4d8d9e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310261986 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2310261986
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3252087044
Short name T678
Test name
Test status
Simulation time 91083605 ps
CPU time 1.01 seconds
Started Aug 03 05:49:42 PM PDT 24
Finished Aug 03 05:49:43 PM PDT 24
Peak memory 217052 kb
Host smart-5addc1b0-cb3a-4d64-a4c0-2cc3b7504c75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252087044 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3252087044
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.554578568
Short name T181
Test name
Test status
Simulation time 24304946 ps
CPU time 1.21 seconds
Started Aug 03 05:49:44 PM PDT 24
Finished Aug 03 05:49:45 PM PDT 24
Peak memory 220528 kb
Host smart-e7fe425f-389d-49c3-853c-fb71577c06c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554578568 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.554578568
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1899825186
Short name T698
Test name
Test status
Simulation time 26416524 ps
CPU time 1.23 seconds
Started Aug 03 05:49:35 PM PDT 24
Finished Aug 03 05:49:36 PM PDT 24
Peak memory 217560 kb
Host smart-cc656f00-f794-439d-8b6e-3096342828b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899825186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1899825186
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.604710349
Short name T370
Test name
Test status
Simulation time 22106748 ps
CPU time 1.22 seconds
Started Aug 03 05:49:46 PM PDT 24
Finished Aug 03 05:49:47 PM PDT 24
Peak memory 215328 kb
Host smart-34ed1872-0172-483d-9898-25a9eb6d39ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604710349 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.604710349
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2939977696
Short name T821
Test name
Test status
Simulation time 39503034 ps
CPU time 0.89 seconds
Started Aug 03 05:49:36 PM PDT 24
Finished Aug 03 05:49:37 PM PDT 24
Peak memory 215296 kb
Host smart-04a6c3ba-6680-4515-b381-a9fe1b418616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939977696 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2939977696
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.889924328
Short name T44
Test name
Test status
Simulation time 236589161 ps
CPU time 1.63 seconds
Started Aug 03 05:49:46 PM PDT 24
Finished Aug 03 05:49:48 PM PDT 24
Peak memory 215248 kb
Host smart-e0661dec-ca3e-4754-bb53-3d6e64a09640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889924328 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.889924328
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.71456013
Short name T234
Test name
Test status
Simulation time 119476784638 ps
CPU time 1687.81 seconds
Started Aug 03 05:49:37 PM PDT 24
Finished Aug 03 06:17:45 PM PDT 24
Peak memory 232160 kb
Host smart-fd26e17b-4d38-440f-a392-da2e69958b12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71456013 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.71456013
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.613160237
Short name T199
Test name
Test status
Simulation time 24977340 ps
CPU time 1.18 seconds
Started Aug 03 05:49:51 PM PDT 24
Finished Aug 03 05:49:52 PM PDT 24
Peak memory 215708 kb
Host smart-4a82956d-86aa-4629-9951-25d3af1c6b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613160237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.613160237
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.454418700
Short name T789
Test name
Test status
Simulation time 53037867 ps
CPU time 1 seconds
Started Aug 03 05:49:51 PM PDT 24
Finished Aug 03 05:49:52 PM PDT 24
Peak memory 215144 kb
Host smart-a61105ef-7fea-4cd6-b738-8ec28a0b2a23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454418700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.454418700
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.4230851329
Short name T723
Test name
Test status
Simulation time 39416358 ps
CPU time 0.87 seconds
Started Aug 03 05:49:50 PM PDT 24
Finished Aug 03 05:49:51 PM PDT 24
Peak memory 216212 kb
Host smart-44118358-8751-47b1-8cf2-08f9a5630de9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230851329 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.4230851329
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.3262427792
Short name T850
Test name
Test status
Simulation time 43553099 ps
CPU time 1.18 seconds
Started Aug 03 05:49:49 PM PDT 24
Finished Aug 03 05:49:50 PM PDT 24
Peak memory 225744 kb
Host smart-029ee462-1296-479c-bcf7-df8b5e1cc26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262427792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3262427792
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.828033159
Short name T521
Test name
Test status
Simulation time 46391123 ps
CPU time 1.16 seconds
Started Aug 03 05:49:51 PM PDT 24
Finished Aug 03 05:49:52 PM PDT 24
Peak memory 217412 kb
Host smart-850d1cde-756d-4b6c-baef-447a1b28efc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828033159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.828033159
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1286254675
Short name T15
Test name
Test status
Simulation time 22485435 ps
CPU time 1.12 seconds
Started Aug 03 05:49:50 PM PDT 24
Finished Aug 03 05:49:51 PM PDT 24
Peak memory 223972 kb
Host smart-cb507b7f-eda6-41e0-af41-92a5aaed2a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286254675 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1286254675
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2373081151
Short name T366
Test name
Test status
Simulation time 22113193 ps
CPU time 0.91 seconds
Started Aug 03 05:49:42 PM PDT 24
Finished Aug 03 05:49:43 PM PDT 24
Peak memory 215240 kb
Host smart-44d1f6db-94bb-4251-be4e-e49698494519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373081151 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2373081151
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.4251963103
Short name T880
Test name
Test status
Simulation time 313677149 ps
CPU time 3.66 seconds
Started Aug 03 05:49:52 PM PDT 24
Finished Aug 03 05:49:56 PM PDT 24
Peak memory 217176 kb
Host smart-dfd71457-c768-4a5b-b137-85c411edd559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251963103 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.4251963103
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.613334660
Short name T744
Test name
Test status
Simulation time 79927110675 ps
CPU time 507.1 seconds
Started Aug 03 05:49:52 PM PDT 24
Finished Aug 03 05:58:19 PM PDT 24
Peak memory 223692 kb
Host smart-862fae6c-d876-46ae-9482-2a2087833235
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613334660 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.613334660
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3250510111
Short name T818
Test name
Test status
Simulation time 29051721 ps
CPU time 1.18 seconds
Started Aug 03 05:49:52 PM PDT 24
Finished Aug 03 05:49:53 PM PDT 24
Peak memory 219624 kb
Host smart-89a81391-7fb1-4b3c-90aa-21f1f307b5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250510111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3250510111
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2495995694
Short name T665
Test name
Test status
Simulation time 57076063 ps
CPU time 0.89 seconds
Started Aug 03 05:50:00 PM PDT 24
Finished Aug 03 05:50:01 PM PDT 24
Peak memory 215116 kb
Host smart-75dc885a-94af-4bf4-933c-488cd34bf8fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495995694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2495995694
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2050725910
Short name T201
Test name
Test status
Simulation time 31314901 ps
CPU time 0.86 seconds
Started Aug 03 05:49:49 PM PDT 24
Finished Aug 03 05:49:50 PM PDT 24
Peak memory 216232 kb
Host smart-964c6d1a-ecf1-4755-a1ae-248b4c53e97d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050725910 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2050725910
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1696435345
Short name T885
Test name
Test status
Simulation time 45557113 ps
CPU time 1.07 seconds
Started Aug 03 05:49:56 PM PDT 24
Finished Aug 03 05:49:57 PM PDT 24
Peak memory 218760 kb
Host smart-5c962edf-4c23-4960-ad5e-179b22d57856
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696435345 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1696435345
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2775030964
Short name T129
Test name
Test status
Simulation time 101769654 ps
CPU time 1.01 seconds
Started Aug 03 05:49:51 PM PDT 24
Finished Aug 03 05:49:52 PM PDT 24
Peak memory 219872 kb
Host smart-02753dbb-ce73-406b-9243-7b061f317d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775030964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2775030964
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2251371541
Short name T832
Test name
Test status
Simulation time 27030662 ps
CPU time 1.2 seconds
Started Aug 03 05:49:52 PM PDT 24
Finished Aug 03 05:49:53 PM PDT 24
Peak memory 217268 kb
Host smart-2a2e6b31-3d6f-4027-a760-07114ae71efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251371541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2251371541
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3558282951
Short name T388
Test name
Test status
Simulation time 21337602 ps
CPU time 1.09 seconds
Started Aug 03 05:49:51 PM PDT 24
Finished Aug 03 05:49:52 PM PDT 24
Peak memory 215316 kb
Host smart-ef1faa34-c97b-4bc9-a7f5-d0aabf7555b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558282951 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3558282951
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2947851944
Short name T399
Test name
Test status
Simulation time 170654128 ps
CPU time 0.96 seconds
Started Aug 03 05:49:50 PM PDT 24
Finished Aug 03 05:49:51 PM PDT 24
Peak memory 215280 kb
Host smart-e9e5c05b-bf2d-4c28-ab1c-9093190f55d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947851944 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2947851944
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1529946073
Short name T408
Test name
Test status
Simulation time 250387959 ps
CPU time 1.72 seconds
Started Aug 03 05:49:51 PM PDT 24
Finished Aug 03 05:49:52 PM PDT 24
Peak memory 217188 kb
Host smart-f69f410e-1464-4769-a482-8c69f2780b85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529946073 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1529946073
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1723941555
Short name T484
Test name
Test status
Simulation time 1342209061794 ps
CPU time 2587.25 seconds
Started Aug 03 05:49:51 PM PDT 24
Finished Aug 03 06:32:59 PM PDT 24
Peak memory 230032 kb
Host smart-3b97cd76-42b0-48eb-9126-a7779a23d580
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723941555 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1723941555
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1311628839
Short name T291
Test name
Test status
Simulation time 48540958 ps
CPU time 1.17 seconds
Started Aug 03 05:49:53 PM PDT 24
Finished Aug 03 05:49:54 PM PDT 24
Peak memory 218348 kb
Host smart-8a913a81-620e-4f20-8499-6f20268b25ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311628839 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1311628839
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2018072656
Short name T671
Test name
Test status
Simulation time 13268743 ps
CPU time 0.89 seconds
Started Aug 03 05:49:55 PM PDT 24
Finished Aug 03 05:49:56 PM PDT 24
Peak memory 206700 kb
Host smart-305e20f2-2713-47aa-afae-b171204edef9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018072656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2018072656
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3885225542
Short name T392
Test name
Test status
Simulation time 16961837 ps
CPU time 0.82 seconds
Started Aug 03 05:49:57 PM PDT 24
Finished Aug 03 05:49:58 PM PDT 24
Peak memory 215936 kb
Host smart-074c054e-e2f5-4975-a148-7fc7b4b4b71e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885225542 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3885225542
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.4158154294
Short name T183
Test name
Test status
Simulation time 34682540 ps
CPU time 1.1 seconds
Started Aug 03 05:49:58 PM PDT 24
Finished Aug 03 05:49:59 PM PDT 24
Peak memory 216784 kb
Host smart-6b28df2e-6788-40a0-b7a7-df59658f683a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158154294 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.4158154294
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2961724221
Short name T819
Test name
Test status
Simulation time 33889870 ps
CPU time 1.18 seconds
Started Aug 03 05:49:54 PM PDT 24
Finished Aug 03 05:49:55 PM PDT 24
Peak memory 229644 kb
Host smart-9a4eff69-eecb-4176-bd90-b83b5c64b82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961724221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2961724221
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.705738623
Short name T752
Test name
Test status
Simulation time 102044304 ps
CPU time 1.11 seconds
Started Aug 03 05:49:56 PM PDT 24
Finished Aug 03 05:49:57 PM PDT 24
Peak memory 217264 kb
Host smart-960a30b1-411c-41ed-bbe0-d59f7e78a804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705738623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.705738623
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3423238843
Short name T802
Test name
Test status
Simulation time 33518290 ps
CPU time 1.02 seconds
Started Aug 03 05:49:57 PM PDT 24
Finished Aug 03 05:49:58 PM PDT 24
Peak memory 224048 kb
Host smart-5eb0db4d-e719-4c82-890e-88e700faf637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423238843 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3423238843
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3866985176
Short name T386
Test name
Test status
Simulation time 30305255 ps
CPU time 0.99 seconds
Started Aug 03 05:49:53 PM PDT 24
Finished Aug 03 05:49:54 PM PDT 24
Peak memory 215284 kb
Host smart-871cb7bd-fd39-4a69-bb40-f6b98b20f9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866985176 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3866985176
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2812936864
Short name T738
Test name
Test status
Simulation time 213509479 ps
CPU time 4.59 seconds
Started Aug 03 05:49:58 PM PDT 24
Finished Aug 03 05:50:03 PM PDT 24
Peak memory 215216 kb
Host smart-c0d70699-9816-40c3-9a2c-ede687c232b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812936864 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2812936864
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.761834687
Short name T227
Test name
Test status
Simulation time 57133620106 ps
CPU time 768.62 seconds
Started Aug 03 05:49:54 PM PDT 24
Finished Aug 03 06:02:43 PM PDT 24
Peak memory 223612 kb
Host smart-7b33a7cc-8f62-4ac8-8682-5a83c4c7d61c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761834687 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.761834687
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3755061622
Short name T289
Test name
Test status
Simulation time 25078197 ps
CPU time 1.22 seconds
Started Aug 03 05:49:56 PM PDT 24
Finished Aug 03 05:49:58 PM PDT 24
Peak memory 218876 kb
Host smart-becf8736-322e-43a5-b14e-d9faaff95164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755061622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3755061622
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2385944337
Short name T538
Test name
Test status
Simulation time 36569020 ps
CPU time 0.91 seconds
Started Aug 03 05:50:00 PM PDT 24
Finished Aug 03 05:50:01 PM PDT 24
Peak memory 206668 kb
Host smart-017f94ad-6d58-47dc-955e-8c5797139758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385944337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2385944337
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.376104284
Short name T915
Test name
Test status
Simulation time 40669464 ps
CPU time 0.9 seconds
Started Aug 03 05:49:56 PM PDT 24
Finished Aug 03 05:49:56 PM PDT 24
Peak memory 216164 kb
Host smart-e0afbc6f-35a9-4795-9e0a-7039561b7923
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376104284 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.376104284
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.674740178
Short name T500
Test name
Test status
Simulation time 93748021 ps
CPU time 1.06 seconds
Started Aug 03 05:49:58 PM PDT 24
Finished Aug 03 05:49:59 PM PDT 24
Peak memory 218576 kb
Host smart-02c89fdd-f32f-42d0-a920-93c0c672616f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674740178 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.674740178
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1871987379
Short name T617
Test name
Test status
Simulation time 29012825 ps
CPU time 0.93 seconds
Started Aug 03 05:49:55 PM PDT 24
Finished Aug 03 05:49:56 PM PDT 24
Peak memory 218700 kb
Host smart-512d030d-6125-45c7-a8fc-1815c0e75654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871987379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1871987379
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3459055351
Short name T467
Test name
Test status
Simulation time 39095767 ps
CPU time 1.68 seconds
Started Aug 03 05:49:51 PM PDT 24
Finished Aug 03 05:49:52 PM PDT 24
Peak memory 217620 kb
Host smart-b0c4c3cc-137e-42b5-ba22-577303fcbb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459055351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3459055351
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.685762438
Short name T600
Test name
Test status
Simulation time 27908854 ps
CPU time 0.97 seconds
Started Aug 03 05:49:56 PM PDT 24
Finished Aug 03 05:49:57 PM PDT 24
Peak memory 215764 kb
Host smart-4e0fa3ec-e5c6-4e46-aefe-acd17ab632c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685762438 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.685762438
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2535371513
Short name T336
Test name
Test status
Simulation time 21954834 ps
CPU time 0.93 seconds
Started Aug 03 05:49:56 PM PDT 24
Finished Aug 03 05:49:57 PM PDT 24
Peak memory 215292 kb
Host smart-0b5cdaa0-c0c4-4eb1-9ca9-5ac596f2092e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535371513 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2535371513
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3468831138
Short name T911
Test name
Test status
Simulation time 2117151912 ps
CPU time 4.65 seconds
Started Aug 03 05:50:01 PM PDT 24
Finished Aug 03 05:50:05 PM PDT 24
Peak memory 217380 kb
Host smart-63c8d5d8-c38d-4c7b-91ab-3f0cf8cd21e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468831138 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3468831138
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3992620412
Short name T24
Test name
Test status
Simulation time 95498861823 ps
CPU time 960.52 seconds
Started Aug 03 05:49:59 PM PDT 24
Finished Aug 03 06:06:00 PM PDT 24
Peak memory 223640 kb
Host smart-b7aadd78-0fe0-4be8-938b-634ee52bdc36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992620412 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3992620412
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1318293683
Short name T72
Test name
Test status
Simulation time 43645589 ps
CPU time 1.22 seconds
Started Aug 03 05:50:01 PM PDT 24
Finished Aug 03 05:50:02 PM PDT 24
Peak memory 218712 kb
Host smart-81a18ae4-f5e7-4076-9c72-e1ecc1f4ec4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318293683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1318293683
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3625804163
Short name T579
Test name
Test status
Simulation time 53957243 ps
CPU time 0.92 seconds
Started Aug 03 05:50:01 PM PDT 24
Finished Aug 03 05:50:02 PM PDT 24
Peak memory 206736 kb
Host smart-9622b2a3-67a9-432b-a540-f5ee0471f884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625804163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3625804163
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3740032422
Short name T122
Test name
Test status
Simulation time 69197695 ps
CPU time 0.88 seconds
Started Aug 03 05:49:57 PM PDT 24
Finished Aug 03 05:49:58 PM PDT 24
Peak memory 216224 kb
Host smart-8cdc86af-7e2e-4922-9ff1-87677314e92c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740032422 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3740032422
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.4131263605
Short name T49
Test name
Test status
Simulation time 25842186 ps
CPU time 0.97 seconds
Started Aug 03 05:49:59 PM PDT 24
Finished Aug 03 05:50:00 PM PDT 24
Peak memory 223820 kb
Host smart-272fcd28-9774-46c5-8da9-01bbe4be6931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131263605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.4131263605
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2781182038
Short name T338
Test name
Test status
Simulation time 34393074 ps
CPU time 1.33 seconds
Started Aug 03 05:50:02 PM PDT 24
Finished Aug 03 05:50:03 PM PDT 24
Peak memory 217236 kb
Host smart-969181f0-1143-496c-a780-687d020a1e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781182038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2781182038
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_smoke.3236898694
Short name T560
Test name
Test status
Simulation time 56845756 ps
CPU time 0.96 seconds
Started Aug 03 05:49:57 PM PDT 24
Finished Aug 03 05:49:58 PM PDT 24
Peak memory 215316 kb
Host smart-083fb50d-8aef-4abe-b092-461de1db6445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236898694 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3236898694
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3205635142
Short name T359
Test name
Test status
Simulation time 417452877 ps
CPU time 4.29 seconds
Started Aug 03 05:49:57 PM PDT 24
Finished Aug 03 05:50:01 PM PDT 24
Peak memory 215372 kb
Host smart-03cb46f4-e9a4-452f-b0cd-32bbcf7c3738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205635142 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3205635142
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2457349222
Short name T229
Test name
Test status
Simulation time 156864706036 ps
CPU time 1006.1 seconds
Started Aug 03 05:50:01 PM PDT 24
Finished Aug 03 06:06:47 PM PDT 24
Peak memory 224176 kb
Host smart-fd76b769-f9f7-496d-a01e-1f874987e48d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457349222 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2457349222
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3805252197
Short name T839
Test name
Test status
Simulation time 49605532 ps
CPU time 1.28 seconds
Started Aug 03 05:50:05 PM PDT 24
Finished Aug 03 05:50:06 PM PDT 24
Peak memory 220768 kb
Host smart-9a239cdf-9307-43ae-8d46-ed883b406ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805252197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3805252197
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2055927005
Short name T489
Test name
Test status
Simulation time 20497214 ps
CPU time 0.89 seconds
Started Aug 03 05:50:07 PM PDT 24
Finished Aug 03 05:50:07 PM PDT 24
Peak memory 206684 kb
Host smart-46f18ebe-ab41-4bc4-8409-a226d0d4896b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055927005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2055927005
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2298027928
Short name T942
Test name
Test status
Simulation time 56217920 ps
CPU time 1.01 seconds
Started Aug 03 05:50:04 PM PDT 24
Finished Aug 03 05:50:05 PM PDT 24
Peak memory 219712 kb
Host smart-a85c1533-57b3-414a-a3c2-5c010707e316
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298027928 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2298027928
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3025953888
Short name T171
Test name
Test status
Simulation time 24060857 ps
CPU time 1.19 seconds
Started Aug 03 05:50:07 PM PDT 24
Finished Aug 03 05:50:08 PM PDT 24
Peak memory 219820 kb
Host smart-f58daaaa-3922-4560-929a-63580e11c319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025953888 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3025953888
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3388622956
Short name T493
Test name
Test status
Simulation time 94610546 ps
CPU time 1.48 seconds
Started Aug 03 05:50:03 PM PDT 24
Finished Aug 03 05:50:05 PM PDT 24
Peak memory 218880 kb
Host smart-718e7f91-77bc-488e-abaa-99f914c73fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388622956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3388622956
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3026135379
Short name T715
Test name
Test status
Simulation time 22502730 ps
CPU time 1.13 seconds
Started Aug 03 05:50:04 PM PDT 24
Finished Aug 03 05:50:05 PM PDT 24
Peak memory 215520 kb
Host smart-5aaf4c9e-d3e3-443d-9ea5-aa992f58518d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026135379 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3026135379
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1281780304
Short name T767
Test name
Test status
Simulation time 16258111 ps
CPU time 1.02 seconds
Started Aug 03 05:50:03 PM PDT 24
Finished Aug 03 05:50:04 PM PDT 24
Peak memory 215264 kb
Host smart-731e5501-abb8-4a6b-a751-2efb336ff096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281780304 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1281780304
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2718530300
Short name T404
Test name
Test status
Simulation time 161269280652 ps
CPU time 1120.08 seconds
Started Aug 03 05:50:06 PM PDT 24
Finished Aug 03 06:08:46 PM PDT 24
Peak memory 224408 kb
Host smart-1b6b1fb7-1bea-4d27-afe7-d9976b8b67a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718530300 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2718530300
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1492862213
Short name T864
Test name
Test status
Simulation time 35124298 ps
CPU time 1.35 seconds
Started Aug 03 05:47:14 PM PDT 24
Finished Aug 03 05:47:16 PM PDT 24
Peak memory 221016 kb
Host smart-a8f06716-dca4-421d-b98f-f74467de71c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492862213 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1492862213
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2045112872
Short name T679
Test name
Test status
Simulation time 26766240 ps
CPU time 1.09 seconds
Started Aug 03 05:47:19 PM PDT 24
Finished Aug 03 05:47:20 PM PDT 24
Peak memory 214876 kb
Host smart-350ca2cc-7451-4dc5-9649-f2d713228492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045112872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2045112872
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.859350739
Short name T97
Test name
Test status
Simulation time 19961075 ps
CPU time 0.84 seconds
Started Aug 03 05:47:16 PM PDT 24
Finished Aug 03 05:47:17 PM PDT 24
Peak memory 216212 kb
Host smart-53a0b641-1b62-43e8-a44e-87455a503762
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859350739 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.859350739
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.4030774626
Short name T127
Test name
Test status
Simulation time 318848012 ps
CPU time 1.15 seconds
Started Aug 03 05:47:17 PM PDT 24
Finished Aug 03 05:47:18 PM PDT 24
Peak memory 216872 kb
Host smart-cded8074-5d1f-4e35-a099-cc0b2da8ff32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030774626 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.4030774626
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2811435484
Short name T47
Test name
Test status
Simulation time 34529954 ps
CPU time 1.44 seconds
Started Aug 03 05:47:09 PM PDT 24
Finished Aug 03 05:47:11 PM PDT 24
Peak memory 225628 kb
Host smart-a5961ba9-7633-4dc7-b484-6877e2f18e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811435484 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2811435484
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1118860642
Short name T506
Test name
Test status
Simulation time 38056593 ps
CPU time 1.58 seconds
Started Aug 03 05:47:11 PM PDT 24
Finished Aug 03 05:47:12 PM PDT 24
Peak memory 217460 kb
Host smart-87ebaff5-8c4e-45c7-a41c-fd886f51505f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118860642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1118860642
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1316488677
Short name T373
Test name
Test status
Simulation time 32264683 ps
CPU time 0.87 seconds
Started Aug 03 05:47:10 PM PDT 24
Finished Aug 03 05:47:11 PM PDT 24
Peak memory 215156 kb
Host smart-f394e9ef-7d82-4fda-8dd7-e8f40ba483c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316488677 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1316488677
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1269664269
Short name T448
Test name
Test status
Simulation time 24803508 ps
CPU time 0.94 seconds
Started Aug 03 05:47:12 PM PDT 24
Finished Aug 03 05:47:13 PM PDT 24
Peak memory 207060 kb
Host smart-2b536756-5da6-462b-9572-794bbc4c20b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269664269 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1269664269
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.3024930129
Short name T822
Test name
Test status
Simulation time 41664219 ps
CPU time 0.91 seconds
Started Aug 03 05:47:11 PM PDT 24
Finished Aug 03 05:47:12 PM PDT 24
Peak memory 215320 kb
Host smart-0c681d99-9016-40e2-9e5c-cd82651612e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024930129 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3024930129
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1114891549
Short name T418
Test name
Test status
Simulation time 140545653 ps
CPU time 1.97 seconds
Started Aug 03 05:47:15 PM PDT 24
Finished Aug 03 05:47:18 PM PDT 24
Peak memory 215368 kb
Host smart-c9509396-b1d9-4efd-9d67-803aab9676ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114891549 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1114891549
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1853270224
Short name T236
Test name
Test status
Simulation time 111781841907 ps
CPU time 1188.45 seconds
Started Aug 03 05:47:15 PM PDT 24
Finished Aug 03 06:07:04 PM PDT 24
Peak memory 223616 kb
Host smart-5e16172b-0888-43aa-b393-17a6e2e95496
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853270224 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1853270224
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3185876785
Short name T297
Test name
Test status
Simulation time 108648048 ps
CPU time 1.16 seconds
Started Aug 03 05:50:07 PM PDT 24
Finished Aug 03 05:50:08 PM PDT 24
Peak memory 219732 kb
Host smart-0d4f314c-d424-4ec7-8f82-259b446acdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185876785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3185876785
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1130992594
Short name T672
Test name
Test status
Simulation time 42364773 ps
CPU time 0.84 seconds
Started Aug 03 05:50:10 PM PDT 24
Finished Aug 03 05:50:11 PM PDT 24
Peak memory 206512 kb
Host smart-c1f09d8b-f64f-40ef-882c-4be8b7dc4348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130992594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1130992594
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3165564004
Short name T106
Test name
Test status
Simulation time 20357760 ps
CPU time 0.88 seconds
Started Aug 03 05:50:16 PM PDT 24
Finished Aug 03 05:50:17 PM PDT 24
Peak memory 216324 kb
Host smart-3c3e11b7-57f1-49e1-bb37-03b1c1766328
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165564004 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3165564004
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1218369410
Short name T461
Test name
Test status
Simulation time 84672546 ps
CPU time 0.9 seconds
Started Aug 03 05:50:08 PM PDT 24
Finished Aug 03 05:50:09 PM PDT 24
Peak memory 216932 kb
Host smart-536d1d66-f218-4d28-b9cc-f1069e55be60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218369410 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1218369410
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3265118928
Short name T130
Test name
Test status
Simulation time 23237880 ps
CPU time 0.91 seconds
Started Aug 03 05:50:06 PM PDT 24
Finished Aug 03 05:50:07 PM PDT 24
Peak memory 218676 kb
Host smart-41ab015c-1e93-4f09-93a7-c6aad4b46221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265118928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3265118928
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.651771664
Short name T64
Test name
Test status
Simulation time 38663695 ps
CPU time 1.38 seconds
Started Aug 03 05:50:05 PM PDT 24
Finished Aug 03 05:50:06 PM PDT 24
Peak memory 218460 kb
Host smart-62e59b47-64d2-4bb2-9cf8-1dd07a823012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651771664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.651771664
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1520437775
Short name T853
Test name
Test status
Simulation time 22432648 ps
CPU time 1.12 seconds
Started Aug 03 05:50:05 PM PDT 24
Finished Aug 03 05:50:06 PM PDT 24
Peak memory 215336 kb
Host smart-9b006d87-d763-46f1-a426-2c67ffeba451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520437775 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1520437775
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1509553168
Short name T719
Test name
Test status
Simulation time 24263563 ps
CPU time 0.97 seconds
Started Aug 03 05:50:07 PM PDT 24
Finished Aug 03 05:50:08 PM PDT 24
Peak memory 215312 kb
Host smart-f2f54b93-a325-4abc-aef7-82b28e2b515c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509553168 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1509553168
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2385147517
Short name T575
Test name
Test status
Simulation time 89136227 ps
CPU time 2.11 seconds
Started Aug 03 05:50:05 PM PDT 24
Finished Aug 03 05:50:07 PM PDT 24
Peak memory 218532 kb
Host smart-8dd5feb9-e7ea-4c1f-bcc4-e93331fe7751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385147517 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2385147517
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.231881010
Short name T725
Test name
Test status
Simulation time 649208509617 ps
CPU time 2136.44 seconds
Started Aug 03 05:50:05 PM PDT 24
Finished Aug 03 06:25:42 PM PDT 24
Peak memory 227308 kb
Host smart-e723d45a-5e17-4ad1-9b86-852dbd4dd7cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231881010 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.231881010
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1918551161
Short name T212
Test name
Test status
Simulation time 34837137 ps
CPU time 1.1 seconds
Started Aug 03 05:50:15 PM PDT 24
Finished Aug 03 05:50:16 PM PDT 24
Peak memory 219036 kb
Host smart-0f9b8bd0-5705-4f95-81fc-3554fe565bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918551161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1918551161
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2930007671
Short name T541
Test name
Test status
Simulation time 29120760 ps
CPU time 0.94 seconds
Started Aug 03 05:50:13 PM PDT 24
Finished Aug 03 05:50:14 PM PDT 24
Peak memory 214904 kb
Host smart-320438cb-d038-417b-850c-3d3fe792ea79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930007671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2930007671
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.665708538
Short name T191
Test name
Test status
Simulation time 41301815 ps
CPU time 0.88 seconds
Started Aug 03 05:50:12 PM PDT 24
Finished Aug 03 05:50:13 PM PDT 24
Peak memory 216164 kb
Host smart-50d17568-672f-4cd3-a539-acdf453438da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665708538 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.665708538
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.688224195
Short name T811
Test name
Test status
Simulation time 97463915 ps
CPU time 1.13 seconds
Started Aug 03 05:50:10 PM PDT 24
Finished Aug 03 05:50:11 PM PDT 24
Peak memory 216752 kb
Host smart-b65a87be-0ea8-4a2a-a2f0-a99990734d30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688224195 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.688224195
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3511575301
Short name T963
Test name
Test status
Simulation time 72474651 ps
CPU time 0.85 seconds
Started Aug 03 05:50:17 PM PDT 24
Finished Aug 03 05:50:18 PM PDT 24
Peak memory 218408 kb
Host smart-a8fa8338-7be6-4fa5-a0ce-70c2d7226104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511575301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3511575301
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.826052113
Short name T868
Test name
Test status
Simulation time 84914690 ps
CPU time 1.45 seconds
Started Aug 03 05:50:10 PM PDT 24
Finished Aug 03 05:50:11 PM PDT 24
Peak memory 218784 kb
Host smart-d7f9e970-8ca7-4ee2-ae68-cb133b056226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826052113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.826052113
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3515240299
Short name T740
Test name
Test status
Simulation time 23443737 ps
CPU time 1.07 seconds
Started Aug 03 05:50:16 PM PDT 24
Finished Aug 03 05:50:17 PM PDT 24
Peak memory 215544 kb
Host smart-f80d80c1-e808-46e0-b80a-c1c4134d81a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515240299 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3515240299
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2448344376
Short name T21
Test name
Test status
Simulation time 43402539 ps
CPU time 0.92 seconds
Started Aug 03 05:50:15 PM PDT 24
Finished Aug 03 05:50:16 PM PDT 24
Peak memory 215312 kb
Host smart-a3cab04d-7d41-4a95-8497-2849f6c7e6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448344376 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2448344376
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3197697370
Short name T247
Test name
Test status
Simulation time 222513339 ps
CPU time 2.71 seconds
Started Aug 03 05:50:12 PM PDT 24
Finished Aug 03 05:50:15 PM PDT 24
Peak memory 216756 kb
Host smart-7d52299e-c32c-4dde-86ad-b8b586ab30d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197697370 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3197697370
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1168096054
Short name T451
Test name
Test status
Simulation time 223173847740 ps
CPU time 821.92 seconds
Started Aug 03 05:50:20 PM PDT 24
Finished Aug 03 06:04:03 PM PDT 24
Peak memory 223660 kb
Host smart-fdf7f460-aad1-4860-af99-30b2e5f23c34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168096054 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1168096054
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.564700559
Short name T609
Test name
Test status
Simulation time 237068947 ps
CPU time 1.09 seconds
Started Aug 03 05:50:15 PM PDT 24
Finished Aug 03 05:50:16 PM PDT 24
Peak memory 219808 kb
Host smart-1dd20d56-650b-433b-bbe8-ac79f8359278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564700559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.564700559
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2964084882
Short name T935
Test name
Test status
Simulation time 22862129 ps
CPU time 0.85 seconds
Started Aug 03 05:50:14 PM PDT 24
Finished Aug 03 05:50:15 PM PDT 24
Peak memory 206512 kb
Host smart-1161c07d-746e-4ab2-98be-b003353993b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964084882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2964084882
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1346367645
Short name T110
Test name
Test status
Simulation time 17605483 ps
CPU time 0.88 seconds
Started Aug 03 05:50:14 PM PDT 24
Finished Aug 03 05:50:15 PM PDT 24
Peak memory 216492 kb
Host smart-e9208685-6391-48ed-b123-48a94805a726
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346367645 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1346367645
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3816487136
Short name T383
Test name
Test status
Simulation time 42181327 ps
CPU time 1.09 seconds
Started Aug 03 05:50:14 PM PDT 24
Finished Aug 03 05:50:16 PM PDT 24
Peak memory 216836 kb
Host smart-bac521ab-5649-445d-b49b-dfe4fafd516a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816487136 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3816487136
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_genbits.103010104
Short name T37
Test name
Test status
Simulation time 52797508 ps
CPU time 1.67 seconds
Started Aug 03 05:50:17 PM PDT 24
Finished Aug 03 05:50:19 PM PDT 24
Peak memory 218452 kb
Host smart-fee4c6e7-207d-43b5-bb18-a82190459680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103010104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.103010104
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1416962485
Short name T657
Test name
Test status
Simulation time 21037219 ps
CPU time 1.06 seconds
Started Aug 03 05:50:14 PM PDT 24
Finished Aug 03 05:50:16 PM PDT 24
Peak memory 215312 kb
Host smart-9bf4c221-688f-45e9-9d65-2858416287bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416962485 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1416962485
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.868308386
Short name T387
Test name
Test status
Simulation time 23603697 ps
CPU time 0.96 seconds
Started Aug 03 05:50:11 PM PDT 24
Finished Aug 03 05:50:12 PM PDT 24
Peak memory 215284 kb
Host smart-fa9a5fdf-d66d-4f79-9eef-e9214ea044b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868308386 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.868308386
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2774843074
Short name T563
Test name
Test status
Simulation time 232572917 ps
CPU time 3.13 seconds
Started Aug 03 05:50:15 PM PDT 24
Finished Aug 03 05:50:18 PM PDT 24
Peak memory 218492 kb
Host smart-fd1bdff6-3a7f-47c2-8465-bf3f44c8ef8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774843074 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2774843074
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3127850606
Short name T891
Test name
Test status
Simulation time 1323062783942 ps
CPU time 2377.19 seconds
Started Aug 03 05:50:13 PM PDT 24
Finished Aug 03 06:29:51 PM PDT 24
Peak memory 231420 kb
Host smart-b63ffbeb-803f-4623-a2fb-a9f7e53b160c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127850606 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3127850606
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2934893933
Short name T743
Test name
Test status
Simulation time 37390009 ps
CPU time 1.28 seconds
Started Aug 03 05:50:22 PM PDT 24
Finished Aug 03 05:50:23 PM PDT 24
Peak memory 215596 kb
Host smart-8a5f8a60-959a-4f92-9944-d1cb7167b950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934893933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2934893933
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3246528011
Short name T536
Test name
Test status
Simulation time 121300622 ps
CPU time 0.97 seconds
Started Aug 03 05:50:19 PM PDT 24
Finished Aug 03 05:50:20 PM PDT 24
Peak memory 214880 kb
Host smart-8ffbd482-3774-4b68-927f-c1806a80aa19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246528011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3246528011
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3474791003
Short name T25
Test name
Test status
Simulation time 26221994 ps
CPU time 0.87 seconds
Started Aug 03 05:50:20 PM PDT 24
Finished Aug 03 05:50:21 PM PDT 24
Peak memory 215324 kb
Host smart-705daa4f-58a5-4e5b-a136-1e416c0e0e95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474791003 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3474791003
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2979011758
Short name T155
Test name
Test status
Simulation time 36026296 ps
CPU time 1.22 seconds
Started Aug 03 05:50:23 PM PDT 24
Finished Aug 03 05:50:24 PM PDT 24
Peak memory 216292 kb
Host smart-a292fead-7f7b-48e5-bfd0-31787c8f5713
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979011758 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2979011758
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3839134563
Short name T190
Test name
Test status
Simulation time 19103920 ps
CPU time 1.02 seconds
Started Aug 03 05:50:20 PM PDT 24
Finished Aug 03 05:50:21 PM PDT 24
Peak memory 218520 kb
Host smart-c470dc50-d611-4f3a-8e1d-75f7fab92b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839134563 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3839134563
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.588996246
Short name T375
Test name
Test status
Simulation time 43351434 ps
CPU time 1.19 seconds
Started Aug 03 05:50:20 PM PDT 24
Finished Aug 03 05:50:21 PM PDT 24
Peak memory 218636 kb
Host smart-cfd970ab-d555-498e-8436-64ffd08a1553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588996246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.588996246
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2315216372
Short name T866
Test name
Test status
Simulation time 23229859 ps
CPU time 1.1 seconds
Started Aug 03 05:50:20 PM PDT 24
Finished Aug 03 05:50:21 PM PDT 24
Peak memory 215356 kb
Host smart-16865a3c-c136-454d-88c5-354d6997d026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315216372 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2315216372
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.260604458
Short name T572
Test name
Test status
Simulation time 16549918 ps
CPU time 0.98 seconds
Started Aug 03 05:50:14 PM PDT 24
Finished Aug 03 05:50:15 PM PDT 24
Peak memory 215232 kb
Host smart-0c388d8f-3832-4df3-9921-e346457e173d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260604458 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.260604458
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.755786374
Short name T335
Test name
Test status
Simulation time 50967889 ps
CPU time 1.59 seconds
Started Aug 03 05:50:20 PM PDT 24
Finished Aug 03 05:50:22 PM PDT 24
Peak memory 218512 kb
Host smart-54942577-8dd7-46ec-9680-9e6c539e666b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755786374 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.755786374
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1386098405
Short name T235
Test name
Test status
Simulation time 48945221298 ps
CPU time 473.15 seconds
Started Aug 03 05:50:20 PM PDT 24
Finished Aug 03 05:58:13 PM PDT 24
Peak memory 217284 kb
Host smart-627ee13e-cd26-4d1e-84fc-65b041960795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386098405 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1386098405
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.592889550
Short name T886
Test name
Test status
Simulation time 27483084 ps
CPU time 1.21 seconds
Started Aug 03 05:50:40 PM PDT 24
Finished Aug 03 05:50:42 PM PDT 24
Peak memory 219592 kb
Host smart-12dbd646-d3d9-4507-959a-e2ce981232cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592889550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.592889550
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3793556147
Short name T238
Test name
Test status
Simulation time 36950685 ps
CPU time 0.88 seconds
Started Aug 03 05:50:26 PM PDT 24
Finished Aug 03 05:50:27 PM PDT 24
Peak memory 215084 kb
Host smart-eded02e4-a707-4e03-ab4d-a6e0251e5633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793556147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3793556147
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2982042283
Short name T747
Test name
Test status
Simulation time 13483116 ps
CPU time 0.85 seconds
Started Aug 03 05:50:27 PM PDT 24
Finished Aug 03 05:50:28 PM PDT 24
Peak memory 216212 kb
Host smart-e371bbdf-e37d-4866-b320-025b8fba2cf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982042283 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2982042283
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1680359028
Short name T570
Test name
Test status
Simulation time 40845716 ps
CPU time 1.29 seconds
Started Aug 03 05:50:27 PM PDT 24
Finished Aug 03 05:50:29 PM PDT 24
Peak memory 218712 kb
Host smart-683c6b7b-3251-4f54-80df-30ed89e9c82a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680359028 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1680359028
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.4062365240
Short name T195
Test name
Test status
Simulation time 162663434 ps
CPU time 1.02 seconds
Started Aug 03 05:50:41 PM PDT 24
Finished Aug 03 05:50:42 PM PDT 24
Peak memory 219616 kb
Host smart-5d8689bb-7c2e-44bd-88eb-08d2dfcd0fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062365240 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.4062365240
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1840156608
Short name T518
Test name
Test status
Simulation time 41360764 ps
CPU time 1.46 seconds
Started Aug 03 05:50:21 PM PDT 24
Finished Aug 03 05:50:23 PM PDT 24
Peak memory 217380 kb
Host smart-3a14c18b-e941-4fef-bc24-85d2323087b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840156608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1840156608
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.712626306
Short name T562
Test name
Test status
Simulation time 23183272 ps
CPU time 1.09 seconds
Started Aug 03 05:50:26 PM PDT 24
Finished Aug 03 05:50:27 PM PDT 24
Peak memory 215268 kb
Host smart-25e5ecfa-2da3-49c2-b6fa-0dbffcb49e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712626306 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.712626306
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3748541562
Short name T395
Test name
Test status
Simulation time 67192420 ps
CPU time 0.9 seconds
Started Aug 03 05:50:21 PM PDT 24
Finished Aug 03 05:50:22 PM PDT 24
Peak memory 215232 kb
Host smart-8fb7c62c-6b67-49be-8082-c1d03f0fc41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748541562 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3748541562
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.469663756
Short name T858
Test name
Test status
Simulation time 368173501 ps
CPU time 2.11 seconds
Started Aug 03 05:50:22 PM PDT 24
Finished Aug 03 05:50:24 PM PDT 24
Peak memory 219312 kb
Host smart-099a98c9-64ab-48d4-b1b8-473414b45c14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469663756 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.469663756
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1138583319
Short name T878
Test name
Test status
Simulation time 36552007418 ps
CPU time 938.68 seconds
Started Aug 03 05:50:27 PM PDT 24
Finished Aug 03 06:06:06 PM PDT 24
Peak memory 218768 kb
Host smart-8881983c-e5d6-45de-b931-03211b4fdb2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138583319 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1138583319
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3231750630
Short name T847
Test name
Test status
Simulation time 37359303 ps
CPU time 1.04 seconds
Started Aug 03 05:50:26 PM PDT 24
Finished Aug 03 05:50:27 PM PDT 24
Peak memory 218812 kb
Host smart-db50e614-73e1-4ce7-aa0a-1f7225a2eac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231750630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3231750630
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3683963833
Short name T346
Test name
Test status
Simulation time 35186728 ps
CPU time 0.93 seconds
Started Aug 03 05:50:40 PM PDT 24
Finished Aug 03 05:50:41 PM PDT 24
Peak memory 206684 kb
Host smart-bb2bd15c-8c07-45fb-9160-352265b0aefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683963833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3683963833
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2879040080
Short name T220
Test name
Test status
Simulation time 17362423 ps
CPU time 0.81 seconds
Started Aug 03 05:50:25 PM PDT 24
Finished Aug 03 05:50:26 PM PDT 24
Peak memory 215268 kb
Host smart-26b5f954-a7bf-4c0e-8146-ac74a3cfa117
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879040080 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2879040080
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1699719963
Short name T40
Test name
Test status
Simulation time 37283346 ps
CPU time 1.1 seconds
Started Aug 03 05:50:27 PM PDT 24
Finished Aug 03 05:50:28 PM PDT 24
Peak memory 216840 kb
Host smart-e2a94020-3a1e-4999-89f5-480a95e425f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699719963 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1699719963
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3628232782
Short name T777
Test name
Test status
Simulation time 28086419 ps
CPU time 0.94 seconds
Started Aug 03 05:50:25 PM PDT 24
Finished Aug 03 05:50:26 PM PDT 24
Peak memory 218540 kb
Host smart-65025364-d0fa-4717-aca2-5b98271b4516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628232782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3628232782
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2442269978
Short name T673
Test name
Test status
Simulation time 425434807 ps
CPU time 2.51 seconds
Started Aug 03 05:50:26 PM PDT 24
Finished Aug 03 05:50:28 PM PDT 24
Peak memory 219788 kb
Host smart-04cc69fb-3e0c-49a1-b886-bafe540ed768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442269978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2442269978
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1200894798
Short name T89
Test name
Test status
Simulation time 21776028 ps
CPU time 1.07 seconds
Started Aug 03 05:50:27 PM PDT 24
Finished Aug 03 05:50:28 PM PDT 24
Peak memory 216060 kb
Host smart-741f1286-098b-41c9-8c08-f84901843050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200894798 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1200894798
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1751670919
Short name T491
Test name
Test status
Simulation time 29113554 ps
CPU time 0.92 seconds
Started Aug 03 05:50:25 PM PDT 24
Finished Aug 03 05:50:26 PM PDT 24
Peak memory 215160 kb
Host smart-db016fb4-d96c-412d-b5f3-47d34c50b1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751670919 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1751670919
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1153844784
Short name T522
Test name
Test status
Simulation time 44559704 ps
CPU time 1.37 seconds
Started Aug 03 05:50:40 PM PDT 24
Finished Aug 03 05:50:41 PM PDT 24
Peak memory 207064 kb
Host smart-1dec8272-88b4-4396-9b80-71ab417bbb1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153844784 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1153844784
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1056135487
Short name T237
Test name
Test status
Simulation time 37484484514 ps
CPU time 470.9 seconds
Started Aug 03 05:50:40 PM PDT 24
Finished Aug 03 05:58:31 PM PDT 24
Peak memory 217872 kb
Host smart-47daa072-2af9-4506-b2d6-ec4877e684cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056135487 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1056135487
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1804147090
Short name T685
Test name
Test status
Simulation time 26047693 ps
CPU time 1.3 seconds
Started Aug 03 05:50:34 PM PDT 24
Finished Aug 03 05:50:35 PM PDT 24
Peak memory 220500 kb
Host smart-e218172a-8cf8-4b42-a98c-15d63f2a5b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804147090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1804147090
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.792264060
Short name T53
Test name
Test status
Simulation time 15218010 ps
CPU time 0.93 seconds
Started Aug 03 05:50:34 PM PDT 24
Finished Aug 03 05:50:36 PM PDT 24
Peak memory 214816 kb
Host smart-a0dbf3d5-d010-45b7-97bb-47605893e5b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792264060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.792264060
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.4001939859
Short name T104
Test name
Test status
Simulation time 40987859 ps
CPU time 0.88 seconds
Started Aug 03 05:50:32 PM PDT 24
Finished Aug 03 05:50:33 PM PDT 24
Peak memory 216292 kb
Host smart-a50a6bfc-6101-4f08-8e4d-7fd2e49ff17d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001939859 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.4001939859
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2821913000
Short name T736
Test name
Test status
Simulation time 28002093 ps
CPU time 1.1 seconds
Started Aug 03 05:50:33 PM PDT 24
Finished Aug 03 05:50:34 PM PDT 24
Peak memory 216880 kb
Host smart-bda35919-a21b-4eb2-9a9c-5226326e6a7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821913000 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2821913000
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.901139187
Short name T614
Test name
Test status
Simulation time 32241421 ps
CPU time 0.82 seconds
Started Aug 03 05:50:31 PM PDT 24
Finished Aug 03 05:50:32 PM PDT 24
Peak memory 218180 kb
Host smart-e3b31872-6340-41a8-ae60-9a0b844b019d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901139187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.901139187
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1874834413
Short name T311
Test name
Test status
Simulation time 43434195 ps
CPU time 1.63 seconds
Started Aug 03 05:50:41 PM PDT 24
Finished Aug 03 05:50:43 PM PDT 24
Peak memory 218516 kb
Host smart-c3cd2763-b0b3-4a96-a106-2a9a0d689446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874834413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1874834413
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1262419036
Short name T131
Test name
Test status
Simulation time 24065785 ps
CPU time 1.01 seconds
Started Aug 03 05:50:41 PM PDT 24
Finished Aug 03 05:50:42 PM PDT 24
Peak memory 215900 kb
Host smart-5a614483-8f99-4d50-8bad-ddc42c47b04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262419036 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1262419036
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2800092079
Short name T397
Test name
Test status
Simulation time 34937097 ps
CPU time 0.97 seconds
Started Aug 03 05:50:40 PM PDT 24
Finished Aug 03 05:50:41 PM PDT 24
Peak memory 215236 kb
Host smart-a32090aa-eecb-4a1c-affd-ab5a8d85794b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800092079 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2800092079
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2905577769
Short name T972
Test name
Test status
Simulation time 667503440 ps
CPU time 6.06 seconds
Started Aug 03 05:50:40 PM PDT 24
Finished Aug 03 05:50:46 PM PDT 24
Peak memory 217160 kb
Host smart-116d6b71-140f-4c50-a2fa-19067e4b129e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905577769 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2905577769
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2182876183
Short name T649
Test name
Test status
Simulation time 19898286569 ps
CPU time 505.98 seconds
Started Aug 03 05:50:39 PM PDT 24
Finished Aug 03 05:59:05 PM PDT 24
Peak memory 219044 kb
Host smart-c315e30c-247d-4b9c-b2e1-63ce6a8a7941
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182876183 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2182876183
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.4145030399
Short name T69
Test name
Test status
Simulation time 73538410 ps
CPU time 1.12 seconds
Started Aug 03 05:50:32 PM PDT 24
Finished Aug 03 05:50:34 PM PDT 24
Peak memory 219184 kb
Host smart-4a24689e-2caa-48bf-868c-9f46e9895944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145030399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.4145030399
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.4020639167
Short name T409
Test name
Test status
Simulation time 24097029 ps
CPU time 0.87 seconds
Started Aug 03 05:50:31 PM PDT 24
Finished Aug 03 05:50:32 PM PDT 24
Peak memory 206632 kb
Host smart-2eab9c66-6ea1-49b0-ad53-5341e1131eae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020639167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.4020639167
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.265962999
Short name T405
Test name
Test status
Simulation time 29991718 ps
CPU time 0.84 seconds
Started Aug 03 05:50:31 PM PDT 24
Finished Aug 03 05:50:32 PM PDT 24
Peak memory 216192 kb
Host smart-c8ccadb7-cbd6-4307-8ee8-2bfa9f8be9ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265962999 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.265962999
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1153383997
Short name T113
Test name
Test status
Simulation time 65092711 ps
CPU time 1.24 seconds
Started Aug 03 05:50:33 PM PDT 24
Finished Aug 03 05:50:34 PM PDT 24
Peak memory 216896 kb
Host smart-29352b2c-a367-4bfa-aa98-46cebddada51
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153383997 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1153383997
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2277457613
Short name T548
Test name
Test status
Simulation time 51404306 ps
CPU time 0.89 seconds
Started Aug 03 05:50:31 PM PDT 24
Finished Aug 03 05:50:32 PM PDT 24
Peak memory 218492 kb
Host smart-4f2b156b-8829-4601-8af3-78809f654334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277457613 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2277457613
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1582203739
Short name T636
Test name
Test status
Simulation time 80710918 ps
CPU time 2.78 seconds
Started Aug 03 05:50:31 PM PDT 24
Finished Aug 03 05:50:34 PM PDT 24
Peak memory 218580 kb
Host smart-acc93486-428e-446f-884a-6e0201ca718e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582203739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1582203739
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.4005446877
Short name T941
Test name
Test status
Simulation time 21937503 ps
CPU time 1.29 seconds
Started Aug 03 05:50:31 PM PDT 24
Finished Aug 03 05:50:33 PM PDT 24
Peak memory 224016 kb
Host smart-3dc5a7f6-ef37-493a-bc74-8779f3359526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005446877 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.4005446877
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.370914263
Short name T717
Test name
Test status
Simulation time 16397290 ps
CPU time 1.02 seconds
Started Aug 03 05:50:35 PM PDT 24
Finished Aug 03 05:50:36 PM PDT 24
Peak memory 215304 kb
Host smart-b1cc88c8-532a-4e00-b8f0-83349f1fd671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370914263 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.370914263
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2616305971
Short name T517
Test name
Test status
Simulation time 1039576461 ps
CPU time 2.8 seconds
Started Aug 03 05:50:32 PM PDT 24
Finished Aug 03 05:50:35 PM PDT 24
Peak memory 215296 kb
Host smart-ef6e1c68-38e6-454e-9586-c1c1b1ee6709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616305971 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2616305971
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1506115800
Short name T231
Test name
Test status
Simulation time 70127305470 ps
CPU time 802.92 seconds
Started Aug 03 05:50:34 PM PDT 24
Finished Aug 03 06:03:57 PM PDT 24
Peak memory 223584 kb
Host smart-a7fbfda6-3b3c-478e-9f54-2a399779529f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506115800 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1506115800
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.822421908
Short name T951
Test name
Test status
Simulation time 22304983 ps
CPU time 1.19 seconds
Started Aug 03 05:50:38 PM PDT 24
Finished Aug 03 05:50:39 PM PDT 24
Peak memory 218312 kb
Host smart-0a323eaf-ed5d-4436-b735-9f2ae9c8f69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822421908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.822421908
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.713286599
Short name T901
Test name
Test status
Simulation time 93672079 ps
CPU time 0.84 seconds
Started Aug 03 05:50:37 PM PDT 24
Finished Aug 03 05:50:38 PM PDT 24
Peak memory 206548 kb
Host smart-d326828e-2ef4-4066-b1ec-fcc63d000214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713286599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.713286599
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.126864870
Short name T200
Test name
Test status
Simulation time 17582545 ps
CPU time 0.83 seconds
Started Aug 03 05:50:39 PM PDT 24
Finished Aug 03 05:50:40 PM PDT 24
Peak memory 216204 kb
Host smart-9e25bd95-c576-42a5-9277-d5753c8a5be5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126864870 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.126864870
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2266163217
Short name T623
Test name
Test status
Simulation time 91663579 ps
CPU time 1.19 seconds
Started Aug 03 05:50:41 PM PDT 24
Finished Aug 03 05:50:42 PM PDT 24
Peak memory 216884 kb
Host smart-9e7831b9-3fa1-40ac-bf87-917dde34ae6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266163217 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2266163217
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3542943103
Short name T352
Test name
Test status
Simulation time 23531124 ps
CPU time 0.96 seconds
Started Aug 03 05:50:37 PM PDT 24
Finished Aug 03 05:50:38 PM PDT 24
Peak memory 218380 kb
Host smart-0f93be10-482b-4a7c-8b53-90cf11467ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542943103 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3542943103
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3246941856
Short name T358
Test name
Test status
Simulation time 86813985 ps
CPU time 1.21 seconds
Started Aug 03 05:50:32 PM PDT 24
Finished Aug 03 05:50:34 PM PDT 24
Peak memory 217448 kb
Host smart-d6cb0706-9aa0-45a8-805f-5208bb245b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246941856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3246941856
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3749408627
Short name T5
Test name
Test status
Simulation time 20921652 ps
CPU time 1.07 seconds
Started Aug 03 05:50:32 PM PDT 24
Finished Aug 03 05:50:33 PM PDT 24
Peak memory 215892 kb
Host smart-b48cc627-ef59-4cb4-a5d1-208d4298fab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749408627 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3749408627
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1457614064
Short name T382
Test name
Test status
Simulation time 23794137 ps
CPU time 1.07 seconds
Started Aug 03 05:50:32 PM PDT 24
Finished Aug 03 05:50:34 PM PDT 24
Peak memory 215312 kb
Host smart-bcb218fb-2331-4912-a25e-36b475018e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457614064 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1457614064
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2345332043
Short name T823
Test name
Test status
Simulation time 176257787 ps
CPU time 2.65 seconds
Started Aug 03 05:50:32 PM PDT 24
Finished Aug 03 05:50:35 PM PDT 24
Peak memory 217320 kb
Host smart-3d3f01cb-3419-461f-8f69-f0092145320a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345332043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2345332043
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1606408001
Short name T896
Test name
Test status
Simulation time 39414834493 ps
CPU time 1012.39 seconds
Started Aug 03 05:50:31 PM PDT 24
Finished Aug 03 06:07:24 PM PDT 24
Peak memory 223816 kb
Host smart-9f71d119-9dc1-4b25-bcad-38ae79679b44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606408001 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1606408001
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2563886932
Short name T249
Test name
Test status
Simulation time 47553519 ps
CPU time 1.11 seconds
Started Aug 03 05:50:36 PM PDT 24
Finished Aug 03 05:50:37 PM PDT 24
Peak memory 218376 kb
Host smart-4acf7ac7-a67c-4fb6-93ad-3eb2d02f9504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563886932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2563886932
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2069060754
Short name T776
Test name
Test status
Simulation time 50574838 ps
CPU time 0.94 seconds
Started Aug 03 05:50:39 PM PDT 24
Finished Aug 03 05:50:40 PM PDT 24
Peak memory 206720 kb
Host smart-202ad4b6-4f51-4e9f-b635-fbe974ce2902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069060754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2069060754
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.108584947
Short name T32
Test name
Test status
Simulation time 18110687 ps
CPU time 0.84 seconds
Started Aug 03 05:50:39 PM PDT 24
Finished Aug 03 05:50:40 PM PDT 24
Peak memory 215396 kb
Host smart-47f56e22-3969-4514-b4bd-f0bb26e27713
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108584947 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.108584947
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.906068829
Short name T786
Test name
Test status
Simulation time 49393009 ps
CPU time 1.15 seconds
Started Aug 03 05:50:37 PM PDT 24
Finished Aug 03 05:50:38 PM PDT 24
Peak memory 216908 kb
Host smart-44eff99c-04ea-4519-9c76-d6a39404085d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906068829 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.906068829
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_genbits.2391578136
Short name T851
Test name
Test status
Simulation time 220165269 ps
CPU time 1.27 seconds
Started Aug 03 05:50:40 PM PDT 24
Finished Aug 03 05:50:41 PM PDT 24
Peak memory 217444 kb
Host smart-31824e03-b908-4ca3-ac8f-b79362370c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391578136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2391578136
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3418523680
Short name T476
Test name
Test status
Simulation time 22505253 ps
CPU time 1.1 seconds
Started Aug 03 05:50:40 PM PDT 24
Finished Aug 03 05:50:42 PM PDT 24
Peak memory 215364 kb
Host smart-3a4ca4d7-5096-4a86-9824-d1b285c13da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418523680 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3418523680
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.650150985
Short name T910
Test name
Test status
Simulation time 44846127 ps
CPU time 0.89 seconds
Started Aug 03 05:50:39 PM PDT 24
Finished Aug 03 05:50:40 PM PDT 24
Peak memory 215252 kb
Host smart-696a990c-f195-4440-a4a6-cb06a131dd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650150985 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.650150985
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3614862977
Short name T246
Test name
Test status
Simulation time 67412495 ps
CPU time 1.51 seconds
Started Aug 03 05:50:40 PM PDT 24
Finished Aug 03 05:50:42 PM PDT 24
Peak memory 215228 kb
Host smart-83498ee5-76f3-4298-804f-9c4683b98a1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614862977 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3614862977
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.973332774
Short name T676
Test name
Test status
Simulation time 14677620997 ps
CPU time 260.87 seconds
Started Aug 03 05:50:40 PM PDT 24
Finished Aug 03 05:55:01 PM PDT 24
Peak memory 222788 kb
Host smart-405ab082-0345-451a-b37b-0aeee4b635ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973332774 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.973332774
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3087451449
Short name T632
Test name
Test status
Simulation time 27182227 ps
CPU time 1.22 seconds
Started Aug 03 05:47:22 PM PDT 24
Finished Aug 03 05:47:24 PM PDT 24
Peak memory 219688 kb
Host smart-af0afbad-243e-4a50-b651-10093596fb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087451449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3087451449
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.4285704005
Short name T239
Test name
Test status
Simulation time 19794856 ps
CPU time 0.99 seconds
Started Aug 03 05:47:28 PM PDT 24
Finished Aug 03 05:47:29 PM PDT 24
Peak memory 206872 kb
Host smart-112282cd-3829-4754-8536-988bcb234a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285704005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.4285704005
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.95127460
Short name T865
Test name
Test status
Simulation time 93760494 ps
CPU time 0.89 seconds
Started Aug 03 05:47:23 PM PDT 24
Finished Aug 03 05:47:24 PM PDT 24
Peak memory 215396 kb
Host smart-962c056c-3a57-4283-b875-acb9054b783b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95127460 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.95127460
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2680079404
Short name T588
Test name
Test status
Simulation time 76995536 ps
CPU time 1.07 seconds
Started Aug 03 05:47:21 PM PDT 24
Finished Aug 03 05:47:22 PM PDT 24
Peak memory 216852 kb
Host smart-3f529a3d-c533-4270-82c6-7a80596a3a18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680079404 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2680079404
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2768756099
Short name T794
Test name
Test status
Simulation time 45706571 ps
CPU time 0.83 seconds
Started Aug 03 05:47:22 PM PDT 24
Finished Aug 03 05:47:23 PM PDT 24
Peak memory 215172 kb
Host smart-44b2190a-bd72-4711-a57d-6a7a184e4a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768756099 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2768756099
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1789188853
Short name T334
Test name
Test status
Simulation time 87051405 ps
CPU time 1.12 seconds
Started Aug 03 05:47:15 PM PDT 24
Finished Aug 03 05:47:17 PM PDT 24
Peak memory 219904 kb
Host smart-fadad3fe-d94a-4711-85f7-b3d17bb9f4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789188853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1789188853
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1516920939
Short name T60
Test name
Test status
Simulation time 36286853 ps
CPU time 0.91 seconds
Started Aug 03 05:47:19 PM PDT 24
Finished Aug 03 05:47:20 PM PDT 24
Peak memory 215616 kb
Host smart-405cd207-5ff3-4a60-a0a0-cd52065824a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516920939 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1516920939
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1258881205
Short name T584
Test name
Test status
Simulation time 18144126 ps
CPU time 1.01 seconds
Started Aug 03 05:47:16 PM PDT 24
Finished Aug 03 05:47:17 PM PDT 24
Peak memory 207112 kb
Host smart-cf11596e-fa82-47c7-9f54-b70b303611c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258881205 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1258881205
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.535758221
Short name T945
Test name
Test status
Simulation time 56642469 ps
CPU time 0.95 seconds
Started Aug 03 05:47:15 PM PDT 24
Finished Aug 03 05:47:16 PM PDT 24
Peak memory 215240 kb
Host smart-a98e7cbb-32f5-4cb9-8297-029f9e4b2b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535758221 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.535758221
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1287610990
Short name T361
Test name
Test status
Simulation time 309383257 ps
CPU time 3.42 seconds
Started Aug 03 05:47:18 PM PDT 24
Finished Aug 03 05:47:22 PM PDT 24
Peak memory 215180 kb
Host smart-895ea428-76be-456c-a03e-dd2dae6c8c8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287610990 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1287610990
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.4188795906
Short name T722
Test name
Test status
Simulation time 38012517538 ps
CPU time 493.48 seconds
Started Aug 03 05:47:17 PM PDT 24
Finished Aug 03 05:55:30 PM PDT 24
Peak memory 223732 kb
Host smart-d2638a8b-7e0d-4cf3-acf9-a2f1152cdf63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188795906 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.4188795906
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.4191744957
Short name T205
Test name
Test status
Simulation time 137620523 ps
CPU time 1.2 seconds
Started Aug 03 05:50:46 PM PDT 24
Finished Aug 03 05:50:48 PM PDT 24
Peak memory 215596 kb
Host smart-3c5a637c-e0a7-4a7f-bd9f-521797882485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191744957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.4191744957
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.4076613449
Short name T771
Test name
Test status
Simulation time 34369011 ps
CPU time 1.13 seconds
Started Aug 03 05:50:44 PM PDT 24
Finished Aug 03 05:50:45 PM PDT 24
Peak memory 219796 kb
Host smart-7ec3b0fe-2cdd-47be-84cc-d31ac66317b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076613449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.4076613449
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2477746697
Short name T721
Test name
Test status
Simulation time 463097116 ps
CPU time 4.05 seconds
Started Aug 03 05:50:38 PM PDT 24
Finished Aug 03 05:50:42 PM PDT 24
Peak memory 217428 kb
Host smart-8b067f19-711f-4f61-a952-023266f20644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477746697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2477746697
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.4205551429
Short name T157
Test name
Test status
Simulation time 29746874 ps
CPU time 1.24 seconds
Started Aug 03 05:50:44 PM PDT 24
Finished Aug 03 05:50:45 PM PDT 24
Peak memory 220572 kb
Host smart-7b97f723-9816-4ad2-bd56-23ddb0a6d55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205551429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.4205551429
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.2303554000
Short name T573
Test name
Test status
Simulation time 29152320 ps
CPU time 1.17 seconds
Started Aug 03 05:50:42 PM PDT 24
Finished Aug 03 05:50:43 PM PDT 24
Peak memory 218536 kb
Host smart-bbe27300-2e6a-4725-a135-a264ef6cb0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303554000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2303554000
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3011346294
Short name T62
Test name
Test status
Simulation time 71203548 ps
CPU time 1.12 seconds
Started Aug 03 05:50:45 PM PDT 24
Finished Aug 03 05:50:46 PM PDT 24
Peak memory 217316 kb
Host smart-763aa5af-5ea3-4050-a6c8-e0c3ba2b032e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011346294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3011346294
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.14673641
Short name T276
Test name
Test status
Simulation time 57995477 ps
CPU time 1.27 seconds
Started Aug 03 05:50:42 PM PDT 24
Finished Aug 03 05:50:43 PM PDT 24
Peak memory 219436 kb
Host smart-5ae5c5ef-964c-4d72-8151-e6692eb3935f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14673641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.14673641
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.154763638
Short name T630
Test name
Test status
Simulation time 30136171 ps
CPU time 1.28 seconds
Started Aug 03 05:50:44 PM PDT 24
Finished Aug 03 05:50:45 PM PDT 24
Peak memory 219456 kb
Host smart-d01a370b-e784-4d51-9db0-d3f1405948b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154763638 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.154763638
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3517275749
Short name T398
Test name
Test status
Simulation time 57893280 ps
CPU time 1.03 seconds
Started Aug 03 05:50:46 PM PDT 24
Finished Aug 03 05:50:47 PM PDT 24
Peak memory 217328 kb
Host smart-eb8a81e2-211b-4e9b-847b-83942efbe2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517275749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3517275749
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2350006862
Short name T208
Test name
Test status
Simulation time 48989531 ps
CPU time 1.19 seconds
Started Aug 03 05:50:45 PM PDT 24
Finished Aug 03 05:50:46 PM PDT 24
Peak memory 219756 kb
Host smart-7f41d1d3-a030-4c3b-aecf-3a96ba945749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350006862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2350006862
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.1922465756
Short name T103
Test name
Test status
Simulation time 63732437 ps
CPU time 0.84 seconds
Started Aug 03 05:50:45 PM PDT 24
Finished Aug 03 05:50:46 PM PDT 24
Peak memory 218472 kb
Host smart-3b8d8acc-b8a2-4ec8-91fc-10ee47f9c26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922465756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1922465756
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.944296842
Short name T26
Test name
Test status
Simulation time 35671655 ps
CPU time 1.54 seconds
Started Aug 03 05:50:43 PM PDT 24
Finished Aug 03 05:50:45 PM PDT 24
Peak memory 218572 kb
Host smart-5743f65b-b68c-4d43-a7c6-ceef99618e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944296842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.944296842
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3814080633
Short name T436
Test name
Test status
Simulation time 69117375 ps
CPU time 1.12 seconds
Started Aug 03 05:50:46 PM PDT 24
Finished Aug 03 05:50:47 PM PDT 24
Peak memory 218632 kb
Host smart-8f778630-2331-473d-89a0-7aa0bb288dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814080633 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3814080633
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.1893283098
Short name T958
Test name
Test status
Simulation time 19092579 ps
CPU time 1.05 seconds
Started Aug 03 05:50:43 PM PDT 24
Finished Aug 03 05:50:44 PM PDT 24
Peak memory 219436 kb
Host smart-2955b995-1191-4693-a3ed-5faab915eb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893283098 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1893283098
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.714015344
Short name T981
Test name
Test status
Simulation time 123747160 ps
CPU time 1.46 seconds
Started Aug 03 05:50:45 PM PDT 24
Finished Aug 03 05:50:47 PM PDT 24
Peak memory 218572 kb
Host smart-511d9272-1edc-4611-9b6c-36b70635b78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714015344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.714015344
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1942992148
Short name T549
Test name
Test status
Simulation time 26860765 ps
CPU time 1.26 seconds
Started Aug 03 05:50:50 PM PDT 24
Finished Aug 03 05:50:51 PM PDT 24
Peak memory 215636 kb
Host smart-947eaa19-4ba0-4c1a-988f-d0e9ea4e962f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942992148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1942992148
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2763763226
Short name T115
Test name
Test status
Simulation time 24376387 ps
CPU time 1 seconds
Started Aug 03 05:50:48 PM PDT 24
Finished Aug 03 05:50:49 PM PDT 24
Peak memory 219604 kb
Host smart-499498dd-a0a6-4ca4-b018-da4dd402ea9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763763226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2763763226
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.161310573
Short name T325
Test name
Test status
Simulation time 35422793 ps
CPU time 1.14 seconds
Started Aug 03 05:50:44 PM PDT 24
Finished Aug 03 05:50:46 PM PDT 24
Peak memory 218744 kb
Host smart-337e953f-8ce0-4f4e-9ec8-9cd3ef6a51e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161310573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.161310573
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.42859251
Short name T742
Test name
Test status
Simulation time 35162976 ps
CPU time 1.08 seconds
Started Aug 03 05:50:48 PM PDT 24
Finished Aug 03 05:50:49 PM PDT 24
Peak memory 219700 kb
Host smart-e3282595-360f-48f0-ab79-0e91a46c99cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42859251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.42859251
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.873116348
Short name T887
Test name
Test status
Simulation time 33866832 ps
CPU time 0.95 seconds
Started Aug 03 05:50:50 PM PDT 24
Finished Aug 03 05:50:51 PM PDT 24
Peak memory 219796 kb
Host smart-8d0a6a25-620a-4fa5-8d16-84d4892521ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873116348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.873116348
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2734702316
Short name T774
Test name
Test status
Simulation time 91641021 ps
CPU time 1.7 seconds
Started Aug 03 05:50:51 PM PDT 24
Finished Aug 03 05:50:52 PM PDT 24
Peak memory 220200 kb
Host smart-705d19ee-8e6a-4bf1-84e0-31416ec7a63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734702316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2734702316
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.2218471283
Short name T175
Test name
Test status
Simulation time 63769132 ps
CPU time 1.15 seconds
Started Aug 03 05:50:51 PM PDT 24
Finished Aug 03 05:50:52 PM PDT 24
Peak memory 220784 kb
Host smart-0fec71a8-6660-4dc4-8200-7164d916ae1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218471283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2218471283
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_genbits.3462013354
Short name T646
Test name
Test status
Simulation time 38091375 ps
CPU time 1.59 seconds
Started Aug 03 05:50:51 PM PDT 24
Finished Aug 03 05:50:52 PM PDT 24
Peak memory 218688 kb
Host smart-630757f3-80bc-4d69-b0cc-9a26b286f70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462013354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3462013354
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.440328722
Short name T350
Test name
Test status
Simulation time 62544695 ps
CPU time 1.23 seconds
Started Aug 03 05:50:51 PM PDT 24
Finished Aug 03 05:50:52 PM PDT 24
Peak memory 219316 kb
Host smart-10060bd2-8f80-4f6a-b9d4-d1114f3383cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440328722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.440328722
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.161482763
Short name T714
Test name
Test status
Simulation time 45167825 ps
CPU time 1.01 seconds
Started Aug 03 05:50:51 PM PDT 24
Finished Aug 03 05:50:52 PM PDT 24
Peak memory 224120 kb
Host smart-67cd8a7f-0495-493d-a97b-eca33b908327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161482763 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.161482763
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.390287645
Short name T431
Test name
Test status
Simulation time 65979045 ps
CPU time 1.6 seconds
Started Aug 03 05:50:50 PM PDT 24
Finished Aug 03 05:50:52 PM PDT 24
Peak memory 220116 kb
Host smart-43cf0d40-2683-49cf-a9d0-9a980f45df0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390287645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.390287645
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.2081170279
Short name T986
Test name
Test status
Simulation time 31097031 ps
CPU time 1.22 seconds
Started Aug 03 05:50:49 PM PDT 24
Finished Aug 03 05:50:50 PM PDT 24
Peak memory 220164 kb
Host smart-197f2e21-6cc4-490c-8d08-83968c6a2a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081170279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2081170279
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.1133153679
Short name T372
Test name
Test status
Simulation time 20589181 ps
CPU time 0.92 seconds
Started Aug 03 05:50:53 PM PDT 24
Finished Aug 03 05:50:54 PM PDT 24
Peak memory 218428 kb
Host smart-d78348f7-5b9d-4e74-9c55-0ca62e1f3336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133153679 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1133153679
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3219113757
Short name T597
Test name
Test status
Simulation time 61170944 ps
CPU time 1.06 seconds
Started Aug 03 05:50:51 PM PDT 24
Finished Aug 03 05:50:52 PM PDT 24
Peak memory 218616 kb
Host smart-7559bdef-f613-4c8b-9e89-ed8a25a640f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219113757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3219113757
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1468722498
Short name T292
Test name
Test status
Simulation time 67182855 ps
CPU time 1.11 seconds
Started Aug 03 05:47:32 PM PDT 24
Finished Aug 03 05:47:33 PM PDT 24
Peak memory 218788 kb
Host smart-fe15a1f7-b81c-4b25-b968-0ba46484b94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468722498 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1468722498
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2382834202
Short name T381
Test name
Test status
Simulation time 22261580 ps
CPU time 1.03 seconds
Started Aug 03 05:47:32 PM PDT 24
Finished Aug 03 05:47:33 PM PDT 24
Peak memory 206716 kb
Host smart-9d6ae2b7-ed0e-4854-a0dc-b04c023f5078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382834202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2382834202
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1198731772
Short name T894
Test name
Test status
Simulation time 70053775 ps
CPU time 0.87 seconds
Started Aug 03 05:47:34 PM PDT 24
Finished Aug 03 05:47:35 PM PDT 24
Peak memory 216324 kb
Host smart-cbbbbfcc-b3cb-49b5-8d1c-feafd8cdc9fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198731772 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1198731772
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2556532129
Short name T449
Test name
Test status
Simulation time 36226735 ps
CPU time 1.23 seconds
Started Aug 03 05:47:34 PM PDT 24
Finished Aug 03 05:47:36 PM PDT 24
Peak memory 218520 kb
Host smart-3ff64dd0-eb37-4b89-8639-6736aa063e61
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556532129 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2556532129
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2920115846
Short name T194
Test name
Test status
Simulation time 59168549 ps
CPU time 1.02 seconds
Started Aug 03 05:47:32 PM PDT 24
Finished Aug 03 05:47:33 PM PDT 24
Peak memory 219648 kb
Host smart-24848631-a942-4f40-99ae-2e23b5f1e347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920115846 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2920115846
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2575728820
Short name T567
Test name
Test status
Simulation time 135456766 ps
CPU time 1.29 seconds
Started Aug 03 05:47:27 PM PDT 24
Finished Aug 03 05:47:29 PM PDT 24
Peak memory 218892 kb
Host smart-6f75a55f-c2c0-4feb-9f55-80ffed9397b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575728820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2575728820
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2762699232
Short name T474
Test name
Test status
Simulation time 24115591 ps
CPU time 0.96 seconds
Started Aug 03 05:47:29 PM PDT 24
Finished Aug 03 05:47:30 PM PDT 24
Peak memory 215352 kb
Host smart-bec1a052-944d-400d-9e90-834b75c6d46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762699232 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2762699232
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1997009378
Short name T87
Test name
Test status
Simulation time 43733025 ps
CPU time 0.93 seconds
Started Aug 03 05:47:28 PM PDT 24
Finished Aug 03 05:47:29 PM PDT 24
Peak memory 207096 kb
Host smart-61a60d92-e828-4007-8a1a-c6abd2e1c474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997009378 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1997009378
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.4057356077
Short name T349
Test name
Test status
Simulation time 16624929 ps
CPU time 1 seconds
Started Aug 03 05:47:29 PM PDT 24
Finished Aug 03 05:47:30 PM PDT 24
Peak memory 215284 kb
Host smart-9eeef248-2992-40c5-a2e5-a911586bfff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057356077 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.4057356077
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.4239341537
Short name T825
Test name
Test status
Simulation time 304023594 ps
CPU time 2.33 seconds
Started Aug 03 05:47:28 PM PDT 24
Finished Aug 03 05:47:31 PM PDT 24
Peak memory 217148 kb
Host smart-19f0757a-9d03-4fab-bfad-50d916e55a18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239341537 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.4239341537
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_alert.4004302270
Short name T706
Test name
Test status
Simulation time 23121678 ps
CPU time 1.14 seconds
Started Aug 03 05:50:51 PM PDT 24
Finished Aug 03 05:50:52 PM PDT 24
Peak memory 218596 kb
Host smart-f866b18f-60bd-464f-86f5-726e04ea4c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004302270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.4004302270
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3822923769
Short name T667
Test name
Test status
Simulation time 22961947 ps
CPU time 1.1 seconds
Started Aug 03 05:50:47 PM PDT 24
Finished Aug 03 05:50:49 PM PDT 24
Peak memory 218488 kb
Host smart-1488b465-4f66-4c37-8235-65342216aa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822923769 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3822923769
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3599543758
Short name T440
Test name
Test status
Simulation time 36601750 ps
CPU time 1.38 seconds
Started Aug 03 05:50:49 PM PDT 24
Finished Aug 03 05:50:51 PM PDT 24
Peak memory 216876 kb
Host smart-034066fd-73cf-4ff2-a075-08c4a1ff8f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599543758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3599543758
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.3449449148
Short name T178
Test name
Test status
Simulation time 88433457 ps
CPU time 1.23 seconds
Started Aug 03 05:50:54 PM PDT 24
Finished Aug 03 05:50:56 PM PDT 24
Peak memory 220668 kb
Host smart-6001f99f-fab6-451d-a58b-443a27983d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449449148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.3449449148
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1016790024
Short name T214
Test name
Test status
Simulation time 24605167 ps
CPU time 0.96 seconds
Started Aug 03 05:50:56 PM PDT 24
Finished Aug 03 05:50:57 PM PDT 24
Peak memory 218368 kb
Host smart-1975948f-2945-4381-8da2-cb8a5b9d1d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016790024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1016790024
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.4002179751
Short name T605
Test name
Test status
Simulation time 49295758 ps
CPU time 1.53 seconds
Started Aug 03 05:50:52 PM PDT 24
Finished Aug 03 05:50:53 PM PDT 24
Peak memory 218648 kb
Host smart-cfa3c0d9-d06c-4258-bed5-49d6d90569ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002179751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.4002179751
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.1805650760
Short name T295
Test name
Test status
Simulation time 29052022 ps
CPU time 1.25 seconds
Started Aug 03 05:50:56 PM PDT 24
Finished Aug 03 05:50:57 PM PDT 24
Peak memory 219136 kb
Host smart-3bf46419-cba6-452b-bc05-0829d9d66fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805650760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1805650760
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1549743968
Short name T128
Test name
Test status
Simulation time 19436347 ps
CPU time 1.09 seconds
Started Aug 03 05:50:54 PM PDT 24
Finished Aug 03 05:50:56 PM PDT 24
Peak memory 218800 kb
Host smart-40d7fdb1-52e8-4da1-aaae-a639dd7a9f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549743968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1549743968
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3893584114
Short name T471
Test name
Test status
Simulation time 42101421 ps
CPU time 1.38 seconds
Started Aug 03 05:50:59 PM PDT 24
Finished Aug 03 05:51:00 PM PDT 24
Peak memory 218632 kb
Host smart-18800d4c-29a9-4181-8867-9cee405e36b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893584114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3893584114
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2207148046
Short name T735
Test name
Test status
Simulation time 229905068 ps
CPU time 1.23 seconds
Started Aug 03 05:50:58 PM PDT 24
Finished Aug 03 05:51:00 PM PDT 24
Peak memory 220712 kb
Host smart-c2013649-5697-4590-9dc6-de102ccb7db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207148046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2207148046
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.3460034934
Short name T625
Test name
Test status
Simulation time 22576572 ps
CPU time 0.92 seconds
Started Aug 03 05:50:54 PM PDT 24
Finished Aug 03 05:50:55 PM PDT 24
Peak memory 218704 kb
Host smart-dbb70a17-4583-4c18-8232-849ab4d5da7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460034934 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3460034934
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3160096532
Short name T430
Test name
Test status
Simulation time 34729869 ps
CPU time 1.07 seconds
Started Aug 03 05:50:59 PM PDT 24
Finished Aug 03 05:51:00 PM PDT 24
Peak memory 217496 kb
Host smart-266abcc2-b4d6-48e8-9abe-54838c7b1e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160096532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3160096532
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.678379873
Short name T185
Test name
Test status
Simulation time 26406337 ps
CPU time 1.13 seconds
Started Aug 03 05:50:54 PM PDT 24
Finished Aug 03 05:50:55 PM PDT 24
Peak memory 218668 kb
Host smart-7cdf88c6-0264-4ad2-9ae8-ec0d64866504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678379873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.678379873
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.2379916818
Short name T681
Test name
Test status
Simulation time 24176479 ps
CPU time 0.94 seconds
Started Aug 03 05:50:55 PM PDT 24
Finished Aug 03 05:50:56 PM PDT 24
Peak memory 218564 kb
Host smart-85ee1508-95bd-401e-86ed-f1d7203b05ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379916818 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2379916818
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/65.edn_alert.2490199912
Short name T854
Test name
Test status
Simulation time 23035737 ps
CPU time 1.15 seconds
Started Aug 03 05:51:00 PM PDT 24
Finished Aug 03 05:51:01 PM PDT 24
Peak memory 218688 kb
Host smart-5993ff85-3273-40af-b824-5a39b3886f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490199912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.2490199912
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.2482401755
Short name T101
Test name
Test status
Simulation time 24050325 ps
CPU time 1.06 seconds
Started Aug 03 05:51:01 PM PDT 24
Finished Aug 03 05:51:02 PM PDT 24
Peak memory 218424 kb
Host smart-e4ae1f76-f4eb-4ae0-933d-f907bc62f970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482401755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2482401755
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1273675522
Short name T74
Test name
Test status
Simulation time 345977677 ps
CPU time 2 seconds
Started Aug 03 05:50:55 PM PDT 24
Finished Aug 03 05:50:57 PM PDT 24
Peak memory 218776 kb
Host smart-ceb5f77e-bfdb-49db-8f77-25edf386c84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273675522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1273675522
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.3244713743
Short name T925
Test name
Test status
Simulation time 54225505 ps
CPU time 1.2 seconds
Started Aug 03 05:51:01 PM PDT 24
Finished Aug 03 05:51:02 PM PDT 24
Peak memory 220696 kb
Host smart-db77ef09-230f-4b82-b7ee-bf1c4169eeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244713743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.3244713743
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1580748759
Short name T51
Test name
Test status
Simulation time 20012569 ps
CPU time 1.17 seconds
Started Aug 03 05:51:02 PM PDT 24
Finished Aug 03 05:51:04 PM PDT 24
Peak memory 224012 kb
Host smart-058d7c9f-8843-4b9c-8562-811c51cfd0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580748759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1580748759
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2222705341
Short name T492
Test name
Test status
Simulation time 113709071 ps
CPU time 1.52 seconds
Started Aug 03 05:50:59 PM PDT 24
Finished Aug 03 05:51:01 PM PDT 24
Peak memory 218628 kb
Host smart-c2610877-97bb-4893-ae4e-b9729e1d2c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222705341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2222705341
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.1588323019
Short name T169
Test name
Test status
Simulation time 91210721 ps
CPU time 1.23 seconds
Started Aug 03 05:50:59 PM PDT 24
Finished Aug 03 05:51:00 PM PDT 24
Peak memory 219768 kb
Host smart-70394e6b-07c1-4578-a538-1675984c180b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588323019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1588323019
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1765860180
Short name T209
Test name
Test status
Simulation time 19203893 ps
CPU time 1.06 seconds
Started Aug 03 05:50:59 PM PDT 24
Finished Aug 03 05:51:00 PM PDT 24
Peak memory 218660 kb
Host smart-9b53edcc-84fe-45b8-8a0c-b6b6eb0975af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765860180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1765860180
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2987433184
Short name T787
Test name
Test status
Simulation time 69055067 ps
CPU time 1.18 seconds
Started Aug 03 05:51:02 PM PDT 24
Finished Aug 03 05:51:03 PM PDT 24
Peak memory 215200 kb
Host smart-0e446739-4e3d-445d-b336-9c9dfe9f7068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987433184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2987433184
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.498106100
Short name T795
Test name
Test status
Simulation time 58105182 ps
CPU time 1.25 seconds
Started Aug 03 05:50:59 PM PDT 24
Finished Aug 03 05:51:00 PM PDT 24
Peak memory 215716 kb
Host smart-ebe7c9d9-61c4-46a3-950d-469fdd888643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498106100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.498106100
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.380374749
Short name T897
Test name
Test status
Simulation time 23612717 ps
CPU time 1.19 seconds
Started Aug 03 05:51:04 PM PDT 24
Finished Aug 03 05:51:05 PM PDT 24
Peak memory 220388 kb
Host smart-2ec56547-2f2a-4910-a56f-63b8a03cbcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380374749 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.380374749
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1639633820
Short name T753
Test name
Test status
Simulation time 30168271 ps
CPU time 1.3 seconds
Started Aug 03 05:50:59 PM PDT 24
Finished Aug 03 05:51:00 PM PDT 24
Peak memory 217272 kb
Host smart-b4568020-6fe0-4be7-87bb-3bf870ceac1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639633820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1639633820
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.346644048
Short name T978
Test name
Test status
Simulation time 86103294 ps
CPU time 1.06 seconds
Started Aug 03 05:51:03 PM PDT 24
Finished Aug 03 05:51:05 PM PDT 24
Peak memory 219708 kb
Host smart-20361eba-881a-4d2f-bd72-8e5f8bad7b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346644048 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.346644048
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3994775062
Short name T153
Test name
Test status
Simulation time 27094376 ps
CPU time 1.26 seconds
Started Aug 03 05:51:04 PM PDT 24
Finished Aug 03 05:51:05 PM PDT 24
Peak memory 219824 kb
Host smart-080ee44c-320a-492b-ac7a-b9d1be475fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994775062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3994775062
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1206071215
Short name T968
Test name
Test status
Simulation time 38598867 ps
CPU time 1.66 seconds
Started Aug 03 05:51:04 PM PDT 24
Finished Aug 03 05:51:06 PM PDT 24
Peak memory 217396 kb
Host smart-22c86dcd-d0a8-485b-8270-d683f12587c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206071215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1206071215
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1147683142
Short name T173
Test name
Test status
Simulation time 47903935 ps
CPU time 1.25 seconds
Started Aug 03 05:47:39 PM PDT 24
Finished Aug 03 05:47:40 PM PDT 24
Peak memory 219728 kb
Host smart-39e109ca-d354-4a7e-ad7f-24485ae8fc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147683142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1147683142
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.798673845
Short name T433
Test name
Test status
Simulation time 25911933 ps
CPU time 0.89 seconds
Started Aug 03 05:47:40 PM PDT 24
Finished Aug 03 05:47:41 PM PDT 24
Peak memory 214904 kb
Host smart-2bd497d2-18ff-4669-b905-600c687ac2ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798673845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.798673845
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2665539869
Short name T416
Test name
Test status
Simulation time 46364184 ps
CPU time 0.86 seconds
Started Aug 03 05:47:39 PM PDT 24
Finished Aug 03 05:47:40 PM PDT 24
Peak memory 215288 kb
Host smart-dd2776bf-cb4d-4e6e-a49e-85ec5ec1a4bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665539869 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2665539869
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1989434458
Short name T769
Test name
Test status
Simulation time 56956675 ps
CPU time 1.13 seconds
Started Aug 03 05:47:41 PM PDT 24
Finished Aug 03 05:47:42 PM PDT 24
Peak memory 218532 kb
Host smart-45289e44-2400-4448-ae2b-ced01758dcc0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989434458 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1989434458
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2315571907
Short name T419
Test name
Test status
Simulation time 18446634 ps
CPU time 1.05 seconds
Started Aug 03 05:47:41 PM PDT 24
Finished Aug 03 05:47:42 PM PDT 24
Peak memory 218576 kb
Host smart-27a09b75-7174-43d7-91e4-f17bbb5e0e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315571907 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2315571907
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.704792808
Short name T502
Test name
Test status
Simulation time 24333796 ps
CPU time 1.08 seconds
Started Aug 03 05:47:32 PM PDT 24
Finished Aug 03 05:47:34 PM PDT 24
Peak memory 219808 kb
Host smart-86eb85f4-b189-48ea-b7f7-83f0c18c7049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704792808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.704792808
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1690000043
Short name T959
Test name
Test status
Simulation time 28610641 ps
CPU time 0.92 seconds
Started Aug 03 05:47:39 PM PDT 24
Finished Aug 03 05:47:40 PM PDT 24
Peak memory 215356 kb
Host smart-f1716306-b641-4cc2-8a31-de77af402f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690000043 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1690000043
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3902665809
Short name T85
Test name
Test status
Simulation time 23193617 ps
CPU time 0.98 seconds
Started Aug 03 05:47:34 PM PDT 24
Finished Aug 03 05:47:35 PM PDT 24
Peak memory 207076 kb
Host smart-1cf3e157-7715-4025-88c8-debf47fae073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902665809 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3902665809
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1815979635
Short name T750
Test name
Test status
Simulation time 38219220 ps
CPU time 0.93 seconds
Started Aug 03 05:47:32 PM PDT 24
Finished Aug 03 05:47:33 PM PDT 24
Peak memory 215292 kb
Host smart-42bbcf04-3d24-4321-961e-7b9c63d0949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815979635 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1815979635
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2168601616
Short name T658
Test name
Test status
Simulation time 105569355 ps
CPU time 2.54 seconds
Started Aug 03 05:47:34 PM PDT 24
Finished Aug 03 05:47:36 PM PDT 24
Peak memory 215192 kb
Host smart-cffbcbee-7ff3-4b0e-ae1e-73ee8e8dd741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168601616 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2168601616
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3758640339
Short name T645
Test name
Test status
Simulation time 40421778195 ps
CPU time 946.53 seconds
Started Aug 03 05:47:39 PM PDT 24
Finished Aug 03 06:03:26 PM PDT 24
Peak memory 223816 kb
Host smart-0d0e7264-3160-4065-be37-af0e93dd9eef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758640339 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3758640339
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.3690218243
Short name T180
Test name
Test status
Simulation time 72944562 ps
CPU time 1.24 seconds
Started Aug 03 05:51:07 PM PDT 24
Finished Aug 03 05:51:08 PM PDT 24
Peak memory 215696 kb
Host smart-e3c8269f-daef-4fa1-a91e-ecbf0cdd91a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690218243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.3690218243
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2773100075
Short name T193
Test name
Test status
Simulation time 19767148 ps
CPU time 1.05 seconds
Started Aug 03 05:51:02 PM PDT 24
Finished Aug 03 05:51:03 PM PDT 24
Peak memory 218380 kb
Host smart-e2b255ea-0976-4123-97b0-87ed17647260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773100075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2773100075
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.4131396473
Short name T828
Test name
Test status
Simulation time 164491854 ps
CPU time 1.04 seconds
Started Aug 03 05:51:04 PM PDT 24
Finished Aug 03 05:51:05 PM PDT 24
Peak memory 217392 kb
Host smart-737cfc5f-eb39-4146-a942-9203a94a9460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131396473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.4131396473
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.394698619
Short name T422
Test name
Test status
Simulation time 20755387 ps
CPU time 1.12 seconds
Started Aug 03 05:51:07 PM PDT 24
Finished Aug 03 05:51:08 PM PDT 24
Peak memory 219900 kb
Host smart-d67cca44-04d0-4969-b4c4-20e7358239ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394698619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.394698619
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2143856033
Short name T73
Test name
Test status
Simulation time 63607661 ps
CPU time 2.2 seconds
Started Aug 03 05:51:07 PM PDT 24
Finished Aug 03 05:51:09 PM PDT 24
Peak memory 219980 kb
Host smart-502da02d-6871-4b97-aa6a-f8fe29962172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143856033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2143856033
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.45917602
Short name T165
Test name
Test status
Simulation time 71975290 ps
CPU time 1.29 seconds
Started Aug 03 05:51:12 PM PDT 24
Finished Aug 03 05:51:14 PM PDT 24
Peak memory 218424 kb
Host smart-cd5f8100-f54c-423e-b19c-5f7fbc8d6b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45917602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.45917602
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.1805945892
Short name T111
Test name
Test status
Simulation time 50454868 ps
CPU time 1.09 seconds
Started Aug 03 05:51:12 PM PDT 24
Finished Aug 03 05:51:13 PM PDT 24
Peak memory 219508 kb
Host smart-66659543-5848-416f-a0e2-fa5acb03914d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805945892 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1805945892
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1679483507
Short name T720
Test name
Test status
Simulation time 32143567 ps
CPU time 1.17 seconds
Started Aug 03 05:51:10 PM PDT 24
Finished Aug 03 05:51:11 PM PDT 24
Peak memory 218340 kb
Host smart-9c047d08-d6e3-42d6-a8cf-87f13acef612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679483507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1679483507
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2150947026
Short name T574
Test name
Test status
Simulation time 29279292 ps
CPU time 1.26 seconds
Started Aug 03 05:51:15 PM PDT 24
Finished Aug 03 05:51:16 PM PDT 24
Peak memory 221212 kb
Host smart-bb77522d-66f6-4248-b809-50cd49c3ca5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150947026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2150947026
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.4076188202
Short name T485
Test name
Test status
Simulation time 18289667 ps
CPU time 1.02 seconds
Started Aug 03 05:51:10 PM PDT 24
Finished Aug 03 05:51:11 PM PDT 24
Peak memory 218456 kb
Host smart-a68c8f1c-de14-4e01-b910-500046fdc5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076188202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.4076188202
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3691342883
Short name T884
Test name
Test status
Simulation time 188223074 ps
CPU time 1.23 seconds
Started Aug 03 05:51:11 PM PDT 24
Finished Aug 03 05:51:12 PM PDT 24
Peak memory 217148 kb
Host smart-de791ace-abf7-4394-93ce-c7ab4c4106d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691342883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3691342883
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2633007096
Short name T796
Test name
Test status
Simulation time 28876694 ps
CPU time 1.32 seconds
Started Aug 03 05:51:10 PM PDT 24
Finished Aug 03 05:51:12 PM PDT 24
Peak memory 220000 kb
Host smart-15b95ace-3dfd-4740-a8e8-394c082a96ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633007096 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2633007096
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.658420828
Short name T726
Test name
Test status
Simulation time 51407480 ps
CPU time 0.9 seconds
Started Aug 03 05:51:15 PM PDT 24
Finished Aug 03 05:51:16 PM PDT 24
Peak memory 223832 kb
Host smart-4a9bcbbc-2b8b-4409-8098-ffca50d33e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658420828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.658420828
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2881625684
Short name T318
Test name
Test status
Simulation time 200684473 ps
CPU time 1.93 seconds
Started Aug 03 05:51:12 PM PDT 24
Finished Aug 03 05:51:14 PM PDT 24
Peak memory 218560 kb
Host smart-a372646f-7757-4259-a380-7ce194c64a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881625684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2881625684
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.3045969177
Short name T192
Test name
Test status
Simulation time 37206731 ps
CPU time 1.19 seconds
Started Aug 03 05:51:13 PM PDT 24
Finished Aug 03 05:51:14 PM PDT 24
Peak memory 219628 kb
Host smart-f06cbc49-ca95-4392-b8f6-a5a07e4c6513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045969177 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.3045969177
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.2210208623
Short name T937
Test name
Test status
Simulation time 18816053 ps
CPU time 1.03 seconds
Started Aug 03 05:51:11 PM PDT 24
Finished Aug 03 05:51:12 PM PDT 24
Peak memory 218708 kb
Host smart-87ea0c89-a7c6-491a-8889-0a5678e071c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210208623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2210208623
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.705221020
Short name T385
Test name
Test status
Simulation time 85389231 ps
CPU time 1.12 seconds
Started Aug 03 05:51:10 PM PDT 24
Finished Aug 03 05:51:11 PM PDT 24
Peak memory 217172 kb
Host smart-42654248-9a32-4b04-b1ce-99a77db89898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705221020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.705221020
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.3076118017
Short name T816
Test name
Test status
Simulation time 40230237 ps
CPU time 1.17 seconds
Started Aug 03 05:51:10 PM PDT 24
Finished Aug 03 05:51:12 PM PDT 24
Peak memory 219008 kb
Host smart-ddbd14c6-8b95-4060-9c5e-e3d31fc90ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076118017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3076118017
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.3823704421
Short name T166
Test name
Test status
Simulation time 24999150 ps
CPU time 1.23 seconds
Started Aug 03 05:51:16 PM PDT 24
Finished Aug 03 05:51:18 PM PDT 24
Peak memory 220568 kb
Host smart-d8a1ec25-29ef-45bb-8d1b-2708b0b0d982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823704421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3823704421
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.353932723
Short name T660
Test name
Test status
Simulation time 134233287 ps
CPU time 1.6 seconds
Started Aug 03 05:51:10 PM PDT 24
Finished Aug 03 05:51:12 PM PDT 24
Peak memory 218940 kb
Host smart-c1c06192-a413-4004-bd2a-b1c2e9dc1e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353932723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.353932723
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.4211364525
Short name T150
Test name
Test status
Simulation time 32927113 ps
CPU time 1.35 seconds
Started Aug 03 05:51:11 PM PDT 24
Finished Aug 03 05:51:12 PM PDT 24
Peak memory 215688 kb
Host smart-38157179-ea2c-48b5-9fac-8e1703ef3fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211364525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.4211364525
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3422903502
Short name T210
Test name
Test status
Simulation time 28456704 ps
CPU time 0.97 seconds
Started Aug 03 05:51:20 PM PDT 24
Finished Aug 03 05:51:21 PM PDT 24
Peak memory 223828 kb
Host smart-d3c19419-dfe7-4eb5-9e97-e4fd5a850a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422903502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3422903502
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2761911699
Short name T357
Test name
Test status
Simulation time 40304070 ps
CPU time 1.11 seconds
Started Aug 03 05:51:10 PM PDT 24
Finished Aug 03 05:51:11 PM PDT 24
Peak memory 217376 kb
Host smart-77d3afb3-d877-489d-ac11-a9a4ee81fba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761911699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2761911699
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.1228483148
Short name T982
Test name
Test status
Simulation time 73455303 ps
CPU time 1.16 seconds
Started Aug 03 05:51:15 PM PDT 24
Finished Aug 03 05:51:16 PM PDT 24
Peak memory 219908 kb
Host smart-5dc8785a-e708-4565-9d3e-d179455fb4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228483148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.1228483148
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.229106454
Short name T187
Test name
Test status
Simulation time 27603178 ps
CPU time 1.05 seconds
Started Aug 03 05:51:19 PM PDT 24
Finished Aug 03 05:51:20 PM PDT 24
Peak memory 224040 kb
Host smart-06f1470c-47e7-435e-ac3c-11160282bc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229106454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.229106454
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2994144603
Short name T281
Test name
Test status
Simulation time 71416616 ps
CPU time 1.26 seconds
Started Aug 03 05:51:19 PM PDT 24
Finished Aug 03 05:51:21 PM PDT 24
Peak memory 218904 kb
Host smart-89807eab-e7a9-448b-bdbc-6a1de023b398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994144603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2994144603
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1956569725
Short name T149
Test name
Test status
Simulation time 29847186 ps
CPU time 1.19 seconds
Started Aug 03 05:51:16 PM PDT 24
Finished Aug 03 05:51:17 PM PDT 24
Peak memory 220784 kb
Host smart-f6d82e61-0ae2-48b6-9fba-40b2c817877e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956569725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1956569725
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.869726007
Short name T580
Test name
Test status
Simulation time 18366638 ps
CPU time 1.02 seconds
Started Aug 03 05:51:18 PM PDT 24
Finished Aug 03 05:51:20 PM PDT 24
Peak memory 218664 kb
Host smart-4a043dce-9c6c-42f9-a8c3-1b5b3a0c4a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869726007 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.869726007
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1193283554
Short name T65
Test name
Test status
Simulation time 101839456 ps
CPU time 1.11 seconds
Started Aug 03 05:51:17 PM PDT 24
Finished Aug 03 05:51:18 PM PDT 24
Peak memory 217380 kb
Host smart-9e90ccc9-963e-45d9-bb19-c0d0af79b893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193283554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1193283554
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.107099974
Short name T955
Test name
Test status
Simulation time 49095115 ps
CPU time 1.19 seconds
Started Aug 03 05:47:43 PM PDT 24
Finished Aug 03 05:47:45 PM PDT 24
Peak memory 219012 kb
Host smart-36bca22f-8dfa-4d28-abbd-8df0b887a5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107099974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.107099974
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.467918432
Short name T339
Test name
Test status
Simulation time 11772993 ps
CPU time 0.85 seconds
Started Aug 03 05:47:50 PM PDT 24
Finished Aug 03 05:47:51 PM PDT 24
Peak memory 206496 kb
Host smart-7d01c024-6e36-4a0f-bed7-a99067ca242a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467918432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.467918432
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2289789220
Short name T378
Test name
Test status
Simulation time 11283082 ps
CPU time 0.92 seconds
Started Aug 03 05:47:50 PM PDT 24
Finished Aug 03 05:47:51 PM PDT 24
Peak memory 216020 kb
Host smart-9ec86837-5c1f-4575-9d2a-f108529c984d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289789220 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2289789220
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1502368389
Short name T739
Test name
Test status
Simulation time 36173521 ps
CPU time 1.04 seconds
Started Aug 03 05:47:54 PM PDT 24
Finished Aug 03 05:47:56 PM PDT 24
Peak memory 217036 kb
Host smart-c346e0da-d8d8-4faa-803e-a5c2ff4c4cd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502368389 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1502368389
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.298026544
Short name T946
Test name
Test status
Simulation time 35792075 ps
CPU time 0.84 seconds
Started Aug 03 05:47:52 PM PDT 24
Finished Aug 03 05:47:53 PM PDT 24
Peak memory 218564 kb
Host smart-fdd8d49b-fa6f-44a1-9a50-ae3dd3f006d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298026544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.298026544
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3560075084
Short name T874
Test name
Test status
Simulation time 32598005 ps
CPU time 1.25 seconds
Started Aug 03 05:47:46 PM PDT 24
Finished Aug 03 05:47:47 PM PDT 24
Peak memory 217152 kb
Host smart-8fe8b961-2adc-465b-b955-1d81898a69dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560075084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3560075084
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_regwen.4099204312
Short name T294
Test name
Test status
Simulation time 19275778 ps
CPU time 1.01 seconds
Started Aug 03 05:47:44 PM PDT 24
Finished Aug 03 05:47:45 PM PDT 24
Peak memory 207064 kb
Host smart-a043fd0c-9504-4ae3-9d67-68288f76154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099204312 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.4099204312
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2525505978
Short name T514
Test name
Test status
Simulation time 18288858 ps
CPU time 1.03 seconds
Started Aug 03 05:47:39 PM PDT 24
Finished Aug 03 05:47:40 PM PDT 24
Peak memory 215288 kb
Host smart-a83481d6-e036-47ac-9b32-fc9f67a2f1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525505978 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2525505978
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.945051618
Short name T245
Test name
Test status
Simulation time 159762026 ps
CPU time 2.11 seconds
Started Aug 03 05:47:44 PM PDT 24
Finished Aug 03 05:47:46 PM PDT 24
Peak memory 217168 kb
Host smart-d64dc1ea-a43c-4936-968b-7f72293966fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945051618 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.945051618
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3241924082
Short name T225
Test name
Test status
Simulation time 136368961717 ps
CPU time 666.5 seconds
Started Aug 03 05:47:46 PM PDT 24
Finished Aug 03 05:58:53 PM PDT 24
Peak memory 220296 kb
Host smart-4baffb3b-e108-4e5d-a7ad-1525028da0a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241924082 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3241924082
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1366908098
Short name T211
Test name
Test status
Simulation time 32456304 ps
CPU time 1.29 seconds
Started Aug 03 05:51:16 PM PDT 24
Finished Aug 03 05:51:18 PM PDT 24
Peak memory 215832 kb
Host smart-d65bcc92-b935-45a5-833e-381c61d23bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366908098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1366908098
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.1944019722
Short name T170
Test name
Test status
Simulation time 26160183 ps
CPU time 1.35 seconds
Started Aug 03 05:51:16 PM PDT 24
Finished Aug 03 05:51:18 PM PDT 24
Peak memory 229804 kb
Host smart-5a11135c-b9a1-44fb-9c2f-b17735b05824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944019722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1944019722
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3597262817
Short name T344
Test name
Test status
Simulation time 91134760 ps
CPU time 1.27 seconds
Started Aug 03 05:51:21 PM PDT 24
Finished Aug 03 05:51:22 PM PDT 24
Peak memory 218964 kb
Host smart-32ef078f-e4dd-4de2-8d8e-6b226d61f9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597262817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3597262817
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2826220593
Short name T871
Test name
Test status
Simulation time 208382591 ps
CPU time 1.43 seconds
Started Aug 03 05:51:15 PM PDT 24
Finished Aug 03 05:51:17 PM PDT 24
Peak memory 218568 kb
Host smart-afbff8d8-bc15-42de-a5b8-ee40ad79ee41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826220593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2826220593
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.135317342
Short name T7
Test name
Test status
Simulation time 55291571 ps
CPU time 0.95 seconds
Started Aug 03 05:51:18 PM PDT 24
Finished Aug 03 05:51:19 PM PDT 24
Peak memory 219916 kb
Host smart-9387301b-e74a-495a-8c8e-fe020aa37f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135317342 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.135317342
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.632991083
Short name T876
Test name
Test status
Simulation time 38580163 ps
CPU time 1.1 seconds
Started Aug 03 05:51:15 PM PDT 24
Finished Aug 03 05:51:17 PM PDT 24
Peak memory 219300 kb
Host smart-c203e372-a923-4cf9-a74f-a12e4494e13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632991083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.632991083
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1643168451
Short name T604
Test name
Test status
Simulation time 29128725 ps
CPU time 0.95 seconds
Started Aug 03 05:51:21 PM PDT 24
Finished Aug 03 05:51:22 PM PDT 24
Peak memory 218308 kb
Host smart-e2a0f938-db79-49a6-b22e-428fdc5e2a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643168451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1643168451
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3529991605
Short name T477
Test name
Test status
Simulation time 139255167 ps
CPU time 1.56 seconds
Started Aug 03 05:51:21 PM PDT 24
Finished Aug 03 05:51:22 PM PDT 24
Peak memory 218764 kb
Host smart-83859ddb-42b3-4354-8d59-48bb0758cb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529991605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3529991605
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.3836573006
Short name T917
Test name
Test status
Simulation time 42549480 ps
CPU time 1.14 seconds
Started Aug 03 05:51:18 PM PDT 24
Finished Aug 03 05:51:19 PM PDT 24
Peak memory 218536 kb
Host smart-98bfcc91-2474-4258-867a-902772849a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836573006 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.3836573006
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.4160316039
Short name T16
Test name
Test status
Simulation time 36446417 ps
CPU time 1.22 seconds
Started Aug 03 05:51:16 PM PDT 24
Finished Aug 03 05:51:18 PM PDT 24
Peak memory 224188 kb
Host smart-d5cb8e21-fba7-4920-8586-201233f69553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160316039 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4160316039
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1944792246
Short name T895
Test name
Test status
Simulation time 39370010 ps
CPU time 1.38 seconds
Started Aug 03 05:51:18 PM PDT 24
Finished Aug 03 05:51:20 PM PDT 24
Peak memory 218356 kb
Host smart-65e6c927-7efb-44b9-a6bc-3526ae7d912e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944792246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1944792246
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.3246185858
Short name T136
Test name
Test status
Simulation time 23576702 ps
CPU time 1.21 seconds
Started Aug 03 05:51:18 PM PDT 24
Finished Aug 03 05:51:20 PM PDT 24
Peak memory 219180 kb
Host smart-01fe045e-5fe3-4c2b-9b9e-52c97bbe596b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246185858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.3246185858
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.824984538
Short name T59
Test name
Test status
Simulation time 36283745 ps
CPU time 0.89 seconds
Started Aug 03 05:51:18 PM PDT 24
Finished Aug 03 05:51:19 PM PDT 24
Peak memory 218544 kb
Host smart-4387e7d0-55d7-4a5a-892f-6ab0ce137608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824984538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.824984538
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3455219244
Short name T760
Test name
Test status
Simulation time 65516005 ps
CPU time 1.3 seconds
Started Aug 03 05:51:18 PM PDT 24
Finished Aug 03 05:51:20 PM PDT 24
Peak memory 218352 kb
Host smart-982912f0-5e6b-4fa2-922b-28e6a5bb71a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455219244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3455219244
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.2324267663
Short name T770
Test name
Test status
Simulation time 48699173 ps
CPU time 1.2 seconds
Started Aug 03 05:51:20 PM PDT 24
Finished Aug 03 05:51:21 PM PDT 24
Peak memory 219452 kb
Host smart-ce6ee7d0-ec62-45ad-a96c-ea3f1ff41cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324267663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2324267663
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1496190326
Short name T126
Test name
Test status
Simulation time 19321802 ps
CPU time 1.05 seconds
Started Aug 03 05:51:25 PM PDT 24
Finished Aug 03 05:51:27 PM PDT 24
Peak memory 218448 kb
Host smart-f5862e11-ee1d-409b-b25d-2714ad7771d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496190326 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1496190326
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.854678603
Short name T944
Test name
Test status
Simulation time 46589681 ps
CPU time 1.7 seconds
Started Aug 03 05:51:16 PM PDT 24
Finished Aug 03 05:51:18 PM PDT 24
Peak memory 218528 kb
Host smart-1ca5dfef-d9c3-496e-9ef8-e62f76363fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854678603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.854678603
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.587068356
Short name T457
Test name
Test status
Simulation time 24867636 ps
CPU time 1.18 seconds
Started Aug 03 05:51:20 PM PDT 24
Finished Aug 03 05:51:21 PM PDT 24
Peak memory 219764 kb
Host smart-b3596ffb-f9f2-4539-b3bd-c758abeeeea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587068356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.587068356
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2314164400
Short name T933
Test name
Test status
Simulation time 47858713 ps
CPU time 0.99 seconds
Started Aug 03 05:51:22 PM PDT 24
Finished Aug 03 05:51:23 PM PDT 24
Peak memory 218776 kb
Host smart-838137f0-c27e-46bf-8b5e-8fe0c1782050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314164400 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2314164400
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1795923669
Short name T948
Test name
Test status
Simulation time 59604835 ps
CPU time 1.33 seconds
Started Aug 03 05:51:20 PM PDT 24
Finished Aug 03 05:51:22 PM PDT 24
Peak memory 218820 kb
Host smart-8aee3936-f3e3-4509-8c4f-8078a0fed9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795923669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1795923669
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.4172789095
Short name T148
Test name
Test status
Simulation time 61357928 ps
CPU time 1.13 seconds
Started Aug 03 05:51:23 PM PDT 24
Finished Aug 03 05:51:24 PM PDT 24
Peak memory 218544 kb
Host smart-6c2aa7ef-5485-4ee7-99e6-1d856d556b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172789095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.4172789095
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2373618491
Short name T824
Test name
Test status
Simulation time 26763800 ps
CPU time 0.85 seconds
Started Aug 03 05:51:24 PM PDT 24
Finished Aug 03 05:51:25 PM PDT 24
Peak memory 218432 kb
Host smart-7455110d-9e31-4d19-8ac8-bf54f7ae7007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373618491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2373618491
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2250055086
Short name T319
Test name
Test status
Simulation time 69627295 ps
CPU time 2.2 seconds
Started Aug 03 05:51:20 PM PDT 24
Finished Aug 03 05:51:23 PM PDT 24
Peak memory 218576 kb
Host smart-8f2f38a2-9607-470f-a362-cd325b8a126a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250055086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2250055086
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.2569222555
Short name T840
Test name
Test status
Simulation time 54631168 ps
CPU time 1.02 seconds
Started Aug 03 05:51:22 PM PDT 24
Finished Aug 03 05:51:23 PM PDT 24
Peak memory 220604 kb
Host smart-13fedd71-e833-434b-8673-a9ad46bc86e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569222555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2569222555
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2783249332
Short name T480
Test name
Test status
Simulation time 32410198 ps
CPU time 1.25 seconds
Started Aug 03 05:51:24 PM PDT 24
Finished Aug 03 05:51:26 PM PDT 24
Peak memory 217340 kb
Host smart-75704c2a-ac49-4506-a367-858a0a3684eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783249332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2783249332
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.1354072187
Short name T957
Test name
Test status
Simulation time 87082603 ps
CPU time 1.2 seconds
Started Aug 03 05:51:26 PM PDT 24
Finished Aug 03 05:51:27 PM PDT 24
Peak memory 220564 kb
Host smart-1d851cc9-35b6-432c-901e-9c10d7e6d7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354072187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.1354072187
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.3999328188
Short name T143
Test name
Test status
Simulation time 23214392 ps
CPU time 1.07 seconds
Started Aug 03 05:51:24 PM PDT 24
Finished Aug 03 05:51:26 PM PDT 24
Peak memory 219632 kb
Host smart-7bcec226-0d98-4da0-af45-8a1b0ba59ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999328188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3999328188
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1436355543
Short name T303
Test name
Test status
Simulation time 39261589 ps
CPU time 1.11 seconds
Started Aug 03 05:51:24 PM PDT 24
Finished Aug 03 05:51:25 PM PDT 24
Peak memory 219464 kb
Host smart-183fde9a-a329-4aa2-acc6-293dcce04ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436355543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1436355543
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert_test.1769273230
Short name T507
Test name
Test status
Simulation time 14990859 ps
CPU time 0.9 seconds
Started Aug 03 05:47:56 PM PDT 24
Finished Aug 03 05:47:57 PM PDT 24
Peak memory 206688 kb
Host smart-51d16c79-3379-4105-94da-39da25c5fabf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769273230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1769273230
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.740394878
Short name T162
Test name
Test status
Simulation time 41764523 ps
CPU time 1.49 seconds
Started Aug 03 05:47:55 PM PDT 24
Finished Aug 03 05:47:56 PM PDT 24
Peak memory 216804 kb
Host smart-f324dff4-d7e1-449e-931b-814e0339fae4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740394878 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.740394878
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3426772172
Short name T670
Test name
Test status
Simulation time 35796614 ps
CPU time 0.88 seconds
Started Aug 03 05:47:53 PM PDT 24
Finished Aug 03 05:47:54 PM PDT 24
Peak memory 218628 kb
Host smart-4eeec36a-c094-4050-a47b-147fae8962f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426772172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3426772172
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1355947923
Short name T688
Test name
Test status
Simulation time 47419535 ps
CPU time 1.77 seconds
Started Aug 03 05:47:54 PM PDT 24
Finished Aug 03 05:47:56 PM PDT 24
Peak memory 218484 kb
Host smart-cd7a16b0-9c66-478c-b55d-fa8c4c149a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355947923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1355947923
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.4182944584
Short name T730
Test name
Test status
Simulation time 37633017 ps
CPU time 1.03 seconds
Started Aug 03 05:47:50 PM PDT 24
Finished Aug 03 05:47:51 PM PDT 24
Peak memory 223820 kb
Host smart-f9a7d1d0-e387-4914-bab6-4c4a33064e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182944584 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.4182944584
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.4280307687
Short name T919
Test name
Test status
Simulation time 34648910 ps
CPU time 0.97 seconds
Started Aug 03 05:47:51 PM PDT 24
Finished Aug 03 05:47:52 PM PDT 24
Peak memory 207052 kb
Host smart-e9b6d1e2-eefa-4fd2-821b-669e3d66aa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280307687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.4280307687
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1633872463
Short name T798
Test name
Test status
Simulation time 24369173 ps
CPU time 0.91 seconds
Started Aug 03 05:47:53 PM PDT 24
Finished Aug 03 05:47:54 PM PDT 24
Peak memory 215296 kb
Host smart-0036b78d-4849-4294-b05b-9b8c7e2d6165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633872463 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1633872463
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1654522957
Short name T455
Test name
Test status
Simulation time 298680385 ps
CPU time 5.48 seconds
Started Aug 03 05:47:50 PM PDT 24
Finished Aug 03 05:47:55 PM PDT 24
Peak memory 217212 kb
Host smart-f452faa6-4f64-4968-a74b-d085f59faa33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654522957 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1654522957
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.4163554860
Short name T668
Test name
Test status
Simulation time 159340329596 ps
CPU time 954.45 seconds
Started Aug 03 05:47:50 PM PDT 24
Finished Aug 03 06:03:44 PM PDT 24
Peak memory 221268 kb
Host smart-42e07f13-c9fb-4b8e-af69-f45c074efc16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163554860 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.4163554860
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.959097979
Short name T615
Test name
Test status
Simulation time 24471881 ps
CPU time 1.26 seconds
Started Aug 03 05:51:21 PM PDT 24
Finished Aug 03 05:51:22 PM PDT 24
Peak memory 220256 kb
Host smart-dfd5fce9-6d2a-49ec-b5de-31e1403bdfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959097979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.959097979
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3096048854
Short name T360
Test name
Test status
Simulation time 69469776 ps
CPU time 1.08 seconds
Started Aug 03 05:51:21 PM PDT 24
Finished Aug 03 05:51:22 PM PDT 24
Peak memory 220720 kb
Host smart-51b53379-c82d-44c3-b207-18752c07a06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096048854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3096048854
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3324616672
Short name T330
Test name
Test status
Simulation time 47069144 ps
CPU time 1.44 seconds
Started Aug 03 05:51:22 PM PDT 24
Finished Aug 03 05:51:23 PM PDT 24
Peak memory 218312 kb
Host smart-746a33db-3d98-43d4-84e7-3ef2026d086b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324616672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3324616672
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.325102916
Short name T274
Test name
Test status
Simulation time 63225128 ps
CPU time 1.15 seconds
Started Aug 03 05:51:23 PM PDT 24
Finished Aug 03 05:51:24 PM PDT 24
Peak memory 218540 kb
Host smart-73c6feb8-91bf-4456-ba50-9887bdeec643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325102916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.325102916
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3354678323
Short name T124
Test name
Test status
Simulation time 20961968 ps
CPU time 1.14 seconds
Started Aug 03 05:51:24 PM PDT 24
Finished Aug 03 05:51:25 PM PDT 24
Peak memory 219468 kb
Host smart-d6e3478d-8fcc-450c-9d05-799a04b7a0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354678323 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3354678323
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1050525574
Short name T317
Test name
Test status
Simulation time 177541029 ps
CPU time 2.75 seconds
Started Aug 03 05:51:22 PM PDT 24
Finished Aug 03 05:51:25 PM PDT 24
Peak memory 219284 kb
Host smart-01aaefdb-b0c2-4d27-95f6-0b49ceefa7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050525574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1050525574
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.2732908149
Short name T790
Test name
Test status
Simulation time 30626192 ps
CPU time 1.16 seconds
Started Aug 03 05:51:26 PM PDT 24
Finished Aug 03 05:51:28 PM PDT 24
Peak memory 218708 kb
Host smart-0c7cb604-2e9d-4b43-ae98-9c4c8f60e6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732908149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2732908149
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3801370719
Short name T943
Test name
Test status
Simulation time 23646998 ps
CPU time 1.19 seconds
Started Aug 03 05:51:27 PM PDT 24
Finished Aug 03 05:51:28 PM PDT 24
Peak memory 229600 kb
Host smart-8c640a00-8af0-4760-bac2-e53cc8e0592f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801370719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3801370719
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3439662424
Short name T926
Test name
Test status
Simulation time 137876111 ps
CPU time 1.76 seconds
Started Aug 03 05:51:22 PM PDT 24
Finished Aug 03 05:51:24 PM PDT 24
Peak memory 219752 kb
Host smart-77a39a81-6793-4b41-9fbd-a9e692414dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439662424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3439662424
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.269675281
Short name T801
Test name
Test status
Simulation time 29583583 ps
CPU time 1.23 seconds
Started Aug 03 05:51:25 PM PDT 24
Finished Aug 03 05:51:26 PM PDT 24
Peak memory 219596 kb
Host smart-2013c07d-d73f-4c6b-9f14-97968a5e1ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269675281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.269675281
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3937594799
Short name T159
Test name
Test status
Simulation time 27332660 ps
CPU time 0.99 seconds
Started Aug 03 05:51:26 PM PDT 24
Finished Aug 03 05:51:27 PM PDT 24
Peak memory 219448 kb
Host smart-fe442b89-092c-46a8-a718-775402829c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937594799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3937594799
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.348084852
Short name T462
Test name
Test status
Simulation time 65216436 ps
CPU time 1.03 seconds
Started Aug 03 05:51:32 PM PDT 24
Finished Aug 03 05:51:34 PM PDT 24
Peak memory 215252 kb
Host smart-f5e7c422-c95a-4686-a58d-e640dd657aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348084852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.348084852
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.2856494099
Short name T899
Test name
Test status
Simulation time 73819469 ps
CPU time 1.09 seconds
Started Aug 03 05:51:28 PM PDT 24
Finished Aug 03 05:51:30 PM PDT 24
Peak memory 219616 kb
Host smart-2371a8ec-fdd8-4b3b-bf6c-c44a8d179efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856494099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.2856494099
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.3941280436
Short name T161
Test name
Test status
Simulation time 23790759 ps
CPU time 1.21 seconds
Started Aug 03 05:51:27 PM PDT 24
Finished Aug 03 05:51:29 PM PDT 24
Peak memory 219640 kb
Host smart-a4e425d6-5ea3-48df-8072-2307a9d5af14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941280436 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3941280436
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2762469747
Short name T2
Test name
Test status
Simulation time 201994543 ps
CPU time 1.78 seconds
Started Aug 03 05:51:24 PM PDT 24
Finished Aug 03 05:51:26 PM PDT 24
Peak memory 219008 kb
Host smart-37f65eec-b2fe-4e67-b2c5-3da1d6882b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762469747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2762469747
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.556395726
Short name T219
Test name
Test status
Simulation time 46158545 ps
CPU time 1.17 seconds
Started Aug 03 05:51:26 PM PDT 24
Finished Aug 03 05:51:28 PM PDT 24
Peak memory 218356 kb
Host smart-dd6c625b-c2d1-4caa-9f20-27c69de9ae2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556395726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.556395726
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.3257429781
Short name T117
Test name
Test status
Simulation time 20468787 ps
CPU time 1.12 seconds
Started Aug 03 05:51:26 PM PDT 24
Finished Aug 03 05:51:27 PM PDT 24
Peak memory 219572 kb
Host smart-50e9ac50-d590-42a7-80a1-af202a98d317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257429781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3257429781
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.94242038
Short name T806
Test name
Test status
Simulation time 213430570 ps
CPU time 1.55 seconds
Started Aug 03 05:51:26 PM PDT 24
Finished Aug 03 05:51:28 PM PDT 24
Peak memory 219100 kb
Host smart-995ebb8f-21a8-4cf5-ba35-624f4a951acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94242038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.94242038
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1834355425
Short name T799
Test name
Test status
Simulation time 32563730 ps
CPU time 1.28 seconds
Started Aug 03 05:51:27 PM PDT 24
Finished Aug 03 05:51:29 PM PDT 24
Peak memory 215688 kb
Host smart-253c2e3a-a886-475b-b659-af9a20e0d779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834355425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1834355425
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1675499064
Short name T953
Test name
Test status
Simulation time 30017836 ps
CPU time 1.29 seconds
Started Aug 03 05:51:27 PM PDT 24
Finished Aug 03 05:51:29 PM PDT 24
Peak memory 219792 kb
Host smart-3c77acf8-e8af-4393-a12c-c390b4a16d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675499064 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1675499064
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.131722026
Short name T290
Test name
Test status
Simulation time 49696416 ps
CPU time 1.17 seconds
Started Aug 03 05:51:27 PM PDT 24
Finished Aug 03 05:51:29 PM PDT 24
Peak memory 219896 kb
Host smart-69497c5e-132d-4b91-b549-feb93bbf33ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131722026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.131722026
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2416945111
Short name T299
Test name
Test status
Simulation time 29193645 ps
CPU time 1.3 seconds
Started Aug 03 05:51:27 PM PDT 24
Finished Aug 03 05:51:28 PM PDT 24
Peak memory 219584 kb
Host smart-0d406924-dd8f-4030-9457-9b54d944219b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416945111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2416945111
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.2865354328
Short name T50
Test name
Test status
Simulation time 19412381 ps
CPU time 1.15 seconds
Started Aug 03 05:51:26 PM PDT 24
Finished Aug 03 05:51:28 PM PDT 24
Peak memory 224024 kb
Host smart-887f274b-d362-4438-833c-4a098b8033d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865354328 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2865354328
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2436506487
Short name T389
Test name
Test status
Simulation time 153963677 ps
CPU time 1.27 seconds
Started Aug 03 05:51:31 PM PDT 24
Finished Aug 03 05:51:33 PM PDT 24
Peak memory 219960 kb
Host smart-6b663566-92e6-482c-8512-893210624fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436506487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2436506487
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.753163882
Short name T29
Test name
Test status
Simulation time 96066916 ps
CPU time 1.28 seconds
Started Aug 03 05:51:32 PM PDT 24
Finished Aug 03 05:51:34 PM PDT 24
Peak memory 218392 kb
Host smart-66039b33-3a98-4bcf-93e1-0b7b196c54e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753163882 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.753163882
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1447175734
Short name T217
Test name
Test status
Simulation time 32388543 ps
CPU time 0.99 seconds
Started Aug 03 05:51:31 PM PDT 24
Finished Aug 03 05:51:32 PM PDT 24
Peak memory 229368 kb
Host smart-f9091cdf-895b-4bd7-a1e8-1f1e8668a3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447175734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1447175734
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3352714240
Short name T576
Test name
Test status
Simulation time 130440617 ps
CPU time 2.92 seconds
Started Aug 03 05:51:32 PM PDT 24
Finished Aug 03 05:51:36 PM PDT 24
Peak memory 220080 kb
Host smart-fe7d061d-7627-432e-9e07-ab02a9ce6a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352714240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3352714240
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.3388976692
Short name T861
Test name
Test status
Simulation time 176414614 ps
CPU time 1.15 seconds
Started Aug 03 05:51:31 PM PDT 24
Finished Aug 03 05:51:32 PM PDT 24
Peak memory 218992 kb
Host smart-3938c657-fa0f-46e0-889c-d5d00d70d33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388976692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.3388976692
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.12299011
Short name T121
Test name
Test status
Simulation time 57826858 ps
CPU time 1.04 seconds
Started Aug 03 05:51:32 PM PDT 24
Finished Aug 03 05:51:33 PM PDT 24
Peak memory 219764 kb
Host smart-f1539bee-7c03-4b38-8a36-b6555b4c681a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12299011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.12299011
Directory /workspace/99.edn_err/latest
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