Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

7785

1

T4

8

T18

46

T19

138

all_values[1]

7785

1

T4

8

T18

46

T19

138

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7929

1

T4

5

T18

44

T19

130

auto[1]

7641

1

T4

11

T18

48

T19

146

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6156

1

T4

5

T18

45

T19

117

auto[1]

9414

1

T4

11

T18

47

T19

159

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9236

1

T4

8

T18

61

T19

170

auto[1]

6334

1

T4

8

T18

31

T19

106

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	0	12	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

1574

1

T18

7

T19

22

T126

14

all_values[0]

auto[0]

auto[0]

auto[1]

774

1

T4

1

T18

4

T19

12

all_values[0]

auto[0]

auto[1]

auto[0]

1509

1

T4

2

T18

11

T19

31

all_values[0]

auto[0]

auto[1]

auto[1]

768

1

T4

1

T18

5

T19

18

all_values[0]

auto[1]

auto[0]

auto[1]

1625

1

T4

2

T18

7

T19

27

all_values[0]

auto[1]

auto[1]

auto[1]

1535

1

T4

2

T18

12

T19

28

all_values[1]

auto[0]

auto[0]

auto[0]

1604

1

T4

1

T18

17

T19

36

all_values[1]

auto[0]

auto[0]

auto[1]

745

1

T4

1

T18

2

T19

9

all_values[1]

auto[0]

auto[1]

auto[0]

1469

1

T4

2

T18

10

T19

28

all_values[1]

auto[0]

auto[1]

auto[1]

793

1

T18

5

T19

14

T126

6

all_values[1]

auto[1]

auto[0]

auto[1]

1607

1

T18

7

T19

24

T126

9

all_values[1]

auto[1]

auto[1]

auto[1]

1567

1

T4

4

T18

5

T19

27

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal